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MICROCHIP PIC24HJXXXGPX06/X08/X10 Data Sheet High-Performance 16-Bit Microcontrollers Manual

1. Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 100 Lead Pitch e 0 50 BSC Overall Height A 1 20 Molded Package Thickness A2 0 95 1 00 1 05 Standoff 1 0 05 0 15 Foot Length L 0 45 0 60 0 75 Footprint L1 1 00 REF Foot Angle 0 3 5 7 Overall Width E 16 00 BSC Overall Length D 16 00 BSC Molded Package Width E1 14 00 BSC Molded Package Length D1 14 00 BSC Lead Thickness 0 09 0 20 Lead Width b 0 17 0 22 0 27 Mold Draft Angle Top 11 12 13 Mold Draft Angle Bottom 11 12 13 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Chamfers at corners are optional size may vary 3 Dimensions D1 and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 25 mm per side 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04 110B DS70175H page 274 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 100 Lead Plastic Thin Quad Flatpack PF 14x14x1 mm Body 2 00 mm TQFP Note For the most current package drawings please see the Microchip Pack
2. TABLE 4 20 ECAN1 REGISTER WHEN C1CTRL1 WIN 1 FOR PIC24HJXXXGP506 510 610 DEVICES ONLY CONTINUED File Name Addr Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 sue C1RXF11EID 046E EID lt 15 8 gt EID lt 7 0 gt C1RXF12SID 0470 SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXF12EID 0472 EID lt 15 8 gt EID lt 7 0 gt C1RXF13SID 0474 SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXF13EID 0476 EID lt 15 8 gt EID lt 7 0 gt C1RXF14SID 0478 SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXF14EID 047A EID lt 15 8 gt EID lt 7 0 gt C1RXF15SID 047C SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXF15EID 047E EID lt 15 8 gt EID lt 7 0 gt Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices 0LX 80X 90XdOXXXf Hv cDld 0 5 1 diuoouorN 6002 TABLE 4 21 2 REGISTER WHEN C2CTRL1 WIN 0 OR 1 FOR PIC24HJ
3. TABLE 4 20 ECAN1 REGISTER WHEN C1CTRL1 WIN 1 FOR PIC24HJXXXGP506 510 610 DEVICES ONLY Addr Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 S RT 0400 See definition when WIN x 041E C1BUFPNT1 0420 F3BP lt 3 0 gt F2BP lt 3 0 gt F1BP lt 3 0 gt FOBP lt 3 0 gt 0000 C1BUFPNT2 0422 F7BP lt 3 0 gt 6 lt 3 0 gt F5BP lt 3 0 gt F4BP lt 3 0 gt 0000 C1BUFPNT3 0424 F11BP lt 3 0 gt F10BP lt 3 0 gt F9BP lt 3 0 gt F8BP lt 3 0 gt 0000 C1BUFPNT4 0426 F15BP lt 3 0 gt F14BP lt 3 0 gt F13BP lt 3 0 gt F12BP lt 3 0 gt 0000 C1RXMOSID 0430 SID lt 10 3 gt SID lt 2 0 gt MIDE EID lt 17 16 gt C1RXMOEID 0432 EID lt 15 8 gt EID lt 7 0 gt C1RXM1SID 0434 SID lt 10 3 gt SID lt 2 0 gt EID lt 17 16 gt C1RXM1EID 0436 EID lt 15 8 gt EID lt 7 0 gt C1RXM2SID 0438 SID lt 10 3 gt SID lt 2 0 gt EID lt 17 16 gt C1RXM2EID 043A EID lt 15 8 gt EID lt 7 0 gt C1RXF0SID 0440 SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXFOEID 0442 EID lt 15 8 gt EID lt 7 0 gt C1RXF1SID 0444 SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXF1EID 0446 EID lt 15 8 gt EID lt 7 0 gt C1RXF2SID 0448 SID lt 10 3 gt SID lt 2 0 gt EXIDE EID lt 17 16 gt C1RXF2EID 044A
4. n 0 1 15 R W x R W x R W x R W x R W x R W x R W x R W x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 15 bit 8 R W x R W x R W x R W x R W x R W x R W x R W x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EIDO bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 0 EID lt 15 0 gt Extended Identifier bits 1 Message address bit EIDx must be 1 to match filter 0 Message address bit EIDx must be o to match filter 2009 Microchip Technology Inc DS70175H page 191 PIC24HJXXXGPX06 X08 X10 REGISTER 19 18 CiFMSKSEL1 ECAN MODULE FILTER 7 0 MASK SELECTION REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F7MSK lt 1 0 gt 6 5 lt 1 0 gt F5MSK lt 1 0 gt F4MSK lt 1 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F3MSK 1 0 2 5 lt 1 0 gt 1 5 lt 1 0 gt FOMSK lt 1 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 F7MSK lt 1 0 gt bit 13 12 6 5 lt 1 0 gt bit 11 10 F5MSK lt 1 0 gt bit 9 8 F4MSK lt 1 0 gt bit 7 6 F3MSK lt 1 0 gt bit 5 4 F2MSK lt 1 0 gt bit 3 2 F1MSK lt 1
5. Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt lt 85 for Industrial Pa Symbol Characteristic Min Typ Max Units Conditions Device Supply ADO1 AVDD Module Vpp Supply Greater of Lesser of V 0 3 VDD 0 3 or 3 0 or 3 6 ADO2 55 Module Vss Supply Vss 0 3 Vss 0 3 V Reference Inputs ADO5 VREFH Reference Voltage High AVSS 2 7 AVDD V See Note 1 AD05a 3 0 3 6 V VREFH AVDD VREFL AVSs 0 AD06 VREFL Reference Voltage Low AVss AVDD 2 7 V See Note 1 AD06a 0 0 V VREFH AVDD VREFL AVSS 0 AD07 VREF Absolute Reference 2 7 3 6 V VREF VREFH VREFL Voltage ADOS IREF Current Drain 250 550 uA operating see Note 1 10 uA ADC off see Note 1 ADO8a 1 Operating Current 7 0 9 0 mA 10 bit ADC mode See Note 2 2 7 3 2 mA 12 bit ADC mode See Note 2 Analog Input AD12 Input Voltage Range VINH VINL VREFH V This voltage reflects Sample and Hold Channels 0 1 2 3 CHO CH3 positive input AD13 VINL Input Voltage Range VINL VREFL 55 1 V This voltage reflects Sample and Hold Channels 0 1 2 and 3 CHO CH3 negative input AD17 Recommended Imped 200 Q 10 bit ADC ance of Analog Voltage 200 Q 12 bit ADC Source Note 1 These param
6. Rene 90 00 Software sets AD1CON SAMP to start sampling Sampling starts after discharge period TSAMP is described in Section 28 Analog to Digital Converter ADC without DMA DS70249 in the PIC24H Family Reference Manual 9 Software clears AD1CON to start conversion Sampling ends conversion sequence starts 5 Convert bit 9 Convert bit 8 7 Convert bit 0 One TAD for end of conversion FIGURE 24 20 ADC CONVERSION 10 BIT MODE TIMING CHARACTERISTICS CHPS lt 1 0 gt 01 SIMSAM o ASAM 1 SSRC lt 2 0 gt 111 lt 4 0 gt 00001 lt R Instruction Execution SetADON i es a 12 055 4 no 4 ADB 07 7o TeAMP _ AD55 lt X r lt x AD1IF POD a Se Se oss IE L L 1 1 Cn i amp qe n 1 1 1 i 1 P 1 1 1 14 1 1 1 DONE NE Viti SR k 1 1 12 1 1 1 1 Y T 127 T T T T 0 Software sets AD1CON ADON to start AD operation 2 Conv
7. REGISTER 7 5 IFS0 INTERRUPT FLAG STATUS REGISTER 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 T2IF OC2IF 2 1 INTOIF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 Unimplemented Read as 0 DMAIF DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred AD1IF ADC1 Conversion Complete Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred U1TXIF UART1 Transmitter Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred U1RXIF UART1 Receiver Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred SPMIF SPI1 Event Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred SPI1EIF SPI1 Fault Interrupt Flag Status bit 1 Interrupt request has occurred Interrupt request has not occurred Timer3 Interrupt Flag Sta
8. 207 ADxCON4 ADCx Control 4 208 ADxCSSH ADCx Input Scan Select High 211 ADxCSSL ADCx Input Scan Select Low 211 ADxPCFGH ADCx Port Configuration High 212 DS70175H page 284 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 ADxPCFGL ADCx Port Configuration Low 212 CiBUFPNT1 ECAN Filter 0 3 Buffer Pointer 188 CiBUFPNT2 ECAN Filter 4 7 Buffer Pointer 189 ECAN Filter 8 11 Buffer Pointer 189 CiBUFPNT4 ECAN Filter 12 15 Buffer Pointer 190 CiCFG1 ECAN Baud Rate Configuration 1 186 CiCFG2 ECAN Baud Rate Configuration 2 187 CiCTRL1 ECAN Control 1 178 2 ECAN Control 2 179 ECAN Transmit Receive Error Count 185 CiFCTRL ECAN FIFO Control ER CiFEN1 ECAN Acceptance Filter Enable 188 CiFIFO ECAN FIFO Status 182 CiFMSKSEL1 ECAN Filter 7 0 Mask Selection 192 193 ECAN Interrupt Enable 184 CilNTF ECAN Interrupt 183 CiRXFnEID ECAN Acceptance Filter n Extended Identi 191 CiRXFnSID Acceptance Filter Standard Identi fieras as uuu aereo t a ett 191 CiRXFUL1 ECAN R
9. R W 0 U 0 R W 0 U 0 U 0 U 0 U 0 U 0 TON TSIDL bit 15 bit 8 U 0 R W 0 R W 0 R W 0 U 0 R W 0 R W 0 U 0 TGATE TCKPS 1 0 TSYNC TCS bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 TON Timer1 On bit 1 Starts 16 bit Timer1 0 Stops 16 bit Timer1 bit 14 Unimplemented Read as 0 bit 13 TSIDL Stop in Idle Mode bit 1 Discontinue module operation when device enters Idle mode 0 Continue module operation in Idle mode bit 12 7 Unimplemented Read as 0 bit 6 TGATE Timer1 Gated Time Accumulation Enable bit When T1CS 1 This bit is ignored When T1CS 0 1 Gated time accumulation enabled 0 Gated time accumulation disabled bit 5 4 TCKPS 1 0 Timer1 Input Clock Prescale Select bits 11 1 256 10 1 64 01 1 8 00 1 1 bit 3 Unimplemented Read 0 bit 2 TSYNC Timer1 External Clock Input Synchronization Select bit When TCS 1 1 Synchronize external clock input 0 Do not synchronize external clock input When TCS o This bit is ignored bit 1 TCS Timer1 Clock Source Select bit 1 External clock from pin T1CK on the rising edge 0 Internal clock FcY bit 0 Unimplemented Read 0 DS70175H page 142 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 13 0 TIMER2 3
10. U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 m m DISSCK DISSDO MODE16 SMP CKE bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 SSEN CKP MSTEN SPRE lt 2 0 gt PPRE lt 1 0 gt 2 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 13 Unimplemented Read as 0 bit 12 DISSCK Disable SCKx pin bit SPI Master modes only 1 Internal SPI clock is disabled pin functions as 0 Internal SPI clock is enabled bit 11 DISSDO Disable SDOx pin bit 1 SDOx pin is not used by module pin functions as 0 SDOx pin is controlled by the module bit 10 MODE16 Word Byte Communication Select bit 1 Communication is word wide 16 bits Communication is byte wide 8 bits bit 9 SMP SPIx Data Input Sample Phase bit Master mode 1 Input data sampled at end of data output time 0 Input data sampled at middle of data output time Slave mode SMP must be cleared when SPIx is used in Slave mode bit 8 SPIx Clock Edge Select 1 Serial output data changes on transition from active clock state to Idle clock state see bit 6 0 7 Serial output data changes on transition from Idle clock state to active clock state see bit 6 bit 7 SSEN Slave Select Enable bit Slave mode 1 SSx pin used for Slave mode 0 SSx pin not used by module Pin controlled by por
11. R W 0 R W 0 R W 0 R W 0 U 0 U 0 U 0 U 0 T9MD T8MD T7MD T6MD bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 I2C2MD AD2MD bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 2 bit 1 bit 0 T9MD Timer9 Module Disable bit 1 Timer9 module is disabled 0 Timer9 module is enabled T8MD Timer8 Module Disable bit 1 Timer8 module is disabled 0 Timer8 module is enabled T7MD Timer7 Module Disable bit 1 Timer7 module is disabled 0 Timer7 module is enabled T6MD Timer6 Module Disable bit 1 Timer6 module is disabled 0 Timer6 module is enabled Unimplemented Read as 0 I2C2MD 12C2 Module Disable bit 1 12 2 module is disabled 0 12C2 module is enabled AD2MD AD2 Module Disable bit 1 AD2 module is disabled 0 AD2 module is enabled 2009 Microchip Technology Inc DS70175H page 137 PIC24HJXXXGPX06 X08 X10 NOTES DS70175H page 138 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 11 0 1 0 PORTS Note This data sheet summarizes the features of the PIC24HJXXXGPX06 X08 X10 fam ily of devices However it is not intended to be a comprehensive reference source To complement the information in this data sheet refer to the PIC24H Family Refer enc
12. Note 1 These parameters are characterized but not tested in manufacturing 2 Because the sample caps eventually loses charge clock rates below 10 kHz may affect linearity performance especially at elevated temperatures 3 tDpPUis the time required for the ADC module to stabilize when it is turned on AD1CON1 lt ADON gt 1 During this time the ADC result is indeterminate DS70175H page 268 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 25 0 PACKAGING INFORMATION 25 1 Package Marking Information 64 Lead TQFP 10x10x1 mm Example MICROCHIP MICROCHIP XXXXXXXXXX PIC24HJ XXXXXXXXXX 256GP706 XXXXXXXXXX I PT O YYWWNNN 0510017 100 Lead TQFP 12x12x1 mm Example MICROCHIP MICROCHIP XXXXXXXXXXXX PIC24HJ256 XXXXXXXXXXXX GP710 I PT YYWWNNN 0510017 O O 100 Lead TQFP 14x14x1mm 100 Lead TQFP 14x14x1mm MICROCHIP MICROCHIP XXXXXXXXXXXX PIC24HJ256 XXXXXXXXXXXX GP710 I PF YYWWNNN 0510017 Legend XX X Customer specific information Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code Pb free designator for Matte Sn This package is Pb free The Pb free designator can be found on the outer packaging for th
13. Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 Repeat Loop Counter Register XXXX SR 0042 DC IPL lt 2 0 gt RA N OV Z 0000 0044 PSV 0000 DISICNT 0052 Disable Interrupts Counter Register XXXX BSRAM 0750 IW_BSR IR BSR RL BSR 0000 SSRAM 0752 IW SSR IR SSR RL SSR 0000 Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices 0LX 80X 90XdOXXXf Hv CODld ABojouyoe dIYSOJISIN 6002 Le 10 5 TABLE 4 2 CHANGE NOTIFICATION REGISTER PIC24HJXXXGPX10 DEVICES NE Bitts Bitt4 Bit13 12 Bit Bitio Bito Bite Bits Bit2 si Bito pAs CNEN1 0060 CN15IE CN14IE CN12IE CN11IE 10 CN9IE CNBIE CNTIE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CNOIE 0000 CNEN2 0062 CN23IE CN22IE CN21IE 2 CN19IE 18 CN17IE CN16IE 0000 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE C
14. 2009 Technology Inc DS70175H page 249 PIC24HJXXXGPX06 X08 X10 FIGURE 24 6 INPUT CAPTURE CAPx TIMING CHARACTERISTICS 110 IC1 14 1015 Note Refer to Figure 24 1 for load conditions TABLE 24 25 INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt lt 85 C for Industrial uon Symbol Characteristic Min Max Units Conditions IC10 TecL ICx Input Low Prescaler 0 5 Tcy 20 ns With Prescaler 10 ns IC11 TccH ICx Input High Time Prescaler 0 5 TcY 20 ns With Prescaler 10 ns IC15 TccP ICx Input Period 40 N ns N prescale value 1 4 16 Note 1 These parameters are characterized but not tested in manufacturing FIGURE 24 7 OUTPUT COMPARE MODULE OCx TIMING CHARACTERISTICS OCx Output Compare 6 PWM Mode OC11 OC10 e Note Refer to Figure 24 1 for load conditions TABLE 24 26 OUTPUT COMPARE MODULE TIMING REQUIREMENTS Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 C for Industrial Symbol Characteristic Min Typ Max Units Conditions 10 TccF OCx Output Fall Time n
15. 0000 AD2CSSL 0370 5515 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 554 CSS3 CSS2 CSS1 CSSO 0000 AD2CON4 0372 DMABL lt 2 0 gt 0000 Reserved 0374 0000 037E Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices 0LX 80X 90XdOXXXf Hv CODld ABojouyoe diuooJ9 IN 6002 6 0 5 TABLE 4 17 REGISTER File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 AA DMAOCON 0380 CHEN SIZE DIR HALF NULLW AMODE lt 1 0 gt MODE lt 1 0 gt 0000 DMAOREQ 0382 FORCE IRQSEL lt 6 0 gt 0000 DMAOSTA 0384 STA lt 15 0 gt 0000 DMAOSTB 0386 5 lt 15 0 gt 0000 DMAOPAD 0388 PAD lt 15 0 gt 0000 DMAOCNT 038A CNT lt 9 0 gt 0000 DMA1CON 038 CHEN SIZE DIR HALF NULLW AMODE lt 1 0 gt MO
16. f f 1 1 N Z COM WREG WREG f 1 1 2 Wd Ws 1 1 NZ 18 cP cP Compare f with WREG 1 1 C DC N OV Z 1165 Compare Wb with 5 1 1 C DC N OV Z Wb Ws Compare Wb with Ws Wb Ws 1 1 C DC N OV Z 19 CPO CPO Compare f with 0x0000 1 1 C DC N OV Z CPO Ws Compare Ws with 0x0000 1 1 C DC N OV Z 20 CPB CPB Compare f with WREG with Borrow 1 1 C DC N OV Z CPB Wb 1it5 Compare Wb with lit5 with Borrow 1 1 C DC N OV Z CPB Wb Ws Compare Wb with Ws with Borrow 1 1 C DC N OV Z Wb Ws 21 CPSEQ CPSEQ Wb Wn Compare Wb with Wn skip if 1 1 None 2 or 3 22 CPSGT CPSGT Wb Wn Compare Wb with Wn skip if gt 1 1 2 or 3 23 CPSLT CPSLT Wb Wn Compare Wb with Wn skip if lt 1 1 None 2 or 3 24 CPSNE CPSNE Wb Compare Wb with Wn skip if 1 1 2 or 3 25 DAW DAW Wn Wn decimal adjust Wn 1 1 26 DEC DEC f f f 1 1 1 C DC N OV Z DEC WREG WREG f 1 1 1 C DC N OV Z DEC Ws Wd Wd Ws 1 1 1 C DC N OV Z 27 DEC2 DEC2 f f 2 1 1 C DC N OV Z DEC2 f WREG WREG f 2 1 1 C DC N OV Z DEC2 Wd Ws 2 1 1 C DC N OV Z 28 DISI DISI 1it14 Disable Interrupts for k instruction cycles 1 1 None 29 DIV DIV S Wm Wn Signed 16 16 bit Integer Divide 1 18 N Z C OV DIV SD Wm Wn Signed 32 16 bit Integer Divide 1 18 N Z C OV DIV U Wm Wn Unsigned 16 16 bit Integer Divide 1 18 N Z C OV DIV UD Wm Wn Unsigned 32 16 bit Integer Divide 1 18 N Z C OV 30 EXCH EXCH Wns
17. bit 15 bit 14 bit 13 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TRAPR Trap Reset Flag bit 1 A Trap Conflict Reset has occurred 0 A Trap Conflict Reset has not occurred IOPUWR Illegal Opcode or Uninitialized W Access Reset Flag bit 1 An illegal opcode detection an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 An illegal opcode or uninitialized W Reset has not occurred Unimplemented Read as 0 VREGS Voltage Regulator Standby During Sleep bit 1 Voltage regulator is active during Sleep Voltage regulator goes into Standby mode during Sleep EXTR External Reset MCLR Pin bit 1 A Master Clear pin Reset has occurred 0 A Master Clear pin Reset has not occurred SWR Software Reset Instruction Flag bit 1 RESET instruction has been executed 0 A RESET instruction has not been executed SWDTEN Software Enable Disable of WDT bit 2 1 WDT is enabled WDT is disabled WDTO Watchdog Timer Time out Flag bit 1 WDT time out has occurred WDT time out has not occurred SLEEP Wake up from Sleep Flag bit 1 Device has been in Sleep mode Device has not been in Sleep mode IDLE Wake up from Idle Flag bit 1 Device was in Idle mode 0 Device was not in Idle mode BOR Brown out Reset Flag bit 1 A Brown out Reset has occurred 0 A Brown out Reset has not occurred POR P
18. 2009 Microchip Technology Inc DS70175H page 175 PIC24HJXXXGPX06 X08 X10 FIGURE 19 1 ECAN MODULE BLOCK DIAGRAM RXF15 Filter RXF 14 Filter RXF 13 Filter RXF 12 Filter DMA Controller RXF 11 Filter RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX RX Buffer Control Register RXF7 Filter TRB6 TX RX Buffer Control Register RXF6 Filter TRB5 TX RX Buffer Control Register RXF65 Filter TRB4 TX RX Buffer Control Register RXF4 Filter TRB3 TX RX Buffer Control Register Filter TRB2 TX RX Buffer Control Register RXF2 Filter RXM2 Mask TRB1 TX RX Buffer Control Register RXF 1 Filter 9 RXM1 Mask TRBO Buffer Control Register RXFO Filter RXMO Mask Transmit Byte Message Assembly Sequencer Buffer Control mM Configuration CPU z Bus Logic CAN Protocol Engine o Interrupts ciTX CIRX Note 1 i 1 or 2 refers to a particular ECAN module ECAN1 ECAN2 DS70175H page 176 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 19 3 Modes of Operation The CAN module can operate in one of several operation modes selected by the user These modes include Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Listen All Messages Mode Loopback Mode Modes are requested by setting
19. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bito OxF80000 FBS RBS lt 1 0 gt BSS lt 2 0 gt BWRP 0 80002 FSS RSS lt 1 0 gt SSS lt 2 0 gt SWRP OxF80004 FGS GSS lt 1 0 gt GWRP OxF80006 FOSCSEL IESO Reserved 5 lt 2 0 gt 0 80008 FOSC FCKSM lt 1 0 gt OSCIOFNC POSCMD 1 0 OxF8000A FWDT FWDTEN WINDIS WDTPRE WDTPOST lt 3 0 gt OxF8000C FPOR FPWRT 2 0 OxF8000E FICD Reserved JTAGEN ICS lt 1 0 gt 0 80010 FUIDO User Unit ID Byte 0 OxF80012 FUID1 User Unit ID Byte 1 OxF80014 FUID2 User Unit ID Byte 2 0 80016 FUID3 User Unit ID Byte 3 Note 1 When read these bits will appear as 1 When you write to these bits set these bits to 1 2 When read this bit returns the current programmed value 2009 Microchip Technology Inc DS70175H page 213 PIC24HJXXXGPX06 X08 X10 TABLE 21 2 PIC24HJXXXGPX06 X08 X10 CONFIGURATION BITS DESCRIPTION Bit Field Register Description BWRP FBS Boot Segment Program Flash Write Protection 1 Boot segment may be written 0 Boot segment is write protected BSS lt 2 0 gt FBS Boot Segment Program Flash Code Protection Size X11 No Boot program Flash segment Boot space is 1K IW less VS 110 Standard security boot program Flash segment starts at End of VS ends at 0x0007FE 010 High security boot program Flash segment starts at End of VS ends at 0x0007
20. 2 E Interrupt Vector 116 0 0000 Interrupt Vector 117 0x0000FE 8 Reserved 0x000100 Reserved 0x000102 5 Reserved Oscillator Trap Vector S Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 0x000114 Interrupt Vector 1 Alternate Interrupt Vector Table AIVT Interrupt Vector 52 0x00017C Interrupt Vector 53 0x00017E Interrupt Vector 54 0x000180 Interrupt Vector 116 Interrupt Vector 117 0x0001FE Y Start of Code 0x000200 Note 1 See Table 7 1 for the list of implemented interrupt vectors DS70175H page 68 2009 Technology Inc PIC24HJXXXGPX06 X08 X10 TABLE 7 1 INTERRUPT VECTORS Vector Interrupt Number Request IRQ IVT Address AIVT Address Interrupt Source Number 8 0 0 000014 0 000114 INTO External Interrupt 0 9 1 0x000016 0x000116 IC1 Input Compare 1 10 2 0x000018 0x000118 OC1 Output Compare 1 11 3 0x00001A 0x00011A T1 Timer1 12 4 0x00001C 0x00011C Channel 0 13 5 0x00001E 0x00011E IC2 Input Capture 2 14 6 0x000020 0x000120 OC2 Output Compare 2 15 7 0x000022 0x000122 T2 Timer2 16 8 0x000024 0x000124 T3 Timer3 17 9 0x000026 0x0001
21. Swap Wns with Wnd 1 1 None 31 FBCL FBCL Ws Wnd Find Bit Change from Left MSb Side 1 1 32 FF1L FF1L Ws Wnd Find First One from Left MSb Side 1 1 33 FF1R FF1R Ws Wnd Find First One from Right LSb Side 1 1 34 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 2009 Microchip Technology Inc DS70175H page 225 PIC24HJXXXGPX06 X08 X10 TABLE 22 2 INSTRUCTION SET OVERVIEW CONTINUED cn eet Assembly Syntax Description o dd riii 35 NC NC f f f 1 1 1 C DC N OV Z NC WREG f 1 1 1 C DC N OV Z NC Ws Wd Wd Ws 1 1 1 C DC N OV Z 36 NC2 NC2 f f f 2 1 1 C DC N OV Z NC2 f WREG WREG f 2 1 1 C DC N OV Z NC2 Wd Ws 2 1 1 C DC N OV Z 37 OR OR f f IOR WREG 1 1 N Z OR WREG WREG f IOR WREG 1 1 N Z OR 11610 Wd 10 IOR Wd 1 1 N Z OR Wd Wb Ws 1 1 N Z OR Wb lit5 Wd Wd Wb IOR lit5 1 1 N Z 38 LNK LNK 11014 Link Frame Pointer 1 1 None 39 LSR LSR f Logical Right Shift f 1 1 C N OV Z LSR WREG WREG Logical Right Shift f 1 1 C N OV Z LSR Ws Wd Wd Logical Right Shift Ws 1 1 C N OV Z LSR Wb Wns Wnd Wnd Logical Right Shift Wb by Wns 1 1 N Z LSR Wb 1it5 Wnd Wnd Logical Right Shift Wb by lit5 1 1 N Z 40 MOV MOV Move f to Wn 1 1 None MOV Mo
22. 02DA RE6 5 4 2 RE1 RE0 LATE 02DC LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATEO Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices Note 1 The actual set of I O port pins varies from one device to another Please refer to the corresponding pinout diagrams TABLE 4 29 PORTF REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 All Resets TRISF 02DE TRISF13 TRISF12 TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISFO 31FF PORTF 02E0 RF13 RF12 c RF8 RF6 RF5 RF4 RF3 RF2 RF1 RF0 LATF 02E2 LATF13 LATF12 LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 06DE ODCF13 ODCF12 ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices Note 1 The actual set of I O port pins varies from one device to another Please refer to the corresponding pinout diagrams TABLE 4 30 PORTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M RR TRISG 02 4 TRISG
23. FIGURE 20 1 ADCx MODULE BLOCK DIAGRAM E m n md TG I S HO CHANNEL gt CHOSB 4 0 j lt 1 CHOSA lt 4 0 gt 4 E EE T I CHO CSCNA Lol SS Se zug VREF DH lt 9 E CH ONB _ _ _ _ _ _ 7 _ 1 Soe fa m 222 Vrer AVDD Avss Y E N mx AN3 X S H1 lt e I N S 1235 1235 2 4 cH1 2 ANG AN9 bestas VREF lt VREFH VREFL 123 123 L 4 Ld ADC y ADC1BUF0 AN1D 5 2 aeo m Lg E a 1235 1235 4 11 04 VREF x CH123NA CH123NB Ls ANOR pce c VREF X CH123NA CH123NB ANR AN5 S H3 e 1235 1235 gt CH3 es Alternate Input Selection VREF VREF inputs can be multiplex 2 Channels 1 2 and 3 not applicabl ed with other analog inputs e for the 12 bit mode of operation 3 For 64 pin devices y 17 for 100 pin devices y 31 for ADC2 y 15 DS70175H page 202 2009 Mic
24. IRQSEL lt 6 0 gt 0000 DMASSTA 03 0 5 lt 15 0 gt 0000 DMASSTB 03C2 STB lt 15 0 gt 0000 Legend unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices 0LX 80X 90XdOXXXf Hv cCDld eBed Hs 107sd 1 diuoouorN 6002 TABLE 4 17 DMA REGISTER MAP CONTINUED File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 oe DMASPAD 03C4 PAD lt 15 0 gt 0000 DMASCNT 03C6 CNT lt 9 0 gt 0000 DMA6CON 03C8 CHEN SIZE DIR HALF NULLW AMODE lt 1 0 gt MODE lt 1 0 gt 0000 DMA6REQ FORCE IRQSEL lt 6 0 gt 0000 DMA6STA 03 STA lt 15 0 gt 0000 DMA6STB 03CE STB lt 15 0 gt 0000 DMA6PAD 0300 PAD lt 15 0 gt 0000 DMA6CNT 0302 CNT lt 9 0 gt 0000 DMA7CON 0304 CHEN SIZE DIR HALF NULLW AMODE lt 1 0 gt MODE lt 1 0 gt 0000 DMA7REQ 0306 FORCE IRQSEL lt 6 0 gt 0000 DMA7STA 0308 5 lt 15 0 gt 0000 DMA7STB 03DA STB lt 15 0 gt 0000 DMA7PAD 03DC PAD lt 15 0 gt 0000 DMA7CNT 03DE CNT lt 9 0 gt 0000 DMACSO 03E0 PWCOL7 PW
25. y 16 16 bit ALU To Peripheral Modules DS70175H page 20 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 FIGURE 3 2 PIC24HJXXXGPX06 X08 X10 PROGRAMMER S MODEL D15 DO WO WREG E PUSH S Shadow W1 wo Shadow Legend W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer J SPLIM Stack Pointer Limit Register Working Registers PC22 PC0 0 Program Counter 7 0 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 CORCON Core Configuration Register DC FIPL2 IPL1 IPLO N Z STATUS Register lt SRH gt lt SRL gt 3 3 CPU Control Registers 2009 Microchip Technology Inc DS70175H page 21 PIC24HJXXXGPX06 X08 X10 REGISTER 3 1 SR CPU STATUS REGISTER U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 DC bit 15 R W 0 1 R W 0 2 R W 0 2 R 0 R W 0 R W 0 R W 0 R W 0 IPL lt 2 0 gt 2 RA N 2 bit 7 Legend Set only bit 1 Bit is set C Clear only bit R Readable bit U Unimplemented bit read as 0 W Writable bit n V
26. 2 422 2 261 I2Cx Bus Data Requirements Master 258 I2Cx Bus Data Requirements Slave Mode Output Compare Requirements PLE COCK ete ene dn edt Reset Watchdog Timer Oscillator Start up Timer Pow er up Timer and Brown out Reset Requirements 247 Simple OC PWM Mode Requirements 251 SPIx Master Mode 0 Requirements 252 SPIx Master Mode 1 Requirements 253 SPIx Slave Mode CKE 0 Requirements SPIx Slave Mode CKE 1 Requirements Timer1 External Clock Requirements Timer2 External Clock Requirements Timer3 External Clock Requirements U UART Module UART1 Register 36 UART2 Register 37 V Voltage Regulator 218 Watchdog Timer 0 213 219 Programming Considerations 219 WWW Address recreo tne ns 287 WWW On Line 10 DS70175H page 286 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www microchip com This web site is used as a means to make files and in
27. Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 C for Industrial beg Symbol Characteristic Min Typ Max Units Conditions SY10 MCLR Pulse Width low 2 us 40 C to 85 SY11 TPWRT Timer Period 2 ms 40 C to 85 C 4 User programmable 8 16 32 64 128 SY12 TPOR Power on Reset Delay 3 10 30 us 40 to 85 C SY13 2 High Impedance from 0 68 0 72 1 2 us MCLR Low Watchdog Timer Reset SY20 1 Watchdog Timer Time out See Section 21 4 Watchdog Period Timer WDT and LPRC specification F21 Table 24 19 SY30 TosT Oscillator Start up Timer 1024 Tosc Tosc OSC1 period Period SY35 Fail Safe Clock Monitor 500 900 us 40 85 Delay Note 1 These parameters are characterized but not tested in manufacturing 2 Data in column is at 3 3V 25 unless otherwise stated 2009 Microchip Technology Inc DS70175H page 247 PIC24HJXXXGPX06 X08 X10 FIGURE 24 5 TIMER 2 3 4 5 6 7 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS gt TMRx Note Refer to Figure 24 1 for load conditions TABLE 24 22 TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions 3 0V to 3 6V unless otherwise stated Oper
28. TSIDL lt 1 0 gt T32 5 0000 T5CON 0120 TON TSIDL TGATE lt 1 0 gt 5 0000 TMR6 0122 Timer6 Register TMR7HLD 0124 Timer7 Holding Register for 32 bit operations only 0126 Register PR6 0128 Period Register 6 FFFF PR7 012A Period Register 7 FFFF 6 012 TSIDL TGATE lt 1 0 gt T32 5 0000 012 TSIDL lt 1 0 gt TCS 0000 TMR8 0130 Timer8 Register XXXX TMR9HLD 0132 Timer9 Holding Register for 32 bit operations only XXXX TMR9 0134 Timer9 Register XXXX PR8 0136 Period Register 8 FFFF PR9 0138 Period Register 9 FFFF T8CON 013A TON TSIDL TGATE TCKPS lt 1 0 gt T32 TCS 0000 T9CON 013C TON TSIDL TGATE lt 1 0 gt 5 0000 Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices 0LX 80X 90XdOXXXf Hv cDld ve eBed Hs 107sa 1 diuoouorN 6002 TABLE 4 7 CAPTURE REGISTER SFR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit
29. 31 m 0 1 7 R W x R W x R W x R W x R W x R W x R W x R W x TRBnDm7 TRBnDm6 TRBnDm5 TRBnDm4 TRBnDm3 TRBnDm2 TRBnDm1 TRBnDmO bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 TRnDm lt 7 0 gt Data Field Buffer n Byte m bits Note 1 The Most Significant Byte contains byte 1 of the buffer 2009 Microchip Technology Inc DS70175H page 199 PIC24HJXXXGPX06 X08 X10 REGISTER 19 31 CiTRBnSTAT ECAN MODULE RECEIVE BUFFER n STATUS n 0 1 31 U 0 U 0 U 0 R W x R W x R W x R W x R W x FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHITO bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bitis unknown bit 15 13 Unimplemented Read as 0 bit 12 8 FILHIT 4 0 Filter Hit Code bits only written by module for receive buffers unused for transmit buffers Encodes number of filter that resulted in writing this buffer bit 7 0 Unimplemented Read as 0 DS70175H page 200 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 20 0 10 BIT 12 BIT ANALOG TO DIGITAL CONVERTER AD
30. Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 bit 11 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented Read as 0 LSTCH lt 3 0 gt Last DMA Channel Active bits 1111 No DMA transfer has occurred since system Reset 1110 1000 Reserved 0111 Last data transfer was by DMA Channel 7 0110 Last data transfer was by DMA Channel 6 0101 Last data transfer was by DMA Channel 5 0100 Last data transfer was by DMA Channel 4 0011 Last data transfer was by DMA Channel 0010 Last data transfer was by DMA Channel 2 0001 Last data transfer was by DMA Channel 1 0000 Last data transfer was by Channel 0 PPST7 Channel 7 Ping Pong Mode Status Flag bit 1 DMATSTB register selected 0 DMATSTA register selected PPST6 Channel 6 Ping Pong Mode Status Flag bit 1 DMAGSTB register selected 0 DMAGSTA register selected PPST5 Channel 5 Ping Pong Mode Status Flag bit 1 DMASSTB register selected 0 DMASSTA register selected PPST4 Channel 4 Ping Pong Mode Status Flag bit 1 DMA4STB register selected DMA4STA register selected PPST3 Channel 3 Ping Pong Mode Status Flag bit 1 DMASSTB register selected 0 DMASSTA register selected PPST2 Channel 2 Ping Pong Mode Status Flag bit 1 DMA2STB register selected DMA2STA register selected PPST1 Channel 1 Ping Pong Mode Status Flag bit 1 DMA1STB register selected 0 DMA1STA register
31. n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 ADRC ADC Conversion Clock Source bit 1 ADC internal RC clock 0 Clock derived from system clock bit 14 13 bit 12 8 Unimplemented Read as 0 SAMC lt 4 0 gt Auto Sample Time bits 11111 31 TAD 00001 1 TAD 00000 0 TAD ADCS lt 7 0 gt Analog to Digital Conversion Clock Select bits 2 11111111 Reserved bit 7 0 01000000 Reserved 00111111 TCY ADCS lt 7 0 gt 1 64 TCY TAD 00000010 ADCS lt 7 0 gt 1 TCY TAD 00000001 ADCS lt 7 0 gt 1 2 TCY TAD 00000000 TCY ADCS lt 7 0 gt 1 1 TCY TAD Note 1 This bit only used if ADXCON1 SSRC 1 2 This bit is not used if ADXCON3 lt ADRC gt 1 2009 Microchip Technology Inc DS70175H page 207 PIC24HJXXXGPX06 X08 X10 REGISTER 20 4 ADxCON4 ADCx CONTROL REGISTER 4 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 DMABL lt 2 0 gt bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 15 3 Unimplemented Read as 0 bit 2 0 DMABL lt 2 0 gt Selects Number of DMA Buffer Locations per Analog Input bits 111 Allocates 128 words of buffer
32. Bit is set 0 Bit is cleared x Bit is unknown bit 15 0 RXFUL lt 15 0 gt Receive Buffer n Full bits 1 Buffer is full set by module 0 Buffer is empty clear by application software REGISTER 19 23 CiRXFUL2 ECAN MODULE RECEIVE BUFFER FULL REGISTER 2 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 bit 15 bit 8 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 bit 7 bit 0 Legend C Clear only bit Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 0 RXFUL lt 31 16 gt Receive Buffer n Full bits 1 Buffer is full set by module 0 Buffer is empty clear by application software DS70175H page 195 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 19 24 CiRXOVF1 ECAN MODULE RECEIVE BUFFER OVERFLOW REGISTER 1 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 RXOVF 15 RXOVF 14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF 1 RXOVFO bit 7 bit 0 Legend C Clear only bit Readable bi
33. DMAXCNT E ete DMAXPAD ae rete p DMAxREQ e DMAXSTA s NE M M dea ipea diede DMAXS TB tii itam morte omae E ECAN Module CiFMSKSEL2 register 193 ECAN 1 Register C1CTRL1 WIN 0 or 1 41 ECAN 1 Register Map C1CTRL1 WIN 0 ECAN 1 Register Map C1CTRL1 WIN 1 2 Register Map C2CTRL1 WIN 0 or 1 44 2 Register Map C2CTRL1 WIN 0 44 ECAN2 Register Map C2CTRL1 WIN 1 45 Frame Types Modes of 177 OVGIVIOW Ret yanapi dd 175 ECAN Registers Filter 15 8 Mask Selection Register CIFMSKSEL2 193 Electrical Characteristics 233 AG s insit eerie ML md cime 242 Enhanced CAN Module 175 Equations Device Operating Frequency FOSC Calculation m XT with PLL Mode Example a ama ena rep rs Flash Program Memory 57 Control Registers ea Programming Algorithm 60 RTSP Operati n ettet eerte 58 Table Instructions
34. Pins with OSC1 or SOSCI Vss 02Vp V DI18 Pins with Vss 0 3VpDD V SMbus disabled DI19 Pins with Vss 0 22 V SMbus enabled VIH Input High Voltage 0120 Pins Not 5V Tolerant 8 Pins 5V Tolerant 0 8 5 5 V Pins Not 5V Tolerant 4 2 VDD V vop 3 3V Pins 5V Tolerant 4 2 5 5 V Vpp 3 3V DI26 Pins with OSC1 or SOSCI 0 7 VoD VDD V 0128 Pins with 2 0 7VDD 5 5 V SMbus disabled 0129 Pins with 0 8 0 5 5 V SMbus enabled ICNPU CNx Pull up Current DI30 50 250 400 uA VDD 3 3V VSS Input Leakage Current 23 0150 Pins 2 VSS lt VPIN lt VDD Pin at high impedance DI51 Pins Not 5V 2 Vss lt lt VDD Pin at high impedance 0151 Pins Not 5V Tolerant 2 Shared with external reference pins DI51b Pins Not 5V 3 5 uA Vss lt VPIN lt VDD Pin at high impedance 0151 Pins Not 5V Tolerant 4 8 uA Analog pins shared with external reference pins DI55 MCLR 2 uA VSS lt VPIN lt VDD DI56 OSC1 2 5 lt VPIN lt VDD HS modes Note 1 Data in Typ column is at 3 3V 25 C unless otherwise stated 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified
35. Read Prog lt 23 16 gt to Wd lt 7 0 gt 1 2 None 2009 Microchip Technology Inc DS70175H page 227 PIC24HJXXXGPX06 X08 X10 TABLE 22 2 INSTRUCTION SET OVERVIEW CONTINUED ieir Assembly Syntax Description a is 66 TBLRDL TBLRDL Read Prog lt 15 0 gt to Wd 1 2 None 67 TBLWTH TBLWTH Write Ws lt 7 0 gt to lt 23 16 gt 1 2 None 68 TBLWTL TBLWTL Write Ws to Prog lt 15 0 gt 4 2 None 69 ULNK ULNK Unlink Frame Pointer 1 1 None 70 XOR XOR f f XOR WREG 1 1 N Z WREG WREG f XOR WREG 1 1 N Z 11610 Wd 10 XOR Wd 1 1 N Z Wb Ws Wd Wd Wb XOR Ws 1 1 N Z XOR Wb 1it5 Wd Wd Wb XOR lit5 1 1 2 71 ZE ZE Wnd Zero extend Ws 1 1 C ZN DS70175H page 228 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 23 0 DEVELOPMENT SUPPORT The PIC microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB IDE Software Assemblers Compilers Linkers MPASM Assembler MPLAB C18 and MPLAB C30 C Compilers MPLINK Object Linker MPLIB Object Librarian MPLAB ASM30 Assembler Linker Library Simulators MPLAB SIM Software Simulator Emulators MPLAB ICE 2000 In Circuit Emulator MPLAB REAL ICE In Circuit Emulator
36. lt lt gt z 222266 x O lt lt TECON A Ss 5 gt 20 22 6 SORA 5 5 gt FF x 0 59 BC aq 2 22 2009 Microchip Technology Inc DS70175H page 5 PIC24HJXXXGPX06 X08 X10 Pin Diagrams Continued 64 Pin TQFP Pins are up to 5V tolerant ot Pc 86566 te ass 65885 ON gt X 2 x ororena oN 6 oQoooo aooQdoooooo O LO LO LO LO LO LO 10 10 st RG15 1 48 PGEC2 SOSCO T1CK CN0 RC14 AN16 T2CK T7CK RC1 2 47 PGED2 SOSCI T4CK CN1 RC13 AN17 T3CK T6CK RC2 3 46mm OC1 RDO SCK2 CN8 RG6 wmm 4 45 mm C4 INT4 RD11 SDI2 CN9 RG7 5 44 mm C3 INT3 RD10 SDO2 CN10 RG8 6 43 sm IC2 U1CTS INT2 RD9 MCLR mmm 7 42mm IC1 INT1 RD8 SS2 CN11 RG9 8 vss Vss 9 PIC24HJ64GP506 405 OSC2 CLKO RC15 VDD 10 PIC24HJ128GP506 39 5 OSC1 CLKIN RC12 AN5 IC8 CN7 RB5 11 38 vpp AN4 IC7 CN6 RB4 12 37 SCL1 RG2 AN3 CN5 RB3 13 36mm SDA1 RG3 AN2 SS1 CN4 RB2 14 35 UTRTS SCK1 INTO RF6 PGEC3 AN1 VREF CN3 RB1 15 34 U1RX SDM RF2 PGED3 ANO VREF CN2 RBO 16 33m U1TX SDO1 RF3 OO O st LO OQ CO ON geen 8 lt lt 5 2 222266 lt lt 5550464 lt lt o 22 R 88 PD
37. 00 EC External Clock mode FWDTEN FWDT Watchdog Timer Enable bit 1 Watchdog Timer always enabled LPRC oscillator cannot be disabled Clearing the SWDTEN bit in the RCON register will have no effect 0 Watchdog Timer enabled disabled by user software LPRC can be disabled by clearing the SWDTEN bit in the RCON register WINDIS FWDT Watchdog Timer Window Enable bit 1 Watchdog Timer in Non Window mode 0 Watchdog Timer in Window mode WDTPRE FWDT Watchdog Timer Prescaler bit 1 1 128 0 1 32 WDTPOST FWDT Watchdog Timer Postscaler bits 1111 1 32 768 1110 1 16 384 0001 1 2 0000 1 1 DS70175H page 216 2009 Technology Inc PIC24HJXXXGPX06 X08 X10 TABLE 21 2 PIC24HJXXXGPX06 X08 X10 CONFIGURATION BITS DESCRIPTION CONTINUED Bit Field Register Description FPWRT 2 0 FPOR Power on Reset Timer Value Select bits 111 PWRT 128 ms 110 PWRT 64 ms 101 PWRT 32 ms 100 PWRT 16 ms 011 PWRT 8 ms 010 PWRT 4 001 PWRT 2 ms 000 PWRT Disabled FICD JTAG Enable bits 1 JTAG enabled 0 JTAG disabled ICS lt 1 0 gt FICD ICD Communication Channel Select bits 11 Communicate on PGEC1 and PGED1 10 Communicate on PGEC2 and PGED2 01 Communicate on PGEC3 and PGED3 00 Reserved 2009 Microchip Technology Inc DS70175H page 217 PIC24HJX
38. 3 6V AD24a EoFF Offset Error 2 3 LSb VINL AVSS OV AVpp 3 6V AD25a Monotonicity Guaranteed Dynamic Performance 12 bit Mode AD30a THD Total Harmonic Distortion 77 69 61 AD31a SINAD Signal to Noise and 59 63 64 dB Distortion AD32a SFDR Spurious Free Dynamic 63 72 74 dB Range AD33a FNYQ Input Signal Bandwidth 250 kHz AD34a ENOB Effective Number of Bits 10 95 11 1 bits 2009 Microchip Technology Inc DS70175H page 263 PIC24HJXXXGPX06 X08 X10 TABLE 24 37 ADC MODULE SPECIFICATIONS 10 BIT MODE Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt lt 85 C for Industrial jus Symbol Characteristic Min Typ Max Units Conditions ADC Accuracy 10 bit Mode Measurements with external VREF VREF AD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity 1 5 1 5 LSb VINL AVSS VREFL OV AVDD VREFH 3 6V AD22b DNL Differential Nonlinearity 2 1 1 LSb VINL AVSS VREFL OV AVDD VREFH 3 6V AD23b GERR Gain Error 1 3 6 LSb VINL AVSS VREFL AVDD VREFH 3 6V AD24b Offset Error 1 2 5 LSb VINL AVSS VREFL OV AVDD VREFH 3 6V AD25b Monotonicity Guaranteed ADC Accuracy 10 bit Measurements with inte
39. Any device Reset AWDT time out On wake up from Idle the clock is reapplied to the CPU and instruction execution begins immediately starting with the instruction following the PWRSAV instruction or the first instruction in the ISR 10 2 3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction is held off until entry into Sleep or Idle mode has completed The device then wakes up from Sleep or Idle mode 10 3 Doze Mode Generally changing clock speed and invoking of the power saving modes are the preferred strategies for reducing power consumption There cir cumstances however where this is not practical For example it may be necessary for an application to main tain uninterrupted synchronous communication even while it is doing nothing else Reducing system clock speed may introduce communication errors while using a power saving mode may stop communications completely Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code In this mode the system clock contin ues to operate from the same source and at the same speed Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced Synchronization between the two clock domains is maintained allowing the peripherals to access the SFRs while the CPU executes code at a slower ra
40. Interrupt Flag Code bits 1000101 1111111 Reserved 1000100 FIFO almost full interrupt 1000011 Receiver overflow interrupt 1000010 Wake up interrupt 1000001 Error interrupt 1000000 No interrupt 0010000 0111111 Reserved 0001111 RB15 buffer Interrupt 0001001 RB9 buffer interrupt 0001000 RB8 buffer interrupt 0000111 TRB buffer interrupt 0000110 TRB6 buffer interrupt 0000101 5 buffer interrupt 0000100 TRB4 buffer interrupt 0000011 TRB3 buffer interrupt 0000010 TRB2 buffer interrupt 0000001 TRB1 buffer interrupt 0000000 TRBO Buffer interrupt DS70175H page 180 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 19 4 CiFCTRL ECAN MODULE FIFO CONTROL REGISTER R W 0 R W 0 R W 0 U 0 U 0 U 0 U 0 U 0 DMABS lt 2 0 gt bit 15 bit 8 U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 5 lt 4 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 13 DMABS lt 2 0 gt DMA Buffer Size bits 111 Reserved 110 32 buffers RAM 101 24 buffers in DMA RAM 100 16 buffers in DMA RAM 011 12 buffers in DMA RAM 010 8 buffers in DUA RAM 001 6 buffers RAM 000 4 buffers in RAM bit 12 5 Unimplemented Read as 0 bit 4 0 FSA lt
41. MICROCHIP PIC24HJXXXGPX06 X08 X10 Data Sheet High Performance 16 Bit Microcontrollers 2009 Microchip Technology DS70175H Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted
42. PIC24HJXXXGPX06 X08 X10 11 2 Open Drain Configuration In addition to the PORT LAT and TRIS registers for data control some port pins can also be individually configured for either digital or open drain output This is controlled by the Open Drain Control register ODCx associated with each port Setting any of the bits con figures the corresponding pin to act as an open drain output The open drain feature allows the generation of outputs higher than VDD e g 5V on any desired digi tal only pins by using external pull up resistors The maximum open drain voltage allowed is the same as the maximum VIH specification See the Pin Diagrams for the available pins and their functionality 11 3 Configuring Analog Port Pins The use of the ADxPCFGH ADxPCFGL and TRIS registers control the operation of the Analog to Digital port pins The port pins that are desired as analog inputs must have their corresponding TRIS bit set input If the TRIS bit is cleared output the digital out put level VoH or VoL is converted Clearing any bit in the ADXPCFGH or ADxPCFGL reg ister configures the corresponding bit to be an analog pin This is also the Reset state of any pin that has an analog function associated with it Note In devices with two ADC modules if the corresponding bit either AD1PCFGH L and AD2PCFGH L is cleared the pin is configured as an analog input When read
43. Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 bit 13 bit 12 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented Read as 0 DMASIE DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 Interrupt request enabled Interrupt request not enabled Unimplemented Read as 0 C2IE ECAN2 Event Interrupt Enable bit 1 Interrupt request enabled Interrupt request not enabled C2RXIE ECAN2 Receive Data Ready Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled INTAIE External Interrupt 4 Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled INT3IE External Interrupt 3 Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled T9IE Timer9 Interrupt Enable bit 1 7 Interrupt request enabled 0 7 Interrupt request not enabled T8IE Timer8 Interrupt Enable bit 1 7 Interrupt request enabled 0 7 Interrupt request not enabled MI2C2IE 2 2 Master Events Interrupt Enable bit 1 7 Interrupt request enabled 0 Interrupt request not enabled SI2C2IE 2 2 Slave Events Interrupt Enable bit 1 7 Interrupt request enabled 0 7 Interrupt request not enabled Timer Interrupt Enable bit 1 7 Interrupt request enabled 0 7 Interrupt request not enabled 2009 Microchip
44. n Circuit Debugger MPLAB ICD 2 Device Programmers PICSTART Plus Development Programmer MPLAB PM3 Device Programmer PICkit 2 Development Programmer Low Cost Demonstration and Development Boards and Evaluation Kits 23 1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8 16 bit micro controller market The MPLAB IDE is a Windows operating system based application that contains single graphical interface to all debugging tools Simulator Programmer sold separately Emulator sold separately In Circuit Debugger sold separately A full featured editor with color coded context A multiple project manager Customizable data windows with direct edit of contents High level source code debugging Visual device initializer for easy register initialization Mouse over variable inspection Drag and drop variables from source to watch windows Extensive on line help Integration of select third party tools such as HI TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PIC MCU emulator and simulator tools automatically updates all project information Debug using Source files assembly or C Mixed assembly and C Machine code MPLAB IDE supports multipl
45. nal clock Other operational features include Device wake up from capture pin during CPU Sleep and Idle modes Interrupt on input capture event 4 word FIFO buffer for capture values Interrupt optionally generated after 1 2 3 or 4 buffer locations are filled Input capture can also be used to provide additional sources of external interrupts Note Only and 2 can trigger DMA data input at 2 pin transfer data transfers Capture timer value on every rising edge of required the FIFO buffer size must be set input at ICx pin to 1 ICI 1 0 00 FIGURE 14 1 INPUT CAPTURE BLOCK DIAGRAM From 16 bit Timers TMRy TMRz ICTMR E 0 ICXCON lt 7 gt Prescaler Edge Detection Logic FIFO Counter and 7 R W 1 4 16 Clock Synchronizer Logic Pin V lt 2 0 gt lt 2 0 gt 3 Mode Select 9 ICOV ICBNE lt 4 3 gt gt ICxBUF lt 1 0 gt Y Y Interrupt ICxCON Logic System Bus Y Set Flag ICxIF in IFSn Register Note An x in a signal register or bit name denotes the number of the capture channel 2009 Microchip Technology Inc DS70175H page 149 PIC24HJXXXGPX06 X08 X10 14 1 REGISTER 14 1 Input Capture Registers ICxCON INPUT
46. sise 57 Flexible Configuration 213 FSCM Delay for Crystal PLL Clock Sources 66 Device Resets sine 66 2009 Microchip Technology Inc DS70175H page 283 PIC24HJXXXGPX06 X08 X10 VO Parallel I O 5 Write Read 2 Operating Modes 2 161 agua 161 2 Module I2C1 Register 36 2 2 Register 36 In Circuit 220 In Circuit Emulation In Circuit Serial Programming ICSP 213 220 Input Capture Registers te ae Input Change Notification Module Instruction Addressing Modes gt File Register Instructions 20 2 Fundamental Modes Supported MCU Instructions Move and Accumulator Instructions ss Other Instructions Instruction Set Overview Summary Instruction Based Power Saving Modes 131 tt tte 132 Sleop s eint 131 Internal RC Oscillator Useiwith WDT ct a d a etes 219 Internet Address erret tnn irn entre reta 287 INTGCON2 3 itte ti i Eire RR 71 INTTREG peace e eei ete 71 IPOX en tie aU Interrupt Setup Procedures 110 Initialization 110 Interrupt 1
47. 2 Update the program data in RAM with the desired new data 3 Erase the page see Example 5 1 a Set the NVMOP bits NVMCON lt 3 0 gt to 0010 to configure for block erase Set the ERASE lt 6 gt and WREN NVMCON lt 14 gt bits b Write the starting address of the page to be erased into the TBLPAG and W registers c Perform a dummy table write operation TBLWTL to any address within the page that needs to be erased d Write 0x55 to NVMKEY e Write OxAA to NVMKEY f Set the WR bit NVMCON lt 15 gt The erase cycle begins and the CPU stalls for the dura tion of the erase cycle When the erase is done the WR bit is cleared automatically and set the WREN bit b Write 0x55 to NVMKEY c Write OxAA to NVMKEY d Set the WR bit The programming cycle begins and the CPU stalls for the duration of the write cycle When the write to Flash mem ory is done the WR bit is cleared automatically 6 Repeat steps 4 and 5 using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG until all 512 instructions are written back to Flash memory For protection against accidental operations the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed After the programming command has been executed the user must wait for the programming time until programming is complete The two instructions following the start of the
48. 4 54 o aS P DONE i RS NT ET EN EP S ADIIF NE NINE EN ERN TES OO Software sets AD1CON SAMP to start sampling Sampling ends conversion sequence starts Sampling starts after discharge period TSAMP is described in Convert bit 11 Section 28 Analog to Digital Converter ADC without DMA DS70249 in the PIC24H Family Reference Manual 8 Convert bit 10 Please see the Microchip web site www microchip com Convert bit 1 for the latest PIC24H Family Reference Manual sections Convert bit 0 Software clears AD1CON SAMP to start conversion One TAD for end of conversion 2009 Microchip Technology Inc DS70175H page 265 PIC24HJXXXGPX06 X08 X10 TABLE 24 38 ADC CONVERSION 12 BIT MODE TIMING REQUIREMENTS Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 for Industrial ii Symbol Characteristic Min Typ Max Units Conditions Clock Parameters AD50 ADC Clock Period 117 6 ns AD51 ADC Internal RC Oscillator 250 ns Period Conversion Rate AD55 tCONV Conversion Time 14 TAD ns AD56 Throughput Rate 500 ksps AD57 Sample Time 3 TAD Timing Parameters AD60 tPcs Conversion
49. AN13 RB AN14 RB AN15 OCFB CN12 RB OC7 CN15 RD6 OC6 CN14 RD5 OC5 CN13 RD4 IC6 CN19 RD13 IC5 RD12 OC4 RD3 OC3 RD2 OC2 RD1 VDD IC7 U1CTS CN20 RD14 IC8 U1RTS CN21 RD15 U2RX CN17 RF4 Bi Pins are up to 5V tolerant Vss PGEC2 SOSCO T1CK CNO RC14 PGED2 SOSCI CN1 RC13 OC1 RDO IC4 RD11 IC3 RD10 IC2 RD9 IC1 RD8 INT4 RA15 INT3 RA14 Vss OSC2 CLKO RC15 1 OSC1 CLKIN RC12 VDD TDO RAS TDI RA4 SDA2 RA3 SCL2 RA2 SCL1 RG2 SDA1 RG3 SCK1 INTO RF6 SDI1 RF7 SDO1 RF8 U1RX RF2 U1TX RF3 U2TXICN18 RF5 DS70175H page 8 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 Pin Diagrams Continued 100 Pin TQFP Pins are up to 5V tolerant AN23 CN23 RA7 AN22 CN22 RA6 C2RX RGO C2TX RG1 IC6 CN19 RD13 IC5 RD12 OC4 RD3 OC3 RD2 OC5 CN13 RD4 OC2 RD1 AN28 RE4 AN27 RE3 AN26 RE2 RG13 AN25 RE1 AN24 REO C1RX RFO VDD VCAP VDDCORE OC8 CN16 RD7 OC7 CN15 RD6 OC6 CN14 RD5 RG12 RG14 OY 0 9 8 4 3 2 1 9 8 85 84 83 82 1 80 79 78 77 76 588 8 5 8 5 RG15 1 75 vVss Voo 2 74 PGEC2 SOSCO T1CK CNO RC14 AN29 RE5 L 3 73 PGED2 SOSCIICN1 RC13 4 72 B OC1 RDO AN31 RE7L_ 5 71 IC4 RD11 AN16 T2CK T7CKIRC1 6 BI IC3 RD10 ANTTIT3
50. CICTRL1 10 8 001 the module will enter the Module Disable mode If the module is active the module will wait for 11 recessive bits on the CAN bus detect that condition as an Idle bus then accept the module disable command When the OPMODE lt 2 0 gt bits CICTRL1 7 52 001 that indi cates whether the module successfully went into Module Disable mode The pins will revert to normal function when the module is in the Module Disable mode The module can be programmed to apply a low pass filter function to the CiRX input line while the module or the CPU is in Sleep mode The WAKFIL bit CiCFG2 lt 14 gt enables or disables the filter Note Typically if the CAN module is allowed to transmit in a particular mode of operation and a transmission is requested immedi ately after the CAN module has been placed in that mode of operation the mod ule waits for 11 consecutive recessive bits on the bus before starting transmission If the user switches to Disable mode within this 11 bit period then this transmission is aborted and the corresponding TXABT bit is set and TXREQ bit is cleared 19 3 3 NORMAL OPERATION MODE Normal Operation mode is selected when REQOP lt 2 0 gt 000 In this mode the module is activated and the pins will assume the CAN bus functions The module will transmit and receive CAN bus messages via the CiTX and CiRX pins 19 3 4 LISTEN ONLY MODE If the Listen Only mode is a
51. Channel 6 77 69 0 00009 0 00019 DMA7 DMA Channel 7 78 70 0x0000A0 0x0001A0 C1TX ECAN1 Transmit Data Request 79 71 0x0000A2 0x0001A2 C2TX 2 Transmit Data Request 80 125 72 117 0 0000 4 0x0001A4 Reserved 0x0000FE 0x0001FE TABLE 7 2 TRAP VECTORS Vector Number IVT Address AIVT Address Trap Source 0 0x000004 0x000104 Reserved 1 0x000006 0x000106 Oscillator Failure 2 0x000008 0x000108 Address Error 3 0x00000A 0x00010A Stack Error 4 0x00000C 0x00010C Math Error 5 0x00000E 0x00010E DMA Error Trap 6 0x000010 0x000110 Reserved 7 0x000012 0x000112 Reserved DS70175H page 70 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 7 3 Interrupt Control and Status Registers PIC24HJXXXGPX06 X08 X10 devices implement a total of 30 registers for the interrupt controller INTCON1 INTCON2 IFSO through IFS4 ECO through IEC4 IPCO through IPC17 INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2 INTCON contains the Inter rupt Nesting Disable NSTDIS bit as well as the control and status flags for the processor trap sources The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table The IFS registers maintain all of the interrupt request flags Each source of interrupt has a Status bit which is set by the respective peripheral
52. Divide by 2 4 8 Divide by 2 513 Note 1 This frequency range must be satisfied at all times TABLE 9 1 CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD lt 1 0 gt FNOSC lt 2 0 gt Note Fast RC Oscillator with Divide by N Internal XX 111 1 2 FRCDIVN Fast RC Oscillator with Divide by 16 Internal xx 110 1 FRCDIV16 Low Power RC Oscillator LPRC Internal xx 101 1 Secondary Timer1 Oscillator SOSC Secondary xx 100 1 Primary Oscillator HS with PLL Primary 10 011 HSPLL Primary Oscillator XT with PLL Primary 01 011 XTPLL Primary Oscillator EC with PLL Primary 00 011 1 ECPLL Primary Oscillator HS Primary 10 010 Primary Oscillator XT Primary 01 010 Primary Oscillator EC Primary 00 010 1 Fast RC Oscillator with PLL FRCPLL Internal xx 001 1 Fast RC Oscillator FRC Internal xx 000 1 Note 1 5 2 function is determined by the OSCIOFNC Configuration bit 2 This is the default oscillator mode for an unprogrammed erased device 2009 Microchip Technology Inc DS70175H page 123 PIC24HJXXXGPX06 X08 X10 REGISTER 9 1 OSCCON OSCILLATOR CONTROL REGISTER 0 0 R 0 R 0 R 0 U 0 R W y R W y R W y COSC lt 2 0 gt NOSC lt 2 0 gt 2 bit 15 bit 8 R W 0 U 0 R 0 U 0 R C 0 U 0 R W 0 R W 0 CLKLOCK LOCK CF L
53. ECAN MODULE FILTER 8 11 BUFFER POINTER REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F11BP lt 3 0 gt F10BP lt 3 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F9BP lt 3 0 gt F8BP lt 3 0 gt bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 bit 11 8 bit 7 4 bit 3 0 F11BP lt 3 0 gt RX Buffer Written when Filter 11 Hits bits F10BP lt 3 0 gt RX Buffer Written when Filter 10 Hits bits F9BP lt 3 0 gt RX Buffer Written when Filter 9 Hits bits F8BP lt 3 0 gt RX Buffer Written when Filter 8 Hits bits 2009 Microchip Technology Inc DS70175H page 189 PIC24HJXXXGPX06 X08 X10 REGISTER 19 15 CiBUFPNT4 ECAN MODULE FILTER 12 15 BUFFER POINTER REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F15BP lt 3 0 gt F14BP lt 3 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F13BP lt 3 0 gt F12BP lt 3 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 F15BP lt 3 0 gt bit 11 8 F14BP lt 3 0 gt bit 7 4 F13BP lt 3 0 gt bit 3 0 RX Buffer Written when Filter 15 Hits bits RX Buffer Written when Filter 14 Hits bits
54. F8MSK lt 1 0 gt 0000 Legend unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices TABLE 4 22 ECAN2 REGISTER MAP WHEN C2CTRL1 WIN 0 FOR PIC24HJ256GP610 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 TM 0500 See definition when WIN x 051E C2RXFUL1 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFULO 0000 C2RXFUL2 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000 C2RXOVF1 0528 RXOVF15 RXOVF14 RXKOVF13 12 RXOVF11 RXOVF10 9 RXOVF08 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVFO 0000 C2RXOVF2 052A RXOVF31 RXOVF30 29 28 RXOVF27 RXOVF26 RXOVF25 24 RXOVF23 22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 C2TRO1CON 0530 TXEN1 TX TX TX TX RTREN1 TX1PRI lt 1 0 gt TXENO TX TX TX TX RTREN0 TXOPRI lt 1 0 gt 0000 ABAT1 LARB1 ERR1 REQ1 ABATO LARBO ERRO REQO C2TR23CON 0532 TXEN3 TX TX TX TX RTREN3 TX3PRI lt 1 0 gt TXEN2 TX TX TX TX RTREN2 TX2PRI lt 1 0 gt 0000 ABAT3 LARB3 ERR3 REQ3 ABAT2 LARB2 ERR2 REQ2 C2TR45CON 0534 TXEN5 TX TX TX TX RTREN5 TX5PRI lt 1 0 gt TXEN4 TX TX
55. IC BLOCK DIAGRAM X 1 OR 2 Internal Data Bus I2CXRCV E Read gt A Shift SCLx Clock 12CxRSR LSB gt SDAx Address Match Match Detect Write C SER Write Read Read Y eii Start and Stop 4 Bit Detect Write Start Stop a 4 lt Bit Generation lt 2 5 odas 2 po g Read Collision 5 Write T Detect 5 ES d 2 ad Acknowledge i 1 m Generation Read _ Clock 2 Stretching 1 Write ac LSB gt Shift Clock Loro l gt Reload Control Write Down Counter 2 A 2 DS70175H page 162 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 17 1 I2CxCON I2Cx CONTROL REGISTER R W 0 U 0 R W 0 R W 1 HC R W 0 R W 0 R W 0 R W 0 I2CEN I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 HC R W 0 HC R W 0 HC R W 0 HC R W 0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend U Unimplemented bit read as 0 Readable bit W Writable bit HS Set in hardware HC Cleared in hardware Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 I2CEN I2Cx Enable bit 1 Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 Disable
56. Input Capture 5 48 40 0x000064 0x000164 IC6 Input Capture 6 49 41 0x000066 0x000166 OC5 Output Compare 5 50 42 0x000068 0x000168 OC6 Output Compare 6 51 43 0x00006A 0x00016A OC7 Output Compare 7 52 44 0x00006C 0x00016C OC8 Output Compare 8 53 45 0x00006E 0x00016E Reserved 2009 Microchip Technology Inc DS70175H page 69 PIC24HJXXXGPX06 X08 X10 TABLE 7 1 INTERRUPT VECTORS CONTINUED Vector Interrupt Number Request IRQ IVT Address AIVT Address Interrupt Source Number 54 46 0x000070 0x000170 DMA4 DMA Channel 4 55 47 0x000072 0x000172 T6 56 48 0x000074 0x000174 T7 Timer7 57 49 0x000076 0x000176 SI2C2 2 2 Slave Events 58 50 0x000078 0x000178 MI2C2 I2C2 Master Events 59 51 0 00007 0 00017 T8 Timer8 60 52 0 00007 0 00017 T9 Timer9 61 53 0x00007E 0x00017E INT3 External Interrupt 62 54 0x000080 0x000180 INT4 External Interrupt 4 63 55 0x000082 0x000182 C2RX ECAN2 Receive Data Ready 64 56 0x000084 0x000184 C2 ECAN2 Event 65 68 57 60 0x000086 0x000186 Reserved 0x00008C 0x00018C 69 61 0x00008bE 0x00018E DMAS5 DMA Channel 5 70 72 62 64 0x000090 0x000190 Reserved 0x000094 0x000194 73 65 0x000096 0x000196 U1E UART1 Error 74 66 0x000098 0x000198 U2E UART2 Error 75 67 0 00009 0 00019 Reserved 76 68 0 00009 0 00019
57. Note 1 Data in column is at 3 3V 25 C unless otherwise stated 2 Instruction cycle period Tcv equals two times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKI pin When an external clock input is used the max cycle time limit is DC no clock for all devices 3 Measurements are taken in EC mode The CLKO signal is measured on the 5 2 pin 4 Data for this parameter is Preliminary This parameter is characterized but not tested in manufacturing 2009 Microchip Technology Inc DS70175H page 243 PIC24HJXXXGPX06 X08 X10 TABLE 24 17 PLL CLOCK TIMING SPECIFICATIONS Vpp 3 0V TO 3 6V Standard Operating Conditions 3 0V to 3 6V unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for Industrial Symbol Characteristic Min Typ Units Conditions OS50 FPLLI PLL Voltage Controlled 0 8 8 MHz ECPLL HSPLL XTPLL Oscillator VCO Input modes Frequency Range OS51 Fsvs On Chip VCO System 100 200 MHz Frequency 0552 TLOCK PLL Start up Time Lock
58. Operating temperature 40 C lt lt 85 C for Industrial m Symbol Characteristic Min Typ Max Units Conditions Operating Voltage DC10 Supply Voltage VDD 3 0 3 6 DC12 VDR RAM Data Retention Voltage 18 v DC16 VPoR Voo Start Voltage Vss v es to ensure internal Power on Reset signal DC17 5 Vpp Rise Rate 0 03 V ms 0 3 0 0 15 to ensure internal Power on Reset signal DC18 VcoRE Core 2 25 2 75 V Voltage is dependent on Internal regulator voltage load temperature and VDD Note 1 Data column is at 3 3V 25 C unless otherwise stated 2 This is the limit to which VDD can be lowered without losing RAM data 3 These parameters are characterized but not tested in manufacturing 4 VDD voltage must remain at Vss for a minimum of 200 us to ensure POR 2009 Microchip Technology Inc DS70175H page 235 PIC24HJXXXGPX06 X08 X10 TABLE 24 5 CHARACTERISTICS OPERATING CURRENT IDD Standard Operating Conditions 3 0V to 3 6V DC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 C for Industrial a Typical Max Units Conditions Operating Current 100 2 DC20d 27 30 mA 40 C DC20a 27 30 mA 25 3 3V 10 MIPS DC20b 27 30 mA 85 C DC21d 36 40 mA 40 C 21 37 40 mA 25 C 3
59. Oscillator PLL clock source Note that clock switching must be enabled in the device Configuration word 2 8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2 ICD 3 or REAL ICE is selected as a debugger it automatically initializes all of the A D input pins ANx as digital pins by setting all bits in the AD1PCFGL register The bits in this register that correspond to the A D pins that are initialized by MPLAB ICD 2 ICD 3 or REAL ICE must not be cleared by the user application firmware otherwise communication errors will result between the debugger and the device If your application needs to use certain A D pins as analog input pins during the debug session the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module When MPLAB ICD 2 ICD 3 or REAL ICE is used as a programmer the user application firmware must correctly configure the AD1PCFGL register Automatic initialization of this register is only done during debugger operation Failure to correctly configure the register s will result in all A D pins being recognized as analog input pins resulting in the port value being read as a logic 0 which may affect user application functionality 2 9 Unused I Os Unused pins should be configured as outputs and driven to a logic low state Alternatively connect a 1k to 10k resistor to Vss on unused pins and drive the o
60. R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 F3BP lt 3 0 gt RX Buffer Written when Filter 3 Hits bits bit 11 8 F2BP lt 3 0 gt RX Buffer Written when Filter 2 Hits bits bit 7 4 F1BP lt 3 0 gt RX Buffer Written when Filter 1 Hits bits bit 3 0 FOBP lt 3 0 gt RX Buffer Written when Filter 0 Hits bits 1111 Filter hits received in RX FIFO buffer 1110 Filter hits received in RX Buffer 14 0001 Filter hits received in RX Buffer 1 0000 Filter hits received in RX Buffer 0 DS70175H page 188 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 19 13 CiBUFPNT2 ECAN MODULE FILTER 4 7 BUFFER POINTER REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F7BP lt 3 0 gt F6BP lt 3 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F5BP lt 3 0 gt F4BP lt 3 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 bit 11 8 bit 7 4 bit 3 0 F7BP lt 3 0 gt RX Buffer Written when Filter 7 Hits bits F6BP lt 3 0 gt RX Buffer Written when Filter 6 Hits bits F5BP lt 3 0 gt RX Buffer Written when Filter 5 Hits bits F4BP lt 3 0 gt RX Buffer Written when Filter 4 Hits bits REGISTER 19 14 CiBUFPNT3
61. RX Buffer Written when Filter 13 Hits bits F12BP lt 3 0 gt RX Buffer Written when Filter 12 Hits bits DS70175H page 190 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 19 16 CiRXFnSID ECAN MODULE ACCEPTANCE FILTER n STANDARD IDENTIFIER n 0 1 15 R W x R W x R W x R W x R W x R W x R W x R W x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R W x R W x R W x 0 0 R W x U 0 R W x R W x SID2 SID1 SIDO EXIDE EID17 EID16 bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bitis unknown bit 15 5 SID lt 10 0 gt Standard Identifier bits 1 Message address bit SIDx must be 1 to match filter 0 Message address bit SIDx must be o to match filter bit 4 Unimplemented Read as 0 bit 3 EXIDE Extended Identifier Enable bit If MIDE 1 then 1 Match only messages with extended identifier addresses 0 Match only messages with standard identifier addresses If MIDE 0 then Ignore EXIDE bit bit 2 Unimplemented Read as 0 bit 1 0 EID lt 17 16 gt Extended Identifier bits 1 Message address bit EIDx must be 1 to match filter 0 Message address bit EIDx must be o to match filter REGISTER 19 17 CiRXFnEID ECAN MODULE ACCEPTANCE FILTER n EXTENDED IDENTIFIER
62. Standard Operating Conditions 3 0V to 3 6V AC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt TA lt 85 C for Industrial Symbol Characteristic Min Typ Max Units Conditions SP10 TscL SCKx Output Low Time TCY 2 ns See Note 3 SP11 TscH SCKx Output High Time Tcv 2 ns See Note 3 SP20 TscF SCKx Output Fall Time ns See parameter 0032 and Note 4 SP21 TscR SCKx Output Rise Time ns See parameter 0031 and Note 4 SP30 SDOx Data Output Fall Time ns See parameter 0032 and Note 4 SP31 TdoR SDOx Data Output Rise Time ns See parameter 0031 and Note 4 SP35 TscH2doV SDOx Data Output Valid after 6 20 ns TscL2doV SCKx Edge SP40 TdiV2scH Setup Time of SDIx Data Input 23 ns TdiV2scL to SCKx Edge SP41 TscH2diL Hold Time of SDIx Data Input 30 ns TscL2diL to SCKx Edge Note 1 These parameters are characterized but not tested in manufacturing 2 Data in Typ column is at 3 3V 25 C unless otherwise stated 3 The minimum clock period for SCKx is 100 ns Therefore the clock generated in Master mode must not violate this specification 4 Assumes 50 pF load on all SPIx pins DS70175H page 252 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 FIGURE 24 10 SPIx MODULE MASTER MODE CKE 7 1 TIMING CHARACTERISTICS SDOx SDIX a SP
63. UEN1 UENO WAKE LPBACK ABAUD URXINV BRGH PDSEL lt 1 0 gt STSEL 0000 U1STA 0222 UTXISEL1 UTXINV UTXISELO UTXBRK UTXEN UTXBF TRMT URXISEL lt 1 0 gt ADDEN RIDLE PERR FERR OERR URXDA 0110 U1TXREG 0224 Transmit Register U1RXREG 0226 UART Receive Register 0000 U1BRG 0228 Baud Rate Generator Prescaler 0000 Legend x 7 unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices 0LX 80X 90XdOXXXf Hv CODld ABojouyoe diuSoJj9i Al 6002 Z eDed Hs L0 Sd TABLE 4 12 UART2 REGISTER MAP pitts 2 11 Bito Bite Bits Bit2 Bit Bito U2MODE 0230 UARTEN USIDL IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL lt 1 0 gt STSEL 0000 U2STA 0232 UTXISEL1 UTXINV UTXISELO UTXBRK UTXEN UTXBF TRMT URXISEL lt 1 0 gt ADDEN RIDLE PERR FERR OERR URXDA 0110 U2TXREG 0234 UART Transmit Register XXXX U2RXREG 0236 UART Receive Register 0000 U2BRG 0238 Baud Rate Genera
64. during operation Using table instructions to access individual bytes or words anywhere in the program space Remapping a portion of the program space into the data space Program Space Visibility Table instructions allow an application to read or write to small areas of the program memory This capability makes the method ideal for accessing data tables that need to be updated from time to time It also allows access to all bytes of the program word The remap ping method allows an application to access a large block of data on a read only basis which is ideal for look ups from a large table of static data It can only access the least significant word of the program word 4 4 1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits respectively a method is needed to create a 23 bit or 24 bit program address from 16 bit data registers The solution depends on the interface method to be used For table operations the 8 bit Table Page register TBLPAG is used to define a 32K word region within the program space This is concatenated with a 16 bit EA to arrive at a full 24 bit program space address In this format the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory TBLPAG lt 7 gt o or the configuration memory TBLPAG lt 7 gt 1 2009 Technology Inc DS70175H page 51 PIC24HJXXXGPX06 X08 X10
65. has a line of evaluation kits and demonstration software for analog filter design KEELOQ security ICs CAN IrDA PowerSmart battery management SEEVAL evaluation system Sigma Delta ADC flow rate sensing plus many more Check the Microchip web page www microchip com for the complete list of demonstration development and evaluation kits DS70175H page 232 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 24 0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC24HJXXXGPX06 X08 X10 electrical characteristics Additional information is provided in future revisions of this document as it becomes available Absolute maximum ratings for the PIC24HJXXXGPX06 X08 X10 family are listed below Exposure to these maximum rating conditions for extended periods can affect device reliability Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied Absolute Maximum Ratings Ambient temperature under bias sienne 40 C to 85 C e EE ESTE A EI an 65 to 150 Voltage on VDD with respect to VSS iii 0 3V to 4 0 Voltage any combined analog and digital pin and MCLR with respect to VSS 0 3V to VDD 0 3V Voltage on any digital on
66. thereby allowing full speed operation without any external clock generation hardware Clock switching between various clock sources Programmable clock postscaler for system power savings A Fail Safe Clock Monitor FSCM that detects clock failure and takes fail safe measures A Clock Control register OSCCON Nonvolatile Configuration bits for main oscillator selection A simplified diagram of the oscillator system is shown in Figure 9 1 FIGURE 9 1 PIC24HJXXXGPX06 X08 X10 OSCILLATOR SYSTEM DIAGRAM PIC24H Primary Oscillator OSC1 r 4 XT HS DOZE lt 2 0 gt X l 2 e 52 rr E RAS i 53 XTPLL HSPLL ECPLL FRCPLL mu 51 PLL 51 53 LN OSC2 r Q POSCMD lt 1 0 gt I I SS ee ee b gt I 2 FRCDIVN Oscillator 5 57 Fosc x e gt LE I Lt eee AD P TUN lt 5 0 gt FRCDIV lt 2 0 gt FRCDIV16 pf 16 56 S0 S5 Oscillator Secondary Oscillator MUERE SOSC sosco gt S4 I LPOSCEN x I I sosci x Clock Fail Clock Switch Reset 57 5 lt 2 0 gt 5 lt 2 0 gt WDT PWRT FSCM gt 1 Note 1 See Figure 9 2 for PLL details 2 Ifthe Oscillator is used with XT HS mo
67. timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high ViH and input low VIL requirements Ensure that the Communication Channel Select i e PGECX PGEDx pins programmed into the device matches the physical connections for the ICSP to MPLAB ICD 2 MPLAB ICD 3 or MPLAB REAL more information ICD 2 ICD 3 REAL ICE connection requirements refer to the following documents that are available on the Microchip website MPLAB ICD 2 In Circuit Debugger User s Guide DS51331 Using MPLAB ICD 2 poster 0551265 MPLAB ICD 2 Design Advisory 0551566 Using MPLABS ICD 3 In Circuit Debugger poster DS51765 MPLAB ICD 3 Design Advisory 0551764 MPLAB REAL ICE In Circuit Emulator User s Guide DS51616 Using MPLAB REAL ICE poster 0551749 2 6 External Oscillator Pins Many MCUs have options for at least two oscillators a high frequency primary oscillator and a low frequency secondary oscillator refer to Section 9 0 Oscillator Configuration for details The oscillator circuit should be placed on the same side of the board as the device Also place the oscillator circuit close to the respective oscillator pins not exceeding one half inch 12 distance between them The load capacitors should be placed next to the o
68. 0 R W 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 T6IE DMA4IE OCBIE OCTIE OC6IE IC6IE bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ICSIE ICAIE IC3IE DMASIE C1RXIE SPI2IE SPI2EIE bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 T6IE Timer6 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled DMAAIE DMA Channel 4 Data Transfer Complete Interrupt Enable bit 1 Interrupt request enabled Interrupt request not enabled Unimplemented Read as 0 OCBIE Output Compare Channel 8 Interrupt Enable bit 1 Interrupt request enabled Interrupt request not enabled OC7IE Output Compare Channel 7 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled OC6IE Output Compare Channel 6 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled Output Compare Channel 5 Interrupt Enable bit 1 Interrupt request enabled Interrupt request not enabled IC6IE Input Capture Channel 6 Interrupt Enable bit 1 Interrupt request enabled Interrupt request not enabled Input Capture Channel 5 Interrupt Enable bit 1 Interrupt request enab
69. 0 gt PLLPRE lt 4 0 gt 3040 PLLFBD 0746 PLLDIV lt 8 0 gt 0030 OSCTUN 0748 TUN lt 5 0 gt 0000 Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices Note 1 RCON register Reset values dependent on type of Reset 2 OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset TABLE 4 32 NVM REGISTER File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 0760 WR WREN WRERR lt 3 0 gt 00000 NVMKEY 0766 NVMKEY lt 7 0 gt 0000 Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices Note 1 Reset value shown is for POR only Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset TABLE 4 33 PMD REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 PMD1 0770 T5MD T4MD T3MD T2MD T1MD 12C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD 0000 PMD2 0772 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 PMD3 0774 T9MD T8
70. 0 gt bit 1 0 FOMSK lt 1 0 gt 11 Reserved Mask Source for Filter 7 bit Mask Source for Filter 6 bit Mask Source for Filter 5 bit Mask Source for Filter 4 bit Mask Source for Filter 3 bit Mask Source for Filter 2 bit Mask Source for Filter 1 bit Mask Source for Filter O bit 10 Acceptance Mask 2 registers contain mask 01 Acceptance Mask 1 registers contain mask 00 Acceptance Mask 0 registers contain mask DS70175H page 192 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 19 19 CiFMSKSEL2 ECAN FILTER 15 8 MASK SELECTION REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F15MSK lt 1 0 gt F14MSK lt 1 0 gt F13MSK lt 1 0 gt F12MSK lt 1 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 F11MSK lt 1 0 gt F10MSK lt 1 0 gt 9 5 lt 1 0 gt F8MSK lt 1 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 F15MSK lt 1 0 gt Mask Source for Filter 15 bit 11 Reserved 10 Acceptance Mask 2 registers contain mask 01 7 Acceptance Mask 1 registers contain mask 00 7 Acceptance Mask 0 registers contain mask bit 13 12 F14MSK lt 1 0 gt Mask Source for Filter 14 bit same values as bit 15 14 bit 11 10 F13MSK lt 1 0 gt Mask Source for Filter 13 bit same values as bit 15 14 bit 9 8 F
71. 00 Register Indirect with Post Increment mode bit 3 2 Unimplemented Read as 0 bit 1 0 MODE lt 1 0 gt DMA Channel Operating Mode Select bits 11 One Shot Ping Pong modes enabled one block transfer from to each DMA RAM buffer 10 Continuous Ping Pong modes enabled 01 One Shot Ping Pong modes disabled 00 Continuous Ping Pong modes disabled 2009 Microchip Technology Inc DS70175H page 113 PIC24HJXXXGPX06 X08 X10 REGISTER 8 2 DMAxREQ DMA CHANNEL x IRQ SELECT REGISTER R W 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 FORCE 22 bit 15 bit 8 0 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSELO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 7 bit 6 0 FORCE Force DMA Transfer bit 1 Force a single DMA transfer Manual mode 0 Automatic DMA transfer initiation by DMA request Unimplemented Read as 0 IRQSEL lt 6 0 gt DMA Peripheral IRQ Number Select bits 2 0000000 1111111 DMAIRQ0 DMAIRQ127 selected to be Channel DMAREQ Note 1 The FORCE bit cannot be cleared by the user The FORCE bit is cleared by hardware when the forced DMA transfer is complete 2 Please see Table 8 1 for a complete listing of
72. 1 FRCDIV lt 2 0 gt Internal Fast RC Oscillator Postscaler bits 000 FRC divide by 1 default 001 FRC divide by 2 010 FRC divide by 4 011 divide by 8 100 FRC divide by 16 101 divide by 32 110 FRC divide by 64 111 FRC divide by 256 PLLPOST lt 1 0 gt PLL VCO Output Divider Select bits also denoted as N2 PLL postscaler 00 Output 2 01 Output 4 default 10 Reserved 11 Output 8 Unimplemented Read as 0 PLLPRE lt 4 0 gt PLL Phase Detector Input Divider bits also denoted as N1 PLL prescaler 00000 Input 2 default 00001 Input 3 11111 Input 33 Note 1 This bit is cleared when the ROI bit is set and an interrupt occurs DS70175H page 126 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 9 3 PLLFBD PLL FEEDBACK DIVISOR REGISTER U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 PLLDIV 8 bit 15 bit 8 R W 0 R W 0 R W 1 R W 1 R W 0 R W 0 R W 0 R W 0 PLLDIV 7 0 bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 9 Unimplemented Read as 0 bit 8 0 PLLDIV lt 8 0 gt PLL Feedback Divisor bits also denoted as M PLL multiplier 000000000 2 000000001 3 000000010 4 000110000 50 default 111111111 513 2
73. 100 256 16 8 9 8 8 0 1ADC 2 212 0 85 PF 32 ch PIC24HJ256GP610 100 256 16 8 9 8 8 0 2ADC 2 212 2 85 PF 32 ch Note 1 size is inclusive of 2 Kbytes RAM 2 Maximum pin count includes pins shared by the peripheral functions 2009 Microchip Technology Inc DS70175H page 3 PIC24HJXXXGPX06 X08 X10 Pin Diagrams 64 Pin TQFP RG15 AN16 T2CK T7CK RC1 AN17 T3CK T6CK RC2 SCK2 CN8 RG6 SDI2 CN9 RG7 SDO2 CN10 RG8 MCLR SS2 CN11 RG9 Vss VDD AN5 IC8 CN7 RB5 AN4 IC7 CN6 RB4 AN3 CN5 RB3 AN2 SS1 CN4 RB2 PGEC3 AN1 VREF CN3 RB1 PGED3 ANO VREF CN2 RBO Note ERRAT C I O Q N OC6 IC6 CN14 RD5 OC5 IC5 CN13 RD4 OC4 RD3 OC3 RD2 OC7 CN15 RD6 OC2 RD1 VCAP VDDCORE OC8 CN16 RD7 PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ256GP206 E Pins are up to 5V tolerant PGEC2 SOSCO T1CK CNO RC14 PGED2 SOSCI TACK CN1 RC13 OC1 RDO IC4 INT4 RD11 IC3 INT3 RD10 IC2 U1CTS INT2 RD9 IC1 INT1 RD8 Vss OSC2 CLKO RC15 OSC1 CLKIN RC12 VDD SCL1 RG2 SDA1 RG3 U1RTS SCK1 INTO RF6 U1RX SDI1 RF2 U1TX SDO1 RF3 PGEC1 ANG OCFA RB6 L 117 L 118 AVDD L 119 AVss L 120 U2CTS AN8 RB8 21 PGED1 AN7 RB7 Vss L 125 VDD L 126 AN9 RB9 L 122 TCK AN12 RB12 427 TMS AN10 RB10 123 TDO AN11 RB11 C 324 TDI AN13 RB13 L 128
74. 1545 TBF SDA Bus Free Time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 1 3 us before a new transmission 1 MHz model 0 5 Al pe Pan otart IS50 CB Bus Capacitive Loading 400 pF Note 1 Maximum pin capacitance 10 pF for all I2Cx pins for 1 MHz mode only DS70175H page 260 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 FIGURE 24 17 ECAN MODULE I O TIMING CHARACTERISTICS Old Value x New Value CAM CiRx Pin input N i 20 TABLE 24 34 ECAN MODULE I O TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions 3 0V to 3 6V unless otherwise stated Operating temperature 40 C lt lt 85 C for Industrial us Symbol Characteristic Min Typ Max Units Conditions CA10 TioF Port Output Fall Time ns See parameter D032 CA11 TioR Port Output Rise Time ns See parameter D031 CA20 Tcwf Pulse Width to Trigger 120 ns Wake up Filter Note 1 2 These parameters are characterized but not tested in manufacturing Data in Typ column is at 3 3V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 2009 Microchip Technology Inc DS70175H page 261 PIC24HJXXXGPX06 X08 X10 TABLE 24 35 ADC MODULE SPECIFICATIONS
75. 2 0 gt bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 11 Unimplemented Read as 0 bit 10 8 U2EIP lt 2 0 gt UART2 Error Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 7 Unimplemented Read as 0 bit 6 4 U1EIP lt 2 0 gt UART1 Error Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3 0 Unimplemented Read as 0 2009 Microchip Technology Inc DS70175H page 107 PIC24HJXXXGPX06 X08 X10 REGISTER 7 32 17 INTERRUPT PRIORITY CONTROL REGISTER 17 U 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 2 lt 2 0 gt C1TXIP lt 2 0 gt bit 15 bit 8 0 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 DMA7IP lt 2 0 gt DMAGIP lt 2 0 gt bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 Unimplemented Read as 0 bit 14 12 C2TXIP lt 2 0 gt ECAN2 Transmit Data Request Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is
76. 28 2009 Technology Inc PIC24HJXXXGPX06 X08 X10 FIGURE 4 4 DATA MEMORY MAP FOR PIC24HJXXXGPX06 X08 X10 DEVICES WITH 16 KBS RAM MSB LSB Address 16 bits Address MSB LSB 0x0001 0x0000 4 2 Kbyte SFR Space SFR Space 0x07FF 0 07 8 Kbyte 0 0801 0 0800 ___ Near Data Space OxTEEES r oe et sn Ox1FFE _ X Data RAM X 16 Kbyte SRAM Space Ox3FFF Ox3FFE 0x4001 0x4000 DMA RAM OxA7FF 0 47 0 4801 0 4800 0 8001 0 8000 X Data Unimplemented X Optionally Mapped into Program Memory 4 2 5 various peripherals using RAM Every PIC24HJXXXGPX06 X08 X10 device contains 2 Kbytes of dual ported DMA RAM located at the end of data space Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA as well as data transferred from accessed by the DMA controller without having to steal cycles from the CPU When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location the hardware ensures that the CPU is given precedence in accessing the DMA RAM location Therefore the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU D
77. 3V 16 MIPS DC21b 38 45 mA 85 C DC22d 43 50 mA 40 C DC22a 46 50 mA 25 C 3 3V 20 MIPS DC22b 46 55 mA 85 C DC23d 65 70 mA 40 C DC23a 65 70 mA 25 C 3 3V 30 MIPS DC23b 65 70 mA 85 C DC24d 84 90 mA 40 C DC24a 84 90 mA 25 C 3 3V 40 MIPS DC24b 84 90 mA 85 C Note 1 Data in Typical column is at 3 3V 25 C unless otherwise stated 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements are as follows OSC1 driven with external square wave from rail to rail All pins are configured as inputs and pulled to Vss MCLR VpD WDT and FSCM are disabled CPU SRAM program memory and data memory are operational No peripheral modules are operating however every peripheral is being clocked PMD bits are all zeroed DS70175H page 236 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 TABLE 24 6 DC CHARACTERISTICS IDLE CURRENT IIDLE Standard Operating Conditions 3 0V to 3 6V DC CHARACTERISTICS unless otherwise stated Operating temperature 40 C lt lt 85 C for Industrial Typical Max Units Conditions Idle Current Core OFF Clock ON Base Current DC40d 3
78. 4 0 gt FIFO Area Starts with Buffer bits 11111 RB31 buffer 11110 RB30 buffer 00001 TRB1 buffer 00000 TRBO buffer 2009 Microchip Technology Inc DS70175H page 181 PIC24HJXXXGPX06 X08 X10 REGISTER 19 5 CiFIFO ECAN MODULE FIFO STATUS REGISTER U 0 U 0 R 0 R 0 R 0 R 0 R 0 R 0 lt 5 0 gt bit 15 bit 8 0 0 0 0 R 0 R 0 R 0 R 0 R 0 R 0 en z FNRB lt 5 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 Unimplemented Read as 0 bit 13 8 FBP lt 5 0 gt FIFO Write Buffer Pointer bits 011111 RB31 buffer 011110 RB30 buffer 000001 TRB1 buffer 000000 TRBO buffer bit 7 6 Unimplemented Read as 0 bit 5 0 FNRB lt 5 0 gt FIFO Next Read Buffer Pointer bits 011111 RB31 buffer 011110 RB30 buffer 000001 TRB1 buffer 000000 TRBO buffer DS70175H page 182 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 19 6 ECAN MODULE INTERRUPT FLAG REGISTER U 0 U 0 R 0 R 0 R 0 R 0 R 0 R 0 TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R C 0 R C 0 R C 0 U 0 R C 0 R C 0 R C 0 R C 0 IVRIF WAKIF ERRIF FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend C Clear only bit R Readable bit n Value a
79. 6 IFS1 INTERRUPT FLAG STATUS REGISTER 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 R W 0 R W 0 IC8IF AD2IF INT1IF CNIF MI2C1IF SI2C11F bit 7 bit O Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 U2TXIF UART2 Transmitter Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred U2RXIF UART2 Receiver Interrupt Flag Status bit 1 Interrupt request has occurred Interrupt request has not occurred INT2IF External Interrupt 2 Flag Status bit 1 Interrupt request has occurred Interrupt request has not occurred T5IF Timer5 Interrupt Flag Status bit 1 Interrupt request has occurred Interrupt request has not occurred TAIF Timer4 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred OC4IF Output Compare Channel 4 Interrupt Flag Status bit 1 Interrupt request has occurred 0 Interrupt request has not occurred OC3IF Output Compare Channel 3 Interrupt Flag Status bit 1 Interrupt request has occurred Interrupt request has not occurred DMA21IF DMA Channel 2 Data Transfer
80. 8 U 0 R W 0 R W 0 R W 0 U 0 U 0 R W 0 U 0 TGATEU TCKPS lt 1 0 gt Tcs 3 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 TON Timery On bit 1 Starts 16 bit Timery 0 Stops 16 bit Timery bit 14 Unimplemented Read as 0 bit 13 TSIDL Stop in Idle Mode bit 1 Discontinue module operation when device enters Idle mode Continue module operation in Idle mode bit 12 7 Unimplemented Read as 0 bit 6 Timery Gated Time Accumulation Enable bit When TCS 1 This bit is ignored When TCS 0 1 Gated time accumulation enabled 0 Gated time accumulation disabled bit 5 4 TCKPS lt 1 0 gt Timer3 Input Clock Prescale Select bits 11 1 256 10 1 64 01 1 8 00 1 1 bit 3 2 Unimplemented Read 0 bit 1 TCS Timery Clock Source Select bit 1 3 1 External clock from pin TyCK on the rising edge 0 Internal clock FcY bit 0 Unimplemented Read 0 Note 1 When 32 bit operation is enabled T2CON lt 3 gt 1 these bits have no effect Timery operation all timer functions are set through T2CON 2 When 32 bit timer operation is enabled T32 1 in the Timer Control register TxCON lt 3 gt the TSIDL bit must be cleared to operate the 32 bit timer in Idle mode 3 The TyCK pin is not available for all timers Refer to the Pin Diagrams sect
81. AD12B 1 CHxSB is U 0 Unimplemented Read as 0 1 CH1 positive input is AN3 CH2 positive input is AN4 CH3 positive input is AN5 0 CH1 positive input is ANO CH2 positive input is AN1 CH3 positive input is 2 bit 7 3 Unimplemented Read as 0 bit 2 1 123 lt 1 0 gt Channel 1 2 3 Negative Input Select for Sample A bits When AD12B 1 CHxNA is U 0 Unimplemented Read as 0 11 CH1 negative input is AN9 CH2 negative input is AN10 CH3 negative input is 11 10 CH1 negative input is AN6 CH2 negative input is AN7 CH3 negative input is AN8 0x CH1 CH2 CH3 negative input is VREF bit O 1235 Channel 1 2 3 Positive Input Select for Sample A bit When AD12B 1 CHxSA is U 0 Unimplemented Read as 0 1 CH1 positive input is AN3 CH2 positive input is AN4 CH3 positive input is AN5 0 CH1 positive input is ANO CH2 positive input is AN1 CH3 positive input is 2 2009 Microchip Technology Inc DS70175H page 209 PIC24HJXXXGPX06 X08 X10 REGISTER 20 6 ADxCHS0 ADCx INPUT CHANNEL 0 SELECT REGISTER R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 CHOSB lt 4 0 gt bit 15 bit 8 R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 CHOSA lt 4 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit i
82. Any one out of three pairs of programming clock data pins may be used PGEC1 and PGED1 PGEC2 and PGED2 PGEC3 and PGED3 21 8 In Circuit Debugger When MPLAB ICD 2 is selected as a debugger the in circuit debugging functionality is enabled This func tion allows simple debugging functions when used with MPLAB IDE Debugging functionality is controlled through the PGECx Emulation Debug Clock and PGEDx Emulation Debug Data pin functions Any one out of three pairs of debugging clock data pins may be used PGEC1 and PGED1 PGEC2 and PGED2 PGEC3 and PGED3 To use the in circuit debugger function of the device the design must implement ICSP programming capa bility connections to MCLR VDD Vss and the PGEDx PGECx pin pair In addition when the feature is enabled some of the resources are not available for general use These resources include the first 80 bytes of data RAM and two pins DS70175H page 220 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 22 0 INSTRUCTION SET SUMMARY Note This data sheet summarizes the features of the PIC24HJXXXGPX06 X08 X10 families of devices However it is not intended to be a comprehensive reference source To complement the information in this data sheet refer to the related section in the PIC24H Family Reference Manual which is available from the Microchip website www microchip com The PIC24H instruction set is identical
83. Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRISD 0202 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF PORTD 02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO LATD 02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATDO XXXX ODCD 06D2 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCDO 0000 Legend x unknown value on Reset unimplemented read as 0 Reset values are shown in hexadecimal for PinHigh devices Note 1 The actual set of I O port pins varies from one device to another Please refer to the corresponding pinout diagrams 0LX 80X 90XdOXXXf Hv cDld gr eBed Hs 107sa 1 dIU9019IWN 6002 TABLE 4 28 PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRISE 02D8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00
84. CAPTURE x CONTROL REGISTER U 0 U 0 R W 0 U 0 U 0 U 0 U 0 U 0 ICSIDL bit 15 bit 8 R W 0 R W 0 R W 0 R 0 HC R 0 HC R W 0 R W 0 R W 0 ICTMR lt 1 0 gt lt 2 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 14 bit 13 bit 12 8 bit 7 bit 6 5 bit 4 bit 3 bit 2 0 Unimplemented Read as 0 ICSIDL Input Capture Module Stop in Idle Control bit 1 Input capture module will halt in CPU Idle mode 0 Input capture module will continue to operate in CPU Idle mode Unimplemented Read as 0 ICTMR Input Capture Timer Select bits 1 1 TMR2 contents are captured on capture event 0 TMR3 contents are captured on capture event lt 1 0 gt Select Number of Captures per Interrupt bits 11 Interrupt on every fourth capture event 10 Interrupt on every third capture event 01 Interrupt on every second capture event 00 Interrupt on every capture event ICOV Input Capture Overflow Status Flag bit read only 1 Input capture overflow occurred No input capture overflow occurred ICBNE Input Capture Buffer Empty Status bit read only 1 Input capture buffer is not empty at least one more capture value can be read Input captu
85. Characteristics for the full operating ranges of VDD and VCAP VDDCORE 2 Itis important for the low ESR capacitor to be placed as close as possible to the VCAP VDDCORE pin 21 3 BOR Brown out Reset The BOR Brown out Reset module is based on an internal voltage reference circuit that monitors the reg ulated voltage VCAP VDDCORE The main purpose of the BOR module is to generate a device Reset when a brown out condition occurs Brown out conditions are generally caused by glitches on the AC mains i e missing portions of the AC cycle waveform due to bad power transmission lines or voltage sags due to exces sive current draw when a large inductive load is turned on A BOR will generate a Reset pulse which will reset the device The BOR will select the clock source based on the device Configuration bit values FNOSC lt 2 0 gt and POSCMD lt 1 0 gt Furthermore if an oscillator mode is selected the BOR will activate the Oscillator Start up Timer OST The system clock is held until OST expires If the PLL is used then the clock will be held until the LOCK bit OSCCON lt 5 gt is 1 Concurrently the PWRT time out TPWRT will be applied before the internal Reset is released If TPWRT 0 and a crystal oscillator is being used then a nominal delay of TFSCM 100 is applied The total delay in this case is TFSCM The BOR Status bit RCON lt 1 gt will be set to indicate that a BOR has occurred The BOR ci
86. Condition Condition Note Refer to Figure 24 1 for load conditions FIGURE 24 14 I2Cx BUS DATA TIMING CHARACTERISTICS MASTER MODE IM20 1 a a IM ee 2 SCLx COCO SDAx CAY Out Note Refer to Figure 24 1 for load conditions 2009 Microchip Technology Inc DS70175H page 257 PIC24HJXXXGPX06 X08 X10 TABLE 24 32 2 BUS DATA TIMING REQUIREMENTS MASTER MODE AC CHARACTERISTICS Standard Operating Conditions 3 0V to 3 6V unless otherwise stated 40 C lt TA lt 85 for Industrial Operating temperature jiu Symbol Characteristic Min Max Units Conditions IM10 TLO scL Clock Low Time 100 kHz mode 2 1 us 400 kHz mode Tcy 2 BRG 1 us 1 MHz 2 Tcv 2 1 us IM11 THI SCL Clock High Time 100 kHz mode TCY 2 BRG 1 us 400 kHz mode Tcy 2 BRG 1 us 1 MHz mode Tcv 2 1 us 20 TF SCL SDAx 100 kHz mode 300 ns CB is specified to be Fall Time 400 kHz mode 20 0 1 300 ns from 10 to 400 pF 1 MHz model 100 ns IM21 TR SCL SDAX and SCLx 100 kHz mode 1000 ns CB is specified to be Rise Time 400 kHz mode 20 0 1 CB 300 ns from 1
87. DS70175H page 57 PIC24HJXXXGPX06 X08 X10 5 2 RTSP Operation The PIC24HJXXXGPX06 X08 X10 Flash program memory array is organized into rows of 64 instructions or 192 bytes RTSP allows the user to erase a page of memory which consists of eight rows 512 instructions at a time and to program one row or one word at a time Table 24 12 displays typical erase and program ming times The 8 row erase pages and single row write rows are edge aligned from the beginning of pro gram memory on boundaries of 1536 bytes and 192 bytes respectively The program memory implements holding buffers that can contain 64 instructions of programming data Prior to the actual programming operation the write data must be loaded into the buffers in sequential order The instruction words loaded must always be from a group of 64 boundary The basic sequence for RTSP programming is to set up a Table Pointer then do a series of TBLWT instructions to load the buffers Programming is performed by set ting the control bits in the NVMCON register A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions All of the table write operations are single word writes two instruction cycles because only the buffers are written A programming cycle is required for programming each row 5 3 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode The process
88. IVRIE WAKIE ERRIE FIFOIE RBIE 0000 C1EC 040E TERRCNT lt 7 0 gt RERRCNT lt 7 0 gt 0000 C1CFG1 0410 SJW lt 1 0 gt BRP lt 5 0 gt 0000 C1CFG2 0412 WAKFIL SEG2PH lt 2 0 gt SEG2PHTS SAM SEG1PH lt 2 0 gt PRSEG lt 2 0 gt 0000 C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 FLTEN7 FLTENS FLTEN4 FLTEN2 FLTEN1 FLTENO FFFF C1FMSKSEL1 0418 F7MSK lt 1 0 gt F6MSK lt 1 0 gt F5MSK lt 1 0 gt F4MSK lt 1 0 gt F3MSK lt 1 0 gt F2MSK lt 1 0 gt 1 5 lt 1 0 gt FOMSK lt 1 0 gt 0000 C1FMSKSEL2 041A F15MSK lt 1 0 gt F14MSK lt 1 0 gt F13MSK lt 1 0 gt F12MSK lt 1 0 gt F11MSK lt 1 0 gt F10MSK lt 1 0 gt F9MSK lt 1 0 gt F8MSK lt 1 0 gt 0000 Legend unimplemented read as 0 Reset values are shown hexadecimal for PinHigh devices TABLE 4 19 ECAN1 REGISTER MAP WHEN C1CTRL1 WIN 0 FOR PIC24HJXXXGP506 510 610 DEVICES ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hou 0400 See definition when WIN x 041E C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFULO 0000 C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20
89. Latch RAM PCU PCH PCL X RAM PORTB Program Counter Stack Loop Address Control Control Latch Logic Logic DMA 6 Controller 16 PORTC Address Latch Address Generator Units Program Memory EA MUX Data Latch ROM Latch PERE 24 16 16 5 Instruction Decode and 5 Control lt T Instruction Reg 9 3 46 PORTE Control Signals to Various Blocks 17 x 17 Multiplier lt gt 16x16 OSC2 CLKO Timing Power up PE W Register Array OSCA CLKI Generation lt gt Timer Divide Support HR 16 PORTF lt lt Oscillator FRC LPRC Start up Timer Oscillators Power on dae 16 bit ALU Precision EDI Band Gap P Reference PORTG Voltage Brown out Regulator Reset VCAP VDDCORE Vop Ves MCLR ee ADC1 2 ECAN1 2 UART1 2 IC1 8 KR CN1 23 SPI1 2 12C1 2 PWM1 8 i i Note Not all pins or features are implemented on all device pinout configurations See pinout diagrams for the specific pins and features present on each device DS70175H page 12 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 TABLE 1 1 PINOUT DESCRIPTIONS Pin Buffer Description AN0 AN31 Analog Analog input channels AVDD P P Positive supply for analog modules This pin must be connected at all times 55 Ground reference for analog modules CLKI ST CMOS External clock source input Always associated with OSC1
90. MPLAB IDE debugger 23 4 MPLINK Object Linker MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler It can link relocatable objects from precompiled libraries using directives from a linker script The MPLIB Object Librarian manages the creation and modification of library files of precompiled code When a routine from a library is called from a source file only the modules that contain that routine will be linked in with the application This allows large libraries to be used efficiently in many different applications The object linker library features include Efficient linking of single libraries instead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing replacement deletion and extraction 23 5 MPLAB ASM30 Assembler Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices MPLAB C30 C Compiler uses the assembler to produce its object file The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file Notable features of the assembler include Support for the entire dsPIC30F instruction set Support for fixed point and floating point data Command line i
91. MULTIPLIER Using the high speed 17 bit x 17 bit multiplier the ALU supports unsigned signed or mixed sign operation in several multiplication modes 16 bit x 16 bit signed 16 bit x 16 bit unsigned 16 bit signed x 5 bit literal unsigned 16 bit unsigned x 16 bit unsigned 16 bit unsigned x 5 bit literal unsigned 16 bit unsigned x 16 bit signed 8 bit unsigned x 8 bit unsigned S F O N gt 3 4 2 DIVIDER The divide block supports 32 bit 16 bit and 16 bit 16 bit signed and unsigned integer divide operations with the following data sizes 1 32 bit signed 16 bit signed divide 2 32 bit unsigned 16 bit unsigned divide 3 16 bit signed 16 bit signed divide 4 16 bit unsigned 16 bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1 Sixteen bit signed and unsigned DIV instructions can specify any W register for both the 16 bit divisor Wn and any W register aligned pair W m 1 Wm for the 32 bit dividend The divide algorithm takes one cycle per bit of divisor so both 32 bit 16 bit and 16 bit 16 bit instructions take the same number of cycles to execute 3 4 3 MULTI BIT DATA SHIFTER The multi bit data shifter is capable of performing up to 16 bit arithmetic or logic right shifts or up to 16 bit left shifts in a single cycle The source can be either a working register or a memory location The shifter requires a signed binary value to determine both the magnitude
92. Multiplier working register pair for DSP instructions e WA W5 W4 W6 W4 W7 W5 W6 W5 W7 W6 W7 Wn One of 16 working registers e W0 W15 DS70175H page 222 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 TABLE 22 1 SYMBOLS USED IN OPCODE DESCRIPTIONS CONTINUED Field Description Wnd One of 16 destination working registers e WO W15 Wns One of 16 source working registers e WO W15 WREG WO working register used in file register instructions Ws Source W register Ws Ws Ws Ws Ws Ws Wso Source W register Wns Wns Wns Wns Wns Wns Wns Wb 2009 Technology Inc DS70175H page 223 PIC24HJXXXGPX06 X08 X10 TABLE 22 2 INSTRUCTION SET OVERVIEW Assembly Syntax Description ane 1 ADD ADD f f WREG 1 1 C DC N OV Z ADD WREG f WREG 1 1 C DC N OV Z ADD 11610 Wd 1110 Wd 1 1 C DC N OV Z ADD Wb Wd Wb Ws 1 1 C DC N OV Z ADD Wb lit5 Wd Wd Wb lit5 1 1 C DC N OV Z 2 ADDC ADDC f f WREG C 1 1 C DC N OV Z ADDC f WREG WREG f WREG C 1 1 C DC N OV Z ADDC lit10 Wn Wd lit10 Wd 1 1 C DC N OV Z ADDC Wb Wd Wb Ws C 1 1 C DC N OV Z ADD
93. NOT affect any operation in progress Automatically cleared by hardware at start of a new conversion 2009 Microchip Technology Inc DS70175H page 205 PIC24HJXXXGPX06 X08 X10 REGISTER 20 2 ADxCON2 ADCx CONTROL REGISTER 2 where x 1 or 2 R W 0 R W 0 R W 0 U 0 U 0 R W 0 R W 0 R W 0 VCFG lt 2 0 gt CSCNA CHPS lt 1 0 gt bit 15 bit 8 R 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 BUFS SMPI 3 0 BUFM ALTS bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 13 VCFG lt 2 0 gt Converter Voltage Reference Configuration bits VREF VREF 000 AVDD 55 001 External VREF AVss 010 AVDD External VREF 011 External VREF External VREF 1 AVDD 55 bit 12 11 Unimplemented Read 0 bit 10 CSCNA Scan Input Selections for CH0 during Sample bit 1 Scan inputs 0 Do not scan inputs bit 9 8 CHPS lt 1 0 gt Selects Channels Utilized bits When AD12B 1 CHPS lt 1 0 gt is 0 0 Unimplemented Read as 0 1 Converts CHO CH1 CH2 and CH3 01 Converts CH0 and CH1 00 Converts CH0 bit 7 BUFS Buffer Fill Status bit only valid when BUFM 1 1 ADC is currently filling second half of buffer user should access data in first half 0 ADC is currently filling first half of buffer
94. PLLPOST lt 1 0 gt bits CLKDIV lt 7 6 gt N2 can be either 2 4 or 8 and must be selected such that the PLL output frequency Fosc is in the range of 12 5 MHz to 80 MHz which generates device operating speeds of 6 25 40 MIPS For a primary oscillator or FRC oscillator output FIN the PLL output Fosc is given by EQUATION 9 2 Fosc CALCULATION _ Fosc FIN s DS70175H page 122 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 For example suppose a 10 MHz crystal is being used EQUATION 9 3 XT WITH PLL MODE with XT with PLL being the selected oscillator mode EXAMPLE If PLLPRE lt 4 0 gt o then 1 2 This yields a VCO input of 10 2 5 MHz which is within the acceptable range of 0 8 8 MHz If PLLDIV 8 0 Ox1E then Foy FOSC 11000009 52 40 MIPS M 32 This yields a VCO output of 5 x 32 160 MHz 2 dv A which within 100 200 MHz ranged needed PLLPOST lt 1 0 gt o then 2 2 This provides Fosc of 160 2 80 MHz The resultant device operating speed is 80 2 40 MIPS FIGURE 9 2 PIC24HJXXXGPX06 X08 X10 PLL BLOCK DIAGRAM Fvco 100 200 MHz 0 8 8 0 2 12 5 80 2 Herel 7 Source Crystal External or Internal RC PLLPRE X gt VCO PLLPOST Fosc N1 Divide by 2 33 N2
95. Programmer The PICkit 2 Development Programmer is a low cost programmer and selected Flash device debugger with an easy to use interface for programming many of Microchip s baseline mid range and PIC18F families of Flash memory microcontrollers The PICkit 2 Starter Kit includes a prototyping development board twelve sequential lessons software and HI TECH s PICC Lite C compiler and is designed to help get up to speed quickly using PIC microcontrollers The kit provides everything needed to program evaluate and develop applications using Microchip s powerful mid range Flash memory family of microcontrollers 23 13 Demonstration Development and Evaluation Boards A wide variety of demonstration development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully func tional systems Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification The boards support a variety of features including LEDs temperature sensors switches speakers RS 232 interfaces LCD displays potentiometers and additional EEPROM memory The demonstration and development boards can be used in teaching environments for prototyping custom circuits and for learning about various microcontroller applications In addition to the PICDEM and dsPICDEM demon stration development board series of circuits Microchip
96. R 0 URXISEL lt 1 0 gt ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend HC Hardware cleared C Clear only bit R Readable bit n Value at POR W Writable bit 1 Bit is set U Unimplemented bit read as 0 0 Bit is cleared x Bit is unknown bit 15 13 bit 14 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 6 Note 1 UTXISEL lt 1 0 gt Transmission Interrupt Mode Selection bits 11 Reserved do not use 10 Interrupt when a character is transferred to the Transmit Shift Register and as a result the transmit buffer becomes empty 01 Interrupt when the last character is shifted out of the Transmit Shift Register all transmit operations are completed 00 Interrupt when a character is transferred to the Transmit Shift Register this implies there is at least one character open in the transmit buffer UTXINV Transmit Polarity Inversion bit If IREN 0 1 UXTX Idle state is o 0 UxTX Idle state is 1 If IREN 1 1 IrDA encoded UxTX Idle state is 1 0 IrDA encoded UxTX Idle state is Unimplemented Read as 0 UTXBRK Transmit Break bit 1 Send Sync Break on next transmission Start bit followed by twelve 0 bits followed by Stop bit cleared by hardware upon completion 0 Sync Break transmission disabled or completed UTXEN Transmit Enable bit 1 Transmit enabled UxTX pin controlled by UARTx 0 Transmit disabled
97. R W 0 U 0 U 0 U 0 U 0 lt 2 0 gt bit 15 bit 8 U 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 MI2C1IP 2 0 SI2C1IP 2 0 bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 Unimplemented Read as 0 bit 14 12 CNIP lt 2 0 gt Change Notification Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 11 7 Unimplemented Read as 0 bit 6 4 MI2C11P lt 2 0 gt 2 1 Master Events Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3 Unimplemented Read as 0 bit 2 0 SI2C1IP 2 0 2 1 Slave Events Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled 2009 Microchip Technology Inc DS70175H page 95 PIC24HJXXXGPX06 X08 X10 REGISTER 7 20 IPC5 INTERRUPT PRIORITY CONTROL REGISTER 5 U 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 IC8IP lt 2 0 gt lt 2 0 gt bit 15 bit 8 0 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 21 lt 2 0 gt INT1IP lt 2 0 gt bit 7 bit 0 Legend R Readable
98. R W 0 U 0 U 0 U 0 U 0 U 0 FRMEN SPIFSD FRMPOL bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 U 0 FRMDLY bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 FRMEN Framed SPIx Support bit 1 Framed SPIx support enabled SSx pin used as frame sync pulse input output 0 Framed SPIx support disabled bit 14 SPIFSD Frame Sync Pulse Direction Control bit 1 Frame sync pulse input slave 0 Frame sync pulse output master bit 13 FRMPOL Frame Sync Pulse Polarity bit 1 Frame sync pulse is active high 0 Frame sync pulse is active low bit 12 2 Unimplemented Read as 0 bit 1 FRMDLY Frame Sync Pulse Edge Select bit 1 Frame sync pulse coincides with first bit clock Frame sync pulse precedes first bit clock bit 0 Unimplemented Read as 0 This bit must not be set to 1 by the user application 2009 Microchip Technology Inc DS70175H page 159 PIC24HJXXXGPX06 X08 X10 NOTES DS70175H page 160 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 17 0 INTER INTEGRATED CIRCUIT Note This data sheet summarizes the features of the PIC24HJXXXGPX06 X08 X10 fam ily of devices However it is not intended to be a comprehensive reference source To complement the information in this data sheet refer to the PIC24H Fa
99. RRNC Ws Wd Wd Rotate Right No Carry Ws 1 1 N Z 57 Wnd sign extended Ws 1 1 C NZ 58 SETM SETM f f 1 1 None SETM WREG WREG 0xFFFF 1 1 Ws Ws 0xFFFF 1 1 None 59 SL SL f f Left Shift f 1 1 C N OV Z SL WREG WREG Left Shift f 1 1 C N OV Z SL Ws Wd Wd Left Shift Ws 1 1 C N OV Z SL Wb Wns Wnd Wnd Left Shift Wb by Wns 1 1 N Z SL Wb 1165 Left Shift Wb by lits 1 1 N Z 60 SUB SUB f f WREG 1 1 C DC N OV Z SUB f WREG WREG f WREG 1 1 C DC N OV Z SUB 1it10 Wn Wn Wn lit10 1 1 C DC N OV Z SUB Wb Ws Wd Wd Wb Ws 1 1 C DC N OV Z SUB Wb 1165 Wd Wb lits 1 1 C DC N OV Z 61 SUBB SUBB f f WREG C 1 1 C DC N OV Z SUBB f WREG WREG f WREG C 1 1 C DC N OV Z SUBB lit10 Wn Wn Wn lit10 C 1 1 C DC N OV Z SUBB Wb Ws Wd Wd Wb Ws C 1 1 C DC N OV Z SUBB Wb 1it5 Wd Wd Wb lit5 C 1 1 C DC N OV Z 62 SUBR SUBR f f WREG f 1 1 C DC N OV Z SUBR WREG WREG f 1 1 C DC N OV Z SUBR Wb Ws Wd Wd Ws Wb 1 1 C DC N OVZ SUBR Wb 1165 Wd 5 Wb 1 1 C DC N OV Z 63 SUBBR SUBBR f WREG f C 1 1 C DC N OV Z SUBBR WREG WREG WREG f C 1 1 C DC N OV Z SUBBR Wb Wd Ws Wb 1 1 C DC N OV Z SUBBR Wb 1it5 Wd Wd 5 Wb C 1 1 C DC N OV Z 64 SWAP SWAP b Wn Wn nibble swap Wn 1 1 None SWAP Wn Wn byte swap Wn 1 1 None 65 TBLRDH TBLRDH
100. Section 5 3 Programming Operations for further details DS70175H page 58 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 5 1 NVMCON FLASH MEMORY CONTROL REGISTER R SO 0 1 RAW 0 1 RAW 0 1 U 0 U 0 U 0 U 0 U 0 WR WREN WRERR bit 15 bit 8 U 0 R W o U 0 U 0 RAN 0 R W o R W o RAW 0 1 NVMOP lt 3 0 gt 2 bit 7 bit O Legend SO Settable only bit R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 WR Write Control bit 1 Initiates a Flash memory program or erase operation The operation is self timed and the bit is cleared by hardware once operation is complete Program or erase operation is complete and inactive bit 14 WREN Write Enable bit 1 Enable Flash program erase operations 0 Inhibit Flash program erase operations bit 13 WRERR Write Sequence Error Flag bit 1 An improper program or erase sequence attempt or termination has occurred bit is set automatically on any set attempt of the WR bit 0 The program or erase operation completed normally bit 12 7 Unimplemented Read as 0 bit 6 ERASE Erase Program Enable bit 1 Perform the erase operation specified by NVMOP lt 3 0 gt on the next WR command Perform the program operation specified by NVMOP lt 3 0 gt o
101. Start from Sample 2 0 TAD 3 0 Auto convert trigger not Trigger selected AD61 tPss Sample Start from Setting 2 0 13 0 Sample 5 bit 2 AD62 css Conversion Completion to 0 5 TAD Sample Start ASAM 1 AD63 tDPU Time to Stabilize Analog Stage 20 us from ADC Off to ADC On 2 5 Note 1 Because the sample caps eventually loses charge clock rates below 10 kHz may affect linearity performance especially at elevated temperatures 2 These parameters are characterized but not tested in manufacturing 3 tDPU is the time required for ADC module to stabilize when it is turned on AD1CON1 ADON 1 During this time the ADC result is indeterminate DS70175H page 266 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 FIGURE 24 19 ADC CONVERSION 10 BIT MODE TIMING CHARACTERISTICS lt 1 0 gt 01 SIMSAM 0 ASAM 0 SSRC 2 0 000 AD50 _ ADCLK Instruction Execution Set SAMP X Clear SAMP X SAMP MIX XE AS Y LR MT i i i LUC UC UR ae ae T PE Te 559 u LX Wh w edes 122 TSAMP peg AD5 A55 DONE 1 1 1 T 1 1 1 1 1 s DE 1 1 1 1 1 IC AD1IF U
102. Start sequence 0 Repeated Start condition not in progress SEN Start Condition Enable bit when operating as 2 master 1 Initiate Start condition on SDAx and SCLx pins Hardware clear at end of master Start sequence 0 Start condition not in progress DS70175H page 164 2009 Microchip Technology Inc PIC24HJXXXGPX06 X08 X10 REGISTER 17 2 I2CxSTAT I2Cx STATUS REGISTER R 0 HSC R 0 HSC U 0 U 0 U 0 R C 0 HS R 0 HSC R 0 HSC ACKSTAT TRSTAT BCL GCSTAT ADD10 bit 15 bit 8 R C 0 HS R C 0 HS R 0 HSC R C 0 HSC 0 HSC R 0 HSC R 0 HSC R 0 HSC IWCOL I2COV DA P 5 R_W RBF TBF bit 7 bit 0 Legend U Unimplemented bit read as 0 C Clear only bit R Readable bit W Writable bit HS Set in hardware HSC Hardware set cleared n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 ACKSTAT Acknowledge Status bit when operating as 2 master applicable to master transmit operation 1 NACK received from slave 0 ACK received from slave Hardware set or clear at end of slave Acknowledge TRSTAT Transmit Status bit when operating as 2 master applicable to master transmit operation 1 Master transmit is in progress 8 bits ACK 0 Master transmit is not in progress Hardware set at beginning of master transmiss
103. Table 4 35 and Figure 4 6 show how the program EA is created for table operations and remapping accesses from the data EA Here P lt 23 0 gt refer

MICROCHIP PIC24HJXXXGPX06/X08/X10 Data Sheet High-Performance 16-Bit Microcontrollers Manual

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