ANALOG DEVICES ADN2813 Manual3
Contents
1. NIN CLKOUTP CLKOUTN DATAOUTP DATAOUTN also REFCLKP and REFCLKN if a high frequency reference clock is used such as 155 MHZ It is also necessary for the PIN NIN input traces to be matched in length and the CLKOUTP CLKOUTN and DATAOUTP DATAOUTN output traces to be matched in length to avoid skew between the differential traces The high speed inputs PIN and NIN are internally terminated with 50 Q to an internal reference voltage see Figure 25 A 0 1 uF is recommended between VREF Pin 3 and GND to provide an ac ground for the inputs As with any high speed mixed signal design take care to keep all high speed digital traces away from sensitive analog nodes vcc X 500 Cin PIN ADN2813 0 1uF 04951 0 026 y Figure 25 ADN2813 AC Coupled Input Configuration Soldering Guidelines for Lead Frame Chip Scale Package The lands on the 32 lead LFCSP are rectangular The printed circuit board PCB pad for these should be 0 1 mm longer than the package land length and 0 05 mm wider than the package land width The land should be centered on the pad This ensures that the solder joint size is maximized The bottom of the chip scale package has a central exposed pad The pad on the PCB should be at least as large as this exposed pad The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow This ensures a solid connection from the exposed pad2. Rev B Page 18 of 28 1 ADN2813 REFCLKP REFCLKN 1 Figure 21 Differential REFCLK Configuration 04951 0 021 O VCC 2 vee ADN2813 REFCLKP OUT REFCLKN 04951 0 022 O VCC 2 Figure 22 Single Ended REFCLK Configuration voc ADN2813 REFCLKP NCO 11 REFCLKN 04951 0 023 O VCC 2 Figure 23 No REFCLK Configuration The two uses of the reference clock are mutually exclusive The reference clock can be used either as an acquisition aid for the ADN2813 to lock onto data or to measure the frequency of the incoming data to within 0 01 There is the capability to measure the data rate to approximately 10 without the use of a reference clock The modes are mutually exclusive because in the first use the user knows exactly what the data rate is and wants to force the part to lock onto only that data rate in the second use the user does not know what the data rate is and wants to measure it Lock to reference mode is enabled by writing a 1 to Register Bit CTRLA 0 Fine data rate readback mode is enabled by writing a 1 to Register Bit CTRLA 1 Writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported ADN2813 Using the Reference Clock to Lock onto Data In this mode the ADN2813 locks onto a frequency derived from the reference clock according to Data Rate 2 T 462 REFCLK 2CTRAAU8 The user must know exactly what t
3. 09 198 3 8247e 08 214 5 4794e 08 230 7 6493e 08 246 1 0959e 09 199 3 9177e 08 215 5 6195e 08 231 7 8355e 08 247 1 1239e 09 200 4 0179e 08 216 5 7706e 08 232 8 0358e 08 248 1 1541e 09 201 4 1322e 08 217 5 9423e 08 233 8 2643e 08 249 1 1885e 09 202 4 2490e 08 218 6 1189e 08 234 8 4981e 08 250 1 2238e 09 203 4 3758e 08 219 6 3098e 08 235 8 7516e 08 251 1 2620e 09 204 4 5133e 08 220 6 5173e 08 236 9 0266e 08 252 1 3035e 09 205 4 6636e 08 221 6 7423e 08 237 9 3272e408 253 1 3485e 09 206 4 8272e 08 222 6 9873e 08 238 9 6543e 08 254 1 3975e 09 207 5 0061e 08 223 7 2525e 08 239 1 0012e 09 255 1 4505e 09 Rev B Page 25 of 28 ADN2813 OUTLINE DIMENSIONS PIN 1 INDICATOR 0 80 MAX T MAR 0 65 TYP 0 05 FOR PROPER CONNECTION OF AS ae THE EXPOSED PAD REFER TO NEN THE PIN CONFIGURATION AND 0 30 COPLANARITY FUNCTION DESCRIPTIONS 023 n 0 20 REF SECTION OF THIS DATA SHEET SEATING 0 08 PLANE PIN 1 EXPOSED PAD BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 Figure 30 32 Lead Frame Chip Scale Package LFCSP VQ 5mm x 5 mm Body Very Thin Quad CP 32 2 Dimensions shown in millimeters INDICATOR 011708 A ORDERING GUIDE Model Temperature Range Package Description Package Option ADN2813ACPZ 40 C to 85 C 32 Lead LFCSP_VQ CP 32 2 ADN2813ACPZ 500RL7 40 C 85 C 32 Lead LFCSP_VQ Tape Reel 500 Pieces CP 32 2 ADN2813ACPZ RL7 40 C to 85 C 32 Lead LFCSP_VQ Tap
4. 1 Static LOL until reset 1 Acquiring 1 Measurement complete Table 8 Control Register CTRLA Frer Range Data Rate Div Facer Ratio Measure Data Rate Lock to Reference D7 D6 D5 D4 D3 D2 D1 DO 0 0 10 MHz to 20 MHz 0 0 0 0 1 Set to 1 to measure data rate 0 Lock to input data 0 1 20 MHz to 40 MHz 0 0 0 1 2 1 Lock to reference clock 1 0 40 MHz to 80 MHz 0 0 1 0 4 1 1 80 MHz to 160 MHz n 2 1 0 0 0 256 1 Where Fi is the divided down reference referred to the 10 MHz to 20 MHz band see the Reference Clock Optional section Table 9 Control Register CTRLB Config LOL Reset MISC 4 System Reset Reset MISC 2 D7 D6 D5 D4 D3 D2 D1 DO 0 LOL pin normal operation Write 1 followed by Write a 1 followed Set Write 1 followed byO Set Set Set 1 LOL pin is static LOL 0 to reset MISC 4 to reset ADN2813 00 toreset MISC 2 to0 100 tod Table 10 Control Register CTRLC Config LOS SQUELCH Mode Output Boost D7 D6 D5 D4 D3 D2 D1 DO Setto0 0 SettoO SettoO Setto0 0 Active high LOS 0 SQUELCH CLK and DATA 0 Default output swing 1 Active low LOS 1 SQUELCH CLK or DATA 1 Boost output swing Rev B Page 11 of 28 ADN2813 TERMINOLOGY Input Sensitivity and Input Overdrive Sensitivity and overdrive specifications for the quantizer involve offset voltage gain and noise The relationship between the logic output
5. LVDS OUTPUT STAGE Figure 4 Differential Output Stage 04951 0 033 Rev B Page 7 of 28 ADN2813 PIN CONFIGURATION AND FUNCTION DESC az EE 55 xx l l oo ow NN VCC 1 PIN 1 24 VCC vcc 2 INDIC ATOR 23 VEE VREF 3 22 LOS NIN 4 ADN2813 21SDA PIN 5 TOP VIEW 20 SCK SLICEP 6 Not to Scale 19 SADDR5 SLICEN 7 18 VCC VEE 8 17 VEE ogreozi2e 20zoumwmr 8 8 0 6659 too 8 rI Im 3 FE co THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND Figure 5 Pin Configuration Table 5 Pin Function Descriptions Pin No Mnemonic Description 1 VCC Al Connect to VCC 2 VCC P Power for Limiting Amplifier LOS 3 VREF AO Internal VREF Voltage Decouple to GND with a 0 1 uF capacitor 4 NIN Al Differential Data Input CML 5 PIN Al Differential Data Input CML 6 SLICEP Al Differential Slice Level Adjust Input 7 SLICEN Al Differential Slice Level Adjust Input 8 VEE P GND for Limiting Amplifier LOS 9 THRADJ Al LOS Threshold Setting Resistor 10 REFCLKP DI Differential REFCLK Input 10 MHz to 160 MHz 11 REFCLKN DI Differential REFCLK Input 10 MHz to 160 MHz 12 VCC P VCO Power 13 VEE P VCO GND 14 CF2 AO Frequency Loop Capacitor 15 CF1 AO Frequency Loop Capacitor 16 LOL DO Loss of Lock Indicator LVTTL active high 17 VEE P FLL Detector GND 18 VCC P FLL Detector Power 19 SADDR5 DI Slave Address Bit 5 20 SCK DI Cloc
6. also be dc coupled This may be necessary in burst mode applications where there are long periods of CIDs and baseline wander cannot be tolerated If the inputs to the ADN2813 are dc coupled care must be taken not to violate the input range and common mode level require ments of the ADN2813 see Figure 27 through Figure 29 If dc coupling is required and the output levels of the TIA do not adhere to the levels shown in Figure 28 then level shifting and or an attenuator must be between the TIA outputs and the ADN2813 inputs 04951 0 028 Figure 27 DC Coupled Application V p p PIN NIN 2 Vgg 10mV AT SENSITIVITY 2 Vse 5mV MIN Vom 2 3V MIN DC COUPLED Figure 28 Minimum Allowed DC Coupled Input Levels V p p PIN NIN 2 Vgg 2 0V MAX Vse 1 0 A A Vcu 23V 5 DC COUPLED a 2 04951 0 030 Figure 29 Maximum Allowed DC Coupled Input Levels Rev B Page 23 of 28 ADN2813 COARSE DATA RATE READBACK LOOK UP TABLE Code is the 9 bit value read back from COARSE RD 8 0 Table 13 Look Up Table Code Code Code Code 0 5 3745 06 48 1 5333 07 96 4 2996 07 144 1 2266e408 1 5 3741e406 49 1 5332e 07 97 4 2993e 07 145 1 2266e 08 2 5 4793e 06 50 1 5643e 07 98 4 3834e 07 146 1 2515e 08 3 5 5912e 06 51 1 5976e 07 99 4 4729e 07 147 1 2781e 08 4 5 7111e 06 52 1 6333e 07 100 4 5688e 07 148 1 3067e 08 5 5 8391e 06 53 1 6714
7. gt ANALOG Continuous Rate 10 Mb s to 1 25 Gb s Clock and DEVICES pata Recovery IC with Integrated Limiting Amp ADN2813 FEATURES Serial data input 10 Mb s to 1 25 Gb s Exceeds SONET requirements for jitter transfer generation tolerance Quantizer sensitivity 3 3 mV typ Adjustable slice level 95 mV Patented clock recovery architecture Loss of signal LOS detect range 2 3 mV to 19 mV Independent slice level adjust and LOS detector No reference clock required Loss of lock indicator PC interface to access optional features Single supply operation 3 3 V Low power 450 mW typ 5 mm x 5 mm 32 lead LFCSP Pb free APPLICATIONS SONET OC 1 3 12 and all associated FEC rates Fibre Channel GbE HDTVs WDM transponders Regenerators repeaters Test equipment Broadband cross connects and routers GENERAL DESCRIPTION The ADN2813 provides the receiver functions of quantization signal level detect and clock and data recovery for continuous data rates from 10 Mb s to 1 25 Gb s The ADN2813 automati cally locks to all data rates without the need for an external reference clock or programming All SONET jitter requirements are met including jitter transfer jitter generation and jitter tolerance All specifications are quoted for 40 C to 85 C ambient temperature unless otherwise noted This device together with a PIN diode and a TIA preamplifier can implement a highly integrated low cost low power fiber opti
8. input data rate is 1 25 Gb s GbE After following Step 1 through Step 4 the value that is read back on FREQ 22 0 0x138800 which is equal to 1 28 x 10 Plugging this value into the equation yields 128e6 x 32e6 20 1 25 Gb s If subsequent frequency measurements are required CTRLA 1 should remain set to 1 It does not need to be reset The measurement process is reset by writing a 1 followed by a 0 to CTRLB 3 This initiates a new data rate measurement Follow Step 2 through Step 4 to read back the new data rate Note that a data rate readback is valid only if LOL is low If LOL is high the data rate readback is invalid Additional Features Available via the Interface Coarse Data Rate Readback The data rate can be read back over the I C interface to approximately 10 without the need of an external reference clock A 9 bit register COARSE RD 8 0 can be read back when LOL is deasserted The eight MSBs of this register are the contents of the RATE 7 0 register The LSB of the COARSE RD register is Bit MISC 0 Table 13 provides coarse data rate readback to within X 1096 LOS Configuration The LOS detector output Pin 22 can be configured to be either active high or active low If CTRLC 2 is set to Logic 0 default the LOS pin is active high when a loss of signal condition is detected Writing a 1 to CTRLC 2 configures the LOS pin to be active low when a loss of signal condition is detected System Rese
9. reason the user does not need to know the data rate to use the reference clock in this manner Prior to reading back the data rate using the reference clock the CTRLA 7 6 bits must be set to the appropriate frequency range with respect to the reference clock being used A fine data rate readback is then executed as follows 1 Write a 1 to CTRLA 1 This enables the fine data rate measurement capability of the ADN2813 This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements 2 Reset MISC 2 by writing a 1 followed by a 0 to CTRLB 3 This initiates a new data rate measurement 3 Read back MISC 2 If it is 0 the measurement is not complete If it is 1 the measurement is complete and the data rate can be read back on 22 0 The time for a data rate measurement is typically 80 ms 4 Read back the data rate from FREQ2 6 0 FREQ1 7 0 and FREQO 7 0 The data rate can be determined by fpATARATE FREQ 22 0 s SrerciK are where FREQ 22 0 is the reading from FREQ2 6 0 MSByte FREQ1 7 0 and FREQO 7 0 LSByte see Table 12 foaranarz is the data rate Mb s frercix is the REFCLK frequency MHz SEL_RATE is the setting from CTRLA 7 6 Table 12 For example if the reference clock frequency is 32 MHz SEL_RATE 1 since the CTRLA 7 6 setting is 01 because the reference frequency falls into the 20 MHz to 40 MHz range Assume for this example that the
10. respect to the reference frequency For more details see the Reference Clock Optional section In this mode the lock detector monitors the difference in frequency between the divided down VCO and the divided down reference clock The loss of lock signal which appears on Pin 16 LOL is deasserted when the VCO is within 250 ppm of the desired frequency This enables the D PLL which pulls the VCO frequency in the remaining amount with respect to the input data and acquires phase lock Once locked if the input frequency error exceeds 1000 ppm 0 196 the loss of lock signal is reasserted and control returns to the frequency loop which reacquires with respect to the reference clock The LOL pin remains asserted until the VCO frequency is within 250 ppm of the desired frequency This hysteresis is shown in Figure 20 Static LOL Mode The ADN2813 implements a static LOL feature which indicates if a loss of lock condition has ever occurred and remains asserted even if the ADN2813 regains lock until the static LOL bit is manually reset The I C register bit MISC 4 is the static LOL bit If there is ever an occurrence of a loss of lock condition this bit is internally asserted to logic high The MISCT 4 bit remains high even after the ADN2813 has reacquired lock to a new data rate This bit can be reset by writing a 1 followed by 0 to Register Bit CTRLB 6 Once reset the MISC 4 bit remains deasserted until another loss of lock c
11. stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADN2813 does not issue an acknowledge and returns to the idle condition If the user exceeds the highest subaddress while reading back in auto increment mode then the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read In a no acknowledge condition the SDATA line is not pulled low on the ninth pulse See Figure 8 and Figure 9 for sample read and write data transfers and Figure 10 for a more detailed timing diagram REFERENCE CLOCK OPTIONAL A reference clock is not required to perform clock and data recovery with the ADN2813 However support for an optional reference clock is provided The reference clock can be driven differentially or single ended If the reference clock is not being used then REFCLKP should be tied to VCC and REFCLKN can be left floating or tied to VEE the inputs are internally terminated to VCC 2 See Figure 21 through Figure 23 for sample configurations The REFCLK input buffer accepts any differential signal with a peak to peak differential amplitude of greater than 100 mV for example LVPECL or LVDS or a standard single ended low voltage TTL input providing maximum system flexibility Phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is sufficient
12. the ADN2813 is operating in lock to reference mode if the user ever changes the reference frequency the Frer range CTRLA 7 6 or the Frrr ratio CTRLA 5 2 this must be followed by writing a 0 to 1 transition into the CTRLA 0 bit to initiate a new lock to reference command Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency In this case the user provides a reference clock and the ADN2813 compares the frequency of the incoming data to the incoming reference clock and returns a ratio of the two frequencies to 0 0196 100 ppm The accuracy error of the reference clock is added to the accuracy of the ADN2813 data rate measurement For example if a 100 ppm accuracy reference clock is used the total accuracy of the measurement is within 200 ppm Rev B Page 19 of 28 ADN2813 The reference clock can range from 10 MHz and 160 MHz The ADN2813 expects a reference clock between 10 MHz and 20 MHz by default If it is between 20 MHz and 40 MHz 40 MHz and 80 MHz or 80 MHz and 160 MHz the user needs to configure the ADN2813 to use the correct reference frequency range by setting two bits of the CTRLA register CTRLA 7 6 Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data In this mode the reference clock is used only to determine the frequency of the data For this
13. to VEE Choosing AC Coupling Capacitors AC coupling capacitors at the input PIN NIN and output DATAOUTP DATAOUTN of the ADN2813 must be chosen such that the device works properly over the full range of data rates used in the application When choosing the capacitors the time constant formed with the two 50 resistors in the signal path must be considered When a large number of consecutive identical digits CIDs are applied the capacitor voltage can droop due to baseline wander see Figure 26 causing pattern dependent jitter PDJ The user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop The amount of PDJ can then be approximated based on the capacitor selection The actual capacitor value selection can require some trade offs between droop and PDJ For example assuming 2 droop can be tolerated then the maximum differential droop is 496 Normalizing to V p p Droop V 0 04 V 0 5 V p p 1 therefore 12t where t is the RC time constant C is the ac coupling capacitor R 100 seen by C t is the total discharge time which is equal to nT n is the number of CIDs T is the bit period The capacitor value can then be calculated by combining the equations for t and t C 12nT R Once the capacitor value is selected the PDJ can be approximated as PDI psp 0 5t 1 e C 18O0 0 6 where PDJpspp is the amount of pattern depende
14. 136e 08 31 1 1332e 07 79 3 1288e 07 127 9 0657e 07 175 2 5030e 08 32 1 0749e 07 80 3 0665e 07 128 8 5991e 07 176 2 4532e 08 33 1 0748e 07 81 3 0664e 07 129 8 5986e 07 177 2 4531e 08 34 1 0959e 07 82 3 1287e 07 130 8 7668e 07 178 2 5029e 08 35 1 1182e 07 83 3 1952e 07 131 8 9458e 07 179 2 5562e 08 36 1 1422e 07 84 3 2667e 07 132 9 1377e 07 180 2 6134e 08 37 1 1678e 07 85 3 3428e 07 133 9 3426e 07 181 2 6742e 08 38 1 1952e 07 86 3 4246e 07 134 9 5616e 07 182 2 7397e 08 39 1 2243e 07 87 3 5122e 07 135 9 7944e 07 183 2 8098e 08 40 1 2556e 07 88 3 6066e 07 136 1 0045e 08 184 2 8853e 08 41 1 2913e 07 89 3 7140e 07 137 1 0330e 08 185 2 9712e 08 42 1 3278e 07 90 3 8243e 07 138 1 0623e 08 186 3 0594e 08 43 1 3674e 07 91 3 9436e 07 139 1 0940e 08 187 3 1549e 08 44 1 4104e 07 92 4 0733e 07 140 1 1283e 08 188 3 2587e 08 45 1 4574e 07 93 4 2140e 07 141 1 1659e 08 189 3 3712e 08 46 1 5085e 07 94 4 3671e 07 142 1 2068e 08 190 3 4936e 08 47 1 5644e 07 95 4 5328e 07 143 1 2515e 08 191 3 6263e 08 Rev B Page 24 of 28 ADN2813 Code Code Code Code 192 3 4397 08 208 4 9064 08 224 6 8793 08 240 9 8129 08 193 3 4394 08 209 4 9062 08 225 6 8789 08 241 9 8124 08 194 3 5067 08 210 5 0059 08 226 7 0135 08 242 1 0012 09 195 3 5783e408 211 5 1123e408 227 7 1567e408 243 1 0225e 09 196 3 6551e 08 212 5 2267e 08 228 7 3102e 08 244 1 0453e 09 197 3 7370e 08 213 5 3485e 08 229 7 4741e 08 245 1 0697e
15. ISTICS LVCMOS Input High Voltage Vin 0 7 VCC V Input Low Voltage Vit 03VCC V Input Current Vin 0 1 VCC or Vin 0 9 VCC 10 0 10 0 yA Output Low Voltage Voi lo 3 0 mA 0 4 V INTERFACE TIMING See Figure 11 SCK Clock Frequency 400 kHz SCK Pulse Width High 600 ns SCK Pulse Width Low tiow 1300 ns Start Condition Hold Time tup sTA 600 ns Start Condition Setup Time tsu srA 600 ns Data Setup Time tsu DAT 100 ns Data Hold Time tHD DAT 300 ns SCK SDA Rise Fall Time Tr Te 20 0 1 Cb 300 ns Stop Condition Setup Time tsusro 600 ns Bus Free Time Between a Stop and a Start teur 1300 ns REFCLK CHARACTERISTICS Optional lock to REFCLK mode Input Voltage Range REFCLKP or REFCLKN Vu 0 V Vin VCC V Minimum Differential Input Drive 100 mV p p Reference Frequency 10 160 MHz Required Accuracy 100 ppm LVTTL DC INPUT CHARACTERISTICS Input High Voltage Vin 2 0 V Input Low Voltage Vit 0 8 V Input High Current liu VN 2 4 V 5 Input Low Current li VN 0 4 V 5 LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Vou 2 0 mA 24 V Output Low Voltage Voi lo 2 0 mA 0 4 V Cb total capacitance of one bus line in pF If mixed with Hs mode devices faster fall times are allowed Rev B Page 5 of 28 ADN2813 ABSOLUTE MAXIMUM RATINGS Ta Tun to Tmax VCC to Vmax VEE 0 V Cr 0 47 SLICEP SLICEN VEE unless otherwise noted Table 4 Parameter Rating Supply Voltage
16. VCC 4 2V Minimum Input Voltage All Inputs VEE 0 4 V Maximum Input Voltage All Inputs VCC 0 4 V Maximum Junction Temperature 125 C Storage Temperature Range 65 C to 150 C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate the human body and test equipment and can discharge without detection Although this product features THERMAL CHARACTERISTICS Thermal Resistance 32 LFCSB 4 layer board with exposed paddle soldered to VEE Oy 28 C W WARNING E proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy SAT electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev B Page 6 of 28 ADN2813 TIMING CHARACTERISTICS CLKOUTP HF Ty Ts gt DATAOUTP N 04951 0 002 Figure 2 Output Timing DIFFERENTIAL CLKOUTP N DATAOUTP N 04951 0 032 E VDIFF E SIMPLIFIED
17. arameter Conditions Min Typ Max Unit PHASE LOCKED LOOP CHARACTERISTICS Jitter Transfer BW OC 12 75 130 kHz OC 3 26 42 kHz Jitter Peaking OC 12 0 0 03 dB OC 3 0 0 03 dB Jitter Generation OC 12 12 kHz to 5 MHz 0 001 0 003 UI rms 0 011 0 026 UI p p OC 3 12 kHz to 1 3 MHz 0 001 0 002 UI rms 0 005 0 010 UI p p Jitter Tolerance 1 GbE IEEE 802 3 637 kHz 0 749 UI p p OC 12 223 1 PRBS 30 Hz 100 UI p p 300 Hz 44 UI p p 25 kHz 2 5 UI p p 250 kHz 1 0 UI p p OC 3 22 1 PRBS 30 Hz 50 UI p p 300 Hz 23 5 UI p p 6500 Hz 3 5 UI p p 65 kHz 1 0 UI p p Jitter tolerance of the ADN2813 at these jitter frequencies is better than what the test equipment is able to measure Rev B Page 4 of 28 OUTPUT AND TIMING SPECIFICATIONS ADN2813 Table 3 Parameter Conditions Min Typ Max Unit LVDS OUTPUT CHARACTERISTICS CLKOUTP CLKOUTN DATAOUTP DATAOUTN Output Voltage High see Figure 3 655 Mb s 1475 mV Output Voltage Low Va see Figure 3 655 Mb s 925 mV Differential Output Swing Vop see Figure 3 655 Mb s 250 320 400 mV Differential Output Swing Vop see Figure 3 1 25 Gb s 240 300 400 Output Offset Voltage Vos see Figure 3 1125 1200 1275 mV Output Impedance Differential 100 LVDS Outputs Timing GbE Rise Time 2096 to 8096 115 220 ps Fall Time 8096 to 2096 115 220 ps Setup Time Ts see Figure 2 GbE 360 400 440 ps Hold Time Tu see Figure 2 GbE 360 400 440 ps INTERFACE DC CHARACTER
18. c receiver The receiver front end loss of signal LOS detector circuit indicates when the input signal level has fallen below a user adjustable threshold The LOS detect circuit has hysteresis to prevent chatter at the output The ADN2813 is available in a compact 5 mm x 5 mm 32 lead LFCSP FUNCTIONAL BLOCK DIAGRAM REFCLKP N OPTIONAL SLICEP N HO O DATA RE TIMING THRADJ LOS DATAOUTP N Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners CLKOUTP N asi FREQUENCY DETECT ADN2813 04951 0 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 2010 Analog Devices Inc All rights reserved ADN2813 TABLE OF CONTENTS Features 1 Applications ito oe ERI ER tede 1 2 1 1 Functional Block Diagram 1 e NA 2 Specifications siepe ete ROMPE Renee 3 Jitter SDecificatlo
19. connections to the supply and ground are made through vias the use of multiple vias in parallel helps to reduce series inductance especially on Pin 24 which supplies power to the high speed CLKOUTP CLKOUTN and DATAOUTP DATAOUTN output buffers Refer to Figure 24 for the recommended connections By using adjacent power supply and GND planes excellent high frequency decoupling can be realized by using close spacing between the planes This capacitance is given by Cp Avg 0 88 A d pF where the dielectric constant of the PCB material A is the area of the overlap of power and GND planes cm d is the separation between planes mm For FR 4 4 4 mm and 0 25 mm spacing C 15 pF cm 500 TRANSMISSION LINES 0 DATAOUTP 6 DATAOUTN 6 cLKourP 6 J cLKouTN vcc 1nF 0 1uF vec f 2 E 105 V O1gF 1 NIN D ANE 25 SDA CONTROLLER PIN WITH vias 20 SCK CONTROLLER wy SLICEP 5 SADDRS vec 14 SLICEN 18 vee Y VEE I 17 VEE TIA 500 4 or ie 1nF 0 1pF la zlolule 2 CiN 69 EIP 2 V 500 uj uc g V vee 0 47uF 20 gt 300 INSULATION RESISTANCE 0 1uF 1nF V Figure 24 Typical ADN2813 Applications Circuit Rev B Page 21 of 28 04951 0 031 ADN2813 Transmission Lines Use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections PIN
20. control voltage remains small for small phase errors therefore the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation Rev B Page 14 of 28 ADN2813 At medium jitter frequencies the gain and tuning range of the VCO are not large enough to track input jitter In this case the VCO control voltage becomes large and saturates and the VCO frequency dwells at one extreme of its tuning range or at the other The size of the VCO tuning range therefore has only a small effect on the jitter accommodation The delay locked loop control voltage is now larger and therefore the phase shifter takes on the burden of tracking the input jitter The phase shifter range in UL can be seen as a broad plateau on the jitter tolerance curve The phase shifter has a minimum range of 2 UI at all data rates The gain of the loop integrator is small for high jitter frequencies therefore larger phase differences are needed to make the loop control voltage large enough to tune the range of the phase shifter Large phase errors at high jitter frequencies cannot be tolerated In this region the gain of the integrator determines the jitter accommodation Because the gain of the loop integrator declines linearly with frequency jitter accom modation is lower with higher jitter frequency At the highest frequencies the loop gain is very small and little tuning of the phase shifter can be
21. des of operation normal mode REFCLK mode and static LOL mode Normal Mode In normal mode the ADN2813 is a continuous rate CDR that locks onto any data rate from 10 Mb s to 1 25 Gb s without the use of a reference clock as an acquisition aid In this mode the lock detector monitors the frequency difference between the VCO and the input data frequency and deasserts the loss of lock signal which appears on Pin 16 LOL when the VCO is within 250 ppm of the data frequency This enables the D PLL which pulls the VCO frequency in the remaining amount and acquires phase lock Once locked if the input frequency error Rev B Page 16 of 28 exceeds 1000 ppm 0 196 the loss of lock signal is reasserted and control returns to the frequency loop which begins a new frequency acquisition starting at the lowest point in the VCO operating range 10 MHz The LOL pin remains asserted until the VCO locks onto a valid input data stream to within 250 ppm frequency error This hysteresis is shown in Figure 20 LOL 1000 250 0 250 1000 fyco ERROR ppm Figure 20 Transfer Function of LOL 04951 0 020 LOL Detector Operation Using a Reference Clock In REFCLK mode a reference clock is used as an acquisition aid to lock the ADN2813 VCO Lock to reference mode is enabled by setting CTRLA 0 to 1 The user also needs to write to the CTRLA 7 6 and CTRLA 5 2 bits to set the reference frequency range and the divide ratio of the data rate with
22. draw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the SDA and SCK lines waiting for the start condition and correct transmitted address The R W bit determines the direction of the data Logic 0 on the LSB of the first byte means that the master writes information to the peripheral Logic 1 on the LSB of the first byte means that the master reads information from the peripheral The ADN2813 acts as a standard slave device on the bus The data on the SDA pin is eight bits long supporting the 7 bit addresses plus the R W bit The ADN2813 has eight subaddresses to enable the user accessible internal registers see Table 6 through Table 10 It therefore interprets the first byte as the device address and the second byte as the starting subaddress Auto increment mode is supported allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without updating all registers Stop and start conditions can be detected at any stage of the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCK high period the user should issue one start condition one
23. e aw am S START BIT P STOP LACK OF ACKNOWLEDGE BY MASTER A S ACKNOWLEDGE BY SLAVE A M ACKNOWLEDGE BY MASTER Figure 9 Read Data Transfer START BIT poem SLAVE ADDRESS SUB ADDRESS DATA SLADDR A 0 SUB ADDRI6 1 DATA 6 1 Figure 10 C Data Transfer Timing EPUREL 1 tsu pat SDA SCK eet UM Baa ed 04951 0 011 Figure 11 Port Timing Diagram Rev B Page 10 of 28 04951 0 009 STOP BIT 1 1 1 ih f 9 l 1 04951 0 010 Table 6 Internal Register Map ADN2813 Reg Marie R W Address D7 D6 D5 D4 D3 D2 D1 DO FREQO R 0x0 MSB LSB FREQ1 R 0x1 MSB LSB FREQ2 R 0x2 0 MSB LSB RATE R 0x3 COARSE RD 8 MSB Coarse Data Rate Readback COARSE_RD 1 misc R x x Lon statics EOE moe Is 5 RD O LSB Status LOL Status Complete CTRA W ox8 Feer Range Data Rate DIV Fac Ratio Measure EGER Data Rate Reference de oe CTRLC W 0x11 0 0 0 0 0 Config LOS 2 Output Boost All writeable registers default to 0x00 Table 7 Miscellaneous Register MISC Data Rate Measurement Coarse Rate LOS Status Static LOL LOL Status Complete Readback LSB D7 D6 D5 D4 D3 D2 D1 DO x x 0 loss of signal 0 Waiting for next LOL 0 Locked 0 Measuring data rate x COARSE_RD 0 1 Loss of signal
24. e 07 101 4 6713e 07 149 1 3371e 08 6 5 9760e 06 54 1 7123e 07 102 4 7808e 07 150 1 3699e 08 7 6 1215e 06 55 1 7561e 07 103 4 8972e 07 151 1 4049e 08 8 6 2780e 06 56 1 8033e 07 104 5 0224e 07 152 1 4427e 08 9 6 4565e 06 57 1 8570e 07 105 5 1652e 07 153 1 4856e 08 10 6 6391e 06 58 1 9122e 07 106 5 3113e 07 154 1 5297e 08 11 6 8372e 06 59 1 9718e 07 107 5 4698e 07 155 1 5774e 08 12 7 0520e 06 60 2 0367e 07 108 5 6416e 07 156 1 6293e 08 13 7 2868e 06 61 2 1070e 07 109 5 8295e 07 157 1 6856e 08 14 7 5424e 06 62 2 1835e 07 110 6 0339e 07 158 1 7468e 08 15 7 8220e 06 63 2 2664e 07 111 6 2576e 07 159 1 8131e 08 16 7 6663e 06 64 2 1498e 07 112 6 1331e 07 160 1 7198e 08 17 7 6659e 06 65 2 1496e 07 113 6 1328e 07 161 1 7197e 08 18 7 8217e 06 66 2 1917e 07 114 6 2574e 07 162 1 7534e 08 19 7 9880e 06 67 2 2365e 07 115 6 3904e 07 163 1 7892e 08 20 8 1667e 06 68 2 2844 07 116 6 5334e407 164 1 8275e 08 21 8 3570e 06 69 2 3357e 07 117 6 6856e 07 165 1 8685e 08 22 8 5616e 06 70 2 3904e 07 118 6 8493e 07 166 1 9123e 08 23 8 7805e 06 71 2 4486e 07 119 7 0244e 07 167 1 9589e 08 24 9 0166e 06 72 2 5112e 07 120 7 2133e 07 168 2 0089e 08 25 9 2849e 06 73 2 5826e 07 121 7 4279e 07 169 2 0661e 08 26 9 5608e 06 74 2 6556e 07 122 7 6486e 07 170 2 1245e 08 27 9 8591e 06 75 2 7349e 07 123 7 8872e 07 171 2 1879e 08 28 1 0183e 07 76 2 8208e 07 124 8 1467e 07 172 2 2566e 08 29 1 0535e 07 77 2 9147e 07 125 8 4279e 07 173 2 3318e 08 30 1 0918e 07 78 3 0170e 07 126 8 7341e 07 174 2 4
25. e Reel 1 500 Pieces CP 32 2 EVAL ADN2813EBZ Evaluation Board 17 RoHS Compliant Part Rev B Page 26 of 28 ADN2813 NOTES Rev B Page 27 of 28 ADN2813 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components an system provided that the system conforms to the Standard Specification as defined by Philips 2005 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners 57 DEVICES Rev B Page 28 of 28 www analog com
26. elow a user adjustable threshold The threshold is set with a single external resistor from Pin 9 THRADJ to VEE The LOS comparator trip point vs the resistor value is illustrated in Figure 6 If the input level to the ADN2813 drops below the programmed LOS threshold the output of the LOS detector LOS Pin 22 is asserted to a Logic 1 The LOS detector s response time is 500 ns by design but is dominated by the RC time constant in ac coupled applications The LOS pin defaults to active high However by setting Bit CTRLC 2 to 1 the LOS pin is configured as active low There is typically 6 dB of electrical hysteresis designed into the LOS detector to prevent chatter on the LOS pin If the input level drops below the programmed LOS threshold causing the LOS pin to assert the LOS pin is not deasserted until the input level has increased to 6 dB 2x above the LOS threshold see Figure 19 LOS OUTPUT INPUT LEVEL ul E 9 HYSTERESIS t DolnclccectlrNEI Ilce Lun ec pEeIX4c LOS THRESHOLD 04951 0 019 Figure 19 LOS Detector Hysteresis The LOS detector and the SLICE level adjust can be used simultaneously on the ADN2813 This means that any offset added to the input signal by the SLICE adjust pins does not affect the LOS detectors measurement of the absolute input level LOCK DETECTOR OPERATION The lock detector on the ADN2813 has three mo
27. expected In this case jitter accommodation is determined by the eye opening of the input data the static phase error and the residual loop jitter generation The jitter accommodation is roughly 0 5 UI in this region The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay locked loop which is roughly 1 5 MHz at 1 25 Gb s Rev B Page 15 of 28 ADN2813 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION The ADN2813 acquires frequency from the data over a range of data frequencies from 10 Mb s to 1 25 Gb s The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data When these frequencies differ by more than 1000 ppm LOL is asserted This initiates a frequency acquisition cycle The VCO frequency is reset to the bottom of its range which is 10 MHz The frequency detector then compares this VCO frequency and the incoming data frequency and increments the VCO frequency if necessary Initially the VCO frequency is incremented in large steps to aid fast acquisi tion As the VCO frequency approaches the data frequency the step size is reduced until the VCO frequency is within 250 ppm of the data frequency at which point LOL is deasserted Once LOL is deasserted the frequency locked loop is turned off The PLL DLL pulls in the VCO frequency the rest of the way until the VCO frequency equals the data frequency The frequency loop requires a sing
28. hase loops together track the phase of the input data signal For example when the clock lags input data the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter both of these actions serve to reduce the phase error between the clock and data The faster clock picks up phase while the delayed data loses phase Because the loop filter is an integrator the static phase error is driven to zero Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second order phase locked loop and this zero is placed in the feedback path and thus does not appear in the closed loop transfer function Jitter peaking in a conventional second order phase locked loop is caused by the presence of this zero in the closed loop transfer function Because this circuit has no zero in the closed loop transfer jitter peaking is minimized The delay and phase loops together simultaneously provide wideband jitter accommodation and narrow band jitter filtering The linearized block diagram in Figure 17 shows that the jitter transfer function Z s X s is a second order low pass providing excellent filtering Note that the jitter transfer has no zero unlike an ordinary second order phase locked loop This means that the main PLL loop has virtually zero jitter peaking see Figure 18 This makes this circuit ideal for signal regen erator applications where jitter
29. he ADN2813 automatically locks onto the new data rate and the LOL pin is deasserted However the harmonic detector does not detect higher harmonics of the data rate If the input data rate switches to a higher harmonic of the data rate then the VCO is currently locked onto the VCO loses lock the LOL pin is asserted and a new frequency acquisition is initiated The ADN2813 automatically locks onto the new data rate The time to detect lock to harmonic is 2 6 x where 1 the new data rate For example if the data rate is switched from OC 12 to OC 3 then T 1 155 52 MHz p is the data transition density Most coding schemes seek to ensure that p 0 5 for example PRBS 8B 10B When the ADN2813 is placed in lock to reference mode the harmonic detector is disabled Rev B Page 17 of 28 ADN2813 SQUELCH MODE Two SQUELCH modes are available with the ADN2813 SQUELCH DATAOUT and CLKOUT mode is selected when CTRLC 1 0 default mode In this mode when the SQUELCH input Pin 27 is driven to a TTL high state both the clock and data outputs are set to the zero state to suppress downstream processing If the SQUELCH function is not required Pin 27 should be tied to VEE SQUELCH DATAOUT or CLKOUT mode is selected when CTRLC 1 is 1 In this mode when the SQUELCH input is driven to a high state the DATAOUTN DATA OUTP pins are squelched When the SQUELCH input is driven to a low state the CLKOUT
30. he data rate is and provide a reference clock that is a function of this rate The ADN2813 can still be used as a continuous rate device in this configuration provided that the user has the ability to provide a reference clock that has a variable frequency see Application Note AN 632 The reference clock can be anywhere between 10 MHz and 160 MHz By default the ADN2813 expects a reference clock of between 10 MHz and 20 MHz If it is between 20 MHz and 40 MHz 40 MHz and 80 MHz or 80 MHz and 160 MHz the user needs to configure the ADN2813 to use the correct reference frequency range by setting two bits of the CTRLA register CTRLA 7 6 Table 11 CTRLA Settings CTRLA 7 6 Range MHz CTRLA 5 2 Ratio 00 10 to 20 0000 1 01 20 to 40 0001 2 10 40 to 80 n 2 11 80 160 1000 256 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA 5 2 where CTRLA should be set to the data rate DIV_Frer where DIV_Frer represents the divided down reference referred to the 10 MHz to 20 MHz band For example if the reference clock frequency is 38 88 MHz and the input data rate is 622 08 Mb s CTRLA 7 6 is set to 01 to give a divided down reference clock of 19 44 MHz CTRLA 5 2 is set to 0101 that is 5 because 622 08 Mb s 19 44 MHz 2 In this mode if the ADN2813 loses lock for any reason it relocks onto the reference clock and continues to output a stable clock While
31. ions Information seen 21 Design Guidelines nite tte 21 DC Coupled Application see 23 Coarse Data Rate Readback Look Up 24 Outline Dimensions eub tenene denen e erdt 26 Ordering Guide nie be RD eats 26 Rev B Page 2 of 28 SPECIFICATIONS ADN2813 Ta Tmn to Tmax VCC to Vmax VEE 0 V Cr 0 47 uF SLICEP SLICEN VEE input data pattern PRBS 2 1 unless otherwise noted Table 1 Parameter Conditions Min Typ Max Unit QUANTIZER DC CHARACTERISTICS Input Voltage Range PIN or NIN dc coupled 1 8 2 8 V Peak to Peak Differential Input PIN NIN 2 0 V Input Common Mode Level DC coupled see Figure 27 Figure 28 and Figure 29 2 3 2 5 2 8 V Differential Input Sensitivity 223 1 PRBS ac coupled BER 1 x 107 6 3 3 mV p p Input Offset 500 uV Input RMS Noise BER 1 x 1071 290 uV rms QUANTIZER AC CHARACTERISTICS Data Rate 10 1250 Mb s S11 2 5 GHz 15 Input Resistance Differential 100 Input Capacitance 0 65 pF QUANTIZER SLICE ADJUSTMENT Gain SLICEP SLICEN 0 5 V 0 10 0 11 0 13 V V Differential Control Voltage Input SLICEP SLICEN 0 95 4095 V Control Voltage Range DC level SLICEP or SLICEN VEE 0 95 V Slice Threshold Offset 1 mV LOSS OF SIGNAL LOS DETECT Loss of Signal Detect Range see Figure 6 RruresH 0 14 165 19 mV 100 23 3 5 4 7
32. k Input 21 SDA DI Data Input 22 LOS DO Loss of Signal Detect Output Active high LVTTL 23 VEE P Output Buffer 2 GND 24 VCC P Output Buffer I C Power 25 CLKOUTN DO Differential Recovered Clock Output LVDS 26 CLKOUTP DO Differential Recovered Clock Output LVDS 27 SQUELCH DI Disable Clock and Data Outputs Active high LVTTL 28 DATAOUTN DO Differential Recovered Data Output LVDS 29 DATAOUTP DO Differential Recovered Data Output LVDS 30 VEE P Phase Detector Phase Shifter GND 31 VCC P Phase Detector Phase Shifter Power 32 VCC Al Connect to VCC Exposed Pad Pad P Connect to GND Works as a heat sink 1 Type P power Al analog input AO analog output DI digital input DO digital output Rev B Page 8 of 28 ADN2813 TYPICAL PERFORMANCE CHARACTERISTICS TRIP POINT mV p p 04951 0 005 Figure 6 LOS Comparator Trip Point Programming Rev B Page 9 of 28 ADN2813 26 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION SLAVE ADDRESS 6 0 CTRL MSB 1 PTS 0 wr E Figure 7 Slave Address Configuration 04951 0 008 S SUAVE ADDR css o WA ADDR AS Figure 8 Write Data Transfer 5 SLAVE ADDR LSB 0 WR ADDR LSB SLAVE ADDR LSB 0 WR SUB ADDR 5 5 SLAVE ADDR LSB 1 RD SLAVE ADDR LSB 1 RD ADDR LSB 1 RD DATA A M ee
33. le external capacitor between CF1 and CF2 Pin 14 and Pin 15 A 0 47 uF 20 X7R ceramic chip capacitor with 10 nA leakage current is recommended Leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0 47 capacitor 3 V by the insulation resistance of the capacitor The insulation resistance of the 0 47 uF capacitor should be greater than 300 MQ LIMITING AMPLIFIER The limiting amplifier has differential inputs PIN NIN which are internally terminated with 50 to an on chip voltage reference VREF 2 5 V typically The inputs are typically ac coupled externally although dc coupling is possible as long as the input common mode voltage remains above 2 5 V see Figure 27 to Figure 29 in the Applications Information section Input offset is factory trimmed to achieve better than 3 3 mV typical sensitivity with minimal drift The limiting amplifier can be driven differentially or single ended SLICE ADJUST The quantizer slicing level can be offset by 100 mV to mitigate the effect of amplified spontaneous emission ASE noise or duty cycle distortion by applying a differential voltage input of up to 0 95 V to SLICEP SLICEN inputs If no adjustment of the slice level is needed SLICEP SLICEN should be tied to VEE The gain of the slice adjustment is 0 11 V V LOSS OF SIGNAL LOS DETECTOR The receiver front end LOS detector circuit detects when the input signal level has fallen b
34. mV Hysteresis Electrical GbE RturesH 0 6 4 7 2 8 0 dB Rrunesa 100 4 6 6 2 7 8 dB OC 1 RturesH 0 5 5 6 6 7 7 dB 10 3 1 54 74 dB LOS Assert Time DC coupled 500 ns LOS Deassert Time DC coupled 400 ns LOSS OF LOCK LOL DETECT VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time 10 Mb s 5 ms OC 12 200 us GbE 200 us ACQUISITION TIME Lock to Data Mode GbE 1 5 ms OC 12 2 0 ms OC 3 34 ms OC 1 9 8 ms 10 Mb s 40 0 ms Optional Lock to REFCLK Mode 20 0 ms DATA RATE READBACK ACCURACY Coarse Readback See Table 13 10 96 Fine Readback In addition to REFCLK accuracy Data rate lt 20 Mb s 200 ppm Data rate gt 20 Mb s 100 ppm Rev B Page 3 of 28 ADN2813 Parameter Conditions Min Typ Max Unit POWER SUPPLY VOLTAGE 3 0 3 3 3 6 V POWER SUPPLY CURRENT Locked to 1 25 Gb s 139 155 mA OPERATING TEMPERATURE RANGE 40 85 eG PIN and NIN should be differentially driven and ac coupled for optimum sensitivity When ac coupled the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 O input termination of the ADN2813 input stage JITTER SPECIFICATIONS Ta Tuis to Tmax VCC to Vmax VEE 0 V Cr 0 47 uF SLICEP SLICEN VEE input data pattern PRBS 2 1 unless otherwise noted Table 2 P
35. ns zoe tte 4 Output and Timing Specifications sss 5 Absolute Maximum Ratings seen 6 Thermal Characteristics seen 6 ESD Ca tiori nei 6 Timing tentent iere aiina 7 Pin Configuration and Function 8 Typical Performance Characteristics sse 9 Interface Timing and Internal Register Description 10 Terminology eei ene ne aUe 12 Jitter 5 22 2444 entente 13 REVISION HISTORY 6 10 Rev A to Rev B Changes to Figure 5 and Table 5 sss 8 Changes to Figure 24 eie erm ee nemen 21 Updated Outline Dimensions seen 26 2 09 Rev 0 to Rev A Updated Outline Dimensions sese 26 Changes to Ordering Guide 9 05 Revision 0 Initial Version Theory of Operation e REA 14 Functional Description eerte 16 Frequency Acquisition eee 16 Limiting Amplifier eene 16 Slice s oer ere Ret rotta 16 Loss of Signal LOS Detector see 16 Lock Detector Operation seen 16 Harmonic Detector 2 2 17 SQUEL CH 18 TG Interface MIENNE 18 Reference Clock Optional sse 18 Applicat
36. nse time Rev B Page 12 of 28 JITTER SPECIFICATIONS The ADN2813 CDR is designed to achieve the best bit error rate BER performance and to exceed the jitter transfer generation and tolerance specifications proposed for SONET SDH equipment defined in the Telcordia Technologies specification Jitter is the dynamic displacement of digital signal edges from their long term average positions measured in unit intervals UL where 1 UI 1 bit period Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge Jitter on the recovered clock causes jitter on the retimed data The following sections briefly summarize the specifications of jitter generation transfer and tolerance in accordance with the Telcordia document GR 253 CORE Issue 3 September 2000 for the optical interface at the equipment level and the ADN2813 performance with respect to those specifications Jitter Generation The jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input For SONET devices the jitter generated must be less than 0 01 UI rms and must be less than 0 1 UI p p Jitter Transfer The jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal vs the frequency This parameter measures the limited amount of the jitter on an input signal that can be transferred to the outpu
37. nt jitter allowed lt 0 01 UI p p typical t is the rise time which is equal to 0 22 BW where BW 0 7 bit rate Note that this expression for f is accurate only for the inputs The output rise time for the ADN2813 is 100 ps regardless of data rate Rev B Page 22 of 28 vcc X vi Cm PIN Vib CiN V2b ADN2813 ADN2813 Cour 90 DATAOUTP 90 DATAOUTN Cour VTH ADN2813 QUANTIZER THRESHOLD NOTES 1 DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO 2 WHEN THE OUTPUT OF THE TIA GOES CID V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS V2 AND V2b DISCHARGE TO THE VREF LEVEL WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS 3 WHEN THE BURST OF DATA STARTS AGAIN THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID IS CANCELED OUT THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE 4 THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2813 THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT 04951 0 027 Figure 26 Example of Baseline Wander DC COUPLED APPLICATION The inputs to the ADN2813 can
38. of the quantizer and the analog voltage input is shown in Figure 12 For sufficiently large positive input voltage the output is always Logic 1 and similarly for negative inputs the output is always Logic 0 However the transitions between output Logic 1 and output Logic 0 are not at precisely defined input voltage levels but occur over a range of input voltages Within this range of input voltages the output may be either 1 or 0 or it may even fail to attain a valid logic state The width of this zone is determined by the input voltage noise of the quantizer The center of the zone is the quantizer input offset voltage Input overdrive is the magnitude of signal required to guarantee the correct logic level with 1 x 1079 confidence level OUTPUT NOISE gt OFFSET INPUT V p p OVERDRIVE 1 1 1 1 1 1 1 1 SENSITIVITY 2x OVERDRIVE 04951 0 012 Figure 12 Input Sensitivity and Input Overdrive Single Ended vs Differential AC coupling is typically used to drive the inputs to the quantizer The inputs are internally dc biased to a common mode potential of 2 5 V Driving the ADN2813 single ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 13 shows a binary signal with an average value equal to the common mode potential and instantaneous values both above and below the average value It is convenient to measure the peak to peak am
39. ondition occurs ADN2813 Writing a 1 to C Register Bit CTRLB 7 causes the LOL pin Pin 16 to become a static LOL indicator In this mode the LOL pin mirrors the contents of the MISC 4 bit and has the functionality described in the previous paragraph The CTRLB 7 bit defaults to 0 In this mode the LOL pin operates in the normal operating mode that is it is asserted only when the ADN2813 is in acquisition mode and deasserts when the ADN2813 has reacquired lock HARMONIC DETECTOR The ADN2813 provides a harmonic detector which detects whether or not the input data has changed to a lower harmonic of the data rate that the VCO is currently locked onto For example if the input data instantaneously changes from OC 12 622 08 Mb s to an OC 3 155 52 Mb s bit stream this could be perceived as a valid OC 12 bit stream because the OC 3 data pattern is exactly 4x slower than the OC 12 pattern Therefore if the change in data rate is instantaneous a 101 pattern at OC 3 would be perceived by the ADN2813 as a 111100001111 pattern at OC 12 If the change to a lower harmonic is instantaneous a typical CDR could remain locked at the higher data rate The ADN2813 implements a harmonic detector that automati cally identifies whether or not the input data has switched to a lower harmonic of the data rate that the VCO is currently locked onto When a harmonic is identified the LOL pin is asserted and a new frequency acquisition is initiated T
40. peaking in a cascade of regenerators can contribute to hazardous jitter accumulation The error transfer e s X s has the same high pass form as an ordinary phase locked loop This transfer function is free to be optimized to give excellent wideband jitter accommodation because the jitter transfer function Z s X s provides the narrow band jitter filtering INPUT DATA gt gt Z s RECOVERED CLOCK d PHASE DETECTOR GAIN JITTER TRANSFER FUNCTION o VCO GAIN c LOOP INTEGRATOR Z s 1 psh PHASE X s _ n DIVIDE RATIO 2 8 1 TRACKING ERROR TRANSFER FUNCTION es 2 2 X 2 d psh do c cn 04951 0 017 Figure 17 ADN2813 PLL DLL Architecture JITTER PEAKING IN ORDINARY PLL a kJ z lt B ADN2813 Z s 5 N X9 d psh n psh C FREQUENCY kHz Figure 18 ADN2813 Jitter Response vs Conventional PLL 04951 0 018 The delay and phase loops contribute to overall jitter accom modation At low frequencies of input jitter on the data signal the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error In this case the VCO is frequency modulated and jitter is tracked as in an ordinary phase locked loop The amount of low frequency jitter that can be tracked is a function of the VCO tuning range A wider tuning range gives larger accommodation of low frequency jitter The internal loop
41. pins are squelched This is especially useful in repeater applications where the recovered clock may not be needed PC INTERFACE The ADN2813 supports a 2 wire C compatible serial bus driving multiple peripherals Two inputs serial data SDA and serial clock SCK carry information between any devices connected to the bus Each slave device is recognized by a unique address The ADN2813 has two possible 7 bit slave addresses for both read and write operations The MSB ofthe 7 bit slave address is factory programmed to 1 B5 of the slave address is set by Pin 19 SADDRS5 Slave Address Bits 4 0 are defaulted to all 0s The slave address consists of the 7 MSBs of an 8 bit word The LSB of the word either sets a read or write operation see Figure 7 Logic 1 corresponds to a read operation while Logic 0 corresponds to a write operation To control the device on the bus the following protocol must be followed First the master initiates a data transfer by establish ing a start condition defined by a high to low transition on SDA while SCK remains high This indicates that an address data stream follows All peripherals respond to the start condition and shift the next eight bits the 7 bit address and the R W bit The bits are transferred from MSB to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse This is known as an acknowledge bit All other devices with
42. plitude of this signal and call the minimum required value the quantizer sensitivity Referring to Figure 13 because both positive and negative offsets need to be accommodated the sensitivity is twice the overdrive The ADN2813 quantizer typically has 3 3 mV p p sensitivity 10 4 4 VREF ADN2813 O 2 5V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 04951 0 013 y Figure 13 Single Ended Sensitivity Measurement Driving the ADN2813 differentially see Figure 14 sensitivity seems to improve from observing the quantizer input with an oscilloscope probe This is an illusion caused by the use ofa single ended probe A 5 mV p p signal appears to drive the ADN2813 quantizer However the single ended probe measures only half the signal The true quantizer input signal is twice this value because the other quantizer input is a complementary signal to the signal being observed O 2 5V 3ko 04951 0 014 Figure 14 Differential Sensitivity Measurement LOS Response Time LOS response time is the delay between removal of the input signal and indication of loss of signal LOS at the LOS output Pin 22 When the inputs are dc coupled the LOS assert time of the ADN2813 is 500 ns typical and the deassert time is 400 ns typical In practice the time constant produced by the ac coupling at the quantizer input and the 50 on chip input termination determines the LOS respo
43. t A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I C Register Bit CTRLB 5 This initiates a new frequency acquisition while keeping the ADN2813 in the operating mode that it was previously programmed to in Registers CTRL A CTRL B and CTRL C D22 D21 D17 D16 D15 D14 D9 D8 D7 D6 D1 DO FREQ2 6 0 FREQ1 7 0 FREQO 7 0 Rev B Page 20 of 28 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended The VEE pins should be soldered directly to the ground plane to reduce series inductance If the ground plane is an internal plane and connections to the ground plane are made through vias multiple vias can be used in parallel to reduce the series inductance especially on Pin 23 which is the ground return for the output buffers The exposed pad should be connected to the GND plane using plugged vias so that solder does not leak through the vias during reflow Use of a 22 uF electrolytic capacitor between VCC and VEE is recommended at the location where the 3 3 V supply enters the PCB When using 0 1 and 1 nF ceramic chip capacitors they should be placed between the IC power supply VCC and VEE as close as possible to the ADN2813 VCC pins vcc ad XPOSED PAD 23 ADN2813 If
44. t signal see Figure 15 ADN2813 SLOPE 20dB DECADE ACCEPTABLE RANGE JITTER GAIN dB fc JITTER FREQUENCY kHz 04951 0 015 Figure 15 Jitter Transfer Curve Jitter Tolerance The jitter tolerance is defined as the peak to peak amplitude of the sinusoidal jitter applied on the input signal which causes a 1 dB power penalty This is a stress test intended to ensure that no additional penalty is incurred under the operating conditions see Figure 16 15 00 SLOPE 20dB DECADE d 1 50 0 15 INPUT JITTER AMPLITUDE UI p p fo h f2 f fy JITTER FREQUENCY kHz Figure 16 SONET Jitter Tolerance Mask 04951 0 016 Rev B Page 13 of 28 ADN2813 THEORY OF OPERATION The ADN2813 is a delay and phase locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage A high speed delay locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter A separate phase control loop comprised of the VCO tracks the low frequency components of input jitter The initial frequency of the VCO is set by yet a third loop which compares the VCO frequency with the input data frequency and sets the coarse tuning voltage The jitter tracking phase locked loop controls the VCO by the fine tuning control The delay and p
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ANALOG DEVICES ADN2813 Manual3