ANALOG DEVICES AD8318 English products handbook Rev B
Contents
1. 10k RF OFF F x 2 gt tk 7 60dBm 40dBm F 20dBm 5 li 100 o Er 10dBm g 0dBm a 10 FREQUENCY kHz Figure 19 Noise Spectral Density of Output CLPF 2 Open 1k N z 2 E D z a j 100 E O ul n o ul e o z o 10 1 3 10 30 100 300 1k 3k 10k FREQUENCY kHz Figure 20 Noise Spectral Density of Output Buffer from CLPF to VOUT Vour V CLPF 0 1 uF Pin dBm Figure 21 Output Voltage Stability vs Supply Voltage at 1 9 GHz When VP Varies by 10 Multiple Devices Rev B Page 10 of 24 ERROR dB 04853 020 THEORY OF OPERATION The AD8318 is a 9 stage demodulating logarithmic amplifier that provides RF measurement and power amplifier control functions The design of the AD8318 is similar to the AD8313 logarithmic detector controller However the AD8318 input frequency range extends to 8 GHz with a 60 dB dynamic range Other improvements include reduced intercept variability vs temperature increased dynamic range at higher frequencies low noise measurement and controller output VOUT adjustable low pass corner frequency CLPF temperature sensor output TEMP negative transfer function slope for higher accuracy and 10 ns respo2. ses 18 Output Filtering nesini iE 18 Controller Mode citer tpi te ti ter NERES 19 Characterization Setup and Methods 21 Evaluation Board tte ette eb RD 22 Outline Dimensions esee tette tenens 24 Ordering Guide 1 eterne 24 Changed General Description Heading to Th ory of Operation certi i 11 Changes to Enable Interface Section sss 12 Inserted Figure 24 1o o LEE ueteri eed 12 Changes to Input Signal Coupling Section 12 Changes to Measurement Mode Section sss 14 Changes to Figure 36 sse R S si 17 Added Output Filtering Section 19 Changes to Controller Mode Section pe be Changes to Response Time Capability Section 18 Changes to Table G reii reete e ete ertt 22 Changes to Figure 47 Figure 48 and Figure 49 23 Updated Outline Dimensions sete 24 Changes to Ordering Guide sse 24 7 04 Rev 0 Initial Version Rev B Page 2 of 24 AD8318 SPECIFICATIONS Vros 5 V Curr 220 pF Ta 25 C 52 3 Q termination resistor at INHI unless otherwise noted Table 1 Parameter Conditions Min Typ Max Unit SIGNAL INPUT INTERFACE INHI Pin 14 and INLO Pin 15 Specified Frequency Range 0 001 8 GHz DC Common Mode Voltage Vros 1 8 V MEASUREMENT MODE VOUT Pin 6 shorted to VSET Pin 7 sinusoidal inp
3. 45 35 25 15 5 5 15 Pix dBm Pin dBm Figure 11 Distribution of Error at Temperature After Ambient Figure 14 Distribution of Error at Temperature After Ambient Normalization vs Input Amplitude at 1900 MHz for at Least 70 Devices Normalization vs Input Amplitude at 5 8 GHz for at Least 70 Devices Rrap 1000 Q 2 0 4 5 1 6 3 6 1 2 j 2 7 0 8 1 9 Tm 0 4 m 09 z k cr o0 x o0 E 04 uj 0 9 0 8 1 8 1 2 2 7 1 6 5 3 6 gt 2 0 8 4 5 65 55 45 35 25 15 5 5 15 65 55 45 35 25 15 5 5 Pix dBm Pin dBm Figure 12 Distribution of Error at Temperature After Ambient Figure 15 Distribution of Error at Temperature After Ambient Normalization vs Input Amplitude at 2 2 GHz for at Least 70 Devices Normalization vs Input Amplitude at 8 GHz for at Least 70 Devices Rev B Page 9 of 24 AD8318 START FREQUENCY 0 1GHz STOP FREQUENCY 8GHz j1 Figure 16 Input Impedance vs Frequency No Termination Resistor INHI Zo 50 w 5 h 8 o SUPPLY CURRENT A o Dx Vea V Figure 17 Supply Current vs Enable Voltage 200mV VERTICAL DIVISION i LI T f SYA WAAAY ee Sees eee eee eee eee eee HH E PULSED RF INPUT 0 1GHz Li 10dBm A Nf MAN NyvVvy 20ns PER HORIZONTAL DIVISION Figure 18 VOUT Pulse Response Time Pulsed RF Input 0 1 GHz 10 dBm CLPF Open n 04853 016 04853 017
4. The AD8318 provides 0 V to 4 9 V output capability at the VOUT pin suitable for controller applications As a measurement device Pin VOUT is externally connected to VSET to produce an output voltage Vour which is a decreasing linear in dB function of the RF input signal amplitude The logarithmic slope is nominally 25 mV dB but can be adjusted by scaling the feedback voltage from VOUT to the VSET interface The intercept is 20 dBm re 50 O CW input using the INHI input These parameters are very stable against supply and temperature variations The AD8318 is fabricated on a SiGe bipolar IC process and is available in a 4 mm x 4 mm 16 lead LFCSP for the operating temperature range of 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2004 2007 Analog Devices Inc All rights reserved AD8318 TABLE OF CONTENTS F atu tes 5o RE EH ERE ERES 1 Applicaton Snia E R 1 General Description iinei a 1 Functional Block Diagram sse 1 REVISION ISL ORY oea r R ee eee Bee tee sete Oe 2 Specifications sese pe tae tier D io MEN Rec iste ees 3 Absolute Maximum Ratings eene 6 ESD Ca tion en ene HG Oe e tenerent 6 Pin Configuration and Function Descriptions s 7 Typical Performance Characteristics sss 8 Theory of Operation iet ttes 11 Using the AD8318 i ies ee terc 12 Basic C
5. resolution bandwidth of 50 Hz video bandwidth of 50 Hz and averages the signal 100x Data is adjusted to account for the dc blocking capacitor impedance on the output at lower frequencies TEKTRONIX TDS5104 CH1 CH3 TRIGGER O O O ie TERMINATION VSET 04853 046 Figure 47 Pulse Response Measurement Test Setup Rev B Page 21 of 24 AD8318 EVALUATION BOARD Table 6 Evaluation Board Rev A Bill of Materials Component Function Default Conditions VP GND Supply and Ground Connections Not Applicable SW1 R3 Device Enable When in Position A the ENBL pin is connected to VP and the SW1 A AD8318 is in operating mode In Position B the ENBL pin is grounded through R3 10 KQ Size 0603 R3 putting the device in power down mode The ENBL pin may be exercised by a pulse generator connected to ENBL SMA and SW1 in Position B R1 C1 C2 Input Interface The 52 3 Q resistor R1 combines with the AD8318 internal R1 52 3 Q Size 0402 input impedance to give a broadband input impedance of 50 Q C1 and C2are C1 1 nF Size 0402 dc blocking capacitors A reactive impedance match can be implemented by C2 1 nF Size 0402 replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors R2 Temperature Sensor Interface The temperature sensor output voltage is R2 1 kQ Size 0402 available at the SMA labeled TEMP via the current limiting resistor R2 R4 Temperature Compe
6. the new output voltage range cannot exceed the output voltage swing capability of the output stage Refer to the Measurement Mode section for further details AD8318 04853 033 Figure 38 Increasing the Slope Rev B Page 17 of 24 AD8318 PULSED RF INPUT Vggr 1 8V 1 2V ADCMP563 O COMPARATOR OUTPUT 04853 040 5 2V Figure 39 AD8318 Operating with the High Speed ADCMP563 Comparator RESPONSE TIME CAPABILITY The AD8318 has a 10 ns rise fall time capability 10 to 90 for input power switching between the noise floor and 0 dBm This capability enables RF burst measurements at repetition rates beyond 45 MHz In most measurement applications the AD8318 has an external capacitor connected to CLPF to provide additional filtering for VOUT However using the CLPF capacitor slows the response time as does stray capacitance on VOUT For an application requiring maximum RF burst detection capability the CLPF pin is left unconnected In this case the integration function is provided by the 1 5 pF on chip capacitor There is a 10 Q internal resistor in series with the output driver Because of this resistor it is necessary to add an external 40 Q back terminating resistor in series with the output when driving a 50 Q load Place the back terminating resistor close to the VOUT pin The AD8318 has the drive capability to drive a 50 Q load at the end of a coaxial cable or transmission line when back terminat
7. 2 239 Vrms for a sinusoidal input signal The slope of the transfer function can be increased to accommodate various converter mV per dB LSB per dB requirements However increasing the slope can reduce the dynamic range This is due to the limitation of the minimum and maximum output voltages determined by the chosen scaling factor X The minimum value for Vour is X x Vorrser The offset voltage Vorrser is equal to 0 5 V and is internally added to the detector output signal Vovraum X x Vorrser 5 Rev B Page 14 of 24 The maximum output voltage is 2 1 V x X and cannot exceed 400 mV below the positive supply Vourmax 2 1 V x X when X lt Vros 400 mV 2 1 V 6 Vourimax Vros 400 mV when X 2 Vros 400 mV 2 1 V 7 When X 1 the typical output voltage swing is 0 5 V to 2 1 V The output voltage swing is modeled using Equation 5 to Equation 7 and restricted by Equation 8 Vout Vovr Vourmax 8 When X 4 and Vros 5 V X x Vorrser lt Vour lt Vros 400 mV 4 x 0 5 V Vour lt 2 1 V x 4 2 V lt Vovr 4 6 V For X 4 slope 100 mV dB Vour can swing 2 6 V and the usable dynamic range is reduced to 26 dB from 0 dBm to 26 dBm The slope is very stable vs process and temperature variation When base 10 logarithms are used Vstorepecape represents the output voltage per decade of input power One decade is equal to 20 dB Vstorgsc 20 Vsrorzas represents the
8. 45 dB control range is constant for the range of Vser voltages The input power levels to the AD8367 must be optimized to achieve this range In Figure 46 the minimum and maximum input power levels are shown vs setpoint voltage Piy dBm 0 5 0 6 1 1 5 pu s Figure 46 Setpoint Voltage vs Input Power Optimal signal levels must be used to achieve the full 45 dB dynamic range capabilities of the AD8367 04853 049 In some cases if Vaam is gt 1 0 V it can take an unusually long time for the AGC loop to recover that is the output of the AD8318 remains at an abnormally high value and the gain is set to its maximum level A voltage divider is placed between the output of the AD8318 and the AD8367 GAIN pin to ensure that Vcaw does not exceed 1 0 V In Figure 43 Cup and Rup are configured to reduce oscillation and distortion due to harmonics at higher gain settings Some additional filtering is recommended between the output of the AD8367 and the input of the AD8318 This helps to decrease the output noise of the AD8367 which can reduce the dynamic range of the loop at higher gain settings smaller Vser Response time and the amount of signal integration are controlled by Cu This functionality is analogous to the feedback capacitor around an integrating amplifier Though it is possible to use large capacitors for Carr in most applications values under 1 nF provide sufficient filtering Calibration i
9. is shown in Figure 32 The figure shows plots of both output voltage vs input power and calculated log conformance error vs input power As the input power varies from 65 dBm to 0 dBm the output voltage varies from 2 V to about 0 5 V Vour 25 C VOUT peat SLOPE x Piy INTERCEPT ao Rod SLOPE Vour1 Vour2 Piwi Pina ERROR 425 C INTERCEPT Pi Vouri SLOPE ERROR ane ERROR dB Vout VOUTipgA SLOPE ERROR 485 C 2 Vour2 RS a kJ 5 S gt ul Vouri 0 2 3 65 60 55 45 40 35 30 25 20 15 5 0 5 s PiN2 Pin dBm Pina INTERCEPT Figure 32 Transfer Function at 2 2 GHz Because the slope and intercept vary from device to device board level calibration is performed to achieve high accuracy The equation can be rewritten for output voltage from the Measurement Mode section using an intercept expressed in dBm Vour Slope x Pw Intercept 14 In general the calibration is performed by applying two known signal levels to the AD8318 input and measuring the corre sponding output voltages The calibration points are generally chosen to be within the linear in dB operating range of the device see Figure 32 Calculation of the slope and intercept is done by Slope Vouri Vovr2 Pii P2 15 Intercept Pii VovrilSlope 16 Once the slope and intercept are calculated an equation can be written to allow calculat
10. output voltage slope in V dB As noted in Equation 3 the Vour voltage has a negative slope This is the correct slope polarity to control the gain of many power amplifiers and other VGAs in a negative feedback configuration Because both the slope and intercept vary slightly with frequency refer to Table 1 for application specific values for the slope and intercept Although demodulating log amps respond to input signal voltage not input signal power it is customary to discuss the amplitude of high frequency signals in terms of power In this case the characteristic impedance of the system Zo must be known to convert voltages to corresponding power levels Beginning with the definitions of dBm and dBV P dBm 10 x logio Vims Zo x 1 mW 9 V dBV 20 x logio Vims 1 Vims 10 When Equation 9 is expanded P dBm 20 x logi Vms 10 x logio Zo x 1 mW 11 and given Equation 10 Equation 11 can be rewritten as P dBm V dBV 10 x logio Zo x 1 mW 12 For example Pivtercerr for a sinusoidal input signal expressed in terms of dBm decibels referred to 1 mW in a 50 O system is Pintercerr dBm Vinrercerr ABV 10 x logio Zo x 1 mW 13 7 dBV 10 x logio 50 x 10 20 dBm AD8318 For further information on the intercept variation dependence upon waveform refer to the AD8313 and AD8307 data sheets DEVICE CALIBRATION AND ERROR CALCULATION The measured transfer function of the AD8318 at 2 2 GHz
11. the gain is stabilized over temperature and supply variations Because the cascaded gain stages are dc coupled the overall dc gain is high An offset compensation loop is included to correct for offsets within the cascaded cells At the output of each of the gain stages a square law detector cell rectifies the signal The RF signal voltages are converted to a fluctuating differential current with an average value that increases with signal level Along with the nine gain stages and detector cells an additional detector is included at the input of the AD8318 altogether providing a 60 dB dynamic range After the detector currents are summed and filtered the function Ip x logio Vi Vintercerr 1 is formed at the summing node where Ipis the internally set detector current Vin is the input signal voltage Vinrercerr is the intercept voltage that is when Vin Vivrercepr the output voltage would be 0 V if capable of going to 0 V Rev B Page 11 of 24 AD8318 USING THE AD8318 BASIC CONNECTIONS The AD8318 is specified for operation up to 8 GHz As a result low impedance supply pins with adequate isolation between functions are essential In the AD8318 VPSI and VPSO the two positive supply pins must be connected to the same positive potential The VPSI pin biases the input circuitry while the VPSO pin biases the low noise output driver for VOUT Separate commons are also included in the device CMOP is used as the commo
12. 10 mA results in the voltage on the temperature sensor to increase by 1 5 C or 3 mV Best precision from the temperature sensor is obtained when the supply current to AD8318 remains fairly constant that is no heavy load drive MEASUREMENT MODE When the VOUT voltage or a portion of the VOUT voltage is fed back to VSET the device operates in measurement mode As shown in Figure 31 the AD8318 has an offset voltage a negative slope and a VOUT measurement intercept greater than its input signal range 24 2 0 Voyr 25 C ork ERROR 25 C E 1 8 1 0 1 5 05 a z 3 5 12 o E gt La 0 9 05 RANGE OF 0 6 L CALCULATION 1 0 1 OF SLOPE AND INTERCEPT EN 0 3 15 g 0 65 60 55 50 45 40 35 30 25 20 15 10 5 0 5 10 15 Pin dBm INTERCEPT Figure 31 Typical Output Voltage vs Input Signal The output voltage vs input signal voltage of the AD8318 is linear in dB over a multidecade range The equation for this function is Vour X x Vsiorzpzc X logio Viv Vintercerr 3 X x Vsyorgas X 20 x logio Viv Vintercerr 4 where X is the feedback factor in Vser Vour X Vinrercerr is expressed in Vims Vs ore pecis nominally 500 mV decade and Vszopsvas is nominally 25 mV dB Vinrercerr expressed in dBV is the x axis intercept of the linear in dB transfer function shown in Figure 31 Vintercert is 7 dBV 20 dBm re 50 Q or
13. 8 1 8 0 6 1 2 0 6 2 7 0 4 1 6 8 0 4 3 6 8 0 2 2 0 3 0 2 45 6 65 55 45 35 25 15 5 5 15 65 55 45 35 25 15 5 5 Pix dBm Pin dBm Figure 6 Vour and Log Conformance vs Input Amplitude at 2 2 GHz Figure 9 Vour and Log Conformance vs Input Amplitude at 8 GHz Typical Device Typical Device Rev B Page 8 of 24 AD8318 2 0 1 6 12 0 8 T 04 a iJ kJ o x W 0 4 W 0 8 1 2 1 6 3 z 2 0 3 3 65 55 45 35 25 15 5 5 15 65 55 45 35 25 15 5 5 15 Pix dBm Pin dBm Figure 10 Distribution of Error over Temperature After Ambient Figure 13 Distribution of Error at Temperature After Ambient Normalization vs Input Amplitude at 900 MHz for at Least 70 Devices Normalization vs Input Amplitude at 3 6 GHz for at Least 70 Devices Rrap 51 Q 2 0 1 6 12 0 8 m 0 4 T kJ kJ x x E S 0 4 0 8 1 2 1 6 5 z 2 0 3 3 65 55
14. 84 V Output Voltage Low Power In Pin 35 dBm 1 2 1 34 1 5 V Temperature Sensitivity Pn 10 dBm 25 C lt Ta lt 85 C 0 0005 dB C 40 C lt Ta lt 25 C 0 0062 dB C Rev B Page 3 of 24 AD8318 Parameter Conditions Min Typ Max Unit f 3 6 GHz Rmo 2510 Input Impedance 119 0 7 Q pF 3 dB Dynamic Range Ta 25 C 70 dB 1 dB Dynamic Range Ta 25 C 58 dB 40 C lt Ta lt 85 C 42 dB Maximum Input Level 1 dB error 2 dBm Minimum Input Level 1 dB error 60 dBm Slope 24 3 mV dB Intercept 19 8 dBm Output Voltage High Power In Pn 10 dBm 0 717 V Output Voltage Low Power In Pin 40 dBm 1 46 V Temperature Sensitivity Pn 10 dBm 25 C lt Ta lt 85 C 0 0022 dB C 40 C lt Ta lt 25 C 0 004 dB C f 5 8 GHz Rraps 1000 Q Input Impedance 33 0 59 Q pF 3 dB Dynamic Range Ta 25 C 70 dB 1 dB Dynamic Range Ta 25 C 57 dB 40 C lt Ta lt 85 C 48 dB Maximum Input Level 1 dB error 1 dBm Minimum Input Level 1 dB error 58 dBm Slope 24 3 mV dB Intercept 25 dBm Output Voltage High Power In Pn 10 dBm 0 86 V Output Voltage Low Power In Pin 40 dBm 1 59 V Temperature Sensitivity Pn 10 dBm 25 C lt Ta lt 85 C 0 0033 dB C 40 C lt Ta lt 25 C 0 0069 dB C f 8 0 GHz Rraps 500 Q 3 dB Dynamic Range Ta 25 C 60 dB 40 C lt Ta lt 85 C 58 dB Maximum Input Level 3 dB error 3 dBm Minim
15. ANALOG DEVICES 1 MHz to 8 GHz 70 dB Logarithmic Detector Controller AD8318 FEATURES Wide bandwidth 1 MHz to 8 GHz High accuracy 1 0 dB over 55 dB range f lt 5 8 GHz Stability over temperature 0 5 dB Low noise measurement controller output VOUT Pulse response time 10 ns 12 ns fall rise Integrated temperature sensor Small footprint LFCSP Power down feature 1 5 mW at 5 V Single supply operation 5 V 68 mA Fabricated using high speed SiGe process APPLICATIONS RF transmitter PA setpoint control and level monitoring RSSI measurement in base stations WLAN WiMAX and radars GENERAL DESCRIPTION The AD8318 is a demodulating logarithmic amplifier capable of accurately converting an RF input signal to a corresponding decibel scaled output voltage It employs the progressive compression technique over a cascaded amplifier chain each stage of which is equipped with a detector cell The device is used in measurement or controller mode The AD8318 maintains accurate log conformance for signals of 1 MHz to 6 GHz and provides useful operation to 8 GHz The input range is typically 60 dB re 50 Q with error less than 1 dB The AD8318 has a 10 ns response time that enables RF burst detection to beyond 45 MHz The device provides unprece dented logarithmic intercept stability vs ambient temperature conditions A 2 mV C slope temperature sensor output is also provided for additional system monitoring A singl
16. cing 15 uA POWER INTERFACE VPSI Pin 3 and Pin 4 VPSO Pin 9 Supply Voltage 4 5 5 5 5 V Quiescent Current ENBL 25V 50 68 82 mA vs Temperature 40 C lt Ta x 85 C 150 pA PC Supply Current when Disabled ENBL OV total currents for VPSI and VPSO 260 uA vs Temperature 40 C lt Ta lt 85 C 350 uA 1 Controller mode Gain 1 For other gains see the Measurement Mode section Rev B Page 5 of 24 AD8318 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress Table 2 Parameter Rating Supply Voltage Pin VPSO Pin VPSI 5 7V ENBL Vser Voltage 0 to Vros Input Power Single Ended re 50 Q 12 dBm Internal Power Dissipation 0 73W Oya 55 C W Maximum Junction Temperature 125 C Operating Temperature Range 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature 260 C rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device With package die paddle soldered to thermal pads with vias connecting to inner and bottom layers Charged devices and circuit boards can discharge without detection Although this p
17. e broadband 50 match Table 4 Input Impedance for Select Frequency Frequency S11 Impedance Q MHz Real Imaginary Series 100 40 918 0 041 927 j491 450 40 905 0 183 173 j430 900 10 834 0 350 61 j233 1900 40 605 0 595 28 j117 2200 0 524 0 616 28 j102 3600 40 070 0 601 26 j49 5300 0 369 0 305 20 j16 5800 0 326 0 286 22 j16 8000 0 390 0 062 22 j3 The coupling time constant 50 x Cc 2 forms a high pass corner with a 3 dB attenuation at fu 1 27 x 50 x Cc where C1 C2 Cc Using the typical value of 1 nF this high pass corner is 3 2 MHz In high frequency applications fur should be as large as possible to minimize the coupling of unwanted low frequency signals Likewise in low frequency applications a simple RC network forming a low pass filter should be added generally placed at the generator side of the coupling capacitors thereby lowering the required capacitance value for a given high pass corner frequency OUTPUT INTERFACE The logarithmic output interface is shown in Figure 27 The VOUT pin is driven by a PNP output stage An internal 10 Q resistor is placed in series with the emitter follower output and the VOUT pin The rise time of the output is limited mainly by the slew on CLPF The fall time is an RC limited slew provided by the load capacitance and the pull down resistance at VOUT There is an internal pull down resistor of 350 Q Any resistive load a
18. e supply of 5 V is required Current consumption is typically 68 mA Power consumption decreases to 1 5 mW when the device is disabled The AD8318 can be configured to provide a control voltage to a VGA such as a power amplifier or a measurement output from Pin VOUT Because the output can be used for controller applications wideband noise is minimal Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM VPSI ENBL TADJ VPSO 04853 001 Figure 1 Vout V R ERROR dB 0 2 5 9 L LLL LL LLLA 4 65 60 55 50 45 40 35 30 25 20 15 10 5 0 5 10 Pin dBm 04853 052 Figure 2 Typical Logarithmic Response and Error vs Input Amplitude at 5 8 GHz In this mode the setpoint control voltage is applied to VSET The feedback loop through an RF amplifier is closed via VOUT the output of which regulates the amplifier output to a magnitude corresponding to VSET
19. ed see Figure 39 The circuit diagram in Figure 39 shows the AD8318 used with a high speed comparator circuit The 40 Q series resistor at the output of the AD8318 combines with an internal 10 Q to properly match to the 50 Q input of the comparator PULSED RF 50dB 30dB 20dB l 10dB INPUT T t COMPARATOR OUTPUT 04853 041 TIME ns Figure 40 Pulse Response of AD8318 and Comparator for RF Pulses of Varying Amplitudes Figure 40 shows the response of the AD8318 and the comparator for a 500 MHz pulsed sine wave of varying amplitudes The output level of the AD8318 is the signal strength of the input signal For applications where these RF bursts are very small the output level does not change by a large amount Using a comparator is beneficial in this case because it turns the output of the log amp into a limiter like signal While this configuration does result in the loss of received signal power level it does allow for presence only detection of low power RF bursts OUTPUT FILTERING For applications in which maximum video bandwidth and consequently fast rise time are desired it is essential that the CLPF pin be left unconnected and free of any stray capacitance To reduce the nominal output video bandwidth of 45 MHz connect a ground referenced capacitor Crrr to the CLPF pin as shown in Figure 41 Generally this is done to reduce output ripple at twice the input fre
20. een Vovr and the RF input signal when the device is in measurement mode the AD8318 adjusts the voltage on VOUT VOUT is now an error amplifier output until the level at the RF input corresponds to the applied V ser When the AD8318 operates in controller mode there is no defined relationship between Vser and Vour voltage Vovr settles to a value that results in the correct input signal level appearing at INHI INLO In order for this output power control loop to be stable a ground referenced capacitor is connected to the CLPF pin This capacitor Cyr integrates the error signal in the form of a current to set the loop bandwidth and ensure loop stability For further details on control loop dynamics refer to the AD8315 data sheet O RFIN DIRECTIONAL COUPLER GAIN CONTROL ATTENUATOR VOLTAGE VOUT INHI 52 30 AD8318 INLO VSET CLPF n Cet Figure 42 AD8318 Controller Mode 04853 034 Decreasing Vsrr which corresponds to demanding a higher signal from the VGA tends to increase Vour The gain control voltage of the VGA must have a positive sense A positive control voltage to the VGA increases the gain of the device AD8318 The basic connections for operating the AD8318 as an analog controller with the AD8367 are shown in Figure 43 The AD8367 is a low frequency to 500 MHz VGA with 45 dB of dynamic range This configuration is very similar to the one shown in Figure 42 For applications working at high inpu
21. ion of an unknown input power based on the output voltage of the detector Pmi unknown Vour measured Slope Intercept 17 Rev B Page 15 of 24 AD8318 Using the equation for the ideal output voltage see Equation 13 as a reference the log conformance error of the measured data can be calculated as Error dB Vourmeasurep Vourqpeat Slope 18 Figure 32 includes a plot of the error at 25 C the temperature at which the log amp is calibrated Note that the error is not zero This is because the log amp does not perfectly follow the ideal Vout vs Pw equation even within its operating region The error at the calibration points 712 dBm and 52 dBm in this case is however equal to 0 by definition Figure 32 includes error plots for the output voltage at 40 C and 85 C These error plots are calculated using the slope and intercept at 25 C This method is consistent with a mass production environment where calibration at temperature is not practical SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE In some applications very high accuracy is required at just one power level or over a reduced input range For example in a wireless transmitter the accuracy of the high power amplifier HPA is most critical at or close to full power Figure 33 shows the same measured data as Figure 32 Note that accuracy is very high from 10 dBm to 30 dBm Below 30 dBm the error increases t
22. iption Package Option Quantity AD8318ACPZ REEL7 40 C to 85 C 16 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 16 4 1 500 AD8318ACPZ R2 40 C to 85 C 16 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 16 4 250 AD8318ACPZ WP 2 40 C to 85 C 16 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 16 4 64 AD8318 EVALZ Evaluation Board 1 Z RoHS compliant part WP waffle pack 2004 2007 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners PPAR DEVICES soils Aud Rev B Page 24 of 24
23. istor at the VOUT pin with a 40 Q resistor the CLPF pin remains open Pulse response time is measured using a Tektronix TDS5104 digital phosphor oscilloscope Both channels on the scope are configured for 50 Q termination The 10 Q internal series resistance at VOUT combined with the 40 Q resistor attenuates the output voltage level by two RF input frequency is set to 100 MHz with 10 dBm at the input of the device The RF burst is generated using a Rohde amp Schwarz SMT06 with the pulse option with a period of 1 5 us a width of 0 1 us and a pulse delay of 0 04 us The output response is triggered using the video output from the SMTO6 Refer to Figure 47 for an overview of the test setup ROHDE amp SCHWARZ SMT06 VIDEO RF OUT OUT 7dBm INHI VOUT AD8318 INLO AD8318 To measure noise spectral density the 0 Q resistor in series with the VOUT pin is replaced with a 1 uF dc blocking capacitor The capacitor is used because the Rohde amp Schwarz FSEA spectrum analyzer cannot handle dc voltages at its RF input The CLPF pin is left open for data collected for Figure 19 For Figure 20 a 1 uF capacitor is placed between CLPF and ground The large capacitor filters the noise from the detector stages of the log amp Noise spectral density measurements are taken using the FSEA spectrum analyzer and the SMT06 signal generator The signal generator frequency is set to 2 2 GHz The spectrum analyzer has a span of 10 Hz
24. ling Caps 18 pF CLPF Open INPUT SIGNAL COUPLING The RF input to the AD8318 INHI is single ended and must be ac coupled INLO input common should be ac coupled to ground see Figure 23 Suggested coupling capacitors are 1 nF ceramic 0402 style capacitors for input frequencies of 1 MHz to 8 GHz The coupling capacitors should be mounted close to the INHI pin and the INLO pin These capacitor values can be increased to lower the input stage high pass cutoff frequency The high pass corner is set by the input coupling capacitors and the internal 10 pF capacitor The dc voltage on INHI and INLO is approximately one diode voltage drop below the voltage applied to the VPSI pin The Smith Chart in Figure 16 shows the AD8318 input impedance vs frequency Table 4 lists the reflection coefficient and impedance at select frequencies For Figure 16 and Table 4 the 52 3 Q input termination resistor is removed At dc the resistance is typically 2 kO At frequencies up to 1 GHz the impedance is approximated as 1000 Q 0 7 pF The RF input pins are coupled to a network as shown in the simplified schematic in Figure 26 Rev B Page 12 of 24 04853 024 Figure 26 Input Interface While the input can be reactively matched this is typically not necessary An external 52 3 Q shunt resistor connected on the signal side of the input coupling capacitors see Figure 23 combines with the relatively high input impedance to provide an adequat
25. n controller mode is similar to the method used in measurement mode Do a simple 2 point calibration by applying two known Vszr voltages or DAC codes and measuring the output power from the VGA Slope and intercept are calculated using Equation 20 to Equation 22 Slope Vseri Vser2 Pour Pour 20 Intercept Pour Vseri Slope 21 Vser Slope x Px Intercept 22 For more information on AGC applications refer to the AD8367 data sheet or ADL5330 data sheet Rev B Page 20 of 24 CHARACTERIZATION SETUP AND METHODS The general hardware configuration used for the AD8318 characterization is shown in Figure 47 The primary setup used for characterization is measurement mode The characterization board is similar to the customer evaluation board with the exception that the RF input has a Rosenberger SMA connector and R10 has changed to a 1 KQ resistor to remove cable capacitance from the bench characterization setup Slope and intercept are calculated in this data sheet and in the production environment using linear regression from 50 dBm to 10 dBm The slope and intercept generate an ideal line Log conformance error is the difference from the ideal line and the measured output voltage for a given temperature in dB For additional information on the error calculation refer to the Device Calibration and Error Calculation section The hardware configuration for pulse response measurement replaces the 0 Q series res
26. n for the output drivers Pin CMIP and Pin CMOP should be connected to a low impedance ground plane A power supply voltage of between 4 5 V and 5 5 V should be applied to VPSO and VPSI In addition 100 pF and 0 1 uF power supply decoupling capacitors connect close to each power supply pin The two adjacent VPSI pins can share a pair of decoupling capacitors due to their proximity 1SEE TEMPERATURE COMPENSATION SECTION 2SEE RESPONSE TIME SECTION 04853 022 Figure 23 Basic Connections The paddle of the AD8318 LFCSP is internally connected to CMIP For optimum thermal and electrical performance solder the paddle to a low impedance ground plane ENABLE INTERFACE To enable the AD8318 the ENBL pin must be pulled high Taking ENBL low puts the AD8318 in sleep mode reducing current consumption to 260 uA at ambient The voltage on ENBL must be greater than 2 Vsz 1 7 V to enable the device When enabled the ENBL pin draws less than 1 uA When ENBL is pulled low the pin sources 15 uA The enable interface has high input impedance An internal 200 Q resistor is placed in series with the ENBL input for added protection Figure 24 depicts a simplified schematic of the enable interface The response time of the AD8318 ENBL interface is shown in Figure 25 04853 023 04853 051 500mV M400ns gt v 425 200ns A CH1 920mV Figure 25 ENBL Response Time VPOS 5 0 V Input AC Coup
27. nless otherwise noted Colors 25 C gt Black 40 C gt Blue 85 C gt Red 2 2 2 0 2 0 1 6 1 8 12 1 6 0 8 14 04 T a s kJ 5 kJ 5 1 2 0 E 5 E o c o c gt gt 1 0 0 4 amp I 0 8 0 8 0 6 1 2 0 4 1 6 8 8 0 2 20 3 65 55 45 35 25 15 5 5 15 Pix dBm Pin dBm Figure 4 VOUT and Log Conformance vs Input Amplitude at 900 MHz Figure 7 Vour and Log Conformance vs Input Amplitude at 3 6 GHz Typical Device Typical Device Rrap 51 Q 22 2 0 22 2 0 2 0 1 6 2 0 1 6 1 8 12 1 8 12 1 6 0 8 1 6 0 8 _ 14 04 T _ 14 04 T e 512 o g 512 o g o a o a gt gt 1 0 0 4 amp 1 0 0 4 E 0 8 0 8 0 8 0 8 0 6 1 2 0 6 1 2 0 4 1 6 8 0 4 1 6 8 0 2 2 0 8 0 2 2 0 3 65 55 45 35 25 15 5 5 15 65 55 45 35 25 15 5 5 15 Pin dBm Pix dBm Figure 5 VOUT and Log Conformance vs Input Amplitude at 1 9 GHz Figure 8 VOUT and Log Conformance vs Input Amplitude at 5 8 GHz Typical Device Typical Device Rrap 1000 Q 2 2 2 0 2 2 4 5 2 0 1 6 2 0 3 6 1 8 1 2 1 8 2 7 1 6 0 8 1 6 1 8 1 4 04 T 1 4 09 g 2 3 512 o g 512 o g o a o a gt gt 1 0 0 4 E 1 0 0 9 X 0 8 0 8 0
28. nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the AD8318 a 0 O series resistor and a 0 1 uF capacitor placed closer to the power supply input pin C5 0 1 uF Size 0603 C6 100 pF Size 0402 C7 100 pF Size 0402 C8 0 1 uF Size 0603 R5 0 Q Size 0603 R6 0 Q Size 0603 C9 Loop Filter Capacitor The low pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a capacitor between CLPF and ground Increasing this capacitor increases the overall rise fall time of the AD8318 for pulsed input signals See the Output Filtering section for more details C9 open Size 0603 Rev B Page 22 of 24 AD8318 04853 035 Figure 48 Evaluation Board Schematic S ANALOG DEVICES TWP 458318 CSP EVAL BD 1 VSET RFIN ENBL 5W1 VoU R3 04853 036 04853 037 Figure 49 Component Side Layout Figure 50 Component Side Silkscreen Rev B Page 23 of 24 AD8318 OUTLINE DIMENSIONS H 0 60 MAX BOTTOM VIEW PIN 1 INDICATOR E 16 4 PIN 1 P 225 INDICATOR EXPOSE uod PAD 1 95 9 8 5 0 25 MIN e l1 95 BSC J N COPLANARITY BARS T on sus COMPLIANT TO JEDEC STANDARDS MO 220 VGGC B Figure 51 16 Lead Lead Frame Chip Scale Package LFCSP VO 4mm x 4 mm Body Very Thin Quad CP 16 4 Dimensions shown in millimeters ORDERING GUIDE Ordering Model Temperature Range Package Descr
29. nsation Interface The internal temperature compensation R4 499 Q Size 0603 resistor is optimized for an input signal of 2 2 GHz when R4 is 500 This circuit can be adjusted to optimize performance for other input frequencies by changing the value of Resistor R4 See the Temperature Compensation of Output Voltage section R7 R8 R9 R10 Output Interface Measurement Mode In measurement mode a portion of R7 0 Q Size 0402 the output voltage is fed back to the VSET pin via R7 The magnitude of the R8 open Size 0402 slope at VOUT can be increased by reducing the portion of Vour that is fed back po _ open Size 0402 to VSET R10 can be used as a back terminating resistor or as part of a single R10 00 Size 0402 pole low pass filter Ins Size 0402 R7 R8 R9 R10 Output Interface Controller Mode In this mode R7 must be open In R7 open Size 0402 controller mode the AD8318 can control the gain of an external component A setpoint voltage is applied to the VSET pin the value of which corresponds to the desired RF input signal level applied to the AD8318 RF input The magnitude of the control voltage is optionally attenuated via the voltage divider comprised of R8 and R9 or a capacitor can be installed in R8 to form a low pass filter along with R9 See the Controller Mode section for more details R8 open Size 0402 R9 0 Q Size 0402 R10 2 0 Q Size 0402 C5 C6 C7 C8 R5 R6 Power Supply Decoupling The
30. nse time for RF burst detection capability A block diagram is shown in Figure 22 VPSI ENBL TADJ VPSO 04853 021 Figure 22 Block Diagram A fully differential design using a proprietary high speed SiGe process extends high frequency performance Input INHI receives the signal with a low frequency impedance of nominally 1200 Q in parallel with 0 7 pF The maximum input with 1 dB log conformance error is typically 0 dBm re 50 Q The noise spectral density referred to the input is 1 15 nV NHz which is equivalent to a voltage of 118 uV rms in a 10 5 GHz bandwidth or a noise power of 66 dBm re 50 Q This noise spectral density sets the lower limit of the dynamic range However the low end accuracy of the AD8318 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise AD8318 CMIP the input system common pin provides a quality low impedance connection to the printed circuit board PCB ground via four package pins Ground the package paddle which is internally connected to the CMIP pin to the PCB to reduce thermal impedance from the die to the PCB The logarithmic function is approximated in a piecewise fashion by nine cascaded gain stages For a more complete explanation of the logarithm approximation refer to the AD8307 data sheet The cells have a nominal voltage gain of 8 7 dB each and a 3 dB bandwidth of 10 5 GHz Using precision biasing
31. o about 1 dB This is because the calibration points have changed to 14 dBm and 26 dBm Vout 25 C ERROR 25 C Voyr 40 C ERROR 40 C Vour 85 C ERROR 85 C 22 2 5 2 0 2 0 1 8 1 5 1 6 1 0 1 4 05 F z 5 1 2 0 E Vour2 2 1 0 05 amp Vouti 1 0 0 6 1 5 0 4 20 8 0 2 2 5 3 65 60 55 50 45 40 35 30 20 10 5 0 5 Pin dBm l Pin2 Pint Figure 33 Output Voltage and Error vs Pin with 2 Point Calibration at 10 dBm and 30 dBm Calibration points are chosen to suit the application at hand In general the calibration points are never chosen in the nonlinear portion of the transfer function of the log amp above 5 dBm or below 60 dBm in this case Figure 34 shows how calibration points can be adjusted to increase dynamic range but at the expense of linearity In this case the calibration points for slope and intercept are set at 4 dBm and 60 dBm These points are at the end of the linear range of the device Once again at 25 C an error of 0 dB is seen at the calibration points Note also that the range over which the AD8318 maintains an error of lt 1 dB is extended to 60 dB at 25 C and 58 dB over temperature The disadvantage of this approach is that linearity suffers especially at the top end of the input range 2 2 2 5 Vout 25 C ERROR 25 C 2 0 Vou
32. onnections sess 12 Enable Interface 2 ertet bieten 12 Input Signal Coupling ettet ite tertie 12 Output Interface netten RH ERE ERE 13 Setpoint Interface i is sisisi ieii 13 REVISION HISTORY 4 07 Rev A to Rev B Added Figure 2 Renumbered Sequentially 1 Changes to Table 1 erotici tes 3 Changes t Figure 23 hier eerte ai 12 Changes to Characterization Setup and Methods Section 21 Changes to Figure 48 Updated Outline Dimensions Changes to Ordering Guide sse 1 06 Rev 0 to Rev A Changed TADJ Resistor to RTADJ Resistor Universal Changes to Applications seen 1 Changes to Table 1 tite incendie 3 Changes to Figure 5 Figure 6 and Figure 7 Captions 8 Changes to Figure 12 Caption 9 Changes to Figure 15 Caption 9 Temperature Compensation of Output Voltage 13 Temperature Sensor seen 14 Measurement Mode E E 14 Device Calibration and Error Calculation 15 Selecting Calibration Points to Improve Accuracy over a Reduced Range tere rh eerie tives 16 Variation in Temperature Drift from Device to Device 17 Temperature Drift at Different Temperatures 17 Setting the Output Slope in Measurement Mode 17 Response Time Capability
33. points in the operating range of the device Rev B Page 16 of 24 Vout 25 C ERROR 25 C wrt Vout Vout 40 C ERROR 40 C wrt Vout Vout 85 C ERROR 85 C wrt Vout Vout V ERROR dB 04853 032 Pin dBm Figure 35 Error vs Temperature with Respect to Output Voltage at 25 C Does Not Take Transfer Function Nonlinearities at 25 C into Account VARIATION IN TEMPERATURE DRIFT FROM DEVICE TO DEVICE Figure 36 shows a plot of output voltage and error for multiple AD8318 devices measured at 5 8 GHz The concentration of black error plots represents the performance of the population at 25 C slope and intercept are calculated for each device The red and blue curves indicate the measured behavior of a population of devices over temperature This suggests a range on the drift from device to device of 1 2 dB 2 2 2 0 2 0 1 6 1 8 1 2 1 6 0 8 14 0 4 g E12 o g gt 1 0 0 4 te 0 8 0 8 0 6 1 2 0 4 1 6 E 0 2 2 0 65 55 45 35 235 15 5 5 15 Piy dBm Figure 36 Output Voltage and Error vs Temperature 4 25 C 40 C and 85 C of a Population of Devices Measured at 5 8 GHz AD8318 TEMPERATURE DRIFT AT DIFFERENT TEMPERATURES Figure 37 shows the log slope and error over temperature for a 5 8 GHz input signal Error due to drift over temperature consistently remains within 0 5 dB and only begin
34. quency for a symmetric input waveform such as sinusoidal signals AD8318 Figure 41 Lowering the Postdemodulation Bandwidth Cuz is selected by 1 Car 1 5 pF 19 n n x3 13 kO x VideoBandwidth p Ws Set the video bandwidth to a frequency equal to about one tenth the minimum input frequency This ensures that the output ripple of the demodulated log output which is at twice the input frequency is well filtered Rev B Page 18 of 24 In many log amp applications it may be necessary to lower the corner frequency of the postdemodulation filtering to achieve low output ripple while maintaining a rapid response time to changes in signal level For an example of a 4 pole active filter see the AD8307 data sheet CONTROLLER MODE The AD8318 provides a controller mode feature at the VOUT pin Using Vser for the setpoint voltage it is possible for the AD8318 to control subsystems such as power amplifiers PAs variable gain amplifiers VGAs or variable voltage attenuators VVAs that have output power that increases monotonically with respect to their gain control signal To operate in controller mode the link between VSET and VOUT is broken A setpoint voltage is applied to the VSET input VOUT is connected to the gain control terminal of the VGA and the detector RF input is connected to the output of the VGA usually using a directional coupler and some additional attenuation Based on the defined relationship betw
35. roduct features A patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD A Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 6 of 24 AD8318 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CMIP CMIP TADJ VPSO 04853 002 Figure 3 Pin Configuration Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 2 11 12 CMIP Device Common Input System Ground 3 4 VPSI Positive Supply Voltage Input System 4 5 V to 5 5 V Voltage on Pin 3 Pin 4 and Pin 9 should be equal 5 CLPF Loop Filter Capacitor 6 VOUT Measurement and Controller Output 7 VSET Setpoint Input for Controller Mode or Feedback Input for Measurement Mode 8 CMOP Device Common Output System Ground 9 VPSO Positive Supply Voltage Output System 4 5 V to 5 5 V Voltage on Pin 3 Pin 4 and Pin 9 should be equal 10 TADJ Temperature Compensation Adjustment 13 TEMP Temperature Sensor Output 14 INHI RF Input Nominal input range 60 dBm to 0 dBm re 50 O ac coupled 15 INLO RF Common for INHI AC coupled RF common 16 ENBL Device Enable Connect to VPSI for normal operation Connect pin to ground for disable mode Paddle Internally Connected to CMIP Solder to Ground Rev B Page 7 of 24 AD8318 TYPICAL PERFORMANCE CHARACTERISTICS Vros 5 V Ta 25 C 40 C 85 C Crier 220 pF Rrapj 500 Q u
36. s to exceed this limit when the ambient temperature drops below 20 C When using a reduced temperature range higher measurement accuracy is achievable for all frequencies Vour 25 C Vout 40 C Vour 85 C Vout 0 C Vour 70 C ERROR 25 C ERROR 10 C ERROR 20C ERROR 0 C ERROR 70 C Voyr 10 C Vout 20 C ERROR 40 C ERROR 85 C Ji H J 1 6 E HERE t 12 lt gt fi x 2 45 id a 0 4 04853 039 0 2 Li 65 60 55 50 45 40 35 30 25 20 15 10 0 5 Pin dBm Figure 37 Typical Drift at 5 8 GHz for Various Temperatures SETTING THE OUTPUT SLOPE IN MEASUREMENT MODE To operate in measurement mode VOUT is connected to VSET This yields the typical logarithmic slope of 25 mV dB The output swing corresponding to the specified input range is then approximately 0 5 V to 2 1 V The slope and output swing can be increased by placing a resistor divider between VOUT and VSET that is one resistor from VOUT to VSET and one resistor from VSET to common As an example if two equal resistors such as 10 kQ 10 kQ are used the slope doubles to approximately 50 mV dB The input impedance of VSET is approximately 500 kQ Slope setting resistors should be kept below 50 kQ to prevent this input impedance from affecting the resulting slope When increasing the slope
37. t 40 C ERROR 40 C 2 0 Vout 85 C ERROR 85 C 1 8 1 5 1 6 1 0 _ 1 4 05 A S 512 0 E o gt 1 0 0 5 amp 0 8 1 0 0 6 1 5 58dB DYNAMIC RANGE 1dB ERROR 0 4 20 8 0 2 65 60 55 50 45 40 35 30 25 20 15 10 5 0 5 Pin dBm Figure 34 Dynamic Range Extension by Choosing Calibration Points Close to the End of the Linear Range Another way of presenting the error function of a log amp detector is shown in Figure 35 In this case the dB error at hot and cold temperatures is calculated with respect to the output voltage at ambient This is a key difference in comparison to the plots in Figure 33 and Figure 34 Previously all errors were calculated with respect to the ideal transfer function at ambient When this alternative technique is used the error at ambient becomes by definition equal to 0 see Figure 35 This is valid if the device transfer function perfectly follows the ideal Vour Slope x Pn Intercept equation However because a log amp in practice never perfectly follows this equation especially outside of its linear operating range this plot tends to artificially improve linearity and extend the dynamic range This plot is a useful tool for estimating temperature drift at a particular power level with respect to the nonideal output voltage at ambient However to achieve this level of accuracy in an end application requires calibration at multiple
38. t frequencies such as cellular bands or WLAN or those requiring large gain control ranges the AD8318 can control the 10 MHz to 3 GHz ADL5330 RF VGA For further details and an application schematic refer to the ADL5330 data sheet The voltage applied to the GAIN pin controls the gain of the AD8367 This voltage Vcam is scaled linear in dB with a slope of 20 mV dB and runs from 50 mV at 2 5 dB of gain up to 1 0 V at 42 5 dB The incoming RF signal to the AD8367 has a varying amplitude level Receiving and demodulating it with the lowest possible error requires that the signal levels be optimized for the highest signal to noise ratio SNR feeding into the analog to digital converters ADC This is done by using an automatic gain control AGC loop In Figure 43 the voltage output of the AD8318 modifies the gain of the AD8367 until the incoming RF signal produces an output voltage that is equal to the setpoint voltage Vser 3V E RF INPUT SIGNAL m VPOS GND RF OUTPUT SIGNAL 57 60 A Mss BANDPA CN FILTER Ly SETPOINT VOLTAGE vp V Figure 43 AD8318 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the AD8367 04853 047 The AGC loop is capable of controlling signals over 45 dB dynamic range The output of the AD8367 is designed to drive loads 2 200 Q As a result it is not necessary to use the 53 6 Q resistor at the input of
39. t VOUT is placed in parallel with the internal pull down resistor and provides additional discharge current AD8318 VPSO CLPF VOUT CMOP g Figure 27 Output Interface SETPOINT INTERFACE The setpoint interface is shown in Figure 28 The VSET input drives the high impedance 250 kQ input of an internal operational amplifier The VSET voltage appears across the internal 3 13 kQ resistor to generate Iser When a portion of VOUT is applied to VSET the feedback loop forces Ip x logio Vin Vintercert ser 2 If Vser Vovr X Iser Vovrl X x 3 13 kQ The result is Vour Ip x 3 13 KQ x X x logio Vin Vinrercert IseT VSET 3 13kO 04853 026 CMOP Figure 28 VSET Interface The slope is given by Ip x X x 3 13 kQ 500 mV x X For example if a resistor divider to ground is used to generate a Vser voltage of Vour 2 X 2 The slope is set to 1 V decade or 50 mV dB TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE The AD8318 functionality includes the capability to externally trim the temperature drift Attaching a ground referenced resistor to the TADJ pin alters an internal current minimizing intercept drift vs temperature As a result the Rray can be optimized for operation at different frequencies Icomp 2V i VINTERNAL 0 4V 2kQ TADJ Figure 29 TADJ Interface Rrap nominally 499 Q for optimal temperature compensation at 2 2 GHz input frequency is connected between the TADJ pin and gro
40. the AD8318 the nominal input imped ance of 2 kQ is sufficient If the AD8367 output drives a 50 Q load such as an oscilloscope or spectrum analyzer use a simple resistive divider network The divider used in Figure 43 has an insertion loss of 11 5 dB Figure 44 shows the transfer function of output power vs Vser voltage for a 100 MHz sine wave at 40 dBm into the AD8367 Rev B Page 19 of 24 AD8318 Pour dBm ERROR dB 04853 048 0 6 0 8 1 0 1 2 1 4 1 6 1 8 20 Vser V Figure 44 AD8367 Output Power vs AD8318 Setpoint Voltage For the AGC loop to remain locked the AD8318 must track the envelope of the VGA output signal and provide the necessary voltage levels to the AD8367 gain control input Figure 45 shows an oscilloscope screen image of the AGC loop depicted in Figure 43 A 50 MHz sine wave with 50 AM modulation is applied to the AD8367 The output signal from the VGA is a constant envelope sine wave with an amplitude corresponding to a setpoint voltage at the AD8318 of 1 0 V AM MODULATED INPUT 2 n illl TR TI M iM ul AD8367 m ut Mi M M NAM T i CH1 50 0mV CH2 200mV M4 00ms A CH2 64 0mV CH3 20 0mV 2j 04853 045 Figure 45 Oscilloscope Screen Image Showing an AM Modulated Input Signal to the AD8367 The AD8318 tracks the envelope ofthis input signal and applies the appropriate voltage to ensure a constant output from the AD8367 The
41. um Input Level 3 dB error 55 dBm Slope 23 mV dB Intercept 37 dBm Output Voltage High Power In Pn 10 dBm 1 06 V Output Voltage Low Power In Pin 40 dBm 1 78 V Temperature Sensitivity Pin 10 dBm 25 C lt TA lt 85 C 0 028 dB C 40 C lt TA lt 25 C 0 0085 dB C OUTPUT INTERFACE VOUT Pin 6 Voltage Swing Vset OV Pin 10 dBm no load 4 9 V Vser 2 1 V Pin 10 dBm no load 25 mV Output Current Drive Vset 1 5 V Pin 50 dBm 60 mA Small Signal Bandwidth Pin 10 dBm from CLPF to VOUT 60 MHz Video Bandwidth or Envelope Bandwidth 45 MHz Output Noise Pin 2 2 GHz 10 dBm froise 100 kHz Cier 220 pF 90 nV 4Hz Fall Time Pin Off to 10 dBm 90 to 10 10 ns Rise Time Pin 10 dBm to off 10 to 90 12 ns Rev B Page 4 of 24 AD8318 Parameter Conditions Min Typ Max Unit VSET INTERFACE VSET Pin 7 Nominal Input Range Pin 0 dBm measurement mode 0 5 Pin 65 dBm measurement mode 2 1 V Logarithmic Scale Factor 0 04 dB mV Bias Current Source Pin 10 dBm Vser 2 1 V 2 5 yA TEMPERATURE REFERENCE TEMP Pin 13 Output Voltage Ta 25 C Rioap 10 KQ 0 57 0 6 0 63 V Temperature Slope 40 C lt TA 85 C Rioap 10 kQ 2 mV C Current Source Sink Ta 25 C 10 0 1 mA POWER DOWN INTERFACE ENBL Pin 16 Logic Level to Enable Device 1 7 V ENBL Current When Enabled ENBL 5V lt 1 uA ENBL Current When Disabled ENBL 0 V sour
42. und see Figure 23 The value of this resistor partially determines the magnitude of an analog correction coefficient that is employed to reduce intercept drift Rev B Page 13 of 24 AD8318 Table 5 lists recommended resistors for various frequencies These resistors provide the best overall temperature drift based on measurements of a diverse population of devices The relationship between output temperature drift and frequency is nonlinear and is not easily modeled Experimentation is required to choose the correct Rrary resistor at frequencies not listed in Table 5 Table 5 Recommended R4 Resistors Frequency Recommended Rap 900 MHz 5000 1 9 MHz 5000 2 2 GHz 5000 3 6 GHz 510 5 8 GHz 1kO 8 GHz 5000 TEMPERATURE SENSOR The AD8318 internally generates a voltage that is proportional to absolute temperature Vrrar The Verar voltage is multiplied by a factor of 5 resulting in a 2 mV C output at the TEMP pin The output voltage at 27 C is typically 600 mV An emitter follower drives the TEMP pin as shown in Figure 30 VPSI INTERNAL O CMIP 04853 028 Figure 30 Temp Sensor Interface The internal pull down resistance is 5 kO The temperature sensor has a slope of 2 mV C The temperature sensor output varies with output current due to increased die temperature Output loads less than 1 kO draw enough current from the output stage causing this increase to occur An output current of
43. ut signal f 900 MHz Rm 500 Q Input Impedance 957 0 71 Q pF 3 dB Dynamic Range Ta 25 C 65 dB 1 dB Dynamic Range Ta 25 C 57 dB 40 C lt Ta lt 85 C 48 dB Maximum Input Level 1 dB error 1 dBm Minimum Input Level 1 dB error 58 dBm Slope 26 24 5 23 mV dB Intercept 19 5 22 24 dBm Output Voltage High Power In Pi 10 dBm 0 7 0 78 0 86 V Output Voltage Low Power In Pin 40 dBm 1 42 1 52 1 62 V Temperature Sensitivity Pn 10 dBm 25 C lt Ta lt 85 C 0 0011 dB C 40 C lt Ta lt 25 C 0 003 dB C f 1 9 GHz Rr 5000 Input Impedance 523 0 68 Q pF 3 dB Dynamic Range Ta 25 C 65 dB 1 dB Dynamic Range Ta 25 C 57 dB 40 C lt Ta lt 85 C 50 dB Maximum Input Level 1 dB error 2 dBm Minimum Input Level 1 dB error 59 dBm Slope 27 24 4 22 mV dB Intercept 17 20 4 24 dBm Output Voltage High Power In Pin 10 dBm 0 63 0 73 0 83 V Output Voltage Low Power In Pin 35 dBm 1 2 1 35 1 5 V Temperature Sensitivity Pn 10 dBm 25 C lt Ta lt 85 C 0 0011 dB C 40 C lt Ta lt 5 C 0 0072 dB C f 2 2 GHz Rraps 500 Q Input Impedance 391 0 66 Q pF 3 dB Dynamic Range Ta 25 C 65 dB 1 dB Dynamic Range Ta 25 C 58 dB 40 C lt Ta lt 85 C 50 dB Maximum Input Level 1 dB error 2 dBm Minimum Input Level 1 dB error 60 dBm Slope 28 24 4 21 5 mV dB Intercept 15 19 6 25 dBm Output Voltage High Power In Pn 10 dBm 0 63 0 73 0
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ANALOG DEVICES AD8318 English products handbook Rev B