ANALOG DEVICES AD8114/AD8115 English products handbook Rev B
Contents
1. GAIN 0 200mV p p 91 FLATNESS 1 0 2 0 1 a a A a z 3 0 2 z z z lt 2V p p o lt o 6 S a 03 Z z E lt lt E l 5 0 4 L L E o AS SHOWN Ri 1500 ra 5 7 06 5 5 0 1 1 10 100 1000 P 10 100 FREQUENCY MHz FREQUENCY MHz Figure 7 AD8114 Frequency Response Ri 150 Q Figure 10 AD8115 Frequency Response Ri 1500 3 0 4 3 0 5 2 0 3 2 0 4 200mV p p 1 0 2 1 0 3 GAIN 200mV p p GAIN 0 0 1 0 0 2 FLATNESS T pu 0 pu 0 1 g o s FLATNESS m z 2 0 1 Li z 2 0 z z E o lt 2V p p E o 9 3 0 2 3 S3 0 1 m L 200mV p p 5 4 0 3 4 2V p p 02 5 5 0 4 0 3 Vo AS SHOWN s Vo AS SHOWN 2V p p z 6 RL z 1kQ 05 5 6 RL z 1kQ 04 5 7 0 6 gt 7 0 5 5 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 8 AD8114 Frequency Response Ri 1 kO Figure 11 AD8115 Frequency Response Ri 1 kO a a 3 z z lt lt 6 S z E 1000 1000 FREQUENCY MHz FREQUENCY MHz Figure 9 AD81 14 Frequency Response vs Load Impedance Figure 12 AD8115 Freguency Response vs Load Impedance Rev B Page 11 of 32 AD8114 AD81152. 0 0 10 Ri 1ko 10 Ru 1k Rr 37 50 Ry 37 50 20 20 30 30 a a 2 40 2 40 x x ALL HOSTILE 50 i ALL HOSTILE 50 o o ADJACENT 6 60 6 60 4 o o 70 ADJACENT 70 80 80 90 90 3 100 5 100 x 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz Figure 13 AD8114 Crosstalk vs Frequency Figure 16 AD8115 Crosstalk vs Frequency 0 10 Vo 2V p p Ri 1500 20 30 8 2 3 40 6 6 E E o O 60 2ND HARMONIC E E o o a B _79 3RD HARMONIC HARMONIC 80 100 5 100 5 1 10 50 1 10 50 FUNDAMENTAL FREQUENCY MHz FUNDAMENTAL FREQUENCY MHz Figure 14 AD81 14 Distortion vs Frequency Figure 17 AD8115 Distortion vs Frequency V STEP RL 1500 2 2 a a 3 0 5 10 15 20 25 30 35 40 45 5ns DIV 5ns DIV Figure 15 AD8114 Settling Time Figure 18 AD8115 Settling Time Rev B Page 12 of 32 AD8114 AD8115
3. 1M ik 100k 100k 3 S LI LI 9 2 s a 2 10k u 10k E 2 z pa 1k Ak 100 5 100 5 0 1 1 10 100 500 0 1 1 10 100 500 FREQUENCY MHz FREGUENCY MHz Figure 19 AD8114 Input Impedance vs Freguency Figure 22 AD8115 Input Impedance vs Frequency 1000 100 u o z lt a a 10 E 2 a E 2 O 1 0 1 1000 0 1 1 10 100 1000 FREQUENCY MHz FREGUENCY MHz Figure 20 AD8114 Output Impedance Enabled vs Freguency Figure 23 AD81 15 Output Impedance Enabled vs Frequency 1M 1M 100k 100k g 3 5 LI Z 10k 2 10k x lt a a LI LI a a E dk E 1k 3 3 100 100 10 a 10 5 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREGUENCY MHz Figure 21 AD81 14 Output Impedance Disabled vs Frequency Figure 24 AD8115 Output Impedance Disabled vs Frequency Rev B Page 13 of 32 AD811 4 AD8115 80 OFF ISOLATION dB LIJ o o o o o 120 130 140 PSRR dB 5 o VOLTAGE NOISE nV VHz 01070 030 FREQUENCY MHz Figure 25 AD8114 Off Isolation Input Output PSRR 01070 031 03 0 1 1 10 FREGUENCY MHz Figure 26 AD8114 PSRR vs Freguency 16nV VHz 01070 032 L T T O AN 10 100 1k 10k 10
4. FREQUENCY n o a o o 80 20 0 12 10 8 6 4 2 0 2 4 6 8 10 14 12 10 8 6 4 2 0 2 4 6 8 10 12 14 16 18 OFFSET VOLTAGE mV OFFSET VOLTAGE mV 01070 043 01070 046 Figure 38 AD8114 Offset Voltage Distribution Figure 41 AD8115 Offset Voltage Distribution FREQUENCY FREQUENCY 01070 044 01070 047 4 0 12 8 0 4 8 12 16 OFFSET VOLTAGE DRIFT uV C OFFSET VOLTAGE DRIFT uV C N Figure 39 AD8114 Offset Voltage Drift Distribution 40 C to 85 C Figure 42 AD8115 Offset Voltage Drift Distribution 40 C to 85 C Rev B Page 16 of 32 AD8114 AD8115 1 0 SCHEMATICS Vec Vec ESD ESD INPUT INPUT ESD 2 ESD F AVEE 3 DGND 5 Figure 43 Analog Input Figure 46 Logic nput Vcc Vcc ESD 2kQ ESD OUTPUT O OUTPUT ESD Yo ESD AVEE DGND Figure 44 Analog Output Figure 47 Logic Output 01070 008 DGND Figure 45 Reset Input Rev B Page 17 of 32 AD8114 AD8115 THEORY OF OPERATION The AD8114 G 1 and AD8115 G 2 are crosspoint arrays wi
5. a 31 11 01 Rev 0 to Rev A Edits to ORDERING GUIDE eene 5 Comments added to Outline Dimensions ss 26 Revision 0 Initial Version Power On Reset as io em EE 19 Gain Selection ze RE ERN qos 19 Creating Larger Crosspoint Arrays eee 20 Multichannel Video eerte 21 Cros et te utem dadda 22 PEB Layout uyu tee e RENI REDE 25 Evaluation Board u aaa ann RU lati na i 29 Control the Evaluation Board from a PC 30 Overshoot of PC Printer Ports Data Lines 30 Outline Dimensions iei eee eH ree 31 Ordering Guide eee eene tte ien 31 Rev B Page 2 of 32 AD8114 AD8115 SPECIFICATIONS Vs 5 V Ta 25 C Ri 1 kO unless otherwise noted AD8114 AD8115 Table 1 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth 200 mV p p R 1500 150 125 225 200 MHz 2Vp p Ri 150Q 100 125 MHz Gain Flatness 0 1 dB 200 mV p p R 2 1500 25 40 MHz 0 1 dB 2 V p p R 1500 20 40 MHz Propagation Delay 2V p p R 21500 5 ns Settling Time 0 1 2 V step R 1500 40 ns Slevv Rate 2V step R 1500 375 450 V us NOISE DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL Ri 1 kO 0 05 NTSC or PAL R 1500 0 05 00 Differential Phase Error NTSC or PAL Ri 1 kO 0 05 Degrees NTSC or PAL RL 1500 0 05 Degrees Crosstalk All Hostile f
6. PARALLEL INTERFACE OVTPUTO2 n Ap sO som INPUTOO WILMINGTON vi INPUTOL MANUFACTURING 01 005957 REV ANALOG our 701 a Y OUTPUTOO DEVICES 01070 051 Figure 51 Component Side Silkscreen 3 m 01070 052 Figure 52 Board Layout Component Side Rev B Page 26 of 32 AD8114 AD8115 01070 053 Figure 53 Board Layout Signal Layer 01070 054 Figure 54 Board Layout Ground Plane Rev B Page 27 of 32 AD8114 AD8115 Figure 55 Board Layout Circuit Side 8 VIA 1660600 10 Figure 56 Circuit Side Silkscreen Rev B Page 28 of 32 01070 055 01070 056 AD8114 AD8115 EVALUATION BOARD DVCC DGND NC AVEE AGND AVCC NC DVCC AVCC AVEE a a ARAS O O O I JUMPER v 0 01uF 0 01uF 0 01uF J 0 1uF 104F y Y 0 1uF 104F 1 75 BR 21 55 BR 20 56 V AVCC AVEE NO CONNECT A 85 93 ad INPUT 00 O INPUT 00 AVCC 750 AGND 0 0tuF Y 7507 OUTPUT 00 V Y OUTPUT 00 Co V INPUT 01 O INPUT 01 O AV pe V AYEE Py OUTPUT 01 Y 750 AGND 0 01uF 750 V OUTPUT 01 o INPUT 02 O INPUT 02 O AVCC Y V 750 AGND r r dur V OUTPUT 02 Y Ou 750 V OUTPUT 02 o INPUT 03 0 INPUT 03 O AVre AGND AVEE Y ko L oair V 750 OUTPUT 03 INPUT 04 O INPUT 04 QUTPUT OS Y 750 AGND ACA O AVCC Ma i 0 01uF Y 750 OUTPUT 04 INPUT 05 0 INPUT 05 OUTPUT 04 Co Y 750 AGND O AVre V AVEE V 0 01uF Y 750 OUTPUTOS INPUT
7. Parallel Port Selection ANALOG 16 X 16 Video Crasspoime Switch DEVICES Evalnutivn Bourd Cuntroller Bev 2 mou Channel 12 9 4 5 679 110 1121913155 OH COOCOCOCOCCSOCO lImocacoosac Hacc mara m mw m sim sm mmm m else YC 99 0 969 ME e miulmiu sin ulu isi ulu l l o 8 9 8 9 8 9 9 9 9 8 OC OC i Figure 59 Screen Display and Control Softvvare Rev B Page 30 of 32 01070 059 OUTLINE DIMENSIONS TOP VIEW PINS DOWN 0 20 imeni 7 mA AC A vu AT 0 15 0 0 05 0 08 MAX COPLANARITY 0 50 gt e 0 22 VIEW A BSC 0 17 ROTATED 90 CCVV LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS 026 BED Figure 60 100 Lead Low Profile Quad Flat Package LOFP ST 100 Dimension shown in millimeters AD8114 AD8115 ORDERING GUIDE Model Temperature Range Package Description Package Option AD8114AST 40 C to 85 C 100 Lead Low Profile Quad Flat Package LOFP ST 100 AD8114ASTZ 40 C to 85 C 100 Lead Low Profile Quad Flat Package LOFP ST 100 AD8115AST 40 C to 85 C 100 Lead Low Profile Quad Flat Package LOFP ST 100 AD8115ASTZ 40 C to 85 C 100 Lead Low Profile Quad Flat Package LOFP ST 100 AD8114 EVAL AD8115 EVAL Evaluation Board Evaluation Board 1 Details of the lead finish composition can be found on the ADI website at www analog com by reviewing the Material Description of each relevant package Z Pb free part
8. Rev B Page 31 of 32 AD8114 AD8115 NOTES O 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com ms La DEVICES Rev B Page 32 of 32
9. 06 O INPUT 06 OUTPUT 05 O V7 750 L AGND OAVCC Y V AVCC o UTPUT 06 INPUT 07 O INPUT 07 0 01uF V 750 ube Cam une OUTPUT 06 o V AGND O AVge Y V AVEE INPUT 08 0 INPUT 08 AD8114 AD8115 0 01uF V 752 OUTPUT 07 Y 750 AGND OUTPUT 07 Co V O AVCC V INPUT 09 O INPUT 09 AVCC OTR X7 7507 OUTPUT 08 y 507 1 AGND OUTPUT 08 o V O AV INPUT 10 O INPUT 10 AVEE y a ia ie 09 750 AGND 0 01uF 750 V OUTPUT 09 o V INPUT 11 0 INPUT 11 DANCE V AVCC 750 AGND 0 01uF OUTPUT 10 V u 750 V OUTPUT 10 o INPUT 12 O INPUT 12 O AVEE J Y 750 AGND Sr rta dhr V OUTPUT 11 Y oiu 750 V OUTPUT 11 o INPUT 13 0 INPUT 13 AVCC 750 AGND AVCC V Y 0 01uF 756 OUTPUT 12 INPUT 14 O INPUT 14 OUTPUT 12 Y 750 AGND E O AV EE T V OUTPUT 13 V 0 01uF 750 INPUT 15 O INPUT 15 OUTPUT 13 Co Y 750 AGND O AVCC y Y Y AVGE OUTPUT 14 0 01uF 750 DATA OUT OUTPUT 14 Co 5 O AVre V AVEE V OE V 750 OUTPUT 15 R OUTPUT 15 o Pas AVCC V P2 a OQ z N e e mi a e P2 2 lt lt lt lt O O O O O 2 74 84 83 82 81 so 79 78 77 76 94 P2 3 R33 20kQ pah o DVCC R OR SR OR OR SR OR SR SRI Or 4 Wal V YA RN dad v SERIAL MODE Y JUMP Oe e V P3 11 P3 12 P3 13 P3 14 NOTES R OPTIONAL 50 TERMINATOR RESISTORS C OPTIONAL SMOOTHING CAPACITOR 01070 050 Figure 57 Evaluation Board Schematic Rev B Page 29 of 32 AD8114 AD8115 CONTROL THE EVALUATION BOARD FROM A PC The evaluation board includes
10. 128 x 16 Array 128 x 32 Blocking Using additional crosspoint devices in the design can lower the number of outputs that must be wire ORed together Figure 49 shows a block diagram of a system using eight AD8114s and two AD8115s to create a nonblocking gain of 2 128 x 16 crosspoint that restricts the vvire ORing at the output to only four outputs Additionally by using the lower eight outputs from each of the two Rank 2 AD8115s a blocking 128 x 32 crosspoint array can be realized There are however some drawbacks to this technigue The offset voltages of the various cascaded devices will accumulate and the bandwidth limitations of the devices will compound In addition the extra devices will consume more current and take up more board space Once again the overall system design specifications will determine how to make the various tradeoffs MULTICHANNEL VIDEO The excellent video specifications of the AD8114 AD8115 make them ideal candidates for creating composite video crosspoint switches These can be made guite dense by taking advantage of the AD8114 AD8115 s high level of integration and the fact that composite video reguires only one crosspoint channel per system video channel There are however other video formats that can be routed with the AD8114 AD8115 reguiring more than one crosspoint channel per video channel Some systems use twisted pair wiring to carry video signals These systems utilize differential signal
11. 5 MHz 70 64 dB f 10 MHz 60 52 dB Off Isolation Input Output f 10 MHz R 150 O one channel 90 dB nput Voltage Noise 0 01 MHz to 50 MHz 16 18 nV 4Hz DC PERFORMANCE Gain Error No load 0 05 0 2 0 08 0 6 96 Ri 1kQ 0 05 0 2 Yo Ri 150Q 0 2 0 35 Yo Gain Matching No load channel channel 0 01 0 5 0 04 1 Yo Ri 1kQchannel channel 0 01 0 5 Yo Gain Temperature Coefficient 0 75 1 5 ppm C OUTPUT CHARACTERISTICS Output Impedance DC enabled 0 2 Q Disabled 10 MQ Output Disable Capacitance Disabled 5 pF Output Leakage Current Disabled 1 HA Output Voltage Range No load 43 0 33 V Voltage Range lour 20 mA 2 5 3 V Short Circuit Current 65 mA INPUT CHARACTERISTICS Input Offset Voltage Worst case all configurations 3 15 mV Temperature coefficient 10 HV C Input Voltage Range No load 3 1 5 3 5 V Input Capacitance Any switch configuration 5 pF Input Resistance 1 10 MO Input Bias Current Per output selected 2 5 HA SWITCHING CHARACTERISTICS Enable On Time 60 ns Switching Time 2 V Step 50 UPDATE to 1 settling 50 ns Switching Transient Glitch 20 30 mV p p Rev B Page 3 of 32 AD8114 AD8115 Parameter Conditions Min Typ Max Unit POWER SUPPLIES Supply Current AVCC outputs enabled no load 70 80 mA AVCC outputs disabled 27 30 mA AVEE outputs enabled no load 70 80 mA AVEE outputs disabled 27 30 mA DVCC outputs enabled no load 16 mA Supply Voltage Range 44 5 to 45 5 V PSRR DC 64 80 dB f 100 kHz 66
12. 65 67 69 71 73 1 75 DVCC 5 V for Digital Circuitry 2 74 DGND Ground for Digital Circuitry 20 56 AVEE 5 V for Inputs and Switch Matrix 21 55 AVCC 5 V for Inputs and Switch Matrix 54 50 46 42 38 34 30 26 22 AVCCxx yy 5 V for Output Amplifier that is Shared by Channels xx and yy Must be connected 52 48 44 40 36 32 28 24 AVEExx yy 5 V for Output Amplifier that is Shared by Channels xx and yy Must be connected 84 A0 Parallel Data Input TTL Compatible output select LSB 83 A1 Parallel Data Input TTL Compatible output select 82 A2 Parallel Data Input TTL Compatible output select 81 A3 Parallel Data Input TTL Compatible output select MSB 80 DO Parallel Data Input TTL Compatible input select LSB 79 D1 Parallel Data Input TTL Compatible input select 78 D2 Parallel Data Input TTL Compatible input select 77 D3 Parallel Data Input TTL Compatible input select MSB 76 D4 Parallel Data Input TTL Compatible output enable 85 to 93 NC No Connect Rev B Page 10 of 32 AD8114 AD8115 TYPICAL PERFORMANCE CHARACTERISTICS
13. AVEE 20 56 AVEE AVCC 21 55 AVCC AVCC15 22 54 AVCCOO OUT15 23 53 OUTOO AVEE14 15 24 52 AVEE00 01 OUT14 25 51 OUTO1 SI SUR 85 Sys SJ 881 sis SIS ES SI ES SLS 2 Ed e NC NO CONNECT z O 0 N AN sr O om o o o Rn Rk o o o UO IO rt st o 6 A SERPS LSE SE CELE SEC ESE SES ES T2aXSSEFSBFS85S8558 5385858398 5858585 OQOOLOQOLOQOLOQOLOQOLOQOLOO S 9 gt 9 gt 2 gt 8 F lt 8 F gt E lt lt lt lt lt lt lt lt lt lt lt lt lt s Figure 6 Pin Configuration Rev B Page 9 of 32 AD8114 AD8115 Table 8 Pin Function Descriptions Pin No Mnemonic Pin Description 58 60 62 64 66 68 70 72 INxx Analog Inputs xx lt Channels 00 through 15 4 6 8 10 12 14 16 18 96 DATA IN Serial Data Input TTL Compatible 97 CLK Clock TTL Compatible Falling edge triggered 98 DATA OUT Serial Data Out TTL Compatible 95 UPDATE Enable Transparent Low Allovvs serial register to connect directly to switch matrix Data latched when high 100 RESET Disable Outputs Active Low 99 CE Chip Enable Enable Low Must be low to clock in and latch data 94 SER PAR Selects Serial Data Mode Low or Parallel Data Mode High Must be connected 53 51 49 47 45 43 41 39 OUTyy Analog Outputs yy lt Channels 00 through 15 37 35 33 31 29 27 25 23 3 5 7 9 11 13 15 17 19 57 AGND Analog Ground for Inputs and Switch Matrix Must be connected 59 61 63
14. IN UPDATE and SER PAR The first step is to assert a low on SER PAR to enable the serial programming mode CE for the chip must be low to allow data to be clocked into the device The CE signal can be used to address an individual device when devices are connected in parallel The UPDATE signal should be high during the time that data is shifted into the devices serial port Although the data will still shift in when UPDATE is low the transparent asynchronous latches will allow the shifting data to reach the matrix This will cause the matrix to try to update to every intermediate state as defined by the shifting data The data at DATA IN is clocked in at every down edge of CLK A total of 80 bits must be shifted in to complete the programming For each of the 16 outputs there are four bits DO to D3 that determine the source of its input followed by one bit D4 that determines the enabled state of the output If D4 is low output disabled the four associated bits DO to D3 do not matter because no input will be switched to that output The most significant output address data is shifted in first and then following in sequence until the least significant output address data is shifted in At this point UPDATE can be taken low which will cause the programming of the device according to the data that was just shifted in The UPDATE registers are asynchronous and when UPDATE is low and CE is low they are transparent Rev B
15. Page 18 of 32 If more than one AD8114 AD8115 device is to be serially programmed in a system the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain All of the CLK CE UPDATE and SER PAR pins should be connected in parallel and operated as described above The serial data is input to the DATA IN pin of the first device of the chain and it will ripple on through to the last Therefore the data for the last device in the chain should come at the beginning of the programming seguence The length of the programming seguence 80 bits will be multiplied by the number of devices in the chain Parallel Programming While using the parallel programming mode it is not necessary to reprogram the entire device when making changes to the matrix In fact parallel programming allows the modification of a single output at a time Since this takes only one CLK UPDATE cycle significant time savings can be realized by using parallel programming One important consideration in using parallel programming is that the RESET signal does not reset all registers in the AD8114 AD8115 When taken low the RESET signal will only set each output to the disabled state This is helpful during power up to ensure that two parallel outputs will not be active at the same time After initial power up the internal registers in the device will generally have random data even though the RESET signal was assert
16. Windows based control software and a custom cable that connects the boards digital interface to the printer port of the PC The wiring of this cable is shown in Figure 58 The software reguires Windows 3 1 or later to operate To install the software insert the disk labeled Disk 1 of 2 into the PC and run the file called SETUP EXE Additional installation instructions will be given on screen Before beginning installation it is important to terminate any other Windows applications that are running When you launch the crosspoint control software you will be asked to select the printer port Most modern PCs have only one printer port usually called LPT1 However some laptop computers use the PRN port Figure 59 shows the main screen of the control software in its initial reset state all outputs off Using the mouse any input can be connected with one or more outputs by simply clicking on the appropriate radio buttons in the 16 x 16 on screen array Each time a button is clicked on the softvvare automatically sends and latches the required 80 bit data stream to the evaluation board An output can be turned off by clicking the appropriate button in the off column To turn off all outputs click on RESET While the computer software only supports serial programming via a PCs parallel port and the provided cable the evaluation board has a connector that can be used for parallel programming The SER PAR signal should be at a logic high to
17. and output signals will have minimum crosstalk if they are located between ground planes on layers above and below and separated by ground in between Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer The only place the input and output signals surface is at the input termination resistors and the output series back termination resistors These signals should also be separated to the extent possible as soon as they emerge from the IC package AD8114 AD8115 Optimized for video applications all signal inputs and outputs are terminated with 75 Q resistors Stripline techniques are used to achieve a characteristic impedance of 75 on the signal input and output lines Figure 50 shows a cross section of one of the input or output tracks along with the arrangement of the PCB layers It should be noted that unused regions of the four layers are filled up with ground planes As a result the input and output traces in addition to having controlled impedances are well shielded w 0 008 0 2mm EZZZZZ77277777777777777777777777777777777777Z27272 TOP LAYER b 0 0514 a 0 008 t 0 00135 0 0343mm 1 3mm 0 2mm WZZZZZZZZ77 e w ZZZZ777777777A SIGNAL LAYER h 0025 A 0 63mm BOTTOM LAYER n 5 q R S 5 Figure 50 Cross Section of Input and Output Traces The board has 32 BNC type connectors 16 inputs and 16 outputs The connectors are arranged in a cresc
18. data bit D4 will determine the enabled state of the output If D4 is low output disabled then the data on DO to D3 does not matter After the desired address and data signals have been established they can be latched into the shift register by a high to low transition of the CLK signal The matrix will not be programmed however until the UPDATE signal is taken low It is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held high and then have all the new data take effect when UPDATE goes low This technique should be used when programming the device for the first time after power up when using parallel programming POWER ON RESET When powering up the AD8114 AD8115 it is usually desirable to have the outputs come up in the disabled state When taken low the RESET pin will cause all outputs to be in the disabled state However the RESET signal does not reset all registers in the AD8114 AD8115 This is important when operating in the parallel programming mode Please refer to that section for information about programming internal registers after power up Serial programming will program the entire matrix each time so no special considerations apply Since the data in the shift register is random after power up it should not be used to program the matrix or the matrix can enter unknown states To prevent this do not apply logic low signals to b
19. into each of the other 15 inputs one at a time while applying no signal to IN00 We can then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations then three at a time etc until there is only one way to drive a test signal into all 15 other inputs in parallel Each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system but it is hardly practical to measure all these terms and then to specify them In addition this describes the crosstalk matrix for just one input channel A similar crosstalk matrix can be proposed for every other input In addition if the possible combinations and permutations for connecting inputs to the other not used for measurement outputs are taken into consideration the numbers rather quickly grow to astronomical proportions If a larger crosspoint array of multiple AD8114 AD8115s is constructed the numbers grow larger still AD8114 AD8115 Obviously some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk One common method is to measure all hostile crosstalk This term means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel In general this will yield the worst crosstalk number but this is not always the case due to the
20. other than a given output 1N07 in the middle are programmed to connect to IN00 OUT07 is programmed to connect to IN15 far away from 1N00 which is terminated to ground Thus OUTO7 should not have a signal present since it is listening to a quiet input Any signal measured at the OUT07 can be attributed to the output crosstalk of the other 16 hostile outputs Again this method can be modified to measure other channels and other crosspoint matrix combinations Rev B Page 23 of 32 AD8114 AD8115 Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs The lower the impedance of the drive source the lower the magnitude of the crosstalk The dominant crosstalk mechanism on the input side is capacitive coupling The high impedance inputs do not have significant current flow to create magnetically induced crosstalk However significant current can flow through the input termination resistors and the loops that drive them Thus the PC board on the input side can contribute to magnetically coupled crosstalk From a circuit standpoint the input crosstalk mechanism looks like a capacitor coupling to a resistive load For low freguencies the magnitude of the crosstalk will be given by IXT 20 log lr Cu x s where Rs is the source resistance Cu is the mutual capacitance between the test signal circuit and the selected circuit and s is the Lapl
21. 0k 1M 10M FREGUENCY Hz Figure 27 AD81 14 Voltage Noise vs Frequency Rev B Page 14 of 32 80 OFF ISOLATION dB Lk io 2 0 o 8 6 120 130 140 01070 033 0 1 1 10 100 500 PSRR dB 170 90 VOLTAGE NOISE nV VHz 10 100 1k 10k 100k 1M 1 FREQUENCY MHz Figure 28 AD8115 Off Isolation Input Output 01070 034 FREQUENCY MHz Figure 29 AD8115 PSRR vs Frequency 01070 035 FREQUENCY Hz Figure 30 AD8115 Voltage Noise vs Frequency AD8114 AD8115 Vo z 200mV STEP Ri 1500 01070 036 01070 039 Vo 2V STEP Vo 200mV STEP 1 5V R 1500 1 5V R 1500 1 0V 1 0V 0 5V 0 5V ov ov 0 5V 0 5V 1 0V 1 0V 1 5V 1 5V 01070 037 01070 040 Figure 32 AD8114 Pulse Response Large Signal Figure 35 AD8115 Pulse Response Large Signal INPUTO AT 1V 01070 038 01070 041 Figure 33 AD8114 Switching Time Figure 36 AD8115 Switching Time Rev B Page 15 of 32 AD8114 AD8115 0 05V 0 05V 01070 042 01070 045 Figure 37 AD8114 Switching Transient Glitch Figure 40 AD8115 Switching Transient Glitch 220 200 a o o a 2B o
22. AD8115 are high density building blocks for creating crosspoint arrays of dimensions larger than 16 x 16 Various features such as output disable chip enable and gain of 1 and gain of 2 options are useful for creating larger arrays When reguired for customizing a crosspoint array size they can be used with the AD8108 and AD8109 a pair of unity gain and gain of 2 8 x 8 video crosspoint switches or with the AD8110 and AD8111 a pair of unity gain and gain of 2 16 x 8 video crosspoint switches The first consideration in constructing a larger crosspoint is to determine the minimum number of devices reguired The 16 x 16 architecture of the AD8114 AD8115 contains 256 points which is a factor of 64 greater than a 4 x 1 crosspoint or multiplexer The PC board area power consumption and design effort savings are readily apparent when compared to using these smaller devices For a nonblocking crosspoint the number of points reguired is the product of the number of inputs multiplied by the number of outputs Nonblocking reguires that the programming ofa given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs Some nonblocking crosspoint architectures will reguire more than this minimum as calculated above Also there are blocking architectures that can be constructed with fewer devices than this minimum These systems have connectivity available on a statistical basis
23. ANALOG DEVICES Low Cost 225 MHz 16 x 16 Crosspoint Switches AD8114 AD8115 FEATURES 16 x 16 high speed nonblocking switch arrays AD8114 G 1 AD8115 G 2 Serial or parallel programming of switch array Serial data out allows daisy chaining of multiple 16 x 16 arrays to create larger switch arrays High impedance output disable allows connection of multiple devices without loading the output bus For smaller arrays see the AD8108 AD8109 8 x 8 or AD8110 AD8111 16x 8 switch arrays Complete solution Buffered inputs Programmable high impedance outputs 16 output amplifiers AD8114 G 1 AD8115 G 2 Drives 150 O loads Excellent video performance 25 MHz 0 1 dB gain flatness 0 05 0 05 differential gain differential phase error Ri 1500 Excellent ac performance 3 dB bandwidth 225 MHz Slew rate 375 V us Low power of 700 mW 2 75 mW per point Low all hostile crosstalk of 70 dB 5 MHz Reset pin allows disabling of all outputs connected through a capacitor to ground provides power on reset capability 100 lead LOFP 14mm x 14mm APPLICATIONS Routing of high speed signals including Video NTSC PAL S SECAM YUV RGB Compressed video MPEG wavelet 3 level digital video HDB3 Datacomms Telecomms GENERAL DESCRIPTION The AD8114 AD8115 are high speed 16 x 16 video crosspoint switch matrices They offer a 3 dB signal bandwidth greater than 200 MHz and channel switch times of less than 50 ns
24. ace transform variable From the equation it can be observed that this crosstalk mechanism has a high pass nature it can be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers If the input is driven from a 75 O terminated cable the input crosstalk can be reduced by buffering this signal with a low output impedance buffer On the output side the crosstalk can be reduced by driving a lighter load Although the AD8114 AD8115 is specified with excellent differential gain and phase when driving a standard 150 O video load the crosstalk will be higher than the minimum obtainable due to the high output currents These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8114 AD8115 From a circuit standpoint this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor For low frequencies the magnitude of the crosstalk is given by XT 20 log Mxyxs R where Mxy is the mutual inductance of Output X to Output Y and R is the load resistance on the measured output This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing Ri The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length Rev B Page 24 of 32 PGB LAYOUT Extreme care must be exercis
25. bit serial shift register location addressed by AO to A3 0 0 X X X 1 X Data in the 80 bit shift register transfers into the parallel latches that control the switch array Latches are transparent X X X X X 0 X Asynchronous operation All outputs are disabled Remainder of logic is unchanged DO PARALLEL D1 DAT Ne ae el Emi T OUTPUT _ BS SS SSS SSS A ud SS pwe f e DATA OUT R D1 D QHD a QHD Q L Al DO zl Do L LI 511 nei DATAIN s D1 SERIAL Li Di D1 D1 aH ah ako ah apio o DO lcuk 19 cik H 3 D LI Di Di Di Di Di QHD ah akpak a DQ a DO 1 c T po L fs L ju D A AU ea ET mwa D1 Dagja app o a ni ki of a CLK LI GE J o ll a mu 5 Da ra Ewa pea pe UPDATE OUTO EN 5 a LI Rc 28 b Og K A0 K A1 K a2 5 a A3 9 K LI a O e o D o ba O usa T o m D LE D LE D LE D LE D LE D OUT14 OUT15 OUT15 OUT15 OUT15 OUT15 0 EN BO B1 B2 B3 EN CLR Q a Q a a RESET a a OUTPUT ENABLE p 01070 011 OUTPUT ENABLE SWITCH MATRIX Figure 4 Logic Diagram Rev B Page 7 of 32 AD8114 AD8115 ABSOLUTE MAXIMUM RATINGS Table 7 Parameter Rating Supply Voltage 12 0 V Internal Power Dissipation AD8114 AD8115 100 Lead 2 6 W Plastic LOFP ST Input Voltage Vs Output Short Circuit Duration Observe po
26. ction of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION Q 01070 004 0 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE C Figure 5 Maximum Power Dissipation vs Temperature the human body and test equipment and can discharge without detection Although this product features FANART TH ej proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy A electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev B Page 8 of 32 AD8114 AD8115 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 m L o Zee LI lt a 2 o E x E Q IZ Li zi lt lt ju O O O O O O O O O O lt Q t Q O G o co o o oblo 222222222 a a 00000 silsisisisisisisisisisisisisisisisisisilsisileilsisiis DVCC 1 75 DVCC cun DGND 2 74 DGND AGND 3 73 AGND INO8 4 72 INO7 AGND 5 71 AGND INO9 6 70 INO6 AGND 7 69 AGND IN10 8 68 INO5 AGND 9 67 AGND IN11 10 AD8114 AD8115 66 INO4 AGND 11 TOP VIEW 65 AGND IN12 12 Not to Scale 64 INO3 AGND 13 63 AGND IN13 14 62 INO2 AGND 15 61 AGND IN14 16 60 INO1 AGND 17 59 AGND IN15 18 58 INOO AGND 19 57 AGND
27. dB f 1 MHz 46 dB OPERATING TEMPERATURE RANGE Temperature Range Operating still air 40 to 85 C Bsa Operating still air 40 C W Rev B Page 4 of 32 TIMING CHARACTERISTICS SERIAL Table 2 Timing Characteristics AD8114 AD8115 Parameter Symbol Min Typ Max Unit Serial Data Setup Time ti 20 ns CLK Pulse Width t 100 ns Serial Data Hold Time ts 20 ns CLK Pulse Separation Serial Mode ta 100 ns CLK to UPDATE Delay ts 0 ns UPDATE Pulse Width te 50 ns CLK to DATA OUT Valid Serial Mode t 200 ns Propagation Delay UPDATE to Switch On or Off 50 ns Data Load Time CLK 5 MHz Serial Mode 16 us CLK UPDATE Rise and Fall Times 100 ns RESET Time s 200 ns Table 3 Logic Levels Vin Vit Von VoL li li lon lou RESET SER PAR RESET SER PAR DATA OUT DATA OUT RESET SER PAR RESET SER PAR DATA OUT DATA OUT CLK DATA IN CLK DATA IN CLK DATA IN CLK DATA IN CE UPDATE CE UPDATE CE UPDATE CE UPDATE 2 0 V min 0 8 V max 2 7 V min 0 5 V max 20 HA max 400 HA min 400 HA max 3 0 mA min 1 CLK LOAD DATA INTO 3 t t ON FALLING EDGE A DATA IN o our pa X OUT D3 OUT00 DO 1 LATCHED oom NT 0 TRANSPARENT t LATCHES DURING LOW LEVEL DATA OUT Figure 2 Timing Diagram Serial Mode Rev B Page 5 of 32 01070 002 AD8114 AD8115 TIMING CHARACTERISTICS PARALLEL Table 4 Timing Charac
28. e is used so that the impedance of the gain of 2 feedback network does not load the output Because no additional input buffering is necessary high input resistance and low input capacitance are easily achieved without additional signal degradation To control enable glitches it is recommended that the disabled output voltage be maintained within its normal enabled voltage range 3 3 V If necessary the disabled output can be kept from drifting out of range by applying an output load resistor to ground A flexible TTL compatible logic interface simplifies the programming of the matrix Both parallel and serial loading into a first rank of latches programs each output A global latch simultaneously updates all outputs A power on reset pin is available to avoid bus conflicts by disabling all outputs APPLICATIONS The AD8114 AD8115 have two options for changing the programming of the crosspoint matrix In the first optiona serial word of 80 bits can be provided that will update the entire matrix each time The second option allows for changing a single outputs programming via a parallel interface The serial option requires fevver signals but more time clock eycles for changing the programming while the parallel programming technigue reguires more signals but can change a single output at a time and reguires fewer clock cycles to complete programming Serial Programming The serial programming mode uses the device pins CE CLK DATA
29. ed If parallel programming is used to program one output then that output will be properly programmed but the rest of the device will have a random program state depending on the internal register content at power up Therefore when using parallel programming it is essential that all outputs be programmed to a desired state after power up This will ensure that the programming matrix is always in a known state From then on parallel programming can be used to modify a single output or more at a time In similar fashion if both CE and UPDATE are taken low after initial power up the random power up data in the shift register will be programmed into the matrix Therefore to prevent the crosspoint from being programmed into an unknown state do not apply low logic levels to both CE and UPDATE after power is initially applied Programming the full shift register one time to a desired state by either serial or parallel programming after initial power up will eliminate the possibility of programming the matrix to an unknown state To change an outputs programming via parallel programming SER PAR and UPDATE should be taken high and CE should be taken low The CLK signal should be in the high state The 4 bit address of the output to be programmed should be put on A0 to A3 The first four data bits DO to D3 should contain the AD8114 AD8115 information that identifies the input that gets programmed to the output that is addressed The fourth
30. ed to minimize additional crosstalk generated by the system circuit board s The areas that must be carefully detailed are grounding shielding signal routing and supply bypassing The packaging of the AD8114 AD8115 is designed to help keep the crosstalk to a minimum Each input is separated from each other input by an analog ground pin All of these AGNDs should be directly connected to the ground plane of the circuit board These ground pins provide shielding low impedance return paths and physical separation for the inputs All of these help to reduce crosstalk Each output is separated from its two neighboring outputs by an analog supply pin of one polarity or the other Each of these analog supply pins provides power to the output stages of only the two nearest outputs These supply pins provide shielding physical separation and a low impedance supply for the outputs Individual bypassing of each of these supply pins with a 0 01 uF chip capacitor directly to the ground plane minimizes high freguency output crosstalk via the mechanism of sharing common impedances Each output also has an on chip compensation capacitor that is individually tied to the nearby analog ground pins AGND00 through AGNDO7 This technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins These AGNDxx signals should all be connected directly to the ground plane The input
31. ent around the device As can be seen from Figure 53 this results in all 16 input signal traces and all 16 signal output traces having the same length This is useful in tests such as all hostile crosstalk where the phase relationship and delay between signals needs to be maintained from input to output The three power supply pins AVCC DVCC and AVEE should be connected to good quality low noise 5 V supplies Where the same 5 V power supplies are used for analog and digital separate cables should be run for the power supply to the evaluation board s analog and digital power supply pins As a general rule each power supply pin or group of adjacent power supply pins should be locally decoupled with a 0 01 uF capacitor If there is a space constraint it is more important to decouple analog power supply pins before digital power supply pins A 0 1 HF capacitor located reasonably close to the pins can be used to decouple a number of power supply pins Finally a 10 uF capacitor should be used to decouple power supplies as they come onto the board Rev B Page 25 of 32 AD8114 AD8115 uzu INPUTI4 S INPUT m eet uum AD8115 IK TU a Eu Tn l ye 1 l sruri iS ES Mm f K yem ES O pou de O Y T INPUTOS OUTPUTI2 e pe Pa N NN ouTpuTo9 INTERFACE ERIAL 5 OVTPUTOB OVIPUTOT OVTPUTOG K J
32. more than one analog circuit per video channel One 2 circuit format that is commonly being used in systems such as satellite TV digital cable boxes and higher guality VCRS is called S video or Y C video This format carries the brightness luminance or Y portion of the video signal on one channel and the color chrominance chroma or C on a second channel Since S video also uses two separate circuits for one video channel creating a crosspoint system reguires assigning one video channel to two crosspoint channels as in the case ofa differential video system Aside from the nature of the video format other aspects of these two systems will be the same There are yet other video formats using three channels to carry the video information Video cameras produce RGB red green blue directly from the image sensors RGB is also the usual format used by computers internally for graphics RGB can be converted to Y R Y B Y format sometimes called YUV format These 3 circuit video standards are referred to as component analog video The component video standards require three crosspoint channels per video channel to handle the switching function In a fashion similar to the 2 circuit video formats the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals CROSSTALK Many systems such as broadcast video that handle numerous analog signal channels have strict
33. oth CE and UPDATE initially after power up The shift register should first be loaded with the desired data and then UPDATE can be taken low to program the device The RESET pin has a 20 kO pull up resistor to DVDD that can be used to create a simple power up reset circuit A capacitor from RESET to ground will hold RESET low for some time while the rest of the device stabilizes The low condition will cause all the outputs to be disabled The capacitor will then charge through the pull up resistor to the high state thus allowing full programming capability of the device GAIN SELECTION The 16 x 16 crosspoints come in two versions depending on the gain of the analog circuit paths that is desired The AD8114 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired The AD8114 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used The AD8114 outputs have very high impedance when their outputs are disabled The AD8115 can be used for devices that will be used to drive a terminated cable with its outputs This device has a built in gain Rev B Page 19 of 32 AD8114 AD8115 of 2 that eliminates the need for a gain of 2 buffer to drive a video line Its high output disabled impedance minimizes signal degradation when paralleling additional outputs CREATING LARGER CROSSPOINT ARRAYS The AD8114
34. reguirements for keeping the various signals from influencing any of the others in the system Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel When there are many signals in close proximity in a system as will undoubtedly be the case in a system that uses the AD8114 AD8115 the crosstalk issues can be quite complex A good understanding of the nature of crosstalk and some definition of terms is reguired to specify a system that uses one or more AD8114 A D8115s Types of Crosstalk Crosstalk can be propagated by means of any of three methods These fall into the categories of electric field magnetic field and sharing of common impedances This section will explain these effects Every conductor can be both a radiator of electric fields and a receiver of electric fields The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance e g free space and couples with the receiver and induces a voltage This voltage is an unwanted crosstalk signal in any channel that receives it Currents flowing in conductors create magnetic fields that circulate around the currents These magnetic fields will then generate voltages in any other conductors whose paths they link The undesired induced voltages in these other channels are crosstalk signals The channels that crosstalk can be said to have a mutual inductance
35. ributing to crosstalk Rev B Page 22 of 32 Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel The measurement is usually expressed as dB down from the magnitude of the test signal The crosstalk is expressed by XT 20 log Asel s Atest s where s jw is the Laplace transform variable Asel s is the amplitude of the crosstalk induced signal in the selected channel and Atest s is the amplitude of the test signal It can be seen that crosstalk is a function of frequency but not a function of the magnitude of the test signal to first order In addition the crosstalk signal will have a phase relative to the test signal associated with it A network analyzer is most commonly used to measure crosstalk over a frequency range of interest It can provide both magnitude and phase information about the crosstalk signal As a crosspoint system or device grows larger the number of theoretical crosstalk combinations and permutations can become extremely large For example in the case of the 16 x 16 matrix of the AD8114 AD8115 we can examine the number of crosstalk terms that can be considered for a single channel say INO0 input INOO is programmed to connect to one of the AD8114 AD8115 outputs where the measurement can be made First we can measure the crosstalk terms associated with driving a test signal
36. s and can lower costs because they use lower cost cables connectors and termination methods They also have the ability to lower crosstalk and reject common mode signals which can be important for eguipment that operates in noisy environments or where common mode voltages are present between transmitting and receiving eguipment In such systems the video signals are differential there is a positive and negative or inverted version of the signals These complementary signals are transmitted onto each of the two wires of the twisted pair yielding a first order zero common mode voltage At the receive end the signals are differentially received and converted back into a single ended signal When switching these differential signals two channels are reguired in the switching element to handle the two differential Rev B Page 21 of 32 AD8114 AD8115 signals that make up the video channel Thus one differential video channel is assigned to a pair of crosspoint channels both input and output For a single AD8114 AD8115 eight differential video channels can be assigned to the 16 inputs and 16 outputs This will effectively form an 8 x 8 differential crosspoint switch Programming such a device will reguire that inputs and outputs be programmed in pairs This information can be deduced by inspection of the programming format of the AD8114 AD8115 and the reguirements of the system There are other analog video formats reguiring
37. teristics Parameter Symbol Min Typ Max Unit Data Setup Time ti 20 ns CLK Pulse Width t 100 ns Data Hold Time t 20 ns CLK Pulse Separation ta 100 ns CLKto UPDATE Delay ts 0 ns UPDATE Pulse Width t6 50 ns Propagation Delay UPDATE to Switch On or Off 50 ns CLK UPDATE Rise and Fall Times 100 ns RESET Time 200 ns Table 5 Logic Levels Vin Vi VoH Vo lin li lon lou RESET SER PAR RESET SER PAR DATA OUT DATAOUT RESET SER PAR RESET SER PAR DATA DATA CLK DO D1 D2 CLK DO D1 D2 CLK DO D1 D2 CLK DO D1 D2 OUT OUT D3 D4 A0 A1 A2 D3 D4 AO A1 A2 D3 D4 AO A1 A2 D3 D4 AO A1 A2 A3 CE UPDATE A3 CE UPDATE A3 CE UPDATE A3 CE UPDATE 400pA 30mA 2 0 V min 0 8 V max 2 7 V min 0 5 V max 20 HA max 400 HA min max min tp ta y CLK o ti i D0 D3 A0 A2 1 LATCHED 7 V TT UPDATE 0 TRANSPARENT Figure 3 Timing Diagram Parallel Mode Rev B Page 6 of 32 01070 003 AD8114 AD8115 Table 6 Operation Truth Table CE UPDATE CLK DATAIN DATA OUT RESET PAR Operation Comment 1 X X X X X X No change in logic 0 1 f Data Datai so 1 0 The data on the serial DATA IN line is loaded into serial register The first bit clocked into the serial register appears at DATA OUT 80 clocks later 0 1 f DO D4 NA in parallel mode 1 1 The data on the parallel data lines DO to D4 are AO A3 loaded into the 80
38. th 16 outputs each of which can be connected to any one of 16 inputs Organized by output rov 16 svvitchable transconductance stages are connected to each output buffer in the form of a 16 to 1 multiplexer Each of the 16 rows of transconductance stages are wired in parallel to the 16 input pins for a total array of 256 transconductance stages Decoding logic for each output selects one or none of the transconductance stages to drive the output stage The transconductance stages are NPN input differential pairs sourcing current into the folded cascode output stage The compensation netvvork and emitter follovver output buffer are in the output stage Voltage feedback sets the gain with the AD8114 configured as a unity gain follower and the AD8115 configured as a gain of 2 amplifier with a feedback network This architecture provides drive for a reverse terminated video load 150 Q with low differential gain and phase error for relatively low power consumption Power consumption is further reduced by disabling outputs and transconductance stages that are not in use The user will notice a small increase in input bias current as each transconductance stage is enabled Features of the AD8114 and AD8115 simplify the construction of larger switch matrices The unused outputs of both devices can be disabled to a high impedance state allowing the outputs of multiple ICs to be bused together In the case of the AD8115 a feedback isolation schem
39. that couples signals from one channel to another The power supplies grounds and other signal return paths ofa multichannel system are generally shared by the various channels When a current from one channel flows in one of these paths a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance All these sources of crosstalk are vector quantities so the magnitudes cannot simply be added together to obtain the total crosstalk In fact there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk Areas of Crosstalk For a practical AD8114 AD8115 circuit it is required that it be mounted to some sort of circuit board to connect it to power supplies and measurement eguipment Great care has been taken to create a characterization board also available as an evaluation board that adds minimum crosstalk to the intrinsic device This however raises the issue that a systems crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted It is important to try to separate these two areas of crosstalk when attempting to minimize its effect In addition crosstalk can occur among the inputs to a crosspoint and among the output It can also occur from input to output Technigues will be discussed for diagnosing which part of a system is cont
40. that is determined vvhen designing the overall system The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to vvire OR the outputs together in the vertical direction The meaning of horizontal and vertical can best be understood by looking at a diagram Figure 48 illustrates this concept for a 32 x 32 crosspoint array that uses four AD8114s or AD8115s AD8114 AD8114 N 00 15 OR OR AD8115 AD8115 AD8114 AD8114 IN 16 31 OR OR AD8115 AD8115 01070 048 Figure 48 32 x 32 Crosspoint Array Using AD8114 or Four AD8115s The inputs are each uniguely assigned to each of the 32 inputs of the two devices and terminated appropriately The outputs are wired ORed together in pairs The output from only one of a wire ORed pair should be enabled at any given time The device programming software must be properly written to cause this to happen Rev B Page 20 of 32 RANK 1 8 x AD8114 128 32 IN 00 15 gt AD8114 a RrERM V 8 IN 16 31 E AD8114 e RrERM V 8 IN 32 47 2 AD8114 a RrERM V 8 IN 48 63 RTERM V 8 IN 64 79 AD8114 s RTERM V 8 IN 80 95 AD8114 s RrERM V 8 IN 96 111 AD8114 RrERM V 8 IN 112 127 AD8114 16 RrERM V 1kQ AD8114 AD8115 RANK 2 32 16 NONBLOCKING 32 32 BLOCKING 8 OUT 00D15 AD8115 8 NONBLOCKING 8 ADDITIONAL AD8115 16 OUTPUTS 8 SUBJECT TO BLOCKING 01070 049 Figure 49 Nonblocking
41. urrent The channel switching is performed via a serial digital control which can accommodate daisy chaining of several devices or via a parallel control allowing updating ofan individual output without reprogramming the entire array The AD8114 AD8115 is packaged in 100 lead LOFP package and is available over the extended industrial temperature range of 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved AD8114 AD8115 TABLE OF GONTENTS AD8114 AD8115 Specifications a 3 Timing Characteristics Serial ee 5 Timing Characteristics Parallel sss 6 Absolute Maximum Ratings eene 8 Maximum Power Dissipation sse 8 ESD Caution cesset e iS 8 Pin Configuration and Function Descriptions 9 Typical Performance Characteristics sss ll VO Schema ient tere tide 17 Theory of Operation eren ette uu 18 Applications sein 18 REVISION HISTORY 9 05 Rev A to Rev B Updated Pormat auri ien Universal Change to Figure ips RU 6 Change to Absolute Maximum Ratings 8 Changes to Maximum Power Dissipation Section 8 Updated Outline Dimensions ss 2 31 Changes to Ordering Guide
42. use parallel programming There is no cable or software provided with the evaluation board for parallel programming These are left to the user to provide The software offers volatile and nonvolatile storage of configurations For volatile storage up to two configurations can be stored and recalled using the Memory 1 and Memory 2 buffers These function in a fashion identical to the memory on a pocket calculator For nonvolatile storage of a configuration the save setup and load setup functions can be used This stores the configuration as a data file on disk MOLEX 0 100 CENTER CRIMP TERMINAL HOUSING D SUB 25 PIN MALE RESET k 14 1 CLK CE o UPDATE DATA IN P s DGND SIGNAL 3 CE 1 RESET 4 UPDATE 5 DATA IN 2 6 CLK DGND 01070 058 EVALUATION BOARD PC Figure 58 Evaluation Board PC Connection Cable OVERSHOOT OF PC PRINTER PORTS DATA LINES The data lines on some printer ports have excessive overshoot Overshoot on the pin that is used as the serial clock Pin 6 on the D Sub 25 connector can cause communication problems This overshoot can be eliminated by connecting a capacitor from the CLK line on the evaluation board to ground A pad has been provided on the circuit side C33 of the evaluation board to allow this capacitor to be soldered into place Depending on the overshoot from the printer port this capacitor may need to be as large as 0 01 uE AD8114 AD8115
43. vector nature of the crosstalk signal Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side These crosstalk measurements will generally be higher than those of more distant channels so they can serve as a worst case measure for any other 1 channel or 2 channel crosstalk measurements Input and Output Crosstalk The flexible programming capability of the AD8114 AD8115 can be used to diagnose whether crosstalk is occurring more on the input side or the output side Some examples are illustrative A given input channel 1N07 in the middle for this example can be programmed to drive OUTO7 also in the middle The input to 1N07 is just terminated to ground via 50 O or 75 Q and no signal is applied All the other inputs are driven in parallel with the same test signal practically that is provided by a distribution amplifier with all other outputs except OUTO7 disabled Since grounded INO7 is programmed to drive OUT07 no signal should be present Any signal that is present can be attributed to the other 15 hostile input signals because no other outputs are driven They are all disabled Thus this method measures the all hostile input contribution to crosstalk into 1N07 Of course the method can be used for other input channels and combinations of hostile inputs For output crosstalk measurement a single input channel is driven 1N00 for example and all outputs
44. wer derating curves Storage Temperature Range 65 C to 125 C Specification is for device in free air TA 25 C 100 lead plastic LQFP ST 04 40 C W Maximum reflow temperatures are to JEDEC industry standard J STD 020 MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8114 AD8115 is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 125 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 125 C for an extended period can result in device failure While the AD8114 AD8115 are internally short circuit protected this may not be sufficient to guarantee that the maximum junction temperature 125 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves shown in Figure 5 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational se
45. with 1 settling With 70 dB of crosstalk and 90 dB isolation 5 MHz the AD8114 AD8115 are useful in many high speed applications The differential gain and differential phase of better than 0 05 and 0 05 respectively along with 0 1 dB Patent pending Rev B nformation furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or othervvise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM SER PAR DO D1 D2 D3 D4 80 BIT SHIFT REGISTER WITH 5 BIT DATA PARALLEL LOADING OUT SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF SWITCH MATRIX 16 16 INPUTS OUTPUTS 01070 001 Figure1 flatness out to 25 MHz vvhile driving a 75 O back terminated load make the AD8114 AD8115 ideal for all types of signal switching The AD8114 AD8115 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off channels do notload the output bus The AD8114 has a gain of 1 while the AD8115 offers a gain of 2 They operate on voltage supplies of 5 V while consuming only 70 mA of idle c
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ANALOG DEVICES AD8114/AD8115 English products handbook Rev B