ANALOG DEVICES ADV3226/ADV3227 English products handbook Rev 0
Contents
1. Parameter Rating Analog Supply Voltage AVCC AVEE 11V Digital Supply Voltage DVCC DGND 6V Supply Potential Difference 0 5V AVCC DVCC Ground Potential Difference 0 5V AGND DGND Maximum Potential Difference 6V DVCC AVEE Analog Input Voltage AVEE lt Vin lt AVCC Digital Input Voltage DGND lt Din lt DVCC Exposed Paddle Voltage AVEE lt Vin lt AVCC Output Voltage Disabled Analog lt Vour lt AVCC Output Output Short Circuit Duration Momentary Current Internally limited to 55 mA Temperature Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Junction Temperature 150 C Lead Temperature Soldering 300 C 10 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 6 Thermal Resistance POWER DISSIPATION The ADV3226 ADV3227 operate with 5 V supplies and can drive loads down to 100 Q resulting in a wide range of possible power dissipations For th2. Description 1 DVCC Digital Positive Power Supply 17 AGND Analog Ground 2 DGND Digital Ground 18 IN15 Input Number 15 3 AGND Analog Ground 19 AGND Analog Ground 4 08 Input Number 8 20 AVEE Analog Negative Supply 5 AGND Analog Ground 21 AVCC Analog Positive Supply 6 INO9 Input Number 9 22 AVCC Analog Positive Supply 7 AGND Analog Ground 23 OUT15 Output Number 15 8 IN10 Input Number 10 24 AVEE Analog Negative Supply 9 AGND Analog Ground 25 OUT14 Output Number 14 10 IN11 Input Number 11 26 AVCC Analog Positive Supply 11 AGND Analog Ground 27 OUT13 Output Number 13 12 IN12 Input Number 12 28 AVEE Analog Negative Supply 13 AGND Analog Ground 29 OUT12 Output Number 12 14 IN13 Input Number 13 30 AVCC Analog Positive Supply 15 AGND Analog Ground 31 OUT11 Output Number 11 16 IN14 Input Number 14 32 AVEE Analog Negative Supply Rev 0 Page 8 of 24 ADV3226 ADV3227 No Mnemonic Description Pin Mnemonic Description 33 OUT10 Output Number 10 68 05 Input Number 5 34 AVCC Analog Positive Supply 69 AGND Analog Ground 35 OUTO9 Output Number 9 70 06 Input Number 6 36 AVEE Analog Negative Supply 71 AGND Analog Ground 37 OUTO8 Output Number 8 72 07 Input Number 7 38 AVCC Analog Positive Supply 73 AGND Analog Ground 39 OUTO7 Output Number 7 74 DGND Digital Ground 40 AVEE Analog Negative Supply 75 DVCC Digital Positive Power Supp
3. ADV3227 Output Noise 100 Load ISOLATION dB ISOLATION dB 1 10 100 1k 10k FREQUENCY MHz Figure 27 ADV3226 Off Isolation Figure 30 ADV3227 Off Isolation 08653 033 08653 036 FREQUENCY MHz Rev 0 Page 14 of 24 ADV3226 ADV3227 0 0 IN3 OUT3 ENABLED CHANNEL IN3 OUT3 ENABLED CHANNEL IN2 ACTIVATED IN2 ACTIVATED 20 20 30 30 S 40 40 50 2 50 a 2 O 60 O 60 70 70 80 80 90 90 1 10 100 1k 8 1 10 100 8 FREQUENCY MHz 3 FREQUENCY MHz 3 Figure 31 ADV3226 Crosstalk One Adjacent Channel RTO Figure 34 ADV3227 Crosstalk One Adjacent Channel RTO 0 20 IN3 OUT3 ENABLED CHANNEL IN3 OUT3 ENABLED CHANNEL 10 0 20 30 20 2 B o 3 40 o 50 a 2 60 60 70 80 80 90 100 z 1 10 100 1k 8 1 10 100 1k amp FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 32 ADV3226 Crosstalk All Hostile RTO Figure 35 ADV3227 Crosstalk All Hostile RTO 1M 1M 100k 10
4. edge of CLK A total of 80 bits must be shifted in to complete the programming For each of the 16 outputs there are four bits DO to D3 that deter mine the source of its input The MSB is shifted in first A fifth bit D4 precedes the four input select bits and determines the enabled state of the output If D4 is low output disabled the four asso ciated bits DO to D3 do not matter because no input switches to that output The most significant output address data is shifted in first and the remaining addresses follow in sequence until the least signifi cant output address data is shifted in At this point UPDATE can be taken low which programs the device according to the Rev 0 Page 21 of 24 ADV3226 ADV3227 data that was just shifted in The update registers are asynchronous and when UPDATE is low and CE is low they are transparent If more than one ADV3226 ADV3227 device is to be serially programmed in a system the DATAOUT signal from one device can be connected to the DATAIN of the next device to form a serial chain Connect all of the CLK CE UPDATE and SER PAR pins in parallel and operate them as described previously in this section The serial data is input to the DATAIN pin of the first device of the chain and it ripples through to the last Therefore the data for the last device in the chain should come at the beginning of the programming sequence The length of the programming sequence 80 bits is multip
5. 0k A 10k 10k 2 2 5 1k 5 1k a a gt gt 100 100 10 10 1 2 1 T 0 01 0 1 1 10 100 1k 10k 8 0 01 0 1 1 10 100 1k 10k 5 FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 33 ADV3226 Input Impedance Figure 36 ADV3227 Input Impedance Rev 0 Page 15 of 24 ADV3226 ADV3227 1M 1M 100k 100k 10k 10k Z ak 1k 8 8 ul n n z z 400 400 10 10 1 o 1 0 1 1 10 100 1 10k 3 0 1 1 10 100 1k 10k 5 FREQUENCY MHz 5 FREQUENCY MHz 5 Figure 37 ADV3226 Output Impedance Disabled Figure 40 ADV3227 Output Impedance Disabled 100 100 10 10 lt lt ul ul n n z z 1 0 1 n 0 1 01 1 10 100 1k 5 0 1 1 10 100 1k 3 FREQUENCY MHz FREQUENCY MHz Figure 38 ADV3226 Output Impedance Enabled Figure 41 ADV3227 Output Impedance Enabled 2 0 3 5 UPDATE UPDATE i 1 5 3 0 ISING EDGE Vour RISING EDGE 1 0 2 5 0 5 20 _ 2 gt 2 E 1 5 2 lt 2 gt gt gt 0 5 10 2 Vout FALLING EDGE 1 0 0 5 1 5 0 2 0 05 10 0 10 20 30 3 10 0 10 20 30 i TIME ns TIME ns 5 Figure 39 ADV3226 Switching Time Figure 4
6. 2 ADV3227 Switching Time Rev 0 Page 16 of 24 ADV3226 ADV3227 20 10 Vout mV Vout mV 40 50 0 5 10 15 20 25 30 35 40 45 50 TIME ns 0 5 10 15 20 25 30 35 40 45 50 TIME ns Figure 43 ADV3226 Switching Glitch Figure 46 ADV3227 Switching Glitch 08653 046 08653 049 UPDATE ISING EDGE Vour V UPDATE V Vour V UPDATE V Vour FALLING EDGE 10 0 10 20 30 8 3 TIME ns TIME ns 8 Figure 44 ADV3226 Enable Time Figure 47 ADV3227 Enable Time 0 040 0 025 0 035 0 020 0 030 9 0 025 amp 0 015 ul ul z z 0 020 0 010 al 2 0 015 0 005 0 010 o ul 0 005 i a 0 0 0 005 0 005 08 06 04 02 0 0 2 0 4 0 6 0 8 INPUT DC OFFSET V 08 06 3 04 02 0 0 2 0 4 0 6 0 8 INPUT DC OFFSET V Figure 45 ADV3226 Differential Gain Error Figure 48 ADV3227 Differential Gain Error 08653 051 08653 054 Rev 0 Page 17 of 24 ADV3226 ADV3227 0 0020 0 008 A 0 006 0 0015 8 0 004 a a 4 1 4 0 0010 0 002 2 2 r4 r4 0 0 0005 0 E 0 002 a E 0 E 0 004 0 006 0 0005 5 5 0 008 0 0010 0 010 08 06 04 0
7. 2 0 0 2 0 4 0 6 0 8 INPUT DC OFFSET V 08 06 3 04 02 0 0 2 0 4 0 6 0 8 INPUT DC OFFSET V 08653 052 08653 055 Figure 49 ADV3226 Differential Phase Error Figure 52 ADV3227 Differential Phase Error 6 Vin 34 55 Vin 34 65 Mus 4 mL gt 5 ST 8 9 9 4 1 al al 1 1 9 9 I gt gt 1 2 e Vout Vin 24 65 4 6 8 0 10 20 30 40 50 60 70 80 90 100 5 TIME ns TIME ns 8 Figure 50 ADV3226 Overdrive Recovery Figure 53 ADV3227 Overdrive Recovery 25 60 20 5 a 40 2 15 z W Es E 30 n 8 10 20 z5 40 0 0 e 10 100 1k 8 10 100 1k 8 INPUT FREQUENCY MHz 8 INPUT FREQUENCY MHz E Figure 51 ADV3227 1 dB Gain Compression 100 O Load Figure 54 ADV3227 Third Order Intercept 100 Load Rev 0 Page 18 of 24 SECOND ORDER dBm NUMBER OF HITS INPUT FREQUENCY MHz Figure 55 ADV3227 Second Order Intercept 100 Load 140 120 100 80 60 40 20 0 30 25 20 15 10 5 15 20 25 30 COUNT Figure 56 ADV3226 and ADV3227 Input Vos Distribution HARMONIC DISTORTION
8. 64 greater than a 4 x 1 crosspoint or multiplexer The benefits realized in PCB area used power consumption and design effort are readily apparent when compared to using multiples of these smaller 4 x 1 devices To obtain the minimum number of required points for a non blocking crosspoint multiply the number of inputs by the number of outputs Nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs Some nonblocking crosspoint architectures require more than this minimum In addition there are blocking architectures that can be constructed with fewer devices than this minimum These systems have connectivity available on a statistical basis that is determined when designing the overall system The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wire OR the outputs together in the vertical direction The meaning of horizontal and vertical can best be understood by referring to Figure 65 which illustrates this concept for a 32 x 32 crosspoint array that uses four ADV3226 or ADV3227 devices IN 00 15 16 31 08653 062 Figure 65 32 x 32 Nonblocking Crosspoint Switch Array Each input is uniquely assigned to each of the 32 inputs ofthe two devices and terminated appropriately The outputs are wired ORed together in pairs Enable the output
9. 750 MHz 2V p p 600 750 MHz Gain Flatness 0 1 dB 2V p p 130 60 MHz 0 5 dB 2 V p p 2 2 pF 400 200 MHz Propagation Delay 2V p p 0 6 0 6 ns Settling Time 1 2 V step 3 3 ns Slew Rate 2V step peak 2150 2950 V us NOISE DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL 0 04 0 02 96 Differential Phase Error NTSC or PAL 0 01 0 01 Degrees Crosstalk Hostile 100 2 45 35 5 MHz 75 60 Off Isolation Input to Output 100 MHz one channel 80 75 IMD2 100 MHz 1000 47 dBm 500 MHz 1000 22 dBm IMD3 100 MHz Ri 1000 42 dBm 500 MHz 1000 14 dBm Output 1 dB Compression Point 100 MHz 1000 18 dBm 500 MHz Ri 1000 9 dBm Input Voltage Noise 0 01 MHz to 50 MHz 16 16 nV VHz DC PERFORMANCE Gain Error 0 1 1 0 0 4 1 5 Gain Matching Channel to channel 1 0 1 5 Gain Temperature Coefficient 0 8 16 OUTPUT CHARACTERISTICS Output Resistance DC enabled 0 2 0 2 Q DC disabled 10 5 MQ Output Disabled Capacitance 2 7 2 7 pF Output Leakage Current Output disabled 1 1 yA Output Voltage Range No load 3 3 1500 2 8 2 8 V Short circuit current 55 55 mA INPUT CHARACTERISTICS Input Offset Voltage Worst case all configurations 5 5 Input Offset Voltage Drift 8 8 Input Voltage Range No load t3 1 5 1500 3 1 5 V Input Capacitance Any switch configuration 2 1 2 1 pF Input Resistance 2 2 MO Input Bias Current Any switch configuratio
10. ANALOG DEVICES 750 MHz 16 x 16 Analog Crosspoint Switch ADV3226 ADV3227 FEATURES 16 x 16 high speed nonblocking switch array Pinout and functionally equivalent to the AD8114 AD8115 Complete solution Buffered inputs Programmable high impedance outputs 16 output amplifiers G 1 ADV3226 G 2 ADV3227 Drives 150 loads Operates on 5 V supplies Low power 1 3 W Excellent ac performance 3 dB bandwidth 200 mV p p 820 MHz ADV3226 750 MHz ADV3227 2V p p 600 MHz ADV3226 750 MHz ADV3227 Slew rate 2150 V us ADV3226 2950 V us ADV3227 Serial or parallel programming of switch array 100 lead LFCSP 12 mm x 12 mm APPLICATIONS Routing of high speed signals including Video NTSC PAL S SECAM YUV RGB Compressed video MPEG wavelet 3 level digital video HDB3 Data communications Telecommunications GENERAL DESCRIPTION The ADV3226 ADV3227 are high speed 16 x 16 analog crosspoint switch matrices They offer a 3 dB signal bandwidth greater than 750 MHz and channel switch times ofless than 20 ns with 196 settling The ADV3226 ADV3227 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus The ADV3226 has a gain of 1 and the ADV3227 has a gain of 2 They both operate on voltage supplies of 5 V Rev 0 FUNCTIONAL BLOCK DIAGRAM SER PAR 00 D1 02 D3 D4 SET INDIV
11. D Analog Ground 1 N A means not applicable 66 04 Input Number 4 67 AGND Analog Ground Rev 0 Page 9 of 24 ADV3226 ADV3227 TRUTH TABLE AND LOGIC DIAGRAM Table 8 Operation Truth Table CE UPDATE CLK DATAIN DATAOUT RESET SER PAR Description 1 X X X X X X No change in logic X Data Datai so X 0 The data on the serial DATAIN line is loaded into the serial register The first bit clocked into the serial register appears at DATAOUT 80 clock cycles later 0 X 0 DO D4 N A in X 1 The data on the parallel data lines DO to D4 are loaded into the parallel 80 bit serial shift register location addressed at AO to A3 0 0 X X X 1 X Data in the 80 bit shift register transfers into the parallel latches that control the switch array Latches are transparent X X X X X 0 X Asynchronous operation All outputs are disabled Second rank latches are cleared Remainder of logic is unchanged 1X is don t care serial data 3 N A means not applicable 4 DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register PARALLEL D1 DATA p L 4 ___ ___________ ____ OUTPUT Bem ec ENABLE P QHD E QHD E M QHD Q M QHD 3 DQ E Do E Do em DO Do Do E la 134 D1 01 QHD E SERIPAR DATA IN NI ek x d SE
12. IDUAL OR RESET ALL OUTPUTS TO OFF 16 OUTPUT ADV3226 BUFFER ADV3227 E E E E E E E VIVIV VIV SWITCH MATRIX 16 INPUTS VIVIVIV 16 OUTPUTS 08653 001 Figure 1 while consuming only 118 mA ADV3226 and 133 mA ADV3227 of idle current Channel switching is performed via a serial digital control that can accommodate daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array The ADV3226 ADV3227 are available in the 100 lead LFCSP package over the extended industrial temperature range of 40 C to 85 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 Analog Devices Inc All rights reserved ADV3226 ADV3227 TABLE OF CONTENTS iie uin HEU M IM MM UD DEDIT Applications tee tenent ether et ette EE General D
13. IGNAL ze 0 10 R 1500 1500 Vout 200mV p p Vout 200mV _ 0 15 x TIME ns E TIME ns 8 Figure 14 ADV3226 Small Signal Pulse Response Figure 17 ADV3227 Small Signal Pulse Response OUTPUT SIGNAL INPUT SIGNAL 18 OUTPUT SIGNAL Vout V Vout V Vout 2V 0 2 4 6 8 10 12 14 16 20 5 5 TIME ns 5 TIME ns 8 Figure 15 ADV3226 Large Signal Pulse Response Figure 18 ADV3227 Large Signal Pulse Response Rev 0 Page 12 of 24 PULSE RISING ED SLEW RATE Vis 0 05 10 15 20 25 30 35 40 TIME ns Figure 19 ADV3226 Rising Edge Slew Rate 2 0 500 SLEW RATE 1 5 0 1 0 500 PULSE FALLING EDGE ug a e e SLEW RATE Vius 1 0 2500 1 5 3000 2 0 3500 0 05 10 15 20 25 30 35 40 45 50 TIME ns Figure 20 ADV3226 Falling Edge Slew Rate OUTPUT INPUT OUTPUT ERROR PUT SIGNAL PROPAGATION DELAY NOT SHOWN 740 05 0 05 10 15 20 25 30 35 40 TIME ns Figure 21 ADV3226 Settling Time 08653 026 08653 120 08653 027 ADV3226 ADV3227 PULSE RISING ED 0 05 10 15 20 25 30 35 40 45 50 TIME ns Figure 22 ADV3227 Rising Edge Slew Rate 0 05 10 15 20 25 30 35 40 45 50 TIME ns Figu
14. RIAL al 5 oa UPDATE OUTPUT ADDRESS gt gt A3 4TO 16 DECODER H L L D LE D LE D LE D LE D ours OUTO OUTO OUTO ours OUT1 OUT15 OUT15 OUT15 B1 B2 B3 Bo Bo B1 B2 256 16 SWITCH MATRIX OUTPUT ENABLE Figure 6 Logic Diagram 08653 006 Rev 0 Page 10 of 24 ADV3226 ADV3227 8 H 6 5 4 3 li 2 1 0 5 iJ z 4 5 T 3 4 5 6 7 1500 8 Ri 1500 Vout 200 9 Vout 200 EN 5 1 10 100 1k 10k 5 FREQUENCY MHz E FREQUENCY MHz Figure 7 ADV3226 Small Signal Frequency Response Figure 10 ADV3227 Small Signal Frequency Response 1 8 7 0 6 1 5 4 2 3 2 3 1 a 2 2 z z 1 4 5 2 o 3 4 27 5 6 8 7 29 1500 8 F 1500 Vout 2V 9 Vout 2
15. V 10 10 1 10 100 1 10k 5 1 10 100 1k 10k 2 FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 8 ADV3226 Large Signal Frequency Response Figure 11 ADV3227 Large Signal Frequency Response 6 12 5 4 10 4pF 10 10 4 3 5 0pF 8 5 0pF 2 i 6 2 2pF 0 2 2 4 S a4 EN 1 2pF T l 5 2 1 2 kJ 2 OpF i OpF 2 0 4 z 5 7 5 4 2 5 6 4 7 6 8 R 1500 g 1500 9 Vout 200mV 200 10 5 10 o 1 10 100 1k 10k 2 1 10 100 1k 10k FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 9 ADV3226 Small Signal Frequency Response with Capacitive Loads Figure 12 ADV3227 Small Signal Frequency Response R 1500 Rev 0 Page 11 of 24 ADV3226 ADV3227 4 3 10 4pF 2 5 0pF 1 2 2pF 1 2 1 2pF a kJ kJ z 3 lt OpF lt o 4 5 6 7 8 R 1500 1500 79 F Vour 2V Vout 2V 10 E 1 10 100 1k 10k 8 100 3 FREQUENCY MHz 5 FREQUENCY MHz 3 Figure 13 ADV3226 Large Signal Frequency Response with Capacitive Loads Figure 16 ADV3227 Large Signal Frequency Response with Capacitive Loads 0 15 0 10 0 05 5 0 o INPUT SIGNAL gt 2905 INPUT S
16. age dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 7 of 24 ADV3226 ADV3227 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS eed o s5Hg9g927999992g2xa3g85888 Slalsisislsiisisisislsisilslsisislsisllsiisi sel serie DJe n 75 DGND 2 74 DGND AGND 3 73 AGND 4 72 INO7 AGND 5 71 AGND 6 70 06 AGND 7 69 AGND Into 68 INOS AGND 9 67 AGND 5 ADV3226 ADV3227 AGND 11 TOP VIEW 65 AGND IN12 12 Not to Scale 64 INO3 AGND 13 63 AGND IN13 14 62 IN02 AGND 15 61 AGND IN14 16 60 1401 AGND 17 59 AGND IN15 18 58 00 AGND 19 57 AGND 20 56 avcc 21 55 avcc Avcc 22 54 avcc 15 23 53 OUTOO 24 52 14 25 51 1 2 1518181815 2 2 5 5 2 5 2 SEH ES EU ES EU ESERESERESERES lt 55 lt 5 lt 5 lt 5 lt 5 lt 59 lt 54 lt 050 lt 54 lt 65 lt 0 lt 654 lt NOTES 1 NC NO CONNECT 2 THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS Table 7 Pin Function Descriptions Figure 5 Pin Configuration 08653 005 Pin No Mnemonic Description Pin No Mnemonic
17. dBc 08653 058 08653 156 Rev 0 Page 19 of 24 ADV3226 ADV3227 HD3 10dBm INPUT FREQUENCY MHz Figure 57 ADV3227 Harmonic Distortion Input Referred 100 Load 1k 08653 061 ADV3226 ADV3227 CIRCUIT DIAGRAMS INx OUTx 2 1pF 08653 007 Figure 58 Analog Input OUTx 08653 010 Figure 59 Analog Output Enabled AVCC AGND DVCC AGND DGND Figure 60 ESD Map CLK RESET SERI PAR CE UPDATE DATAIN DATAOUT A 3 0 D 4 0 08653 013 Rev 0 Page 20 of 24 A 3 0 CE CLK 1kQ D 4 0 DATAIN SER PAR UPDATE 08653 008 DGND Figure 61 Logic Input OUTx 2 7pF 7 Figure 62 Analog Output Disabled 08653 011 DVCC 20kQ __ 1kQ RESET 08653 009 DGND Figure 63 Reset Input DVCC DATAOUT DGND 08653 012 Figure 64 Logic Output ADV3226 ADV3227 THEORY OF OPERATION The ADV3226 G 1 and ADV3227 G 2 crosspoint arrays with 16 outputs each of which can be connected to any one of 16 inputs Organized by output row 16 switchable input transconductance stages are connected to each output buffer to form 16 to 1 multiplexers There are 16 of these multiplexers each with its inputs wired in parallel for a total array of 256 trans conductance stages forming a multicast capable crosspoint switch Each input is buffered and is not loaded by the outputs simplifyin
18. erial output buffer is a rail to rail output stage with 5 mA of drive capability APPLICATIONS INFORMATION The ADV3226 ADV3227 have two options for changing the programming of the crosspoint matrix In the first option a serial word of 80 bits can be provided which updates the entire matrix each time the 80 bit word is shifted into the part The second option allows for changing the programming of a single output via a parallel interface The serial option requires fewer signals but more time clock cycles for changing the program ming whereas the parallel programming technique requires more signals but can change a single output at a time and requires fewer clock cycles to complete the programming Serial Programming The serial programming mode uses the CE CLK DATAIN UPDATE and SER PAR pins The first step is to assert a low on SER PAR to enable the serial programming mode CE for the chip must be low to allow data to be clocked into the device The CE signal can be used to address an individual device when devices are connected in parallel The UPDATE signal should be high during the time that data is shifted into the serial port of the device Although the data still shifts in when UPDATE is low the transparent asynchronous latches allow the shifting data to reach the matrix which causes the matrix to try to update to every intermediate state as defined by the shifting data The data at DATAIN is clocked in at every falling
19. escription dante tet tette etr Ie IRR Functional Block Diagram senten Revision History oic E ORERRRREE ORNARE te latin tete Timing Characteristics Serial sss Logic Levels zit nti RH iSt eis Timing Characteristics Parallel sss Absolute Maximum Ratings esee Thermal Resistance eerte tentent Power DISsIDatiOn OS E REVISION HISTORY 4 10 Revision 0 Initial Version ESD Cautionzziiie eter pe ee RHEINE 7 Pin Configuration and Function Descriptions ss 8 Truth Table and Logic Diagram sse 10 Typical Performance Characteristics see 11 Circuit uice eR ERREUR EXER IAEA 20 Theory of Operation siete oreet es Pre titt totis 21 Applications Information eene 21 Power On Reset iere tite et eite 22 Gain Selections uec EET NE inris 22 Creating Larger Crosspoint 23 Outline Dimensions Neinar A 24 Ordering Guide SE AE 24 Rev 0 Page 2 of 24 ADV3226 ADV3227 SPECIFICATIONS Vs 5 V Ta 25 C Ri 150 unless otherwise noted Table 1 ADV3226 ADV3227 Parameter Test Conditions Comments Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth 200 mV p p 820
20. from only one wire ORed pair at any given time The device programming software must be properly written to prevent multiple connected outputs from being enabled at the same time For a complete 32 x 32 array in a single device refer to the AD8117 and AD8118 for high bandwidth or the ADV3200 and ADV3201 for lower bandwidth Also available are 32 x 16 arrays a single package AD8104 AD8105 ADV3202 and ADV3203 Rev 0 Page 23 of 24 ADV3226 ADV3227 OUTLINE DIMENSIONS 12 00 0 60 MAX 0 25 BSC SQ PIN 1 INDICATOR PIN 1 INDICATOR EXPOSED PAD 7 00 BOTTOM VIEW 6 90 SQ 6 80 0 20 MIN TOP VIEW 12 0 85 5 Fs 0 60 FOR PROPER CONNECTION OF 250 n 0 05 MAX THE EXPOSED PAD REFER TO CARRARA 0 01 NOM EAM AND SEATING SECTION OF THIS DATA SHEET PLANE 0 20 REF COMPLIANT TO JEDEC STANDARDS MO 220 VRRE Figure 66 100 Lead Lead Frame Chip Scale Package LFCSP VO 12 x 12 mm Body Very Thin Quad CP 100 1 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADV3226ACPZ 40 C to 85 C 100 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 100 1 ADV3227ACPZ 40 C to 85 C 100 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 100 1 ADV3226 EVALZ ADV3227 EVALZ Evaluation Board Evaluation Board 17 RoHS Compliant Part 2010 Analog Devices Inc A
21. g the construction of larger arrays using the ADV3226 or ADV3227 as a building block Decoding logic for each output selects one or none of the transconductance stages to drive the output stage The enabled transconductance stage drives the output stage and feedback forms a closed loop amplifier A mask programmable feedback network sets the closed loop signal gain For theADV3226 this gain is 1 and for the ADV3226 this gain is 2 The output stage of the ADV3226 or ADV3227 is designed for low differential gain and phase error when driving composite video signals It also provides slew current for a fast pulse response when driving component video signals Unlike many multiplexer designs these requirements are balanced such that large signal bandwidth is very similar to small signal bandwidth The design load is150 but provisions are made to drive loads as low as 100 when on chip power dissipation limits are not exceeded The outputs of the ADV3226 ADV3227 can be disabled to mini mize on chip power dissipation When disabled there is no feedback network loading the output This high disabled output impedance allows multiple ICs to be bussed together without additional buffering Care must be taken to reduce output capa citance which results in more overshoot and frequency domain peaking A series of internal amplifiers drives internal nodes such that a wideband high impedance is presented at the disabled output even while the
22. ime 30 ns Timing Diagram Serial Mode CLK LOAD DATA INTO 0 SERIAL REGISTER ON FALLING EDGE 1 DATAIN D3 1 LATCHED UPDATE TRANSFER DATA FROM SERIAL 0 2 TRANSPARENT REGISTER TO PARALLEL t LATCHES DURING LOW LEVEL DATAOUT 08653 002 Figure 2 Timing Diagram Serial Mode LOGIC LEVELS Table 3 Logic Levels Vu Vou li lin lu lou lo RESET SER PAR RESET SER PAR DATAOUT DATAOUT SER PAR SER PAR CLK RESET RESET DATAOUT DATAOUT CLK DATAIN CLK DATAIN CLK DATAIN DATAIN CE CE UPDATE CE UPDATE CE UPDATE UPDATE 2 0 V min 0 8 V max 2 4 V min 0 4 2 uA max 2 uA max 2 uA max 300 uA 3mA 1 mA min Rev 0 Page 5 of 24 ADV3226 ADV3227 TIMING CHARACTERISTICS PARALLEL Table 4 Parameter Symbol Min Typ Max Unit Parallel Data Setup Time tid 10 ns Address Setup Time tha 10 ns CLK Pulse Width t2 10 ns Parallel Data Hold Time tsa 10 ns Address Hold Time 10 ns CLK Pulse Separation t4 20 ns UPDATE Pulse Width ts 10 ns CLK UPDATE Rise and Fall Times 50 ns RESET Time 30 ns Timing Diagram Parallel Mode DO TO D4 0 1 LATCHED 4 UPDATE 0 TRANSPARENT 08653 003 Figure 3 Timing Diagram Parallel Mode Rev 0 Page 6 of 24 ADV3226 ADV3227 ABSOLUTE MAXIMUM RATINGS Table 5
23. is reason extra care must be taken when derating the operating conditions based on ambient temperature Packaged in the 100 lead LFCSP the ADV3226 ADV3227 junction to ambient thermal impedance is 26 C W For long term reliability the maximum allowed junction temperature of the die should not exceed 125 C even temporarily exceeding this limit can cause a shift in parametric performance due to a change in stresses exerted on the die by the package Exceeding a junction temperature of 150 C for an extended period can result in device failure In Figure 4 the curve shows the range of allowed internal die power dissipation that meets these conditions over the 40 C to 85 C ambient temperature range When using Figure 4 do not include the external load power in the maximum power calculation but do include the load current dropped on the die output transistors 6 5 ISS MAXIMUM POWER W 2 I TL 15 25 35 45 55 65 75 AMBIENT TEMPERATURE C 2 Ty 150 C 8 5 08653 004 Figure 4 Maximum Die Power Dissipation vs Ambient Temperature Package Type War Unit 100 Lead LFCSP 26 2 56 9 5 0 2 8 9 C W ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry dam
24. lied by the number of devices in the chain Parallel Programming When using the parallel programming mode it is not necessary to reprogram the entire device when making changes to the matrix Parallel programming allows the modification of a single output at a time Because this takes only one CLK UPDATE cycle signifi cant time savings can be realized by using parallel programming An important consideration in using parallel programming is that the RESET signal does not reset all registers in the ADV3226 ADV3227 When taken low the RESET signal sets each output to the disabled state This is helpful during power up to ensure that two parallel outputs are not active at the same time After initial power up the internal registers in the device generally contain random data even though the RESET signal was asserted If parallel programming is used to program one output that output is properly programmed but the rest of the device has a random program state depending on the internal register content at power up Therefore when using parallel programming it is essential that all outputs be programmed to a desired state after power up to ensure that the programming matrix is always in a known state From this point parallel pro gramming can be used to modify either a single output or multiple outputs at one time Similarly if both CE and UPDATE are taken low after initial power up the random power up data in the shift regi
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26. ly 41 00706 Output Number 6 76 D4 Parallel Data Input Output Enable 42 AVCC Analog Positive Supply 77 D3 Parallel Data Input 43 OUTO5 Output Number 5 78 D2 Parallel Data Input 44 AVEE Analog Negative Supply 79 D1 Parallel Data Input 45 OUTOA Output Number 4 80 DO Parallel Data Input 46 AVCC Analog Positive Supply 81 A3 Parallel Data Input 47 OUTO3 Output Number 3 82 A2 Parallel Data Input 48 AVEE Analog Negative Supply 83 Al Parallel Data Input 49 OUTO2 Output Number 2 84 0 Parallel Data Input 50 AVCC Analog Positive Supply 851093 NC No Connect 51 OUTO1 Output Number 1 94 SER PAR Serial Parallel Mode Select Control Pin 52 AVEE Analog Negative Supply 95 UPDATE Second Rank Write Strobe Control Pin 53 OUTOO Output Number 0 96 DATAIN Serial Data In Control Pin 54 AVCC Analog Positive Supply 97 CLK Serial Data Clock Parallel 1st rank latch 55 AVCC Analog Positive Supply enable control pin 56 AVEE Analog Negative Supply 98 DATAOUT Serial Data Out 57 AGND Analog Ground 99 CE Chip Enable Control Pin 58 INOO Input Number 0 100 RESET Second Rank Reset Control Pin 59 AGND Analog Ground Exposed Paddle The exposed metal 60 INO1 Input Number 1 paddle on the bottom of the LFCSP 61 AGND Analog Ground package must be soldered to the PCB 62 INO2 Input Number 2 ground for proper heat dissipation and 63 AGND Analog Ground 22 mechanical strength 64 INO3 Input Number 3 65 AGN
27. n 1 1 pA Rev 0 Page 3 of 24 ADV3226 ADV3227 ADV3226 ADV3227 Parameter Test Conditions Comments Min Typ Max Min Typ Max Unit SWITCHING CHARACTERISTICS Enable Disable Time 5096 UPDATE to 196 settling 20 20 ns Switching Time 2 V Step 5096 UPDATE to 196 settling 20 20 ns Switching Transient Glitch 40 65 mV p p POWER SUPPLIES Supply Current AVCC outputs enabled no load 110 130 125 140 mA AVCC outputs disabled 25 35 25 35 mA AVEE outputs enabled no load 110 130 125 140 mA AVEE outputs disabled 25 35 25 35 mA DVCC outputs enabled no load 8 10 8 10 mA Supply Voltage Range 45 5 5 5 45 5 5 5 V PSRR DC to 50 kHz AVCC AVEE gt 60 gt 60 dB f 100 kHz AVCC AVEE 55 60 dB 10 MHz AVCC 45 40 dB f 10 MHz AVEE 35 55 dB 100 kHz DVCC 90 80 dB OPERATING TEMPERATURE RANGE Temperature Range Operating still air 40 85 40 85 C Operating still air 26 26 C W Rev 0 Page 4 of 24 ADV3226 ADV3227 TIMING CHARACTERISTICS SERIAL Table 2 Parameter Symbol Min Typ Max Unit Serial Data Setup Time ti 10 ns CLK Pulse Width t 10 ns Serial Data Hold Time ts 10 ns CLK Pulse Separation Serial Mode ta 10 ns CLK to UPDATE Delay ts 10 ns UPDATE Pulse Width te 10 ns CLK to DATAOUT Valid Serial Mode t 50 ns Propagation Delay UPDATE to Switch On or Off 20 ns Data Load Time CLK 5 MHz Serial Mode 1 6 us CLK UPDATE Rise and Fall Times 50 ns RESET T
28. ode the CLK pin is level sensitive whereas in serial mode it is edge triggered POWER ON RESET When powering up the ADV3226 ADV 3227 it is usually desirable to have the outputs come up in the disabled state When taken low the RESET pin causes all outputs to be in the disabled state However the RESET signal does not reset all registers in the ADV3226 ADV3227 This is important when operating in the parallel programming mode Refer to the Parallel Programming section for information about programming internal registers after power up Serial programming programs the entire matrix each time therefore no special considerations apply Because the data in the shift register is random after power up it should not be used to program the matrix or the matrix can enter unknown states To prevent the matrix from entering unknown states do not apply logic low signals to both CE and UPDATE initially after power up Instead first load the shift register with the data and then take UPDATE low to program the device The RESET pin has a 20 pull up resistor to DVCC that can be used to create a simple power up reset circuit A capacitor from RESET to ground holds the RESET pin low for a period during which the rest of the device stabilizes The low condition causes all of the outputs to be disabled The capacitor then charges through the pull up resistor to the high state thereby allowing full programming capability of
29. output bus is under large signal swings To keep these internal amplifiers in their linear range of operation when the outputs are disabled and driven externally do not allow the voltage applied to them to exceed the valid output swing range for the ADV3226 ADV3227 If the disabled outputs are left floating they may exhibit high enable glitches If necessary the disabled output can be kept from drifting out of range by applying an output load resistor to ground The connection of the ADV3226 ADV3227 is controlled by a flexible TTL compatible logic interface Either parallel or serial loading into a first rank of latches preprograms each output A global update signal moves the programming data into the second rank of latches simultaneously updating all outputs In serial mode a serial out pin allows devices to be daisy chained together for single pin programming of multiple ICs A power on reset pin is available to avoid bus conflicts by disabling all outputs This power on reset clears the second rank of latches but does not clear the first rank of latches In serial mode preprogramming individual inputs is not possible and the entire shift register needs to be flushed To easily interface to ground referenced video signals the ADV3226 ADV3227 operate on split 5 V supplies The logic inputs and output run on a single 5 V supply but the logic inputs switch at approximately 1 6 V for compatibility with a variety of logic families The s
30. re 23 ADV3227 Falling Edge Slew Rate 15 40 1 0 QUTPUT INPUT B 0 5 20 OUTPUT SIGNAL gt E 10 o gt 0 5 0 1 0 INPUT SIGNAL 10 PROPAGATION DELAY NOT SHOWN 1 5 20 1 0 05 0 05 10 15 20 25 30 35 40 TIME ns Figure 24 ADV3227 Settling Time Rev 0 Page 13 of 24 SLEW RATE Vlus SLEW RATE Vius OUTPUT ERROR 08653 122 08653 029 08653 030 ADV3226 ADV3227 Vee AGGRESSOR PSR dB PSR dB Vcc AGGRESSOR 0 1 1 10 100 1k FREQUENCY MHz 0 1 1 10 100 1k FREQUENCY MHz 08653 028 08653 031 Figure 25 ADV3226 Power Supply Rejection Figure 28 ADV3227 Power Supply Rejection N eo N o EN EN 140 N o N o NOISE SPECTRAL DENSITY nVA Hz NOISE SPECTRAL DENSITY nVA Hz a 20 N 1 10k 100k 1M 10M 100M FREQUENCY Hz 08653 032 08653 035 FREQUENCY Hz Figure 26 ADV3226 Output Noise 100 O Load Figure 29
31. ster is programmed into the matrix Therefore to prevent programming the crosspoint into an unknown state do not apply low logic levels to both CE and UPDATE after power is initially applied To eliminate the possibility of programming the matrix to an unknown state after initial power up program the full shift register one time to a desired state using either serial or parallel programming To change the programming of an output via parallel program ming take the SER PAR and UPDATE pins high and take the CE pin low The CLK signal should be in the high state Place the 4 bit address of the output to be programmed on 0 to The first four data bits DO to D3 contain the information that identifies the input that is programmed to the addressed output The fifth data bit D4 determines the enabled state of the out put If D4 is low output disabled the data on DO to D3 does not matter After the address and data signals are established they can be latched into the shift register by pulling the CLK signal low however the matrix is not programmed until the UPDATE signal is taken low In this way it is possible to latch in new data for several or all of the outputs first via successive negative transi tions of CLK while UPDATE is held high and then have all the new data take effect when UPDATE goes low Use this technique when programming the device for the first time after power up when using parallel programming In parallel m
32. the device GAIN SELECTION The 16 x 16 crosspoints come in two versions depending on the gain ofthe analog circuit path The ADV3226 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired The ADV3226 outputs have very high impedance when their outputs are disabled The ADV3227 can be used for devices that drive a terminated cable with its outputs This device has a built in gain of 2 that eliminates the need for a gain of 2 buffer to drive a video line Its Rev 0 Page 22 of 24 ADV3226 ADV3227 high output disabled impedance minimizes signal degradation when paralleling additional outputs CREATING LARGER CROSSPOINT ARRAYS The ADV3226 ADV3227 are high density building blocks for creating crosspoint arrays of dimensions larger than 16 x 16 Various features such as output disable chip enable and gain of 1 and gain of 2 options are useful for creating larger arrays When required for customizing a crosspoint array size they can be used with the AD8108 and AD8109 which are a pair of unity gain and gain of 2 8 x 8 video crosspoint switches or with the AD8110 and AD8111 a pair of unity gain and gain of 2 16 x 8 video crosspoint switches The first consideration in constructing a larger crosspoint is to determine the minimum number of required devices that are required The 16 x 16 architecture of the ADV3226 ADV3227 contains 256 points which is a factor of
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ANALOG DEVICES ADV3226/ADV3227 English products handbook Rev 0