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PHILIPS LPC2114/2124/2212/2214 USER MANUAL

1. Figure 12 Oscillator modes and models a slave mode of operation b oscillation mode of operation c external crystal model used for Cx4 x2 evaluation Table 13 Recommended values for Cy4 x2 in oscillation mode crystal and external components parameters Fundamental Oscillation Crystal Load Max Crystal Series External Load Frequency Fc Capacitance C Resistence Rs Capacitors Cy4 Cx 10 pF n a n a System Control Block 52 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 13 Recommended values for Cxyyx2 in oscillation mode crystal and external components parameters Fundamental Oscillation Crystal Load Max Crystal Series External Load Frequency Fc Capacitance C Resistence Rs Capacitors Cy4 Cx 10 pF 300 Q 18 pF 18 pF C fosc Selection on chip PLL used in application Y False SP used for initial code download Y False external crystal oscillator used False Y v min foso 10 MHz min fosc 1 MHz min fosc 1 MHz max fosc 25 MHz max fosc 50 MHz max fosc 30 MHz Figure 12 mode a and or b Figure 12 mode a Figure 12 mode b Figure 13 Fosc selection algorithm System Control Block 53 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcont
2. 86 9 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 55 Pin description for LPC2114 2124 liliis 94 Table 56 Pin description for LPC2212 2214 0 0000oooooooocoo ne 99 Table 57 Pin Connect Block Register Map o ooccccccccocnc eh 109 Table 58 Pin Function Select Register 0 for LPC2114 2124 2212 2214 PINSELO 0xE002C000 110 Table 59 Pin Function Select Register 1 for LPC2114 2124 2212 2214 PINSEL1 OXE002C004 110 Table 60 Pin Function Select Register 2 for LPC2114 2124 PINSEL2 0xE002C014 111 Table 61 Pin Function Select Register 2 for LPC2212 2214 PINSEL2 0xE002C014 112 Table 62 Pin Function Select Register Bits llis es 113 Table 63 Boot Gontrol on BOOT1 0 ias rr AAA UA A xb eun Rep e gs 114 Table 64 GPIO Pin Description s saaana aaaea RR m 115 Table 65 GPIO Register Map oooccocccccco RR mmn 116 Table 66 GPIO Pin Value Register IOOPIN 0xE0028000 IO1PIN 0xE0028010 IO2PIN 0xE0028020 IO3PIN 0xE0028030 oococccccocccoc eee 117 Table 67 GPIO Output Set Register IOOSET 0xE0028004 IO1SET 0xE0028014 IO2SET 0xE0028024 IOSSET OxE0028034 liis 117 Table 68 GPIO Output Clear Register IOOCLR OXE002800C IO1CLR 0xE002801C IO2CLR 0xE002802C IOSCLR OXE002803C o ooocccccoccccc eere 118 Table 69 GPIO Direction Regi
3. BEIM MN This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Description Flash Memory System and Programming 236 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Copy RAM to Flash Table 181 IAP Copy RAM to Flash command description Command Copy RAM to Flash Command code 51 ParamO DST Destination Flash address where data bytes are to be written The destination address should be a 512 byte boundary Input Param1 SRO Source RAM address from which data bytes are to be read This address should be on word boundary Param2 Number of bytes to be written Should be 512 1024 4096 8192 Param3 System Clock Frequency CCLK in KHz CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary Status Code SRC ADDR NOT MAPPED DST ADDR NOT MAPPED COUNT ERROR Byte count is not 512 1024 4096 8192 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY BELLNM MN This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Oper
4. sse RH 37 Table 4 LPC2114 2124 2212 2214 Memory Mapping Modes llis eee eese 37 Table 5 Address Ranges of External Memory Banks LPC2212 2214 only oo oococcoocooooo 41 Table 6 External Memory Controller Pin Description llli 42 Table 7 External Memory Controller Register Map iile 42 Table 8 Bank Configuration Registers 0 3 BCFGO 3 OxFFEOQ000 0C 05 43 Table 9 Default memory widths at Reset o oooccocccccoocccr e 43 Table 10 External memory and system requirements llle eee 47 Table Tf Pin sumrmiaty cz fi ote et id ERR fue aed cele AE Se eel ge Bled IRURE IDEN CBE 49 Table 12 Summary of System Control Registers 0 0 cece ete ete 51 Table 13 Recommended values for CX1 X2 in oscillation mode crystal and external components parameters 00 000 c cece eee ete eee 52 Table 14 External Interrupt Registers 20 0 0 cece eR m 54 Table 15 External Interrupt Flag Register EXTINT OXEO1FC140 0 0 eee ee eee 55 Table 16 External Interrupt Wakeup Register EXTWAKE OXEO1FC144 0 0 2 eee eee eee 56 Table 17 External Interrupt Mode Register EXTMODE OXEO1FC148 0 0 ee eee eee 56 Table 18 External Interrupt Polarity Register EXTPOLAR OxEO1FC14C 0 000002 ue 57 Table 19 MEMMAP Register 0 0 59 Table 20 Memory Mapping Control Register MEMMAP OxEO1FC
5. BLS 1 D 15 8 CE OE WE IO 7 0 A a m 0 BLS 0 D 7 0 CE OE WE IO 7 0 A a m 0 A a b 1 a 16 bit wide memory bank interfaced to 8 bit memory chips LPC211 Preliminary User Manual 4 2124 2212 2214 BLS 1 BLS 0 D 15 0 IO 15 0 A a m 0 A a b 1 a 16 bit wide memory bank interfaced to 16 bit memory chips Figure 8 16 Bit Bank External Memory Interfaces BLS 0 D 7 0 CE OE WE IO 7 0 A a m 0 A a b 0 Figure 9 8 Bit Bank External Memory Interface External Memory Controller EMC 45 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 TYPICAL BUS SEQUENCES Following figures show typical external read and write access cycles XCLK is the clock signal avalable on P3 23 While not necessary used by external memory In these examples it is used to provide the time reference XCLK and CCLK were set to have the same frequency 1 wait state WST1 0 XCLK cs OE WE BLS Addr valid address Data change valid data X 2 wait states WST1 1 XCLK cs OE WE BLS Addr valid address Data change valid data Figure 10 External memory read access WST1 0 and W
6. AR MR UART1 Figure 23 UART1 Block Diagram 146 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 12 IC INTERFACE FEATURES Standard 12C compliant bus interface Easy to configure as Master Slave or Master Slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The IC bus may be used for test and diagnostic purposes APPLICATIONS Interfaces to external 12C standard parts such as serial RAMs LCDs tone generators etc DESCRIPTION Atypical 12C bus configuration is shown in Figure 24 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus Datatransfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitt
7. ooooccooocococco lees 75 MAM Configuration 0 0 0 ccc Rm mh murs 76 Register Description ooo rad ORARE e da ia ge E Roe 76 MAM Usage Notes ico eset eee ee So eee ee An ee ee ee eee eee EE 77 May 03 2004 Philips Semiconductors ARM based Microcontroller Vectored Interrupt Controller VIC 0 00 cece ee ee eee 79 Features fcc se ase SETA ERGGUEEG s ch ae ee deep pa eee Ache RAUS PAIN SURE 79 DeSCription p en e esee eR ae MEER ee eas ae Oe ue uM ee ae ee E 79 Register Description cu Sybase AS Ge Oe ed eles ERE a RES 80 VIG Hegisters Loses A bat DURS p ERE dines deine OP RUD 82 interrupt SourceS nli ue ERR RI EE DR Md E TAE 86 Sputious lnterT pts z d asciende be Cor bcp e EE rtr PE a Ae es 88 VIC Usage Notes cer Ll reden E Rex Da ex Ee E RR A E E Ene Oed 91 Pin Configuration Lt 5L a Bee LLLA ree VELA lua ee 93 EPOC2114 2124 PINOUT robe vitate to tret eed Sia b Eds S ERU ETE RUE RS 93 Pin Description for LPC2114 2124 0 00ooccccoccc enn 94 EPG2212 2214 PIO E irre te I ao tea co dee tob pu e tutelle eri eae 98 Pin Description for LPC2212 2214 20 en 99 Pin Connect Block lll Er xe ll eet MESE Rr eee 109 Features cria A A A A AA A AIR 109 Applications cesta A A A Aa E E 109 Description cit A A A A MEN uer A 109 Register Description isses see xy gg A GER Ey URGE n ee 109 Boot Control on 144 pin Package ssseseeeeleee RR n 114 OPIO or ANE 115 AA a hoa a a e a een en eet been Ie gen
8. Preliminary User Manual LPC2114 2124 2212 2214 Address Register al Shift Register 4 12DAT Bit Counter Arbitration amp Sync Logic Timing amp Control Logic VPB BUS Serial Clock Generator Control Register amp SCL Duty Cycle Registers Status Register I2STAT Figure 32 IC Architecture 158 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 13 SPI INTERFACE FEATURES Two complete and independent SPI cintrollers Compliant with Serial Peripheral Interface SPI specification Synchronous Serial Full Duplex Communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate DESCRIPTION SPI Overview SPIO and SPI1 are full duplex serial interfaces They can handle multiple masters and slaves being connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends a byte of data to the slave and the slave always sends a byte of data to the master SPI Data Transfers Figure 33 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing one should notice in this timing diagram is that it is divided into three
9. Table 4 LPC2114 2124 2212 2214 Memory Mapping Modes Mode Activation Usage The Boot Loader always executes after any reset The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process Boot Loader Hardware activation mode by any Reset Activated by Boot Loader when a valid User Program Signature is recognized in memory and Boot Loader operation is not forced Interrupt vectors are not re mapped and are found in the bottom of the Flash memory User Flash Software activation mode by Boot code User RAM Software activation Activated by a User Program as desired Interrupt vectors are re mapped to the bottom mode by User program of the Static RAM Activated by the Boot Loader when either or both BOOT pins are low at the end of Activated by RESET low Interrupt vectors are re mapped from the bottom of the external memory BOOT1 0 pins not map 11 at Reset User External mode Note This mode is available in LPC2212 2214 only LPC2114 2124 2212 2214 Memory Addressing 37 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Memory Re Mapping In order to allow for compatibility with future derivatives the entire Boot Block is mapped to the top of the on chip memory space In this manner the use of larger or smaller flash modules will not require changing the location
10. This command makes flash write erase operation a two step process Table 170 ISP Prepare sector s for write operation command description Command P Start Sector Number End Sector Number Should be greater than or equal to start sector number Input CMD SUCCESS BUSY INVALID SECTOR PARAM ERROR This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example X P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Return Code Description Copy RAM to Flash Flash address RAM address number of bytes gt Table 171 ISP Copy RAM to Flash command description Command C Flash Address DST Destination Flash address where data bytes are to be written The destination address should be a 512 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 512 1024 4096 8192 CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary SRC ADDR NOT MAPPED DST ADDR NOT MAPPED Return Code COUNT ERROR Byte count is not 512 1024 4096 8192 SECTOR NOT
11. ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address n Offset Name Description LSB Access U1 Receiver U1RBR Buffer 8 bit data DLAB 0 Register U1 Transmit DLAB 0 Register Eu Pa Divisor U1 Interrupt M Enable 0xE0010004 Register aah U1 Divisor uma Uf Interrupt eie Enabled m3 Re IIR1 0x01 ID Register 0xE0010008 U1 FIFO U1FCR Control Rx Trigger aon WO Register Enable U1 Line 0xE001000C U1LCR Control plas Set Stick parity Parity Word Length Ryw Break Parity Enable Select Register Select U1 Modem 0xE0010010 Un Control Bee RTS DTR RW Register U1 Line Rx 0xE0010014 U1LSR Status FIFO TEMT THRE 0x60 Register Error 0xE001001C Utscn Y Scratch 8 bit data Pad Register U1 Modem Trailing U1 Delta Delta Delta 0xE0010018 MSR Status DCD DSR CTS DCD Edge DSR CTS Register RI PWM Int Int Int 0xE0014000 PM Interrupt IR Register MR3 MR2 MR1 E Int Int Int E PWM Timer PWM PWM CTR CTR egister oxE0014008 PWM PWM Timer 32 bit data TC Counter Introduction 24 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address n Reset Offset Description LSB Access Value PWM Prescale 32 bit data R W 0 Register PWM Prescale 32 bit data R W Counter PWM Match 0xE0014014 Control 7 R W Register nt
12. Details on re mapping and examples can be found in System Control Block on page 49 LPC2114 2124 2212 2214 Memory Addressing 38 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 0x8000 0000 2 0 GB 8K byte Boot Block Ox7FFF FFFF re mapped from top of Flash memory 2 0 GB 8K Boot Block interrupt vectors Reserved for On Chip Memory 0x4000 4000 0x4000 3FFF 16 kB On Chip SRAM SRAM interrupt vectors 0x4000 0000 Ox3FFF FFFF Reserved for On Chip Memory 0x0002 0000 8k byte Boot Block re Mapped to higher address range 0x0001 FFFF Active interrupt vectors from Flash SRAM or Boot Block 0x0000 0000 Note memory regions are not drawn to scale Figure 6 Map of lower memory is showing re mapped and re mappable areas 128 kB Flash LPC2114 2124 2212 2214 Memory Addressing 39 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PREFETCH ABORT AND DATA ABORT EXCEPTIONS The LPC2114 2124 2212 2214 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region The regions are Areas of the memory map that are not implemented for a specific ARM derivative For the LPC2114 2124 2212 2214 this is Address space between On Chip Non Volatile Memory and On Chip SRAM labelled Reserved for On Chip Memory in Figure
13. REGISTER TIMER COUNT SHADOW BIT WDMOD AEGICTER WDEN WDTOF WDINT WDRESET 1 Counter is enabled only when the WDEN bit is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they can t be cleared until the Watchdog underflows INTERRUPT or an external reset occurs Figure 42 Watchdog Block Diagram Watchdog 216 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 19 FLASH MEMORY SYSTEM AND PROGRAMMING This chapter describes the Flash Memory System and the Boot Loader It also includes In System Programming ISP and In Application Programming IAP interfaces FLASH MEMORY SYSTEM The Flash Memory System contains 16 sectors for 128 kB part and 17 sectors for 256 kB part Flash memory begins at address 0 and continues upward Details may be found in the LPC2114 2124 2212 2214 Memory Addressing chapter On chip Flash memory is capable of withstanding at least 10 000 erase and write cycles over the whole temperature range FLASH BOOT LOADER The Boot Loader controls initial operation after reset and also provides the means to accomplish programming of the Flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the Flash memory by the application program in a running system FEATURES In System Programming I
14. Transmitter Holding Register Empty THRE Error in Rx FIFO RXFE 0 UART1 142 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Modem Status Register U1MSR 0x0xE0010018 The U1MSR is a read only register that provides status information on the modem input signals UT MSR3 0 is cleared on U1MSR read Note that modem signals have no direct affect on UART1 operation they facilitate software implementation of modem signal operations Table 99 UART1 Modem Status Register Bit Descriptions U1MSR 0x0xE0010018 Reset Function Description Value 0 No change detected on modem input CTS Delta CTS 1 State change detected on modem input CTS 0 Set upon state change of input CTS Cleared on an U1MSR read 0 No change detected on modem input DSR Delta DSR 1 State change detected on modem input DSR Set upon state change of input DSR Cleared on an U1MSR read 0 No change detected on modem input RI Trailing Edge RI 1 Low to high transition detected on RI Set upon low to high transition of input RI Cleared on an U1MSR read 0 No change detected on modem input DCD 3 Delta DCD 1 State change detected on modem input DCD Set upon state change of input DCD Cleared on an U1MSR read 4 CTS Clear To Send State Complement of input signal CTS This bit is connected to U1MCR 1 in modem loopback mode 5 DSR Data Set Ready State Compleme
15. 8kB Boot Block interrupt vectors Ox7FFF E000 0x0001 FFFF 8k byte Boot Block re Mapped to higher address range 0x0001 E000 0 0 GB Active interrupt vectors from the Boot Block 0x0000 0000 Note memory regions are not drawn to scale Figure 43 Map of lower memory after any reset 128 kB Flash part Criterion for valid user code The reserved ARM interrupt vector location 0x0000 0014 should contain the 2 s complement of the check sum of the remaining interrupt vectors This causes the checksum of all of the vectors together to be 0 The boot loader code disables the overlaying of the interrupt vectors from the boot block then calculates the checksum of the interrupt vectors in sector 0 of the flash If the signatures match then the execution control is transferred to the user code by loading the program counter with Ox 0000 0000 Hence the user flash reset vector should contain a jump instruction to the entry point of the user application code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF g
16. ARM based Microcontroller LPC2114 2124 2212 2214 18 WATCHDOG FEATURES Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a Watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate Watchdog reset Programmable 32 bit timer with internal pre scaler Selectable time period from tpg x 256 x 4 to tpoik x 29 x 4 in multiples of too x 4 APPLICATIONS The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset if the user program fails to feed or reload the Watchdog within a predetermined amount of time For interaction of the on chip watchdog and other peripherals especially the reset and boot up procedures please read Reset and Boot Control on 144 pin Package sections of this document DESCRIPTION The Watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is too x 256 x 4 and the maximum Watchdog interval is tpcik x 232 x 4 in multiples of tpcik x 4 The Watchdog should be used in the fo
17. CAP1 1 can be selected from on 1 pin CAP1 2 can be selected from on up to 2 pins at the same time CAP1 3 can be selected from on up to 2 pins at the same time External Match Output 0 1 When a match register 0 1 MR3 0 equals the timer counter TC this output can either toggle go low go high or do nothing The External Match Register EMR controls the functionality of this output Match Output functionality can be selected on a number of pins in parallel It is also possible for example to have 2 pins selected at the same time so that they provide MAT1 3 function in parallel MATO 3 0 Output MATO 0 can be selected on up to 2 pins at the same time MAT1 0 0 MATO 1 can be selected on up to 2 pins at the same time MATO 2 can be selected on up to 2 pins at the same time MATO 3 can be selected on 1 pin MAT1 0 can be selected on 1 pin MAT1 1 can be selected on 1 pin MAT 1 2 can be selected on up to 2 pins at the same time MAT 1 3 can be selected on up to 2 pins at the same time TimerO and Timer1 170 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION Each Timer contains the registers shown in Table 122 More detailed descriptions follow Table 122 TIMERO and TIMER1 Register Map Reset TIMERO TIMER1 Description Access Value Address amp Address amp Name Name Interrupt Register The IR can be written to clear interrupts The IR can
18. Capture on CAPn 2 When one a sequence of 1 then 0 on CAPn 2 will cause CR2 to be loaded with falling edge the contents of TC When zero this feature is disabled TimerO and Timer1 174 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 External Match Register EMR TIMERO TOEMR 0xE000403C TIMER1 T1EMR 0xE000803C The External Match Register provides both control and status of the external match pins M 0 3 Table 127 External Match Register EMR TIMERO TOEMR 0xE000403C TIMER1 T1EMR OxE000803C Function Description This bit reflects the state of output MATO O MAT 1 0 whether or not this output is connected to its pin When a match occurs for MRO this output of the timer can either toggle go low go high or do nothing Bits EMR 4 5 control the functionality of this output External Match 0 This bit reflects the state of output MATO 1 MAT1 1 whether or not this output is connected to its pin When a match occurs for MR1 this output of the timer can either toggle go low go high or do nothing Bits EMR 6 7 control the functionality of this output External Match 1 This bit reflects the state of output MATO 2 MAT1 2 whether or not this output is connected to its pin When a match occurs for MR2 this output of the timer can either toggle go low go high or do nothing Bits EMR 8 9 control the functionality of this output External
19. Counter Increment Interrupt The Counter Increment Interrupt Register CIIR gives the ability to generate an interrupt every time a counter is incremented This interrupt remains valid until cleared by writing a one to bit zero of the Interrupt Location Register ILR 0 Table 146 Counter Increment Interrupt Register Bits CIIR 0xE002400C Function IMSEC IMMIN IMHOUR Alarm Mask The Alarm Mask Register AMR allows the user to mask any of the alarm registers Table 147 shows the relationship between the bits in the AMR and the alarms For the alarm function every non masked alarm register must match the corresponding time counter for an interrupt to be generated The interrupt is generated only when the counter comparison first changes from no match to match The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register ILR If all mask bits are set then the alarm is disabled Real Time Clock 202 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 147 Alarm Mask Register Bits AMR 0xE0024010 Function Description AMRSEC When one the Second value is not compared for the alarm AMRMIN When one the Minutes value is not compared for the alarm AMRHOUR When one the Hour value is not compared for the alarm AMRDOM When one the Day of Month value is not compared for the alarm 5 AMRMON enone e Mont
20. Description BIT7 BIT6 BIT4 BIT3 Receiver UORBR Buffer READ DATA Register Transmit UOTHR Holding WRITE DATA WO Register Interrupt UOIER Enable Register Interrupt Enable THRE Interrupt Enable Rx Data Available Enable Rx Line i 0xE000C008 NA HB 0xE000C008 m OxEO00CO0C 0xE000C014 0x01 IIRS IIR2 IIR1 uoir Iterrupt ID FIFOs Enabled Register FIFO UOFCR Control Rx Trigger Reserved Register UOLCR Line Control Register voLsr Line Status TEMT Register Error UOSCR Scratch Pad Register Divisor Latch Divisor Latch T Reset Value refers to the data stored in used bits only It does not include reserved bits content WO Tx FIFO Reset Rx FIFO Reset FIFO Enable Word Length Select Break T ng DLAB O Parity pa fem lal e O m B LS ES OxE000C01C tsp mw Ey OxEO00CO00 LS M M DLAB 1 OxE000C004 DLAB 1 UARTO contains ten 8 bit registers as shown in Table 74 The Divisor Latch Access Bit DLAB is contained in UOLCR7 and enables access to the Divisor Latches x D D 2 2 2 SB SB B B UARTO Receiver Buffer Register UORBR 0xE000C000 when DLAB 0 Read Only The UORBR is the top byte of the UARTO Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded w
21. I2EN must be set to 1 to enable the I C function AA bit must be set to 1 to acknowledge its own slave address or the general call address The STA STO and SI bits are set to 0 After IPADR and I2CONSET are initialized the 12C interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 5 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http Awww semiconductors philips com acrobat various 8XC552_5620VERVIEW_2 paf for the status codes and actions 12C Interface 150 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Slave Address Ww DATA A 2 A A P RS pr m A Data Transferred A n Bytes Acknowledge 1 Read Acknowledge SDA low From Master to Slave Not Acknowledge SDA high From Slave to Master START condition STOP Condition S Repeated START Condition Figure 30 Format of slave receiver mode Slave Transmitter Mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is t
22. INTEGRATED CIRCUITS USER MANUAL LPC2114 2124 2212 2214 USER MANUAL Preliminary 2004 May 03 Supersedes data of 2004 Feb 03 Philips PHILIPS Semiconductors El l LI PS Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 2 May 03 2004 Philips Semiconductors ARM based Microcontroller Table of Contents Preliminary User Manual LPC2114 2124 2212 2214 LISDORRIQUIES oia A DUC ON E DH eR WE ATA edis he UB eite et 7 Listot E lo ETT 9 Document Revision History 00 60 e m 13 Introduction MIR de abe Pee A mee A 15 General Description canst et kerk ERES EXPERS RENE UR Rp EI kl 15 Feat re Me 15 Applications si ER EROPLDEREPDOENEB CHE E OE Rug ERREUR Diane Rind dee ded 16 Device informatlom iii IP teks ewe ae UD ERROR E 16 Architectural OVerview 2 y npe ECCE ERE M LS EIUS REPE IU RAE 17 ARMZEDMES PrOGeSSOFE 12i eeu Le o ACE LAS M ai 17 On Chip Flash Memory System ooococcccoc her 17 On Chip Static RAM sags einen ie ee ee les eee dee ee eames eae eee RD er 18 Block Diagram oer a Lek nU UE ERR DE dcr See eee 19 LPC2114 2124 2212 2214 Registers llle ees 20 LPC2114 2124 2212 2214 Memory Addressing 200 eee eee e ee eee 33 Memory Maps tercios eee itt ea iene eere ete in RUE EU Ere ied eee 33 LPC 2114 21 24 2212 2214 Memory Re mapping and Boot Block o o ooocooooo o 37 Prefetch Abort
23. But if more than one request is assigned to the FIQ class the FIQ service routine can read a word from the VIC that identifies which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority but ony 16 of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot O has the highest priority and slot 15 has the lowest Non vectored IRQs have the lowest priority The VIC ORs the requests from all the vectored and non vectored IRQs to produce the IRQ signal to the ARM processor The IRQ service routine can start by reading a register from the VIC and jumping there If any of the vectored IRQs are requesting the VIC provides the address of the highest priority requesting IRQs service routine otherwise it provides the address of a default routine that is shared by all the non vectored IRQs The default routine can read another VIC register to see what IRQs are active All registers in the VIC are word registers Byte and halfword reads and write are not supported Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell Vectored Interrupt Controller PL190 documentation Vectored Interrupt Controller VIC 79 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The VIC implements the registers shown in Table 40
24. Do nothing on match APPLICATIONS Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer TimerO and Timer1 169 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 DESCRIPTION The Timer is designed to count cycles of the peripheral clock pclk and optionally generate interrupts or perform other actions at specified timer values based on four match registers It also includes four capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt PIN DESCRIPTION Table 121 gives a brief summary of each of the Timer related pins Table 121 Pin summary Pin name Pin direction Pin Description Capture Signals A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt Capture functionality can be selected from a number of pins Also if for example 2 pins are selected to provide CAPO 2 function in parallel their inputs will be logically ored and this value will be processed as a single input CAPO 3 0 CAPO 0 can be selected from on up to 3 pins at the same time CAP1 3 0 CAPO 1 can be selected from on up to 2 pins at the same time CAPO 2 can be selected from on up to 3 pins at the same time CAPO 3 can be selected from on 1 pin CAP1 0 can be selected from on 1 pin
25. It s a 32 bit register with 8 LSB set to 1 on reset Writing values below OxFF will cause OxFF to be loaded to the WDTC Thus the minimum time out interval is too x 256 x 4 Function Description Count Watchdog time out interval Watchdog 213 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Watchdog Feed Register WDFEED 0xE0000008 Writing OxAA followed by 0x55 to this register will reload the Watchdog timer to the WDTC value This operation will also start the Watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must first be completed before the Watchdog is capable of generating an interrupt reset Until then the Watchdog will ignore feed errors Once 0xAA is written to the WDFEED register the next operation in the Watchdog register space should be a WRITE 0x55 to the WDFFED register otherwise the Watchdog is triggered The interrupt reset will be generated during the second pelk following an incorrect access to a watchdog timer register during a feed sequence Table 160 Watchdog Feed Register WDFEED 0xE0000008 Reset Value 7 0 Feed Feed value should be OxAA followed by 0x55 undefined WDFEED Function Description Watchdog Timer Value Register WDTV 0xE000000C The WDTV register is used to read the current value of Watchdog timer Tab
26. OxE001 0000 OxE000 C000 OxE000 8000 OxE000 4000 OxE000 0000 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 LPC2114 2124 2212 2214 MEMORY RE MAPPING AND BOOT BLOCK Memory Map Concepts and Operating Modes The basic concept on the LPC2114 2124 2212 2214 is that each memory area has a natural location in the memory map This is the address range for which code residing in that area is written The bulk of each memory space remains permanently fixed in the same location eliminating the need to have portions of the code designed to run in different address ranges Because of the location of the interrupt vectors on the ARM7 processor at addresses 0x0000 0000 through 0x0000 001C as shown in Table 3 below a small portion of the Boot Block and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 4 Re mapping of the interrupts is accomplished via the Memory Mapping Control feature described in the System Control Block section Table 3 ARM Exception Vector Locations Address Exception Prefetch Abort instruction fetch memory fault Data Abort data access memory fault wmews ma Identified as reserved in ARM documentation this location is used by the Boot Loader as the Valid User Program key This is descibed in detail in Flash Memory System and Programming on page 217
27. OxE0024080 lessen 208 Table 153 Prescaler Fraction Register PREFRAC 0xE0024084 0 0 cece eee ee 208 Table 154 Prescaler cases where the Integer Counter reload value is incremented 210 Table 155 Watchdog Register Map oooccocooc HR 3 n 212 Table 156 Watchdog Mode Register WDMOD OxE0000000 0 0 0 cee eee eee 213 Table 157 Watchdog Feed Register WDFEED 0xE0000008 2 000020 ee eeee 214 Table 158 Watchdog Timer Value Register WDTV OxXE000000C sssseseseeeee rennes 214 Table 159 Sectors in a device with 128K bytes of Flash 0 0 0 0c cece eee 223 Table 160 ISP Command Summary 225 11 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 161 ISP Unlock command description llle eh 225 Table 162 ISP Set Baud Rate command description 0 0 0 cect 226 Table 163 Correlation between possible ISP baudrates and external crystal frequency in MHz 226 Table 164 ISP Echo command description oooococcocccococ eh 226 Table 165 ISP Write to RAM command description llle 227 Table 166 ISP Read Memory command description oooocococcococccea ee 228 Table 167 ISP Prepare sector s for write operation command descripti0N o o ooo 229 Table 168 ISP Copy RAM to Flash command descripti0N ooo oooooocoooooro lees 229 Table 1
28. PHASE LOCKED LOOP The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only The input frequency is multiplied up into the cclk with the range of 10 MHz to 60 MHz using a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 in practice the multiplier value cannot be higher than 6 on the LPC2114 2124 2212 2214 due to the upper frequency limit of the CPU The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle A block diagram of the PLL is shown in Figure 15 PLL activation is controlled via the PLLCON register The PLL multiplier and divider values are controlled by the PLLCFG register These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL Since all chip operations including the Watchdog Timer are dependent on the PLL when it is providing the chip clock accidental changes to the PLL setup could result in unexpected behavior of the microcontroller The protection is accomplished by a feed sequence similar to that of the Watchdog Timer Details are provided in the description of the PLLFEED register The
29. SCK is active high Master mode select When 1 the SPI operates in Master mode When 0 the SPI 5 MSTR operates in Slave mode LSB First controls which direction each byte is shifted when transferred When 1 SPI data is transferred LSB bit 0 first When 0 SPI data is transferred MSB bit 7 first Serial peripheral interrupt enable When 1 a hardware interrupt is generated each time the SPIF or MODF bits are activated When 0 SPI interrupts are inhibited SPI Interface 164 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SPI Status Register SOSPSR 0xE0020004 S1SPSR 0xE0030004 The SPSR register controls the operation of the SPI as per the configuration bits setting Table 117 SPI Status Register SOSPSR 0xE0020004 S1SPSR 0xE0030004 Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Slave abort When 1 this bit indicates that a slave abort has occurred This bit is cleared by reading this register Mode fault when 1 this bit indicates that a Mode fault error has occurred This bit is cleared by reading this register then writing the SPI control register Read overrun When 1 this bit indicates that a read overrun has occurred This bit is cleared by reading this register Write collision When 1 this bit indicates that a write collision has occurred T
30. THRE is set immediately upon detection of an empty UARTO THR and is cleared on a UOTHR write 0 UOTHR and or the UOTSR contains valid data 1 UOTHR and the UOTSR are empty TEMT is set when both UOTHR and UOTSR are empty TEMT is cleared when either the UOTSR or the UOTHR contain valid data 0 UORBR contains no UARTO Rx errors or UOFCRO 0 Error in Rx 1 UARTO RBR contains at least one UARTO Rx error FIFO UOLSR7 is set when a character with a Rx error such as framing error parity error or break interrupt is loaded into the UORBR This bit is cleared when the UOLSR register is read and there are no subsequent errors in the UARTO FIFO Transmitter Empty 0 UARTO 128 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UARTO Scratch Pad Register UOSCR 0xE000C01C The UOSCR has no effect on the UARTO operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the UOSCR has occurred Table 85 UARTO Scratchpad Register UOSCR 0xE000C01C UOSCR Function Description 7 0 A readable writable byte UARTO 129 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ARCHITECTURE The architecture of the UARTO is shown below in the block diagram The VPB interface provides a comm