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samsung S3C84I8X/F84I8X/C84I9X/F84I9X USER S MANUAL

1. 6 74 5 0 Select Bank and dG ue def 6 75 SB1 Select Bank E a c i e barn RR EE ela 6 76 SBC Subtract With Garry faz osea et eei e ee edite LER REOR Fe DRM n e DR eee 6 77 SCF Set Carry F 8g u s asahan aap ii usay 6 78 SRA Shift BlghtArithimetie a rea la teet edet 6 79 SRP SRPO SRP1 Set Register Pointer U nennen enn nnns 6 80 STOP Stop REMIT 6 81 SUB SUDUACL 6 82 SWAP beat 6 83 TCM Test Complement under Mask sse nennen nnns 6 84 TM Test under Mask erect e quce koe 6 85 WFI Wate for 6 86 XOR Eogical Excl sive OB iah uusha washa 6 87 xxii S3C84I8X F8418X C84I9X F8419X USER S MANUAL REV 2 00 MICROCONTROLLER S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode released by interrupt or reset Buil
2. SIOCON serial VO Module Control Registers F2H Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write RAN RAN RAN R W R W R W R W R W 7 SIO Shift Clock Selection Bit 0 Interval clock P S Clock 1 External clock 6 Data Direction Control Bit 0 MSB first mode 1 LSB first mode 5 SIO Mode Selection Bit 0 Receive only mode 1 Transmit Receive mode 4 Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges 33 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit 0 Disable shift and clock counter 1 Enable shift and clock counter 1 SIO Interrupt Enable Bit 0 Disable SIO interrupt 1 Enable SIO interrupt 0 SIO Interrupt Pending Bit 0 No interrupt pending 1 Interrupt pending Clear pending bit when write 4 34 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 CONTROL REGISTER SIOPS sio Prescaler Register Set 1 1 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Baud rate Input clock fxx SIOPS 1 x4 SCK input clock
3. a System Clock Control Register Flash Memory Control Register a Flash Memory Sector Register High byte Flash Memory Sector Register Low Flash Memory User Programming Enable Register System Flags 2 2 00 10 enne Interrupt Mask Instruction Pointer Low Interrupt Priority Register Interrupt Request LCD Mode Control Register LCD Port Control Register a Oscillator Control Port 0 Control Register High Port 1 Control Register High Byte Port 1 Control Register Low Byte 2 Port 1 Interrupt Pending Port 1 Interrupt Enable Port 2 Control Register High Port 2 Control Register Low Byte Port 2 Pull up Resistor Control Port Control Register High Port Control Register Low Byte sse Port 4 Control Register High Byte Port 4 Control Regi
4. 3 10 3 11 Direct Addressing for Call and Jump Instructions sees 3 11 3 12 Indirect Addressing eroe oor ree aces 3 12 3 13 Relative 3 13 3 14 Immediate 3 14 S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 MICROCONTROLLER xi Figure Number 4 1 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 1 7 1 7 2 7 3 7 4 7 5 7 6 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 9 10 9 11 9 12 xii List of Figures continued Title Page Number Register Description Format sess enn eene nnne 4 4 S3C8 Series Interrupt Types 5 3 S3C8418X F8418X C84I9X F84I9XInterrupt Structure 5 5 ROM Vector Address Area ener nnn sinn ns 5 6 Interrupt Function 5 9 System Mode Register SYM a 5 11 Interrupt Mask Register 5 12 Interrupt Request Priority Groups sss 5 13 Interrupt Priority Register IPR 5 14 Interrupt Request Register 5 15 System Flags Register 6 6 Main Oscillator Circuit Crystal or Ceramic Oscillator 7 1 Sub
5. teet reete a deer aed Hx ele 14 1 Serial Control Registers 14 2 SIO Prescaler Register ai ee eit tia B ta eee 14 3 viii S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 MICROCONTROLLER Table of Contents Continued Chapter 15 UART Q V VISW T 15 1 Programming Procedure A a a wak AS S a 15 1 Uart Control Register uuu te ettet ii e 15 2 Uart Interrupt Pending Register UARTPND T 15 4 Uart Data Register UDATA ss ua terne nne rte ese pete n e 15 5 Uart Baud Rate Data Register BRDATAH BRDATAL L 15 6 Baud Rate Calculations ier fett ect a e dL ie c Ra 15 6 Block Diagram iiit ie te c Iti anite tii t RT etii ease 15 8 Uart Mode 0 Function Description enne 15 9 Uart Mode 1 Function Description nene nennen ener nennen 15 10 Uart Mode 2 Function Description U 15 11 Serial Communication for Multiprocessor 15 13 Chapter 16 A D Converter OVOIVIOW in tt He td dra HE oe E ete een E 16 1 Function Description S y a ed ul eh dete id on eee deed ta ats Le as
6. src dst 2 14 F3 Irr r Given 7FH R6 21H and R7 LDCPI RR6 RO RR6 lt bRR6 1 the contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 lt bRR6 1 the contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 57 INSTRUCTION SET S3C84I8X F8418X C8419X F8419X USER S MANUAL REV 2 00 L DW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR 8 C5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register register 01H 02H register 02H 03H and register OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 03H register 01H OFH register 02H 03H register OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H Q01H Register O4H 03H register 05H OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H Z0FEDH Register 02H OFH register
7. PORTS S3C8418X F8418X C84I9X F8419X USER S MANUAL REV 2 00 PORT 1 Port 1 is a 6 bit port with individually configurable pins that you can use two ways General purpose digital I O Alternative function INTO INT3 TAOUT TACK TACAP T1OUT1 T1CK1 T1CAP1 AD5 AD6 Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H in set 1 bank 0 Port 1 Control Register P1CONH P1CONL Port 1 has two 6 bit control registers P1CONH for P1 4 P1 5 and P1CONL for P1 0 P1 3 A reset clears the P1CONH and P1CONL registers to configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Interrupt Enable Pending and Edge Selection Registers P1INT P1INTPND To process external interrupts at the port 1 pins three additional control registers are provided the port 1 interrupt enable register P1INT SET1 BANK 0 the port 1 interrupt pending bits P1INTPND SET1 BANK 0 The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects inter
8. R W Reset value 00 7 6 P4 7 COM7 SEG19 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 4 N channel open drain output 5 4 P4 6 COM6 SEG18 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 4 N channel open drain output 3 2 P4 5 COM5 SEG17 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 4 N channel open drain output 1 0 P4 4 COM4 SEG16 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 4 N channel open drain output Figure 9 11 Port 4 High Byte Control Register PACONH ELECTRONICS 9 17 PORTS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 Port 4 Control Register Low Byte PACONL Seti Reset value 00 7 6 P4 3 BUZ SEG15 Configuration Bits 0 0 2 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P4 2 SEG14 Configuration Bits 0 0 2 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P4 1 SEG13 Configuration Bits 00 Input mode 0 1 Input mode with pull up 10 Push pull output mode 1 1 N channel open drain output 1 0 P4 0 SEG12 Configuration Bits 0 0 Input mode 0 4 Input mode with pull up 1 0 Pus
9. IP lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex 1 16 2 Example The diagram below shows an example of how to use an EXIT statement Before After Address Data Address Data IP 0050 IP 0043 Address Data Address Data PC PC 0110 50 PCL old 60 Main 51 0022 Memory 22 0020 20 00 21 IPL 50 22 Data 140 Memory Stack Stack 6 42 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 INSTRUCTION SET IDLE Operation IDLE Operation See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 Example The instruction IDLE stops the CPU clock but it does not stop the system clock ELECTRONICS 6 43 INSTRUCTION SET S3C841I8X F8418X C8419X F8419X USER S MANUAL REV 2 00 INC Increment INC Operation Flags Format Examples dst dst lt dst 1
10. Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent 5 18 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To acces
11. Program Memory Register File 8 bit Register File Address dst OPERAND Point to One O CODE Register in Register One Operand File Instruction Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File UM rs RPO ot RP1 RPO RP1 Selected RP points to start of working Program Memory 4 bit Working Register dst OPCODE Point to the OPERAND Working Register Two Operand O 1 of 8 Instruction Example Sample Instruction ADD R1 R2 Where 1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using
12. 18 3 18 4 LCD Mode Control Register 0 18 4 18 5 LCD Port Control Register n nennen nennen nnn nennen 18 5 18 6 Internal Voltage Dividing Resistor 18 6 18 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias 18 7 18 8 LCD Signal Waveforms 1 4 Duty 1 3 18 8 18 9 LCD Signal Waveforms 1 3 Duty 1 3 18 9 19 1 Low Voltage Reset u uu eene a hu a nnne 19 2 S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 MICROCONTROLLER xiii Figure Number 20 1 20 2 20 3 20 4 20 5 21 1 21 2 21 3 21 4 21 5 21 6 21 7 21 8 21 9 22 1 22 2 23 1 23 2 23 3 23 4 23 5 23 6 xiv List of Figures Concluded Title Page Number Flash Memory Control Register FMCON sse 20 3 Flash Memory User Programming Enable Register FMUSR 20 4 Sectors in User Program Mode U 20 5 Flash Memory Sector Address Register 20 6 Flash Memory Sector Address Register 20 6 Input Timing for External Interrupts Ports 2 a 21 6 Input Timing formRESET none nie aeta 21 6
13. 4 2 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers Register Name Mnemonic Decimal Hex R W Timer A Timer 1 interrupt pending register Timer A control register Timer A data register Timer A counter register Timer 1 0 data register High Byte Timer 1 0 Low Byte Timer 1 1 data register High Byte data register Low Byte control register control register counter register High Byte Timer 1 0 Low Byte Timer 1 1 counter register High Byte Timer 1 1 counter register Low Byte UART baud rate data register High Byte BRDATAH UART baud rate data register Low Byte BRDATAL SIO pre scalar register SIO data register Serial I O control register PWM data register High PWM data register LOW PWM control register LCD mod register LCD port control register Watch timer control register Flash memory sector register Hige byte Flash memory sector register Low byte Flash memory user enable register Flash memory control register 2 Location FDH FFH are not mapped m m m 2 m J m zz data register m iL N m 2 i z Timer 1 Timer 1 0 Timer 1 1 Timer 1 0 aN 00 mimi O counter register a m I m zz L T z l 224 225 226 227 228 229 230 231 232 233 234
14. ADDRESS SPACES S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 11008 indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These address 1 working register address addressing Register po
15. BLOCK DIAGRAM 88 Internal Data Bus L UDATA MSO Baud Rate Ww CLK MS1 RxD P2 6 Generator Zero Detector UBATA gt Start Shift De P2 7 Tx Control Tx Clock TIP Interrupt Rx Clock RIP Receive Rx Control Start Shift 1 to 0 Transition Detector Shift Bit Detector RxD P2 6 SAMBS Internal Data Bus Figure 15 5 UART Functional Block Diagram 15 8 ELECTRONICS S3C8418X F8418X 8419X F8419X USER S MANUAL REV 2 00 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0 UART is input and output through the RxD P2 6 pin and TxD P2 7 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 00B 2 Write transmission data to the shift register UDATA F5H to start the transmission operation Mode 0 Receive Procedure 1 Select mode 0 by setting UATCON 6 and 7 to 00B 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD P2 7 pin and will read the data at the RxD P2 6 pin A UART receive interrupt vector E4H occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA IL JL JE JL IL JL dL d
16. RxD Data Out DO D1 D2 D3 D4 D5 D6 07 Transmit TxD Shift Clock Write to UARTPND Clear RIP and set RE RE Shift RxD Data In 00 D1 D2 D3 D4 D5 D6 D7 TxD Shift Clock _ _ Figure 15 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS 15 9 UART S3C8418X F8418X 8419X F8419X USER S MANUAL REV 2 00 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P2 7 pin or received through the RxD P2 6 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01 3 Write transmission data to the shift register UDATA F5H The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P1 4 pin will cause the UART module to start the serial data receive operation Tx Clock Write to Shift Register UDATA Stop Bit o c lea JL fL fL m IL sa
17. The contents of the destination operand are incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r OtoF dst 2 4 20 R 4 21 IR Given RO 1BH register and register 1BH OFH INCRO 1CH INCOOH gt Register 00H INC RO 1BH register 01H 10H In the first example if the destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register at the location assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 INSTRUCTION SET INCW Increment Word INCW dst Operation dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overfl
18. register block Figure 2 10 Non Contiguous 16 Byte Working Register Block 2 PROGRAMMING Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 respectively SRPO 80H ADD RO R1 ADC RO R2 ADC RO R3 ADC RO R4 ADC RO R5 RPO lt 80H RO lt RO R1 RO lt RO R2 C RO lt RO lt RO 4 RO RO 5 The sum these six registers 6FH is located in the register 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H ADC 80H 82H ADC 80H 83H ADC 80H 84H ADC 80H 85H 80H 80H 81H 80H 80H 82H C 80H lt 80H 83H C 80H lt 80H 84H C 80H lt 80H 85H C Now the sum of the six registers is also located in register However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working
19. tM tLOW To generate the above repeated waveform consisted of low period time t and high period time When T FF 0 ti ow TBDATAL 1 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock When T FF 1 ti ow TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock TBDATAL 1 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock make tj ow 24 us and tyigy 15 us fosc 4 MHz fx 4 MHz 4 1 MHz When T FF 0 ti ow 24 us TBDATAL 1 TBDATAL 1 x tus TBDATAL 23 tuich 15 us TBDATAH 1 TBDATAH 1 x tus TBDATAH 14 When T FF 1 15 us TBDATAL 1 fx TBDATAL 1 x 1 TBDATAL 14 ti ow 24 us TBDATAH 1 fx TBDATAH 1 x 1us TBDATAH 23 ELECTRONICS 8 BIT TIMER S3C8418X F8418X 8419X F8419X USER S MANUAL REV 2 00 Timer B Clock T FF 0 TBDATAL 01 FFH TBDATAH 00H T FF 0 TBDATAL 00H TBDATAH 01 FFH T FF 0 TBDATAL 00H TBDATAH 00H T FF 1 TBDATAL 00H TBDATAH 00H Timer B Clock 1 TBDATAL DFH TBDATAH 1FH T FF 0 TBDATAL DFH TBDATAH 1FH T FF 1 TBDATAL 7FH TBDATAH 7FH T FF 0 TBDATAL 7FH TBDATAH 7FH Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 ELEC
20. 0 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement TCM RO R 1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 TM Test under Mask TM Operation Flags Format Examples dst src dst AND src INSTRUCTION SET This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Always reset to O Unaffected Unaffected dst src src dst opc dst src Bytes Cycles 2 4 6 3 6 3 6 Opcode Hex 72 73 74 75 76 Addr Mode dst src r r r Ir R R R IR R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 02H and register 02H 23H TM TM TM TM TM
21. 24 PWM CONTROL REGISTER PAGE 13 5 PWM Control Register PWMCON F5H R W Reset 00H PWM input clock PWM OVF interrupt pending bit selection bits 0 No interrupt pending 00 fosc 64 0 Clear pending condition when write 01 fosc 8 1 Interrupt pending 10 fosc 2 11 fosc 1 PWM OVF interrupt enable bit 0 Disable interrupt Not used for 1 Enable interrupt S3C8418X F8418X C8419X F8419X PWM counter enable bit PWMDATA reload 0 Stop counter erval Se Ecion bit 1 Start resume countering 0 reload from 10bit up counter overflow 1 reload from 8bit PWM counter clear bit up counter overflow 0 No effect 1 Clear the PWM counter Figure 13 3 PWM Control Register PWMCON ELECTRONICS 23 USER S MANUAL S3C8418X F8418X C8419X F8419X ERRATA REV 2 00 25 UART BAUD RATE DATA REGISTER PAGE 15 7 Table 15 1 Commonly Used Baud Rates Generated by 16bit BRDATA BRDATAH BRDATAL ewm o o 7 m _ sah ewm o 9 3 m Pome o 9 s Ar _ o 9 o sn sesm _ ewe o 9 2 9 _ 26 Internal A D Conversion Procedure PAGE 16 5 VDD Analog ADCO Input Pin ADC7 S3C8419X F8419X S3C8418X F8418X AVss Vss NOTES 1 The symbol signifies an offset resistor with a value of from50 to 1000 2 Avref must be tied to Vdd Figure 16 5 Recommended A D Converter Circuit for Highest Absolute Accur
22. Flags Format Example NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register 005 changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3C841I8X F8418X C8419X F8419X USER S MANUAL REV 2 00 CLR Clear CLR dst Operation dst lt Flags Format Examples The destination location is cleared to O No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register 4FH register 01H 02H and register 02H 5EH CLR 00H gt Register OOH OOH 901H E Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR clears the destination register value to OOH In the second example the statement CLR 01 uses Indirect Register IR addressing mode to clear the 02H register value to 00H ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 INSTRUCTION SET Complement COM dst Operation dst lt NOT dst The contents of the destination location are complemented one s complement
23. O 0 PWM data register ow PWMDATAL 244 0 0 0 0 o o PWMcontolregister PWMCON 245 FSH 0 O O 0 O O 0 LCD mod register MOD 246 F H 0 0 0 0 0 0 LTU TUK EE eer e be re e rn Watch merconroregser WTCON eas Fen 0 0 0 Flash memory sector register FMSECH 249 F9H high byte Flash memory sector register FMSECL 250 FAH low byte o nee lee EON CH ERA EHE 8 4 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 except for the current consumption of LVR Low voltage Reset circuit All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vas to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and t
24. PWM counter stop start or resume operation PWM counter overflow 10 bit counter overflow interrupt control A reset clears all PWMCON bits to logic zero disabling the entire PWM module PWM Control Register PWMCON F5H R W Reset 00H PWM input clock PWM OVF interrupt pending bit selection bits 0 No interrupt pending 00 fxx 64 0 Clear pending condition when write 01 2 fxx 8 1 Interrupt pending 10 fxx 2 11 fxx 1 PWM OVF interrupt enable bit 0 Disable interrupt Not used for 1 Enable interrupt S3C8418X F8419X C8419X F8419X PWM counter enable bit 0 Stop counter 1 Start resume countering PWMDATA reload interval selection bit 0 reload from 10bit up counter overflow 1 reload from 8bit PWM counter clear bit up counter overflow 0 No effect 1 Clear the PWM counter Figure 13 3 PWM Control Register PWMCON ELECTRONICS 13 5 10 BIT PWM PULSE WIDTH MODULATION S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 6 7 2 bit Extend bit 8 bit up counter PWMDATAL PWMDATAH 2 bit 8 bit Counter Counter PWMCON 2 1 When REG gt Count lt Comparator P2 1 PWM 1 When REG Count 8 bit Data Extension Buffer Control Logic Extension Data A Buffer 8 bit Data Bank Register F3H PWMDATAH Seti Bank1 F4H PWMDATAL 1 0 PWMCON 3 clear 8 bit up counter overflow DATA BUS 7 0 Figur
25. Push pull output mode 1 1 N channel open drain output 1 0 P3 4 SEG8 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 9 Port 3 High Byte Control Register P3CONH 9 14 ELECTRONICS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 ELECTRONICS Port Control Register Low Byte PSCONL Set1 0 R W Reset value 00 7 6 P3 3 SEG7 Configuration Bits 0 0 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 2 SEG6 Configuration Bits 0 0 Input mode 0 1 2 Input mode with pull up 1 0 Push pull output mode 1 4 2 N channel open drain output 3 2 P3 1 SEG5 Configuration Bits 0 0 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 4 2 N channel open drain output 1 0 P3 0 SEG4 Configuration Bits 0 0 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 4 N channel open drain output Figure 9 10 Port 3 Low Byte Control Register PSCONL 9 15 PORTS PORTS S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 PROGRAMMING TIP To make as Normal I O or Alternative function ORG 0100H Reset address START DI SB1 LD LPOT is normal I O or alternative function SBO LD P3CONH 00H is input mode LD P3CONL 00H is input mode LD P3CON
26. STOP control register STOPCON 229 ESH O O O O 0 O O Port 0 control register high byte POCON 230 Location FBH is not mapped Port 1 control register high byte 0 0 0 0 0 0 0 0 Port 1 control register ow byte PICONL 233 o o o Port 1 interrupt pending register PIINTEND 234 EAH o 0 0 9 Port interrupt control register PINT 235 o o o o 9 ojo o PorZconrolregster ghbye P2CONH 234 ean o o Port 2 control register low byte P2CONL 2 esa o 0 9 ojo o Por control register high by e P3CONH 238 EH o o Boe ee s s Oe Oe Lo pending register UART data register UART control register A D converter control register ofofo ND convener dataregisterighbve 248 Fea o o o AD converte dataregisterfow byte ADDATAL 249 FH o o o o 9 2 enable contol register rarum 250 o o o o Location FBH is not mapped Location FCH is factory use only Basio timer counter register Bront 253 0 0 0 oJ 0 Location FEH is not mapped esr ELECTRONICS 8 3
27. WR INSECTOR2 LD 0 40 LD R1 40H SB1 LD FMUSR 0A5H User Program mode enable LD FMCON 01010001B Programming mode enable LD FMSECH 01H Set sector address located in target address to write data LD FMSECL 00H SECTOR2 sector base address 100H LD R9 0CCH Load data CCH to write LD R10 01H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE LD 0 40 WR 50 LD FMSECH 19H Set sector address located in target address to write data LD FMSECL 00H 50 sector base address 1900H LD 9 4 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR INSECTOR128 LD FMSECH 40H Set sector address located in target address to write data LD FMSECL 00H SECTOR128 sector base address 4000H LD R9 0A3H Load data to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE1 LDC QRR10 R9 Write data A3H at flash memory location INC R11 DJNZ R1 WR BYTE1 LD FMCON 01010000B Programming stop LD FMUSR 00H User Program mode
28. run PWM is always enabled whether run or not J102 INTO TAOUT P1 0 1 P4 7 SEG19 COM7 INT1 BUZ TACK P1 1 2 P4 6 SEG18 COM6 INT2 TACAP P1 2 3 P4 5 SEG17 COM5 INT3 T1OUT1 P1 3 4 P4 4 SEG16 COMA VDD 5 P4 3 SEG15 VSS 6 L P4 2 SEG14 XOUT 7 gt P4 1 SEG13 XIN 8 U P4 0 SEG12 TEST P3 7 SEG11 Xtin g P3 6 SEG10 Xtout 79 P3 5 SEG9 nRESET o P3 4 SEG8 TBPWM T1CKO P2 0 S P3 3 SEG7 T1CAP0 PWM P2 1 A P3 2 SEG6 T1OUTO ADA P2 2 P3 1 SEG5 AD5 T1CK1 P1 4 P3 0 SEG4 T1CAP1 AD6 P1 5 P0 3 COM3 AD3 SI AD7 P2 3 P0 2 COM2 AD2 SO SEGO P2 4 P0 1 COM1 AD1 SCK SEG1 P2 5 P0 0 COMO ADO Rx SEG2 P2 6 Avss TX SEG3 P2 7 Avref Figure 23 4 44 Pin Connector Pin Assignment for 8419 ELECTRONICS USER S MANUAL 36 J102 SEG14 P4 2 1 P4 1 SEG13 SEG15P4 3 2 P4 0 SEG12 SEG16 COM4 P4 4 3 P3 7 SEG11 SEG17 COMB P4 5 4 P3 6 SEG10 COM6 SEG18 P4 6 5 P3 5 SEG9 COM7 SEG19 P4 7 6 A P3 4 SEG8 INTO TAOUT P1 0 7 n P3 3 SEG7 INT1 BUZ TACK P1 1 8 U P3 2 SEG6 INT2 TACAP P1 2 z P3 1 SEG5 INT3 T1OUT1 P1 3 o P3 0 SEG4 VDD 79 AD3 COM3 P0 3 vss o AD2 COM2 P0 2 Xout S AD1 COM1 P0 1 Xin x ADO COMO PO 0 TEST AVss XTin m AVref XTout P2 7 SEG3 TxD nRESET P2 6 SEG2 RxD 1 2 0 P2 5 SEG1 SCK PWM T1CAPO P2 1 P2 4 SEGO SO T1OUTO ADA4 P2 2 P2 3 AD7 SI Figure 23 5 42 Pin Connector Pin Assignment for 8419 Target Board Target System J101 201090000 Ulg pt 201090000 Ulg pt Figure
29. 1 1 Alternative function mode TAOUT output Figure 9 3 Port 1 Low Byte Control Register P1 CONL ELECTRONICS USER S MANUAL S3C8418X F8418X C8419X F8419X ERRATA REV 2 00 15 PORT CONTROL REGISTERS PAGE 9 9 PORT2 Port 2 is an 8 bit port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 P2 0 P2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions General purpose digital I O Alternative function SEGO SEG3 ADC4 ADC7 SI T1OUTO T1CK0 TBPWM PWM 16 PORT CONTROL REGISTERS PAGE 9 10 MSB 16 Port 2 Control Register High Byte P2CONH Seti R W Reset value 00 Ef 6 5 4 3 2 4 0 LSB 7 6 P2 7 SEG3 TxD Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 10 Push pull output mode 11 Alternative function mode TxD output 5 4 P2 6 SEG2 RxD Configuration Bits 0 0 Input mode RxD iput 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode RxD output 3 2 P2 5 SEG1 SCK Configuration Bits 0 0 Input mode SCK input 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode output 1 0 P2 4 SEG0 SO Configur
30. 10 Bit PWM Pulse Width Modulation Programming the PWM Module to Sample Specifications a 13 7 Chapter 14 Serial Interface SIQ Q S pU 14 5 Chapter 16 Converter Configuring A D GORVeT eruu eire h ite Au u ha epe Es 16 6 Chapter 17 Watch Timer Using the Watehy e e eet etd 17 4 Chapter 20 Embedded Flash Memory Interface Sector Erase Not to use an interrupt 20 7 Sector Erase To use an 20 7 Programimifigi a ante ane dt kuku ku paqa 20 9 Read u 20 11 Hard Kock Protectlon stot rede M Ee od e eie eg 20 12 S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 MICROCONTROLLER xvii Register Identifier ADCON BTCON CLKCON FMCON FMSECH FMSECL FMUSR FLAGS IMR IPL IPR IRQ LMOD LPOT OSCCON POCON P1CONH P1CONL P1INTPND P1INT P2CONH P2CONL P2PUR P3CONH P3CONL P4CONH P4CONL PP PWMCON RPO 1 SIOCON SIOPS SPH SPL STOPCON SYM T1CONO T1CON1 TACON TBCON TINTPND UARTCON UARTPND WTCON List of Register Descriptions Full Register Name A D Converter Control Register Basic Timer Control Register
31. 70H POPUI 02H Q00H gt Register 02H register 01H 70H register 02H 70H If the general register contains the value 01H and the register 01H the value 70H the statement POPUI 02 loads the value 70H into the destination general register 02H The user stack pointer the register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3C84I8X F8418X C8419X F8419X USER S MANUAL REV 2 00 PUSH Push to Stack PUSH Operation Flags Format Examples src SP SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4 5 00H and SPL 00H PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and the general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH
32. Clock Timing Measurement at 21 8 Stop Mode Release Timing initiated by 21 9 Stop Mode Main Release Timing Initiated by Interrupts 21 10 Stop Mode Sub Release Timing Initiated by Interrupts 21 10 Waveform for UART Timing 21 11 Operating Voltage Range 21 13 The Circuit Diagram to Improve EFT Characteristics 21 14 42 SDIP 600 Package 22 1 44 QFP 1010 Package Dimensions 22 2 Development System Configuration 23 2 S3F8419X S3F8418X Target Board Configuration 23 3 DIP Switch for Smart 23 5 44 Pin Connector Pin Assignment for 9 23 6 42 Pin Connector Pin Assignment for 19 23 7 8419 Adapter Cable for 44pin Connector Package 23 7 S3C8418X F8418X C8419X F8419X USER S MANUAL REV 2 00 MICROCONTROLLER List of Tables Table Title Page Number Number 1 1 S3C8418X F8418X C84I9X F84I9X Pin
33. ELECTRONICS 23 3 DEVELOPMENT TOOLS S3C8418X F8418X 8419X F8419X USER S MANUAL REV 2 00 Table 23 1 Components of 8419 18 Symbols Usage Description CN1 100 pin connector Connection between emulator and TB8419 8 target board J101 J102 50 pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to S3F8419X 8X EVA chip VCC GND POWER connector External power connector for TB8419 8 IDLE STOP LED STOP IDLE Display Indicate the status of STOP or IDLE of S3F8419X 8X EVA chip on 819 8 target board Table 23 2 Power Selection Settings for 8419 To User_Vcc Settings Operating Mode To User_Vbp SMDS2 or SK 1000 supplies 8419 Vpp to the target board ff jee evaluation chip and the target system SMDS2 or SK 1000 To User SMDS2 or SK 1000 supplies F Vpp only to the target board ff 9 n evaluation chip The target system must have a power supply of its own SMDS2 or SK 1000 IDLE LED This LED is ON when the evaluation chip 53 8410 is in idle mode STOP LED This LED is ON when the evaluation chip 53 8410 is in stop mode 23 4 ELECTRONICS S3C8418X F8418X 8419X F8419X USER S MANUAL REV 2 00 HU UL 0 1 2 3FH 7 Low NOTE Smart option is determined by DIP switch Figure 23 3 DIP Switch for Smart Option DEV
34. Example dst src dst lt src IR lt IR 1 This instruction is used for user defined stacks in the register file The contents of the register file lo