ANALOG DEVICES AD708 English products handbook Rev C
Contents
1. Table 1 AD708J AD708A AD708B AD708S Parameter Conditions Min Typ Min Typ Typ Unit INPUT OFFSET VOLTAGE 30 100 5 50 5 30 uV Tmn to Tmax 50 150 15 65 15 50 uV Drift 0 3 1 0 0 1 0 4 0 1 0 3 uV C Long Term Stability 0 3 0 3 0 3 uV month INPUT BIAS CURRENT 1 0 2 5 0 5 1 0 0 5 1 nA Tmn to Tmax 2 0 4 0 1 0 2 0 1 0 4 nA Average Drift 15 40 10 25 10 30 pA C OFFSET CURRENT Vcem 0V 0 5 2 0 0 1 1 0 0 1 1 nA Tmn to Tmax 2 0 4 0 0 2 1 5 0 2 1 5 nA Average Drift 2 60 1 25 1 25 MATCHING CHARACTERISTICS Offset Voltage 80 50 30 uV Tmn to Tmax 150 75 50 uV Offset Voltage Drift 1 0 0 4 0 3 uV C Input Bias Current 4 0 1 0 1 0 nA Tmn tO Tmax 5 0 2 0 2 0 nA Common Mode Rejection 120 140 130 140 130 140 dB Tmn to Tmax 110 130 130 dB Power Supply Rejection 110 120 120 dB Tmn to Tmax 110 120 120 dB Channel Separation 135 140 140 dB INPUT VOLTAGE NOISE 0 1 Hz to 10 Hz 0 23 0 6 0 23 0 6 0 23 0 35 uV p p f 10Hz 10 3 18 103 12 10 3 12 nV 4Hz f 100 Hz 10 0 13 0 10 0 11 0 10 0 11 nV 4Hz f 1kHz 96 11 0 96 11 0 96 11 nV 4Hz INPUT CURRENT NOISE 0 1 Hz to 10 Hz 14 35 14 35 14 35 pA p p 10 2 0 32 0 9 0 32 0 8 0 32 0 8 pA VHz f 100 Hz 0 14 0 27 0 14 0 23 0 14 0 23 pA VHz f 1kHz 0 12 0 18 0 12 0 17 0 12 0 17 pA VHz COMMON MODE REJECTION RATIO Vem 13 V 120 140 130 140 130 140 dB Tmn to Tmax 120 140 130 140 130 140 dB OPEN LOOP GAIN Vo 10V Rioap gt 2 3 10 5 10 4 10 V uV Tmn2. 05789 008 DIFFERENTIAL VOLTAGE V Figure 8 Input Bias Current vs Differential Input Voltage 05789 009 0 1 1 FREQUENCY Hz Figure 9 Input Noise Spectral Density EE UNE TRAIN II V UNE RIP NT 05789 010 TIME 1s DIV Figure 10 0 1 Hz to 10 Hz Voltage Noise OPEN LOOP GAIN dB Rev C Page 7 of 16 OPEN LOOP GAIN V uV OPEN LOOP GAIN V uV 140 120 100 o 40 20 0708 05789 011 TEMPERATURE Figure 11 Open Loop vs Temperature Ri 2kQ 05789 012 0 5 10 15 20 25 SUPPLY VOLTAGE V Figure 12 Open Loop Gain vs Supply Voltage 2kQ C 1000pF 30 60 90 PHASE MARGIN 43 120 150 GAIN 180 001 041 1 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 13 Open Loop Gain and Phase vs Frequency PHASE Degrees 05789 013 0708 160 2mV DIV EN A N 100 COMMON MODE REJECTION dB H1 05789 014 05789 017 0 1 1 10 100 1k 10k 100k FREQUENCY Hz TIME 2us DIV Figure 14 Common Mode Rejection vs Frequency Figure 17 Small Signal Transient Response 1 2
3. 50 pF a rf lt E 9 gt n E 2 o CH1 1k 10k 100k 1M TIME 2us DIV FREQUENCY Hz Figure 15 Large Signal Frequency Response Figure 18 Small Signal Transient Response Av 1 2 C 1000 pF 160 140 ao 5 gt 120 o 5 Q 100 ul 80 gt amp 2 60 o 40 o n 20 0 8 0 001 0 01 0 1 1 10 100 1k 10k 100k FREQUENCY Hz Figure 16 Power Supply Rejection vs Frequency Rev C Page 8 of 16 AD708 MATCHING CHARACTERISTICS 32 16 28 14 24 12 o o E E z 20 10 2 2 16 8 2 12 6 i i 8 n 4 4 2 2 0 8 0 8 50 40 30 20 10 0 10 20 30 40 50 1 0 08 0 6 0 4 0 2 0 02 04 06 0 8 1 0 OFFSET VOLTAGE MATCH pV OFFSET CURRENT MATCH nA Figure 19 Typical Distribution of Offset Voltage Match Figure 22 Typical Distribution of Input Offset Current Match 32 160 55 TO 125 28 140 S 24 120 p 20 100 Lu o 16 80 lt 12 2 60 wi o n ui 40 4 8 20 amp 0 8 0 8 0 5 04 03 02 01 0 01 02 03 04 0 5 60 40 20 0 20 40 60 80 100 120 140 OFFSET DRIFT
4. The three op amp programmable gain amplifier shown in Figure 29 takes advantage of the outstanding matching characteristics of the AD708 to achieve high dc precision AD708 05789 029 Figure 29 Precision PGA The gains of the circuit are controlled by the select lines AO and Al of the AD7502 multiplexer and are 1 10 100 and 1000 in this design The input stage attains very high dc precision due to the 30 uV maximum offset voltage match of the AD708S and the 1 nA maximum input bias current match The accuracy is main tained over temperature because of the ultralow drift performance of the AD708 To achieve 0 196 gain accuracy along with high common mode rejection the circuit should be trimmed To maximize common mode rejection 1 Set the select lines for gain 1 and ground Vins 2 Applya precision dc voltage to Vina and trim until Vo Vma to the required precision 3 Connect Vins to Vina and apply an input voltage equal to the full scale common mode expected 4 Trim Rez until Vo 0 V To minimize gain errors 1 Select gain 10 with the control lines and apply differential input voltage 2 Adjust the 100 potentiometer to Vo 10 adjust Vin magnitude as necessary 3 Repeat Step 1 and Step 2 for gain 100 and gain 1000 adjusting the 1 and 10 potentiometers respectively The design shown in Figure 29 should allow for 0 1 gain accuracy and 0 1 uV V common mod
5. C unless otherwise noted COMMON MODE VOLTAGE LIMIT V REFERRED TO SUPPLY VOLTAGES 0 5 10 15 20 SUPPLY VOLTAGE V Figure 2 Input Common Mode Range vs Supply Voltage a OUTPUT VOLTAGE SWING tV 5 REFERRED TO SUPPLY VOLTAGES 0 5 10 15 20 SUPPLY VOLTAGE V Figure 3 Output Voltage Swing vs Supply Voltage w a wo N a N PPLIES a OUTPUT VOLTAGE V 10 100 1k LOAD RESISTANCE Figure 4 Output Voltage Swing vs Load Resistance 05789 004 05789 002 25 05789 003 25 Rev 6 of 16 SUPPLY CURRENT NUMBER OF UNITS OUTPUT IMPEDANCE 100 05789 005 3 6 9 12 15 18 21 SUPPLY VOLTAGE V N A Figure 5 Supply Current vs Supply Voltage 256 UNITS TESTED 55 C 125 0 4 03 02 0 1 0 0 1 0 2 0 3 0 100 10 0 1 0 01 0 001 05789 006 gt OFFSET VOLTAGE DRIFT uV C Figure 6 Typical Distribution of Offset Voltage Drift Ay 1000 05789 007 0 1 1 10 100 1k 10k 100k FREQUENCY Hz Figure 7 Output Impedance vs Frequency INPUT VOLTAGE NOISE nVA Hz INEST CURRENT IA INPUT VOLTAGE NOISE 100nV DIV
6. Ceramic Dual In Line Package CERDIP Q 8 Dimensions shown in inches and millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD708JN 0 to 70 8 Lead Plastic Dual In Line Package PDIP N 8 AD708JNZ 0 to 70 8 Lead Plastic Dual In Line Package PDIP N 8 AD708AQ 40 to 85 8 Lead Ceramic Dual In Line Package CERDIP Q 8 AD708BQ 40 to 85 8 Lead Ceramic Dual In Line Package CERDIP Q 8 AD708SQ 883B 55 C to 125 C 8 Lead Ceramic Dual In Line Package CERDIP Q 8 17 Pb free part Rev C Page 13 of 16 AD708 NOTES Rev C Page 14 of 16 AD708 NOTES Rev C Page 15 of 16 AD708 NOTES 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners C05789 0 1 06 C DEVICES www analog com Rev C Page 16 of 16
7. MATCH TEMPERATURE C Figure 20 Typical Distribution of Offset Voltage Drift Match Figure 23 PSRR Match vs Temperature 16 160 14 140 12 120 o E 10 S 100 o u 8 80 gt 5 6 60 5 40 2 z 20 i 0 s 0 3 1 0 08 06 04 02 0 02 04 06 08 1 0 60 40 20 0 20 40 60 80 100 120 140 INPUT BIAS CURRENT MATCH nA TEMPERATURE C Figure 21 Typical Distribution of Input Bias Current Match Figure 24 CMRR Match vs Temperature Rev C Page 9 of 16 AD708 THEORY OF OPERATION CROSSTALK PERFORMANCE The AD708 exhibits very low crosstalk as shown in Figure 25 gt 10 Figure 26 and Figure 27 Figure 25 shows the offset voltage induced on Side B of the AD708 when Side A output is moving slowly 0 2 Hz from 10 V to 10 V under no load This is the least stressful situation to the part because the overall power in the chip does not change Only the location of the power in the output device changes Figure 26 shows the input offset voltage change to Side B when Side A is driving a 2 kO load Here the power changes in the chip with the maximum power change occurring at 7 5 V Figure 27 shows crosstalk under the most severe conditions Side A is connected as a follower with 0 V input and is forced to sink and source 5 mA of output current 1uVIDIV Power 30 V 5 mA 150 mW Even this large change in power causes only an 8 uV linear change in the input offset
8. voltage of Side B AVosB Vin 10V 05789 026 Vouta 2V DIV Figure 26 Crosstalk with 2 Load VourB AVosg 1uVIDIV 05789 025 2uV DIV SERED AINE Vouta 2V DIV Figure 25 Crosstalk with No Load 05789 027 INA 1mA DIV Figure 27 Crosstalk Under Forced Source and Sink Conditions Rev C Page 10 of 16 OPERATION WITH A GAIN OF 100 To show the outstanding dc precision of the AD708 in a real application Table 3 shows an error budget calculation for a gain of 100 This configuration is shown in Figure 28 Table 3 Maximum Error Contribution 100 S Grade Error Sources Full Scale Vou 10 V Vin 100 mV Vos 30 uV 100 mV 300 ppm los 100 kO 1 nA 10 V 10 ppm Gain 2 kO Load 10V 5x106 100mV 20 ppm Noise 0 35 mV 100 mV 4ppm Vos Drift 0 3 mV C 100 mV 3 ppm C Total Unadjusted Error 25 C 334 ppm gt 11 bits 55 to 125 C 634 ppm gt 10 bits With Offset Calibrated Out 25 C 34 ppm gt 14 bits 55 to 125 C 334 ppm gt 11 bits 100kO 05789 028 Figure 28 Gain of 100 Configuration This error budget assumes no error in the resistor ratio and no error from power supply variation the 120 dB minimum PSRR of the AD708S makes this a good assumption The external resistors can cause gain error from mismatch and drift over temperature HIGH PRECISION PROGRAMMABLE GAIN AMPLIFIER
9. ANALOG DEVICES Ultralow Offset Voltage Dual Amp AD708 FEATURES Very high dc precision 30 pV maximum offset voltage 0 3 pV C maximum offset voltage drift 0 35 uV maximum voltage noise 0 1 Hz to 10 Hz 5 million V V minimum open loop gain 130 dB minimum CMRR 120 dB minimum PSRR Matching characteristics 30 pV maximum offset voltage match 0 3 pV C maximum offset voltage drift match 130 dB minimum CMRR match Available in 8 lead narrow body PDIP and hermetic CERDIP and CERDIP 883B packages GENERAL DESCRIPTION The AD708 is a high precision dual monolithic operational amplifier Each amplifier individually offers excellent dc precision with maximum offset voltage and offset voltage drift of any dual bipolar op amp The matching specifications are among the best available in any dual op amp In addition the AD708 provides 5 V V mini mum open loop gain and guaranteed maximum input voltage noise of 350 nV 0 1 Hz to 10 Hz dc specifications show excellent stability over temperature with offset voltage drift typically 0 1 uV C and input bias current drift of 25 pA C maximum The AD708 is available in four performance grades The AD708 is rated over the commercial temperature range of 0 C to 70 C and is available in a narrow body PDIP The AD708A and AD708B are rated over the industrial temperature range of 40 C to 85 C and are available in a CERDIP Rev C Information fumished by Analo
10. IONS 0 400 10 16 0 365 9 27 0 355 9 02 8 5 0 280 7 11 0 250 6 35 7 0 250 6 35 7 4 0 240 6 10 PIN 1 77 e D 0 310 7 87 0 100 2 54 0 300 M 62 886 0 060 1 at 0 195 4 95 533 0 130 3 30 ita 0 015 0 115 2 92 0 150 3 81 088 0 015 038 0 130 3 30 0 115 2 92 an PLANE 0 014 0 36 rick es 00840 0 022 0 56 0430 1032 0 018 0 eee ty gt 1005 0 13 0 014 0 36 B 0070 1 78 0 060 1 52 0 045 1 14 COMPLIANT STANDARDS MS 001 BA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS Figure 33 8 Lead Plastic Dual In Line Package PDIP Narrow Body N 8 Dimensions shown in inches and millimeters AD708 0 005 0 13 0 055 1 40 Rx 0 310 7 87 0 220 5 59 je 0 100 2 54 BSC 0 405 29 0 320 8 13 e 290 7 ar 0200 5 08 0 060 1 52 0 015 0 38 0 200 5 08 N pi 3 81 0 125 3 18 0 023 0 58 Ae 2015 0 008 0 20 2 0 014 0 36 0 070 78 PLANE 15 0 030 0 76 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 34 8 Lead
11. addition the tight offset voltage drift match maintains the resolution of the circuit over the full military temperature range The high dc open loop gain and exceptional gain linearity allows the circuit to perform well at both large and small signal levels In this circuit the only significant dc errors are due to the offset voltage of the two amplifiers the input offset current match of the amplifiers and the mismatch of the resistors Errors associated with the AD708S contribute less than 0 001 error over 55 C to 125 C Maximum error at 25 C 30 uV 10 ko 1 nA 10V 40 uV 10 uV 4 ppm Maximum error at 125 C or 55 C 50 uV 2 nA 10 10 V 7 ppm 125 C Figure 32 shows vs Vn for this circuit with a 3 mV input signal at 0 05 Hz Note that the circuit exhibits very low offset at the zero crossing This circuit can also produce Vour Vin by reversing the polarity of the two diodes 1mV DIV Vour 05789 032 Vin 1mVIDIV Figure 32 Absolute Value Circuit Performance Input Signal 0 05 Hz SELECTION OF PASSIVE COMPONENTS Use high quality passive components to take full advantage of the high precision and low drift characteristics of the AD708 Discrete resistors and resistor networks with temperature coefficients of less than 10 ppm C are available from Vishay Caddock Precision Replacement Parts PRP and others Rev C Page 12 of 16 OUTLINE DIMENS
12. e RH RHENUS 1 Crosstalk Performance essent 10 General Description teet e eee ee 1 Operation with a Gain of 100 sse 11 Product Highlights seen 1 High Precision Programmable Gain Amplifier 11 Revision History sirenai ER E ER R 2 Bridge Signal Conditioner see 12 Specifications et 3 Precision Absolute Value Circuit ss 12 Absolute Maximum Ratings eee 5 Selection of Passive Components sse 12 ESD etui dediti tse iens 5 Outlin Dimensions ete rette ite eie itane 13 Typical Performance Characteristics sse 6 Ordering ciere tae iere te 13 Matching Characteristics seen 9 REVISION HISTORY 1 06 Rev B to Rev C Updated Format Universal Removed TO 99 Package Universal Deleted AD707 References sse Universal Deleted LT1002 Reference seen 1 Deleted RERO ERES 1 Deleted Metalization Photograph sse 5 Moved Figure 25 Figure 26 and Figure 27 to Theory of Operation section sse 10 Updated Outline Dimensions seen 13 Changes to Ordering Guide sse 13 2 91 Rev A to Rev B Rev C 2 of 16 SPECIFICATIONS 25 and 15 V dc unless otherwise noted AD708
13. e rejection when 1 resistors and 5 potentiometers are used Rev Page 11 of 16 AD708 BRIDGE SIGNAL CONDITIONER The AD708 can be used in the circuit shown in Figure 30 to produce an accurate and inexpensive dynamic bridge condi tioner The low offset voltage match and low offset voltage drift match of the AD708 combine to achieve circuit performance better than all but the best instrumentation amplifiers The outstanding specifications of the AD708 such as open loop gain input offset currents and low input bias currents do not limit circuit accuracy As configured the circuit only requires a gain resistor Re of suitable accuracy and a stable accurate voltage reference The transfer function is Vo Vrer AR R The only significant errors due to the AD708S are Vos ovr Vos_matcu 2Rc R 30 mV Vos ovr T Vos purr 2Ro R 0 3 mV C To achieve high accuracy Resistor should be 0 1 or better with a low drift coefficient 15V 05789 030 15V Figure 30 Bridge Signal Conditioning Circuit 10kQ 10kQ IN4591 lt 1 2 5kQ AD708 O Vo 05789 031 1LOW LEAKAGE DIODES Figure 31 Precision Absolute Value Circuit PRECISION ABSOLUTE VALUE CIRCUIT The AD708 is ideally suited to the precision absolute value circuit shown in Figure 31 The low offset voltage match of the AD708 enables this circuit to accurately resolve the input signal In
14. g Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property their respective owners PIN CONFIGURATION 05789 001 TOP VIEW Not to Scale Figure 1 PDIP N and CERDIP Q Packages The 7085 is rated over the military temperature range of 55 C to 125 C and is available in a CERDIP military version processed to MIL STD 883B PRODUCT HIGHLIGHTS 1 Thecombination of outstanding matching and individual specifications make the AD708 ideal for constructing high gain precision instrumentation amplifiers 2 The low offset voltage drift and low noise of the AD708 allow the designer to amplify very small signals without sacrificing overall system performance 3 The AD708 10 V uV typical open loop gain and 140 dB common mode rejection make it ideal for precision applications One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD708 TABLE OF CONTENTS iu MP 1 Theory Of ODeratIOD dete 10 Pin Configuration eoe e Re
15. ge Vs Output Short Circuit Duration Indefinite Differential Input Voltage Vs and Vs Storage Temperature Range Q 65 to 150 C Storage Temperature Range N 65 to 125 C Lead Temperature Soldering 60 sec 300 C Thermal Characteristics 8 lead PDIP 33 C W Oya 100 C W 8 lead CERDIP 9 30 C W 8a 110 C W For supply voltages less than 22 V the absolute maximum input voltage is equal to the supply voltage ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate AD708 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability the human body and test equipment and can discharge without detection Although this product features lt proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit 4 electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev C Page 5 of 16 AD708 TYPICAL PERFORMANCE CHARACTERISTICS Vs 15 and Ta 25
16. to Tmax 3 10 5 10 4 7 V uV POWER SUPPLY REJECTION RATIO Vs 3Vto 18V 110 130 120 130 120 130 dB Tmn to Tmax 110 130 120 130 120 130 dB FREQUENCY RESPONSE Closed Loop Bandwidth 0 5 0 9 0 5 0 9 0 5 0 9 MHz Slew Rate 0 15 03 0 15 0 3 0 15 03 V us INPUT RESISTANCE Differential 60 200 200 MO Common Mode 200 400 400 GO Rev C Page3 of 16 0708 AD708J AD708A AD708B AD708S Parameter Conditions Min Typ Min Typ Min Typ Unit OUTPUT VOLTAGE Roan gt 10 13 5 14 13 5 140 13 5 14 V gt 2 12 5 13 0 12 5 13 0 12 5 13 V Rioad gt 1 120 125 12 0 12 5 12 0 12 5 V Tmn to Tmax 12 0 13 0 120 13 0 12 0 13 OPEN LOOP OUTPUT RESISTANCE 60 60 60 Q POWER SUPPLY Quiescent Current 45 5 5 45 5 5 45 5 5 mA Power Consumption Vs 15V 135 165 135 165 135 165 mW Vs 3V 12 18 12 18 12 18 mW Operating Range 3 18 3 18 3 18 1 All min and max specifications are guaranteed Specifications in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing quality levels Input offset voltage specifications are guaranteed after five minutes of operation at TA 25 Matching is defined as the difference between parameters of the two amplifiers Rev C Page4 of 16 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Supply Voltage 22 Internal Power Dissipation Input Volta
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ANALOG DEVICES AD708 English products handbook Rev C