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ANALOG DEVICES Zero-Drift Single-Supply Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574 English products handbook Rev E

1. 0 95 15 MAX 0 85 1 10 MAX ran 120 vs tempt a U 015 F s 0 23 ll 9 30 COPLANARITY 239 SEATING 0 20 T 0 05 0 40 T 0 09 1 0 10 0 19 PLANE 0 60 0 25 0 40 0 09 0 45 COPLANARITY d e 0 10 3 COMPLIANT TO JEDEC STANDARDS MO 153 AA COMPLIANT TO JEDEC STANDARDS MO 187 AA E m Figure 71 8 Lead Thin Shrink Small Outline Package TSSOP Figure 69 8 Lead Mini Small Outline Package MSOP 9 RU 8 gel RM 8 r F a TOUT Dimensions shown in millimeters Dimensions shown in millimeters 5 00 0 1968 p ce 80 0 1890 ji 8 5 4 00 0 1574 6 20 I 2441 3 80 0 1497 4 4 5 80 0 2284 p 1 27 0 0500 0 50 0 0196 z BSC 1 75 0 0688 r 0 25 0 0099 I T 0 25 0 0098 mm 1 35 0 0532 z Ani 0 10 0 0040 Y HHI yy 0 65 BSC 0 51 0 0201 gt ke SE don 7031 la 0122 0 B 0098 1 27 0 0500 100 1 20 SEATING 0 25 0 0098 515 0 0157 Geo MAX E PLANE 0 17 0 0067 C c 0 09 14 0 75 0 15 N tt lt 0 60 oas gt SEATING Ls l 0 60 COMPLIANT TO JEDEC STANDARDS MS 012 AA 0 05 0 30 PLANE o 0 45 CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS COPLANARITY 0 19 IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR i REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 012407 A 061908 A COMPLIANT TO JEDEC STANDARDS MO 153 AB 1 Figure 72 14 Lead Thin Shrink Small Outline Package TSSOP RU 14 Dimensio
2. Vin 60mV p p 1 1 a A rd o 1 n 200us 1V i d 3 E FREQUENCY Hz Figure 34 PSRR vs Frequency 140 140 Vs 2 5V 120 120 100 100 PSRR g 80 S 80 I a 3 60 2 60 40 40 PSRR 20 20 0 h 0 100 1k 10k 100k 1M 10M 3 100 1k 10k 100k 1M 10M FREQUENCY Hz FREQUENCY Hz Figure 32 CMRR vs Freguency Figure 35 PSRR vs Freguency 140 Vs 5v 120 100 a 2 8 80 z x z 60 i 2 E 40 a 20 0 100 1k Bu TEE IM TM 3 100 1k 10k 100k 1M E Hz 5 FREQUENCY Hz Figure 33 CMRR vs Frequency Figure 36 Maximum Output Swing vs Frequency Rev E Page 10 of 24 OUTPUT SWING V p p AD8571 AD8572 AD8574 Vs 2 5V RL 2kQ Ay 1 THD N lt 1 en nVNHz 0 0 5 1 0 1 5 2 0 2 5 FREQUENCY kHz 01104 037 01104 040 FREQUENCY Hz Figure 37 Maximum Output Swing vs Frequency Figure 40 Voltage Noise Density from 0 Hz to 2 5 kHz Vs 1 35V Ay 120 0 en nVWHz 01104 038 0 5 10 15 20 25 3 FREQUENCY kHz Figure 38 0 1 Hz to 10 Hz Noise Figure 41 Voltage Noise Density from 0 Hz to 25 kHz Vs 2 5V Ay 120 000 f z gt E c o d
3. 01104 023 01104 024 Figure 24 Large Signal Transient Response 01104 022 AD8571 AD8572 AD8574 SMALL SIGNAL OVERSHOOT 01104 025 10 100 1k 10k CAPACITANCE pF 01104 028 Figure 25 Small Signal Transient Response Figure 28 Small Signal Overshoot vs Load Capacitance ov Vs 2 5V VIN I Vin 200mV p p RET TO GND C 0pF Ry 10ko Ay 100 Vour g ov i 20us 1V BOTTOM SCALE 1V DIV TOP SCALE 200mV DIV 01104 029 Figure 29 Positive Overvoltage Recovery Vin 200mV p p RET TO GND C OpF RL 10kQ Ay 7 100 SMALL SIGNAL OVERSHOOT BOTTOM SCALE 1V DIV TOP SCALE 200mV DIV 01104 030 01104 027 CAPACITANCE pF Figure 27 Small Signal Overshoot vs Load Capacitance Figure 30 Negative Overvoltage Recovery Rev E Page 9 of 24 AD8571 AD8572 AD8574
4. 200 175 150 125 100 OUTPUT VOLTAGE mV TEMPERATURE C 01104 048 Figure 48 Output Voltage to Supply Rail vs Temperature Rev E Page 13 of 24 AD8571 AD8572 AD8574 FUNCTIONAL DESCRIPTION The AD8571 AD8572 AD8574 are CMOS amplifiers that achieve their high degree of precision through random frequency auto zero stabilization The autocorrection topology allows the AD857x to maintain its low offset voltage over a wide temperature range and the randomized auto zero clock eliminates any inter modulation distortion IMD errors at the amplifier output The AD857x can run from a single supply voltage as low as 2 7 V The extremely low offset voltage of 1 uV and no IMD products allow the amplifier to be easily configured for high gains without risk of excessive output voltage errors which makes the AD857x an ideal amplifier for applications requiring both dc precision and low distortion for ac signals The extremely small temperature drift of 5 nV C ensures a minimum of offset voltage error over its 40 C to 125 C temperature range These combined features make the AD857x an excellent choice for a variety of sensitive measurement and automotive applications AMPLIFIER ARCHITECTURE Each AD857x op amp consists of two amplifiers a main amplifier and a secondary amplifier that is used to correct the offset voltage of the main amplifier Both consist of a rail to ra
5. 2 m ui m 2 5 z z 3 0 1 2 3 4 5 s i i INPUT COMMON MODE VOLTAGE V INPUT OFFSET DRIFT nV C 3 Figure 8 Input Bias Current vs Input Common Mode Voltage Figure 11 Input Offset Voltage Drift Distribution 1500 10k 1000 1k lt lt amp 500 E E E ii 100 E 0 lt 3 3 a gt SOURCE lt 500 5 10 m a m E E 1000 o z 1 1500 0 1 a 2000 1 2 3 4 58 0 0001 0 001 0 01 0 1 1 10 100 5 3 3 COMMON MODE VOLTAGE V LOAD CURRENT mA Figure 9 Input Bias Current vs Common Mode Voltage Figure 12 Output Voltage to Supply Rail vs Load Current Rev E Page 6 of 24 AD8571 AD8572 AD8574 10k lt 1k x ul S E a 100 lt m ui a o 2 5 10 u E 4 5 5 o o gt 1 a a gt o 0 1 o 0 0001 0 001 0 01 0 1 1 10 100 5 0 1 2 3 4 5 6 5 LOAD CURRENT mA SUPPLY VOLTAGE V z Figure 13 Output Voltage to Supply Rail vs Load Current Figure 16 Supply Current per Amplifier vs Supply Voltage 1000 60 Vs 27V Vom 2 5V s 7 50 CL OpF Vg 5V R oh 40 0 lt 750 r 2 a 9 S 30 45 3 z o g 3 20 90 Q 500 amp 10 435 E o Ir lt 9 o m 3 0 180 ui o 5 a i 10 225 T a o Z 250 zi 20 270 30 0 40 k 75 50 25 0 25 50 75 100 125 150 3
6. offsetting the tendency of the noise to increase exponentially as frequency decreases which allows the AD857x to have lower noise near dc than standard low noise amplifiers that are susceptible to 1 f noise RANDOM AUTO ZERO CORRECTION ELIMINATES INTERMODULATION DISTORTION The AD857x can be used as a conventional op amp for gains up to 1 MHz The auto zero correction frequency of the device continuously varies based on a pseudorandom generator with a uniform distribution from 2 kHz to 4 kHz The randomization of the autocorrection clock creates a continuous randomization of IMD products that show up as simple broadband noise at the output of the amplifier This broadband noise naturally combines with the amplifier voltage noise in a root squared sum fashion resulting in an output free IMD Figure 56 shows the spectral output of an AD8572 with the amplifier configured for unity gain and the input grounded Figure 57 shows the spectral output with the amplifier configured for a gain of 60 dB OUTPUT SIGNAL 01104 056 1 2 3 4 5 6 7 8 9 10 FREQUENCY kHz Figure 56 Spectral Analysis of AD8572 Output in Unity Gain Configuration OUTPUT SIGNAL 01104 057 FREQUENCY kHz Figure 57 Spectral Analysis of AD857x Output with 60 dB Gain Figure 58 shows the spectral output of an AD8572 configured in a high gain 60 dB with a 1 mV input signal applie
7. 10k 100k 1M 10M 100M 5 i TEMPERATURE C FREQUENCY Hz Figure 14 Input Bias Current vs Temperature Figure 17 Open Loop Gain and Phase Shift vs Frequency 1 0 60 Vs 5V 50 CL 0pF RL 0 8 40 0 E o6 2 o 2 W ra o E 5 o 1 135 amp I o o E gt 0 4 3 0 180 w a ui a a lt 2 o 0 225 T 0 2 20 270 30 0 o 40 2 75 50 25 0 25 50 75 100 125 150 5 10k 100k 1M 10M 100M 8 TEMPERATURE C FREQUENCY Hz Figure 15 Supply Current vs Temperature Figure 18 Open Loop Gain and Phase Shift vs Freguency Rev E Page 7 of 24 AD8571 AD8572 AD8574 CLOSED LOOP GAIN dB CLOSED LOOP GAIN dB OUTPUT IMPEDANCE Q 10k FREQUENCY Hz Figure 19 Closed Loop Gain vs Frequency 40 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 20 Closed Loop Gain vs Frequency 300 270 Vs 2 7V 240 210 180 150 120 30 Ay 1 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 21 Output Impedance vs Frequency OUTPUT IMPEDANCE Q 01104 020 01104 019 01104 021 Rev E Page 8 of 24 300 270 240 210 180 150 120 FREQUENCY Hz Figure 22 Output Impedance vs Frequency
8. AD857x is 51 nV VHz and the input noise in is 2 fA VHz The en rora is dominated by the input voltage noise provided that the source resistance is less than 172 kQ With source resistance greater than 172 kO the overall noise of the system is dominated by the Johnson noise of the resistor itself Because the input current noise of the AD857x is very small in does not become a dominant term unless rs gt 4 GO which is an impractical value of source resistance The total noise e rorat is expressed in volts per square root Hertz and the equivalent rms noise over a certain bandwidth can be found as En en TOTAL X 4a BW 16 where BW is the bandwidth of interest in Hertz OUTPUT OVERDRIVE RECOVERY The AD857x amplifiers have an excellent overdrive recovery of only 200 us from either supply rail This characteristic is particularly difficult for autocorrection amplifiers because the nulling amplifier requires a substantial amount of time to error correct the main amplifier back to a valid output Figure 29 and Figure 30 show the positive and negative overdrive recovery times for the AD857x The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail The input voltage is then stepped do
9. Temperature Soldering 60 sec 300 C P pen Differential input voltage is limited to 5 0 V or the supply voltage Table 4 Thermal Resistance Whichever ss less Package Type Osa Bic Unit 8 Lead SOIC R 158 43 C W 8 Lead MSOP RM 190 44 C W 8 Lead TSSOP RU 240 43 C W 14 Lead SOIC R 120 36 C W 14 Lead TSSOP RU 180 36 C W ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage dy 4 may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev E Page 5 of 24 AD8571 AD8572 AD8574 TYPICAL PERFORMANCE CHARACTERISTICS 180 180 160 160 o 140 o 140 i g ur 120 i 120 3 a a 100 100 lt lt u u O 80 O 80 f I u ul B2 I P gt a z z 40 40 liil p 0 S 0 o 2 5 1 5 0 5 0 5 1 5 2 5 H 2 5 1 5 u 0 5 1 5 2 5 5 OFFSET VOLTAGE uV OFFSET VOLTAGE uV Figure 7 Input Offset Voltage Distribution Figure 10 Input Offset Voltage Distribution Vs 5V TA 40 C 25 C 85 C TA 40 C TO 125 C lt o 5 wa E u z u P a 3 o u o lt
10. available in 14 lead narrow SOIC and TSSOP packages One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 1999 2011 Analog Devices Inc All rights reserved AD8571 AD8572 AD8574 TABLE OF CONTENTS Features s etr e Ue 1 Applications toe o e Ee HP UR o On too 1 General Descriptl0D eene eR 1 Pin Configurations ceccsessessesssessesseesessesssesessessesssessesseeseeseess 1 REevisiOniHIStory lt e jeni sivi a R eS 2 Specifications op en e ete PROPER Reds 3 5 V Electrical Characteristics sse 3 2 7 V Electrical Characteristics see 4 Absolute Maximum Ratings sse 5 Thermal Characteristics eerte 5 TNI DAON i a lol o OAERTN 5 Typical Performance Characteristics sse 6 Functional Description ttr ttti 14 Amplifier Architecture sep la innii iais 14 Basic Auto Zero Amplifier Theory sss 14 AutozZ ro Phases js eiie ene nene de eene ett 15 Amplification Phase 15 High Gain CMRR and PSRR sss 16 REVISION HISTORY 2 11 Rev D to Rev E Changes to Figure 66 21 Updated Outline Dimensions eerte 22 Changes to Ordering Guide sees 23 6 08 Rev C to Rev D Changes to Figure 19 and Figure 20 sse 8 Changes to Figure 44 Changes to Figure 38 Moved Figure 50 and Figure 51 sss 1
11. noted Table 2 Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage Vos 1 5 uV 40 C lt Ta lt 125 C 10 uV Input Bias Current ls 10 50 pA AD8571 AD8574 40 C lt Ta lt 125 C 1 0 1 5 nA AD8572 40 C lt TA lt 85 C 160 300 pA 40 C lt Ta lt 125 C 2 5 4 nA Input Offset Current los 10 50 pA AD8571 AD8574 40 C lt Ta lt 125 C 150 200 pA AD8572 40 C lt Ta lt 85 C 30 150 pA 40 C lt Ta lt 125 C 150 400 pA Input Voltage Range 0 2 7 V Common Mode Rejection Ratio CMRR Vem OV to 2 7 V 115 130 dB 40 C lt TA lt 125 C 110 130 dB Large Signal Voltage Gain Avo R 10 KO Vo 0 3 V to 2 4 V 110 140 dB 40 C lt Ta lt 125 C 105 130 dB Offset Voltage Drift AVos AT 40 C lt Ta lt 125 C 0 005 0 04 uV C OUTPUT CHARACTERISTICS Output Voltage High Von RL 100 kO to GND 2 685 2 697 V Ri 100 kO to GND 40 C to 125 C 2 685 2 696 V RL 10 kO to GND 2 67 2 68 V Ri 10 kO to GND 40 C to 125 C 2 67 2 675 V Output Voltage Low Vor Ri 100 KO to V 1 10 mV Ri 100 kO to V 40 C to 125 C 2 10 mV Ri 10 kO to V 10 20 mV Ri 10 kO to V 40 C to 125 C 15 20 mV Short Circuit Limit Isc 10 15 mA 40 C to 125 C 10 mA Output Current lo 10 mA 40 C to 125 C 5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 7Vto5 5V 120 130 dB 40 C lt TA lt 125 C 115 130 dB Supply Curren
12. 1000 USE 0 19 TOLERANCE RESISTORS 01104 063 Figure 63 5 V Precision Strain Gage Amplifier 3 V INSTRUMENTATION AMPLIFIER The high common mode rejection high open loop gain and operation down to 3 V of the supply voltage make the AD857x family an excellent op amp choice for discrete single supply instrumentation amplifiers The common mode rejection ratio of the AD857x is greater than 120 dB but the CMRR of the system is also a function of the external resistor tolerances The gain of the difference amplifier shown in Figure 64 is given as Yos V ki Ju E v2 22 18 R3 RA RZ RI R2 v2 Vout VI AD8571 R4 AD8572 AD8574 R4 R2 R2 H IF gs gp THEN Vout pi X VI V2 i Figure 64 Using the AD857x as a Difference Amplifier In an ideal difference amplifier the ratio of the resistors is set equal to R2 R4 19 Y RI R3 Set the output voltage of the system to Vour Av VI V2 20 Due to finite component tolerance the ratio between the four resistors is not exactly equal and any mismatch results in a reduction of common mode rejection from the system Referring to Figure 64 the exact common mode rejection ratio can be expressed as RIR4 2R2R4 R2R3 CMRR 21 2RIRA 2R2R3 In the 3 op amp instrumentation amplifier configuration shown in Figure 65 the output difference amplifier is set to unity gain with all four resistors equal in value If the tolerance of t
13. 4 Changes to Figure 66 Precision Current Meter Section Layout Figure 67 Equation 24 and Figure 68 sss 21 5 07 Rev B to Rev C Changes to Features Changes to Table I eerte ete iret c pi RR Changes to Table 2 5er iore rmt eret rer ase 4 Changes to Basic Auto Zero Amplifier Theory Section 14 Changes t Figure 50 esee eee ttt teer tede 15 Changes to Figure DS inser rise noge po pese tet ep ke ovija 16 Changes to Figure 66 21 Updated Outline Dimensions seen 22 Maximizing Performance Through Proper Layout 16 1 f Noise Characteristics seen 17 Random Auto Zero Correction Eliminates Intermodulation Distortions 17 Broadband and External Resistor Noise Considerations 18 Output Overdrive Recovery sse 18 Input Overvoltage Protection sse 18 Output Phase Reversal sse 18 Capacitive Load Drive eerte 19 Power Up Behavior zia 19 Applications Information 20 5 V Precision Strain Gage Circuit sess 20 3 V Instrumentation Amplifier sse 20 High Accuracy Thermocouple Amplifier 21 Precision Current Meter sss 21 Precision Voltage Comparator 21 Outline Dimensions ysna E 22 Ordering Guide sisisi r s 23 9 06 Rev A to Rev B Updated Formati see tne hen Er ne ente Univ
14. 5V 120 140 dB 40 C lt TA lt 125 C 115 130 dB Large Signal Voltage Gain Avo R 10 KO Vo 0 3 V to 4 7 V 125 145 dB 40 C lt Ta lt 125 C 120 135 dB Offset Voltage Drift AVos AT 40 C lt Ta 125 C 0 005 0 04 uV C OUTPUT CHARACTERISTICS Output Voltage High Von RL 100 kO to GND 499 4 998 V Ri 100 kQ to GND 40 C to 125 C 4 99 4 997 V RL 10 kO to GND 4 95 4 98 V Ri 10 kO to GND 40 C to 125 C 4 95 4 975 V Output Voltage Low VoL Ri 100 kO to V 1 10 mV R 100 kO to V 40 C to 125 C 2 10 mV Ri 10 kO to V 10 30 mV Ri 10 kO to V 40 C to 125 C 15 30 mV Short Circuit Limit Isc 25 50 mA 40 C to 125 C 40 mA Output Current lo 30 mA 40 C to 125 C 15 mA POWER SUPPLY Power Supply Rejection Ratio PSRR Vs 2 7 V to 5 5 V 120 130 dB 40 C lt Ta 125 C 115 130 dB Supply Current per Amplifier Isy Vo 0V 850 975 MA 40 C lt Ta lt 125 C 1000 1075 MA DYNAMIC PERFORMANCE Slew Rate SR Ri 10 kO 0 4 V us Overload Recovery Time 0 05 0 3 ms Gain Bandwidth Product GBP 1 5 MHz NOISE PERFORMANCE Voltage Noise en p p OHzto 10 Hz 1 3 UV p p OHzto 1 Hz 0 41 UV p p Voltage Noise Density en f 1kHz 51 nV 4Hz Current Noise Density in f 10Hz 2 fA VHz 1 Gain testing is dependent upon test bandwidth Rev E Page 3 of 24 AD8571 AD8572 AD8574 2 7 V ELECTRICAL CHARACTERISTICS Vs 2 7 V Vou 1 35 V Vo 1 35 V Ta 25 C unless otherwise
15. ANALOG Zero Drift Single Supply Rail to Rail DEVICES Input Output Operational Amplifiers AD8571 AD8572 AD8574 FEATURES Low offset voltage 1 pV Input offset drift 0 005 pV C Rail to rail input and output swing 5 V 2 7 V single supply operation High gain 145 dB typical CMRR 140 dB typical PSRR 130 dB typical Ultralow input bias current 10 pA typical Low supply current 750 pA per op amp Overload recovery time 50 us No external capacitors required APPLICATIONS Temperature sensors Pressure sensors Precision current sensing Strain gage amplifiers Medical instrumentation Thermocouple amplifiers GENERAL DESCRIPTION This family of amplifiers has ultralow offset drift and bias current The AD8571 AD8572 and AD8574 are single dual and quad amplifiers respectively featuring rail to rail input and output swings All are guaranteed to operate from 2 7 V to 5 V single supply The AD857x family provides benefits previously found only in expensive auto zeroing or chopper stabilized amplifiers Using Analog Devices Inc topology these zero drift amplifiers combine low cost with high accuracy No external capacitors are required Using a patented spread spectrum auto zero technique the AD857x family eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications With an offset voltage of only 1 uV and drift of 0 005 uV C the AD857x family i
16. ARZ 40 C to 125 C 8 Lead SOIC_N R 8 AD8572ARZ REEL 40 C to 125 C 8 Lead SOIC_N R 8 AD8572ARZ REEL7 40 C to 125 C 8 Lead SOIC_N R 8 AD8572ARUZ 40 C to 125 C 8 Lead TSSOP RU 8 AD8572ARUZ REEL 40 C to 125 C 8 Lead TSSOP RU 8 AD8574AR 40 C to 125 C 14 Lead SOIC_N R 14 AD8574AR REEL 40 C to 125 C 14 Lead SOIC_N R 14 AD8574AR REEL7 40 C to 125 C 14 Lead SOIC_N R 14 AD8574ARZ 40 C to 125 C 14 Lead SOIC_N R 14 AD8574ARZ REEL 40 C to 125 C 14 Lead SOIC_N R 14 AD8574ARZ REEL7 40 C to 125 C 14 Lead SOIC_N R 14 AD8574ARU 40 C to 125 C 14 Lead TSSOP RU 14 AD8574ARU REEL 40 C to 125 C 14 Lead TSSOP RU 14 AD8574ARUZ 40 C to 125 C 14 Lead TSSOP RU 14 AD8574ARUZ REEL 40 C to 125 C 14 Lead TSSOP RU 14 1 Z RoHS Compliant Part denotes RoHS compliant product may be top or bottom marked Rev E Page 23 of 24 AD8571 AD8572 AD8574 NOTES 1999 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D01104 0 2 11 E DEVICES www analo g com Rev E Page 24 of 24
17. OR Figure 67 shows a high side current monitor configuration The AD857x can be operated open loop and used as a precision Here the input common mode voltage of the amplifier is at or comparator The AD857x have less than 50 uV of offset voltage near the positive supply voltage The rail to rail input of the when they run in this configuration The slight increase of amplifier provides a precise measurement even with the input offset voltage stems from the fact that the autocorrection common mode voltage at the supply voltage The CMOS input architecture operates with the lowest offset in a closed loop structure does not draw any input bias current ensuring a configuration that is one with negative feedback With 50 mV minimum of measurement error of overdrive the device has a propagation delay of 15 us on the rising edge and 8 us on the falling edge The 0 1 Q resistor creates a voltage drop to the noninverting input of the AD857x The output of the amplifier is corrected Care should be taken to ensure that the maximum differential until this voltage appears at the inverting input which creates a voltage of the device is not exceeded For more information see current through RI that in turn flows through R2 The monitor the Input Overvoltage Protection section output is given by Rev E Page 21 of 24 AD8571 AD8572 AD8574 OUTLINE DIMENSIONS 3 20 4 50 3 00 440 6 40 BSC 2 80 430 PIN 1 IDENTIFIER
18. ces which is another characteristic of rail to rail output amplifiers BASIC AUTO ZERO AMPLIFIER THEORY Autocorrection amplifiers are not a new technology Various IC implementations have been available for more than 15 years and some improvements have been made over time The AD857x design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost This section offers a simplified explanation of how the AD857x is able to offer extremely low offset voltages and high open loop gains As noted in the Amplifier Architecture section each AD857x op amp contains two internal amplifiers One is used as the primary amplifier and the other as an autocorrection or nulling amplifier Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input In Figure 50 and Figure 51 these are labeled as Vosa and Voss where A denotes the nulling amplifier and B denotes the primary amplifier The open loop gain for the IN and IN inputs of each amplifier is given as Ax Both amplifiers also have a third voltage input with an associated open loop gain of Bx Voss Vint O Vin 01104 050 Figure 50 Auto Zero Phase of the Amplifier Vosa OVouT 01104 051 VNA Figure 51 Output Phase of the Amplifier There are two modes of operation determined by the action of two sets of switches in
19. d Note the absence of any IMD products in the spectrum The signal to noise ratio SNR of the output signal is better than 60 dB or 0 196 OUTPUT SIGNAL 01104 058 FREQUENCY kHz Figure 58 Spectral Analysis of AD8572 in High Gain with an Input Signal Rev E Page 17 of 24 AD8571 AD8572 AD8574 BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS The total broadband noise output from any amplifier is primarily a function of three types of noise input voltage noise from the amplifier input current noise from the amplifier and Johnson noise from the external resistors used around the amplifier Input voltage noise or en is strictly a function of the amplifier used The Johnson noise from a resistor is a function of the resistance and the temperature Input current noise or in creates an equivalent voltage noise proportional to the resistors used around the amplifier These noise sources are not correlated with each other and their combined noise sums in a root squared sum fashion The full equation is given as TOTAL e AKTr int s 0 15 where e is the input voltage noise of the amplifier in is the input current noise of the amplifier rs is the source resistance connected to the noninverting terminal k is Boltzmanns constant 1 38 x 107 J K T is the ambient temperature in Kelvin K 273 15 C The input voltage noise density e of the
20. e output is at 0 V Using the values shown in Figure 66 the output voltage tracks temperature at 10 mV C For a wider range of temperature measurement R9 can be decreased to 62 kO This creates a MONITOR 5 mV C change at the output allowing measurements of up 2 49kQ 3 to 1000 C 5 Figure 67 High Side Load Current Monitor Figure 68 shows the low side monitor eguivalent In this circuit the input common mode voltage to the AD8572 is at or near ground Again a 0 1 Q resistor provides a voltage drop propor tional to the return current The output voltage is given as R1 10 7kQ 1N4148 R2 Monitor Output V Sr Rs TA 24 K TYPE THERMOCOUPLE 40 7uV C For the component values shown in Figure 68 the monitor output transfer function is V 2 49 V A 0 C TO 500 C 01104 066 i i ifi MONITOR Figure 66 Precision K Type Thermocouple Amplifier OUTPUT with Cold Junction Compensation PRECISION CURRENT METER Because of its low input bias current and superb offset voltage at single supply voltages the AD857x family is an excellent amplifier for precision current monitoring Its rail to rail input allows the amplifier to be used as either a high side or a low side current monitor Using both amplifiers in the AD8572 provides a simple method to monitor both current supply and return paths for 01104 068 Figure 68 Low Side Load Current Monitor toad Se fant dete dnom PRECISION VOLTAGE COMPARAT
21. ersal Changes to Table I 0 a eie S di eS 3 Changes to Table 2 ottime te 4 Changes to Figure 50 eite eee niei eei ea 14 Changes to Figure 51 cerei teet ein 15 Changes to Figure 66 sse nentes 21 Deleted Figure 69 and SPICE Macro Model Section 17 Deleted SPICE Macro Model for the AD857x Section 18 Updated Outline Dimensions seen 22 Changes to Ordering Guide sse 23 7 03 Rev 0 to Rev A Renumbered Figures sse Universal Changes to Ordering Guide sse 4 Change to Figure 15 2 dote tt teet 16 Updated Outline Dimensions seen 19 10 99 Revision 0 Initial Version Rev E Page 2 of 24 AD8571 AD8572 AD8574 SPECIFICATIONS 5 V ELECTRICAL CHARACTERISTICS Vs 5 V Vou 2 5 V Vo 2 5 V Ta 25 C unless otherwise noted Table 1 Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage Vos 1 5 uV 40 C lt Ta lt 125 C 10 uV Input Bias Current ls 10 50 pA AD8571 AD8574 40 C lt Ta lt 125 C 1 0 1 5 nA AD8572 40 C lt Ta lt 85 C 160 300 pA 40 C lt Ta lt 125 C 2 5 4 nA Input Offset Current los 20 70 pA AD8571 AD8574 40 C lt Ta lt 125 C 150 200 pA AD8572 40 C lt TA lt 85 C 30 150 pA 40 C lt Ta lt 125 C 150 400 pA Input Voltage Range 0 5 V Common Mode Rejection Ratio CMRR Ven 2 OVto
22. f the amount of offset voltage an amplifier has as a result of a change in its input common mode or power supply voltages As shown in the Amplification Phase section the autocorrection architecture of the AD857x allows it to effectively minimize offset voltages The technique also corrects for offset errors caused by common mode voltage swings and power supply variations which results in superb CMRR and PSRR figures in excess of 130 dB Because the autocorrection occurs continuously these figures can be maintained across the temperature range of the device 40 C to 125 C MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD857x care should be taken in the circuit board layout The PCB surface must remain clean and free of moisture to avoid leakage currents between adjacent traces Surface coating of the circuit board reduces surface moisture and provides a humidity barrier reducing parasitic resistance on the board The use of guard rings around the amplifier inputs further reduces leakage currents Figure 52 shows how the guard ring should be configured and Figure 53 shows the top view of how a surface mount layout can be arranged The guard ring does not need to be a specific width but it should form a continuous loop around both inputs By setting the guard ring voltage equal to the voltage at the non inverting input parasitic capac
23. he resistors used in the circuit is given as 5 the worst case CMRR of the instrumentation amplifier is 1 CMRR 22 28 MIN AD8574 A v2 AD8574 B 01104 065 2R Vour 1 Rg V1 V2 Figure 65 Discrete Instrumentation Amplifier Configuration Therefore using 196 tolerance resistors results in a worst case system CMRR of 0 02 or 34 dB To achieve high common mode rejection either high precision resistors or an additional trimming resistor as shown in Figure 65 should be used The value of this trimming resistor should be equal to the value of R multiplied by its tolerance For example using 10 kQ resistors with 196 tolerance would require a series trimming resistor equal to 100 9 Rev E Page 20 of 24 AD8571 AD8572 AD8574 HIGH ACCURACY THERMOCOUPLE AMPLIFIER Monitor Output R2 x Rsense R1 x I 23 Figure 66 shows a K type thermocouple amplifier configuration Using the components shown in Figure 67 the monitor output with cold junction compensation Even from a 5 V supply the transfer function is 2 49 V A AD8571 can provide enough accuracy to achieve a resolution of better than 0 02 C from 0 C to 500 C D1 is used as a tempera RSENSE LN V ture measuring device to correct the cold junction error from the thermocouple and should be placed as close as possible to the two terminating junctions With the thermocouple measuring tip immersed in a 0 C ice bath R6 should be adjusted until th
24. il input stage allowing the input common mode voltage range to reach both supply rails The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail to rail output stage The wide voltage swing of the amplifier is achieved by using two output transistors in a common source configuration The output voltage range is limited by the drain to source resistance of these transistors As the amplifier is required to source or sink more output current the voltage drop across these transistors increases due to their on resistance Ros Simply put the output voltage does not swing as close to the rail under heavy output current conditions as it does with light output current This is a characteristic of all rail to rail output amplifiers Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current The output of the AD857x is short circuit protected to approximately 50 mA of current The AD857x amplifiers have exceptional gain yielding greater than 120 dB of open loop gain with a load of 2 kQ Because the output transistors are configured in a common source configuration the gain of the output stage and thus the open loop gain of the amplifier is dependent on the load resistance Open loop gain decreases with smaller load resistan
25. itance is minimized as well For further reduction of leakage currents components can be mounted to the PCB using Teflon standoff insulators y Vout i AD8572 Vin AD8572 Vour AD8572 Vour Figure 52 Guard Ring Layout and Connections to Reduce PCB Leakage Currents 01104 052 V R1 R2 AD8572 R2 R1 VIN1 VIN2 GUARD GUARD RING VREF RING VREF 01104 053 V Figure 53 Top View of AD8572 SOIC Layout with Guard Rings Other potential sources of offset error are thermoelectric voltages on the circuit board This voltage also called Seebeck voltage occurs at the junction of two dissimilar metals and is proportional to the junction temperature The most common metallic junctions on a circuit board are solder to board trace and solder to component lead Figure 54 shows a cross section view of the thermal voltage error sources When the temperature of the PCB at one end of the component Tai differs from the temperature at the other end Taz the Seebeck voltages are not equal resulting in a thermal voltage error This thermocouple error can be reduced by using dummy components to match the thermoelectric error source Placing the dummy component as close as possible to its partner ensures that both Seebeck voltages are equal thus canceling the thermo couple error Maintaining a constant ambient temperature on the circuit board further reduces this error The use of a ground plane helps distribute heat throughout the boa
26. lification phase Voa Vys so this can be rewritten as Vourlt V 9 AsV t T ApVosn B A Vin t lt 1 B Combining terms yield Vourlt A B V 10 Vin As i A B p PA Apos 1 B The AD857x architecture is optimized in such a way that Aa As Ba Bs and Ba gt gt 1 In addition the gain product to AaBs is much greater than As Therefore Equation 10 can be simplified to Vovr t Vin t AaBa Aa Vosat Voss 11 Most obvious is the gain product of both the primary and nulling amplifiers This AaBa term is what gives the AD857x its extremely high open loop gain To understand how Vosa and Voss relate to the overall effective input offset voltage of the complete amplifier set up the generic amplifier equation of Vovr k x Vin Vos EFF 12 where kis the open loop gain of an amplifier Vos rrr is its effective offset voltage Putting Equation 12 into the form of Equation 11 gives Vovrlt Vin t AaBa Vos errAaBa 13 Rev E Page 15 of 24 AD8571 AD8572 AD8574 Therefore _ OSA OSB 14 Thus the offset voltages of both the primary and nulling amplifiers are reduced by the gain factor Ba which takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts This autocorrection scheme makes the AD857x family of amplifiers extremely precise HIGH GAIN CMRR AND PSRR Common mode and power supply rejection are indications o
27. ng and overshoot AD8571 AD8572 AD8574 lt o c S Rx 600 CL Cx 4 7nF g 0 47uF Figure 59 Snubber Network Configuration for Driving Capacitive Loads VIN O 200mV p p 01104 059 Although the snubber network does not recover the loss of amplifier bandwidth from the load capacitance it does allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing Figure 60 shows the output of an AD857x driving a 1 nF capacitor with and without a snubber network 10us WITH SNUBBER WITHOUT SNUBBER Vs 5V CL 4 7nF 1 190my 01104 060 Figure 60 Overshoot and Ringing Are Substantially Reduced Using a Snubber Network The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically because actual C includes stray capacitances and can differ substantially from the nominal capacitive load Table 5 shows some snubber network values that can be used as starting points Table 5 Snubber Network Values for Driving Capacitive Loads C nF Rx Q Cx 1 200 1nF 4 7 60 0 47 uF 10 20 10 uF POWER UP BEHAVIOR At power up the AD857x settles to a valid output within 5 ps Figure 61 shows an oscilloscope photo of the output of the amplifier along with the power supply voltage Figure 62 shows the test circuit With the amplifier c
28. ns shown in millimeters Figure 70 8 Lead Standard Small Outline Package SOIC NJ Narrow Body R 8 Dimensions shown in millimeters and inches Rev E Page 22 of 24 AD8571 AD8572 AD8574 8 75 0 3445 8 55 0 3366 4 00 0 1575 6 20 0 2441 3 80 0 1496 5 80 0 2283 T Ly ol le 121 9 0500 0 50 0 0197 _ 4go 1 75 0 0689 025 0 0098 0 25 0 0095 1 35 0 0531 8 0 10 0 0039 v n Ty Fo L COPLANARITY alle SEATING LJ Bes 0 10 0 51 0 0201 PLANE 0 25 0 0098 1 27 0 0500 0 31 0 0122 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012 AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 73 14 Lead Standard Small Outline Package SOIC N Narrow Body R 14 Dimensions shown in millimeters and inches 060606 A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8571ARZ 40 C to 125 C 8 Lead SOIC_N R 8 AD8571ARZ REEL 40 C to 125 C 8 Lead SOIC_N R 8 AD8571ARZ REEL7 40 C to 125 C 8 Lead SOIC_N R 8 AD8571ARMZ 40 C to 125 C 8 Lead MSOP RM 8 AJA AD8571ARMZ REEL 40 C to 125 C 8 Lead MSOP RM 8 AJA AD8572AR 40 C to 125 C 8 Lead SOIC_N R 8 AD8572AR REEL 40 C to 125 C 8 Lead SOIC_N R 8 AD8572AR REEL7 40 C to 125 C 8 Lead SOIC_N R 8 AD8572
29. nts of current can flow through these diodes causing permanent damage to the device If inputs are subject to overvoltage appropriate series resistors should be inserted to limit the diode current to less than 2 mA OUTPUT PHASE REVERSAL Output phase reversal occurs in some amplifiers when the input common mode voltage range is exceeded As common mode voltage moves outside the common mode range the outputs of these amplifiers suddenly jump in the opposite direction to the supply rail This is the result of the differential input pair shutting down causing a radical shifting of internal voltages that results in the erratic output behavior The AD857x amplifier has been carefully designed to prevent any output phase reversal provided that both inputs are maintained within the supply voltages If one or both inputs exceed either supply voltage a resistor should be placed in series with the input to limit the current to less than 2 mA to ensure that the output does not reverse its phase Rev E Page 18 of 24 AD8571 AD8572 AD8574 CAPACITIVE LOAD DRIVE The AD857x have excellent capacitive load driving capabilities and can safely drive up to 10 nF from a single 5 V supply Although the device is stable capacitive loading limits the bandwidth of the amplifier Capacitive loads also increase the amount of overshoot and ringing at the output The RC snubber network shown in Figure 59 can be used to reduce the capacitive load ringi
30. onfigured for unity gain the device takes approximately 5 us to settle to its final output voltage hundreds of microseconds faster than many other autocorrection amplifiers BOTTOM TRACE 2V DIV TOP TRACE 1V DIV Figure 61 AD857x Output Behavior at Power Up 01104 061 D Vsy OV TO 5v lt o c S AD8571 AD8572 V AD8574 01104 062 Figure 62 AD857x Test Circuit for Power Up Time Rev E Page 19 of 24 AD8571 AD8572 AD8574 APPLICATIONS INFORMATION 5 V PRECISION STRAIN GAGE CIRCUIT The extremely low offset voltage of the AD8572 makes it an ideal amplifier for any application requiring accuracy with high gains such as a weigh scale or strain gage Figure 63 shows a configura tion for a single supply precision strain gage measurement system The REF192 provides a 2 5 V precision reference voltage for A2 The A2 amplifier boosts this voltage to provide a 4 0 V reference for the top of the strain gage resistor bridge Q1 provides the current drive for the 350 bridge network A1 is used to amplify the output of the bridge with the full scale output voltage equal to 2 x RI R2 R 17 where Rz is the resistance of the load cell Using the values given in Figure 63 the output voltage linearly varies from 0 V with no strain to 4 V under full strain Q1 2N2222 OR EQUIVALENT AD8572 B 12kQ 4 0V R3 NOTE 17 4kQ
31. rd and also reduces EMI noise pickup COMPONENT LEAD MM v SOLDER SC2 SET y SURFACE MOUNT V COMPONENT A N PC BOARD Ta2 IF Ta Tag THEN Vrsi Vsci Vts2 Vsc2 COPPER TRACE 01104 054 Figure 54 Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error RF R1 Vout AD8571 AD8572 Re Ri AD8574 Ay 1 Re R1 Rs SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES 01104 055 Figure 55 Using Dummy Components to Cancel Thermoelectric Voltage Errors Rev E Page 16 of 24 AD8571 AD8572 AD8574 1 f NOISE CHARACTERISTICS Another advantage of auto zero amplifiers is their ability to cancel flicker noise Flicker noise also known as 1 f noise is noise inherent in the physics of semiconductor devices and increases 3 dB for every octave decrease in frequency The 1 f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier At lower frequencies flicker noise dominates causing higher degrees of error for sub Hertz frequencies or dc precision applications Because the AD857x amplifiers are self correcting op amps they do not have increasing flicker noise at lower frequencies In essence low frequency noise is treated as a slowly varying offset error and is greatly reduced with autocorrection The correction becomes more effective as the noise frequency approaches dc
32. s now open and there is no place for Cm to discharge the voltage Vxa at the present time t is equal to the voltage at the output of the nulling amp Voa at the time when QD Ax is closed If the period of the autocorrection switching frequency is designated as Ts the amplifier switches between phases every 0 5 x Ts Therefore in the amplification phase VNA t vut d 4 and substituting Equation 4 and Equation 2 into Equation 3 yields 1 AB Yo 2 d 5 Voa t A Vin t A Vosalt 1 8B A For the sake of simplification it can be assumed that the auto correction frequency is much faster than any potential change in Vosa or Voss This is a good assumption because changes in offset voltage are a function of temperature variation or long term wear time both of which are much slower than the auto zero clock frequency of the AD857x which effectively makes the Vos time invariant and Equation 5 can be rewritten as A 1 F Ba Vosa d A 4B Vos 1 B Vo t A Vin t 6 or V V A V 7 oa lt Dd Here the auto zeroing becomes apparent Note that the Vos term is reduced by a factor of 1 Ba which shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier Therefore the primary amplifier output voltage is the voltage at the output of the AD857x amplifier It is equal to Vovr t As Vi t Voss BaVus 8 In the amp
33. s perfectly suited for applications where error sources cannot be tolerated Position and pressure sensors medical equipment and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range Many more systems require the rail to rail input and output swings provided by the AD857x family Rev E Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners PIN CONFIGURATIONS 01104 001 NC NO CONNECT Figure 1 8 Lead MSOP RM Suffix 01104 004 NC NO CONNECT Figure 2 8 Lead SOIC R Suffix AD8572 TOP VIEW Not to Scale 01104 002 AD8572 TOP VIEW Not to Scale 01104 005 01104 003 01104 006 Figure 6 14 Lead SOIC R Suffix The AD857x family is specified for the extended industrial automotive temperature range 40 C to 125 C The AD8571 single amplifier is available in 8 lead MSOP and narrow SOIC packages The AD8572 dual amplifier is available in 8 lead narrow SOIC and surface mount TSSOP packages The AD8574 quad amplifier is
34. sac 50mV g 0 0 5 1 0 1 5 2 0 25 FREQUENCY kHz Figure 39 0 1 Hz to 10 Hz Noise Figure 42 Voltage Noise Density from 0 Hz to 2 5 kHz Rev E Page 11 of 24 AD8571 AD8572 AD8574 en nVWHz en nVAHz 0 5 10 15 20 25 FREQUENCY kHz Figure 43 Voltage Noise Density from 0 Hz to 25 kHz 210 180 150 120 90 60 30 FREQUENCY Hz Figure 44 Voltage Noise Density from 0 Hz to 10 Hz POWER SUPPLY REJECTION dB 01104 043 OUTPUT SHORT CIRCUIT CURRENT mA 01104 044 Rev E Page 12 of 24 150 145 140 135 130 75 50 25 0 25 50 75 100 125 150 TEMPERATURE C Figure 45 Power Supply Rejection vs Temperature TEMPERATURE C Figure 46 Output Short Circuit Current vs Temperature 01104 045 01104 046 AD8571 AD8572 AD8574 100 z Vg 5V E E 60 mi Isc 40 t 2 u E 20 2 lt o 0 5 o o gt z 20 5 3 E n 3 5 SC m 60 E 2 o 80 100 E 75 50 235 0 25 50 75 100 125 150 3 75 50 25 0 25 50 75 100 125 150 3 TEMPERATURE C TEMPERATURE C 2 Figure 47 Output Short Circuit Current vs Temperature Figure 49 Output Voltage to Supply Rail vs Temperature 250 225
35. t per Amplifier Isy Vo 0V 750 900 MA 40 C lt Ta lt 125 C 950 1000 MA DYNAMIC PERFORMANCE Slew Rate SR Ri 10 kO 0 5 V us Overload Recovery Time 0 05 ms Gain Bandwidth Product GBP 1 MHz NOISE PERFORMANCE Voltage Noise en p p OHzto 10Hz 2 0 uV p p Voltage Noise Density en f 1 kHz 94 nV VHz Current Noise Density in f 10Hz 2 fA VHz 1 Gain testing is dependent upon test bandwidth Rev E Page 4 of 24 AD8571 AD8572 AD8574 ABSOLUTE MAXIMUM RATINGS Table 3 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any Supply Voltage 6V a wes i i other conditions above those indicated in the operational section of Input Voltage GND to Vs 0 3 V ji ka pies d 1 i this specification is not implied Exposure to absolute maximum Differential Input Voltage 5 0 V ditions fi tended period affect devi liabili ESD Human Body Model 2000 V rating conditions for extended periods may affect device reliability Output Short Circuit Duration to GND Indefinite THERMAL CHARACTERISTICS St T ture R 65 C to 150 C o Mois Mou MCG e 40 C 2 125 C Oja is specified for the worst case conditions that is Oya is P i Ing peratu 9 specified for a device soldered in a circuit board for SOIC and Junction Temperature Range 65 C to 150 C TSSOP packages Lead
36. the amplifier an auto zero phase and an amplification phase Rev E Page 14 of 24 AD8571 AD8572 AD8574 AUTO ZERO PHASE In this phase all DAx switches are closed and all B switches are open Here the nulling amplifier is taken out of the gain loop by shorting its two inputs together Of course there is a degree of offset voltage shown as Vosa inherent in the nulling amplifier that maintains a potential difference between the IN and IN inputs The nulling amplifier feedback loop is closed through A and Vosa appears at the output of the nulling amplifier and on Cm an internal capacitor in the AD857x Mathematically this can be expressed in the time domain as Voalt AaVosa t BAVoa t 1 This can also be expressed as A AVosa le 1 B Volt 2 The previous equations show that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the Cui capacitor AMPLIFICATION PHASE When the DOB switches close and the Ax switches open for the amplification phase the offset voltage remains on CM1 and essentially corrects any error from the nulling amplifier The voltage across Cm is designated as Vya The potential difference between the two inputs to the primary amplifier is designated as Vin or Vin Vins Vin The output of the nulling amplifier can then be expressed as Voa t Aa Vin t Vosa t BaVwa t 3 Because D Ax i
37. wn to the linear region of the amplifier usually to halfway between the supplies The time from the input signal step down to the output settling to within 100 uV of its final value is the overdrive recovery time Many autocorrection amplifiers require a number of auto zero clock cycles to recover from output overdrive and some can take several milliseconds for the output to settle properly INPUT OVERVOLTAGE PROTECTION Although the AD857x are rail to rail input amplifiers care should be taken to ensure that the potential difference between the inputs does not exceed 5 V Under normal operating conditions the amplifier corrects its output to ensure that the two inputs are at the same voltage However if the device is configured as a comparator or is under some unusual operating condition the input voltages may be forced to different potentials which could cause excessive current to flow through the internal diodes in the AD857x used to protect the input stage against overvoltage If either input exceeds either supply rail by more than 0 3 V large amounts of current begin to flow through the ESD protection diodes in the amplifier These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse biased However if the input voltage exceeds the supply voltage these ESD diodes become forward biased Without current limiting excessive amou

ANALOG DEVICES Zero-Drift Single-Supply Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574 English products handbook Rev E

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