ANALOG DEVICES AD8061/AD8062/AD8063 English products handbook Rev G
Contents
1. 5 4 Nite ub latins 170 i 3 00 4 80 0 1890 1 60 2 80 250 2 60 ARRA 1 2 ns 5 L 4 00 0 1574 6 20 0 2441 3 80 0 1497 1 4 5 80 0 2284 0 95 BSC Y 1 90 O 5 gt lt 1 27 0 0500 0 50 0 0196 5 130 BSC 1 75 0 0688 0 25 0 0099 145 0 25 0 0098 1 35 0 0532 445MAX 020 0 10 0 0040 vy 0 95 08 MIN COPLANARITY 0 51 0 0201 l ke Y Qo MIN 1 la 0 51 0 0201 x 1 27 0 0500 0 55 0 10 0 31 0 0122 0 25 0 0098 4 01 0 15 10 SEATING 369 2220 0 40 0 0157 0 15 E M 10 lel L045 PLANE 0 17 0 0067 0 05 MIN SEATING 0 20 045 0 50 PLANE BSC 0 35 0 35 MIN 9 COMPLIANT TO JEDEC STANDARDS MS 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 121608 A 012407 A COMPLIANT TO JEDEC STANDARDS MO 178 AA Figure 58 5 Lead Small Outline Transistor Package SOT 23 Figure 59 8 Lead Standard Small Outline Package SOIC_N RJ 5 Narrow Body R 8 Dimensions shown in millimeters Dimensions shown in millimeters and inches 3 20 3 00 2 80 170 3 00 1 60 2 802. 150 60 1 50 545 INDICATOR E 280 4 65 0 95 BSC a 1 90 1 BSC IDENTIFIER 1 30 115 090 4 1 45 0 20 0 95 15 095 0 08 MIN 0 85 1 10 r 075 Fy 015 7 Li 0 80 0 05 MIN N L SEATING 0 15 0 23 055 0 50 MAX PLANE 0 05 lt 0 40 0 0 09 0 40 0 30 COPLANARITY 0 25 0 10 COMPLIANT TO JEDEC STANDARDS 178 COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 60 6 Lead Small Outline Transistor Package SOT 23 Figure 61 8 Lead Mini Small Outline Package MSOP RJ 6 RM 8 Dimensions shown in millimeters Dimensions shown in millimeters Rev Page 19 of 20 AD8061 AD8062 AD8063 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8061AR 40 C to 85 8 Lead SOIC R 8 AD8061AR REEL 40 to 85 C 8 Lead SOIC N 13 Inch Tape and Reel R 8 AD8061AR REEL7 40 C to 85 C 8 Lead SOIC_N 7 Inch Tape and Reel R 8 AD8061ARZ 40 C to 85 C 8 Lead SOIC_N R 8 AD8061ARZ REEL 40 C to 85 C 8 Lead SOIC_N 13 Inch Tape and Reel R 8 AD8061ARZ REEL7 40 C to 85 C 8 Lead SOIC_N 7 Inch Tape and Reel R 8 AD8061ART R2 40 C to 85 C 5 Lead SOT 23 250 Piece Tape and Reel RJ 5 HGA AD8061ART REEL 40 C to 85 C 5 Lead SOT 23 13 Inch Tape and Reel RJ 5 HGA AD8061ART REEL7 40 C to 85 C 5 Lead SOT 23 7 Inch Tape and
3. 1999 2010 Analog Devices Inc All rights reserved AD8061 AD8062 AD8063 TABLE OF CONTENTS Features sm amy a hap qaa 1 Applicati ns a RR RERO 1 Connection Diagrams sse 1 General Description earn eta tiene E aya aya 1 REVISION HISEOEY Deseos esce e tod ceed E EE 2 sereni RD Ue E e 3 Absolute Maximum Ratings seen 6 Maximum Power Dissipation sss 6 5 cete toe aya as des 6 Typical Performance Characteristics sse 7 Circuit Descriptio aasawa ayasa kasaae qana 14 REVISION HISTORY 2 10 Rev F to Rev G Changes to Table 4 a erepti NERES 6 11 09 Rev E to Rev F Changed Input Common Mode Voltage Range Parameter 4 Updated Outline Dimensions sse 19 10 07 Rev D to Rev E Changes to Applications seen 1 Updated Outline Dimensions 19 12 05 Rev C to Rev D Updated au a hebetes Universal Change to Features and General 1 Updated Outline Dimensions seen 19 Changes to Ordering Guide eee 20 5 01 Rev B to Rev C Replaced TPC 9 with new graph sse 7 11 00 Rev A to Rev B 2 00 Rev 0 to Rev A 11 99 Revision 0 Initial Version Headroom Considerations eee 14 Overload Behavior
4. 85 C 6 Lead SOT 23 250 Piece Tape and Reel RJ 6 HHA AD8063ART REEL 409 to 85 6 Lead SOT 23 13 Inch Tape and Reel RJ 6 HHA AD8063ART REEL7 409 to 85 C 6 Lead SOT 23 7 Inch Tape and Reel RJ 6 HHA AD8063ARTZ R2 409 to 85 6 Lead SOT 23 250 Piece Tape and Reel RJ 6 HOE AD8063ARTZ REEL 409 to 85 C 6 Lead SOT 23 13 Inch Tape and Reel RJ 6 HOE AD8063ARTZ REEL7 409 to 85 C 6 Lead SOT 23 7 Inch Tape and Reel RJ 6 HOE 12 RoHS Compliant Part denotes RoHS product may be top or bottom marked New branding after data code 0542 previously branded HGA 3 New branding after data code 0542 previously branded HHA 1999 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D01065 0 2 10 G Huc Rev G Page 20 of 20
5. and the AD8062 dual amplifies the three video channels of an RGB system Figure 55 shows a circuit that performs this function Rev G Page 17 of 20 AD8061 AD8062 AD8063 MULTIPLEXER The select signal and the output waveforms for this circuit are The AD8063 has a disable pin used to power down the ampli fier to save power or to create a mux circuit If two or more AD8063 outputs are connected together and only one is enabled then only the signal of the enabled amplifier will appear at the output This configuration is used to select from various input signal sources Additionally the same input signal is applied to OUTPUT different gain stages or differently tuned filters to make a gain step amplifier or a selectable frequency amplifier Figure 56 shows a schematic of two AD8063 devices used to create a mux that selects between two inputs One of these is a 1 V p p 3 MHz sine wave the other is a 2 V p p 1 MHz sine wave SELECT 4V 01065 056 SELECT Figure 56 Two to One Multiplexer Using Two AD8063s Rev G Page 18 of 20 Figure 57 AD8063 Mux Output shown in Figure 57 For synchronization clarity two different frequency synthesizers whose time bases are locked to each other generate the signals 01065 057 AD8061 AD8062 AD8063 OUTLINE DIMENSIONS 5 00 0 1968
6. 04 amp 2 o 03 0 2 0 1 9 0 5 5 0 0 1 0 2 0 3 0 4 0 5 1 0 15 2 0 2 5 3 0 TIME us OUTPUT STEP AMPLITUDE V Figure 21 400 mV Pulse Response Figure 24 Slew Rate vs Output Step Amplitude Rev G Page 9 of 20 AD8061 AD8062 AD8063 1400 Vs 2 5V G 1 FALLING EDGE 1200 Ve 4 RL 1 s 2 5V 1000 FALLING EDGE Vg 5V 2 800 o Vour n 5 gt 600 SING EDGE 5 L Vg 4V ov o 400 RISING Vs 200 8 500mV DIV p 05 10 15 20 25 30 35 P 0 20 40 60 80 100 120 140 160 180 200 OUTPUT STEP V TIME ns Figure 25 Slew Rate vs Output Step Amplitude G 2 1 Vs 5 V Figure 28 Input Overload Recovery Input Step 0 V to 2 V 1k Vs 5V RL 1kQ E 2 5 100 o a 5 2 gt 1 0V 10 gt ov mV DIV 3 1 5 5 10 100 1k 10k 100k 1M 10M 0 20
7. Reel RJ 5 HGA AD8061ARTZ R2 40 C to 85 C 5 Lead SOT 23 250 Piece Tape and Reel RJ 5 HOD AD8061ARTZ REEL 40 C to 85 5 Lead SOT 23 13 Inch Tape and Reel RJ 5 HOD AD8061ARTZ REEL7 40 C to 85 C 5 Lead SOT 23 7 Inch Tape and Reel RJ 5 HOD AD8062AR 40 C to 85 C 8 Lead SOIC N R 8 AD8062AR REEL 40 to 85 C 8 Lead SOIC N 13 Inch Tape and Reel R 8 AD8062AR REEL7 40 C to 85 8 Lead SOIC N 7 Inch Tape and Reel R 8 AD8062ARZ 40 C to 85 8 Lead SOIC R 8 AD8062ARZ RL 40 C to 85 C 8 Lead SOIC_N 13 Inch Tape and Reel R 8 AD8062ARZ R7 40 C to 85 C 8 Lead SOIC_N 7 Inch Tape and Reel R 8 AD8062ARM 40 C to 85 C 8 Lead MSOP RM 8 HCA AD8062ARM REEL 40 C to 85 C 8 Lead MSOP 13 Inch Tape and Reel RM 8 HCA AD8062ARM REEL7 409 to 85 C 8 Lead MSOP 7 Inch Tape and Reel RM 8 HCA AD8062ARMZ 40 C to 85 C 8 Lead MSOP RM 8 AD8062ARMZ RL 40 C to 85 C 8 Lead MSOP 13 Inch Tape and Reel RM 8 HCA AD8062ARMZ R7 40 C to 85 C 8 Lead MSOP 7 Inch Tape and Reel RM 8 AD8063AR 40 C to 85 8 Lead SOIC N R 8 AD8063AR REEL 409 to 85 C 8 Lead SOIC N 13 Inch Tape and Reel R 8 AD8063AR REEL7 409 to 85 C 8 Lead SOIC N 7 Inch Tape and Reel R 8 AD8063ARZ 40 C to 85 C 8 Lead SOIC_N R 8 AD8063ARZ REEL 40 C to 85 C 8 Lead SOIC_N 13 Inch Tape and Reel R 8 AD8063ARZ REEL7 40 C to 85 C 8 Lead SOIC_N 7 Inch Tape and Reel R 8 AD8063ART R2 409 to
8. Signal Response Rr 0 50 Figure 12 Small Signal Frequency Response Rev G Page 7 of 20 AD8061 AD8062 AD8063 0 5V 10 R 1kO G 1 20 a 8 Z 730 2ND 1MHz lt 40 50 3RD 10MHz 0 a 5 2 z 80 2 90 2 106 2ND 10MHz 3RD 1MHz 8 0 5 1 0 1 5 2 0 2 5 3 0 3 5 FREQUENCY MHz INPUT SIGNAL DC BIAS V Figure 13 Large Signal Frequency Response Figure 16 Harmonic Distortion for a 1 V p p Signal vs Input Signal DC Bias 0 1 40 Vs 27V 02V RL 1kO 0 1V 50 1 a 60 Q INPUT 5 04 z Vs 5V 5 70 0 2 N PU s 80 z 5 2NDH E 0 3 90 04 100 R 3RD H 0 5 5 410 5 1 10 100 1 0 01 0 1 1 10 50 FREQUENCY MHz FREQUENCY MHz START 10kHz STOP 30MHz Figure 14 0 1 dB Flatness Figure 17 Harmonic Distortion for a 1 V p p Output Signal vs Input Signal DC Bias 80 200 150 60 SERIES 1 100 T 50 5 40 gt m z SERIES 2 A 5 5 g z o n 20 50 E 9 a 7 E 100 2 2 a a 0 150 5 200 20 250 s 40 300 5 3 0 01 0 1 1 10 100 1k FREQUENCY MHz OUTPUT SIGNAL DC BIA
9. V 1k Vs 5V Vo 0 2V RL 1kQ 100 Veias 1V E 10 amp ul u n 1 a z lt 0 1 5 0 01 5 1 10 100 1 0 1 1 10 100 1 FREQUENCY MHz FREQUENCY MHz Figure 33 AD8063 Disabled Output Isolation Frequency Response Figure 36 Output Impedance vs Frequency Vour 0 2 1 5 V Rev G Page 11 of 20 AD8061 AD8062 AD8063 1 SETTLING TIME TO 0 SETTLING TIME ns 0 1 0 1 20ns DIV Figure 37 Output Settling Time to 0 196 01065 037 01065 038 2 5 OUTPUT VOLTAGE STEP Figure 38 Settling Time vs Vour Figure 39 Output Swing 01065 039 Rev G Page 12 of 20 TIME ns Figure 40 1 V Step Response TIME ns Figure 41 100 mV Step Response VOLTS 2us DIV Figure 42 Output Rail to Rail Swing 01065 040 01065 041 01065 042 AD8061 AD8062 AD8063 2 6V 4 5V P d 25V a 2 5V gt s 2 4 0 5V E i 1VIDIV 0 5 10 15 20 25 30 35 40 45 50 50 TIME ns Figure 43 200 mV Step Response Figure 44 2 V Step Response Rev G Page 13 of 20 AD8061 AD8062 AD8063 CIRCUIT DESCRIPTION The AD8061 AD8062 AD8063
10. the whole waveform is positive and the black level is not at ground but at a positive voltage The circuit can be modified to provide the sync stripping function for such a waveform Instead of connecting Re to ground connect it to a dc voltage that is two times the black level of the input signal The gain from the noninverting input to the output is 2 which means the black level is amplified by 2 to the output However the gain through Ra is 1 to the output It takes a dc level of twice the input black level to shift the black level to ground at the output When this occurs the sync is stripped and the active video is passed as in the ground referenced case MONITOR 1 MONITOR 2 01065 055 Figure 55 RGB Cable Driver Using AD8061 AD8062 RGB AMPLIFIER Most RGB graphics signals are created by video DAC outputs that drive a current through a resistor to ground At the video black level the current goes to zero and the voltage of the video is also zero Before the availability of high speed rail to rail op amps it was essential that an amplifier have a negative supply to amplify such a signal Such an amplifier is necessary if one wants to drive a second monitor from the same DAC outputs However high speed rail to rail output amplifiers like the AD8061 and AD8062 accept ground level input signals and output ground level signals They are used as RGB signal amplifiers A combination of the AD8061 single
11. 40 60 80 100 120 140 160 180 200 FREQUENCY Hz TIME ns Figure 26 Voltage Noise vs Frequency Figure 29 Output Overload Recovery Input Step 0 Vto 1 V lt a S 9 x 3 z i x x 2 o 10M FREQUENCY Hz FREQUENCY MHz Figure 27 Current Noise vs Frequency Figure 30 CMRR vs Frequency Rev G Page 10 of 20 AD8061 AD8062 AD8063 AVs 7 0 2V p p lt t 2 z i 0 10 15 20 25 30 35 40 45 50 FREQUENCY MHz DISABLE VOLTAGE Figure 31 PSRR vs Frequency Delta Figure 34 AD8063 DISABLE Voltage vs Supply Current 20 Vs 5V 30 2 8 fin 10MHz Z 40 1 3Vgias F b 50 60 9 o Es 5 70 9 INPUT SIDE 2 INPUT SIDE 1 E gt 80 2 5 HHI 2 EO Vs 5V o Vin 400 rms 100 RL 1 2 8 110 3 120 5 5 001 04 1 10 100 500 FREQUENCY MHz TIME us Figure 32 AD8062 Crosstalk 2 0 V p p 1 G 2 Vs 5V Figure 35 AD8063 DISABLE Function Voltage 0 V to 5
12. ANALOG DEVICES Low Cost 300 MHz Rail to Rail Amplifiers AD8061 AD8062 AD8063 FEATURES Low cost Single AD8061 dual AD8062 Single with disable AD8063 Rail to rail output swing Low offset voltage 6 mV High speed 300 MHz 3 dB bandwidth G 1 650 V ps slew rate 8 5 nV VHz at 5 V 35 ns settling time to 0 196 with 1 V step Operates on 2 7 V to 8 V supplies Input voltage range 0 2 V to 3 2 V with Vs 5 V Excellent video specifications R 150 O G 2 Gain flatness 0 1 dB to 30 MHz 0 0196 differential gain error 0 04 differential phase error 35 ns overload recovery Low power 6 8 mA amplifier typical supply current AD8063 400 pA when disabled APPLICATIONS Imaging Photodiode preamps Professional video and cameras Handsets DVDs CDs Base stations Filters ADC drivers Clock buffers GENERAL DESCRIPTION The AD8061 AD8062 AD8063 are rail to rail output voltage feedback amplifiers offering ease of use and low cost They have a bandwidth and slew rate typically found in current feedback amplifiers All have a wide input common mode voltage range and output voltage swing making them easy to use on single supplies as low as 2 7 V Despite being low cost the AD8061 AD8062 AD8063 provide excellent overall performance For video applications their differential gain and phase errors are 0 0196 and 0 04 into a Rev Information fumished by Analog Devices is believed to be accurate and reliable
13. D 5V 01065 048 0 100 200 300 400 500 600 TIME ns Figure 48 Pulse Response for G 1 Follower Input Step Overloading the Input Stage Output Output overload recovery is typically within 40 ns after the amplifiers input is brought to a nonoverloading value Figure 49 shows output recovery transients for the amplifier recovering from a saturated output from the top and bottom supplies to a point at midsupply 5 0 4 6 42 OUTPUT VOLTAG 5V TO 2 5V 3 8 34 OUTPUT VOLTAGE 3 0 2 6 2 2 1 8 1 4 1 0 INPUT AND OUTPUT VOLTAGE V 0 6 0 2 0 2 01065 049 0 TIME ns Figure 49 Overload Recovery G 1 V 5V Rev G Page 15 of 20 AD8061 AD8062 AD8063 CAPACITIVE LOAD DRIVE The AD8061 AD8062 AD8063 family is optimized for bandwidth and speed not for driving capacitive loads Output capacitance creates a pole in the amplifier s feedback path leading to excessive peaking and potential oscillation If dealing with load capacitance is a requirement of the application the two strategies to consider are as follows Use a small resistor in series with the amplifier s output and the load capacitance Reduce the bandwidth of the amplifier s feedback loop by increasing the overall noise gain Figure 50 shows a unity gain follower using the series resistor strategy The resistor isolates t
14. However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners CONNECTION DIAGRAMS 08061 PSU 8 54 1 AD8063 IN1 2 Vour2 01065 001 Not to Scale Figure 2 8 Lead SOIC R MSOP RM 01065 003 NC NO CONNECT Figure 1 8 Lead SOIC R AD8061 5 Vs Not to Scale Figure 4 5 Lead SOT 23 RJ 01065 004 01065 002 NORMALIZED GAIN dB 01065 005 FREQUENCY MHz Figure 5 Small Signal Response Rr 00 500 150 Q load along with 0 1 dB flatness out to 30 MHz Addi tionally they offer wide bandwidth to 300 MHz along with 650 V us slew rate The AD8061 AD8062 AD8063 offer a typical low power of 6 8 mA amplifier while being capable of delivering up to 50 mA of load current The AD8063 has a power down disable feature that reduces the supply current to 400 uA These features make the AD8063 ideal for portable and battery powered applications where size and power are critical One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113
15. ISABLE is toggled from 0 V to 5 V illustrating the part s turn on and turn off time Figure 33 shows the input output isolation response with the AD8063 shut off BOARD LAYOUT CONSIDERATIONS Maintaining the high speed performance of the AD8061 AD8062 AD8063 family requires the use of high speed board layout techniques and low parasitic components The PCB should have a ground plane covering unused portions of the component side of the board to provide a low impedance path Remove the ground plane near the package to reduce parasitic capacitance Proper bypassing is critical Use a ceramic 0 1 uF chip capacitor to bypass both supplies Locate the chip capacitor within 3 mm of each power pin Additionally connect in parallel a 4 7 uF to 10 tantalum electrolytic capacitor to provide charge for fast large signal changes at the output Minimizing parasitic capacitance at the amplifier inverting input pin is very important Locate the feedback resistor close to the inverting input pin The value of the feedback resistor may come into play for instance 1 interacting with 1 pF of parasitic capacitance creates a pole at 159 MHz Use stripline design techniques for signal traces longer than 25 mm Design them with either 50 or 75 characteristic impedance and proper termination at each end Rev G Page 16 of 20 AD8061 AD8062 AD8063 APPLICATIONS INFORMATION SINGLE SUPPLY SYNC STRIPPER When a video signal contain
16. S V Figure 15 AD8062 Open Loop Gain and Phase vs Frequency Figure 18 Harmonic Distortion vs Output Signal DC Bias Vs 5V R 1kQ Rev G Page 8 of 20 AD8061 AD8062 AD8063 z a ES z o 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH o a o 5 H cope UR eedem cT m a 5 lt 5 8 1 0 1 5 2 0 2 5 3 0 3 5 40 4 5 ui 8 RTO OUTPUT V p 8 V 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 4178 5 Figure 19 Harmonic Distortion vs Output Signal Amplitude Figure 22 Differential Gain and Phase Error G 2 NTSC Input Signal R 1 5 5 V z lt E a S1 HARMONIC x 5 DUAL 2 5V SUPPLY m z o S1 2ND HARMONIC a DUAL 2 5V SUPPLY 1ST 2 0 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH S1 2ND HARMONIC ul E 5V SUPPLY E a g d r 51 3RD HARMONIC SINGLE 5V SUPPLY ui 2 5 0 01 0 1 10 48 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 2 FREQUENCY MHz START 10kHz STOP 30MHz Figure 20 Harmonic Distortion vs Frequency Figure 23 Differential Gain and Phase Error G 2 NTSC Input Signal R 150 Vs 5 V 1 0 Vs 5V 0 9 RL 1kQ 1 0 8 5 o 9 06 os 5 gt
17. Vo 1Vp p 250 MHz Bandwidth for 0 1 dB Flatness G 1 Vo 0 2 Vp p 30 MHz Slew Rate G 1 Vo 1 V step R 2 190 280 V us G 2 Vo 1 5 V step R 2 180 230 V us Settling Time to 0 1 2 Vo 1 V step 40 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vo 2 V p p R 1 60 dBc fc 20 MHz Vo 2 V p p R 1 44 dBc Crosstalk Output to Output 5 MHz G 2 90 Input Voltage Noise f 100 kHz 8 5 nV VHz Input Current Noise 100 kHz 1 2 pA VHz DC PERFORMANCE Input Offset Voltage 1 6 mV Tmn to Tmax 2 6 mV Input Offset Voltage Drift 3 5 uV C Input Bias Current 3 5 8 5 uA Tmn to Tmax 4 8 5 uA Input Offset Current 0 3 4 5 pA Open Loop Gain Vo 0 5 V to 2 5 V 1500 66 70 dB Vo 0 5 V to 2 5 V R 2 74 90 dB INPUT CHARACTERISTICS Input Resistance 13 Input Capacitance 1 pF Input Common Mode Voltage Range 0 2 to 1 2 V Common Mode Rejection Ratio 0 2V to 1 2 V 80 dB OUTPUT CHARACTERISTICS Output Voltage Swing Load Resistance Is Terminated at Midsupply R 150 O 0 3 0 1 to 2 87 285 V R 2kQ 0 3 0 1 to 2 9 2 90 V Output Current Vo 0 5 V to 2 5 V 25 mA Capacitive Load Drive 0 8 V 30 overshoot G 1 Rs 0 0 25 pF G 2 Rs 47 Q 300 pF POWER DOWN DISABLE Turn On Time 40 ns Turn Off Time 300 ns DISABLE Voltage Off 0 8 V DISABLE Voltage On 12 V POWER SUPPLY Operating Range 2 7 3 V Quiescent Current per Amplifier 6 8 9 mA Supply Current when Di
18. and Recovery sss 15 Capacitive Load Drive asnosi issi e 16 Disable Op ration Je ep e 16 Board Layout Considerations eee 16 Applications Information eee tentent 17 Single Supply Sync Stripper sss 17 RGB Amphlifietx asd eee ete 17 Multiplexer ettet ER MI 18 Outline Dimensions tette tentent ente 19 Orderime Guides 20 Rev G Page 2 of 20 AD8061 AD8062 AD8063 SPECIFICATIONS Ta 25 Vs 5 V 1 Vo 1 V unless otherwise noted Table 1 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Gz1 Voz0 2V p p 150 320 MHz G 1 2 Vo 0 2 V p p 60 115 MHz 3 dB Large Signal Bandwidth G 1 Vo 1Vp p 280 MHz Bandwidth for 0 1 dB Flatness G 1 Vo 0 2 Vp p 30 MHz Slew Rate Gz1 Voz2Vstep R 2 500 650 V us G 2 Vo 2 V step R 2 300 500 V us Settling Time to 0 196 2 2 V step 35 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vo 2 V p p R 1 77 dBc fc 20 MHz Vo 2 V p p R 1 50 dBc Crosstalk Output to Output f 5 MHz G 2 AD8062 90 dBc Input Voltage Noise f 100 kHz 8 5 nV VHz Input Current Noise 100 kHz 1 2 pA VHz Differential Gain Error NTSC G 2 RL 1500 0 01 Differential Phase Error NTSC 2 1500 0 04 Degrees Third Order In
19. family is comprised of high speed voltage feedback op amps The high slew rate input stage is a true single supply topology capable of sensing signals at or below the minus supply rail The rail to rail output stage can pull within 30 mV of either supply rail when driving light loads and within 0 3 V when driving 150 High speed perform ance is maintained at supply voltages as low as 2 7 V HEADROOM CONSIDERATIONS These amplifiers are designed for use in low voltage systems To obtain optimum performance it is useful to understand the behavior of the amplifier as input and output signals approach the amplifiers headroom limits The AD8061 AD8062 AD8063 input common mode voltage range extends from the negative supply voltage actually 200 mV below this or ground for single supply operation to within 1 8 V of the positive supply voltage Thus at a gain of 2 the AD8061 AD8062 AD8063 can provide full rail to rail output swing for supply voltage as low as 3 6 V assuming the input signal swings from Vs or ground to Vs 2 At a gain of 3 the AD8061 AD8062 AD8063 can provide a rail to rail output range down to 2 7 V total supply voltage Exceeding the headroom limit is not a concern for any inverting gain on any supply voltage as long as the reference voltage at the amplifiers positive input lies within the amplifiers input common mode range The input stage is the headroom limit for signals when the amplifier is used in a gain
20. gure 46 Unity Gain Follower Bandwidth vs Input Common Mode Vs 5 V Higher frequency signals require more headroom than lower frequencies to maintain distortion performance Figure 47 illustrates how the rising edge settling time for the amplifier configured as a unity gain follower stretches out as the top of a 1 V step input approaches and exceeds the specified input common mode voltage limit For signals approaching the minus supply and inverting gain and high positive gain configurations the headroom limit is the output stage The AD8061 AD8062 AD8063 amplifiers use a common emitter style output stage This output stage maximizes the available output range limited by the saturation voltage of the output transistors The saturation voltage increases with the drive current the output transistor is required to supply due to the output transistors collector resistance The saturation voltage is estimated using the equation Vsar2 25 mV lox 8 where Iois the output current 8 is a typical value for the output transistors collector resistance Rev G Page 14 of 20 2 3V TO 3 3V STEP OUTPUT VOLTAGE V 2 4V TO 3 4V STEP 01065 047 0 4 8 42 16 20 24 28 3 TIME ns Figure 47 Output Rising Edge for 1 V Step at Input Headroom Limits G 1 Vs 5 V 0 V As the saturation point of the output stage is approached the output signal
21. he output from the capacitance and more importantly creates a zero in the feedback path that compensates for the pole created by the output capacitance 01065 050 Figure 50 Series Resistor Isolating Capacitive Load Voltage feedback amplifiers like those in the AD8061 AD8062 AD8063 family are able to drive more capacitive load without excessive peaking when used in higher gain configurations because the increased noise gain reduces the bandwidth of the overall feedback loop Figure 51 plots the capacitance that produces 3096 overshoot vs noise gain for a typical amplifier 10k Rg 4 7 Rs 0 e CAPACITIVE LOAD pF 01065 051 1 2 3 4 5 CLOSED LOOP GAIN Figure 51 Capacitive Load vs Closed Loop Gain DISABLE OPERATION The internal circuit for the AD8063 disable function is shown in Figure 52 When the DISABLE node is pulled below 2 V from the positive supply the supply current decreases from typically 6 5 mA to under 400 uA and the AD8063 output enters a high impedance state If the DISABLE node is not connected and allowed to float the AD8063 stays biased at full power vcc 2 TO AMPLIFIER BIAS DISABLE gt 01065 052 Figure 52 Disable Circuit of the AD8063 Figure 34 shows the AD8063 supply current vs DISABLE voltage Figure 35 plots the output seen when the AD8063 input is driven with a 10 MHz sine wave and D
22. of 1 for signals approaching the positive rail Figure 45 shows a typical offset voltage vs input common mode voltage for the AD8061 AD8062 AD8063 amplifier on a 5 V supply Accurate dc performance is main tained from approximately 200 mV below the minus supply to within 1 8 V of the positive supply For high speed signals however there are other considerations Figure 46 shows 3 dB bandwidth vs dc input voltage for a unity gain follower As the common mode voltage approaches the positive supply the amplifier holds together well but the bandwidth begins to drop at 1 9 V within Vs This manifests itself in increased distortion or settling time Figure 16 plots the distortion of a 1 V p p signal with the AD8061 AD8062 AD8063 amplifier used as a follower on a 5 V supply vs signal common mode voltage Distortion performance is maintained until the input signal center voltage gets beyond 2 5 V as the peak of the input sine wave begins to run into the upper common mode voltage limit 0 4 0 8 1 2 1 6 S 20 gt 24 2 8 3 2 3 6 3 4 0 5 05 0 05 10 15 20 25 30 35 40 Figure 45 Vos vs Common Mode Voltage Vs 5 V 2 0 I TH Vom 3 0 Vem 3 1 PES Vom 3 2 5 WA Vem 3 3 z Vom 3 4 lt 9 4 6 3 8 5 0 1 1 10 100 1 10 FREQUENCY MHz Fi
23. ply R 21500 0 3 0 1 to 2 55 255 V 2 0 25 0 1 to 2 6 2 6 V Output Current Vo 0 5 V to 2 2 V 25 mA Capacitive Load Drive Vour 0 8 V 30 overshoot G 1 Rs 0 Q 25 pF G 2 Rs 47 Q 300 pF POWER DOWN DISABLE Turn On Time 40 ns Turn Off Time 300 ns DISABLE voltage Off 0 5 V DISABLE voltage On 0 9 V POWER SUPPLY Operating Range 2 7 8 V Quiescent Current per Amplifier 6 8 8 5 mA Supply Current when Disabled AD8063 Only 0 4 mA Power Supply Rejection Ratio 80 dB Rev G Page 5 of 20 AD8061 AD8062 AD8063 ABSOLUTE MAXIMUM RATINGS Table 4 Parameter Rating Supply Voltage 8V Internal Power Dissipation 8 lead SOIC R 0 8W 5 lead SOT 23 RJ 0 5 6 lead SOT 23 RJ 0 5W 8 lead MSOP RM 0 6W Input Voltage Common Mode Differential Input Voltage Output Short Circuit Duration Storage Temperature Range R 8 RM 8 SOT 23 5 SOT 23 6 Operating Temperature Range Lead Temperature Soldering 10 sec 0 2 V to 4 Vs 0 2 V Vs Observe power derating curves 65 C to 125 C 40 C to 85 C 300 C 1 Specification is for device in free air 8 Lead SOIC_N 160 C W 56 C W 5 Lead SOT 23 04 240 C W 0x 92 C W 6 Lead SOT 23 04 230 C W 0x 92 C W 8 Lead MSOP 200 C W 0 44 C W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional opera
24. s synchronization pulses it is sometimes desirable to remove them prior to performing certain operations In the case of analog to digital conversion the sync pulses consume some of the dynamic range so removing them increases the converter s available dynamic range for the video information Figure 53 shows a basic circuit for creating a sync stripper using the AD8061 powered by a single supply When the negative supply is at ground potential the lowest potential to which the output can go is ground This feature is exploited to create a waveform whose lowest amplitude is the black level of the video and does not include the sync level RG PIN NUMBERS ARE 1 FOR 8 LEAD PACKAGE 01065 053 Figure 53 Single 3 V Sync Stripper Using AD8061 In this case the input video signal has its black level at ground so it comes out at ground at the input Because the sync level is below the black level it does not show up at the output However all of the active video portion of the waveform is amplified by a gain of 2 and then normalized to unity gain by the back terminated transmission line Figure 54 is an oscilloscope plot of the input and output waveforms INPUT 01065 054 Figure 54 Input and Output Waveforms for a Single Supply Video Sync Stripper Using an AD8061 Some video signals with sync are derived from single supply devices such as video DACs These signals can contain sync but
25. sabled AD8063 Only 0 4 mA Power Supply Rejection Ratio 72 80 dB Rev G Page 4 of 20 Ta 25 C Vs 2 7 V R 1 Vo 1 V unless otherwise noted AD8061 AD8062 AD8063 Table 3 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth G 1 Vo 0 2 V p p 150 300 MHz G 1 2 Vo 0 2 V p p 60 115 MHz G 1 Vo 1Vp p 230 MHz Bandwidth for 0 1 dB Flatness G 1 Vo 0 2V p p Vo dc 1 V 30 MHz Slew Rate 1 0 7 V step R 2 110 150 V us 2 Vo 1 5 V step R 2 95 130 V us Settling Time to 0 196 G 2 Vo 1 V step 40 ns NOISE DISTORTION PERFORMANCE Total Harmonic Distortion fc 5 MHz Vo 2 V p p R 1 60 dBc fc 20 MHz Vo 2V p p R 1 44 dBc Crosstalk Output to Output f 5 MHz G 2 90 Input Voltage Noise 100 kHz 8 5 nV VHz Input Current Noise f 100 kHz 1 2 pA VHz DC PERFORMANCE Input Offset Voltage 1 6 Tmn to Tmax 2 6 mV Input Offset Voltage Drift 3 5 uV C Input Bias Current 3 5 HA Tuis to Tmax 4 8 5 uA Input Offset Current 0 3 45 pA Open Loop Gain Vo 0 5 V to 2 2 V 1500 63 70 dB Vo 0 5 V to 2 2 V R 2 74 90 dB INPUT CHARACTERISTICS Input Resistance 13 MQ Input Capacitance 1 pF Input Common Mode Voltage Range 0 2 to 0 9 V Common Mode Rejection Ratio 0 2 V to 40 9 V 0 8 dB OUTPUT CHARACTERISTICS Output Voltage Swing Load Resistance Is Terminated at Midsup
26. shows increasing amounts of compression and clipping in the input headroom case the higher frequency signals require a bit more headroom than lower frequency signals Figure 16 Figure 17 and Figure 18 illustrate this point plotting typical distortion vs output amplitude and bias for gains of 2 and 5 OVERLOAD BEHAVIOR AND RECOVERY Input specified input common mode voltage of the AD8061 AD8062 AD8063 is 200 mV below the negative supply to within 1 8 V of the positive supply Exceeding the top limit results in lower bandwidth and increased settling time as seen in Figure 46 and Figure 47 Pushing the input voltage of a unity gain follower beyond 1 6 V within the positive supply leads to the behavior shown in Figure 48 an increasing amount of output error and much increased settling time Recovery time from input voltages 1 6 V or closer to the positive supply is approximately 35 ns which is limited by the settling artifacts caused by transistors in the input stage coming out of saturation The AD8061 AD8062 AD8063 family does not exhibit phase reversal even for input voltages beyond the voltage supply rails Going more than 0 6 V beyond the power supplies turns on protection diodes at the input stage which greatly increases the current draw of the device AD8061 AD8062 AD8063 VOLTAGE STEP FROM 2 4V TO 3 6V OUTPUT VOLTAGE V VOLTAGE STEP FROM 2 4V TO 3 8V 4V AN
27. tercept 10 2 28 dBc SFDR 5 MHz 62 DC PERFORMANCE Input Offset Voltage 1 6 mV tO Tmax 2 6 Input Offset Voltage Drift 3 5 Input Bias Current 3 5 9 Tmn to Tmax 4 9 uA Input Offset Current 0 3 45 pA Open Loop Gain Vo 0 5 V to 4 5 1500 68 70 dB Vo 0 5 V to 4 5 V R 2 74 90 dB INPUT CHARACTERISTICS Input Resistance 13 MQ Input Capacitance 1 pF Input Common Mode Voltage Range 0 2 to V 132 Common Mode Rejection Ratio 0 2 V to 43 2 V 62 80 dB OUTPUT CHARACTERISTICS Output Voltage Swing Load Resistance Is Terminated at Midsupply R 21500 0 3 0 1 to 4 5 4 75 V R 2kQ 025 0 1 to 4 9 485 V Output Current Vo 0 5V to 4 5 V 25 50 mA Capacitive Load Drive 0 8 V 30 overshoot G 1 Rs 0 Q 25 pF G 2 Rs 47 Q 300 pF POWER DOWN DISABLE Turn On Time 40 ns Turn Off Time 300 ns DISABLE Voltage Off 2 8 V DISABLE Voltage On 3 2 V POWER SUPPLY Operating Range 2 7 5 8 V Quiescent Current per Amplifier 6 8 9 5 mA Supply Current when Disabled AD8063 Only 0 4 mA Power Supply Rejection Ratio AVs 2 7Vto 5 V 72 80 dB Rev G Page 3 of 20 AD8061 AD8062 AD8063 Ta 25 C Vs 3 V R 1 Vo 1 V unless otherwise noted Table 2 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Small Signal Bandwidth Gz1 Voz0 2V p p 150 300 MHz G 1 2 Vo 0 2 V p p 60 115 MHz 3 dB Large Signal Bandwidth G 1
28. tion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8061 AD8062 AD8063 is limited by the associated rise in junction temperature The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic approximately 150 C Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package Exceeding a junction temperature of 175 C for an extended period can result in device failure While the AD8061 AD8062 AD8063 is internally short circuit protected this may not be sufficient to guarantee that the maximum junction temperature 150 C is not exceeded under all conditions To ensure proper operation it is necessary to observe the maximum power derating curves 2 0 8 LEAD SOIC Ty 150 C z PACKAGE 8 15 o a c 1 0 a 0 5 MSOP SOT 23 5 SOT 23 6 h 0 E 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE Figure 6 Maximum Power Dissipation vs Temperature for AD8061 AD8062 AD8063 ESD CAUTION ESD elec
29. trostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev G Page 6 of 20 AD8061 AD8062 AD8063 NORMALIZED GAIN dB VOLTAGE DIFFERENTIAL FROM Vs Unit 01065 007 01065 010 10 k LOAD CURRENT mA FREQUENCY MHz Figure 7 Output Saturation Voltage vs Load Current Figure 10 Small Signal Frequency Response 18 Vo 1 0V p p AD8062 RI 1kQ 16 G Pt Veias 1V 14 0 a G 2 E 1 P z a lt 3 10 o AD8061 a M G 5 a 6 4 x P n 2 0 s 42 5 2 3 4 5 6 7 8 1 10 100 1k SINGLE POWER SUPPLY V FREQUENCY MHz Figure 8 Isupp y VS VsuPPLY Figure 11 Large Signal Frequency Response 3 5V Vo 0 2V p p o RL 1kO Vo 0 2V p p Vplas 1V 5 5 5 1 z z lt lt 3 G 5 o G 2 N N N N lt i z z E amp 2 g 9 12 5 100 1 10 100 1k FREQUENCY MHz FREQUENCY MHz Figure 9 Small
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