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ANALOG DEVICES AD8065/AD8066 Manual

1. 8 Vo 200mV 6 C 5pF P L C 55pF 4 C 25pF E 5 z z 0 lt 2 4 Vo 200mV p p G 2 e 8 2 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz amp Figure 10 Small Signal Frequency Response for Various See Figure 42 Figure 13 Small Signal Frequency Response for Various Coa See Figure 43 8 A OUT 0 2V 6 G 42 Vout 2V J 4 2 m m 5 Vout 4V 71 kJ z 0 z lt lt 2 4 6 8 z 0 1 1 10 100 100 5 J FREQUENCY MHz 8 FREQUENCY MHz 8 Figure 11 Frequency Response for Various Output Amplitudes Figure 14 Small Signal Frequency Response for Various Rioap See Figure 43 See Figure 43 120 60 Ey P a z o T lt m 5 5 2 a lt ul gt 60 lt n 120 5i 180 2 0 1 1 10 100 1000 5 0 01 0 1 1 10 100 1000 hi FREQUENCY MHz FREQUENCY MHz 8 Figure 12 Small Signal Frequency Response for Various Rg Cr See Figure 43 Figure 15 Open Loop Response Rev J Page 11 of 28 AD8065 AD8066
2. 60 z 70 HD2 1500 2 2 80 HD2 Ry 1kO 5 HD3 1kQ a 90 a HD3 R 1500 100 110 120 2 0 1 1 10 100 0 1 1 10 100 a FREQUENCY MHz amp FREQUENCY MHz Figure 16 Harmonic Distortion vs Frequency for Various Loads Figure 19 Harmonic Distortion vs Frequency for Various Gains See Figure 43 See Figure 42 and Figure 43 30 40rG 2 Vs 412V 50 1MHz 60 s 2 70 HD2 R 1500 o 80 1500 E E Vo 10V p p Q o a 90 HD2 R 3000 a 100 HD3 R 3000 110 120 8 012 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 1 0 10 0 9 OUTPUT AMPLITUDE V amp FREQUENCY MHz 8 Figure 17 Harmonic Distortion vs Amplitude for Various Loads Vs 12 V Figure 20 Harmonic Distortion vs Frequency for Various Amplitudes See Figure 43 See Figure 43 100 m F gt 10 gt E 1 10 100 1k 10k 100k 1M
3. 0 2 0 3 14 12 10 8 6 4 2 0 2 4 6 8 10 12 14 COMMON MODE VOLTAGE V Figure 30 Input Offset Voltage vs Common Mode Voltage i E ad SER popu 40 196 Bi 02916 028 o ri HH 5 i HH E a 10 5 0 lt 3 10 E a 2 245 z 20 lh 25 30 12 10 8 6 4 2 2 4 6 8 10 12 02916 E 029 COMMON MODE VOLTAGE V Figure 32 Input Bias Current vs Common Mode Voltage Range See the Input and Output Overload Behavior Section N 299 SD 0 388 0 069 2 0 1 5 10 0 5 0 0 5 1 0 1 5 2 0 INPUT OFFSET VOLTAGE mV 02916 E 030 Figure 33 Input Offset Voltage Rev J Page 14 of 28 02916 E 031 02916 E 032 02916 E 033 AD8065 AD8066 CMRR dB o OUTPUT IMPEDANCE Q 100 i 0
4. Tmax 2 6 mV Input Offset Voltage Drift 1 17 uV C AD8065WARTZ only Tmn Tmax 17 uV C Input Bias Current SOIC package 1 5 pA Tmn to Tmax 25 125 pA Input Offset Current 1 5 pA Tmn to Tmax 1 125 pA Open Loop Gain Vo 1 V to 4 V AD8065 100 113 dB AD8065WARTZ only Tmn Tmax 100 dB Vo 1 V to 4 V AD8066 90 103 dB INPUT CHARACTERISTICS Common Mode Input Impedance 1000 2 1 GQ pF Differential Input Impedance 1000 4 5 GO pF Input Common Mode Voltage Range FET Input Range Oto 1 7 0102 4 V AD8065WARTZ only Tmn Tmax Oto 1 7 V Common Mode Rejection Ratio 0 5 V to 1 5 V 74 100 dB 1 V to 2 V SOT 23 78 91 dB AD8065WARTZ only 76 dB OUTPUT CHARACTERISTICS Output Voltage Swing R 1 kO 0 1t04 85 0 03 to 4 95 V AD8065WARTZ only Tmn Tmax 0 1 to 4 85 V 21500 0 07 to 4 83 V Output Current Vo 4 V p p SFDR 60 dBc f 500 kHz 35 mA Short Circuit Current 75 mA Capacitive Load Drive 30 overshoot G 1 5 pF Rev J Page 7 of 28 AD8065 AD8066 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range 5 24 V AD8065WARTZ only Tmn Tmax 5 10 V Quiescent Current per Amplifier 5 8 6 4 7 0 mA AD8065WARTZ only Tmn Tmax 7 0 mA Power Supply Rejection Ratio PSRR 78 100 dB AD8065WARTZ only Tmn Tmax 78 dB Rev J Page 8 of 28 AD8065 AD8066 ABSOLUTE MAXIMUM RATINGS Table 4 Parameter Rati
5. 2 Vo 0 2 V p p 50 MHz G 2 Vo 2V p p 40 MHz Bandwidth for 0 1 dB Flatness G 2 Vo 0 2 V p p 7 MHz Input Overdrive Recovery G 1 12 5 V to 12 5 V 175 ns Output Overdrive Recovery G 1 12 5 V to 12 5 V 170 ns Slew Rate G 2 Vo 4 V step 130 180 V us Settling Time to 0 196 G 42 Vo 2Vstep 55 ns G 2 Vo 10 V step 250 ns NOISE HARMONIC PERFORMANCE SFDR fc 1 MHZ G 2 Vo 2 V p p 100 dBc fc 5 MHZ G 2 Vo 2 V p p 67 dBc fc 1 MHZ G 2 Vo 10 V p p 85 dBc Third Order Intercept 10 MHz R 1000 24 dBm Input Voltage Noise f 10 kHz 7 nV VHz Input Current Noise f 10 kHz 1 fA VHz Differential Gain Error NTSC 2 1500 0 04 Differential Phase Error NTSC 2 1500 0 03 Degrees DC PERFORMANCE Input Offset Voltage OV SOIC package 0 4 1 5 mV Input Offset Voltage Drift 1 17 uV C Input Bias Current SOIC package 3 7 pA Tmn to Tmax 25 pA Input Offset Current 2 10 pA Tmn to Tmax 2 pA Open Loop Gain Vo 10V RL 1kO 103 114 dB INPUT CHARACTERISTICS Common Mode Input Impedance 1000 2 1 GO pF Differential Input Impedance 1000 4 5 GO pF Input Common Mode Voltage Range FET Input Range 12 to 8 5 12 0 to 9 5 V Common Mode Rejection Ratio Ven 2 1Vto 1V 85 100 dB 1 V to 1 V SOT 23 82 91 dB OUTPUT CHARACTERISTICS Output Voltage Swing R 1 kO 118to 11 8 11 9 to 11 9 V 3500 11 25 to 11 5 V Output Current
6. 3V 1 100 113 dB AD8065WARTZ only Tmn Tmax 100 dB INPUT CHARACTERISTICS Common Mode Input Impedance 1000 2 1 GO pF Differential Input Impedance 1000 4 5 GO pF Input Common Mode Voltage Range FET Input Range 5 to 1 7 5 0 to 2 4 V AD8065WARTZ only Tmn Tmax 5to 1 7 V Common Mode Rejection Ratio Vem 1 V to 1 V 85 100 dB Vem 1 V to 1 V SOT 23 82 91 dB AD8065WARTZ only Tmn Tmax 82 dB Rev J Page 4 of 28 AD8065 AD8066 Parameter Conditions Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing R 1 kO 4 88 4 90 4 94 to 4 95 V AD8065WARTZ only Tmn Tmax 4 88 to 4 90 V R 21500 4 8 to 4 7 V Output Current Vo 9 V p p SFDR 60 dBc f 500 kHz 35 mA Short Circuit Current 90 mA Capacitive Load Drive 30 overshoot G 1 20 pF POWER SUPPLY Operating Range 5 24 V AD8065WARTZ only Tmn Tmax 5 10 V Quiescent Current per Amplifier 6 4 7 2 mA AD8065WARTZ only Tmn Tmax 7 2 mA Power Supply Rejection Ratio PSRR 85 100 dB AD8065WARTZ only Tmn Tmax 85 dB Rev J Page 5 of 28 AD8065 AD8066 SPECIFICATIONS 12 V Ta 25 C Vs 12 V Rr 1 unless otherwise noted Table 2 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vo 0 2 V p p AD8065 100 145 MHz G 1 Vo 0 2 V p p AD8066 100 115 MHz G
7. to spread the current minimizing parasitic inductances However an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design The length of the current path is directly proportional to the magnitude of parasitic inductances and therefore the high frequency impedance of the path High speed currents in an inductive ground return create unwanted voltage noise The length of the high frequency bypass capacitor leads is most critical A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor Place the ground leads of the bypass capacitors at the same physical location Because load currents flow from the supplies as well the ground for the load impedance should be at the same physical location as the bypass capacitor grounds For the larger value capacitors which are effective at lower frequencies the current return path distance is less critical LEAKAGE CURRENTS Poor PC board layout contaminants and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065 AD8066 Any voltage differential between the inputs and nearby runs sets up leakage currents through the PC board insulator for example 1 V 100 GO 10 pA Similarly any contaminants on the board can create significant leakage skin oils are a common problem To reduce leakage significantly put a guard ring
8. 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 62 8 Lead Standard Small Outline Package SOIC_N 012407 A Narrow Body R 8 Dimensions shown in millimeters and inches 3 00 290 2 80 170 5 4 3 00 tao m 150 60 1 50 q d 3 E 0 95 BSC lt 1 90 BSC 1 30 145 0 90 i n 145MAX 0 20 0 95 MIN 08 MIN 1 puc 0 55 0 15 1 kN 4 dio Ll 045 0 05 SEATING Bo 0 20 hind 005 MIN L 0 50 MAX PLANE BSC 0 35 0 35 MIN 0 8 COMPLIANT TO JEDEC STANDARDS MO 178 AA Figure 63 5 Lead Small Outline Transistor Package SOT 23 RJ 5 Dimensions shown in millimeters 3 20 3 00 2 80 5 15 3 20 4 90 3 00 4 65 2 80 PIN 1 IDENTIFIER Be 0 65 BSC 0 95 15 MAX 0 85 1 10 MAX udi as 0 75 1 Lt 0 80 015 ejl 1 055 0 05 o5 0 09 0 40 COPLANARITY 0 10 100709 B COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 64 8 Lead Mini Small Outline Package MSOP RM 8 Dimensions shown in millimeters Rev J Page 27 of 28 AD8065 AD8066 ORDERING GUIDE Model 2 Temperature Range Package Description Package Option Branding AD8065AR 40 C to 85 C 8 Lead SOIC_N R 8 AD8065AR REEL 40 C to 85 C 8 Lead SOIC
9. Figure 20 The lowest distortion is obtained with the AD8065 used in low gain inverting applications because this eliminates common mode effects Higher closed loop gains result in worse distortion performance INPUT PROTECTION The inputs of the AD8065 AD8066 are protected with back to back diodes between the input terminals as well as ESD diodes to either power supply This results in an input stage with picoamps of input current that can withstand up to 1500 V ESD events human body model with no degradation Excessive power dissipation through the protection devices destroys or degrades the performance of the amplifier Differ ential voltages greater than 0 7 V result in an input current of approximately V V 0 7 V Rr where Rris the resistance series with the inputs For input voltages beyond the positive supply the input current is approximately Vi Vcc 0 7 R Beyond the negative supply the input current is about Vi Ver 0 7 Ri If the inputs of the amplifier are to be subjected to sustained differential voltages greater than 0 7 V or to input voltages beyond the amplifier power supply input current should be limited to 30 mA by an appropriately sized input resistor Ri as shown in Figure 55 V V_ 0 7V R V Vee 0 7V 0 3mA 1 gt goma FOR LARGE V v_i _ R gt AM 0 70 30mA AD8065 o FOR VI BEYOND 4 SUPPLY VOLTAGES Vo Ri 1
10. Figure 55 Current Limiting Resistor 02916 E 055 Rev J Page 21 of 28 AD8065 AD8066 THERMAL CONSIDERATIONS With 24 V power supplies and 6 5 mA quiescent current the AD8065 dissipates 156 mW with no load The AD8066 dissipates 312 mW This can lead to noticeable thermal effects especially in the small SOT 23 5 thermal resistance of 160 C W Vos temperature drift is trimmed to guarantee a maximum drift of 17 uV C so it can change up to 0 425 mV due to warm up effects for an AD8065 AD8066 in a SOT 23 5 package on 24 V Ip increases by a factor of 1 7 for every 10 C rise in temperature I is close to five times higher at 24 V supplies as opposed to a single 5 V supply Heavy loads increase power dissipation and raise the chip junction temperature as described in the Maximum Power Dissipation section Care should be taken not to exceed the rated power dissipation of the package VTHRESHOLD INPUT AND OUTPUT OVERLOAD BEHAVIOR A simplified schematic of the AD8065 AD8066 input stage is shown in Figure 56 This shows the cascoded N channel JFET input pair the ESD and other protection diodes and the auxiliary NPN input stage that eliminates any phase inversion behavior When the common mode input voltage to the amplifier is driven to within approximately 3 V of the positive power supply the input JFET s bias current turns off and the bias of the NPN pair turns on taking over control of the amplifier The NPN differ
11. noise peaking effects which adds to the output noise Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp Table 5 summarizes approximations for the amplifier and feedback and source resistances Noise components for an example preamp with Re 50 Cs 15 pF and Cr 2 pF bandwidth of about 1 6 MHz are also listed Rev J Page 24 of 28 AD8065 AD8066 Table 5 RMS Noise Contributions of Photodiode Preamp Contributor Expression RMS Noise with Rr 50 Cs 15 pF Cr 2 pF Rr x2 2X 4KkTX Rz x f X157 64 5 Amp to f VEN x 2 4 uV Amp f f Cute C 42C 31 uV VEN x lt 5 x a Jf f Amp to past f2 C 4C 2C C 260 uV VEN x 5 DTE x Jf x1 57 Jf 270 uV Total AW Rp 5000 Rp 5000 or AD8066 02916 E 060 Figure 60 High Speed Instrumentation Amplifier HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER Figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065 AD8066 The dc transfer function is 1000 Vour Vy e R G For G 1 it is recommended that the feedback resistors for the two preamps be set to a low value for instance 50 for 50 Q source impedance The bandwidth for G 1
12. of 28 AD8065 AD8066 SPECIFICATIONS 5 V Ta 25 C Vs 5 V Rr 1 unless otherwise noted Table 1 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vo 0 2 V p p AD8065 100 145 MHz AD8065WARTZ only Tmn Tmax 88 MHz G 1 Vo 0 2 V p p AD8066 100 120 MHz G 2 Vo 02V p p 50 MHz G 2 Vo 2Vp p 42 MHz Bandwidth for 0 1 dB Flatness G 2 Vo 0 2 V p p 7 MHz Input Overdrive Recovery Time G 1 5 5 V to 5 5 V 175 ns Output Recovery Time G 1 5 5 V to 5 5 V 170 ns Slew Rate G 2 Vo 4 V step 130 180 V us AD8065WARTZ only Tmn Tmax 155 V us Settling Time to 0 1 G 2 Vo 2 V step 55 ns G 2 Vo 8 V step 205 ns NOISE HARMONIC PERFORMANCE SFDR fc 1 MHz G 2 Vo 2 V p p 88 dBc fc 5 MHz G 2 Vo 2 V p p 67 dBc fc 1 MHz G 2 Vo 8 V p p 73 dBc Third Order Intercept fc 10 MHz R 100 O 24 dBm Input Voltage Noise f 10 kHz 7 nV VHz Input Current Noise f 10 kHz 0 6 fA VHz Differential Gain Error NTSC 2 1500 0 02 Differential Phase Error NTSC G 2 R 1500 0 02 Degrees DC PERFORMANCE Input Offset Voltage 0 V SOIC package 0 4 1 5 mV AD8065WARTZ only Tmn Tmax 2 6 mV Input Offset Voltage Drift 1 17 uV C AD8065WARTZ only Tmn Tmax 17 uV C Input Bias Current SOIC package 2 6 pA Tmn to Tmax 25 125 pA Input Offset Current 1 10 pA Tmn to Tmax 1 125 pA Open Loop Gain Vo
13. 10M 100M 1G 02916 E 021 FREQUENCY Hz 02916 E 018 FREQUENCY MHz Figure 18 Third Order Intercept vs Frequency and Supply Voltage Figure 21 Voltage Noise Rev J Page 12 of 28 AD8065 AD8066 50mV DIV 50mV DIV 02916 022 02916 025 Figure 22 Small Signal Transient Response 5 V Supply See Figure 42 Figure 25 Small Signal Transient Response 5 V See Figure 42 50ns DIV 50ns DIV 02916 023 02916 026 Figure 23 Large Signal Transient Response See Figure 42 Gz 1 Vs 5 ATSA TES el N y I 2 0V DIV 100ns DIV 1 2 0V DIV 1 100ns DIV 02916 024 02916 027 Figure 24 Output Overdrive Recovery See Figure 44 Figure 27 Input Overdrive Recovery See Figure 42 Rev J Page 13 of 28 AD8065 AD8066 0 1 0 1 INPUT BIAS CURRENT pA OFFSET VOLTAGE mV 140mV DIV 4 2mV DI 64us DIV pet Figure 28 Long Term Settling Time See Figure 49 25 35 45 55 65 75 85 TEMPERATURE C Figure 29 Input Bias Current vs Temperature 0 3 0 2 0 1 Vs 5V 0 Vg 5V 7 0 1 Vs 12V
14. 4 and total power dissipated in the package Pp determine the junction temperature of the die The junction temperature can be calculated by Ta Pp x Oa The power dissipated in the package Pp is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs The quiescent power is the voltage between the supply pins Vs times the quiescent current Is Assuming the load Ri is referenced to midsupply then the total drive power is Vs 2 x Iour some of which is dissipated in the package and some in the load Vour x Iour The difference between the total drive power and the load power is the drive power dissipated in the package Pp Quiescent Power Total Drive Power Load Power Vs V Vovr Pp Vs our epe Sac DUI 7 2 R R RMS output voltages should be considered If Ri is referenced to Vs as in single supply operation then the total drive power is Vs x Lour If the rms signal levels are indeterminate then consider the worst case when Vour Vs 4 for Ri to midsupply Vl4 sn R In single supply operation with Ri referenced to Vs worst case is Vour Vs 2 MAXIMUM POWER DISSIPATION W 60 40 20 0 20 40 60 80 100 AMBIENT TEMPERATURE C 02916 E 003 Figure 3 Maximum Power Dissipation vs Temperature for a 4 Layer Board Airflow increases heat dissipation effectively reducing Also mo
15. 5 100 1k 10k 100k 1M 10M 100M FREQUENCY MHz FREQUENCY Hz 8 Figure 34 CMRR vs Frequency See Figure 46 Figure 37 Output Impedance vs Frequency See Figure 45 and Figure 47 0 30 0 25 u 9 9 020 5 gt e z E 0 15 E lt lt c 2 2 gt a 0 10 5 5 5 VEE a 2 005 3 0 8 8 0 10 20 30 40 mA TEMPERATURE C Figure 35 Output Saturation Voltage vs Output Load Current Figure 38 Output Saturation Voltage vs Temperature 0 10 20 30 PSRR g 40 PSRR 8 50 lt a 60 4 o 70 80 90 100 8 0 01 0 1 1 10 100 1000 5 FREQUENCY MHz FREQUENCY MHz Figure 36 PSRR vs Frequency See Figure 48 and Figure 50 Figure 39 Crosstalk vs Frequency See Figure 51 Rev J Page 15 of 28 AD8065 AD8066 SUPPLY CURRENT mA Vg 12V 6 55 Vg 25V Vg 5V 40 20 0 20 40 60 80 TEMPERATURE C Figure 40 Quiescent Supply Current vs Temperature for Various Supply Voltages OPEN LOOP GAIN dB 02916 E 040 125 120 115 110 105 100 95 90 85 80 Vg 12 Vg 5V Vg 5 10 20 30 mA 40 02916 041 Figure 41 Open Loop Gain vs Load Current for Various Supply Voltages Rev J Page 16 of 28 AD8065 AD8066 TEST CIRCUITS SOIC 8 Pinout Voc Vcc O FET PROBE FET PROB
16. 9 24 Changes to Table 5 eii Ree 25 Moved Figure 60 and High Speed JFET Input Instrumentation Amplifier 5 etes ntt tei 25 Updated Outline Dimensions s 27 Changes to Ordering Guide sse 28 Added Automotive Products Section sss 28 3 09 Rev H to Rev I Changes to High Speed JFET Input Instrumentation Amplifier SECON 23 Updated Outline Dimensions s 24 9 08 Rev G to Rev H Deleted Usable Range Parameter Table 1 3 Deleted Usable Range Parameter Table 2 4 Deleted Usable Range Parameter Table 3 5 Changes to Layout eee treni Pre pepper 6 Changes to Input and Output Overload Behavior Section 19 Changes to Table 5 Expressions Column sss 22 1 06 Rev F to Rev G Changes to Ordering Guide sse 26 12 05 Rev E to Rev F Updated F r matieirassa ghasuqu qha uuu asa Universal Changes to Features saan 1 Changes to General Description ul Changes to Figure 22 through Figure 27 sss 11 Updated Outline Dimensions seen 25 Changes to Ordering Guide see 26 2 04 Rev D to Rev E Updated Format aa Universal Updated Fig re 56
17. ANALOG DEVICES High Performance 145 MHz FastFETOp Amps AD8065 AD8066 FEATURES Qualified for automotive applications FET input amplifier 1 pA input bias current Low cost High speed 145 MHz 3 dB bandwidth G 1 180 V us slew rate G 2 Low noise 7 nV VHz f 10 kHz 0 6 fA VHz f 10 kHz Wide supply voltage range 5 V to 24V Single supply and rail to rail output Low offset voltage 1 5 mV maximum High common mode rejection ratio 100 dB Excellent distortion specifications SFDR 88 dBc 1 MHz Low power 6 4 mA amplifier typical supply current No phase reversal Small packaging SOIC 8 SOT 23 5 and MSOP 8 GENERAL DESCRIPTION The AD8065 AD8066 FastFET amplifiers are voltage feedback amplifiers with FET inputs offering high performance and ease of use The AD8065 is a single amplifier and the AD8066 isa dual amplifier These amplifiers are developed in the Analog Devices Inc proprietary XFCB process and allow exceptionally low noise operation 7 0 nV NHz and 0 6 fA VHz as well as very high input impedance With a wide supply voltage range from 5 V to 24 V the ability to operate on single supplies and a bandwidth of 145 MHz the AD8065 AD8066 are designed to work in a variety of applications For added versatility the amplifiers also contain rail to rail outputs Despite the low cost the amplifiers provide excellent overall performance The differential gain and phase errors of 0 0296 and 0 02 re
18. E CLoAD 02916 E 042 02916 E 044 VEE VEE Figure 42 G 1 Figure 44 G 1 Vcc Vcc O Q FET PROBE NETWORK ANALYZER S22 CLoAD I 0 1uF VEE 02916 E 043 02916 E 045 VEE Figure 43 G 2 Figure 45 Output Impedance G 1 Rev J Page 17 of 28 AD8065 AD8066 Vcc VEE Figure 46 CMRR Vcc 4 7uF NETWORK ANALYZER 22 02916 E 047 VEE Figure 47 Output Impedance G 2 FET PROBE 02916 E 046 Rev J Page 18 of 28 Figure 48 Positive PSRR Vcc VEE Figure 49 Settling Time 9760 FET PROBE 02916 E 048 49 90 TO SCOPE O 02916 E 049 AD8065 AD8066 2 2pF FET PROBE FET PROBE 1kQ 02916 E 052 O 1 5V 1 5V 02916 E 050 VEE Figure 50 Negative PSRR Figure 52 Single Supply 24 90 AD8066 FET PROBE 24 90 RECEIVE SIDE 5V O DRIVE SIDE 02916 E 051 Figure 51 Crosstalk AD8066 Rev J Page 19 of 28 AD8065 AD8066 THEORY OF OPERATION The AD8065 AD8066 are voltage feedback operational amplifiers that combine a laser trimmed JFET input stage with the Analog Devices eXtra Fast Complementary Bipolar XFCB process resulting in an outstanding combination of precision and speed The supply voltage range is from 5 V to 24 V The amplifiers feature a patented rail to rail output stage capable of driving within 0 5 V of either power supply while sourcing or sinking up to 30 mA Also feat
19. Vo 22V SFDR gt 60 dBc f 500 kHz 30 mA Short Circuit Current 120 mA Capacitive Load Drive 30 overshoot G 1 25 pF POWER SUPPLY Operating Range 5 24 V Quiescent Current per Amplifier 6 6 74 mA Power Supply Rejection Ratio PSRR 84 93 dB Rev J Page 6 of 28 AD8065 AD8066 SPECIFICATIONS 5 V Ta 25 C Vs 5 V Rr 1 unless otherwise noted Table 3 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vo 0 2 V p p AD8065 125 155 MHz AD8065WARTZ only Tmn Tmax 90 MHz G 1 Vo 0 2 V p p AD8066 110 130 MHz G 2 Vo 0 2 V p p 50 MHz G 2 Vo 2Vp p 43 MHz Bandwidth for 0 1 dB Flatness G 2 Vo 0 2 V p p 6 MHz Input Overdrive Recovery Time G 1 0 5 V to 5 5 V 175 ns Output Recovery Time G 1 0 5 V to 5 5 V 170 ns Slew Rate G 2 Vo 2 V step 105 160 V us AD8065WARTZ only Tmn Tmax 123 V us Settling Time to 0 196 G 42 Vo 2 V step 60 ns NOISE HARMONIC PERFORMANCE SFDR fc 1 MHz G 2 Vo 2 V p p 65 dBc fc 5 MHz G 2 Vo 2 V p p 50 dBc Third Order Intercept fc 10 MHz R 100 O 22 dBm Input Voltage Noise f 10 kHz 7 nv VHz Input Current Noise f 10 kHz 0 6 fA VHz Differential Gain Error NTSC G 2 1500 0 13 Differential Phase Error NTSC G 2 R 150 Q 0 16 Degrees DC PERFORMANCE Input Offset Voltage Vem 1 0 V SOIC package 0 4 1 5 mV AD8065WARTZ only Tmn
20. Vosnom T AVs is the change in power supply from nominal conditions PSR is the power supply rejection AVcw is the change in common mode voltage from nominal conditions and CMR is the common mode rejection WIDEBAND OPERATION Figure 42 through Figure 44 show the circuits used for wideband characterization for gains of 1 2 and 1 Source impedance at the summing junction Re Rc forms a pole in the amplifiers loop response with the amplifier s input capacitance of 6 6 This can cause peaking and ringing if the time constant formed is too low Feedback resistances of 300 to 1 are recommended because they do not unduly load down the amplifier and the time constant formed will not be too low Peaking in the frequency response can be compensated for with a small capacitor Cr in parallel with the feedback resistor as illustrated in Figure 12 This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G 2 amplifier For the best settling times and the best distortion the impedances at the AD8065 AD8066 input terminals should be matched This minimizes nonlinear common mode capacitive effects that can degrade ac performance Actual distortion performance depends on a number of variables e closed loop gain of the application e Whether it is inverting or noninverting Amplifier loading e Signal frequency and amplitude e Board layout Also see Figure 16 to
21. _N R 8 AD8065AR REEL7 40 C to 85 C 8 Lead SOIC_N R 8 AD8065ARZ 40 C to 85 C 8 Lead SOIC_N R 8 AD8065ARZ REEL 40 C to 85 C 8 Lead SOIC_N R 8 AD8065ARZ REEL7 40 C 85 C 8 Lead SOIC_N R 8 AD8065ART R2 40 C to 85 C 5 Lead SOT 23 RJ 5 HRA AD8065ART REEL 40 C to 85 C 5 Lead SOT 23 RJ 5 HRA AD8065ART REEL7 40 C to 85 C 5 Lead SOT 23 RJ 5 HRA AD8065ARTZ R2 40 C to 85 C 5 Lead SOT 23 RJ 5 HRA AD8065ARTZ REEL 40 C to 85 C 5 Lead SOT 23 RJ 5 HRA AD8065ARTZ REEL7 40 C to 85 C 5 Lead SOT 23 RJ 5 HRA AD8065WARTZ REEL7 40 C to 105 C 5 Lead SOT 23 RJ 5 H2F AD8065ART EBZ Evaluation Board 8 Lead SOIC N AD8065AR EBZ Evaluation Board 5 Lead SOT 23 AD8066AR 40 C to 85 C 8 Lead SOIC_N R 8 AD8066AR REEL7 40 C to 85 C 8 Lead SOIC_N R 8 AD8066ARZ 40 C to 85 C 8 Lead SOIC_N R 8 AD8066ARZ RL 40 C to 85 C 8 Lead SOIC R 8 AD8066ARZ R7 40 C to 85 C 8 Lead SOIC_N R 8 AD8066ARM 40 C to 85 C 8 Lead MSOP RM 8 H1B AD8066ARM REEL 40 C to 85 C 8 Lead MSOP RM 8 H1B AD8066ARM REEL7 40 C to 85 C 8 Lead MSOP RM 8 H1B AD8066ARMZ 40 C to 85 C 8 Lead MSOP RM 8 H7C AD8066ARMZ REEL7 40 C to 85 C 8 Lead MSOP RM 8 H7C AD8066AR EBZ Evaluation Board 8 Lead SOIC_N AD8066ARM EBZ Evaluation Board 5 Lead SOT 23 17 RoHS Compliant Part denotes RoHS compliant product may be top or bottom marked W Qualified for Automotive A
22. ency response There are two methods to effectively minimize their effect e As shown in Figure 57 put a small value resistor Rs in series with the output to isolate the load capacitor from the amps output stage A good value to choose is 20 see Figure 10 e Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from IN to the output AD8065 Rg 200 lt o Vi 02916 E 057 Figure 57 Output Isolation Resistor Rev J Page 23 of 28 AD8065 AD8066 IPHOTO Rsp 10110 02916 058 Figure 58 Wideband Photodiode Preamp INPUT TO OUTPUT COUPLING To minimize capacitive coupling between the inputs and output the output signal traces should not be parallel with the inputs WIDEBAND PHOTODIODE PREAMP Figure 58 shows an I V converter with an electrical model of a photodiode The basic transfer function is 1 Xx Rr QUT 1 sCpRz where Iporo is the output current of the photodiode and the parallel combination of Rr and Cr sets the signal bandwidth The stable bandwidth attainable with this preamp is a function of Rg the gain bandwidth product of the amplifier and the total capacitance at the amplifiers summing junction including Cs and the amplifier input capacitance Rr and the total capacitance produce a pole in the amplifier s loop transmission that can result in peaking and instability Adding Cr creates a 0
23. ential pair now sets the amplifier s offset and the input bias current is now in the range of several tens of microamps This behavior is shown in Figure 32 Normal operation resumes when the common mode voltage goes below the 3 V from the positive supply threshold The output transistors of the rail to rail output stage have circuitry to limit the extent of their saturation when the output is overdriven This helps output recovery time Output recovery from a 0 5 V output overdrive on a 5 V supply is shown in Figure 24 vBIAS Q7 02916 E 056 VEE Figure 56 Simplified Input Stage Rev J Page 22 of 28 AD8065 AD8066 LAYOUT GROUNDING AND BYPASSING CONSIDERATIONS POWER SUPPLY BYPASSING Power supply pins are actually inputs and care must be taken so that a noise free stable dc voltage is applied The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies thereby shunting or filtering most of the noise Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors 0 1 uF X7R or NPO chip capacitors are critical and should be as close as possible to the amplifier package The 4 7 uF tantalum capacitor is less critical for high frequency bypassing and in most cases only one is needed per board at the supply inputs GROUNDING A ground plane layer is important in densely packed PC boards
24. esponse 20 Wideband Operatloti ect ettet 21 Input Protection eterne 21 Thermal Considerations seen 22 Input and Output Overload Behavior 22 Layout Grounding and Bypassing Considerations 23 Power Supply Bypassing seen 23 GOUGING eee ADD abel 23 Leakage Currents i PE Rete R Ei 23 Input Capacitance iiri DR I 23 Output Capacitance esee tnnt 23 Input to Output Coupling een 24 Wideband Photodiode Preamp sss 24 High Speed JFET Input Instrumentation Amplifier 25 Video B ffet gan i Outline Dimensions Orderine Guides cose ott etn 28 Automotive Products asss 28 Rev J Page 2 of 28 AD8065 AD8066 REVISION HISTORY 8 10 Rev I to Rev J Changes to Features Section Applications Section and General er tente eoe det 1 Change to TablesE ettet P eei ets 4 Change to Table E bea 7 Changes to Tabled usen et deris 9 Changes to Figure 10 Changes to Inverting Closed Loop Frequency Response ru 20 Moved Leakage Currents Section Input Capacitance Section and Output Capacitance Section sse 23 Moved Input to Input Coupling Section Wideband Photodiode Preamp Section and Figure 5
25. gure 4 Small Signal Frequency Response for Various Gains Vo 200mV p p 10 1000 FREQUENCY MHz Figure 5 Small Signal Frequency Response for Various Supplies See Figure 42 10 FREQUENCY MHz Figure 6 Large Signal Frequency Response for Various Supplies See Figure 42 GAIN dB 02916 E 004 GAIN dB 02916 E 005 GAIN dB 02916 E 006 Rev J Page 10 of 28 100 FREQUENCY MHz Figure 7 0 1 dB Flatness Frequency Response See Figure 43 Vo 200mV 2 8 Vg 5V 7 Sce Vg 5V 6 Vg 12V 5 4 3 0 1 1 10 100 1000 FREQUENCY MHz Figure 8 Small Signal Frequency Response for Various Supplies See Figure 43 Vo 2V p p FREQUENCY MHz Figure 9 Large Signal Frequency Response for Various Supplies See Figure 43 02916 E 007 02916 009 02916 E 008 AD8065 AD8066
26. in the loop transmission that compensates for the pole effect and reduces the signal bandwidth It can be shown that the signal bandwidth resulting in a 45 phase margin fus is defined by Fer 2nx Rp XC fas where fcr is the amplifier crossover frequency Rr is the feedback resistor and Cs is the total capacitance at the amplifier summing junction amplifier photodiode board parasitics The value of Cr that produces fs can be shown to be C C 2 S 2n X Ry X fen The frequency response in this case shows about 2 dB of peaking and 15 overshoot Doubling Cr and cutting the bandwidth in half results in a flat frequency response with about 5 transient overshoot The preamps output noise over frequency is shown in Figure 59 1 fe 2nRp CF Cs Cu 2Cp 1 2 Quos 3 iL 3 Cg 205 NOISE VOLTAGE NOISE 2 02916 E 059 FREQUENCY Hz Figure 59 Photodiode Voltage Noise Contributions The pole in the loop transmission translates to a 0 in the amplifier noise gain leading to an amplification of the input voltage noise over frequency The loop transmission 0 introduced by C limits the amplification The noise gain bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier Keeping the input terminal impedances matched is recommended to eliminate common mode
27. is 50 MHz For higher gains the bandwidth is set by the preamp equaling Inamp fca x Ro 2X Re Common mode rejection of the in amp is primarily determined by the match of the resistor ratios R1 R2 to R3 R4 It can be estimated Vo _ 61 82 Vom 1 81 82 The summing junction impedance for the preamps is equal to Re 0 5 Ro This is the value to be used for matching purposes Rev J Page 25 of 28 AD8065 AD8066 VIDEO BUFFER The output current capability and speed of the AD8065 make it useful as a video buffer shown in Figure 61 The G 2 configuration compensates for the voltage division of the signal due to the signal termination This buffer maintains 0 1 dB flatness for signals up to 7 MHz from low amplitudes up to 2 V p p see Figure 7 Differential gain and phase have been measured to be 0 02 and 0 028 respectively at 5 V supplies 759 Vo 02916 E 061 Figure 61 Video Buffer Rev J Page 26 of 28 AD8065 AD8066 OUTLINE DIMENSIONS 5 00 0 1968 4 80 0 1890 RR 8 5 4 00 0 1574 6 20 0 2441 3 80 0 1497 11 4 5 80 0 2284 t xb l lt 1 27 0 0500 0 50 0 0196 5 BSC 1 75 0 0688 F 0 25 0 0099 0 25 0 0098 1 35 0 0532 0 10 0 0040 yy PLANARITY 0 51 0 0201 gt e ii 0 10 N alos 00122 0 Um 1 27 0 0500 SEATING 0 25 0 0098 525 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS
28. ncy where the amplifiers open loop gain equals 0 db Vo _ Rr R G Atdc L C V RG Closed loop 3 dB frequency R foie x Ret Rs INVERTING CLOSED LOOP FREQUENCY RESPONSE Vo _ 2n x Jose x Rp Vi s R Rg 21X forossover X Rg Closed loop 3 dB frequency R x 8 _ Rp t Rg J sap zi Terossover forossover 65MHz 02916 E 053 10 100 Figure 53 Open Loop Gain vs Frequency and Basic Connections Rev J Page 20 of 28 AD8065 AD8066 The closed loop bandwidth is inversely proportional to the noise gain of the op amp circuit Rr Re Rc This simple model is accurate for noise gains above 2 The actual bandwidth of circuits with noise gains at or below 2 is higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp 02916 E 054 Figure 54 Voltage Feedback Amplifier DC Errors Figure 54 shows a voltage feedback amplifier s dc errors For both inverting and noninverting configurations Ro R Vo error 2 Ij X Rs Ro R S 3 G The voltage error due to Iz and Iv is minimized if Rs Re Re though with the AD8065 input currents at typically less than 20 pA over temperature this is likely not a concern To include common mode and power supply rejection effects total Vos can be modeled AV AV u PSR CMR V is the offset voltage specified at nominal conditions OSnom Vos
29. ng Supply Voltage 26 4V Power Dissipation See Figure 3 Common Mode Input Voltage Ve 0 5 V to Vcc 0 5 V Differential Input Voltage 1 8V Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C AD8065WARTZ Only 40 C to 105 C Lead Temperature 300 C Soldering 10 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8065 AD8066 packages is limited by the associated rise in junction temperature Tj on the die The plastic encapsulating the die locally reaches the junction temperature At approximately 150 C which is the glass transition temperature the plastic changes its properties Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die permanently shifting the parametric performance of the AD8065 AD8066 Exceeding a junction temperature of 175 C for an extended time can result in changes in the silicon devices potentially causing failure The still air thermal properties of the package and PCB ambient temperature T
30. pplications AUTOMOTIVE PRODUCTS The AD8065W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications Note that these automotive models may have specifications that differ from the commercial models therefore designers should review the Specifications section of this data sheet carefully Only the automotive grade products shown are available for use in automotive applications Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models 2002 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D02916 0 8 10 J DEVICES Rev J Page 28 of 28
31. re metal directly in contact with the package leads from metal traces through holes ground and power planes reduce the Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Layout Grounding and Bypassing Considerations section Figure 3 shows the maximum safe power dissipation in the package vs the ambient temperature for the SOIC 125 C W SOT 23 180 C W and MSOP 150 C W packages on a standard 4 layer board Oja values are approximations OUTPUT SHORT CIRCUIT Shorting the output to ground or drawing excessive current for the AD8065 AD8066 will likely cause catastrophic failure ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev J Page 9 of 28 AD8065 AD8066 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions 5 V 5 pF Rr 1 Vour 2 V p p Temperature 25 C GAIN dB GAIN dB GAIN dB 24 21 10 200mV p p lt o 5 2 1 10 100 1000 FREQUENCY MHz Fi
32. s rated to operate over the extended temperature range 40 C to 105 C up to a maximum supply voltage range of 5V only 24 21 G 10 Vo 200mV 18 15 G2 5 12 ta 9 lt 2 9 6 3 1 0 3 6 0 1 1 10 100 1000 02916 E 002 FREQUENCY MHz Figure 2 Small Signal Frequency Response One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2002 2010 Analog Devices Inc All rights reserved AD8065 AD8066 TABLE OF CONTENTS Features aS amaka Sua LU LE Mer 1 Applications i a eroe Me IR CURVE 1 Connection Diagrams seen 1 General Descriptions onec t o RE lya daya 1 REVISION Histoby aaa esie Died Ie cece ee 3 Specifications SP Vaaa asss 4 Specifications E12 V a 6 Specifications 4 5 Vua a s ee dinde e sua patsa 7 Absolute Maximum Ratings seen 9 Maximum Power Dissipation sse 9 Output Short Circuit y eect tec 9 ESD nette tiennent eerie tins 9 Typical Performance Characteristics a 10 Test Circuits Lee 17 Theory of Operation retten entere 20 Closed Loop Frequency Response eee 20 Noninverting Closed Loop Frequency Response 20 Inverting Closed Loop Frequency R
33. shield around the inputs and input leads that are driven to the same voltage potential as the inputs This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents For the guard ring to be completely effective it must be driven by a relatively low impedance source and should completely surround the input leads on all sides above and below using a multilayer board Another effect that can cause leakage currents is the charge absorption of the insulator material itself Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption Also low absorption materials such as Teflon or ceramic could be necessary in some instances INPUT CAPACITANCE Along with bypassing and ground high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground A few pF of capacitance reduces the input impedance at high frequencies in turn increasing the amplifiers gain causing peaking of the frequency response or even oscillations if severe enough It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance The ground and power planes must be kept at a small distance from the input pins on all layers of the board OUTPUT CAPACITANCE To a lesser extent parasitic capacitances on the output can cause peaking and ringing of the frequ
34. spectively along with 0 1 dB flatness out to 7 MHz make these amplifiers ideal for video applications Additionally they offer a high slew rate of 180 V us excellent distortion SFDR of 88 dBc 1 MHz extremely high common mode rejection of 100 dB and a low input offset voltage of 1 5 mV maximum under warmed up conditions The AD8065 AD8066 operate using only a 6 4 mA amplifier typical supply current and are capable of delivering up to 30 mA ofload current Protected by U S Patent No 6 262 633 Rev J Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners APPLICATIONS Automotive driver assistance systems Photodiode preamps Filters A D drivers Level shifting Buffering CONNECTION DIAGRAMS 02916 E 001 Figure 1 The AD8065 AD8066 are high performance high speed FET input amplifiers available in small packages SOIC 8 MSOP 8 and SOT 23 5 They are rated to work over the industrial temperature range of 40 C to 85 C The AD8065WARTZ REEL7 is fully qualified for automotive applications It i
35. tres ntt ERR 21 Updated Outline Dimensions eee 25 Updated Ordering Guide es 26 11 03 Rev C to Rev D Changes to Feat res eicere ene its 1 Changes to Connection Diagrams esee 1 Updated Ordering Guide sse Updated Outline Dimensions 4 03 Rev B to Rev C Added SOIC 8 R for the AD8065 sse 4 2 03 Rev A to Rev B Changes to Absolute Maximum Ratings sess 4 Changes to Test Circuit 10 14 Changes to Test Circuit TL iie teet a a u a yaka 15 Changes to Noninverting Closed Loop Frequency Response 16 Changes to Inverting Closed Loop Frequency Response 16 Updated Figure 6 SGre ete eiae i e 18 Changes to Figure 7 1 iode teet 19 Changes to Figure entere tabes 21 Changesto Figure 22 Changes to High Speed JFET Instrumentation Amplifier 22 Changes to Video Buffer eu eite eoe ieri 22 8 02 Rev 0 to Rev A Added AD8066 oe Ret EE diede Universal Added SOIC 8 R and MSOP 8 RM es 1 Edits to General Description zl Edits to Specifications neee i eqs 2 New 5 Changes to Ordering Guide sse 5 Edits to TPCs 18 25 and 287 sss 8 New TPO 36 11 Added Test Circuits 10 and 11 sse 14 MSOP RM 8 Added aicise 23 Rev J Page 3
36. ured is a single supply input stage that handles common mode signals from below the negative supply to within 3 V of the positive rail Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply The amplifiers operate as if they have a rail to rail input and exhibit no phase reversal behavior for common mode voltages within the power supply With voltage noise of 7 nV VHz and 88 dBc distortion for 1 MHz 2 V p p signals the AD8065 AD8066 are a great choice for high resolution data acquisition systems Their low noise sub pA input current precision offset and high speed make them superb preamps for fast photodiode applications The speed and output drive capability of the AD8065 AD8066 also make them useful in video applications CLOSED LOOP FREQUENCY RESPONSE The AD8065 AD8066 are classic voltage feedback amplifiers with an open loop frequency response that can be approximated as the integrator response shown in Figure 53 Basic closed loop frequency response for inverting and noninverting configurations can be derived from the schematics shown 80 2 fcrossover S OPEN LOOP GAIN dB 2 N 0 01 0 1 1 FREQUENCY MHz NONINVERTING CLOSED LOOP FREQUENCY RESPONSE Solving for the transfer function Vo 27 x Rg Rg s 27 x Rg where ferossover is the freque

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