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ANALOG DEVICES AD8099 handbook

1. 4 4 Vout 0 2V p p G 2 Vour 0 2V p p 3 Vs 5V G 5 3 Vs 5V 2 Rloap 1ko 2 Rloan lt 1ko a s CN S o1 a EE a o H A o a 5 NE 9 9 Bi G 20 a 3 bo G 10 T O A oO A G G 1 G a 5 D a 5 N N 6 7 S z z o u 6 E 9 z 9 z 2 10 S 10 8 1 10 100 1000 1 10 100 1000 7 FREGUENCY MHz FREQUENCV MHz E Figure 5 Small Signal Frequency Response for Various Gains SOIC Figure 8 Small Signal Freguency Response for Various Gains CSP 17 RL 1ko CSP G 45 16 RL 1ko Vout 0 2V p p Vg E 15 Z g ga z S Na Vs 5V SOIC i a lt H Q S V a a S B 12 A te e D 3 1 11 Y S Vs 2 5V CSP L 8 6 1 H al l 1 o gt 4 Vs 5V CSP 8 Ti z Vs 2 5V SOIC i S 7 3 1 10 100 1000 1 10 100 1000 FREGUENCY MHz E FREQUENCV MHz Figure 6 Small Signal Frequency Response for Various Load Resistors Figure 9 Small Signal Frequency Response for Various Supply Voltages 11 Vour 0 2V p p 125 C Vout 0 2V p p 10 9 Q A 85 C 8 kl z z a 7 1 lt 6 6 o Ei 25 C d fe a 5 a W W o 4 o a 40 C a o lE o 3 G 2 2 Ve 5V R
2. Figure 49 Input Voltage Noise vs Frequency POWER SUPPLY REJECTION dB 04511 0 113 INPUT CURRENT NOISE pAWHz 04511 0 004 COUNT 04511 0 005 Rev B Page 13 of 28 AD8099 FREQUENCV MHz Figure 50 Power Supplv Rejection vs Frequencv 1000 eo o o 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz Figure 51 Input Current Noise vs Frequency DISABLE Vs 120 sr y A 1 JI Jm bet 200 100 A 200 VoFFSET ka Figure 52 Input Offset Voltage Distribution 04511 0 114 04511 0 003 04511 0 075 AD8099 OFFSET VOLTAGE uV BIAS CURRENT 1A Figure 54 Input Bias Current vs Temperature DISABLE Pin Floating OUTPUT SATURATION VOLTAGE V 400 300 200 100 Vs 5V 100 200 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 53 Input Offset Voltage vs Temperature le Vg SEN Is Vg 5V
3. Figure 25 Harmonic Distortion vs Freguency SOIC HARMONIC DISTORTION dBc 04511 A 009 HARMONIC DISTORTION dBc 04511 A 010 HARMONIC DISTORTION dBc 04511 A 011 Rev B Page 9 of 28 AD8099 40 G 2 Vout 2V pp P 50 ve 5V 7 RL 1ko d p SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC 1 0 10 0 FREQUENCY MHz Figure 26 Harmonic Distortion vs Frequency CSP x Wi 60 70 80 90 100 110 120 EZ ad da SOLID LINE SECOND HARMONIC 130 0 1 DOTTED LINE THIRD HARMONIC 1 0 10 0 FREQUENCV MHz Figure 27 Harmonic Distortion vs Freguency CSP SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC 1 0 10 0 FREQUENCV MHz Figure 28 Harmonic Distortion vs Frequency CSP 04511 A 012 04511 A 013 04511 A 014 AD8099 Vg 2 5V 5 Ki Vout 1V p p m a e KA z z ej E E 7 e o o H H 9 9 a a z z S 0 e lt lt R ee T ano SOLID LIN
4. PackageTvpe Board Configuration CSP SOIC Inverting EVAL ADOPAMP 1CSP EVAL ADOPAMP 1R IN Noninverting EVAL ADOPAMP 1CSP N EVAL ADOPAMP 1R NI Rev B Page 24 of 28 OUTLINE DIMENSIONS 5 00 0 197 BOTTOM VIEW 4 90 0 193 PINS UP 4 00 0 157 e 0 189 L tali 29 0 092 3 90 0 154 AAA ADF 3 80 0 150 6 20 0 244 2 29 0 092 6 00 0 236 Wt 5 80 0 228 DI JI 127 0 08 0 50 0 020 BSC kie aa TT 1 75 0 069 0 25 0 010 0 25 0 0098 1 35 0 053 ra atowo 4 TITTI HA R JL 0 51 0 020 0 25 b 0098 0 1 27 0 050 copa ya RITY SEATING 0 31 0 012 0 17 0 0068 040 0 016 PLANE COMPLIANT TO JEDEC STANDARDS MS 012 CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 74 8 Lead Standard Small Outline Package SOIC ED RD 8 1 0 50 0 40 0 60 MAX 9 G PIN1 d INDICATOR 0 45 3 Ai 1 PIN 1 11l A 1 90 150 1 90 INDICATOR eal OTOM jis L Bsc Lg a Ka 0 25 JL 1 60 0 90 19 MAX 0 80 MAX MIN 1 45 085 j 0 65TYP 1 30 0 80 0 05 MAX 0 02 NOM SEATING ae 0 30 LANE 0 0 20 REF 0 18 Figure 75 8 Lead Plastic Surface Mount Package CSP CP 8 Dimensions shown in millimeters Rev B Page 25 of 28 AD8099 AD8099 ORDERING GUIDE Model Branding Package Option AD8099ARD 40 C to 125 C 8 Lead SOIC ED RD 8 1
5. 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C 1 24 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 55 Output Saturation Voltage vs Temperature SUPPLY CURRENT mA 04511 A 003 BIAS CURRENT HA 0451 1 A 004 04511 A 005 Rev B Page 14 of 28 20 IS N 16 14 10 0 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 56 Supply Current vs Temperature Ip Vg 5V l S AN 0 jis Vs AN s lei Vg BV lt le Vg 5V 1 0 0 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 57 Input Bias Current vs Temperature DISABLE Pin Vs 04511 A 006 0451 1 A 007 THEORY OF OPERATION The AD8099 is a voltage feedback op amp that employs a new highly linear low noise input stage With this input stage the AD8099 can achieve better than 90 dB distortion for a 2 V p p 10 MHz output signal with an input referred voltage noise of less than 1 nV VHz This noise level and distortion performance has been previously achievable only with fully uncompensated amplifiers The AD8099 achieves this level of performance for gains as low as 2 This new input stage also triples the achievable slew rate for comparably compensated 1 nV VHz amplifiers The simplified AD8099 topology is shown in Figure 58 The amplifier is a sing
6. Figure 63 Amplifier Configuration for CSP Package Gain 2 Rev B Page 17 of 28 AD8099 04511 0 057 04511 0 055 Figure 66 Amplifier Configuration for CSP and SOIC Packages Gain 20 Figure 64 Amplifier Configuration for CSP and SOIC Package Gain 5 Vs C2 O 04511 0 056 Figure 65 Amplifier Configuration for CSP and SOIC Packages Gain 10 Rev B Page 18 of 28 AD8099 PERFORMANCE VS COMPONENT VALUES The influence that each component has on the AD8099 frequency response can be seen in Figure 67 and Figure 68 In Figure 67 and Figure 68 all component values are held constant except for the individual component shown which is varied For example in the Rsperformance plot of Figure 68 all components are held constant except Rs which is varied from 0 Q to 50 Q and clearly indicates that Rs has a major influence on peaking and bandwidth of the AD8099 CLOSED LOOP GAIN dB G 2 2 1 Rioap 1k SOIC PACKAGE 1 10 100 1000 3000 FREOUENCY MHz 04511 0 020 04511 0 117 19 Vg LBV g G 2 Rioap 1kO L 8 SOIC PACKAGE L T a 7 Z z z z 6 WU Rc 500 lt lt 0 6 G 5 a a fej fe H o 6 4 H a a 3 8 8 2 H a G Rc 200 d D T
7. ssesemenmnnnnnnzonnnnznzonnizn 8 Inserted new Figures 51 to Been 14 Changes to Theory of Operation section 16 Changes to Circuit Components section 17 Changes to Tablet isir 18 Changes to Figure 60 sssseeennznnnszznnzzznnnezznniznzznnzzni 18 Changes to Total Output Noise Calculations and Design SCCEON sign asni siss sas nisagaassan saa s an s pe Changes to Figure 60 Changes to Figure 62 Changes to 16 Bit ADC Driver section eee 23 Changes RE TTT 23 Additions to PCB Layout section En 23 11 03 Revision 0 Initial Version Recommended Valties sis sisieniezianzesejenzontennzezstosetazitoiemz ediiazzz 17 Circuit Configurations eenegen 17 Performance vs Component values essere eree 19 Total Output Noise Calculations and Design s m 20 Input Bias Current and DC Offset ENNEN 21 DISABLE Pin and Input Bias Cancellation 21 16 Bit ADC KE 22 Circuit Considerations ENEE 23 Design Tools and Technical Support 23 Outline Dimensions ENEE 25 Ordering Guides sins siri 26 Rev B Page 2 of 28 AD8099 SPECIFICATIONS SPECIFICATIONS WITH 5 V SUPPLY Ta 25 C G 2 R 1 kO to ground unless otherwise noted Refer to Figure 60 through Figure 66 for component values and gain configurations Table 1 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 5 Vour 0 2 V p p 450 510 MHz G 5 Vout 2 V p p 205 235 MHz Band
8. AD8099ARD REEL SH 40 C to 125 C 8 Lead SOIC ED RD 8 1 AD8099ARD REEL7 1 000 40 C to 125 C 8 Lead SOIC ED RD 8 1 AD8099ARDZ 1 40 C to 125 C 8 Lead SOIC ED RD 8 1 AD8099ARDZ REEL 2 500 40 C to 125 C 8 Lead SOIC ED RD 8 1 AD8099ARDZ REEL7 1 000 40 C to 125 C 8 Lead SOIC ED RD 8 1 AD8099ACP R2 250 40 C to 125 C 8 Lead CSP HDB CP 8 AD8099ACP REEL 5 000 40 C to 125 C 8 Lead CSP HDB CP 8 AD8099ACP REEL7 1 500 40 C to 125 C 8 Lead CSP HDB CP 8 AD8099ACPZ R2 250 40 C to 125 C 8 Lead CSP HDB CP 8 AD8099ACPZ REEL 5 000 40 C to 125 C 8 Lead CSP HDB CP 8 AD8099ACPZ REEL7 1 500 40 C to 125 C 8 Lead CSP HDB CP 8 1Z Pb free Rev B Page 26 of 28 AD8099 NOTES Rev B Page 27 of 28 AD8099 NOTES 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana l 0 g com ass LA DEVICES Rev B Page 28 of 28
9. 0 i x Rc 350 7 1 10 100 1000 3000 1 10 100 1000 3000 S z FREOUENCY MHz FREQUENCV MHz Figure 67 Frequencv Response for Various Values of C1 Cc Rc Rev B Page 19 of 28 AD8099 w RF RG 200 9 M d 8 a 7 z d z S 5 e Rr Rg 300 A 8 4 3 Rf Rg 250 5 3 F Rg LU 2 ti 2 1 o i 1 Vs 5V H G 42 H RLoaD 1kQ t 4 SOIC PACKAGE H 1 10 100 1000 3000 FREQUENCV MHz 12 Rs 0 11 10 9 H D Q z 8 z h lt 7 L e La a o Rs 507 fe d 7 OS Y a kI 9 4 a 3 O Rs 20 d 2 Vs 5V A G 42 i 1 RLoAD 1KQ T o SOIC PACKAGE H 1 10 100 1000 10000 FREOUENCY MHz 04511 0 032 04511 0 034 CLOSED LOOP GAIN dB TA 10 100 1000 3000 FREQUENCV MHz E tVs c2 O O Vout 04511 0 117 SOIC PINOUT SHOWN Figure 68 Frequencv Response for Various Values of Rr Cr Rs TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN To analvze the noise performance of an amplifier circuit the individual noise sources must be identified Then determine if the source has a significant contribution to overall noise perfor mance of the amplifier To simplifv the noise calculations we will work with noise spectral densities rather than actual voltages to leave bandwidth out of t
10. Performance fc 20 kHz Vour 2 24 V p p Parameter Measurement dB Second Harmonic Distortion Third Harmonic Distortion THD SFDR SNR Rev B Page 22 of 28 111 4 103 2 101 4 102 2 88 1 CIRCUIT CONSIDERATIONS Optimizing the performance of the AD8099 requires attention to detail in layout and signal routing of the board Power supply bvpassing parasitic capacitance and component selection all contribute to the overall performance of the amplifier The AD8099 features an exposed paddle on the backs of both the CSP and SOIC packages The exposed paddle provides a low thermal resistive path to the ground plane For best performance solder the exposed paddle to the ground plane PCB Layout The compensation network is determined by the amplifier gain requirements For lower gains the layout and component placement are more critical For higher gains there are fewer compensation components which results in a less complex layout With diligent consideration to layout grounding and component placement the AD8099 evaluation boards have been optimized for peak performance These are the same evaluation boards that are available to customers see Table 7 for ordering information The noninverting evaluation board art work for SOIC and CSP layouts are shown in Figure 72 and Figure 73 Incorporating the layout information shown in Figure 72 and Figure 73 into new designs is highly recom mended and helps t
11. UNC Input Bias Current DISABLE pin floating 6 2 13 pA DISABLE pin Vs 0 2 2 pA Input Bias Offset Current 0 05 1 HA Input Bias Offset Current Drift 2 4 nA C Open Loop Gain Vour 1 Vto4V 76 81 dB INPUT CHARACTERISTICS Input Resistance Differential mode 4 kO Common mode 10 MQ Input Capacitance 2 pF Input Common Mode Voltage Range 1 3 to 3 7 V Common Mode Rejection Ratio Vm 2Vto3V 88 105 dB DISABLE PIN DISABLE Input Voltage Output disabled lt 24 V Turn Off Time 50 of DISABLE to lt 10 of Final Vour 105 ns Vn 0 5 V G 2 Turn On Time 50 of DISABLE to lt 10 of Final Vour 61 ns Vn 0 5 V G 2 Enable Pin Leakage Current DISABLE 5 V 16 21 HA DISABLE Pin Leakage Current DISABLE 0V 33 44 HA OUTPUT CHARACTERISTICS Overdrive Recovery Time Rise Fall Vin 0to2 5V G 2 50 70 ns Output Voltage Swing Ri 1000 1 5 to 3 5 1 2 to 3 8 V RL 1 kO 1 2 to 3 8 1 2 to 3 8 V Short Circuit Current Sinking and Sourcing 60 80 mA Off Isolation f 1 MHz DISABLE Low 61 dB POWER SUPPLY Operating Range 5 6 V Quiescent Current 14 5 154 MA Ouiescent Current Disabled DISABLE Low 1 4 17 MA Positive Power Supply Rejection Ratio Vs 4 5 V to 5 5 V Vs 0 V input referred 84 89 dB Negative Power Supply Rejection Ratio Vs 5 V Vs 0 5 V to 0 5 V input referred 84 90 dB Rev B Page 4 of 28 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating Supplv Voltage 12 6V Power Dissipation See Figure 4 Differ
12. V RL 1 ko 3 7 to 3 7 3 8 to 3 8 V Short Circuit Current Sinking and sourcing 131 178 mA Off Isolation f 1 MHz DISABLE low 61 dB POWER SUPPLY Operating Range 5 6 V Quiescent Current 15 16 mA Quiescent Current Disabled DISABLE Low 1 7 2 mA Positive Power Supply Rejection Ratio Vs 4V to 6V Vs 5V input referred 85 91 dB Negative Power Supply Rejection Ratio Vs 5V Vs 6 V to 4 V input referred 86 94 dB Rev B Page 3 of 28 AD8099 SPECIFICATIONS WITH 5 V SUPPLY Vs 5 VE TA 25 C G 2 Rr 1 kO to midsupply unless otherwise noted Refer to Figure 60 through Figure 66 for component values and gain configurations Table 2 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 5 Vout 0 2 V p p 415 440 MHz G 5 Vout 2 V p p 165 210 MHz Bandwidth for 0 1 dB Flatness SOIC CSP G 2 Vour 0 2 V p p 33 23 MHz Slew Rate G 10 Vout 2 V Step 630 715 V us G 2 Vout 2 V Step 340 365 V us Settling Time to 0 190 G 2 Vout 2 V Step 18 ns NOISE DISTORTION PERFORMANCE Harmonic Distortion dBc HD2 HD3 fc 500 kHz Vour 1 V p p G 10 82 94 dBc fc 10 MHZ Vour 1 V p p G 10 80 75 dBc Input Voltage Noise f 100 kHz 0 95 nV Hz Input Current Noise f 100 kHz DISABLE pin floating 2 6 pA Hz f 100 kHz DISABLE pin Vs 5 2 pA Hz DC PERFORMANCE Input Offset Voltage 0 1 0 5 mV Input Offset Voltage Drift 2 5
13. d S 4 N 1 0 z z 8 CSP E 50 Sole f 3 01 9 ae 60 u 2 6 E 70 0 01 80 Vg 5V G 2 wei 3 0 001 8 90 8 1 10 100 1000 2 0 1 1 10 100 1000 Ha FREQUENCV MHz 8 FREQUENCV MHz Figure 18 Input Impedance vs Frequency Figure 21 Off Isolation vs Frequency 100 0 rr ooo oro G 45 vour S N P P 60 Vs G 2 5 RL 1000 10 g a 8 70 z 6 e E 80 lt tr solc Q 1 G 42 G 10 o S 90 A 3 l o 4 zene 5 2 E B K 5 S 100 o 01 fa at ja CSP TIT a I dal SOLID LINES SECOND HARMONICS l Vs 5V g DOTTED LINES THIRD HARMONICS g 0 1 1 10 100 1000 1 0 10 0 i FREQUENCV MHz S FREQUENCV MHz g Figure 19 Output Impedance vs Frequency for Various Gains Figure 22 Harmonic Distortion vs Frequency Rev B Page 8 of 28 HARMONIC DISTORTION dBc HARMONIC DISTORTION dBc HARMONIC DISTORTION dBc SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC 1 0 10 0 FREQUENCV MHz Figure 23 Harmonic Distortion vs Frequencv SOIC SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC 0 1 1 0 10 0 FREQUENCV MHz Figure 24 Harmonic Distortion vs Frequencv SOIC SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC 0 1 1 0 10 0 FREQUENCV MHz
14. for ease in con necting a feedback network to the inputs The secondary output pin also isolates the interaction of any capacitive load on the AD8099 output and self inductance of the package and bond wire from the feedback loop While using the secondary output for feed back inductance in the primary output will now help to isolate capacitive loads from the output impedance of the amplifier Since the SOIC has greater inductance in its output the SOIC will drive capacitive loads better than the LFCSP Using the primary output for feedback with both packages will result in the LFCSP driving capacitive load better than the SOIC The LFCSP and SOIC pinouts are identical except for the rotation of all pins counterclockwise by one pin on the LFCSP This isolates the inputs from the negative power supply pin removing a mutually inductive coupling that is most prominent while driving heavy loads For this reason the LFCSP second harmonic while driving a heavy load is significantly better than that of the SOIC A three state input pin is provided on the AD8099 for a high impedance power down and an optional input bias current cancellation circuit The high impedance output allows several AD8099s to drive the same ADC or output line time inter leaved Pulling the DISABLE pin low activates the high impedance state See Table 5 for threshold levels When the DISABLE pin is left floating the AD8099 operates normally With the DISABLE pin pul
15. if Is and Ir are the same and R3 equals the parallel combination of RI and R2 then the RTI offset voltage can be reduced to only Vos This is a common method used to reduce output offset voltage Keeping resistances low helps to minimize offset error voltage and keeps the voltage noise low DISABLE PIN AND INPUT BIAS CANCELLATION The AD8099 DISABLE pin performs three functions enable disable and reduction of the input bias current When the DISABLE pin is brought to within 0 7 V of the positive supplv the input bias current is reduced bv an approximate factor of 60 However the input current noise doubles to 5 2 pA VHz Table 5 outlines the DISABLE pin functionalitv Table 5 DISABLE Pin Truth Table Supplv Voltage 5V 5V Disable 5 to 2 4 0to 2 4 Enable Open Open Low Input Bias Current 4 3 to 5 4 3 to 5 Rev B Page 21 of 28 AD8099 2 5V R1 L 5900 5907 AVDD O AD7667 Figure 71 ADC Driver 16 BIT ADC DRIVER Ultralow noise and distortion performance make the AD8099 an ideal ADC driver Even though the AD8099 is not unity gain stable it can be configured to produce a net gain of 1 amplifier as shown in Figure 71 This is achieved by combining a gain of 2 and a gain of 1 for a net gain of 1 The input range of the ADC is 0 V to 2 5 V Table 6 shows the performance data of the AD8099 and the Analog Devices AD7667 a 1 MSPS 16 bit ADC O DVDD 04511 0 072 Table 6 ADC Driver
16. pins of the amplifier For C3 C5 a 0508 case size should be used The 0508 case size offers reduced inductance and better frequency response C4 and C2 Electrolytic bypass capacitors Rev B Page 16 of 28 AD8099 RECOMMENDED VALUES Table 4 Recommended Values and AD8099 Performance Feedback Compensation 3 dB SS Output Noise Total Output Noise Network Values Network Values Bandwidth Slew Rate Peaking AD8099 Only Including Resistors Gain Package Re Re Rs Ce Re Cc C1 MHz V us dB nV VHz nV VHz 1 2 SOIC 250 250 50 1 5 50 4 1 5 440 700 515 0 3 3 1 2 1 4 2 CSP 250 250 50 0 5 50 5 2 700 475 3 2 2 1 4 1 CSP 250 250 50 1 0 50 5 2 420 475 0 8 2 1 4 5 CSP SOIC 499 124 20 0 5 50 1 0 510 735 1 4 4 9 8 6 10 CSP SOIC 499 54 0 5 0 550 1350 0 8 9 6 13 3 20 CSP SOIC 499 26 0 0 160 1450 0 19 23 3 CIRCUIT CONFIGURATIONS Figure 60 through Figure 66 show typical schematics for the AD8099 in various gain configurations Table 4 data was collected using the schematics shown in Figure 60 through Figure 66 Resistor RI as shown in Figure 60 through Figure 66 04511 0 054 Figure 61 Amplifier Configuration for SOIC Package Gain 2 04511 0 116 is the test eguipment termination resistor RI is not reguired for normal operation but is shown in the schematics for completeness 04511 0 108 04511 0 053
17. ANALOG DEVICES FEATURES Ultralow noise 0 95 nV Hz 2 6 pA VHz Ultralow distortion 2 4 harmonicR 1kQ G 42 92 dB 10 MHz 3 harmonic RB 1 kO G 2 105 dB 10 MHz High speed GBWP 3 8 GHz 3 dB bandwidth 700 MHz G 2 550 MHz G 10 Slew rate 475 V s G 2 1350 V us G 10 New pinout Custom external compensation gain range 1 2 to 10 Supply current 15 mA Offset voltage 0 5 mV max Wide supply voltage range 5 Vto 12V GENERAL DESCRIPTION The AD8099 is an ultralow noise 0 95 nV VHz and distortion 92 dBc 10 MHz voltage feedback op amp the combination of which make it ideal for 16 and 18 bit systems The AD8099 features a new highly linear low noise input stage that increases the full power bandwidth FPBW at low gains with high slew rates ADTs proprietary next generation XFCB process enables such high performance amplifiers with relatively low power The AD8099 features external compensation which lets the user set the gain bandwidth product External compensation allows gains from 2 to 10 with minimal trade off in band width The AD8099 also features an extremely high slew rate of 1350 V s giving the designer flexibility to use the entire dynamic range without trading off bandwidth or distortion The AD8099 settles to 0 1 in 18 ns and recovers from overdrive in 50 ns The AD8099 drives 100 02 loads at breakthrough performance levels with only 15 mA of supply current With the wid
18. ES SECOND HARMONICS SOLID LINES SECOND HARMONICS DOTTED LINES THIRD HARMONICS 2 120 DOTTED LINES THIRD HARMONICS 2 0 1 1 0 10 0 i 0 1 1 0 10 0 i FREQUENCV MHz Ki FREQUENCV MHz Z Figure 29 Harmonic Distortion vs Freguency and Supply Voltage SOIC Figure 32 Harmonic Distortion vs Freguency for Various Supplies CSP G G a a 2 e z z ej o E E 7 7 S S 9 9 a a S z z G G z z lt lt ka ka SOLID LINE SECOND HARMONIC SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC DOTTED LINE THIRD HARMONIC 1 2 3 4 5 6 7 1 2 3 4 5 6 r OUTPUT AMPLITUDE V p p E OUTPUT AMPLITUDE V p p z Figure 30 Harmonic Distortion vs Output Amplitude SOIC Figure 33 Harmonic Distortion vs Output Amplitude CSP 40 50 f 10MHz G m m a a z z o H H 7 e fe fe H E 9 9 a a 2 z z o o z z r lt lt lt x SOLID LINE SECOND HARMONIC SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC DOTTED LINE THIRD HARMONIC 3 4 5 6 7 OUTPUT AMPLITUDE V p p Figure 31 Harmonic Distortion vs Output Amplitude SOIC 1 2 3 4 5 6 7 OUTPUT AMPLITUDE V p p 04511 A 017 04511 A 021 Figure 34 Harmonic Distortion vs Output Amplitude CSP Rev B Page 10 of 28 AD8099 0 20 10pF 200 RSNUB 10pF 200 RSNUB 0 15 0 10 s g
19. L 1kQ d e 1 10 100 1000 3 1 10 100 1000 FREQUENCV MHz 2 FREQUENCY MHz 3 Figure 7 Small Signal Frequency Response for Various Temperatures SOIC Figure 10 Small Signal Frequency Response for Various Temperatures CSP Rev B Page 6 of 28 AD8099 A 2 5 5pF Sel x ba get 19 Vs 5V 7 k 80 45 1 d 1 18 De 1 70 60 my EI a 1 CT a i s 60 75 Z 16 d L B E h 11 z 5 9 G 15 B t 3 EI Al fi 40 4105 lt o a x o 14 1pF SOIC Q a 30 120 A a 13 1 o u l o 2 e l H 2 135 3 a 1pF CSP 1 o D 11 10 150 jil U 10 5pF SOIC I 163 TAH Ni UNCOMPENSATED 9 410 180 1 10 100 1000 0 001 0 01 0 1 1 0 10 100 1000 04511 0 104 04511 0 080 FREQUENCV MHz FREQUENCV MHz Figure 11 Small Signal Frequency Response for Various Capacitive Loads Figure 14 Open Loop Frequency Response NORMALIZED CLOSED LOOP GAIN dB NORMALIZED CLOSED LOOP GAIN dB Vg LBV Vour 2V pp RLoap 1kQ 1 10 100 1000 FREQUENCV MHz FREQUENCV MHz Figure 12 Large Signal Frequencv Response for Various Gains SOIC Figure 15 La
20. P Figure 41 Large Signal Transient Response vs Supplv Voltage CSP OUTPUT VOLTAGE V OUTPUT INPUT VOLTAGE V 04511 0 051 70 10 20 30 40 50 TIME ns TIME ns 04511 0 118 Figure 42 Large Signal Frequencv Response vs Supplv Voltage SOIC Figure 45 Short Term Settling Time SOIC 0 30 0 20 s ta 0 10 u lt g H fe a N 0 o l gt gt a L gt E D K 5 5 0 10 o E 8 0 20 Ri 1kQ 1000 gl 5 l 0 30 8 0 10 20 30 40 50 2 0 50 100 150 200 250 300 350 400 450 500 TIME ns TIME us Z Figure 43 Large Signal Transient Response for Various Supply Voltages and Figure 46 Long Term Settling Time Load Resistances SOIC and CSP Rev B Page 12 of 28 INPUT CURRENT NOISE pAwHz COMMON MODE REJECTION dB INPUT VOLTAGE NOISE nVWHz 0 1 1 0 10 100 1000 FREQUENCV MHz Figure 47 Common Mode Rejection vs Frequencv 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz Figure 48 Input Current Noise vs Frequency DISABLE Open 1000 0 1 I 1 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY Hz
21. Ww u 0 05 G 6 lt lt 5 a o o o gt gt 5 5 a 0 05 E E gt gt o 0 10 0 15 8 20 S TIME ns S TIME ns S Figure 35 Small Signal Transient Response for Various Capacitive Loads Figure 38 Small Signal Transient Response for Various Capacitive Loads SOIC CSP A 0 15 Vs 2 5V CSP a Vs 5 0V AND 2 5V CSP 0 10 0 05 LU lt a 9 gt S a A an 2 o 0 10 L 4 e Ve AND 2 5V 15 S 8 0 10 20 30 40 so 0 10 20 30 40 50 7 TIME ns E TIME ns 3 Figure 36 Small Signal Transient Response for Various Supplv Voltages Figure 39 Small Signal Transient Response for Various Supplv Voltages 8 Z lt e H 8 HE gt 5 5 a a E E 2 gt o o 0 100 200 300 400 500 600 700 800 900 1000 i S TIME ns Z TIME ns Z Figure 37 Output Overdrive Recoverv for Various Resistive Loads Figure 40 Disable Enable Switching Speed Rev B Page 11 of 28 AD8099 1 5 0 3 OUTPUT 1 0 H AO EET 0 2 s i INPUT s S 05 0 1 H a G 5 i a fe 1 Z i 8 ok 0 C a l 2 E d ERROR B 05H 0 1 gt a H o E H 5 o 41 0 k 0 2 G 2 Rioap 1kQ Vs 5V M 1 5 0 3 0 5 10 15 20 25 30 35 40 45 E 04511 0 106 TIME ns TIME ns Figure 44 Short Term Settling Time CS
22. bility The value of Rs should be kept to 50 Q or lower to maintain low noise performance At higher gains Rs may be reduced or even eliminated Typical range is 0Qto50 Q Cc The compensation capacitor decreases the open loop gain at higher frequencies where the phase is degrading By decreas ing the open loop gain here the phase margin is increased and the amplifier is stabilized Typical range is 0 pF to 5 pE The value of Cc is gain dependent Rc The series lead inductance of the package and the com pensation capacitance Cc forms a series resonant circuit Rc dampens this resonance and prevents oscillations The recommended value of Rc is 50 0 for a closed loop gain of 2 This resistor introduces a zero in the open loop response and must be kept low so that this zero occurs at a higher freguency The purpose of the compensation network is to decrease the open loop gain If the resistance becomes too large the gain will be reduced to the resistor value and not necessarily to 0 0 which is what a single capacitor would do over freguency Typical value range is 0 Q to 50 Q C1 Tolower the impedance of Rc CI is placed in parallel with Rc C1 is not required but greatly reduces peaking at low closed loop gains The typical value range is 0 pF to 2 pF C2 and C3 Bypass capacitors are connected between both supplies for optimum distortion and PSRR performance These capacitors should be placed as close as possible to the supply
23. ble ground and power planes should be used Ground and power planes reduce the resistance and inductance of the power supply feeds and ground returns If multiple planes are used they should be stitched together with multiple vias The returns for the input output terminations bypass capacitors and Re should all be kept as close to the AD8099 as possible Ground vias should be placed at the very end of the component mounting pad to provide a solid ground return The output load ground and the bypass capacitor grounds should be returned to a common point on the ground plane to minimize parasitic inductance and improve distortion performance The AD8099 packages feature an exposed paddle For optimum performance solder this paddle to ground For more information on PCB layout and design considerations refer to section 7 2 of the 2002 Analog Devices Op Amp Applications book Power Supply Bypassing The AD8099 power supply bypassing has been optimized for each gain configuration as shown in Figure 60 through Figure 66 in the Circuit Configurations section The values shown should be used when possible Bypassing is critical for stability frequency response distortion and PSRR performance The 0 1 uF capacitors shown in Figure 60 through Figure 66 should be as close to the supply pins of the AD8099 as possible and the electrolytic capacitors beside them Component Selection Smaller components less than 1206 SMT case size offer sma
24. e supply voltage range 5 V to 12 V low offset voltage 0 1 mV typ wide bandwidth 700 MHz for G 2 and a GBWP up to 3 8 GHz the AD8099 is designed to work in a wide variety of applications Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Ultralow Distortion High Speed 0 95 nV NHz Voltage Noise Op Amp AD8099 APPLICATIONS Pre amplifiers Receivers Instrumentation Filters IF and baseband amplifiers A to D drivers DAC buffers Optical electronics CONNECTION DIAGRAMS FEEDBACK 04511 0 001 U lt a o e Figure 1 8 Lead CSP CP 8 The AD8099 is available in a 3 mm x 3 mm lead frame chip scale package LFCSP with a new pinout that is specificallv optimized for high performance high speed amplifiers The new LFCSP package and pinout enable the breakthrough performance that previouslv was not achievable with amplifiers The AD8099 is rated to work over the extended industrial temperature range 40 C to 125 C 4 9 G 2 Vour 2V p p 50 ye 5V Ri 1
25. ential Input Voltage 1 8V Differential Input Current 10mA Storage Temperature 65 C to 125 C Operating Temperature Range 40 C to 125 C Lead Temperature Range Soldering 10 sec 300 C Junction Temperature 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8099 package is limited by the associated rise in junction temperature Tj on the die The plastic encapsulating the die will locally reach the junction temperature At approximately 150 C which is the glass transition temperature the plastic will change its properties Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die permanently shifting the parametric performance of the AD8099 Exceeding a junction temperature of 150 C for an extended period can result in changes in silicon devices potentially causing failure The still air thermal properties of the package and PCB Dr the ambient temperature TA and the total power dissipated in the package Po determine the junction temperature of the die The junc
26. he expressions noise spectral density which is generally expressed in nV VHz is equivalent to the noise in a 1 Hz bandwidth The noise model shown in Figure 69 has six individual noise sources the Johnson noise of the three resistors the op amp voltage noise and the current noise in each input of the amplifier Each noise source has its own contribution to the noise at the output Noise is generally specified RTI referred to input but it is often simpler to calculate the noise referred to the output RTO and then divide by the noise gain to obtain the RTI noise All resistors have a Johnson noise of V 4kBTR where k is Boltzmann s Constant 1 38 x 1075 J K T is the absolute temperature in Kelvin B is the bandwidth in Hz and R is the resistance in ohms A simple relationship which is easy to remember is that a 50 resistor generates a Johnson noise of 1 nV VHZ at 25 C The AD8099 amplifier has roughly the same equivalent noise as a 50 0 resistor Rev B Page 20 of 28 R2 GAIN FROM _ A TO OUTPUT 7 NOISE GAIN R2 NG 1 01 O Vout GAIN FROM _R2 B TO OUTPUT Ri VZ 4kTR3 aam Si a RTI NOISE Iy42R32 In 2 ER Raj aktR2 Si sie 04511 0 070 RTO NOISE NG x RTI NOISE Figure 69 Op Amp Noise Analysis Model In applications where noise sensitivity is critical care must be taken not to introduce other significant noise sources to the amplifier Each resistor
27. ingle supply operation with R referenced to Vs worst case is Vour Vs 2 Airflow will increase heat dissipation effectively reducing a Also more metal directly in contact with the package leads from metal traces through holes ground and power planes will reduce the Du Soldering the exposed paddle to the ground plane significantly reduces the overall thermal resistance of the package Care must be taken to minimize parasitic capaci tances at the input leads of high speed op amps as discussed in the PCB Layout section Figure 4 shows the maximum safe power dissipation in the package versus the ambient temperature for the exposed paddle e pad SOIC 8 70 C W and CSP 70 C W packages on a JEDEC standard 4 layer board Dr values are approximations 4 0 3 5 3 0 2 5 2 0 1 5 LFCSP AND SOIC 1 0 MAXIMUM POWER DISSIPATION Watts 40 20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE C 04511 0 115 Figure 4 Maximum Power Dissipation Ee ESD SENSITIVE DEVICE Rev B Page 5 of 28 AD8099 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions Vs 5 V Ta 25 C Ri 1 kQ tied to ground unless otherwise noted Refer to Figure 63 through Figure 66 for component values and gain configurations
28. is a noise source Attention to the following areas is critical to maintain low noise performance design layout and component selection A summary of noise performance for the amplifier and associated resistors can be seen in Table 4 INPUT BIAS CURRENT AND DC OFFSET In high noise gain configurations the effects of output offset voltage can be significant even with low input bias currents and input offset voltages Figure 70 shows a comprehensive offset voltage model which can be used to determine the referred to output RTO offset voltage of the amplifier or referred to input RTI offset voltage R2 GAINFROM _ A TO OUTPUT 7 NOISE GAIN R2 NG 1 57 Vout GAIN FROM R2 B TO OUTPUT RI OFFSET RTO Vos AT lg x R3 ji Ra Ip x R2 R1 x R2 e OFFSET RTI Vos lg x R3 Ig RT R2 FOR BIAS CURRENT CANCELLATION 04511 0 071 OFFSET RTI lt Vas IF Ip Ig AND R3 Ii S Fa R2 Figure 70 Op Amp Total Offset Voltage Model AD8099 For RTO calculations the input offset voltage and the voltage generated by the bias current flowing through R3 are multiplied by the noise gain of the amplifier The voltage generated by Is through R2 is summed together with the previous offset voltages to arrive at a final output offset voltage The offset voltage can also be referred to the input RTI by dividing the calculated output offset voltage bv the noise gain As seen in Figure 70
29. kQ Wi K sl ei IR 110 Gah a oo e HARMONIC DISTORTION dBc SOLID LINE SECOND HARMONIC DOTTED LINE THIRD HARMONIC 0 1 1 0 10 0 FREGUENCY MHz 04511 A 013 Figure 3 Harmonic Distortion vs Frequencv and Gain SOIC One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 6 2004 Analog Devices Inc All rights reserved 8 DISABLE Figure 2 8 Lead SOIC ED RD 8 04511 0 002 AD8099 TABLE OF CONTENTS Specifications eege EEN 3 Specifications with 5 V Supply EEN 3 Specifications with 5 V Supply EEN 4 Absolute Maximum Ratings sese 5 Maximum Power Dissipation En 5 EE Eege 5 Typical Performance Characteristics een 6 Theory of Operation ENEE 15 e i lo E E 16 Using the ADSO99 iis cisssscsessisscnessas ssonestsernsonsssvoveasssveneadicvevsnsseie s 16 Gircuit COPOnEHtS siseses sseni iessen sanna 16 REVISION HISTORY 6 04 Data Sheet changed from REV A to REV B Change to General Description esses Changes to Maximum Power Dissipation section Changes to Applications section EE Changes to Table Z siiis ieiti oris sieer N Changes to Ordering Guide ue 1 04 Data Sheet changed from REV 0 to REV A Inserted new Figure 3 ssmsememenenzzonenzannnnnzannnzzonnnzzonnenezza 1 Changes to Specifications ENEE 3 Inserted new Figures 22 to 34
30. le gain stage with a unity gain output buffer fabricated in Analog Devices extra fast complimentary bipolar process XFCB The AD8099 has 85 dB of open loop gain and maintains precision specifications such as CMRR PSRR Vos and AVos AT to levels that are normally associated with topologies having two or more gain stages 04511 0 060 Figure 58 AD8099 Topology The AD8099 can be externally compensated down to a gain of 2 through the use of an RC network Above gains of 15 no exter nal compensation network is required To realize the full gain bandwidth product of the AD8099 no PCB trace should be connected to or within close proximity of the external compen sation pin for the lowest possible capacitance External compensation allows the user to optimize the closed loop response for minimal peaking while increasing the gain bandwidth product in higher gains lowering distortion errors that are normally more prominent with internally compensated parts in higher gains For a fixed gain bandwidth wideband distortion products would normally increase by 6 dB going from a closed loop gain of 2 to 4 Increasing the gain bandwidth product of the AD8099 eliminates this effect with increasing closed loop gain The AD8099 is available in both a SOIC and an LFCSP each of which has a thermal pad for lower operating temperature To help avoid this pad in board layout both packages have an extra output pin on the opposite side of the package
31. led within 0 7 V of the positive supply an optional input bias current cancellation circuit is turned on which lowers the input bias current to less than 200 nA In this mode the user can drive the AD8099 with a high dc source impedance and still maintain minimal output referred offset without having to use impedance matching techniques In addition the AD8099 can be ac coupled while setting the bias point on the input with a high dc impedance network The input bias current cancellation circuit will double the input referred current noise but this effect is minimal as long as wideband impedance is kept low see Figure 48 and Figure 51 A pair of internally connected diodes limits the differential voltage between the noninverting input and the inverting input of the AD8099 Each set of diodes has two series diodes which are connected in anti parallel This limits the differential voltage between the inputs to approximately 1 8 V All of the AD8099 pins are ESD protected with voltage limiting diodes connected between both rails The protection diodes can handle 5 mA of steady state current Currents should be limited to 5 mA or less through the use of a series limiting resistor Rev B Page 15 of 28 AD8099 APPLICATIONS USING THE AD8099 The AD8099 offers unrivaled noise and distortion performance in low signal gain configurations In low gain configurations less than15 the AD8099 requires external compensation The amount of gai
32. ller mounting pads which have less parasitics and allow for a more compact layout It is critical for optimum performance that high quality tight tolerance where critical and low drift compo nents be used For example tight tolerance and low drift is critical in the selection of the feedback capacitor used in Figure 60 The feedback compensation capacitor in Figure 60 is 1 5pE This capacitor should be specified with NPO material NPO material typically has a 30 ppm C change over 55 C to 125 C temperature range For a 100 C change this would result in a 4 5 fF change in capacitance compared to an X7R material which would result in a 0 23 pF change a 15 change from the nominal value This could introduce excessive peaking as shown in Figure 68 Cr vs Frequency Response DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices is committed to the design process by providing technical support and online design tools ADI offers technical support via free evaluation boards sample ICs SPICE models interactive evaluation tools application notes phone and email support all available at www analog com Rev B Page 23 of 28 AD8099 04511 A 001 04511 A 001 Figure 73 CSP Evaluation Board Artwork Evaluation Boards There are four different evaluation boards available as shown in Table 7 and an Application Note AN 720 that explains the use of the evaluation boards Table 7 Evaluation Board Selection Guide
33. n and performance needed will determine the compensation network Understanding the subtleties of the AD8099 gives the user insight on how to exact its peak performance Use the component values and circuit configurations shown in the Applications section as starting points for designs Specific circuit applications will dictate the final configuration and value of your components CIRCUIT COMPONENTS The circuit components are referenced in Figure 59 the recommended noninverting circuit schematic for the AD8099 See Table 4 for typical component values and performance data Cr Vs c2 O Vour 04511 0 061 Figure 59 Wideband Noninverting Gain Configuration SOIC Rr and Ra The feedback resistor and the gain set resistor determine the noise gain of the amplifier tvpical Rr values range from 250 Q to 499 Q Cr Creates a zero in the loop response to compensate the pole created by the input capacitance including stray capacitance and the feedback resistor Rr Cr helps reduce high frequency peaking and ringing in the closed loop response Typical range is 0 5 pF to 1 5 pF for evaluation circuits used here R1 This resistor terminates the input of the amplifier to the source resistance of the signal source typically 50 2 This is application specific and not always reguired Rs Many high speed amplifiers in low gain configurations reguire that the input stage be terminated into a nominal impedance to maintain sta
34. o ensure optimal circuit performance The concepts of layout grounding and component placement llustrated in Figure 72 and Figure 73 also apply to inverting configurations For scale the boards are 2 x 2 Parasitics The area surrounding the compensation pin is very sensitive to parasitic capacitance To realize the full gain bandwidth product of the AD8099 there should be no trace connected to or within close proximity of the external compensation pin for the lowest possible capacitance When compensation is required the traces to the compensation pin the negative supply and the interconnect between components i e Cc CI and Rc in Figure 59 should be made as wide as possible to minimize inductance All ground and power planes under the pins of the AD8099 should be cleared of copper to prevent parasitic capacitance between the input and output pins to ground A single mount ing pad on a SOIC footprint can add as much as 0 2 pF of capacitance to ground as a result of not clearing the ground or power plane under the AD8099 pins Parasitic capacitance can cause peaking and instability and should be minimized to ensure proper operation The new pinout of the AD8099 reduces the distance between the output and the inverting input of the amplifier This helps to minimize the parasitic inductance and capacitance of the feedback path which in turn reduces ringing and second harmonic distortion AD8099 Grounding When possi
35. rge Signal Freguency Response for Various Gains CSP T A Z 3 z z a a G o S 3 E 9 S P o 9 9 o o 2 1 10 100 FREQUENCV MHz Z FREQUENCV MHz Figure 13 0 1 dB Flatness SOIC Figure 16 0 1 dB Flatness CSP Rev B Page 7 of 28 AD8099 15 14 13 g r Z z z a 1 lt S 6 a o w 5 9 E U U 9 8 7 O fe o o 7 6 G 2 5 Vg 5V 5 Vout 2V p p i g 8 1 10 100 1000 1 10 100 1000 FREQUENCV MHz 3 FREQUENCV MHz 3 Figure 17 Large Signal Frequency Response for Various Load Resistances Figure 20 Large Signal Frequency Response for Various Supply Voltages 100 1 00 0 9 G 2 RL 1kQ 20 Vs 5V ioo Vos ON 30 fel
36. tion temperature can be calculated as T T P x The power dissipated in the package Pp is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs The quiescent power is the voltage between the supply pins Vs times the quiescent current Is Assuming the load Ri is referenced to midsupply the total drive power is Vs 2 x Iour some of which is dissipated in the package and some in the load Vour x Iour ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readilv accumulate on the human bodv and test equipment and can discharge without detection Although this product features proprietarv ESD protection circuitrv permanent damage mav occur on devices subjected to high energv electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionalitv AD8099 The difference between the total drive power and the load power is the drive power dissipated in the package Pp Quiescent Power Total Drive Power Load Power V V V P V a jal Sy ax OUT D SS 2 R RMS output voltages should be considered If R is referenced to Vs as in single supply operation then the total drive power is Vs x Tour If the rms signal levels are indeterminate consider the worst case when Vour Vs 4 for Ri to midsupply V 4 P V x1I L In s
37. width for 0 1 dB Flatness SOIC CSP G 2 Vour 0 2 V p p 34 25 MHz Slew Rate G 10 Vout 6 V Step 1120 1350 V us G 2 Vout 2 V Step 435 470 V us Settling Time to 0 190 G 2 Vout 2 V Step 18 ns NOISE DISTORTION PERFORMANCE Harmonic Distortion dBc HD2 HD3 fc 500 kHz Vour 2 V p p G 10 102 111 dBc fc 10 MHz Vout 2 V p p G 10 84 92 dBc Input Voltage Noise f 100 kHz 0 95 nV VHz Input Current Noise f 100 kHz DISABLE pin floating 2 6 pA Hz f 100 kHz DISABLE pin Vs 5 2 pA VHz DC PERFORMANCE Input Offset Voltage 0 1 0 5 mV Input Offset Voltage Drift 2 3 UNC Input Bias Current DISABLE pin floating 6 13 LA DISABLE pin Vs 0 1 2 pA Input Bias Current Drift 3 NA C Input Bias Offset Current 0 06 1 HA Open Loop Gain 82 85 dB INPUT CHARACTERISTICS Input Resistance Differential mode 4 ko Common mode 10 MO Input Capacitance 2 pF Input Common Mode Voltage Range 3 7 to 3 7 V Common Mode Rejection Ratio Vem 2 5 V 98 105 dB DISABLE PIN DISABLE Input Voltage Output disabled lt 2 4 V Turn Off Time 5090 of DISABLE to lt 10 of final Vour 105 ns Vn 0 5V G 42 Turn On Time 50 of DISABLE to lt 10 of final Vout 39 ns Vn 0 5V G 42 Enable Pin Leakage Current DISABLE 5 V 17 21 pA DISABLE Pin Leakage Current DISABLE 5 V 35 44 HA OUTPUT CHARACTERISTICS Output Overdrive Recoverv Time Rise Fall Vin 2 5 V to 2 5 V G 2 30 50 ns Output Voltage Swing RL 1000 3 4 to 3 5 3 6to 3 7

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