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ANALOG DEVICES ADA4896-2/ADA4897-1/ADA4897-2 Manual

1. 0 3 V to 0 7 V 96 120 dB DISABLE PIN ADA4897 1 ADA4897 2 DISABLE Voltage Enabled Vs 0 5 V Disabled lt Vs 2 V Input Current Enabled DISABLE 3 V 1 2 Disabled DISABLE 0V 15 uA Switching Speed Enabled 0 25 us Disabled 12 us Rev B Page 7 of 28 ADA4896 2 ADA4897 1 ADA4897 2 ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating Supply Voltage 11V Power Dissipation See Figure 3 Common Mode Input Voltage Vs 0 7 V to Vs 07V Differential Input Voltage 0 7V Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 125 C Lead Temperature Soldering 10 sec 300 C Junction Temperature 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE Oya is specified for the worst case conditions that is Oja is specified for a device soldered in a circuit board for surface mount packages Table 7 lists the for the ADA4896 2 ADAA897 1 ADA4897 2 Table 7 Thermal Resistance Package Type Osa Unit 8 Lead Dual MSOP ADA4896 2 222 C W 8 Lead Dual LFCSP ADA4896 2 61 C W 8 L
2. V x 1 In single supply operation with Ri referenced to Vs worst case is Vour Vs 2 Airflow increases heat dissipation effectively reducing Oya Also more metal directly in contact with the package leads and exposed paddle from metal traces through holes ground and power planes reduces 054 Figure 3 shows the maximum safe power dissipation in the package vs the ambient temperature on a JEDEC standard 4 layer board Oja values are approximations 3 5 3 0 MAXIMUM POWER DISSIPATION W 0 45 35 25 15 5 5 15 25 35 45 55 65 75 85 95 105 115 125 AMBIENT TEMPERATURE C Figure 3 Maximum Power Dissipation vs Temperature for a 4 Layer Board 2 8 n i 0 ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage dy 4 may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 8 of 28 ADA4896 2 ADA4897 1 ADA4897 2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADA4896 2 OUT1 1 Vs IN1 2 OUT2 ADA4896 2 IN1 3 IN2 Vs 4 IN2 NOTES 1 THE EXPOSED PAD CAN BE 8 CONNECTED TO GND OR 8 E POWER PLANES OR IT CAN S TOP VIEW BE LEFT FLOATING
3. VOUT seror B v Vom V Venom j Vour eater Ry 4 OFFSET yom CMRR PSRR A R G where VorrseTyo 1 the offset voltage at the specified supply voltage which is measured with the input and output at midsupply Vcu is the common mode voltage Vp is the power supply voltage Vonom is the specified power supply voltage CMRR is the common mode rejection ratio PSRR is the power supply rejection ratio A is the dc open loop gain The output error due to the input currents can be estimated as R R Vour nog Rell Re x c x xI R x h xI 5 G BIAS CURRENT CANCELLATION To cancel the output voltage error due to unmatched bias currents at the inputs Rep and Rex can be used see Figure 47 Rc Rs Rep 09447 048 Figure 47 Using Ree and Ren to Cancel Bias Current Error To compensate for the unmatched bias currents at the two inputs set Rs and Ren as shown in Table 11 Table 11 Setting Rss and Rs to Cancel Bias Current Errors Value of Value of Rer Q Value of Ren Greater Than Rs Re Rc Rs 0 Less Than Rs 0 Rs Re Re Table 12 shows sample values for Ree and Ren when Ri Rc gt Rs and when R Rc lt Rs Table 12 Examples of Rex and Rep Settings Gain Rr Q Rep Ren 2 249 249 50 74 5 0 10 249 27 4 50 0 25 3 Rev B Page 18 of 28 ADA4896 2 ADA4897 1 ADA4897 2 NOISE CONSIDERA
4. 85 4 98 V 1000 4 8 4 88 V Negative 1 0 15 0 014 V R 21000 0 2 0 08 V Output Current SFDR 45 dBc 70 mA Short Circuit Current Sinking sourcing 125 mA Capacitive Load Drive 30 overshoot G 2 39 pF POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2 6 2 8 2 9 mA DISABLE 0V 0 05 0 18 mA Power Supply Rejection Ratio PSRR Positive Vs 4 5 V to 5 5 V Vs 0 V 96 123 dB Negative Vs 5 V Vs 2 0 5V to 40 5 V 96 121 dB DISABLE PIN ADA4897 1 ADA4897 2 DISABLE Voltage Enabled Vs 0 5 V Disabled lt Vs 2 V Input Current Enabled DISABLE 45 V 1 2 Disabled DISABLE 0V 20 uA Switching Speed Enabled 0 25 us Disabled 12 us Rev B Page 5 of 28 ADA4896 2 ADA4897 1 ADA4897 2 3 V SUPPLY Ta 25 C G 1 Ri 1 to midsupply unless otherwise noted Table 5 Parameter Test Conditions Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vour 0 02 V p p 230 MHz G 1 Vout 1 V p p 45 MHz G 2 Vour 0 02 V p p 90 MHz Bandwidth for 0 1 dB Flatness G 2 Vout 2 V p p R 2 100 Q 7 MHz Slew Rate G 2 Vour 1 V step 85 V us Settling Time to 0 196 G 2 Vout 2 V step 45 ns Settling Time to 0 01 G 2 Vout 2 V step 96 ns NOISE HARMONIC PERFORMANCE Harmonic Distortion SFDR fc 100 kHz Vour 2 V p p G 2 105 dBc fc 1 MHz Vout 1 V p p G 1 84 dBc fc 2 MHz Vout 1 V p p
5. Changes to Table 7 and Figure 2 8 Changes to Figure 4 Table 8 and Table 9 9 Added Figure 8 and Table 10 Renumbered Sequentially 10 Changed Summary Statement for Typical Performance Characteristics Section 11 Changes to Figure 18 ENE 12 Change to Figure K 12 Theory of Opetation e Ea ER Re RADAR 17 Atmplifier Description ette eatis 17 Input 17 Disable Operation 4 ret a a 17 18 Bias Current Cancellation see 18 Noise Considerations tentent 19 Capacitance Drive 19 Applications Information seeeeeeteeetns 20 Typical Performance 8 20 Low Noise Gain Selectable Amplifier 21 Medical Ultrasound Applications sss 22 Layout Considerations sees 24 Outline Dimensions wee 25 Ordering Guilde 27 Change to Figure 26 Moved Figure 26 x Changes to Fig re 37 ita ne a HE EDI iens Changes to Amplifier Description Section Disable Operation Section Figure 44 and Figure 45 sss 17 Added Bias Current Cancellation Section Figure 47 Table 11 and Table 12 eerte 18 Changes ito Table 13 epe pU e RUE 20 Changes to Low Noise Gain Selectable Ampli
6. G 1 77 dBc fc 5 MHz Vour 1 V p p G 1 60 dBc Input Voltage Noise 109 2 3 nV 4Hz f 100 kHz 1 Input Current Noise f 10Hz 11 pA VHz f 100 kHz 2 8 pA VHz 0 1 Hz to 10 Hz Noise G 4101 Rrz 1 100 99 nV p p DC PERFORMANCE Input Offset Voltage 500 30 500 Input Offset Voltage Drift 0 2 yv C Input Bias Current 17 11 4 uA Input Bias Current Drift 3 Input Bias Offset Current 0 6 0 02 10 6 uA Open Loop Gain Vour 0 5 V to 2 5 V 95 108 dB INPUT CHARACTERISTICS Input Resistance Common Mode 10 Differential 10 Input Capacitance Common Mode 3 pF Differential 11 pF Input Common Mode Voltage Range 0 1 to 2 1 V Common Mode Rejection Ratio Vou 1 1 V to 1 9V 90 124 dB CMRR OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VN 20Vto3V G2 42 83 ns Output Voltage Swing Positive 1 2 85 2 97 V R 21000 2 8 2 92 V Negative 1 0 15 0 01 V R 2 1000 0 2 0 05 V Output Current SFDR 45 dBc 60 mA Short Circuit Current Sinking sourcing 120 mA Capacitive Load Drive 30 overshoot G 2 39 pF POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2 5 2 7 2 9 mA DISABLE 20V 0 035 0 15 mA Rev B Page 6 of 28 ADA4896 2 ADA4897 1 ADA4897 2 Parameter Test Conditions Comments Min Typ Max Unit Power Supply Rejection Ratio PSRR Positive 4Vs 2 7 V to 3 7 V Vs 0V 96 121 dB Negative TVs 3 V Vs
7. Not to Scale Figure 4 8 Lead LFCSP Pin Configuration Figure 5 8 Lead MSOP Pin Configuration Table 8 ADA4896 2 Pin Function Descriptions Pin No Mnemonic Description 1 OUT1 Output 1 2 IN1 Inverting Input 1 3 IN1 Noninverting Input 1 4 Vs Negative Supply 5 IN2 Noninverting Input 2 6 2 Inverting Input 2 7 OUT2 Output 2 8 Vs Positive Supply EPAD Exposed Pad LFCSP Only The exposed pad can be connected to GND or power planes or it can be left floating OUT El Vs Vs 2 5 DISABLE NC NO CONNECT DO NOT 3 E IN 5 CONNECT THIS PIN 8 ADA4897 1 i Figure 6 8 Lead SOIC Pin Configuration Figure 7 6 Lead SOT 23 Pin Configuration Table 9 ADA4897 1 Pin Function Descriptions Pin No SOIC SOT 23 Mnemonic Description 1 5 N A NC No Connect Do not connect to these pins 2 4 IN Inverting Input 3 3 Noninverting Input 4 2 Vs Negative Supply 6 1 OUT Output 7 6 Vs Positive Supply 8 5 DISABLE Disable Rev B Page 9 of 28 ADA4896 2 ADA4897 1 ADA4897 2 DISABLE1 5 ADA4897 2 6 DISABLE2 09447 069 Figure 8 10 Lead MSOP Pin Configuration Table 10 ADA4897 2 Pin Function Descriptions Pin No Mnemonic Description 1 OUT1 Output 1 2 IN1 Inverting Input 1 3 IN1 Noninverting Input 1 4 Vs Negative Supply 5 DISABLE1 Disable 1 6 DISABLE2 Disable 2 7 IN2 Noninverting Input 2 8 2 I
8. R7 40 C to 125 C 8 Lead SOIC R 8 1 000 ADA4897 1ARZ RL 40 C to 125 C 8 Lead SOIC_N R 8 2 500 ADA4897 1ARJZ R2 40 C to 125 C 6 Lead SOT 23 RJ 6 250 H2K ADA4897 1ARJZ R7 40 C to 125 C 6 Lead SOT 23 RJ 6 3 000 H2K ADA4897 1ARJZ RL 40 C to 125 C 6 Lead SOT 23 RJ 6 10 000 H2K ADA4897 1AR EBZ Evaluation Board for the 8 Lead SOIC_N ADA4897 1ARJ EBZ Evaluation Board for the 6 Lead SOT 23 ADA4897 2ARMZ 40 C to 125 C 10 Lead MSOP RM 10 50 H2N ADA4897 2ARMZ R7 40 C to 125 C 10 Lead MSOP RM 10 1 000 H2N ADA4897 2ARMZ RL 40 C to 125 C 10 Lead MSOP RM 10 3 000 H2N ADA4897 2ARM EBZ Evaluation Board for the 10 Lead MSOP Z RoHS Compliant Part Rev B Page 27 of 28 ADA4896 2 ADA4897 1 ADA4897 2 NOTES 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners DEVICES Rev B Page 28 of 28
9. Various Supplies G 1 100 6 2 Vout 20mV p p TIME 100ns DIV 10 E E i a d 10 9 E 5 i n t E c 2 5 5 o 10 3 i 1 1 10 100 1k 10k 100k M 5M 8 FREQUENCY Hz 3 Figure 23 Current Noise vs Frequency Figure 26 Small Signal Transient Response for Various Supplies G 2 Rev B Page 13 of 28 ADA4896 2 ADA4897 1 ADA4897 2 z Vs 55 C 39pF isi TIME 100ns DIV Vg 5V G 2 TIME 100ns DIV e OUTPUT VOLTAGE mV e L 5 INPUT AND OUTPUT VOLTAGE V 09447 039 09447 051 Figure 27 Small Signal Transient Response for Various Capacitive Loads Figure 30 Output Overdrive Recovery Time Vs 45V 250 Vour 2V p p TIME 100ns DIV 200 e a 150 100 OUTPUT VOLTAGE V 50 AVERAGE OUTPUT OVERLOAD RECOVERY TIME ns 09447 009 09447 055 OVERLOAD DURATION ns Figure 28 Large Signal Transient Response G 1 and G 42 Figure 31 Average Output Overload Recovery Time vs Overload Duration Vs 45V G 1 TIME 100ns DIV SLEW RATE Vius INPUT AND OUTPUT VOLTAGE V 0944
10. 0 s Vs 5V G 1 2 625 gs Vin 1V 0 2 500 0 5 23755 Figure 41 Turn On Time vs Temperature ADA4897 1 and ADA4897 2 Rev B Page 16 of 28 ADA4896 2 ADA4897 1 ADA4897 2 THEORY OF OPERATION AMPLIFIER DESCRIPTION The ADA4896 2 ADA4897 1 ADA4897 2 are 1 nV VHz input noise amplifiers that consume 3 mA from supplies ranging from 3 V to 10 V Fabricated on the Analog Devices SiGe bipolar process the ADA4896 2 ADA4897 1 ADA4897 2 have a bandwidth in excess of 200 MHz The amplifiers are unity gain stable and the input structure results in an extremely low input 1 f noise for a high speed amplifier The rail to rail output stage is designed to drive the heavy feed back load required to achieve an overall low output referred noise To meet more demanding system requirements the large signal bandwidth of the ADA4896 2 ADA4897 1 ADA4897 2 was increased beyond the typical fundamental limits of other low noise unity gain stable amplifiers The maximum offset voltage of 500 uV and drift of 0 2 wV C make the ADA4896 2 ADA4897 1 ADA4897 2 excellent amplifier choices even when the low noise performance is not needed because there is minimal power penalty in achieving the low input noise or the high bandwidth INPUT PROTECTION The ADA4896 2 ADA4897 1 ADA4897 2 are fully protected from ESD events withstanding human body model ESD events of 2 5 kV and charged device model events of 1 kV with no mea sured performance degradatio
11. 3 00 SQ i 2 90 0 50 BSC PIN 1 INDEX 1 70 AREA 1 60 1 50 PIN 1 TOP VIEW 4 BOTTOM VIEW INDICATOR R 0 15 0 80 FOR PROPER CONNECTION OF 0 75 0 05 MAX THE EXPOSED PAD REFER TO 0 02 NOM THE PIN CONFIGURATION AND 0 70 d t 3 FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET SEATING 2 0 30 4 0 08 PLANE 0 25 0 203 REF 0 20 01 24 2011 B COMPLIANT TO JEDEC STANDARDS MO 229 WEED Figure 57 8 Lead Lead Frame Chip Scale Package LFCSP WD 3mm x 3 mm Body Very Very Thin Dual Lead CP 8 11 Dimensions shown in millimeters Rev B Page 25 of 28 ADA4896 2 ADA4897 1 ADA4897 2 5 00 0 1968 4 80 0 1890 t 4 00 0 1574 6 20 0 2441 3 80 0 1497 5 80 0 2284 E E 27 0 05 0 50 0 0196 1 27 0 0500 50 0 x 45 BSC 1 75 0 0688 M 0 25 0 0099 i 0 25 0 0098 1 35 0 0532 0 10 0 0040 Y 9 y COPLANARITY 4 0 51 0 0201 gt e 0 10 ur 0 E 0098 1 27 0 0500 SEATING 2 29 USO 0 40 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 58 8 Lead Standard Small Outline Package SOIC_N Narrow Body R 8 Dimensions shown in millimeters and inches 1 70 3 00 1 60 2 80
12. 7 049 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C 09447 052 Figure 29 Input Overdrive Recovery Time Figure 32 Slew Rate vs Temperature Rev B Page 14 of 28 ADA4896 2 ADA4897 1 ADA4897 2 0 3 G 2 Vout 2V STEP L 1kO Vs 5V 1 Piy 30dBm 0 2 TIME 10ns DIV e 5 SETTLING TIME 56 e 09447 028 0 3 o 0 1 1 10 100 500 5 FREQUENCY MHz E Figure 33 Settling Time to 0 196 Figure 36 Output Impedance vs Frequency 20 26 0 Vs 5V 30 2V p p 40 gt 50 Fi 28 5 60 o a 70 9 80 o 90 6 p 31 0 100 110 120 130 33 5 ET 1k 10k 100k 1M 10M 100M 40 25 10 5 20 35 50 65 80 95 110 125 3 FREQUENCY Hz E TEMPERATURE C Figure 34 CMRR vs Frequency Figure 37 Input Offset Voltage vs Temperature for Various Supplies 10 50 Vs 5V 10 AVs 2V p p 20 21 me 10 75 40 E 50 a 5 PSRR g N Z 60 m 3 11 00 70 6 a PSRR lt 80 o
13. 7 1 ADA4897 2 make them excellent choices for processing weak Doppler signals The rail to rail output and the high output current drive of the ADA4896 2 ADA4897 1 ADA4897 2 make them suitable candidates for the I to V converter current summer and ADC driver Figure 55 shows an interconnection block diagram of all eight channels of the AD9279 Two stages of the ADA4896 2 amplifiers are used The first stage performs an I to V conver sion and filters the high frequency content that results from the demodulation process The second stage of the ADA4896 2 amplifiers is used to sum the output currents of multiple AD9279 devices to provide gain and to drive the AD7982 device an 18 bit SAR ADC The output referred noise of the CW signal path depends on the LNA gain the selection ofthe first stage summing amplifier and the value of Rurr To determine the output referred noise it is important to know the active low pass filter LPF values Ra Rrr and Curr as shown as Figure 55 Typical filter values for all eight channels of a single AD9279 are 100 for R4 500 for Rew and 2 0 nF for Cir these values implement a 100 kHz single pole LPF The gain ofthe I to V converter can be increased by increasing the filter resistor Rrrr To keep the corner frequency unchanged decrease the filter capacitor Curr by the same factor The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected
14. ANALOG DEVICES 1 nV Hz Low Power Rail to Rail Output Amplifiers ADA4896 2 ADA4897 1 ADA4897 2 FEATURES Low wideband noise 1 nV VHz 2 8 pA VHz Low 1 f noise 2 4 nV VHz at 10 Hz Low distortion 115 dBc at 100 kHz Vout 2 V p p Low power 3 mA per amplifier Low input offset voltage 0 5 mV maximum High speed 3 dB bandwidth 230 MHz G 1 Slew rate 120 V us Settling time to 0 196 45 ns Rail to rail output Wide supply range 3 V to 10V Disable feature ADA4897 1 ADA4897 2 APPLICATIONS Low noise preamplifier Ultrasound amplifiers PLL loop filters High performance ADC drivers DAC buffers GENERAL DESCRIPTION The ADA4896 2 ADA4897 1 ADA4897 2 are unity gain stable low noise rail to rail output high speed voltage feedback amplifiers that have a quiescent current of 3 mA With a 1 f noise of 24 nV NHz at 10 Hz and a spurious free dynamic range of 80 dBc at 2 MHz the ADA4896 2 ADA4897 1 ADA4897 2 are ideal solutions in a variety of applications including ultrasound low noise preamplifiers and drivers of high performance ADCs The Analog Devices Inc proprietary next generation SiGe bipolar process and innovative architecture enable such high performance amplifiers The ADA4896 2 ADA4897 1 ADA4897 2 have 230 MHz bandwidth 120 V us slew rate and settle to 0 196 in 45 ns With a wide supply voltage range of 3 V to 10 V the ADA4896 2 ADA4897 1 ADA4897 2 are ideal candidates for systems that require hig
15. B switches are on the first stage amplifier gain is 2 The first set of switches of the ADG633 is placed on the output side of the feedback loop and the second set of switches is used to sample at a point V1 or V2 where switch resistances and nonlinear resistances do not matter In this way the gain error can be reduced while preserving the noise performance of the ADA4896 2 Note that the input bias current of the output buffer can cause problems with the impedance of the S2A and S2B sampling switches Both sampling switches are not only nonlinear with voltage but with temperature as well If this is an issue place the unused switch of the ADG633 S3B in the feedback path of the output buffer to balance the bias currents see Figure 52 In addition the bias current of the input amplifier causes an offset at the output that varies based on the gain setting Because the input amplifier and the output buffer are mono lithic the relative matching of their bias currents can be used to cancel out the varying offset Placing a resistor equal to the difference between Rr and Rm in series with Switch S2A results in a more constant offset voltage The following derivation shows that sampling at V1 yields the desired signal gain without gain error Rs denotes the switch resistance V2 can be derived using the same method Ry R Vig f d 7 Ra Ra R VI Vp m cI 6 Rg Ry Substituting Equation 1 into Equation 2 t
16. FIER AND RESISTOR NOISE NOISE nV Hz a SOURCE RESISTANCE NOISE TOTAL AMPLIFIER NOISE 0 5 50 500 5k 50k SOURCE RESISTANCE Q 09447 057 Figure 49 RTI Noise vs Source Resistance CAPACITANCE DRIVE Capacitance at the output of an amplifier creates a delay within the feedback path that if within the bandwidth of the loop can create excessive ringing and oscillation The ADA4896 2 ADA4897 1 ADA4897 2 show the most peaking at a gain of 2 see Figure 9 Placing a small snub resistor Rsnus in series with the amplifier output and the capacitive load mitigates the problem Figure 50 shows the effect of using a snub resistor Rsxus on reducing the peaking for the worst case frequency response gain of 2 Using Rswus 100 Q eliminates the peaking entirely with the trade off that the closed loop gain is reduced by 0 8 dB due to attenuation at the output Rsnus can be adjusted from 0 to 100 to maintain an acceptable level of peaking and closed loop gain see Figure 50 3 Vs 5V Vout 200 p p 5 2 G 2 R 0Q Rsnup 6 Renue 1000 Renys 500 o 0 q E R2 9 249 a 2 N i RsNUB Vour R C L L i 1kQ I 39pF 5 l l i 10 100 09447 058 FREQUENCY MHz Figure 50 Usin
17. O 90 2 n 100 Z 11 25 110 120 130 e 11 50 o 1k 10k 100k 1M 10M 100M 5 40 25 10 5 20 35 50 65 80 95 110 125 b b FREQUENCY Hz 3 TEMPERATURE C Figure 35 PSRR vs Frequency Figure 38 Input Bias Current vs Temperature for Various Supplies Rev B Page 15 of 28 ADA4896 2 ADA4897 1 ADA4897 2 DISABLE PIN 25 Vs 5V 3 750 G 41 Vin 1V 3 625 z 3 500 E 5 3 375 y 3 250 lt n d 9 4 3 125 8 o m gt lt 3 000 5 a 3 E 2 875 5 o 2 750 2 625 2 500 8 2 5 E 2375 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 39 Supply Current vs Temperature for Various Supplies Figure 42 Turn Off Time vs Temperature ADA4897 1 and ADA4897 2 Vg 5V G 2 Vout 2V p p 5 5 x z z 5 E E to lt o d 9 o 6 o FREQUENCY MHz FREQUENCY MHz Figure 40 Crosstalk OUT1 to OUT2 ADA4896 2 and ADA4897 2 Figure 43 Forward Isolation vs Frequency 5 5 3 875 DISABLE PIN 5 0 3 750 4 5 3 625 4 0 3 500 3 5 33759 25 C 125 C 0 z 30 3 250 amp a 40 C u 25 3 125 O Q E lt 20 3 000 5 a A 15 2 875 5 TIME 200ns DIV 2 75
18. PIN 1 EE INDICATOR 0 95 BSC la 190 BSC 1 30 1 15 0 90 4 1 45 MAX 0 20 MAX 0 95 MIN 08 MIN 0 15 MAX 7 F 10 0 05 MIN SEATING 45 0 60 gt 090MAX BSC 0 30 MIN 0 COMPLIANT TO JEDEC STANDARDS MO 178 AB Figure 59 6 Lead Small Outline Transistor Package SOT 23 RJ 6 Dimensions shown in millimeters Rev B Page 26 of 28 012407 A 0 35 12 16 2008 A ADA4896 2 ADA4897 1 ADA4897 2 3 10 3 00 PIN 1 0 95 15 MAX 0 85 1 10 MAX aas 0 75 i i n 1 0 70 0 15 amp 1 f 923 055 0 05 gt 0 30 D 13 0 40 0 15 0 0 40 COPLANARITY 0 10 091709 A COMPLIANT TO JEDEC STANDARDS MO 187 BA Figure 60 10 Lead Mini Small Outline Package MSOP RM 10 Dimensions shown in millimeters ORDERING GUIDE Package Ordering Model Temperature Range Package Description Option Quantity Branding ADA4896 2ARMZ 40 C to 125 C 8 Lead MSOP RM 8 50 H2P ADA4896 2ARMZ R7 40 C to 125 C 8 Lead MSOP RM 8 1 000 H2P ADA4896 2ARMZ RL 40 C to 125 C 8 Lead MSOP RM 8 3 000 H2P ADA4896 2ACPZ R2 40 C to 125 C 8 Lead LFCSP WD CP 8 11 250 H2P ADA4896 2ACPZ R7 40 C to 125 C 8 Lead LFCSP WD CP 8 11 1 500 H2P ADA4896 2ACPZ RL 40 C to 125 C 8 Lead LFCSP WD CP 8 11 5 000 H2P ADA4896 2ACP EBZ Evaluation Board for the 8 Lead LFCSP ADA4896 2ARM EBZ Evaluation Board for the 8 Lead MSOP ADA4897 1ARZ 40 C to 125 C 8 Lead SOIC R 8 98 ADA4897 1ARZ
19. TIONS Figure 48 illustrates the primary noise contributors for the typical gain configurations The total rms output noise is the root mean square of all the contributions Rr vn _ Rp z NA4KT x Re o ae 09447 034 Figure 48 Noise Sources in Typical Connection The output noise spectral density can be calculated by vout __en 2 2 jur 0x AKTR ien G where kis Boltzmanns constant T is the absolute temperature degrees Kelvin iep and ien represent the amplifier input current noise spectral density pA VHz ven is the amplifier input voltage noise spectral density nV VHz Rs is the source resistance as shown in Figure 48 Rr and Rc are the feedback network resistances as shown in Figure 48 Source resistance noise amplifier voltage noise ven and the voltage noise from the amplifier current noise iep x Rs are all subject to the noise gain term 1 Re Rc Note that with a 1 nV VHz input voltage noise and 2 8 pA VHz input current noise the noise contributions of the amplifier are relatively small for source resistances from approximately 50 Q to 700 Q Figure 49 shows the total RTI noise due to the amplifier vs the source resistance In addition the value of the feedback resistors used affects the noise It is recommended that the value of the feedback resistors be maintained between 250 and 1 to keep the total noise low 500 a e AMPLI
20. Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vour 0 02 V p p 230 MHz G 1 Vout 2 V p p 30 MHz G 2 Vout 0 02 V p p 90 MHz Bandwidth for 0 1 dB Flatness G 2 Vout 2 V p p R 1000 7 MHz Slew Rate G 2 Vout 3 V step 100 V us Settling Time to 0 196 G 2 Vout 2 V step 45 ns Settling Time to 0 01 G 2 Vout 2 V step 95 ns NOISE HARMONIC PERFORMANCE Harmonic Distortion SFDR Vout 2 V p p fc 100 kHz 115 dBc fc 1 MHz 93 dBc fc 2 MHz 80 dBc fc 5 MHz 61 dBc Input Voltage Noise f 10Hz 24 nV VHz f 100 kHz 1 nV VHz Input Current Noise f 10Hz 11 pA VHz 100 kHz 2 8 pA VHz 0 1 Hz to 10 Hz Noise G 101 R 1 Rc 2 100 99 nV p p DC PERFORMANCE Input Offset Voltage 500 30 500 Input Offset Voltage Drift 0 2 yv C Input Bias Current 17 11 4 uA Input Bias Current Drift 3 nA C Input Bias Offset Current 0 6 0 02 0 6 uA Open Loop Gain Vour 0 5 V to 4 5 V 97 110 dB Rev B Page 4 of 28 ADA4896 2 ADA4897 1 ADA4897 2 Parameter Test Conditions Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance Common Mode 10 MQ Differential 10 Input Capacitance Common Mode 3 pF Differential 11 pF Input Common Mode Voltage Range 0 1 to 4 1 V Common Mode Rejection Ratio Ven 2 1Vto 4V 91 118 dB CMRR OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VN 0Vto5V G2 42 96 ns Output Voltage Swing Positive R 21kQ 4
21. Vout 2V p p 5 9 G 1 q lt 0 5 n 8 j ao D W 2 6 10 al al o o g N N N N E z E amp z 9 5 P 6 o 100k 1M 10M 100M 16 8 0 1 1 10 100 FREQUENCY Hz FREQUENCY MHz E Figure 11 Small Signal Frequency Response vs Temperature Figure 14 Large Signal Frequency Response vs Gain Rev B Page 11 of 28 ADA4896 2 ADA4897 1 ADA4897 2 Vg 5V Vout 2V p p G 10 1000 SECON DISTORTION dBc 1kO THIRD NORMALIZED CLOSED LOOP GAIN dB 0 1 1 10 100 8 0 1 1 5 FREQUENCY MHz E FREQUENCY MHz 3 Figure 15 Small Signal Frequency Response vs Capacitive Load Figure 18 Harmonic Distortion vs Frequency G 10 50 Vs 5V Vour 2V p p G 1 60 1000 SECO 70 9 g 5 bad z 80 6 E R 1000 THIRD 3 fz E 90 8 ae 1kO THIRD a a L J a A 100 4V p p THIRD 110 R 1kQ SECOND 120 e 0 1 1 59 0 1 1 58 FREQUENCY MHz FREQUENCY MHz i Figure 16 Harmonic Distortion vs Frequency G 1 Figure 19 Harmonic Distortion vs Frequency for Various Output Voltages 40 Vs 5V Vout 2V p p so 1515 E 1000 SECOND FP 4 60 P a z
22. as Offset Current 0 6 0 02 10 6 pA Open Loop Gain Vout 4V to 4 V 100 110 dB INPUT CHARACTERISTICS Input Resistance Common Mode 10 MO Differential 10 Input Capacitance Common Mode 3 pF Differential 11 pF Input Common Mode Voltage Range 4 9 to 14 1 V Common Mode Rejection Ratio Vou 2V to 2 V 92 120 dB CMRR OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Vn 45 V G 2 81 ns Output Voltage Swing Positive 1 4 85 4 96 V R 2 1000 4 5 4 73 V Negative 1 4 85 4 97 V R 2 1000 4 5 4 84 V Output Current SFDR 45 dBc 80 mA Short Circuit Current Sinking sourcing 135 mA Capacitive Load Drive 30 overshoot G 2 39 pF Rev B Page 3 of 28 ADA4896 2 ADA4897 1 ADA4897 2 Parameter Test Conditions Comments Min Typ Max Unit POWER SUPPLY Operating Range 3to 10 V Quiescent Current per Amplifier 2 8 3 0 3 2 mA DISABLE 5 V 0 13 0 25 mA Power Supply Rejection Ratio PSRR Positive Vs 4V to 6V Vs 5 V 96 125 dB Negative Vs 5V Vs 4 V to 6 V 96 121 dB DISABLE PIN ADA4897 1 ADA4897 2 DISABLE Voltage Enabled Vs 0 5 V Disabled lt Vs 2 V Input Current Enabled DISABLE 5 V 1 2 pA Disabled DISABLE 5 V 40 Switching Speed Enabled 0 25 Hs Disabled 12 us 5 V SUPPLY Ta 25 C G 1 Ri 1 to midsupply unless otherwise noted Table 4 Parameter Test Conditions Comments Min
23. ead Single SOIC ADA4897 1 133 C W 6 Lead Single SOT 23 ADA4897 1 150 C W 10 Lead Dual MSOP ADA4897 2 210 C W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4896 2 ADA4897 1 ADA4897 2 is limited by the associated rise in junction temperature on the die At approximately 150 C which is the glass transition temperature the properties of the plastic change Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die permanently shifting the parametric performance of the ADA4896 2 ADA4897 1 ADA4897 2 Exceeding a junction temperature of 175 C for an extended period of time can result in changes in silicon devices potentially causing degradation or loss of functionality The power dissipated in the package Pp is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4896 2 ADA4897 1 ADA4897 2 drive at the output The quiescent power dissipation is the voltage between the supply pins Vs multiplied by the quiescent current Is Pp Quiescent Power Total Drive Power Load Power V vV uos P V x1 4 E x an our 1 L RMS output voltages should be considered If Ri is referenced to Vs as in single supply operation the total drive power is Vs x If the rms signal levels are indeterminate consider the worst case when Vour Vs 4 for Ri to midsupply V 4 1 P
24. fier Section and Figure 52 eot vett Y He edd 21 Deleted Eig re 51 25 ud eps 22 Changes to Power Supply Bypassing Section 24 Moved Figure 57 iecit I UR Ee De ER 25 Moved Figure 58 we 26 Added Figure 60 Changes to Ordering Guide see 27 7 11 Revision 0 Initial Version Rev B Page 2 of 28 ADA4896 2 ADA4897 1 ADA4897 2 SPECIFICATIONS 5 V SUPPLY Ta 25 C G 1 R 1 to ground unless otherwise noted Table 3 Parameter Test Conditions Comments Min Typ Max Unit DYNAMIC PERFORMANCE 3 dB Bandwidth G 1 Vour 0 02 V p p 230 MHz G 1 Vout 2 V p p 30 MHz G 2 Vour 0 02 V p p 90 MHz Bandwidth for 0 1 dB Flatness G 2 Vout 2 V p p R 2 100 Q 7 MHz Slew Rate G 2 Vout 6 V step 120 V us Settling Time to 0 196 G 2 Vout 2 V step 45 ns Settling Time to 0 01 G 2 Vout 2 V step 90 ns NOISE HARMONIC PERFORMANCE Harmonic Distortion SFDR Vour 2 V p p fc 100 kHz 115 dBc fc 1 MHz 93 dBc fc 2 MHz 80 dBc fc 5 MHz 61 dBc Input Voltage Noise f 10Hz 24 nV VHz f 100 kHz 1 nV VHz Input Current Noise f 10Hz 11 pA VHz f 100 kHz 2 8 pA VHz 0 1 Hz to 10 Hz Noise G 101 Rez 1 100 99 nV p p DC PERFORMANCE Input Offset Voltage 500 28 500 Input Offset Voltage Drift 0 2 Input Bias Current 17 11 4 uA Input Bias Current Drift 3 nA C Input Bi
25. for the I to V converter in this example the ADA4896 2 ADA4897 1 ADA4897 2 Because any amplifier has limited drive capability a finite number of channels can be summed Rev B Page 23 of 28 ADA4896 2 ADA4897 1 ADA4897 2 LAYOUT CONSIDERATIONS To ensure optimal performance careful and deliberate attention must be paid to the board layout signal routing power supply bypassing and grounding Ground Plane It is important to avoid ground in the areas under and around the input and output of the ADA4896 2 ADA4897 1 ADA4897 2 Stray capacitance created between the ground plane and the input and output pads of a device is detrimental to high speed amplifier performance Stray capacitance at the inverting input along with the amplifier input capacitance lowers the phase margin and can cause instability Stray capacitance at the output creates a pole in the feedback loop which can reduce phase margin and can cause the circuit to become unstable Power Supply Bypassing Power supply bypassing is a critical aspect in the performance of the ADA4896 2 ADA4897 1 ADA4897 2 A parallel connec tion of capacitors from each power supply pin to ground works best Smaller value capacitor electrolytics offer better high frequency response whereas larger value capacitor electrolytics offer better low frequency performance Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided with a lo
26. g a Snub Resistor to Reduce Peaking Due to Output Capacitive Load Rev B Page 19 of 28 ADA4896 2 ADA4897 1 ADA4897 2 APPLICATIONS INFORMATION TYPICAL PERFORMANCE VALUES Vee Vout 200mV p p To reduce design time and eliminate uncertainty Table 13 9 1 Rr 2490 E provides a reference for typical gains component values and Zo G 2 performance parameters The supply voltage used is 5 V The band a width is obtained with a small signal output of 200 mV p p and 9 the slew rate is obtained with a 2 V output step il SR Note that as the gain increases the small signal bandwidth o SEM a3 decreases as is expected from the gain bandwidth product u relationship In addition the phase margin improves with z EH higher gains and the amplifier becomes more stable As a S Ls result the peaking in the frequency response is reduced see Figure 51 d 1 10 100 500 09447 020 FREQUENCY MHz Figure 51 Small Signal Frequency Response at Various Gains Table 13 Recommended Values and Typical Performance Total Output Noise Including Gain Rr Q Re Q 3 dB BW MHz Slew Rate tr tr V us Peaking dB Resistors nV 4Hz 1 0 92 78 158 0 8 1 0 2 249 249 54 101 140 1 2 3 6 5 249 61 9 30 119 137 0 6 8 10 249 27 4 17 87 88 0 12 0 20 249 13 0 9 37 37 0 21 1 Rev B Pa
27. ge 20 of 28 ADA4896 2 ADA4897 1 ADA4897 2 LOW NOISE GAIN SELECTABLE AMPLIFIER Rr2 2250 5V USING S3B IS OPTIONAL S3B D3 ADG633 R 52 BALANCE 1500 ADG633 09447 100 Figure 52 Using the ADA4896 2 and the ADG633 to Construct a Low Noise Gain Selectable Amplifier to Drive a Low Resistive Load gain selectable amplifier makes processing a wide range of input signals possible A traditional gain selectable amplifier uses switches in the feedback loops connecting to the inverting input The switch resistances degrade the noise performance of the amplifier as well as adding significant capacitance on the inverting input node The noise and capacitance issues can be especially bothersome when working with low noise amplifiers Also the switch resistances contribute to nonlinear gain error which is undesirable Figure 52 presents an innovative switching technique used in the gain selectable amplifier such that the 1 nV Hz noise per formance of the ADA4896 2 is preserved while the nonlinear gain error is much reduced With this technique the user can also choose switches with minimal capacitance to optimize the bandwidth of the circuit In the circuit shown in Figure 52 the switches are implemented with the ADG633 and are configured such that either 51 and S2A are on or S1B and S2B are on In this example when the S1A and S2A switches are on the first stage amplifier gain is 4 When the 51 and S2
28. h dynamic range precision low power and high speed The ADA4896 2 is available in 8 lead LFCSP and 8 lead MSOP packages The ADA4897 1 is available in 8 lead SOIC and 6 lead SOT 23 packages The ADA4897 2 is available in a 10 lead MSOP package The ADA4896 2 ADA4897 1 ADA4897 2 operate over the extended industrial temperature range of 40 C to 125 C Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM 09447 101 VOLTAGE NOISE nV Hz 100 1k 10k 100k 1M 5M FREQUENCY Hz 09447 102 Figure 2 Voltage Noise vs Frequency Table 1 Other Low Noise Amplifiers Vn nV VHz Supply Part No At 1 kHz At 100 kHz BW MHz Voltage V AD797 0 9 0 9 8 10 to 30 AD8021 5 2 1 490 5 to 24 AD8099 3 0 95 510 5 to 12 AD8045 6 3 1000 3 3 to 12 ADA4899 1 1 4 1 600 5 to 12 ADA4898 1 0 9 0 9 65 10 to 32 ADA4898 2 Table 2 Complementar
29. h programmable phase rotation For detailed information about how to use the AD9279 in an ultrasound system see the AD9279 data sheet Medical ultrasound systems are among the most sophisticated signal processing systems in widespread use today By transmit ting acoustic energy into the body and receiving and processing the returning reflections ultrasound systems can generate images of internal organs and structures map blood flow and tissue motion and provide highly accurate blood velocity information Figure 54 shows a simplified block diagram of an ultrasound system Rev B Page 22 of 28 ADA4896 2 ADA4897 1 ADA4897 2 ADA4896 2 ADA4897 1 ADA4897 2 in the Ultrasound System M 500 AD7982 DA4896 2 2 5V ADA4896 2 ADA4897 1 ADA4897 1 18 BIT ADC I ADA4897 2 25y ADA4897 2 CWI 500 4nF IT M Reitt CWQ 500 AD7982 E ADA4896 2 2 5V ADA4896 2 ADA4897 1 ADA4897 1 18 ADC Q ADA4897 2 2 5y ADA4897 2 500 LO GENERATION AD9279 V4 09447 032 Figure 55 Using the ADA4896 2 ADA4897 1 ADA4897 2 as Filters I to V Converters Current Summers and ADC Drivers After the I Q Outputs of the AD9279 The ADA4896 2 ADA4897 1 ADA4897 2 are used in the CW Doppler path in the ultrasound application after the I Q demod ulators of the AD9279 Doppler signals can be typically between 100 Hz to 100 kHz The low noise floor and high dynamic range of the ADA4896 2 ADA489
30. he DISABLE pin is protected by ESD clamps as shown in Figure 45 Voltages beyond the power supplies cause these diodes to conduct For protection of the DISABLE pin the voltage to this pin should not exceed 0 7 V above the positive supply or 0 7 V below the negative supply If an overvoltage condition is expected it is recommended that the input current be limited with a series resistor to less than 10 mA When the amplifier is disabled its output goes to a high impedance state The output impedance decreases as frequency increases this effect can be observed in Figure 36 In disable mode a forward isolation of 50 dB can be achieved at 10 MHz Figure 43 shows the forward isolation vs frequency data Rev B Page 17 of 28 ADA4896 2 ADA4897 1 ADA4897 2 DC ERRORS Figure 46 shows a typical connection diagram and the major dc error sources 09447 031 Figure 46 Typical Connection Diagram and DC Error Sources The ideal transfer function all error sources set to 0 and infinite dc gain can be written as R R Vour t H x Vp 1 This equation reduces to the familiar forms for noninverting and inverting op amp gain expressions as follows For noninverting gain Vin 0 V R Vour f x x Vip 2 G R Vour x x Vin 3 The total output voltage error is the sum of errors due to the amplifier offset voltage and input currents The output error due to the offset voltage can be estimated as
31. he following derivation is obtained Ry Vl V x 1 9 Note that if Vo yields the desired signal gain without gain error the buffered output Vo will also be free from gain error Figure 53 shows the normalized frequency response of the circuit at Vo 6 Vs 35 3 Vin 100mV p p 1kQ 0 3 6 9 12 NORMALIZED CLOSED LOOP GAIN dB 10 FREQUENCY MHz 100 500 09447 064 Figure 53 Frequency Response of Vo2 Vin Rev B Page 21 of 28 ADA4896 2 ADA4897 1 ADA4897 2 MEDICAL ULTRASOUND APPLICATIONS T R SWITCHES BEAMFORMER CENTRAL CONTROL Tx BEAMFORMER Rx BEAMFORMER B AND F MODES TRANSDUCER ARRAY CW ANALOG SPECTRAL IMAGE AND COLOR ee PROCESSIN ADA4896 2 MODE B MODE F MODE ADA4897 1 ADA4897 2 AUDIO OUTPUT DISPLAY 09447 033 Figure 54 Simplified Ultrasound System Block Diagram Overview of the Ultrasound System The ultrasound system consists of two main operations the time gain control TGC operation and the continuous wave CW Doppler operation The AD9279 integrates the essential components of these two operations into a single IC It contains eight channels of a variable gain amplifier VGA with a low noise preamplifier LNA an antialiasing filter AAF an analog to digital converter ADC and an I Q demodulator wit
32. n The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair as shown in Figure 44 VsO 09447 068 TO THE REST OF THE AMPLIFIER Figure 44 Input Stage and Protection Diodes For differential voltages above approximately 0 7 V the diode clamps begin to conduct Too much current can cause damage due to excessive heating If large differential voltages must be sustained across the input terminals it is recommended that the current through the input clamps be limited to less than 10 mA Series input resistors that are sized appropriately for the expected differential overvoltage provide the needed protection The ESD clamps begin to conduct for input voltages that are more than 0 7 V above the positive supply and input voltages more than 0 7 V below the negative supply If an overvoltage condition is expected it is recommended that the input current be limited to less than 10 mA DISABLE OPERATION Figure 45 shows the ADA4897 1 ADA4897 2 power down circuitry If the DISABLE pin is left unconnected the base of the input PNP transistor is pulled high through the internal pull up resistor to the positive supply and the part is turned on Pulling the DISABLE pin to 22 V below the positive supply turns the part off reducing the supply current to approximately 18 uA for a 5 V voltage supply Vs O ESD O DISABLE ESD H 3 Figure 45 DISABLE Circuit T
33. nverting Input 2 9 OUT2 Output 2 10 Vs Positive Supply Rev B Page 10 of 28 ADA4896 2 ADA4897 1 ADA4897 2 TYPICAL PERFORMANCE CHARACTERISTICS Ri 1 unless otherwise noted When G 1 Rr 0 Q otherwise Rr 249 Q Vs 5V G E 1 5 1 20mV p p lt q lt q 5 oO n n 3 E 3 1 100mV p p m m Lil o 9 400 d d o o 8 3 29 p p q o 4 z z 2 S 0 1 1 10 100 500 FREQUENCY MHz i FREQUENCY MHz i Figure 9 Small Signal Frequency Response vs Gain Figure 12 Frequency Response for Various Output Voltages 0 8 Vs 5V 5 gU Your 2V p p Rf Rg 2490 5 S 1k S z 06 4 00 eo Oo 05 n n Q 8 04 o o 9 Rr Rg 49 90 i i a 03 0 0 5 8 o o a 01 N N 0 m amp 0 1 2 6 2 0 3 z 0 1 1 10 50 5 FREQUENCY MHz i FREQUENCY MHz Figure 10 Small Signal Frequency Response vs Supply Voltage Figure 13 0 1 dB Bandwidth at Selected Rr Values Vs 5V B E T
34. w ac impedance across a wide band of frequencies This is important for minimiz ing the coupling of noise into the amplifier especially when the amplifier PSRR begins to roll off because the bypass capacitors can help lessen the degradation in PSRR performance The smallest value capacitor should be placed on the same side of the board as the amplifier and as close as possible to the amp lifier power supply pins The ground end of the capacitor should be connected directly to the ground plane It is recommended that a 0 1 uF ceramic capacitor with a 0508 case size be used The 0508 case size offers low series inductance and excellent high frequency performance A 10 uF electrolytic capacitor should be placed in parallel with the 0 1 uF capacitor Depending on the circuit parameters some enhancement to performance can be realized by adding additional capacitors Each circuit is different and should be analyzed individually for optimal performance Rev B Page 24 of 28 ADA4896 2 ADA4897 1 ADA4897 2 OUTLINE DIMENSIONS 5 15 3 20 190 3 00 165 2 80 1 IDENTIFIER 0 95 15 MAX 0 85 1 10 MAX sa 0 75 Y i Ll 0 80 o15 e f 1 023 oss 0 40 5 55 0 05 gt 025 0 0 09 0 40 COPLANARITY m 0 10 COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 56 8 Lead Mini Small Outline Package MSOP RM 8 Dimensions shown in millimeters 3 10
35. x 7 n 8 B 70 Je g Vs 3V E LE ut c SECOND x O 80 O 5 Pd 5 a 7 7 a J R 1000 THIRD 8 90 4 B BO ler R 1kO THIRD 100 MR SECOND 110 9 0 1 1 5 3 H FREQUENCY MHz FREQUENCY MHz Figure 17 Harmonic Distortion vs Frequency G 5 Figure 20 Harmonic Distortion vs Frequency for Various Supplies Rev B Page 12 of 28 ADA4896 2 ADA4897 1 ADA4897 2 90 0 18 Vs 5V 80 100 UNITS 100 16 309 2 a v 14 zc 120 i 9 PHASE o o S o Ee 12 z 5 mE 140 amp E lt ul a 40 2 u 10 a 160 T o o 30 oa c a ul 8 3 o 2 2 20 m o 5 6 5 10 a E 200 amp 3 p REN 20 240 0 10k 100k 1M 10M 100M 1G i 600 400 200 0 200 400 600 800 1000 2 i FREQUENCY Hz 8 OFFSET VOLTAGE DRIFT DISTRIBUTION nV C Figure 21 Open Loop Gain and Phase vs Frequency Figure 24 Input Offset Voltage Drift Distribution G 1 Vout 20mV p p TIME 100ns DIV F 5 3 t gt ul 9 lt Ez 5 8 6 5 E a 2 5 o gt S 5 FREQUENCY Hz Figure 22 Voltage Noise vs Frequency Figure 25 Small Signal Transient Response for
36. y ADCs Part No Bits Speed MSPS Power mW AD7944 14 2 5 15 5 AD7985 16 2 5 15 5 AD7986 18 2 15 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2012 Analog Devices Inc All rights reserved ADA4896 2 ADA4897 1 ADA4897 2 TABLE OF CONTENTS Features 1 Applications UR 1 General Description eite eet eb dete 1 Functional Block Diagram seen 1 Revision 2 3 tete tete 3 T9 ViSupply 4 ABM SUpply sissies 6 Absolute Maximum Ratings seen 8 Thermal Resistance teer tret 8 Maximum Power Dissipation sss 8 ESD Cauti nsciis sisisi ssi sisii i eiei Soie Pin Configurations and Function Descriptions Typical Performance Characteristics ssssss REVISION HISTORY 4 12 Rev A to Rev B Changed 6 Lead Single SOT 23 ADA4897 1 Thermal Reistance from 306 C W to 150 8 Changes peer 8 10 11 Rev 0 to Rev A Added ADA4897 2 and 10 Lead 5 Universal Change to Table T i erii tie eritis 1 Changes to Table 3 9 Changes to Table Airisis 4 Ghanges 6

ANALOG DEVICES ADA4896-2/ADA4897-1/ADA4897-2 Manual

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