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TEXAS INSTRUMENTS MSP430x31x Manual

1. Incl 16 MDB 16 Bit Z Bus Conv k RST NMI 8 bit Timer Counter Serial Protocol Pad Support Reset MAB 4 Bit Port O s All With nterr Cap Int Vectors Watchdog Basic Timer Port Timer 15 16 Bit Applications Timer1 A D Conv Timer O P TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 0 3 52 16 02 16 27 027 CMPI MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 Terminal Functions MSP430C311S MSP430P315S 48 pin SSOP package TERMINAL y o DESCRIPTION NAME NO CIN 24 Counter enable CIN input enables counter TPCNT1 timer port coMo GOMS 44 47 O Common output pins COMO COMGarewsedorLCDbackpanes R3 Input of second positive analog LCD level V2 LCD 39 Input of third positive analog LCD level V3 of V4 LCD PASTA a i _ Resetinputornonmaskable 52 02 55 05 25 2 O Segment lines S2 to S5 or digital output port O2 to O5 group 1 LCD 56 06 5909 29 32 O Segment lines S6 to S9 or digital output port O6 to O9 group 2 LCD 510 010 513 013 33 O Segment lines S10 to S13 or digital output port O10 to O13 group 3 LCD 514014519010 57552 0 Segment lines 514 to 517 digital output port 14 to 017 group 4 LCD S27
2. ADD 235h amp MEM ADD B 35h amp MEM PUSH R5 PUSH B R5 SWPB R5 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 Table 2 Address Mode Descriptions mmesswo s __ __ __ OPERATION ________ 2 5 2 R5 6 R6 PCa s Pe even aon ET v woveme nw wovemo m wmoommo 25 n0 immdae ____ NOTE s source d destination Computed branches BR and subroutine call CALL instructions use the same addressing modes as the other instructions These addressing modes provide indirect addressing ideally suited for computed branches and calls The full use of this programming capability permits a program structure different from conventional 8 and 16 bit controllers For example numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control operation modes and interrupts The MSP430 operating modes support various advanced requirements for ultra low power and ultra low energy consumption This is achieved by the management of the operations during the different module operation modes and CPU states The requirements ar
3. 5 0 230xVogg 0 25xVCC 0 260 5 Vcc 3 V Vhys com Input hysteresis comparator CPON Voo 5V T RAM NOTE 14 This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged No program execution should happen during this supply voltage condition PUC POR PARAMETER CONDITIONS NOM MAX UNIT Ta 40C POR delay V POR ITA 29C Ta 8C Voc 23 V 5V PUC POR Reset is internally Ji TEXAS INSTRUMENTS 20 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 H e m V vec V POR POR No POR POR Figure 4 Power On Reset POR vs Supply Voltage V POR V Temperature C Figure 5 vs Temperature wakeup from LPM3 PARAMETER TEST CONDITIONS NOM MAX UNIT 3 w 5 t LPM3 Delay time 3 us 5 f MHz Voc 5 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 electrical characteristics over recommended operating free air temperature range unless otherwise noted JTAG program memory PARAMETER TEST CONDITION
4. 5 5 8 8 T Operating Free Air Temperature C Supply Voltage V Figure 7 Figure 8 4 EXAS INSTRUMENTS 24 POST OFFICE BOX 655303 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 TYPICAL CHARACTERISTICS typical input output schematics Vcc see Note A see Note B 0 see B see Note A GND CMOS INPUT RST NMI Vcc see Note A see Note B see Note B see Note GND WITH SCHMITT TRIGGER INPUT P0 x TP0 5 Vcc 60 TYP gt gt MSP430C31x TMS MSP430P E31x TMS Vcc see Note see Note B see Note B see Note A CMOS SCHMITT TRIGGER INPUT CIN CMOS 3 STATE OUTPUT TP0 0 4 XBUF TDO Internal TDO Control TDI Control TDI Internal MSP430C31x TDO TDI MSP430P E31x TDO TDI NOTES A Optional selection of pull up or pull down resistors with ROM masked versions B Fuses for the optional pull up and pull down resistors can only be programmed at the factory 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 25 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 TYPICAL CHARACTERISTICS typical input output schematics VC O VD Control COMO 3
5. 3 Low power mode LPMO 1 P313T TA 409 85 C Vec 5V 3 P315 S 40 C 85 C 5 3 2 Low power mode LPM2 4090 85 C Voc 5V TA 40 C 25 3 TA 85 C lLPM3 Low power mode LPM3 TA 40 C TA 25 C Vcc 5V ILPM4 Low power mode LPM4 Vcc 3 V 5 V T MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 NOTE Allinputs are tied to 0 V or Vcc Outputs do not source or sink any current The current consumption in LPM2 and LPM3 are measured with active basic timer ACLK selected and LCD module fj 1024 Hz 4 mux 35 TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 electrical characteristics over recommended operating free air temperature range unless otherwise noted continued current consumption of active mode versus system frequency C versions only IAM MHz X fsystem MHz current consumption of active mode versus supply voltage C versions only IAM lAMI3 v 200 x Vcc 3 V schmitt trigger inputs port 0 Timer Port CIN TP0 5 PARAMETER TEST CONDITIONS MIN NOM MAX UNIT 2 Voc 23V 1 2 2 1 Positive going input threshold voltage V Voc 5 V 2 3 3 4 Negative going input threshold voltage Vnys Input hysteresis VI
6. 3 fpCO26 Npco 11 0100 0000 FN_4 1 FN_3 FN_2 X Vec 5V 177 Npco fMCLK NOM FN 4 FN 3 FN 2 0 3 5 Aoh 1A0h 340 00 f DCO26 4xfNOM f DCO3 f DCO3 Legend Tolerance at Tap 26 2xfNOM DCO Frequency Adjusted by Bits 2 9 2 5 in SCFI1 fNOM Tolerance at Tap 3 FN 2 0 FN 2 1 FN 2 FN 2 FN 3 0 FN 3 0 FN 3 1 FN 3 FN 4 0 FN 4 0 FN 4 0 FN 1 Figure 3 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 electrical characteristics over recommended operating free air temperature range unless otherwise noted LCD PARAMETER 5 CONDITIONS UNIT 3 5 2 3 lt Vcc Vss x Voltage at R13 Voc 3 V 5 V V Output 1 HLCD lt 10 nA E 0 125 Output 0 LLCD lt 10 0 125 Fouen m p LLCD Voc 3 V 5 V 55 ______ e leakage 823 see 13 823 2 ro R13 to S XX 2200 Output SXX I SXX 3 nA Voc 3 5 823 10 NOTE 13 l Rxx is measured with no load on the segment common LCD pins comparator Timer Port PARAMETER Voc 23V 250 350 Comparator timer port CPON Voc 25V 450 600 Internal reference voltage at terminal CPON 3
7. Plastic Small Outline Package TEG 2204 SSOP m Ea 48 Pin SSOP 5 430 3115 TP0 3 54 04 MSP430P315S TIN 5123 68 J Leaded Ceramic Chip JLCC Package EPROM Only NC internal connection description The MSP430 is ultralow power mixed signal microcontroller family consisting of several devices that feature different sets of modules targeted to various applications The microcontroller is designed to be battery operated for an extended application lifetime With 16 bit RISC architecture 16 bit integrated registers on the CPU and a constant generator the MSP430 achieves maximum code efficiency The digitally controlled oscillator together with the frequency locked loop FLL provides a wakeup from a low power mode to active mode in less than 6 us Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet T MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 PRODUCTION DATA information is current as of publication date Copyright 2000 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments i standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 DALLAS TEXAS 75265 1 MSP430x31x MIXED S
8. XBUF The controller system clock has to operate with different requirements according to the application and system conditions Requirements include High frequency in order to react quickly to system hardware requests or events Low frequency in order to minimize current consumption EMI etc Stable frequency for timer applications e g real time clock RTC Enable start stop operation with a minimum delay These requirements cannot all be met with fast frequency high Q crystals or with RC type low Q oscillators The compromise selected for the MSP430 uses a low crystal frequency which is multiplied to achieve the desired nominal operating range f system N 1 x f crystal The crystal frequency multiplication is achieved with a frequency locked loop FLL technique The factor N is set to 31 after a power up clear condition The FLL technique in combination with a digital controlled oscillator DCO provides immediate start up capability together with long term crystal stability The frequency variation of the DCO with the FLL inactive is typically 330 ppm which means that with a cycle time of 1 us the maximum possible variation is 0 33 ns For more precise timing the FLL can be used This forces longer cycle times if the previous cycle time was shorter than the selected one This switching of cycle times makes it possible to meet the chosen system frequency over a long period of time The start up operation of the sys
9. gt 50 1 VB Segment control gt 2 02 Sn On VB Segment control LCDCTL LCDM5 6 7 Data LCD RAM bits 0 3 or bits 4 7 LCD OUTPUT COMO0 4 Sn Sn On NOTE The signals VA VB VC and VD come from the LCD module analog voltage generator oo gt VPP Internal gt p TDI Internal TDI VPP gt JTAG 0 Fuse 4 TDO TDI Control TDO TDI lt TDO Internal JTAG Fuse TMS Blow From To JTAG CBT SIG REG Control NOTES A During programming activity and when blowing the JTAG enable fuse the TDI VPP terminal is used to apply the correct voltage source The TDO TDI terminal is used to apply the test input data for JTAG circuitry B The TDI VPP terminal of the P31x and E31x does not have an internal pullup resistor An external pulldown resistor is recommended to avoid a floating node which could increase the current consumption of the device C The TDO TDI terminal is in a high impedance state after POR The P31x and E31x need a pullup or a pulldown resistor to avoid floating a node which could increase the current consumption of the device Figure 9 MSP430P313 E313 P315 S E315 TDI VPP TDO TDI 35 TEXAS INSTRUMENTS 26 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 MECHANICAL DATA DL R PDSO G PLASTIC SMALL OUTLINE PACKAGE 48 P
10. 0 direction Port P0 output Port P0 input Special function SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 35 TEXAS INSTRUMENTS 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 absolute maximum ratingst Voltage applied at Voo0 residen roe e e tret eet se odd ce ded anes Sus 0 3 V to 6 V Voltage applied to any pin referenced to Vss 0 3 V to Vcc 40 3 V Diode current at any device terminal 1 4 7 2 Storage temperature Tstg unprogrammed device 55 C 150 Storage temperature programmed device 40 to 85 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE All voltages referenced to 55 recommended operating conditions NOM UNT Supply voltage V MSP430P313 27 5 5 u voltage aurin rogramming RICE a
11. 7 Segmentline 518 or digital output port O18 group 5 LCD S22 O22 S23 O23 4849 Segment lines S22 to S23 or digital output port 022 to O23 group 6 LCD S26 O26 Ea Segment line S26 or digital output port O26 group 7 LCD S27 O27 CMPI Segment line S27 or digital output port O27 group 7 can be used as a comparator input port CMPI timer port TeK A Test clock TCK is a clock input terminal for device programming and test TDI VPP 2 Test data input port TDI VPP is used as a data terminal an input for programming voltage TDO TDI 1 lO Test data output port TDO TDI is used as a data output terminal or as data input during programming 911 Test mode select TMS is an input terminal for device programming and iest General purpose 3 state digital output port bit 4 timer port s IXBUF 6 Clock signa output of 80 clock MCLK or crystal clock ACLK O T MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 functional block diagram MSP430C311S and MSP430P315S TDI VPP TDO TDI TMS TCK Oscillator FLL System Clock 128 512B RAM Power On Test _
12. 9 47 58 08 46 s7 07 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 MECHANICAL DATA FZ S CQCC J J LEADED CERAMIC CHIP CARRIER 28 LEAD SHOWN 0 040 1 02 x 45 Seating Plane 0 180 4 57 0 155 3 94 0 140 3 55 0 120 3 05 0 050 1 27 v 0 032 0 81 at Seating 0 026 0 66 Plane 0 020 0 51 0 014 0 36 w A 0 025 0 64 R TYP M 0 040 1 02 MIN 0 120 3 05 0 090 2 29 JEDEC NO OF OUTLINE PINS MO 087AA 28 MO 087AB 44 MO 087AC 52 MO 087AD 4040219 B 03 95 NOTES A Alllinear dimensions are in inches millimeters B This drawing is subject to change without notice C This package can be hermetically sealed with a ceramic lid using glass frit 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the rightto make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those
13. E Timer Port enable signal BTIE Basic Timer1 enable signal interrupt flag register 1 and 2 Address 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 1 rw 0 WDTIFG Set on overflow or security key violation OR Reset power on or reset condition at RST NMI pin OFIFG Flag set on oscillator fault PO OIFG Dedicated I O P0 0 P0 1 or 8 Bit Timer Counter RXD NMIIFG Signal at RST NMI pin Address 7 6 5 4 3 2 1 0 rw BTIFG Basic Timer1 flag module enable register 1 and 2 Address 7 6 5 4 3 2 1 0 Address 7 6 5 4 3 2 1 0 Legend rw Bit can be read and written Bit can be read and written It is reset by PUC rw 0 EE SFR bit is not present in device 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 memory organization MSP430C311S MSP430C312 MSP430C313 MSP430C314 MSP430C315 FFFFh FFFFh FFFFh FFFFh FFFFh Int Vector Int Vector Int Vector Int Vector Int Vector FFE0h FFE0h FFE0h FFE0h FFE0h 12 kB ROM FFDFh 2 kB ROM FFDFh FFDFh F800h 4kB ROM F000h FFDFh FFDFh D000h 16 kB ROM u 03FFh o200n 5128 RAM o200n 5128 027Fh 02FFh 02FFh 1288 o200n 2568 RAM o2oon 2568 RAM 01FFh 46b per O1FFh 416p Per O1FFh per O1FFh i16p Per O1FFh 46b Per 0100h 0100h 0100h 0100h 0100h 0010h 0010h 0010h 0010h 0010h 000Fh 000Fh 000
14. Fh 000Fh 000Fh 0000h 0000h 0000h 0000h 0000h MSP430P315 MSP430P313T MSP430P315S PMS430E313T PMS430E315 FFFFh FFFFh Int Vector Int Vector preon int Vector int Vector FFDFh FFDFh 8 or EPROM E000h C000h 03FFh 0200h 0100h 0100h 0010h 0010h 02FFh 512B RAM 000Fh 0000h 0000h T MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 peripherals Peripherals connected to the CPU through a data address and control busses can be handled easily with instructions for memory manipulation oscillator and system clock Two clocks usedin the system the system master clock MCLK and the auxiliary clock ACLK The MCLK is a multiple ofthe ACLK The ACLK runs with the crystal oscillator frequency The special design ofthe oscillator supports the feature of low current consumption and the use of a 32 768 Hz crystal The crystal is connected across two terminals without requiring any other external components The oscillator starts after applying VCC due to a reset of the control bit OscOff in the status register SR It can be stopped by setting the OscOff bit to a 1 The enabled clock signals ACLK ACLK 2 ACLK 4 or MCLK are accessible for use by external devices at output terminal
15. IGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 description continued Typical applications include sensor systems that capture analog signals converting them to digital values and then processes the data and displays them or transmits them to a host system The timer port module provides single slope A D conversion capability for resistive sensors AVAILABLE OPTIONS PACKAGED DEVICES TA MSP430C312IDL MSP430C313IDL MSP430C311SIDL MSP430C314IDL 0 19856 MSP430P315SIDL MSP430C315IDL MSP430P313IDLT MSP430P315IDL m PMS430E313FZT 5 PMS430E315FZ T MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 functional block diagram MSP430C312 313 314 315 and MSP430P3131 315 and PMS430E313 315 XIN XBUF Vec Vss RST NMI P0 0 7 4 8 12 16 kB ROM ACLK 8 16 kB 256 512 B Power On OPT or EPROM RAM Reset C ROM P OTP Oscillator FLL System Clock 8 Bit Timer Port Counter O s All With Serial Protocol Pad nterr Cap Support Int Vectors TDI VPP E EPROM TDO TDI MAB MAB 4 Bit CPU Test Incl 16 Reg JTAG m m DB 16 Bi M SBN 7 Z Bus gt Conv TMS TCK Watchdog Timer Port Basic ications Timer1 Timer i ions 0 3 onv S0 18 22 23 26 15 16 Bit Timer O2 18 22 23 26 27 027 CMPI 35 TEXAS INST
16. IN SHOWN 0 025 0 635 0 012 0 305 0 008 0 203 0 005 0 13 0 006 0 15 NOM 7 59 7 39 0 420 10 67 0 395 10 03 0 040 1 02 0 020 0 51 Seating Plane 0 110 2 79 MAX 0 008 0 20 NE 0 004 0 10 PINS 4040048 D 08 97 NOTES A Alllinear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MO 118 com 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 PMS430E313T PMS430E315 FZ package FZ PACKAGE TOP VIEW 5 2 5 25 8555055 S00 E FE O O O On Z Z L IL JL JL JL JL JL JL JL JU JL JL IL JE JL 9 87 6 5 4 8 2 1 68 67 66 65 64 63 62 61 NC 10 e eo NC NCH 11 59 523 023 NC No internal connection T MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 35 TEXAS INSTRUMENTS 28 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 58 522 022 57 S18 O18 5e S17 O17 55 516 016 54 S15 015 53 514 014 52 513 013 51 512 012 511 011 49 510 010 48 59 0
17. MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 Low Supply Voltage Range 2 5 V 5 5 V DL PACKAGE 56 PIN TOP VIEW e UltraLow Power Consumption TDO TDI Low Operation Current 400 uA at 1 MHz TDIVPP 3V TMS Five Power Saving Standby UE 1 3 RAM Retention Off Mode 0 1 HA Wakeup From Standby Mode 6 us Xout TCLK e 16 Bit RISC Architecture 300 ns Instruction P0 0 P0 1 RXD Cycle Time P0 2 TXD Single Common 32 kHz Crystal Internal P0 4 System Clock up to 3 3 MHz BE Integrated LCD Driver for up to 64 or 92 3509 Segments TED A Slope A D Converter With External Hsc Components 05 Serial Onboard Programming NC Program Code Protection by Security Fuse Family Members Include DL PACKAGE MSP430C311S 2k Byte ROM 128 Byte RAM E PIN TOP VIEW MSP430C312 4k Byte ROM 256 Byte RAM s MSP430C313 8k Byte ROM 256 Byte RAM _ TCK COM MSP430C314 12k Byte ROM 512 Byte RAM RS TAMI COMO MSP430C315 16k Byte ROM 512 Byte RAM Vss SZ7 O27ICMPI MSP430P313 8k Byte 256 Byte RAM Vas MSP430P315 16k Byte OTP 512 Byte RAM pos SOCIIS MSP430P315S 16k Byte OTP 512 ByteRAM Xout TCLK 515 015 P0 1 RXD S14 O14 EPROM Version Available for Prototyping ae ee PMS430E313FZT PMS430E315FZ P0 4 S11 011 P0 5 510 010 e Available P0 6 S9 O9 56 Pin
18. O27 CMPI Segment line S27 or digital output port O27 group 7 can be used as a comparator input port CMPI timer port TK 8 Test clock TCK is a clock input terminal for device programming and test TDI VPP 1 EN Test data input port TDI VPP is used as a data input terminal or an input for programming voltage TDO TDI 48 lO Test data output port TDO TDI is used as a data output terminal or as a data input during programming ms 2 _ Test mode select san input terminal for device programming andtest General purpose 3 state digital output port bit 3 timer port Mec sas VS AT emeen j XBU 5 Clock zidna output of Sytem clock MCLK or crystal clock ACLK 971 I i 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 short form description processing unit The processing unit is based on a consistent and orthogonal designed CPU and instruction set This design structure results in a RISC like architecture highly transparent to the application development and distinguishable by the ease of programming All operations other than program flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operand CPU Program Counter PC RO Sixteen registers located
19. RUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 Terminal Functions MSP430C312 5 430 3131 MSP430C314 MSP430C315 MSP430P313t MSP430P315 56 pin SSOP package TERMINAL y o DESCRIPTION NAME NO CIN 27 EM Counter enable CIN input enables counter TPCNT1 timer port 0 52 55 O Common output pins 0 are used for LCD back planes P0 0 13 General purpose digital I O pin P0 1 RXD 14 General purpose digital I O pin receive data input port 8 bit timer counter P0 2 TXD 15 General purpose digital I O pin transmit data output port 8 bit timer counter P0 3 P0 7 16 20 Five general purpose digital I O pins bit 3 7 R23 9 Input of second positive analog LCD level V2 LCD R13 10 1 Input of third positive analog LCD level of V4 LCD RST NMI 5 Reset input nonmaskable interrupt input S0 29 Segment line S0 LCD 51 30 0 1 LCD S2 O2 S5 O5 31 34 Segment lines S2 to S5 or digital output port O2 to O5 group 1 LCD S6 06 S9 O9 35 38 O Segment lines S6 to 59 or digital output port to O9 group 2 LCD 10 010 13 013 39 42 Segmentlines S10 to S13 or digital output port O10 to O13 group 3 LCD 14 014 17 017 43 46 O Segment lines S14 to 517 or digital output port O14 to O17 group 4 LCD 518 018 4
20. S NOM UNIT f TCK TCK frequency JTAG Test Pullup resistors on TMS TCK TDI see Note 15 Fuse blow voltage C versions see Note 15 R TEST lt T v Fuse blow voltage E P versions JTAG Fuse see Note 16 See Note 17 Supply current on TDI VPP to blow fuse Time to blow the fuse P313 E313 Programming voltage applied to TDI VPP 11 11 5 P315 S E315 Programming voltage applied to TDI VPP 12 12 5 Current from programming voltage source EPROM E and OTP P versions only see Note 18 Programming time fast algorithm Programming time single pulse V PP ep pps pp __ Pulses for successful programming Erase time wave length 2537 at 15 Ws cm2 UV lamp of 12 mW cm2 Write erase cycles Data retention Ty lt 55 C NOTES 15 The TMS and TCK pullup resistors are implemented in all ROM C and EPROM E versions 16 Once the JTAG fuse is blown no further access to the MSP430 JTAG test feature is possible 17 The voltage supply to blow the JTAG fuse is applied to TDI VPP pin when fuse blowing is desired 18 Referto the Recommended Operating Conditions for the correct Vcc during programing 35 TEXAS INSTRUMENTS 22 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 TYPICAL CHARACTERISTICS JTAG fuse check mode MSP430 devices that have the fuse on the TDI VPP termin
21. T VIT standard inputs TCK TMS TDI RST NMI PARAMETER TEST CONDITIONS V Low level input voltage AES zb Vec 3 V 5 V VIH High level input voltage V High level output voltage Wh 2 2 9 loH 15mA Vcc 5V SeeNote5 4 5 mA Vcc 5V SeeNote6 IOL 1 2 mA Voc 3V SeeNote5 IOL 3 5 mA 3 SeeNote6 VoL Low level output voltage loL 1 5 mA Voc 5V SeeNote5 IOL 4 5 mA Voc 5V SeeNote6 NOTES 5 Themaximum total current and Io max for all outputs combined should not exceed 9 6 mA to hold the maximum voltage drop specified 6 The maximum total current and max for all outputs combined should not exceed 20 mA to hold the maximum voltage drop specified leakage current see Note 7 Timer port VTpQ x Vss High impedance leakage current timer port Voc 3 VV see Note 8 527 leakage current S27 7 Vss to Voc Voc 3 5 V 5 lt lt lkg POx Leakage current port 0 c tenets NGC nA NOTES 7 The leakage current is measured with Vss or Vcc applied to the corresponding pin s unless otherwise noted 8 Alltimer port pins TP0 0 to TP0 5 are Hi Z Pins CIN and TP 0 to 5 are connected together during leakage current measurement In the leakage measurement the input CIN is included The input voltage is Vss or Vcc 9 The port pin must be selected for input and ther
22. al have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power on reset POR When activated a fuse check current of 1 mA at 3 V 2 5 mA at 5 V can flow from the TDI VPP pin to ground if the fuse is not burned Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low after power up The second positive edge on the TMS pin deactivates the fuse check mode After deactivation the fuse check mode remains inactive until another POR occurs After each POR the fuse check mode has the potential to be activated Time TMS Goes Low After POR Figure 6 Fuse Check Mode Current MSP430P E313 P E315 C31x Care must be taken to avoid accidentally activating the fuse check mode including guarding against EMI ESD spikes that could cause signal edges on the TMS pin Configuration of TMS TCK TDI VPP and TDO TDI pins in applications 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 TYPICAL CHARACTERISTICS DIGITAL CONTROLLED OSCILLATOR FREQUENCY DIGITAL CONTROLLED OSCILLATOR FREQUENCY vs vs OPERATING FREE AIR TEMPERATURE SUPPLY VOLTAGE gt 9 8 8
23. ator faul OFFFCh 14 OFIFG see Notes 1 and 4 Non maskable Dedicated P0 0 P0 0IFG Maskable OFFFAh PO 1IFG Maskable OFFF8h 12 8 Bit Timer Counter e On 9 7 RC1FG RC2FG EN1FG Timer Port see Note 2 Maskable OFFEAh 5 Basic Timer BTIFG Maskable Port 0 2 7 P0 27IFG see Note 1 Maskable OFFEOh 0 lowest NOTES 1 Multiple source flags 2 Timer port interrupt flags are located in the timer port registers 3 Non maskable neither the individual nor the general interrupt enable bit will disable an interrupt event 4 Non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable bit cannot Watchdog Timer 49 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 special function registers Mostinterrupt and module enable bits are collected into the lowest address space Special function register bits that are not allocated to a functional purpose are not physically present in the device Simple software access is provided with this arrangement interrupt enable 1 and 2 Address 7 6 5 4 3 2 1 0 a m m o rw 0 rw 0 rw 0 rw 0 WDTIE Watchdog Timer enable signal OFIE Oscillator fault enable signal 0 Dedicated I O P0 0 POIE 1 P0 1 or 8 Bit Timer Counter RXD Address 7 6 5 4 3 2 1 0 rw 0 rw 0 TPI
24. e fully supported during interrupt event handling An interrupt event awakens the system from each ofthe various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event The clocks used are ACLK and MCLK ACLK is the crystal frequency and MCLK a multiple of ACLK is used as the system clock The software can configure five operating modes Active mode AM The CPU is enabled with different combinations of active peripheral modules Low power mode 0 LPMO The CPU is disabled peripheral operation continues ACLK and MCLK signals are active and loop control for MCLK is active Low power mode 1 LPM1 The CPU is disabled peripheral operation continues ACLK and MCLK signals are active and loop control for MCLK is inactive Low power mode 2 LPM2 The CPU is disabled peripheral operation continues ACLK signal is active and MCLK and loop control for MCLK are inactive Low power mode 3 LPM3 The CPU is disabled peripheral operation continues ACLK signal is active MCLK and loop control for MCLK are inactive and the dc generator for the digital controlled oscillator DCO gt generator is switched off Low power mode 4 LPM4 The CPU is disabled peripheral operation continues ACLK signal is inactive crystal oscillator stopped MCLK and loop control for MCLK are inactive and the dc generator for the DCO is switched off The special functio
25. e must be no optional pullup or pulldown resistor 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 17 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 electrical characteristics over recommended operating free air temperature range unless otherwise noted continued optional resistors individually programmable with ROM code P0 x see Note 10 PARAMETER TEST CONDITIONS MIN NOM Voc 3 V 5 V 4 2 Voc 3 5 3 1 Resistors individually programmable with ROM code all port pins 3 values applicable for pulldown and pullup 38 7 5 Ropt NOTE 10 Optional resistors Roptx for pull down or pull up are not programmed in standard OTP EPROM devices 13 MSP430P313 E313 not recommended for new designs replaced by MSP430P315 E315 and P E315 s inputs P0 x CIN TP 5 output XBUF PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Port t int External interrupt timing External trigger signal for the 3 V 5V 1 5 cycle interrupt flag see Notes 11 and 12 Input frequency o PO x CIN TP 5 High level or low level time or t L f XBUF Clock output frequency XBUF 20 pF XBUF Cj 20 pF f MCLK 1 1 MHz o o Z gt gt o o o o 9 5 S 5 3 7 5 ALS 5 lt Q Q I 9 P e L Duty cycle of clock output fr
26. equency lt gt lt 9 f XBUF f ACLK n 3V SV NOTES 11 The external signal sets the interrupt flag every time tint is met It may be set even with trigger signals shorter than tint The conditions to set the flag must be met independently from this timing constraint Tint is defined in MCLK cycles 12 The external interrupt signal cannot exceed the maximum inut frequency fin crystal oscillator Xin Xout PARAMETER TEST CONDITIONS MIN NOM UNIT C xin Integrated capacitance at input Voc 3 V V C Xout Integrated capacitance at output Voc 23V 5V 35 TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 electrical characteristics over recommended and operating free air temperature range unless otherwise noted continued PARAMETER TEST CONDITIONS NOM UNIT f N 00 0110 0000 FN_4 FN_3 FN_2 0 Vcc 3V 22 ea Dcos 5V 0 18 0 62 2xf NOM 3 2 5 8 1 fpc26 11 0100 0000 FN 4 FN 3 0 FN 2 1 Vcc 5V 3 0 5 1 5 Npco 00 0110 0000 FN 4 0 FN_3 1 EN 2 X Vec 5V T 3xf NOM f N 11 0100 0000 FN 4 0 3 1 2 500737 af 10 Eid 27 Voc 5V 45 13 8 3 0 7 1 85 00 0110 0000 FN 4 1 EN 3 2 Vec 5V 65 21 4xf NOM 3 4 8 13
27. in eight bits except for the interrupt flag register and the interrupt enable register The two least significant bits LSBs of the interrupt flag and interrupt enable registers are located in the special functions register SFR Three interrupt vectors are implemented one for Port0 0 one for 1 and one commonly used for any interrupt event on Port0 2 to Port0 7 The 1 and Port0 2 pin function is shared with the 8 bit timer counter LCD drive Liquid crystal displays LCDs for static 2 3 and 4 MUX operations can be driven directly The controller LCD logic operation is defined by software using memory bit manipulation LCD memory is part of the LCD module and not part of the data memory Eight mode and control bits define the operation and current consumption of the LCD drive The information for the individual digits can be easily obtained using table programming techniques combined with the correct addressing mode The segment information is stored in LCD memory using instructions for memory manipulation The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2 3 and 4 MUX operation Groups of the LCD segment lines can be selected for digital output signals The MSP430x31x has four common signals and 23 segment lines The MSP430C311S and MSP430P315S have four common lines and 16 segment lines Timer Port The Timer Port module has two 8 bit counters an input that t
28. inside the CPU provide reduced instruction execution time This reduces Stack Pointer SP R1 aregister register operation execution time to one cycle of the processor frequency Status Register SR CG1 R2 Four registers are reserved for special use as a Constant Generator CG2 R3 program counter a stack pointer a status register and aconstant generator The remaining ones are General Purpose Register R4 available as general purpose registers General Purpose Register R5 Peripherals connected to the CPU using a data address and control bus can be handled easily with all instructions for memory manipulation General Purpose Register R14 instruction set The instruction set for this register register General Purpose Register R15 architecture provides a powerful and easy to use assembly language The instruction set consists of 51 instructions with three formats and seven addressing modes Table 1 provides a summation and example of the three types of instruction formats the addressing modes are listed in Table 2 Table 1 Instruction Word Formats Dual operands source destination e g ADD R4 R5 R4 R5 gt R5 Single operands destination only e g CALL R8 PC TOS R8 gt PC Relative jump un conditional e g JNE Jump on equal bit 0 Each instruction that operates on word and byte data is identified by the suffix B Examples Instructions for word operation Instructions for byte operation MOV EDE TONI MOVB
29. ischarge the capacitor The reference resistor s charge or discharge time is represented by counts The unknown resistors Rmeas charge or discharge time is represented by counts The unknown resistor s value Rmeas is the value of Rre multiplied by the relative number of counts Nmeas Nret This value determines resistive sensor values that correspond to the physical data for example temperature when an NTC or PTC resistor is used Basic Timer1 The Basic Timer1 BT1 divides the frequency of MCLK or ACLK as selected with the SSEL bit to provide low frequency control signals This is done within the system by one central divider the basic timer1 to support low current applications The BTCTL control register contains the flags which controls or selects the different operational functions When the supply voltage is applied or when a reset of the device RST NMI pin a watchdog overflow or a watchdog security key violation occurs all bits in the register hold undefined or unchanged status The user software usually configures the operational conditions on the BT1 during initialization The Basic Timer1 has two 8 bit timers which can be cascaded to a 16 bit timer Both timers can be read and written by software Two bits in the SFR address range handle the system control interaction according to the function implemented in the Basic Timer1 These two bits are the Basic Timer1 interrupt flag BTIFG and the basic ti
30. mer interrupt enable BTIE bit Watchdog Timer The primary function of the Watchdog Timer WDT module is to perform a controlled system restart after a software problem has occurred If the selected time interval expires a system reset is generated If this watchdog function is not needed in an application the module can work as an interval timer which generates an interrupt after the selected time interval The Watchdog Timer counter WDTCNT is 15 16 bit up counter which is not directly accessible by software The WDTONT is controlled using the Watchdog Timer control register WDTCTL which is a 16 bit read write register Writing to WDTCTL in both operating modes watchdog or timer is only possible by using the correct password in the high byte The low byte stores data written to the WDTCTL The high byte password is 05Ah If any value other than 05Ah is written to the high byte of the WDTCTL a system reset is generated When the password is read its value is 069h This minimizes accidental write operations to the WDTCTL register In addition to the Watchdog Timer control bits there are two bits included in the WDTCTL which configure the NMI pin 8 Bit Timer Counter The 8 bit interval timer supports three major functions for the application Serial communication or data exchange Pulse counting or pulse accumulation Timer The 8 bit Timer Counter peripheral includes the following major blocks an 8 bit up coun
31. n registers SFR include module enable bits that stop or enable the operation of the specific peripheral module All registers of the peripherals may be accessed if the operational function is stopped or enabled However some peripheral current saving functions are accessed through the state of local register bits An example is the enable disable of the analog voltage generator in the LCD peripheral which is turned on or off using one register bit 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 operation modes and interrupts continued The most general bits that influence current consumption and support fast turn on from low power operating modes are located in the status register SR Four of these bits control the CPU and the system clock generator SCG1 SCGO OscOff and 15 9 8 7 0 Reserved For Future rw 0 rw 0 rw 0 0 0 0 rw 0 rw 0 rw 0 rw 0 rw rw rw interrupt vector addresses The interrupt vectors and the power up starting address are located in the ROM with an address range of OFFFFh OFFEOh The vector contains the 16 bit address of the appropriate interrupt handler instruction sequence INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power up external reset watchdog WDTIFG see Note 1 OFFFEh 15 highest NMIIFG see Notes 1 and 3 Nonmaskable NMI oscill
32. ne MSP430P315 4 5 5 5 Supply voltage VSS f MSP430C31x Operating free air temperature range TA MSP430P31x c Processor frequency f system signal MCLK fsystem Low level input voltage VIL eee Xin pem t MSP430P313 E313 recommended for new designs replaced by MSP430P315 E315 f MHz 3 3 Minimum f system Maximum Processor Frequency MHz N N Vcc Supply Voltage V NOTE Minimum processor frequency is defined by system clock Figure 1 Processor Frequency vs Supply Voltage C Versions vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 15 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 f MHz 3 3 2 2 1 5 Minimum f system Maximum Processor Frequency MHz Vcc Supply Voltage V NOTE Minimum processor frequency is defined by system clock Figure 2 Processor Frequency vs Supply Voltage P E Versions electrical characteristics over recommended operating free air temperature range unless otherwise noted supply current into Vcc excluding external current f system 1 MHz PARAMETER TEST CONDITIONS TA 409 85 C 5 3 V Active mode 40 C 85 C 5 3 P315 S 40 C 85 C 5 C31x 40 C 85 C e 5
33. ounter starts counting after start bit condition is detected The first signal level is sampled into the RXD input data latch after completing the first timing interval which is programmed into the counter Two latches used for input and output data RXD FF and TXD FF are clocked by the counter after the programmed timing interval has elapsed UART The serial communication is realized by using software and the 8 bit timer counter hardware The hardware supports the output of the serial data stream bit by bit with the timing determined by the counter The software hardware interface connects the mixed signal controller to external devices systems or networks peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog Timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS EPROM control EPCTL 054h Crystal buffer control CBCTL 053h SCG frequency control SCFQCTL 10528 SCG frequency integrator SCFI1 051h SCG frequency integrator SCFIO 050h Timer Port Timer Port enable TPE Timer Port data TPD Timer Port counter2 TPCNT2 Timer Port counter1 TPCNT1 Timer Port control TPCTL 8 Bit Timer Counter 8 Bit Timer Counter data 8 Bit Timer Counter preload 8 Bit Timer Counter control Basic Timer Counter2 BTCNT2 Basic Timer Counter1 BTCNT1 Basic Timer control BTCTL LCD memory 15 LCDM15 LCD memory1 LCDM1 LCD control amp mode LCDCTL Port P0 Port P0 interrupt enable Port P0 interrupt edge select Port P0 interrupt flag Port P
34. pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
35. riggers one counter and six digital outputs in the MSP430x31x MSP430C311S MSP430C315S have five digital outputs available on external pins with high impedance state capability Both counters have an independent clock selector for selecting an external signal or one of the internal clocks ACLK or MCLK One counter has an extended control capability to halt count continuously or gate the counter by selecting one of two external signals This gate signal sets the interrupt flag if an external signal is selected and the gate stops the counter Both timers can be read from and written to by software The two 8 bit counters can be cascaded to a 16 bit counter A common interrupt vector is implemented The interrupt flag can be set from three events in the 8 bit counter mode gate signal overflow from the counters or from two events in the 16 bit counter mode gate signal overflow from the MSB of the cascaded counter 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 peripherals continued slope A D conversion Slope A D conversion is accomplished with the timer port module using external resistor s for reference Ryef external resistor s to the measured Rmeas and an external capacitor The external components are driven by software in such a way that the internal counter measures the time that is needed to charge or d
36. tem clock depends on the previous machine state During a power up clear PUC the DCO is reset to its lowest possible frequency The control logic starts operation immediately after removal of the PUC condition Correct operation of the FLL control logic requires the presence of a stable crystal oscillator ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 peripherals continued digital 1 0 There is one eight bit I O port Port0 that is implemented MSP430C311S and MSP430P315S have six bits available on external pins Six control registers give maximum digital input output flexibility to the application All individual I O bits are programmable independently Any combination of input output and interrupt conditions is possible Interrupt processing of external events is fully implemented for all eight bits of port PO Provides read write access to all registers with all instructions The six registers are Input register 8 bits contains information at the pins Output register 8 bits contains output information Direction register 8 bits controls direction Interrupt flags 6 bits indicates if interrupt s are pending Interrupt edge select 8 bits contains input signal change necessary for interrupt 9 Interrupt enable 6 bits contains interrupt enable bits All these registers conta
37. ter with preload register an 8 bit control register an input clock selector an edge detection e g start bit detection for asynchronous protocols and an input and output data latch triggered by the carry out signal from the 8 bit counter The 8 bit counter counts up with an input clock which is selected by two control bits from the control register The four possible clock sources are MCLK ACLK the external signal from terminal PO 1 and the signal from the logical AND of MCLK and terminal PO 1 vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 13 MSP430x31x MIXED SIGNAL MICROCONTROLLERS SLAS165D FEBRUARY 1998 REVISED APRIL 2000 8 Bit Timer Counter continued Two counter inputs load enable control the counter operation The load input controls load operations write access to the counter results in loading the content of the preload register into the counter The software writes or reads the preload register with allinstructions The preload register acts as a buffer and can be written immediately after the load of the counter is completed The enable input enables the count operation When the enable signal is to high the counter will count up each time a positive clock edge is applied to the clock input of the counter Serial protocols like UART protocol need start bit edge detection to determine at the receiver the start of a data transmission When this function is activated the c

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