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TEXAS INSTRUMENTS TPS5430/TPS5431 handbook

1. Exposed Thermal Pad Top View NOTE All linear dimensions are in millimeters Exposed Thermal Pad Dimensions 4206322 3 G 08 07 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to T s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with T s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied
2. It is very important that the maximum ratings for voltage and current are not exceeded under any circumstance Additionally some bulk capacitance may be needed especially if the TPS5430 circuit is not located within about 2 inches from the input voltage source The value for this capacitor is not critical but it also should be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage is acceptable 12 Submit Documentation Feedback I TPS5430 si TEXAS TPS5431 INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 Output Filter Components Two components need to be selected for the output filter L1 and C2 Since the TPS5430 is an internally compensated device a limited range of filter component types and values can be supported Inductor Selection To calculate the minimum value of the output inductor use Equation 4 w VouT MAX gt NS a Vour MIN V x K x OUT x Fow m IN max Knp Is a coefficient that represents the amount of inductor ripple current relative to the maximum output current Three things need to be considered when determining the amount of ripple current in the inductor the peak to peak ripple current affects the output ripple voltage amplitude the ripple current affects the peak switch current and the amount of ripple current determines at what point the circuit becomes discontinuous For designs using the TPS5430 Knp of 0 2 t
3. SUPPLY VOLTAGE VIN PIN lo Quiescent current PTa auer Noah jj ma Shutdown ENA 0 V 18 50 uA UNDERVOLTAGE LOCK OUT UVLO Start threshold voltage UVLO 5 3 5 5 V Hysteresis voltage UVLO 330 mV VOLTAGE REFERENCE Ty 25 C 1 202 1 221 1 239 Voltage reference accuracy V Ip 0A 3A 1 1906 1 221 1 245 OSCILLATOR Internally set free running frequency 400 500 600 kHz Minimum controllable on time 150 200 ns Maximum duty cycle 87 89 ENABLE ENA PIN Start threshold voltage ENA 1 3 V Stop threshold voltage ENA 0 5 V Hysteresis voltage ENA 450 mV Internal slow start time 0 100 6 6 8 10 ms CURRENT LIMIT Current limit 4 5 6 A Current limit hiccup time 13 16 20 ms THERMAL SHUTDOWN Thermal shutdown trip point 135 162 C Thermal shutdown hysteresis 14 G OUTPUT MOSFET I VIN 5 5V 150 ps High side power MOSFET switch 110 230 ma Submit Documentation Feedback 3 TPS5430 TPS5431 A Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 PIN ASSIGNMENTS DDA PACKAGE TOP VIEW BOOT PH NC VIN NC GND VSENSE ENA TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO BOOT 1 Boost capacitor for the high side FET gate driver Connect 0 01 uF low ESR capacitor from BOOT pin to PH pin NC 2 3 Not connected internally VSENSE 4 Feedback voltage for the regulator Connect to output voltage divider ENA 5 On off control Below 0 5 V the device stops switching Float th
4. The dc voltage and ripple current ratings cannot be exceeded The ESR is important because along with the inductor ripple current it determines the amount of output ripple voltage The actual value of the output capacitor is not critical but some practical limits do exist Consider the relationship between the desired closed loop crossover frequency of the design and LC corner frequency of the output filter Due to the design of the internal compensation it is desirable to keep the closed loop crossover frequency in the range 3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation For this design example it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHz and also below the ESR zero of the output capacitor Under these conditions the closed loop crossover frequency is related to the LC corner frequency by f 2 CO 85Vour And the desired output capacitor value for the output filter to Submit Documentation Feedback 13 TPS5430 TPS5431 A Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 o 1 Cour 3357 x Lour X fco X Vout 8 For a desired crossover of 18 kHz and a 15 uH inductor the calculated value for the output capacitor is 220 uF The capacitor type should be chosen so that the ESR zero is above the loop crossover The maximum ESR should be 1 ESR MAX 21 X Court x foo 9 The maximum ESR of the ou
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6. with a reverse voltage of 40 V forward current of 3 A and a forward voltage drop of 0 5 V Additional Circuits Figure 12 and Figure 13 show application circuits using wide input voltage ranges The design parameters are similar to those given for the design example with a larger value output inductor and a lower closed loop crossover frequency U1 c2 L1 10 35 V TPS5430DDA TP6 22 uH 0 01 uF H VIN 1 VOUT I C3 Sanyo POSCAP 10TP220M R2 3 24 kQ Figure 12 10 35 V Input to 5 V Output Application Circuit U1 c2 L1 9 21 V TPS5431DDA 18 uH VIN 0 01 uF H 1 VOUT D1 C3 B340A T 220 uF C3 Sanyo POSCAP 10TP220M 3 24 kO Figure 13 9 21 V Input to 5 V Output Application Circuit Circuit Using Ceramic Output Filter Capacitors Figure 14 shows an application circuit using all ceramic capacitors for the input and output filters which generates a 3 3 V output from a 10 V to 24 V input The design procedure is similar to those given for the design example except for the selection of the output filter capacitor values and the design of the additional compensation components required to stabilize the circuit Submit Documentation Feedback 15 TPS5430 TPS5431 Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 U1 VIN 10 24 V TPS5430DDA a VIN VOUT D1 L c3 MRBS340 Figure 14 Ceramic Output Filter Capacitors Circuit Output Filter Co
7. 11 Where Nc is the number of output capacitors in parallel Fsw is the switching frequency Other capacitor types can be used with the TPS5430 depending on the needs of the application Output Voltage Setpoint The output voltage of the TPS5430 is set by a resistor divider R1 and R2 from the output to the VSENSE pin Calculate the R2 resistor value for the output voltage of 5 V using Equation 12 R2 i OUT 12 For any TPS5430 design start with an R1 value of 10 kQ R2 is then 3 24 kQ Boot Capacitor The boot capacitor should be 0 01 uF 14 Submit Documentation Feedback TPS5430 si TEXAS TPS5431 INSTRUMENTS Www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 Catch Diode The TPS5430 is designed to operate using an external catch diode between PH and GND The selected diode must meet the absolute maximum ratings for the application Reverse voltage must be higher than the maximum voltage at the PH pin which is VINMAX 0 5 V Peak current must be greater than IOUTMAX plus on half the peak to peak inductor current Forward voltage drop should be small for higher efficiencies It is important to note that the catch diode conduction time is typically longer than the high side FET on time so attention paid to diode parameters can make a marked improvement in overall efficiency Additionally check that the device chosen is capable of dissipating the power losses For this design a Diodes Inc B340A is chosen
8. on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release Addendum Page 1 K TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 31 Oct 2008 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis OTHER QUALIFIED VERSIONS OF TPS5430 e Automotive TPS5430 Q1 NOTE Qualified Version Definitions e Automotive Q100 devices qualified for high reliability automotive applications targeting zero defects Addendum Page 2 TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 31 Oct 2008 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS A Reel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Y Overall width of the carrier tape Pitch between successive ca
9. the top layer directly underneath the IC with an exposed area for connection to the PowerPAD Use vias to connect this ground area to any internal ground planes Use additional vias at the ground side of the input and output filter capacitors as well The GND pin should be tied to the PCB ground by connecting it to the ground area under the device as shown below The PH pin should be routed to the output inductor catch diode and boot capacitor Since the PH connection is the switching node the inductor should be located very close to the PH pin and the area of the PCB conductor minimized to prevent excessive capacitive coupling The catch diode should also be placed close to the device to minimize the output current loop area Connect the boot capacitor between the phase node and the BOOT pin as shown Keep the boot capacitor close to the IC and minimize the conductor trace lengths The component placements and connections shown work well but other connection routings may also be effective Connect the output filter capacitor s as shown between the VOUT trace and GND It is important to keep the loop formed by the PH pin Lout Cout and GND as small as is practical Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage Do not route this trace too close to the PH trace Due to the size of the IC package and the device pin out the trace may need to be routed under the output capacitor Alternately the
10. thermal pad on the board Refer to Technical Brief PowerPad Thermally Enhanced Package Texas Instruments Literature No SLMA002 for information regarding recommended board layout This document is available at www ti com lt http www ti com gt PowerPAD is a trademark of Texas Instruments si TEXAS INSTRUMENTS www ti com K3 Texas THERMAL PAD MECHANICAL DATA et com DDA R PDSO G8 THERMAL INFORMATION This PowerPAD package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink The thermal pad must be soldered directly to the printed circuit board PCB After soldering the PCB can be used as a heatsink In addition through the use of thermal vias the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device or alternatively can be attached to a special heatsink structure designed into the PCB This design optimizes the heat transfer from the integrated circuit IC For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities refer to Technical Brief PowerPAD Thermally Enhanced Package Texas Instruments Literature No SLMA002 and Application Brief PowerPAD Made Easy Texas Instruments Literature No SLMAQ04 Both documents are available at www ti com The exposed thermal pad dimensions for this package are shown in the following illustration
11. voltage of an external resistor divider network to the VSENSE pin In steady state operation the VSENSE pin voltage should be equal to the voltage reference 1 221 V The TPS5430 TPS5431 implements internal compensation to simplify the regulator design Since the TPS5430 TPS5431 uses voltage mode control a type 3 compensation network has been designed on chip to provide a high crossover frequency and a high phase margin for good stability See the Internal Compensation Network in the applications section for more details Voltage Feed Forward The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input voltage This greatly simplifies the stability analysis and improves the transient response Voltage feed forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constant at the feed forward gain i e VIN Feed Forward Gain Panic aMP ok pk The typical feed forward gain of TPS5430 TPS5431 is 25 Pulse Width Modulation PWM Control The regulator employs a fixed frequency pulse width modulator PWM control method First the feedback voltage VSENSE pin voltage is compared to the constant voltage reference by the high gain error amplifier and compensation network to produce a error voltage Then the error voltage is compared to the ramp voltage by the PWM comparator In this way the error voltage magnitude is converted to a pul
12. 1 These designs are based on certain assumptions and will tend to always select output capacitors within a limited range of ESR values If a different capacitor type is desired it may be possible to fit one to the internal compensation of the TPS5430 TPS5431 Equation 23 gives the nominal frequency response of the internal voltage mode type Ill compensation network S S 1 ze x 1 srir H s s s s s 515550 A i j eee i i j opr Where FpO 2165 Hz Fz1 2170 Hz Fz2 2590 Hz Fp1 24 kHz Fp2 54 kHz Fp3 440 kHz Fp3 represents the non ideal parasitics effect Using this information along with the desired output voltage feed forward gain and output filter characteristics the closed loop transfer function can be derived Thermal Calculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations They should not be used if the device is working at light loads in the discontinuous conduction mode Conduction Loss Pcon lour X Rds on x Vour ViN Switching Loss Psw V X lour x 0 01 Quiescent Current Loss Pq V x 0 01 Total Loss Ptot Pcon Psw Pq Given T gt Estimated Junction Temperature T Ta Rth x Ptot Given Tmax 125 C gt Estimated Maximum Ambient Temperature Tamax Tumax Rth x Ptot Submit Documentation Feedback TPS5430 si TEXAS TPS5431 INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOV
13. Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Clocks and Timers www ti com clocks Digital Control www ti com digitalcontrol Interface interface ti com Medical www ti com medical Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Telephony www ti com telephony RF IF and ZigBee Solutions www ti com lprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
14. EMBER 2006 PERFORMANCE GRAPHS The performance graphs Figure 15 through Figure 21 are applicable to the circuit in Figure 11 Ta 25 C unless otherwise specified 100 0 3 0 2 95 0 1 90 Efficiency 85 Output Regulation 80 75 1 1 5 2 2 5 3 0 0 5 0 0 5 1 1 5 2 2 5 3 3 5 lo Output Current A lo Output Current A Figure 15 Efficiency vs Output Current Figure 16 Output Regulation vs Output Current Vin 77100 mV Div AC Coupled sites VibiG Input Regulation 1 1 10 8 13 8 16 8 19 8 t Time 500 ns Div V Input Voltage V Figure 17 Input Regulation vs Input Voltage Figure 18 Input Voltage Ripple and PH Node lo 3 A Submit Documentation Feedback 19 TPS5430 TPS5431 A Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 Vou 20 mV Div AC Coupled 1 Vour 50 mV Div AC Coupled t Time 500 ns Div t Time 200 ps Div Figure 19 Output Voltage Ripple and PH Node lo 3A Figure 20 Transient Response lo Step 0 75 to 2 25 A Vin 5 VIDiv t Time gt 2 ms Div _ Figure 21 Startup Waveform Vin and Vout 20 Submit Documentation Feedback K TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 31 Oct 2008 PACKAGING INFORMATION Orderable Device
15. MPERATURE 80 9 Vi 12V 70 e 60 F 2 8 5 y 5 wo 8 130 s 5 5 q 20 8 110 7 5 a n 00 2 90 7 80 50 235 0 25 50 75 100 125 50 25 o 25 50 75 100 125 Ty Junction Temperature C Ty Junction Temperature C Figure 5 Figure 6 Submit Documentation Feedback 5 TPS5430 TPS5431 43 Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS continued MINIMUM CONTROLLABLE ON TIME MINIMUM CONTROLLABLE DUTY RATIO vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 180 TT g 170 7 75 E x 8 1 5 150 7 50 8 5 E 140 7 25 Z 130 7 os ee ee 120 50 25 0 25 50 75 100 125 50 25 o 25 50 75 100 125 T Junction Temperature C Ty Junction Temperature C Figure 7 Figure 8 6 Submit Documentation Feedback TPS5430 si TEXAS TPS5431 INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN m r r m Y n 1 221 V Band SHDN Boot Perce T Hiccup Regulator BOOT l ENA m SHDN SHDN gt I VSENSE 17 H w miO SA Y Ramp NC T VINT Generator Feed Forward Gain 25
16. Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty TPS5430DDA ACTIVE so DDA 8 100 Green RoHS amp CUNIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5430DDAG4 ACTIVE so DDA 8 100 Green RoHS amp CUNIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5430DDAR ACTIVE so DDA 8 2500 Green RoHS amp CU NIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5430DDARG4 ACTIVE so DDA 8 2500 Green RoHS amp CU NIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5431DDA ACTIVE so DDA 8 100 Green RoHS CUNIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5431DDAG4 ACTIVE so DDA 8 100 Green RoHS amp CUNIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5431DDAR ACTIVE so DDA 8 2500 Green RoHS amp CU NIPDAU Level 1 260C UNLIM Power no Sb Br PAD TPS5431DDARG4 ACTIVE so DDA 8 2500 Green RoHS amp CU NIPDAU Level 1 260C UNLIM Power no Sb Br PAD The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco frien
17. ance the exposed PowerPAD underneath the device must be soldered down to the printed circuit board U1 TPS5430DDA c2 L1 0 01 pF 15 uH sv VOUT 10 8 19 8 V 10 pF R1 10 KQ R2 3 24 ka Figure 11 Application Circuit 12 V to 5 0 V Design Procedure The following design procedure can be used to select component values for the TPS5430 Alternately the SWIFT Designer Software may be used to generate a complete design The SWIFT Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design This section presents a simplified discussion of the design process Submit Documentation Feedback 11 TPS5430 TPS5431 A Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 APPLICATION INFORMATION continued To begin the design process a few parameters must be decided upon The designer needs to know the following e Input voltage range e Output voltage e Input ripple voltage e Output ripple voltage e Output current rating e Operating frequency Design Parameters For this design example use the following as the input parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 10 8 V to 19 8 V Output voltage 5V Input ripple voltage 300 mV Output ripple voltage 30 mV Output current rating 3A Operating frequency 500 kHz 1 As an additional constrain
18. d warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet SWIFT PowerPAD are trademarks of Texas Instruments PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2006 Texas Instruments Incorporated TPS5430 TPS5431 A Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam a during storage or handling to prevent electrostatic damage to the MOS gates ORDERING INFORMATION Ty INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE PART NUMBER 40 C to 125 C 5 5 V to 36 V Adjustable to 1 22 V Thermally Enhanced SOIC DDA TPS5430DDA 40 C to 125 C 5 5 V to 23 V Adjustable to 1 22 V Thermally Enhanced SOIC DDA TPS5431DDA 1 2 For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI web site at www ti com The DDA package is also available taped and reeled Add an R suffix to the device type i e TPS5430DDAR See applications section of data sheet for PowerPAD drawing and layout infor
19. dly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS 8 no Sb Br please check http Avww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS T s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief
20. e TPS5430 there are both upper and lower output voltage limits for any given input voltage The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87 and is given by aura 9 87 X VINMIN lomax 0 230 Vp lomax RL Vp 21 Where Vinmin Minimum input voltage lomax maximum load current Vp catch diode forward voltage R output inductor series resistance This equation assumes maximum on resistance for the internal high side FET The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns The approximate minimum output voltage for a given input voltage and minimum load current is given by Voutmin 9 12 x Vinmax lopin 0 110 Vp lom RL gt Vp 22 Where Vinmax Maximum input voltage lomin minimum load current Vp catch diode forward voltage R output inductor series resistance This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of operating frequency set point Any design operating near the operational limits of the device should be carefully checked to assure proper functionality Submit Documentation Feedback 17 TPS5430 TPS5431 A Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 Internal Compensation Network The design eguations given in the example circuit can be used to generate circuits using the TPS5430 TPS543
21. e pin to enable GND 6 Ground Connect to PowerPAD VIN 7 Input supply voltage Bypass VIN pin to GND pin close to device package with a high quality low ESR ceramic capacitor PH 8 Source of the high side power MOSFET Connected to external inductor and diode PowerPAD 9 GND pin must be connected to the exposed pad for proper operation 4 Submit Documentation Feedback f TPS5430 si TEXAS TPS5431 INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY NON SWITCHING QUIESCENT CURRENT vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE 530 3 5 Vy 2120 520 lt 510 sa gt A 500 490 2 480 9 a 2 75 470 460 2 5 50 25 0 25 50 75 100 125 0 25 0 25 50 75 100 125 T Junction Temperature C Ty Junction T emperature C Figure 1 Figure 2 SHUTDOWN QUIESCENT CURRENT VOLTAGE REFERENCE vs vs INPUT VOLTAGE JUNCTION TEMPERATURE 25 1 230 ENA 0V 2o0 T 125 C gt 1 225 3 15 1 220 2 s i 2 10 1 215 5 1 210 0 5 10 15 20 25 30 35 40 50 25 0 25 50 75 100 125 Vi Input Voltage V T Junction Temperature C Figure 3 Figure 4 ON RESISTANCE INTERNAL SLOW START TIME vs vs JUNCTION TEMPERATURE JUNCTION TE
22. mation ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 2 VALUE UNIT VIN 0 3 to 40 9 TPS5430 BOOT 0 3 to 50 PH steady state 0 6 to 40 9 V Input voltage range VIN 0 3 to 25 TPS5431 BOOT 0 3 to 35 V PH steady state 0 6 to 25 ENA 0 3 to 7 BOOT PH 10 VSENSE 0 3 to 3 PH transient lt 10 ns 1 2 lo Source current PH Internally Limited likg Leakage current PH 10 uA Ty Operating virtual junction temperature range 40 to 150 C Tstg Storage temperature 65 to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 All voltage values are with respect to network ground terminal 2 3 Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating DISSIPATION RATINGS THERMAL IMPEDANCE PACKAGE JUNCTION TO AMBIENT 8 Pin DDA 2 layer board with solder 9 33 C W 8 Pin DDA 4 layer board with solder 4 26 C W Maximum power dissipation may be limited by overcur
23. mponent Selection Using Equation 11 the minimum inductor value is 12 uH A value of 15 uH is chosen for this design When using ceramic output filer capacitors the recommended LC resonant frequency should be no more than 7 kHz Since the output inductor is already selected at 15 uH this limits the minimum output capacitor value to 1 Co MIN gt gt 2x x 7000 x Lo 13 The minimum capacitor value is calculated to be 34uF For this circuit a larger value of capacitor yields better transient response A single 100 uF output capacitor is used for C3 It is important to note that the actual capacitance of ceramic capacitors decreases with applied voltage In this example the output voltage is set to 3 3 V minimizing this effect External Compensation Network When using ceramic output capacitors additional circuitry is required to stabilize the closed loop system For this circuit the external components are R3 C4 C6 and C7 To determine the value of these components first calculate the LC resonant frequency of the output filter 1 Fic 2nV Lo x Co EFF 14 For this example the effective resonant frequency is calculated as 4109 Hz The network composed of R1 R2 R3 C5 C6 and C7 has two poles and two zeros that are used to tailor the overall response of the feedback network to accommodate the use of the ceramic output capacitors The pole and zero locations are given by the following equations 16 Submit Documen
24. n application requires controlling the ENA pin use open drain or open collector output logic to interface with the pin To limit the start up inrush current an internal slow start circuit is used to ramp up the reference voltage from 0 V to its final value linearly The internal slow start time is 8 ms typically Submit Documentation Feedback 7 TPS5430 TPS5431 Texas INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 APPLICATION INFORMATION continued Undervoltage Lockout UVLO The TPS5430 TPS5431 incorporates an undervoltage lockout circuit to keep the device disabled when VIN the input voltage is below the UVLO start voltage threshold During power up internal circuits are held inactive and the internal slow start is grouded until VIN exceeds the UVLO start threshold voltage Once the UVLO start threshold voltage is reached the internal slow start is released and device start up begins The device operates until VIN falls below the UVLO stop threshold voltage The typical hysteresis in the UVLO comparator is 330 mv Boost Capacitor BOOT Connect a 0 01 uF low ESR ceramic capacitor between the BOOT pin and PH pin This capacitor provides the gate drive voltage for the high side MOSFET X7R or X5R grade dielectrics are recommended due to their stable values over temperature Output Feedback VSENSE and Internal Compensation The output voltage of the regulator is set by feeding back the center point
25. ne 5 SHDN A GNP SHDN Oscillator I I L VSENSE OVP gt i POWERPADI 112 5 VREF Gate 3o Driver LH SHDN BOOT PH 1H VOUT TN DETAILED DESCRIPTION Oscillator Freguency The internal free running oscillator sets the PWM switching freguency at 500 kHz The 500 kHz switching frequency allows less output inductance for the same output ripple reguirement resulting in a smaller output inductor Voltage Reference The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit The bandgap and scaling circuits are trimmed during production testing to an output of 1 221 V at room temperature Enable ENA and Internal Slow Start The ENA pin provides electrical on off control of the regulator Once the ENA pin voltage exceeds the threshold voltage the regulator starts operation and the internal slow start begins to ramp If the ENA pin voltage is pulled below the threshold voltage the regulator stops switching and the internal slow start resets Connecting the pin to ground or to any voltage less than 0 5 V will disable the regulator and activate the shutdown mode The quiescent current of the TPS5430 TPS5431 in shutdown mode is typically 18 uA The ENA pin has an internal pullup current source allowing the user to float the ENA pin If a
26. o 0 3 yields good results Low output ripple voltages can be obtained when paired with the proper output capacitor the peak switch current will be well below the current limit set point and relatively low load currents can be sourced before discontinuous operation For this design example use Knp 0 2 and the minimum inductor value is calculated to be 12 5 uH The next highest standard value is 15 uH which is used in this design For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded The RMS inductor current can be found from Equation 5 2 N VouT Vinda Vout x L RMS OUT MAX 12 Vinag Lour Few 08 and the peak inductor current can be determined with Equation 6 Vout Vita u Vour IL PK 7 OUTIMAX TEX ViN x Few 6 MAX X LoUT For this design the RMS inductor current is 3 003 A and the peak inductor current is 3 31 A The chosen inductor is a Sumida CDRH104R 150 15uH It has a saturation current rating of 3 4 A and a RMS current rating of 3 6 A easily meeting these requirements A lesser rated inductor could be used however this device was chosen because of its low profile component height In general inductor values for use with the TPS5430 are in the range of 10 uH to 100 uH Capacitor Selection The important design factors for the output capacitor are dc voltage rating ripple current rating and equivalent series resistance ESR
27. rent protection Power rating at a specific ambient temperature T should be determined with a junction temperature of 125 C This is the point where distortion starts to substantially increase Thermal management of the final PCB should strive to keep the junction temperature at or below 125 C for best performance and long term reliability See Thermal Calculations in applications section of this data sheet for more information Test board conditions a 3 in x 3 in 2 layers thickness 0 062 inch b 2 oz copper traces located on the top and bottom of the PCB c 6 thermal vias in the PowerPAD area under the device package Test board conditions a 3inx 3 in 4 layers thickness 0 062 inch b 2 oz copper traces located on the top and bottom of the PCB c 2 oz copper ground planes on the 2 internal layers d 6 thermal vias in the PowerPAD area under the device package Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com RECOMMENDED OPERATING CONDITIONS TPS5430 TPS5431 SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 MIN NOM MAX UNIT TPS5430 5 5 36 VIN Input voltage range V TPS5431 5 5 23 Ty Operating junction temperature 40 125 C ELECTRICAL CHARACTERISTICS T 40 C to 125 C VIN 12 0 V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
28. resistance high side N channel MOSFET Included on the substrate with the listed features are a high performance voltage error amplifier that provides tight voltage regulation accuracy under transient conditions an undervoltage lockout circuit to prevent start up until the input voltage reaches 5 5 V an internally set slow start circuit to limit inrush currents and a voltage feed forward circuit to improve the transient response Using the ENA pin shutdown supply current is reduced to 18 HA typically Other features include an active high enable overcurrent limiting overvoltage protection and thermal shutdown To reduce design complexity and external component count the TPS5430 TPS5431 feedback loop is internally compensated The TPS5431 is intended to operate from power rails up to 23 V The TPS5430 regulates a wide variety of power sources including 24 V bus The TPS5430 TPS5431 device is available in a thermally enhanced easy to use 8 pin SOIC PowerPAD package TI provides evaluation modules and the SWIFT Designer software tool to aid in quickly achieving high performance power supply designs to meet aggressive equipment development cycles Efficiency vs Output Current Efficiency N a Vj 12V Vo 5V 60 fs 500 kHz TA 25 C 50 0 05 1 15 2 25 3 35 lg Output Current A A Please be aware that an important notice concerning availability standar
29. routing may be done on an alternate layer if a trace under the output capacitor is not desired If using the grounding scheme shown in Figure 9 use a via connection to a different layer to route to the ENA pin Submit Documentation Feedback 9 TPS5430 TPS5431 SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 APPLICATION INFORMATION continued CATCH BOOT DIODE CAPACITOR gt INPUT INPUT BYPASS BULK EMN CAPACITOR FILTER OUTPUT a v x f f Vin NC one GND RESISTOR VSENSE a O O O O DIVIDER i q Les VOUT OUTPUT FILTER TOPSIDE GROUND AREA CAPACITOR VIA to Ground Plane Route feedback trace under output a filter capacitor or on uj Signal VIA other layer Figure 9 Design Layout 10 Submit Documentation Feedback dis TEXAS INSTRUMENTS www ti com I TPS5430 si TEXAS TPS5431 INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 APPLICATION INFORMATION continued 0 110 lt __ 0 220 v i A Ni O g E S L S 0 013 DIA 4 PL la 0 040 lt 0 098 All dimensions in inches Figure 10 TPS5430 Land Pattern Application Circuits Figure 11 shows the schematic for a typical TPS5430 application The TPS5430 can provide up to 3 A output current at a nominal output voltage of 5 V For proper thermal perform
30. se width which is the duty cycle Finally the PWM output is fed into the gate drive circuit to control the on time of the high side MOSFET Overcurrent Limiting Overcurrent limiting is implemented by sensing the drain to source voltage across the high side MOSFET The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit If the drain to source voltage exceeds the overcurrent threshold limit the overcurrent indicator is set true The system will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn on noise glitches Once overcurrent indicator is set true overcurrent limiting is triggered The high side MOSFET is turned off for the rest of the cycle after a propagation delay The overcurrent limiting mode is called cycle by cycle current limiting 8 Submit Documentation Feedback f TPS5430 si TEXAS TPS5431 INSTRUMENTS Www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 APPLICATION INFORMATION continued Sometimes under serious overload conditions such as short circuit the overcurrent runaway may still happen when using cycle by cycle current limiting A second mode of current limiting is used i e hiccup mode overcurrent limiting During hiccup mode overcurrent limiting the voltage reference is grounded and the high side MOSFET is turned off for the hiccup time Once the hiccup time duration is complete the reg
31. t the design is set up to be small size and low component height Switching Frequency The switching frequency for the TPS5430 is internally set to 500 kHz It is not possible to adjust the switching frequency Input Capacitors The TPS5430 requires an input decoupling capacitor and depending on the application a bulk input capacitor The recommended value for the decoupling capacitor C1 is 10 uF A high quality ceramic type X5R or X7R is required For some applications a smaller value decoupling capacitor may be used so long as the input voltage and current ripple ratings are not exceeded The voltage rating must be greater than the maximum input voltage including ripple This input ripple voltage can be approximated by Equation 2 I x 0 25 OUT MAX 5 pot OUTIMAX A ESR ax AV CguLk X J sw 2 Where lour vAx is the maximum load current fsw is the switching frequency Cy is the input capacitor value and ESRvuax is the maximum series resistance of the input capacitor The maximum RMS ripple current also needs to be checked For worst case conditions this can be approximated by Equation 3 ma IOUT MAX CIN 2 3 In this case the input ripple voltage would be 156 mV and the RMS ripple current would be 1 5 A The maximum voltage across the input capacitors would be VIN max plus delta VIN 2 The chosen input decoupling capacitor is rated for 25 V and the ripple current capacity is greater than 3 A providing ample margin
32. tation Feedback TPS5430 si TEXAS TPS5431 INSTRUMENTS www ti com SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 V Fp1 500000 x Fic 15 Fz2 2 5 x Fic 17 The final pole is located at a frequency too high to be of concern The second zero Fz2 as defined by Equation 17 uses 2 5 for the frequency multiplier In some cases this may need to be slightly higher or lower Values in the range of 2 3 to 2 7 work well The values for R1 and R2 are fixed by the 3 3 V output voltage as calculated usingEquation 12 For this design R1 10 kQ and R2 5 90 kQ With Fp1 401 Hz Fz1 2876 Hz and Fz2 10 3 kHz the values of R3 C6 and C7 are determined using Equation 18 Equation 19 and Equation 20 1 C7 2n x Fp1 x R1 R2 18 1 R3 gt x x Fzi x C 19 S 1 c6 2n x Fz2 xR1 20 For this design using the closest standard values C7 is 0 1 uF R3 is 549 Q and C6 is 1500 pF C4 is added to improve load regulation performance It is effectively in parallel with C6 in the location of the second pole frequency so it should be small in relationship to C6 C4 should be less the 1 10 the value of C6 For this example 150 pF works well For additional information on external compensation of the TPS5430 TPS5431 or other wide voltage range SWIFT devices see SLVA237 Using TPS5410 20 30 31 With Aluminum Ceramic Output Capacitors ADVANCED INFORMATION Output Voltage Limitations Due to the internal design of th
33. tput capacitor also determines the amount of output ripple as specified in the initial design parameters The output ripple voltage is the inductor ripple current times the ESR of the output filter Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output ripple voltage ESRwax X Vout X Vinsa Vout Where A Vpp is the desired peak to peak output ripple Na is the number of parallel output capacitors Fow is the switching frequency For this design example a single 220 uF output capacitor is chosen for C3 The calculated RMS ripple current is 143 mA and the maximum ESR required is 40 mQ A capacitor that meets these requirements is a Sanyo Poscap 10TPB220M rated at 10 V with a maximum ESR of 40 mQ and a ripple current rating of 3 A An additional small 0 1 uF ceramic bypass capacitor may also used but is not included in this design The minimum ESR of the output capacitor should also be considered For good phase margin the ESR zero when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and 54 kHz The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one half the ripple voltage Any derating amount must also be included The maximum RMS ripple current in the output capacitor is given by Equation 11 1 Your Vinuraax Vout l x COUT RMS 42 Yinamaxy X out X Fsw X No
34. ulator restarts under control of the slow start circuit Overvoltage Protection The TPS5430 TPS5431 has an overvoltage protection OVP circuit to minimize voltage overshoot when recovering from output fault conditions The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112 5 x VREF Once the VSENSE pin voltage is higher than the threshold the high side MOSFET will be forced off When the VSENSE pin voltage drops lower than the threshold the high side MOSFET will be enabled again Thermal Shutdown The TPS5430 TPS5431 protects itself from overheating with an internal thermal shutdown circuit If the junction temperature exceeds the thermal shutdown trip point the voltage reference is grounded and the high side MOSFET is turned off The part is restarted under control of the slow start circuit automatically when the junction temperature drops 14 C below the thermal shutdown trip point PCB Layout Connect a low ESR ceramic bypass capacitor to the VIN pin Care should be taken to minimize the loop area formed by the bypass capacitor connections the VIN pin and the TPS5430 TPS5431 ground pin The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace and place the bypass capacitor as close as possible to the VIN pin The minimum recommended bypass capacitance is 4 7 uF ceramic with a X5R or X7R dielectric There should be a ground area on
35. vB TEXAS INSTRUMENTS www ti com e TPS5430 TPS5431 SLVS632C JANUARY 2006 REVISED NOVEMBER 2006 3 A WIDE INPUT RANGE STEP DOWN SWIFT CONVERTER FEATURES e Wide Input Voltage Range TPS5430 5 5 V to 36 V TPS5431 5 5 V to 23 V e Up to 3 A Continuous 4 A Peak Output Current e High Efficiency up to 95 Enabled by 110 mQ Integrated MOSFET Switch e Wide Output Voltage Range Adjustable Down to 1 22 V with 1 5 Initial Accuracy Internal Compensation Minimizes External Parts Count e Fixed 500 kHz Switching Frequency for Small Filter Size e Improved Line Regulation and Transient Response by Input Voltage Feed Forward System Protected by Overcurrent Limiting Overvoltage Protection and Thermal Shutdown e 40 C to 125 C Operating Junction Temperature Range e Available in Small Thermally Enhanced 8 Pin SOIC PowerPAD Package e For SWIFT Documentation Application Notes and Design Software See the TI Website at www ti com swift Simplified Schematic VIN PH TPS5430 31 NC BOOT 71 NG J ENA VSENE eo APPLICATIONS e Consumer Set top Box DVD LCD Displays e Industrial and Car Audio Power Supplies e Battery Chargers High Power LED Supply e 12 V 24 V Distributed Power Systems DESCRIPTION As a member of the SWIFTTM family of DC DC regulators the TPS5430 TPS5431 is a high output current PWM converter that integrates a low
36. vity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPQ Reel Reel AO mm BO mm KO mm P1 w Pin1 Type Drawing Diameter Width mm mm Quadrant mm W1 mm TPS5430DDAR so DDA 8 2500 330 0 12 4 6 4 5 2 2 1 8 0 12 0 Q1 Power PAD TPS5431DDAR SO DDA 8 2500 330 0 12 4 6 4 5 2 2 1 8 0 12 0 Q1 Power PAD Pack Materials Page 1 Ki Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 31 Oct 2008 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TPS5430DDAR SO PowerPAD DDA 8 2500 346 0 346 0 29 0 TPS5431DDAR SO PowerPAD DDA 8 2500 346 0 346 0 29 0 Pack Materials Page 2 MECHANICAL DATA DDA R PDSO G8 PowerPAD PLASTIC SMALL OUTLINE PACKAGE Thermal Pad See Note D 0 20 NOM 1 68 MAX TESTE Seating Plone O atl 4202561 D 04 04 NOTES All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 This package is designed to be soldered to a
37. would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements

TEXAS INSTRUMENTS TPS5430/TPS5431 handbook

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