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MICROCHIP PIC16C7X datasheet

1. 22 9 44 Lead Plastic Surface Mount TQFP 10x10 mm Body 1 0 0 10 mm Lead Form TQ D gt e D1 Leg 1 09 0 0399 Ref Pin i Pini iL i s e v SEE X eu 0 Min js S Et TE i s co Ho Ge oum Be Var I d 11 13 4x CL C Ij H Detail B JHHHRLE e el 3 00 0 1189 Ref R1 0 08 Min Option 1 TOP side Option 2 TOP side R 0 08 0 20 i i Gage Plane ums A1 0 250 x A2 A Base Metal Lead Finish i ee deci Detail A B c ie Detail B zelda 1 00 Ref f y t 1 00 Ref Detail A Detail B Package Group Plastic TQFP Millimeters Inches Symbol Min Max Notes Min Max Notes A 1 00 1 20 0 039 0 047 A1 0 05 0 15 0 002 0 006 A2 0 95 1 05 0 037 0 041 D 11 75 12 25 0 463 0 482 D1 9 90 10 10 0 390 0 398 E 11 75 12 25 0 463 0 482 E1 9 90 10 10 0 390 0 398 L 0 45 0 75 0 018 0 030 e 0 80 BSC 0 031 BSC b 0 30 0 45 0 012 0 018 b1 0 30 0 40 0 012 0 016 c 0 09 0 20 0 004 0 008 c1 0 09 0 16 0 004 0 006 N 44 44 44 44 ei 0 7 0 7 Note 1 Dimensions D1 and E1 do not include mold protrusion Allowable mold protrusion is 0 25m m 0 010 per side D1 and E1 dimensions including mold mismatch 2 Dimension b
2. 22 6 28 Lead Plastic Surface Mount SSOP 209 mil Body 5 30 mm SS E et v A I Occ pe C S or D HOO Y 2 3 e 4 Lan 5 P s Base plane 7 KH Seating plane p gt A1 Package Group Plastic SSOP Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 8 0 8 A 1 730 1 990 0 068 0 078 A1 0 050 0 210 0 002 0 008 B 0 250 0 380 0 010 0 015 C 0 130 0 220 0 005 0 009 D 10 070 10 330 0 396 0 407 E 5 200 5 380 0 205 0 212 e 0 650 0 650 Reference 0 026 0 026 Reference H 7 650 7 900 0 301 0 311 L 0 550 0 950 0 022 0 037 N 28 28 28 28 CP 0 102 0 004 DS30390E page 256 1997 Microchip Technology Inc PIC16C7X 22 7 44 Lead Plastic Leaded Chip Carrier Square PLCC 0 812 0 661 N Pics mE gt La 0 177 1 27 032 026 esr Fo i CH 0 177 2 Sid m y E edere UE i R G Sg Ur H 2 Sid
3. TABLE 4 2 PIC16C73 73A 74 74A SPECIAL FUNCTION REGISTER SUMMARY Cont d Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 2 Bank 1 80h 9 INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 81h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 111 11111111 1111 82h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 83h STATUS IRP RP10 RPO TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA PORTA Data Direction Register 1 111 11 1111 86h TRISB PORTB Data Direction Register 111 111 1111 1111 87h TRISC PORTC Data Direction Register 111 111 1111 1111 ssh TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 111 0000 111 8Ah 4 PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 8Bh 2 INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIEG ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 0000 8Dh PIE2 CCP2IE 0 8bh PCON POR BOR qq
4. Condition Condition Note Refer to Figure 18 1 for load conditions TABLE 18 9 12C BUS START STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No 90 TSU STA START condition 100 kHz mode 4700 m Only relevant for repeated START Setup time 400 kHz mode 600 condition 91 THD STA START condition 100 kHz mode 4000 m After this period the first clock Hold time 400 kHz mode 600 pulse is generated 92 Tsu sTO STOP condition 100 kHz mode 4700 Setup time 400 kHz mode 600 93 THD STO STOP condition 100 kHz mode 4000 Ge Hold time 400 kHz mode 600 A a DS30390E page 196 1997 Microchip Technology Inc PIC16C7X Out Note Refer to Figure 18 1 for load conditions FIGURE 18 10 IC BUS DATA TIMING Applicable Devices 72 73 73A 74 74A 76 77 TABLE 18 10 12C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No 100 THIGH Clock high time 100 kHz mode 4 0 us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 0 6 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 101 TLow Clock low time 10
5. Setting a TRISA register bit puts the corresponding out put driver in a hi impedance mode Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin s Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch All write operations are read modify write operations Therefore a write to a port implies that the port pins are read this value is modified and then written to the port data latch Pin RA4 is multiplexed with the TimerO module clock input to become the RA4 TOCKI pin Other PORTA pins are multiplexed with analog inputs and analog VREF input The operation of each pin is selected by clearing setting the control bits in the ADCON1 register A D Control Register1 Note On a Power on Reset these pins are con figured as analog inputs and read as 0 The TRISA register controls the direction of the RA pins even when they are being used as analog inputs The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs EXAMPLE 5 1 INITIALIZING PORTA BCF STATUS RPO BCF STATUS RP1 CLRF PORTA PIC16C76 77 only Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data BSF STATUS RPO MOVLW OxCF direction Set RA 3 0 as inputs RA lt 5 4 gt as outputs TRISA 7 6 are always read as 0 MOVWF TRISA
6. 3 5 4 0 4 5 5 0 5 5 6 0 Vpp Volts The shaded region represents the built in hysteresis of the 3 0 3 5 4 0 4 5 brown out reset circuitry Vpp Volts 1997 Microchip Technology Inc DS30390E page 243 Data based on matrix samples See first page of this section for details Data based on matrix samples See first page of this section for details PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 12 TYPICAL IDD vs FREQUENCY RC MODE 22 pF 25 C prd ES H D 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 Frequency MHz Shaded area is beyond recommended range Gg Es p H ZA D 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 Frequency MHz Shaded area is beyond recommended range DS30390E page 244 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 14 TYPICAL IDD vs FREQUENCY RC MODE 100 pF 25 C 200 400 800 1000 1200 1400 1600 1800 Shaded area is Frequency kHz beyond recommended range FIGURE 21 15 MAXIMUM IDD vs FREQUENCY RC MODE 100 pF 40
7. E 7 PIC16C6X Family of Devices PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 Maximum Frequency 20 20 20 20 20 cick ff Operation MHz EPROM Program Memory 1K 2K 4K x14 words Memory ROM Program Memory 2K 4K x14 words Data Memory bytes 36 128 128 192 192 Timer Module s TMRO TMRO TMRO TMRO TMRO TMR1 TMR1 TMR1 TMR1 TMR2 TMR2 TMR2 TMR2 Capture Compare 1 1 2 2 Weg lieler Module s Serial Port s SPI I C SPI C SPI C SPI IC SPI I2C USART USART USART Parallel Slave Port Interrupt Sources 3 7 7 10 10 UO Pins 13 22 22 22 22 Voltage Range Volts 3 0 6 0 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 In Circuit Serial Programming Yes Yes Yes Yes Yes Brown out Reset Yes Yes Yes Yes 28 pin SDIP 28 pin SDIP 28 pin SDIP 28 pin SDIP SOIC SSOP SOIC SSOP SOIC SOIC Clock Maximum Frequency 20 20 20 20 20 20 of Operation MHz EPROM Program Memory 2K 4K 8K 8K x14 words Memory ROM Program Memory x14 E 2K mE 4K words Data Memory bytes 128 128 192 192 368 368 Timer Module s TMRO TMRO TMRO TMRO TMRO TMRO TMR1 TMR1 TMR1 TMR1 TMR1 TMR1 TMR2 TMR2 TMR2 TMR2 TMR2 TMR2 Capture Compare PWM Mod ule s Peripherals Serial Port s SPI C USART SPC SPI C SPI C SPI C SPI C SPI C USART USART USART USART Parallel Slave Port Yes Yes Yes Yes Y
8. 23 25 27 117 119 unm 9 Application Notes AN546 Using the Analog to Digital Converter 117 AN552 Implementing Wake up on Key Strokes Using PIG16 C XXX tede ERREUR AN556 Table Reading Using PIC16CXX AN578 Use of the SSP Module in the DC Multi Master Environment issues seems 77 AN594 Using the CCP Modules AN607 Power up Trouble Shooting 134 Architecture TT EE Overview von Neumann Assembler MPASM Assembler ssssssssnesesiesinerresresenensrenrrnsrenne 164 N Baud Rate Error 101 Baud Rate Formula Baud Rates Asynchronous Mode Synchronous Mode A D ces 119 Analog Input Model 120 Capture sise annees 72 Comparte coni yn E P e y ORO egent IEG MOD el ss pu recent On Chip Reset Circuit S PIC16C 72 ifc ERRORES PIC16Q18 siete REMECTS PIC16C73A PIGIE C74 Tr ie Then era ee Deed PIGTOGYAA rar nn rene mir mme ire tee PIC16C76 PIC16C77 PORTG ere PORTD In I O Port Mode cccccccsssesseeseeeteeseeeees 50 PORTD and PORTE as a Parallel Slave Port 54 PORTE In I O Port Mode eeeeeeeeee 51 PME Ss eg EN md sese ties ctis 74 RA3 RAO and RAS Port Pins ueesesssssss 43 RA4 TOCKI Pin et e dete 43 RB3 RBO Port PINS uitia 45 RB7 RB4 Port Pins 46 SPI Master Slave Connection
9. Yee ams Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BC other Resets OCh PIR1 PsPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Slave Reception Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear Dame 1997 Microchip Technology Inc DS30390E page 115 PIC16C7X NOTES DS30390E page 116 1997 Microchip Technology Inc PIC16C7X 13 0 ANALOG TO DIGITAL CONVERTER A D MODULE Applicable Devices 72 73 73A 74 74A 76 77 The analog to digital A D converter module has five inputs for the PIC16C72 73 73A 76 and eight for the PIC16C74 74A 77 The A D allows conversion of an analog input signal to a corresponding 8 bit digital number refer to Applica tion Note AN546 for use of A D Converter The output of the sample and hold is the input into the converter which generates the result via successive approxima tion The analog reference vo
10. Note 1 Higher order bits are from the STATUS register 2 Brown out Reset is not available on the PIC16C73 1997 Microchip Technology Inc DS30390E page 11 FIGURE 3 3 PIC16C7X Device Program Memory Data Memory RAM PIC16C74 PIC16C74A PIC16C77 Program Bus EPROM Program Memory 14 Instruction reg 13 Program Counter KZ PIC16C74 74A 77 BLOCK DIAGRAM Data Bus 8 Level Stack 13 bit RAM File Registers RAM Adar 1 Direct Addr 7 d Addr MUX Indirect Addr FSR reg STATUS reg Power up Timer Instruction Decode amp Control Oscillator Start up Timer Power on RAO ANO RA1 AN1 RA2 AN2 RAS ANS VREF RA4 TOCKI RA5 SS AN4 RBO INT RB7 RB1 RCO T1OSO T1CKI RC1 T10SI CCP2 RC2 CCP1 RC3 SCK SCL RC4 SDI SDA RC5 SDO RC6 TX CK RC7 RX DT Reset Timing Watchdog DE Generation Timer OSC1 CLKIN Brown out OSC2 CLKOUT Reset i Parallel Slave Port MCLR VDD Vss RD7 PSP7 RDO PSPO REO RD AN5 RE1 WR AN6 Time Timer1 Timer2 gt gt Synchronous Serial Port RE2 CS AN7
11. BSF ADCONO GOX 134 Tosc 2 1 Q4 A D CLK 132 Xr OGOCGOCOGOGOCOGOC OLD DATA X NEW DATA A D DATA ADRES ADIF SAMPLE SAMPLING STOPPED Note 1 Ifthe A D clock source is selected as RC a time of TCY is added before the A D clock starts This allows the SLEEP instruction to be executed TABLE 17 11 A D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 130 TaD A D clock period PIC16C72 1 6 us Tosc based VREF 2 3 0V PIC16LC72 2 0 us Tosc based VREF full range PIC16C72 2 0 4 0 6 0 us A D RC Mode PIC16LC72 3 0 6 0 9 0 us A D RC Mode 131 TcNv Conversion time not including S H 9 5 TAD time Note 1 132 Taca Acquisition time Note 2 20 us 5 us The minimum time is the amplifier settling time This may be used if the new input voltage has not changed by more than 1 LSb i e 20 0 mV 9 5 12V from the last sampled voltage as stated on CHOLD 134 TGO Q4 to A D clock start Tosc 2 Ifthe A D clock source is selected as RC a time of Tcv is added before the A D clock starts This allows the SLEEP instruction to be executed 135 Tswc Switching from convert sample time 1 5 TAD These
12. Reference Reference Typical Typical L 3 175 3 810 0 125 0 150 N 40 40 40 40 S 1 016 2 286 0 040 0 090 S1 0 381 1 778 0 015 0 070 DS30390E page 252 1997 Microchip Technology Inc 22 3 28 Lead Plastic Dual In line 300 mil SP Pin No 1 Indicator Area PIC16C7X E D gt GE Base PlaneN Seating gt Plane L el 4 A1 A2 A D1 Package Group Plastic Dual In Line PLA Millimeters Inches Max Notes Min Max 10 0 10 Typical Typical 4 places 4 places 4 places 4 places Typical Typical Reference Reference Typical Typical Reference Reference 1997 Microchip Technology Inc DS30390E page 253 PIC16C7X 22 4 40 Lead Plastic Dual In line 600 mil P Pin No 1 Hu Area 4 Base PlaneN Seating gt Plane B1 B gt _ D1 Package Group Plastic Dual I
13. RE RCE respect to CCP1 CCP2 operates the same as CCP1 poule except where noted CCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 TABLE 10 2 INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time base Capture Compare The compare should be configured for the special event trigger which clears TMR1 Compare Compare The compare s should be configured for the special event trigger which clears TMR1 PWM PWM The PWMs will have the same frequency and update rate TMR2 interrupt PWM Capture None PWM Compare None 1997 Microchip Technology Inc DS30390E page 71 PIC16C7X FIGURE 10 1 CCP1CON REGISTER ADDRESS 17h CCP2CON REGISTER ADDRESS Dh U 0 UO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxMO R Readable bit bit7 bito W Writable bit bit 7 6 Unimplemented Read as 0 bit 5 4 CCPxX CCPxY PWM Least Significant bits Capture Mode Unused Compare Mode Unused U Unimplemented bit read as 0 n Value at POR reset PWM Mode These bits are the two LSbs of the PWM duty cycle The eight MSbs are found in CCPRxL bit 3 0 CCPxM3 CCPxMO CCPx Mode Select bits 0000 Capture Compare PWM off resets CCPx module 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edg
14. Note 1 Higher order bits are from the STATUS register 2 Brown out Reset is not available on the PIC16C74 DS30390E page 12 1997 Microchip Technology Inc PIC16C7X TABLE 3 1 PIC16C72 PINOUT DESCRIPTION Pin Name De SSOR SO odii Butter Description Pin Pin Pin Type Type OSC1 CLKIN 9 9 9 ST CMOS Oscillator crystal input external clock source input OSC2 CLKOUT 10 10 10 O Oscillator crystal output Connects to crystal or resonator in crystal oscillator mode In RC mode the OSC2 pin outputs CLKOUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate MGLR VPP 1 1 1 I P ST Master clear reset input or programming voltage input This pin is an active low reset to the device PORTA is a bi directional UO port RAO ANO 2 2 2 yo TTL RAO can also be analog inputO RA1 AN1 3 3 3 yo TTL RA1 can also be analog inputi RA2 AN2 4 4 4 yo TTL RA2 can also be analog input2 RA3 AN3 VREF 5 5 5 y o TTL RAS can also be analog input3 or analog reference voltage RA4 TOCKI 6 6 6 y o ST RA4 can also be the clock input to the TimerO module Output is open drain type RA5 SS AN4 7 7 7 UO TTL RAS can also be analog input4 or the slave select for the synchronous serial port PORTB is a bi directional UO port PORTB can be software programmed for internal weak pull up on all inputs RBO INT 21 21 21 UO TTL sT RBO can also be the external interrupt pin RB1
15. TABLE 3 3 PIC16C74 74A 77 PINOUT DESCRIPTION Pin Name DIP PLCC QFP I O P Buffer Descnotibn Pin Pin Pin Type Type p OSC1 CLKIN 13 14 30 ST CMOS Oscillator crystal input external clock source input OSC2 CLKOUT 14 15 31 O Oscillator crystal output Connects to crystal or resonator in crystal oscillator mode In RC mode OSC2 pin outputs CLKOUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate MCLR VPP 1 2 18 IP ST Master clear reset input or programming voltage input This pin is an active low reset to the device PORTA is a bi directional UO port RAO ANO 2 3 19 yo TTL RAO can also be analog inputO RA1 AN1 3 4 20 yo TTL DAT can also be analog input1 RA2 AN2 4 5 21 yo TTL RA2 can also be analog input2 RA3 AN3 VREF 5 6 22 y o TTL RAS can also be analog input3 or analog reference voltage RA4 TOCKI 6 7 23 yo ST RA4 can also be the clock input to the TimerO timer counter Output is open drain type RA5 SS AN4 7 8 24 yo TTL RAS can also be analog input4 or the slave select for the synchronous serial port PORTB is a bi directional UO port PORTB can be software programmed for internal weak pull up on all inputs RBO INT 33 36 8 UO TTL STU RBO can also be the external interrupt pin RB1 34 37 9 UO TTL RB2 35 38 10 UO TTL RB3 36 39 11 UO TTL RB4 37 41 14 UO TTL Interrupt on change pin RB5 38 42 15 UO TTL Interrupt on change pin RB6 39 43 16 yo TTL ST Interrupt on change pin Serial
16. suus 104 RX Pin Sampling Scheme BRGH 1 PIC16C73 73A 74 74A ssss 104 DS30390E page 280 1997 Microchip Technology Inc PIC16C7X Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 12 9 Figure 12 10 Figure 12 11 Figure 12 12 Figure 12 13 Figure 12 14 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 14 10 Figure 14 11 Figure 14 12 Figure 14 13 Figure 14 14 Figure 14 15 Figure 14 16 Figure 14 17 Figure 14 18 Figure 14 19 Figure 14 20 Figure 14 21 Figure 15 1 Figure 17 1 Figure 17 2 Figure 17 3 RX Pin Sampling Scheme BRGH 1 PIC16C73 73A 74 74A sees 104 RX Pin Sampling Scheme BRGH 0 OR BRGH 1 PIC16C796 77 eee 105 USART Transmit Block Diagram 106 Asynchronous Master Transmission 107 Asynchronous Master Transmission Back to Back 107 USART Receive Block Diagram 108 Asynchronous Reception 108 Synchronous Transmission 111 Synchronous Transmission Through TXEN eee 111 Synchronous Reception Master Mode GEN 113 ADCONO Register Address 1Fh 117 ADCON1 Register Address 9Fh 118 A D Block Diagoram
17. Note 1 When an I O register is modified as a function of itself e g MOVF PORTB 1 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a O 2 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned to the TimerO Module 3 If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP DS30390E page 148 1997 Microchip Technology Inc PIC16C7X 15 1 Instruction Descriptions ADDLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example ADDWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Add Literal and W label ADDLW k 0 lt k lt 255 W k gt W C DC Z 11 111x kkkk kkkk The contents of the W register are added to the eight bit literal k and the result is placed in the W register 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data W ADDLW 0x15 Before Instruction W 0x10 After Instruction W 0x25 Add W and f abe ADDWF fd O lt f lt 127 de 0 1 W f destination C DC Z 00 0111
18. ssssse 81 SSP in DC Modenas e ai R 93 SSP in SPI Mode 80 85 TIMErQ NEE 59 TimerO WDT Prescaler 62 Timer1 Timer2 USART RECEIVE cuiii 108 USART Transmitter hend 106 Watchdog Timer BOR Dit Rd e ERN ER B ea RRG Dit scent Soe E Ed ee Buffer Full Status bit BE 78 83 C E TEE 20 C Compiler ss ree eee 165 Capture Compare PWM Capture Block Diagram eeeeeene 72 CCP1CON Register see 72 CCP1IF CCPR1 CCPR1H CCPR1L Mode Prescaler ressens 73 CCP Timer Resources s nssnnsennsesiinssinnseinnsrinnnsnane 71 Compare Block Diagram eseeeeeeeeene Mode teiseni e re rata ace tie atin de Software Interrupt Mode Special Event Trigger Special Trigger Output of CCP1 Special Trigger Output of CCP2 Interaction of Two CCP Modules sssseseeseeeeeeeeeee ee WEE Special Event Trigger and A D Conversions 73 Capture Compare PWM CCP PWM Block Diagram een 74 PWM Mod htt he tele eb tees 74 PWM Example Frequencies Resolutions 75 Gatrty Dlt zi dc eget eade wed CCPICON 29 SEI 33 CCPY1IF bit 95 36 CCPR2GON EE 29 CGP IE Dit 25 atest ME See WAL te o var Sete 37 1997 Microchip Technology Inc DS30390E page 273 PIC16C7X CGP2IF bib oec ra e ane Cete 38 CCPR1H Register A
19. 18 20 21 34 7 h NC 1 4 RCO T1OSO T1CKI 1 OSC2 CLKOUT J OSC1 CLKIN O Vss Oz Von 7 RE2 CS AN7 1 lt RE1 WR AN6 1 REO RD AN5 DI RA5 SS AN4 RA4 TOCKI RAO ANO 119 RA1 AN1 RA2 AN2 RAS ANS VREF 122 MCLR VPP RB3 RB2 RB1 RBO INT VDD Vss RD7 PSP7 RD6 PSP6 RD5 PSP5 RD4 PSP4 RC7 RX DT RC6 TX CK lt RC1 T10SI CCP2 43 RC5 SDO RC4 SDI SDA 41 E3 lt RD3 PSP3 lt RC3 SCK SCL RD2 PSP2 36 31 RC2 CCP1 RD1 PSP1 38 L3 RDO PSPO 44 42 40 39 37 35 34 NC L3 RCO0 T1OSO T1CKI L3 OSC2 CLKOUT OSC1 CLKIN PIC16C74A 5 vs PIC16C77 RC7 RX DT RD4 PSP4 RD5 PSP5 RD6 PSP6 RD7 PSP7 Vss VDD RBO INT RB1 RB2 RB3 O lt RE2 CS AN7 RE1 WR AN6 REO RD AN5 RA5 SS AN4 RA4 TOCKI Oo B Li 200 00 BR amp D 19 21 RA2 AN2 RAS ANS VREF EI 22 MCLR VPP RAO ANO RA1 AN1 C 20 1997 Microchip Technology Inc DS30390E page 3 PIC16C7X Table of Contents 1 0 General Description fnr inet etre ten dt me rte HERE de ER dt t HEEL HE daa 5 2 0
20. 81 SPI Mode Timing Master Mode or Slave Mode w o SS Control 82 SPI Mode Timing Slave Mode with SS Control 82 SSPSTAT Sync Serial Port Status Register Address 94h PIC16C76 77 83 SSPCON Sync Serial Port Control Register Address 14h PIC16C76 77 84 SSP Block Diagram SPI Mode PICTTOG76 T re reperi RE 85 SPI Master Slave Connection PIC IIe 86 SPI Mode Timing Master Mode PIC16C76 77 87 SPI Mode Timing Slave Mode With CKE 0 PIC16C796 77 87 SPI Mode Timing Slave Mode With CKE 1 PIC16C796 77 88 Start and Stop Conditions 7 bit Address Format DC 10 bit Address Format Slave receiver Acknowledge 90 Data Transfer Wait State 90 Master transmitter Sequence 91 Master receiver Sequence 91 Combined Format 91 Multi master Arbitration Two Masters Clock Synchronization SSP Block Diagram GE Mode s Roe oma 93 DC Waveforms for Reception 7 bit Address 95 DC Waveforms for Transmission 7 bit Address 96 Operation of the PC Module in IDLE MODE RCV MODE or SMIT MODE eene 98 TXSTA Transmit Status and Control Register Address 98h 99 RCSTA Receive Status and Control Register Address 18h 100 RX Pin Sampling Scheme BRGH 0 PIC16C73 73A 74 74A
21. Note For the PIC16C73 73A 74 74A the asynchronous high speed mode BRGH 1 may experience a high rate of receive errors It is recommended that BRGH 0 If you desire a higher baud rate than BRGH 0 can support refer to the device errata for additional information or use the PIC16C76 77 1997 Microchip Technology Inc DS30390E page 103 PIC16C7X 12 1 1 SAMPLING The data on the RC7 RX DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin If bit BRGH TXSTA lt 2 gt is clear i e at the low baud rates the sampling is done on the seventh eighth and ninth fall ing edges of a x16 clock Figure 12 3 If bit BRGH is set i e at the high baud rates the sampling is done on the 3 clock edges preceding the second rising edge after the first falling edge of a x4 clock Figure 12 4 and Figure 12 5 FIGURE 12 3 RX PIN SAMPLING SCHEME BRGH 0 PIC16C73 73A 74 74A RX Start bit RC7 RX DT pin baud CLK 7 Baud CLK for all but start bit x16 CLK RX pin 11 12 18 14 15 16 1 Start Bit baud clk First falling edge after RX pin goes low LE rising edge 4 1 2 UU Q2 Q4 ck UU UU UU L Il S
22. 0 C lt TA 70 C for commercial Operating voltage VDD range as described in DC spec Section 20 1 and Section 20 2 Param Characteristic Sym Min Typ Max Units Conditions No Output High Voltage D090 O ports Note 3 VoH VDD 0 7 V IOH 3 0 mA VDD 4 5V 40 C to 85 C D090A VDD 0 7 V loH 2 5 mA VDD 4 5V 40 C to 125 C D092 OSC2 CLKOUT RC osc config VpD 0 7 V lOH 1 3 mA VDD 4 5V 40 C to 85 C D092A VDD 0 7 V IOH 1 0 mA VDD 4 5V 40 C to 125 C D150 Open Drain High Voltage VoD S 14 V RAA pin Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 15 pF In XT HS and LP modes when exter nal clock is used to drive OSC1 D101 All I O pins and OSC2 in RC CIO 50 pF D102 model SCL SDA in PC mode CB 400 pF These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced
23. In some graphs or tables the data presented are outside specified operating range i e outside specified Vop range This is for information only and devices are guaranteed to operate properly only within the specified range Note The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples Typical represents the mean of the distribution at 25 C while max or min represents mean 36 and mean 3o respectively where o is standard deviation FIGURE 21 1 TYPICAL IPD vs VoD WDT DISABLED RC MODE Nm di 4 0 4 5 Vpp Volts FIGURE 21 2 MAXIMUM IPD vs VDD WDT DISABLED RC MODE 4 0 4 5 Vpp Volts 1997 Microchip Technology Inc DS30390E page 241 Data based on matrix samples See first page of this section for details PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 3 TYPICAL IPD vs VDD 25 C FIGURE 21 5 TYPICAL RC OSCILLATOR WDT ENABLED RC MODE FREQUENCY vs VDD Cext 22 pF T 25 C N I z o o LL 4 0 4 5 Vop Volts 25 30 35 40 45 50 Vpp Volts
24. uu 8Fh Unimplemented 90h Unimplemented 91h Unimplemented 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port IC mode Address Register 0000 0000 0000 0000 94h SSPSTAT D A P S RW UA BF 00 0000 00 0000 95h Unimplemented 96h Unimplemented 97h Unimplemented 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah Unimplemented 9Bh Unimplemented 9Ch Unimplemented 9Dh Unimplemented 9Eh Unimplemented 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Shaded locations are unimplemented read as 0 Note 1 tents are transferred to the upper byte of the program counter NO ok ON Other non power up resets include external reset through MCLR and Watchdog Timer Reset Bits PSPIE and PSPIF are reserved on the PIC16C73 73A always maintain these bits clear These registers can be addressed from either bank PORTD and PORTE are not physically implemented on the PIC16C73 73A read as 0 Brown out Reset is not implemented on the PIC16C73 or the PIC16C74 read as 0 The IRP and RP1 bits are reserved on the PIC16C73 73A 74 74A always maintain these bits clear The upper byte of
25. 22 Status Register Address 03h 83h 103h 183h asset 30 OPTION Register Address 81h 1811 its irent M net ent 31 INTCON Register Address OBh 8Bh 10bh 18bh 32 PIE1 Register PIC16C72 Address OCH 33 PIE1 Register PIC16C73 73A 74 74A 76 77 Address 8Ch 34 PIR1 Register PIC16C72 Address OCH 35 PIR1 Register PIC16C73 73A 74 74A 76 77 Address OCh PIE2 Register Address 8Dh PIR2 Register Address ODh PCON Register Address 8Eh Loading of PC In Different SItUAtIONS riot eerie Direct Indirect Addressing Block Diagram of RA3 RAO and RAS Pins eeseseeeeeee 43 Block Diagram of RA4 TOCKI Pin 43 Block Diagram of RB3 RBO Pins 45 Block Diagram of RB7 RB4 Pins PIC16C 793 74 tient 46 Block Diagram of RB7 RB4 Pins PIC16C72 73A GC EE 46 PORTC Block Diagram Peripheral Output Override 48 PORTD Block Diagram in UO Port Mode 50 PORTE Block Diagram in UO Port Mode TRISE Register Address 89h x Successive I O Operation PORTD and PORTE Block Diagram Parallel Slave Port 54 Parallel Slave Port Write Waveforms 55 Parallel Slave Port Read Waveforms 55 TimerO Block Diagram 59 TimerO Timing Internal Clock No Prescale ss 59 TimerO Timing Internal Clock Pre
26. RC6 TX CK VN pin 125 RC7 RX DT a pin X E E 126 w Note Refer to Figure 18 1 for load conditions TABLE 18 12 USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 125 TdtV2ckL SYNC RCV MASTER amp SLAVE Data setup before CK J DT setup time 15 ns 126 TckL2dtl Data hold after CK J DT hold time 15 ns t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 198 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 7T9A 74 74A 76 77 TABLE 18 13 A D CONVERTER CHARACTERISTICS PIC16C73 74 04 Commercial Industrial PIC16C73 74 10 Commercial Industrial PIC16C73 74 20 Commercial Industrial PIC16LC73 74 04 Commercial Industrial Param Sym Characteristic Min Typt Max Units Conditions No A01 NR Resolution 8 bits bit VREF VDD 5 12V Vss lt VAIN lt VREF A02 Eass Total Absolute error t1 LSb VREF VDD 5 12V VSS VAIN VREF A03 EiL Integral linearity error t1 LSb VREF VDD 5 12V VSS VAIN VREF A04 EDL Differential linearity error t1 LSb VREF VDD 5 12V VSS VAIN VREF A05 Ers Full scale error lt 1 LSb VREF VDD 5 12V
27. DAMADI Transmit Shift Reg Transmit shift reg empty flag FIGURE 12 9 ASYNCHRONOUS MASTER TRANSMISSION BACK TO BACK Write to TXREG 1 1 C BEG GU Word 1 Word 2 32 utpu shift clock 60 RC6 TX CK pin l Start Bit i i Start Bit i TXIF bit it BIO 9 6 X Bit 7 8 7 Stop Bit Bit 0 interrupt reg flag OB gt ja WORD 2 TRMT bit it o d WORD 2 Transmit shift Transmit Shift Reg Transmit Shift Reg reg empty flag 45 Note This timing diagram shows two consecutive transmissions TABLE 12 6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR Resets OCh PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1lIE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Transmission Note 1 Bits PSPIE
28. DS30390E page 92 1997 Microchip Technology Inc Applicable ee p PI C1 6C7X 72 73 73A 74 11 5 SSP 12C Operation The SSP module in I C mode fully implements all slave functions except general call support and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions The SSP module implements the standard mode specifica tions as well as 7 bit and 10 bit addressing Two pins are used for data transfer These are the RC3 SCK SCL pin which is the clock SCL and the RC4 SDI SDA pin which is the data SDA The user must configure these pins as inputs or outputs through the TRISC lt 4 3 gt bits The SSP module functions are enabled by setting SSP Enable bit SSPEN SSP CON lt 5 gt FIGURE 11 24 SSP BLOCK DIAGRAM EC MODE Internal data bus Write SSPBUF re SSPSR reg LSb XZ detect m Addr Match SSPADD reg Start and Set Reset Stop bit detect S P bits p SSPSTAT reg The SSP module has five registers for C operation These are the SSP Control Register SSPCON SSP Status Register SSPSTAT Serial Receive Transmit Buffer SSPBUF SSP Shift Register SSPSR Not directly acces sible SSP Address Register SSPADD The SSPCON register allows control of the IC opera tion Four mode selection bits SSPC
29. Note 1 Asatransmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of START or STOP conditions 2 Afast mode 400 kHz I2C bus device can be used in a standard mode 100 kHz S C bus system but the requirement tsu DAT gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line TR max tsu DAT 1000 250 1250 ns according to the standard mode DC bus specification before the SCL line is released DS30390E page 180 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 17 10 A D CONVERTER CHARACTERISTICS PIC16C72 04 Commercial Industrial Extended PIC16C72 10 Commercial Industrial Extended PIC16C72 20 Commercial Industrial Extended PIC16LC72 04 Commercial Industrial Param Sym Characteristic Min Typt Max Units Conditions No A01 NR Resolution 8 bits bit VREF VDD 5 12V VSS VAIN VREF A02 EABS Total Absolute error zx t1 LSb VREF VDD 5 12V Vss VAIN lt VREF A03 EiL Integral linearity error E lt 1 LSb VREF VDD 5 12V Vss VAIN lt VREF A0
30. PORTA Data Direction Register 11 1111 11 1111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by TimerO 1997 Microchip Technology Inc DS30390E page 63 PIC16C7X NOTES DS30390E page 64 1997 Microchip Technology Inc PIC16C7X 8 0 TIMER1 MODULE Applicable Devices 72 73 73A 74 74A 76 77 The Timer1 module is a 16 bit timer counter consisting of two 8 bit registers TMR1H and TMR1L which are readable and writable The TMR1 Register pair TMR1H TMR1L increments from 0000h to FFFFh and rolls over to 0000h The TMR1 Interrupt if enabled is generated on overflow which is latched in interrupt flag bit TMR1IF PIR1 lt 0 gt This interrupt can be enabled disabled by setting clearing TMR1 interrupt enable bit TMR1IE PIE1 lt 0 gt Timer1 can operate in one of two modes Asa timer As a counter The operating mode is determined by the clock select bit TMR1CS T1CON 1 In timer mode Timer1 increments every instruction cycle In counter mode it increments on every rising edge of the external clock input Timeri can be enabled disabled by setting clearing control bit TMR1ON T1CON 0 Timer1 also has an internal reset input This reset can be generated by either of the two CCP modules Section 10 0 Figure 8 1 shows the Timer1 control register For the PIC16C72 73A 74A 76 77 when the Timer1 oscillator is enabled TIOSCE
31. and n Capture edge detect Enable TMR1H CCP1CON lt 3 0 gt Q s 10 1 2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature In asynchronous counter mode the capture operation may not work 10 1 3 SOFTWARE INTERRUPT When the Capture mode is changed a false capture interrupt may be generated The user should keep bit CCP1IE PIE1 lt 2 gt clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode DS30390E page 72 1997 Microchip Technology Inc PIC16C7X 10 1 4 CCP PRESCALER There are four prescaler settings specified by bits CCP1M3 CCP1MO Whenever the CCP module is turned off or the CCP module is not in capture mode the prescaler counter is cleared This means that any reset will clear the prescaler counter Switching from one capture prescaler to another may generate an interrupt Also the prescaler counter will not be cleared therefore the first capture may be from a non zero prescaler Example 10 1 shows the recom mended method for switching between capture pres calers This example also clears the prescaler counter and will not generate the false interrupt EXAMPLE 10 1 CHANGING BETWEEN CAPTURE PRESCALERS CLRF CCP1CON Turn CCP module off MOVLW NEW CAPT PS Load the W reg with the new prescaler mode value and
32. 119 Analog Input Model 120 A D Transfer Function 125 Flowchart of A D Operation 126 Configuration Word for PIC16C73 74 see 129 Configuration Word for PIC16C072 73A 74A 76 77 130 Crystal Ceramic Resonator Operation HS XT or LP OSC Configuration 131 External Clock Input Operation HS XT or LP OSC Configuration 131 External Parallel Resonant Crystal Oscillator Circuit 132 External Series Resonant Crystal Oscillator Circuit 132 RC Oscillator Mode 132 Simplified Block Diagram of On chip Reset Circuit 133 Brown out Situations 134 Time out Sequence on Power up MCLR not Tied to VDD Case 1 139 Time out Sequence on Power up MCLR Not Tied To VDD Case 2 139 Time out Sequence on Power up MCLR Tied to VDD 139 External Power on Reset Circuit for Slow VDD Power up 140 External Brown out Protection CirCUIL tiamina ce 140 External Brown out Protection Circuit 2 140 Interrupt Logic 142 INT Pin Interrupt Timing 142 Watchdog Timer Block Diagram 144 Summary of Watchdog Timer Registers 144 Wake up from Sleep Through Interrupt eee eeeeeeeee teat e
33. 14 15 RC4 SDI SDA RC1 T1OSI CCP2 RC6 TX CK RC2 CCP1 RC5 SDO PIC16C73 Ee CN PIC16C73A oer SE ge PIC16C74 PIC16C74A PIC16C77 DS30390E page 2 1997 Microchip Technology Inc PIC16C7X Pin Diagrams Cont d RC7 RX DT RD4 PSP4 RD5 PSP5 RD6 PSP6 RD7 PSP7 Vss VDD RBO INT RB1 RB2 RB3 u u 2 a Owu ot Zzzz LEE CEE qaa ccccrZ RA4 TOCKI RA5 SS AN4 REO RD AN5 RE1 WR AN6 RE2 CS AN7 PIC1 6C74 Vi Ves PIC16C74A 3 OSC1 CLKIN 32 OSC2 CLKOUT PIC1 6C77 31 RCO T1OSO T1CKI 30 NC 29 D 28 RC1 TIOS CCP2 lt O48 RC2 CCP1 O19 RC3 SCK SCL Dan RDO PSPO lt 21 RD1 PSP1 O22 RD2 PSP2 Daa RD3 PSP3 lt 024 RC4 SDI SDA L 25 RC5 SDO O26 RC6 TX CK Cl 27 NC gt RCI T1OSI CCP2 RC5 SDO lt RD3 PSP3 lt RD2 PSP2 RDO PSPO lt RC2 CCP1 44 s RC6 TX CK 42 3 lt RC4 SDI SDA 39 3 RD1 PSP1 37 gt RC3 SCK SCL 43 41 40 38 36 35 O PIC16C74
34. PIC16C923 PIC16C924 64 68 pin PIC17C756 PIC17C752 64 68 pin 1997 Microchip Technology Inc DS30390E page 271 PIC16C 7X NOTES DS30390E page 272 1997 Microchip Technology Inc PIC16C7X ACCUEACV ETFOE WEE ADCONO Register ADCON1 Register m ADIF Dit oie nance entente Analog Input Model Block Diagram 120 Analog to Digital Converter TR Block Diagram sseeeeeeeeen Configuring Analog Port Pins sssssss 121 Configuring the Interrupt 119 Configuring the Module Connection Considerations 125 Conversion Clock 121 Conversion Time 123 GConVersions 0 acne eoe deerat ERES 122 Converter Characteristics Delays 120 Effects of a Reset 124 QUATIONS sur Pioneer bec ret needs 120 Faster Conversion Lower Resolution Tradeoff 123 Flowchart of A D Operation seeen 126 GO DONE EE 119 Internal Sampling Switch Rss Impedance 120 Operation During Sleep Sampling Requirements sess 120 Sampling Time ee Source Impedance x Time Delays seen Transfer Function issues Using the CCP Trigger Absolute Maximum Ratings 167 183 201 219 Le 90 94 95 ADIE bit ADIF bit ioter beers 35 ADRES Register
35. sssssssseeeeeeneneen 94 Table 11 5 Registers Associated with ke Operation 4 Stee 97 Table 12 1 Baud Rate Formula 101 Table 12 2 Registers Associated with Baud Rate Generator 101 Table 12 3 Baud Rates for Synchronous Mode 102 Table 12 4 Baud Rates for Asynchronous Mode BRGH z 0 nein 102 Table 12 5 Baud Rates for Asynchronous Mode BRGH STY EEN 103 Table 12 6 Registers Associated with Asynchronous Transmission 107 Table 12 7 Registers Associated with Asynchronous Reception 109 Table 12 8 Table 12 9 Table 12 10 Table 12 11 Table 13 1 Table 13 2 Table 13 3 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 14 5 Table 14 6 Table 14 7 Table 14 8 Table 15 1 Table 15 2 Table 16 1 Table 17 1 Table 17 2 Table 17 3 Table 17 4 Table 17 5 Table 17 6 Table 17 7 Table 17 8 Table 17 9 Table 17 10 Table 17 11 Table 18 1 Registers Associated with Synchronous Mas ter Transmission 111 Registers Associated with Synchronous Mas ter Reception 112 Registers Associated with Synchronous Slave Transmission 115 Registers Associated with Synchronous Slave Reception 115 TAD vs Device Operating Frequencies sees 121 Registers Bits Associated with A D PIC16C72 5 1 non Beet 126 Summary of A D Registers PIC16C73 73A 74 74A 76 77
36. Applicable Devices 72 74 73 73A 74A 76 77 18 3 DC Characteristics PIC16C73 74 04 Commercial Industrial PIC16C73 74 10 Commercial Industrial PIC16C73 74 20 Commercial Industrial PIC16LC73 74 04 Commercial Industrial DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C OC TA lt 85 C for industrial and lt TA 70 C for commercial Operating voltage VDD range as described in DC spec Section 18 1 and Section 18 2 Param Characteristic Sym Min Typ Max Units Conditions No Input Low Voltage I O ports VIL D030 with TTL buffer Vss 0 15VDD V For entire VDD range D030A Vss 0 8V V 4 5V lt VDD lt 5 5V D031 with Schmitt Trigger buffer Vss 0 2VDD V D032 MCLR OSC1 in RC mode Vss O02VDD V D033 OSC1 in XT HS and LP Vss 0 3VDD V Note Input High Voltage I O ports VIH D040 with TTL buffer 2 0 VDD V 4 5V lt VDD lt 5 5V D040A 0 25VDD VDD V For entire VDD range 0 8V D041 with Schmitt Trigger buffer 0 8VDD VDD V For entire VDD range D042 MCLR 0 8VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note D043 OSC1 in RC mode 0 9VDD VDD V D070 PORTB weak pull up current IPURB 50 1250 400 uA VDD 5V VPIN VSS Input Leakage Current Notes 2 3 D060 WO ports liL 1 uA Vss VPIN lt VD
37. Masters that also incorporate the slave function and have lost arbitration must immediately switch over to slave receiver mode This is because the winning mas ter transmitter may be addressing it Arbitration is not allowed between Arepeated START condition ASTOP condition and a data bit Arepeated START condition and a STOP condi tion Care needs to be taken to ensure that these conditions do not occur 11 2 4 2 Clock Synchronization Clock synchronization occurs after the devices have started arbitration This is performed using a wired AND connection to the SCL line A high to low transition on the SCL line causes the concerned devices to start counting off their low period Once a device clock has gone low it will hold the SCL line low until its SCL high state is reached The low to high tran sition of this clock may not change the state of the SCL line if another device clock is still within its low period The SCL line is held low by the device with the longest low period Devices with shorter low periods enter a high wait state until the SCL line comes high When the SCL line comes high all devices start counting off their high periods The first device to complete its high period will pull the SCL line low The SCL line high time is determined by the device with the shortest high period Figure 11 23 FIGURE 11 23 CLOCK SYNCHRONIZATION start counting HIGH period wait state counter Ww reset
38. NA NA NA 1 2 1 221 1 73 255 1 202 0 16 207 1 202 0 16 129 1 203 0 23 92 2 4 2 404 0 16 129 2 404 0 16 103 2 404 0 16 64 2 380 0 83 46 9 6 9 469 1 36 32 9 615 0 16 25 9 766 1 73 15 9 322 2 90 11 19 2 19 53 1 73 15 19 23 0 16 12 19 53 1 73 7 18 64 2 90 5 76 8 78 13 1 73 3 83 33 8 51 2 78 13 1 73 1 NA 96 104 2 8 51 2 NA NA NA 300 312 5 4 17 0 NA NA NA 500 NA NA NA NA HIGH 312 5 0 250 0 156 3 0 111 9 0 LOW 1 221 255 0 977 255 0 6104 255 0 437 255 FOSC 5 0688 MHz 4 MHz 3 579545 MHz 1 MHz 32 768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE 96 value 96 value 96 value 96 value 96 value K KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 0 3 0 31 3 13 255 0 3005 0 17 207 0 301 0 23 185 0 300 0 16 51 0 256 14 67 1 1 2 1 2 0 65 1 202 41 67 51 1 190 0 83 46 1 202 40 16 12 NA e 2 4 2 4 0 32 2 404 41 67 25 2 432 41 32 22 2 232 6 99 6 NA 9 6 9 9 3 13 7 NA 9 322 2 90 5 NA D NA 7 19 2 19 8 3 13 3 NA E 18 64 2 90 2 NA S NA 76 8 79 2 3 13 0 NA E NA NA E NA 96 NA S NA 7 NA NA NA 7 300 NA 7 NA NA NA NA 500 NA z NA 5 7 NA NA S NA S 2 HIGH 79 2 T 0 62 500 E 0 55 93 S 0 15 63 S 0 0 512 0 LOW 0 3094 255 3 906 255 0 2185 255 0 0610 255 0 0020 S 255 DS30390E page 102 1997 Microchip Technology Inc
39. Note 1 I O pins have protection diodes to VDD and Vss TABLE 5 7 PORTD FUNCTIONS Name Bit Buffer Type Function RDO PSPO bitO ST TTL Input output port pin or parallel slave port bitO RD1 PSP1 bit sT TTL Input output port pin or parallel slave port bit1 RD2 PSP2 bit2 ST TTL Input output port pin or parallel slave port bit2 RD3 PSP3 bit3 ST TTL Input output port pin or parallel slave port bit3 RD4 PSP4 bit4 ST TTL Input output port pin or parallel slave port bit4 RD5 PSP5 bits ST TTL Input output port pin or parallel slave port bit5 RD6 PSP6 bit6 ST TTL Input output port pin or parallel slave port bit6 RD7 PSP7 bit7 ST TTL Input output port pin or parallel slave port bit7 Legend ST Schmitt Trigger input TTL TTL input Note 1 Input buffers are Schmitt Triggers when in I O mode and TTL buffer when in Parallel Slave Port Mode TABLE 5 8 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO XXXX XXXX uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 111 0000 111 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by PORTD DS30390E pa
40. PIC16C7X TABLE 12 5 BAUD RATES FOR ASYNCHRONOUS MODE BRGH 1 BAUD FOSC 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG 7 16 MHz SPBRG RATE 96 value 96 value 96 value 96 value K KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 9 6 9 615 40 16 129 9 615 40 16 103 9 615 0 16 64 9 520 0 83 46 19 2 19 230 0 16 64 19 230 0 16 51 18 939 1 36 32 19 454 1 32 22 38 4 37 878 1 36 32 38 461 0 16 25 39 062 1 7 15 37 286 2 90 11 57 6 56 818 1 36 21 58 823 42 12 16 56 818 1 36 10 55 930 2 90 7 115 2 1113 636 1 36 10 111 111 3 55 8 125 8 51 4 111 860 2 90 3 250 250 0 4 250 0 3 NA NA 625 625 0 1 NA 625 0 0 NA 1250 1250 0 0 NA NA NA BAUD FOSC 5 068 MHz SPBRG 4 MHz SPBRG 3 579 MHz SPBRG 1 MHz SPBRG 32 768 kHz SPBRG RATE value 96 value 96 value 96 value 96 value K KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 9 6 9 6 0 32 NA 9 727 41 32 22 8 928 6 99 6 NA 19 2 18 645 2 94 16 1 202 401417 207 18 643 2 90 11 20 833 48 51 2 NA 38 4 39 6 3 12 7 2 403 40 13 103 37 286 2 90 5 31 25 18 61 1 NA 57 6 52 8 8 33 5 9 615 0 16 25 55 930 2 90 3 62 5 8 51 0 NA 115 2 105 6 8 33 2 19 231 0 16 12 111 860 2 90 1 NA NA 250 NA NA 223 721 10 51 0 NA NA 625 NA NA NA NA NA 1250 NA NA NA NA NA
41. h hh he Sai Data in sampled SSPIF PIR1 lt 3 gt BF SSPSTAT lt 0 gt SCL hil PU while responds to SSPIF A D E AIA f A fV V Fu low cleared in software CKP SSPCON lt 45 From SSP interrupt SSPBUF is written in software jee routine Set bit after writing to SSPBUF the SSPBUF must be written to before the CKP bit can be set DS30390E page 96 1997 Microchip Technology Inc Applicable Devices 72 73 73A 74 74A PIC16C7X 76 77 11 5 2 MASTER MODE Master mode of operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions The STOP P and START S bits are cleared from a reset or when the SSP module is disabled The STOP P and START S bits will toggle based on the START and STOP condi tions Control of the I C bus may be taken when the P bit is set or the bus is idle and both the S and P bits are clear In master mode the SCL and SDA lines are manipu lated by clearing the corresponding TRISC lt 4 3 gt bit s The output level is always low irrespective of the value s in PORTC lt 4 3 gt So when transmitting data a 1 data bit must have the TRISC lt 4 gt bit set input and a 0 data bit must have the TRISC lt 4 gt bit cleared out put The same scenario is true for the SCL line with the TRISC lt 3 gt bit The following events will cause
42. t1 LSb VREF VDD 5 12V VSS VAIN VREF A10 Monotonicity guaranteed VSs VAIN lt VREF A20 VREF Reference voltage 3 0V VDD 0 3 V A25 VAIN Analog input voltage Vss 0 3 VREF 0 3 V A30 ZAIN Recommended impedance of 10 0 kQ analog voltage source A40 IAD A D conversion current PIC16C76 77 180 uA Average current consump VDD PIC16LC76 77 Em 90 uA tion when A D is on Note 1 A50 IREF VREF input current Note 2 10 1000 uA During VAIN acquisition Based on differential of VHOLD to VAIN to charge CHOLD see Section 13 1 10 uA During A D Conversion cycle These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested When A D is off it will not consume any current other than minor leakage current The power down current spec includes any such leakage from the A D module 2 VREF current is from RAS pin or VDD pin whichever is selected as reference input DS30390E page 238 1997 Microchip Technology Inc PIC16C7X FIGURE 20 17 A D CONVERSION TIMING TABLE 20 14 A D CONVERSION REQUIREMENTS Param Sym Characteristic No 130 TaD A D clock period PIC16C76 77 PIC16LC76 77 PIC16C76 77 PIC16LC76 77 131 TcNv Conversion time not including S H time Note 1 132 TACQ Acquisition time 134 Teo
43. unimplemented bit read as 0 q value depends on condition Note 1 One or more bits in INTCON PIR1 and or PIR2 will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h 3 See Table 14 7 for reset value for specific condition ER GGTCLECARAAARADAGQARAER NENEYISNENE HEH TEN a DS30390E page 138 1997 Microchip Technology Inc PIC16C7X FIGURE 14 10 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO VDD CASE 1 VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 14 11 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO VDD CASE 2 VDD LOT MCLR a QU INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET 1997 Microchip Technology Inc DS30390E page 139 PIC16C7X FIGURE 14 13 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW VDD POWER UP NW MCLR PIC16CXX Note 1 External Power on Reset circuit is required only if VDD power up slope is too slow The diode D helps discharge the capacitor quickly when VDD powers down R lt 40 kQ is recommended to make sure that voltage drop across R does not violate the device s electrical specification R1 1000 to 1 kQ will lim
44. 127 Ceramic Resonators c cseeeeeseeeeetees 131 Capacitor Selection for Crystal Deelt icin ir rete reet 131 Time out in Various Situations PIC16C73 74 sse 135 Time out in Various Situations PIC16C72 73A 74A 76 77 sss 135 Status Bits and Their Significance PIC16C79 74 itio it cct 135 Status Bits and Their Significance PIC16C72 73A 74A 76 77 sss 136 Reset Condition for Special Registers ss 136 Initialization Conditions for all Registers ss 136 Opcode Field Descriptions 147 PIC16CXX Instruction Set 148 Development Tools from Microchip 166 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices 167 External Clock Timing Requirements 173 CLKOUT and UO Timing Requirements AA 174 Reset Watchdog Timer Oscillator Start up Timer Power up Timer and brown out Reset Requirements sese 175 TimerO and Timer1 External Clock Requirements esssssseseseeeeeee eeen 176 Capture Compare PWM Requirements CCP1 SPI Mode Requirements DC Bus Start Stop Bits Requirements DC Bus Data Requirements A D Converter Characteristics PIC16C72 04 Commercial Industrial Extended PIC16C72 10 Comme
45. Bit3 Bit2 Bit1 BitO POR other resets BOR 06h 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO XXXX XXXX uuuu uuuu 86h 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h 181h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 111T 1111 Legend x unknown u unchanged Shaded cells are not used by PORTB 1997 Microchip Technology Inc DS30390E page 47 PIC16C7X 5 3 PORTC and TRISC Registers FIGURE 5 6 PORTC BLOCK DIAGRAM Applicable Devices PERIPHERAL OUTPUT 72 73 73A 74 74A 76 77 OVERRIDE PORTC is an 8 bit bi directional port Each pin is indi A PORT PERIPHERAL Select vidually configurable as an input or output through the ORT Select TRISC register PORTC is multiplexed with several Peripheral Data Out peripheral functions Table 5 5 PORTC pins have Data bus B Schmitt Trigger input buffers When enabling peripheral functions care should be pee taken in defining TRIS bits for each PORTC pin Some Data Latch peripherals override the TRIS bit to make a pin an out Q put while other peripherals override the TRIS bit to m make a pin an input Since the TRIS bit override is in p gt CKO SES effect while the peripheral is enabled read modify TRIS Latch write instructions BSF BCF XORWF with TRISC as Vss destination should be avoided The user should refer to Schmitt t
46. LP Mode Zb 248 Typical XTAL Startup Time vs VDD HS Mode 25 C 248 Typical XTAL Startup Time vs VDD XT Mode 25 C 248 Typical Idd vs Frequency LP Mode 25 C see 249 Maximum IDD vs Frequency LP Mode 85 C to 40 C 249 Figure 21 27 Figure 21 28 Figure 21 29 Figure 21 30 Typical IDD vs Frequency XT Mode 25 C 249 Maximum IDD vs Frequency XT Mode 40 C to 85 C 249 Typical IDD vs Frequency HS Mode 25 C RENE 250 Maximum IDD vs Frequency HS Mode 40 C to 85 C 250 DS30390E page 282 1997 Microchip Technology Inc PIC16C7X LIST OF TABLES Table 1 1 PIC16C7XX Family of Devces 6 Table 3 1 PIC16C72 Pinout Description Table 3 2 PIC16C73 73A 76 Pinout Description 14 Table 3 3 PIC16C74 74A 77 Pinout Description 15 Table 4 1 PIC16C72 Special Function Register SUMMA serene pace in epe 23 Table 4 2 PIC16C73 73A 74 74A Special Function Register Summary 25 Table 4 3 PIC16C76 77 Special Function Register Summary sss 27 Table 5 1 PORTA Functions sssssssss 44 Table 5 2 Summary of Registers Associated with PORTA 44 Table 5 3 PORTB Functions 46 Table 5 4 Summary of Registers Associated With PORTB epe re e pho ens 47 Table 5 5 POR
47. PARTING LINE A aT T Ns l E3 FE 1 60 Ref SS EE poroa L CHHHEHHEHEHE T TX E Y o B loz H A B DE N sn g _ _ 0 05 mm mm D K Base Plane ALA HHHHH i Seating Plane A1 Package Group Plastic MQFP Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 7 0 7 A 2 000 2 350 0 078 0 093 A1 0 050 0 250 0 002 0 010 A2 1 950 2 100 0 768 0 083 b 0 300 0 450 Typical 0 011 0 018 Typical C 0 150 0 180 0 006 0 007 D 12 950 13 450 0 510 0 530 D1 9 900 10 100 0 390 0 398 D3 8 000 8 000 Reference 0 315 0 315 Reference E 12 950 13 450 0 510 0 530 E1 9 900 10 100 0 390 0 398 E3 8 000 8 000 Reference 0 315 0 315 Reference e 0 800 0 800 0 031 0 032 L 0 730 1 030 0 028 0 041 44 44 44 44 CP 0 102 0 004 DS30390E page 258 1997 Microchip Technology Inc P IC16C7X
48. RC6 TX CKpn ML ML ro nma eg e ee ea es Write to bit SREN Lt SREN bit CREN bit H RCIF bit interrupt Read RXREG Note Timing diagram demonstrates SYNC master mode with bit SREN 1 and bit BRG 01 1997 Microchip Technology Inc DS30390E page 113 PIC16C7X 12 4 USART Synchronous Slave Mode Applicable Devices 72 73 73A 74 74A 76 77 Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6 TX CK pin instead of being supplied internally in master mode This allows the device to transfer or receive data while in SLEEP mode Slave mode is entered by clearing bit CSRC TXSTA lt 7 gt 12 444 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the synchronous master and slave modes are identical except in the case of the SLEEP mode If two words are written to the TXREG and then the SLEEP instruction is executed the following will occur a The first word will immediately transfer to the TSR register and transmit b The second word will remain in TXREG register c Flag bit TXIF will not be set d When the first word has been shifted out of TSR the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set e If enable bit TXIE is set the interrupt will wake the chip from SLEEP and if the global interrupt is enabled the program will branc
49. Vss lt VAIN lt VREF Offset error VREF VDD 5 12V Vss lt VAIN lt VREF Monotonicity Vss lt VAIN lt VREF A20 VREF Reference voltage 3 0V VDD 0 3 V A25 VAIN Analog input voltage Vss 0 3 VREF 0 3 V A30 ZAIN Recommended impedance of 10 0 kQ analog voltage source A40 IAD A D conversion current PIC16C73 74 180 HA Average current consump VDD PIC16LC73 74 I 90 Aes uA tion when A D is on Note 1 A50 IREF VREF input current Note 2 10 1000 uA During VAIN acquisition Based on differential of VHOLD to VAIN to charge CHOLD see Section 13 1 10 uA During A D Conversion cycle These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested When A D is off it will not consume any current other than minor leakage current The power down current spec includes any such leakage from the A D module 2 VREF current is from RAS pin or VDD pin whichever is selected as reference input 1997 Microchip Technology Inc DS30390E page 199 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 13 A D CONVERSION TIMING BSF ADCONO GOX 134 Tosc 2 Q4 A D CLK 132 e OGOCGOCOGOGOCOGOC OLD DATA
50. ns PIC16LC7X 100 ns Ft1 Timer1 oscillator input frequency range DC 200 kHz oscillator enabled by setting bit TTOSCEN 48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc 7Tosc These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 210 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 7 CAPTURE COMPARE PWM TIMINGS CCP1 AND CCP2 RC1 T1OSI CCP2 and RC2 CCP1 Capture Mode RC1 T1OSI CCP2 and RC2 CCP1 Compare or PWM Mode 53 Note Refer to Figure 19 1 for load conditions TABLE 19 6 CAPTURE COMPARE PWM REQUIREMENTS CCP1 AND CCP2 Param Sym Characteristic Min Typt Max Units Conditions No 50 TccL CCP1 and CCP2 No Prescaler 0 51cY 20 ns Input ow time PIC16C73A 74A 10 ns With Prescaler PIC16LC73A 74A 20 lee 51 TccH CCP4 and CCP2 No Prescaler 0 5TcY 20 ns input high time PIC16C73A 74A 10 ex sem Ins With Prescaler S GLC73A 74A 20 PUER 52 TccP CCP1 and CCP2 input period 3TCY 40 ns N prescale N value 1 4 or 16 53 TccR CCP1 and CCP2 output rise time PIC16C73A 74A 10 25 ns PIC16LC73A 7
51. out Reset BOR They are not affected by a WDT Wake up which is viewed as the resumption of normal operation The TO and PD bits are set or cleared differ ently in different reset situations as indicated in Table 14 5 and Table 14 6 These bits are used in soft ware to determine the nature of the reset See Table 14 8 for a full description of reset states of all reg isters A simplified block diagram of the on chip reset circuit is shown in Figure 14 8 The PIC16C72 73A 74A 76 77 have a MCLR noise fil ter in the MCLR reset path The filter will detect and ignore small pulses It should be noted that a WDT Reset does not drive MCLR pin low FIGURE 14 8 SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT External Reset X SLEEP WDT WDT 4 N Module Time out J Reset VDD rise detect Power on Reset 2 Brown out Reset BODEN OST PWRT OST Chip_Reset gt 10 bit Ripple counter 1 PWRT On chi RG ode C 10 bit Ripple counter I Enable PWRT 3 Enable OST Note 1 This is a separate oscillator from the RC oscillator of the CLKIN pin 2 Brown out Reset is implemented on the PIC16C72 73A 74A 76 77 3 See Table 14 3 and Table 14 4 for time out situations 1997 Microchip Technology I
52. 0 PD Status Affected TO PD Encoding 00 0000 0110 0011 Description The power down status bit PD is cleared Time out status bit TO is set Watchdog Timer and its pres caler are cleared The processor is put into SLEEP mode with the oscillator stopped See Section 14 8 for more details Words 1 Cycles 1 Q Cycle Activity Example Q1 Q2 Q3 Q4 Decode No No Go to Operation Operation Sleep SLEEP SUBLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example 1 Example 2 Example 3 Subtract W from Literal label SUBLW k O lt k lt 255 k W gt W C DC Z RER 110x kkkk kkkk The W register is subtracted 2 s comple ment method from the eight bit literal K The result is placed in the W register 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k data SUBLW 0x02 Before Instruction W 1 C Z 9 After Instruction W 1 C 1 resultis positive Z 0 Before Instruction W 2 C Z After Instruction W C 1 result is zero Z 1 Before Instruction W 8 C Z After Instruction W OxFF C O resultis negative Z 0 DS30390E page 160 1997 Microchip Technology Inc PIC16C7X SUBWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example 1 Examp
53. 1 Serial port enabled Configures RC7 RX DT and RC6 TX CK pins as serial port pins 0 Serial port disabled bit 6 RX9 9 bit Receive Enable bit 1 Selects 9 bit reception 0 Selects 8 bit reception bit 5 SREN Single Receive Enable bit Asynchronous mode Don t care Synchronous mode master 1 Enables single receive 0 Disables single receive This bit is cleared after reception is complete Synchronous mode slave Unused in this mode bit 4 CREN Continuous Receive Enable bit Asynchronous mode 1 Enables continuous receive 0 Disables continuous receive Synchronous mode 1 Enables continuous receive until enable bit CREN is cleared CREN overrides SREN 0 Disables continuous receive bit 3 Unimplemented Read as 0 bit 2 FERR Framing Error bit 1 Framing error Can be updated by reading RCREG register and receive next valid byte 0 No framing error bit 1 OERR Overrun Error bit 1 Overrun error Can be cleared by clearing bit CREN 0 No overrun error bit 0 RX9D 9th bit of received data Can be parity bit DS30390E page 100 1997 Microchip Technology Inc PIC16C7X 12 1 USART Baud Rate Generator BRG EXAMPLE 12 1 CALCULATING BAUD Applicable Devices RATE ERROR 72 73 73A 74 74A 76 77 Desired Baud rate Fosc 64 X 1 The BRG supports both the Asynchronous and Syn 9600 16000000 64 X 1 chronous modes of the USART It is a dedicated 8
54. A i new value i Note Refer to Figure 19 1 for load conditions TABLE 19 3 CLKOUT AND I O TIMING REQUIREMENTS Sym Characteristic i Max Units Conditions TosH2ckL OSC1T to CLKOUTL 75 200 ns Note 1 TosH2ckH OSC1T to CLKOUTT 75 200 ns Note 1 TckR CLKOUT rise time 35 100 ns Note 1 TckF CLKOUT fall time 35 100 ns Note 1 TckL2ioV CLKOUT 1 to Port out valid 0 5TcY 20 ns Note 1 TioV2ckH Port in valid before CLKOUT T TckH2iol Port in hold after CLKOUT T ns Note 1 TosH2ioV OSC1T Q1 cycle to 50 150 ns Port out valid TosH2iol OSC1T Q2 cycle to PIC16C73A 74A ns Port input invalid 1 O in PIC16LC73A 74A ES ns hold time TioV20sH Port input valid to OSC1T I O in setup time ns TioR Port output rise time PIC16C73A 74A 10 40 ns PIC16LC73A 74A 80 ns 21 TioF Port output fall time PIC16C73A 74A 10 40 ns PIC16LC73A 74A 80 ns 22tt Tinp INT pin high or low time TCY ns 23tt Trop RB7 RB4 change INT high or low time TCY ns These parameters are characterized but not tested TData in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested tt These parameters are asynchronous events not related to any internal clock edges Note 1 Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC DS30390E page 208 1997 Microch
55. C to 70 C D021A 0 9 5 HA VDD 3 0V WDT disabled 40 C to 85 C D023 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as UO pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all UO pins tristated pulled to VoD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VOD and Vss 4 For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula Ir VDD 2Rext mA with Rext in kOhm 5 Timer1 oscillator when enabled adds approximately 20 pA to the specification This value is from charac terization and is for design guidance only This is not tested 6 The A
56. Combined format SriSlave Address R W Slave Address First 7 bits Second byte A Sr Slave Address R W A DatalA Data A First 7 bits 4 write read Combined format A master addresses a slave with a 10 bit address then transmits data to this slave and reads data from this slave A acknowledge SDA low S Start Condition From slave to master P Stop Condition 1997 Microchip Technology Inc DS30390E page 91 Applicable Devices PIC16C7X 72 73 79A 74 74A 76 77 11 4 4 MULTI MASTER The DC protocol allows a system to have more than one master This is called multi master When two or more masters try to transfer data at the same time arbi tration and synchronization occur 11 4 4 1 ARBITRATION Arbitration takes place on the SDA line while the SCL line is high The master which transmits a high when the other master transmits a low loses arbitration Figure 11 22 and turns off its data output stage A master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration When the master devices are addressing the same device arbitration continues into the data FIGURE 11 22 MULTI MASTER ARBITRATION TWO MASTERS transmitter 1 loses arbitration x DATA 1 SDA DATA 17A 3 1 a meme E
57. FIGURE 21 4 MAXIMUM IPD vs VDD WDT Shaded area is beyond recommended range ENABLED RC MODE FIGURE 21 6 TYPICAL RC OSCILLATOR FREQUENCY vs VDD Cext 100 pF T 25 C Fosc MHz 4 0 4 5 5 0 5 5 6 0 Vpp Volts 25 30 35 40 45 50 55 60 Vpp Volts FIGURE 21 7 TYPICAL RC OSCILLATOR FREQUENCY vs VDD Cext 300 pF T 25 C Fosc kHz 3 5 40 4 5 Vpp Volts DS30390E page 242 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 8 TYPICAL IPD vs Voo BROWN FIGURE 21 10 TYPICAL IPD vs TIMER1 OUT DETECT ENABLED RC ENABLED 32 kHz RCO RC1 MODE 33 pF 33 pF RC MODE Device NOT in Brown out Reset Device in Brown out Reset 3 5 4 0 4 5 5 0 5 5 6 0 Vpp Volts 4 0 4 5 The shaded region represents the built in hysteresis of the Vbb Volts brown out reset circuitry FIGURE 21 9 MAXIMUM IPD vs VDD BROWN OUT DETECT FIGURE 21 11 MAXIMUM IPD vs TIMER1 ENABLED ENABLED 85 C TO 40 C RC MODE 32 kHz RCO RC1 z 33 pF 33 pF 85 C TO 40 C RC MODE Device NOT in Brown out Reset Device in Brown out Reset
58. FIGURE 5 3 BLOCK DIAGRAM OF RB3 RBO PINS REPU Data Latch D Q Data bus WR Port b CK AC WR TRIS SE RD TRIS A RBO INT Schmitt Trigger RD Port Buffer Note 1 UO pins have diode protection to VDD and Vss 2 To enable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit OPTION lt 7 gt Four of PORTB s pins RB7 RB4 have an interrupt on change feature Only pins configured as inputs can cause this interrupt to occur i e any RB7 RB4 pin con figured as an output is excluded from the interrupt on change comparison The input pins of RB7 RB4 are compared with the old value latched on the last read of PORTB The mismatch outputs of RB7 RB4 are OR ed together to generate the RB Port Change Inter rupt with flag bit RBIF INTCON lt 0 gt This interrupt can wake the device from SLEEP The user in the interrupt service routine can clear the inter rupt in the following manner a Any read or write of PORTB This will end the mismatch condition b Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared This interrupt on mismatch feature together with soft ware configurable pull ups on these four pins allow easy interface to a keypad and make it possible for wake up on key depression Refer to the Embed
59. Fosc 4 MHz VDD 5 5V Note 4 D013 S 10 20 mA 1997 Microchip Technology Inc DS30390E page 221 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20 2 DC Characteristics PIC16LC76 77 04 Commercial Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt Ta lt 85 C for industrial and 0 C lt TA lt 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 2 5 6 0 V LB XT RC osc configuration DC 4 MHz D002 RAM Data Retention VDR 1 5 V Voltage Note 1 D003 VDD start voltage to VPOR S Vss V See section on Power on Reset for details ensure internal Power on Reset signal D004 VDD rise rate to ensure SvpD 0 05 V ms See section on Power on Reset for details internal Power on Reset signal D005 Brown out Reset Voltage BVDD 3 7 4 0 43 V BODEN bit in configuration word enabled D010 Supply Current Note 2 5 IDD 2 0 3 8 mA XT RC osc configuration Fosc 4 MHz VDD 3 0V Note 4 D010A 22 5 48 uA LP osc configuration Fosc 32 kHz VDD 3 0V WDT disabled D015 Brown out Reset Current AIBOR 350 425 pA BOR enabled VDD 5 0V Note 6 D020 Power down Current IPD 7 5 30 HA VDp 3 0V WDT enabled 40 C to 85 C D021 Note 3 5 0 9 5 uA VDD 3 0V WDT disabled 0
60. Frequency kHz 12 16 20 24 28 32 36 40 Frequency MHz FIGURE 21 26 MAXIMUM IDD vs FIGURE 21 28 MAXIMUM IDD vs FREQUENCY FREQUENCY LP MODE 85 C TO 40 C XT MODE 40 C TO 85 C LA A Lt LA 100 Ze Frequency kHz 0 0 04 08 1 2 16 20 24 28 32 36 4 0 Frequency MHz 1997 Microchip Technology Inc DS30390E page 249 Data based on matrix samples See first page of this section for details PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 29 TYPICAL IDD vs FREQUENCY HS MODE 25 HS06 717 25 6 7 677 482 05 6 7 537 482 15 6 7 677 482 05276 7 677 482 F10 17 25 6 7 6 DS30390E page 250 1997 Microchip Technology Inc PIC16C7X 22 0 PACKAGING INFORMATION 22 1 28 Lead Ceramic Side Brazed Dual In Line with Window 300 mil JW Je Pin 1 Indicator Area Base T Plane i Seating 7 t A3 A2 PS
61. HS oscillator 01 XT oscillator 00 LP oscillator 1997 Microchip Technology Inc DS30390E page 129 PIC16C7X FIGURE 14 2 CONFIGURATION WORD FOR PIC16C72 73A 74A 76 77 CP1 CPO CP1 CPO CP1 CPO BODEN CP1 CPO PWRTE WDTE FOSC1 FOSCO Register CONFIG bit13 bito Address 2007h bit 13 8 CP1 CP0 Code Protection bits 2 5 4 11 Code protection off 10 Upper half of program memory code protected 01 Upper 3 4th of program memory code protected 00 All memory is code protected bit 7 Unimplemented Read as 1 bit 6 BODEN Brown out Reset Enable bit 1 1 BOR enabled 0 BOR disabled bit 3 PWRTE Power up Timer Enable bit 1 1 PWRT disabled 0 PWRT enabled bit 2 WDTE Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled bit 1 0 FOSC1 FOSCO Oscillator Selection bits 11 RC oscillator 10 HS oscillator 01 XT oscillator 00 LP oscillator Note 1 Enabling Brown out Reset automatically enables Power up Timer PWRT regardless of the value of bit PWRTE Ensure the Power up Timer is enabled anytime Brown out Reset is enabled 2 All of the CP1 CPO pairs have to be given the same value to enable the code protection scheme listed DS30390E page 130 1997 Microchip Technology Inc PIC16C7X 14 2 Oscillator Configurations Applicable Devices 72 73 73A 74 74A 76 77 14 2 1 OSCILLATOR TYP
62. PC will be cleared Figure 4 17 shows the two situa tions for the loading of the PC The upper example in the figure shows how the PC is loaded on a write to PCL PCLATH lt 4 0 gt PCH The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction PCLATH lt 4 3 gt PCH FIGURE 4 17 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 Instruction with PC PCLATH lt 4 0 gt 8 i ALU PCLATH 12 11 10 8 7 0 PC GOTO CALL PCLATH lt 4 3 gt 11 Opcode lt 10 0 gt 4 3 1 COMPUTED GOTO A computed GOTO is accomplished by adding an off set to the program counter ADDWF PCL When doing a table read using a computed GOTO method care should be exercised if the table location crosses a PCL memory boundary each 256 byte block Refer to the application note Implementing a Table Read AN556 4 3 2 STACK The PIC16CXX family has an 8 level deep x 13 bit wide hardware stack The stack space is not part of either program or data space and the stack pointer is not readable or writable The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch The stack is POPed in the event of a RETURN RETLW Or a RETFIE instruction execution PCLATH is not affected by a PUSH or POP operation The stack operates as a circular buffer This means that after the stack has been PUSHed eight times
63. PIC16C76 77 BCF STATUS RP1 Specify Bank 1 BSF STATUS RPO LOOP BTFSS SSPSTAT BF Has data been received transmit complete GOTO LOOP No BCF STATUS RPO MOVF SSPBUF W Specify Bank 0 W reg contents of SSPBUF MOVWF RXDATA Save in user RAM MOVF TXDATA W W reg contents of TXDATA MOVWF SSPBUF New data to xmit The block diagram of the SSP module when in SPI mode Figure 11 9 shows that the SSPSR is not directly readable or writable and can only be accessed from addressing the SSPBUF register Additionally the SSP status register SSPSTAT indicates the various status conditions FIGURE 11 9 SSP BLOCK DIAGRAM SPI MODE PIC16C76 77 lt Internal data bus Read ENA Write SSPBUF reg XZ Xa SSPSR reg RC4 SDI SDA bitO RC5 SDO SS Control Enable RA5 SS AN4 Edge Select Clock Select SSPM3 SSPMO TMR2 output 2 Prescaler RC3 SCK 4 16 64 SCL TRISC lt 3 gt 1997 Microchip Technology Inc DS30390E page 85 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 To enable the serial port SSP Enable bit SSPEN SSPCON lt 5 gt must be set To reset or reconfigure SPI mode clear bit SSPEN re initialize the SSPCON reg ister and then set bit SSPEN This configures the SDI SDO SCK and SS pins as serial port
64. PIG16G 3A caet ee dee pe 201 PIC16G74 Ren da PIC16C74A Ellen Le len Lee External Brown out Protection Circuit External Power on Reset Circuit usussuss F Family of Devices PIC12CXXX PIC14C000 s PIC16O KE een PICT6Gb5X 3 ence Ede eder D tere PIC16C5X i PIC16C62X and PIC16064X ecese 267 PIC16G6X EE PIC16C7XX len Le Neser PIC17CXX pe FERR Dit rs sen ni nn enr nine FSR Register 23 24 25 26 27 28 29 41 Fuzzy Logic Dev System fuzzyTECH MP 163 165 G General Description ssessseeeen 5 GIE rete ree tie tod ed pi eee eed 141 UO Ports PORTA Inc A A ee eei 43 PORTB ai PORT stats nine ire dente tet i eie ied 48 PORTD 50 54 PORTE 3c ot cerent e e pesetas 51 Section e osse 43 19 Programming Considerations sess 53 FC Addressing rentre oneri 94 Addressing I C Devices ssssssssee 90 Arbitration G Block Diagram onn eere 93 Clock Synchronization sese 92 Combined Format i IEG Operation x i enana cene rst PC Owervlenw E EA AS Initiating and Terminating Data Transfer ae Master Mode sn Master Receiver Sequence sss Master Transmitter Sequence Multi Master Mode A Reception eren ettet Reception Timing Diagram SCL and SD
65. Please list the following information and use this outline to provide us with your comments about this Data Sheet To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX z Application optional Would you like a reply Y N Device PIC16C6X Literature Number DS30390E Questions 1 What are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this data sheet easy to follow If not why 4 What additions to the data sheet do you think would enhance the structure and subject 5 What deletions from the data sheet could be made without affecting the overall usefulness 6 Isthere any incorrect or misleading information what and where 7 How would you improve this document 8 How would you improve our software systems and silicon products DS30390E page 286 1996 Microchip Technology Inc PIC16C7X PIC16C7X PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO XX X XX XXX Examples pattern QTP SQTP Code or Special Requirements a PIC16C72 04 P 301 Windowed CERDIP Commercial Temp MQFP Metric PQFP PDIP Package 4 MHz TQFP Thin Quad Flatp
66. Q Cycle Activity Example CLRWDT Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Clear W abel CLRW None 00h gt W 1 27 Z 00 0001 Oxxx XXXX W register is cleared Zero bit Z is set Q1 Q2 Q3 Q4 Decode No Process Write to Operation data W CLRW Before Instruction W Ox5A After Instruction W 0x00 Z 1 Clear Watchdog Timer abel CLRWDT None 00h WDT 0 WDT prescaler 1oTO 1o PD TO PD 00 0000 0110 0100 CLRWDT instruction resets the Watch dog Timer It also resets the prescaler of the WDT Status bits TO and PD are set 1 1 Q1 Q2 Q3 Q4 Decode No Process Clear Operation data WDT Counter CLRWDT Before Instruction WDT counter After Instruction WDT counter 0x00 WDT prescaler 0 TO 1 PD 1 DS30390E page 152 1997 Microchip Technology Inc PIC16C7X COMF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example DECF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Complement f label COMF fd O lt f lt 127 de 0 1 f destination Z 00 1001 afff ffff The contents of register f are comple mented If d is O the result is stored in W If d is 1 the
67. RA4 TOCKI RB2 RA4 TOCKI lt gt RB2 RAS SS AN4 a RB1 RAS SS ANA RB1 Vss RBO INT Vss RBO INT OSC1 CLKIN LI VDD OSC1 CLKIN VDD OSC2 CLKOUT Vss OSC2 CLKOUT Vss RCO T1OSO T1CK 9 RC7 RCO T1OSO T1CKl RC7 RC1 T1OSI RC6 RC1 T1OSI 4 RC6 RC2 CCP1 RC5 SDO RC2 CCP1 4 RC5 SDO RC3 SCK SCL lt gt RC4 SDI SDA RC3 SCK SCL 4 RC4 SDI SDA PIC16C72 PIC16C72 SDIP SOIC Windowed Side Brazed Ceramic PDIP Windowed CERDIP Mer RB7 CZ MCLR VPP RB7 RAO ANO RB6 RAO ANO RBG RA1 AN1 RB5 RA1 AN1 RB5 RA2 AN2 RB4 RA2 AN2 RB4 RA3 AN3 VREF lt gt RB3 RAS ANS VREF RBS RA4 TOCKI RB2 RAA TOCKI gt RB2 RA5 SS AN4 RB1 RAS SS AN4 RB1 REO RD AN5 RBO INT Vss RBO INT RE1 WR ANG vo OSC1 CLKIN 9 Von RE2 CS AN7 Mes OSC2 CLKOUT 10 190 Vss Ke E Vss RD6 PSP6 RCO T1OSO T1CKI lt 11 18 RC7 RX DT OSC1 CLKIN RDS PSPS RC1 T10SI CCP2 12 17 RC6 TX CK OSC2 CLKOUT RD4 PSP4 RC2 CCP1 lt 13 16 RC5 SDO RCO T1OSO T1CKI RC7 RX DT RC3 SCK SCL
68. Reference voltage 3 0V VDD 0 3 V A25 VAIN Analog input voltage Vss 0 3 VREF 0 3 V A30 ZAIN Recommended impedance of 10 0 kQ analog voltage source A40 IAD A D conversion current PIC16C73A 74A 180 uA Average current consump VDD PIC16LC73A 74A 90 uA tion when A D is on Note 1 A50 IREF VREF input current Note 2 10 1000 uA During VAIN acquisition Based on differential of VHOLD to VAIN to charge CHOLD see Section 13 1 ES 10 uA During A D Conversion cycle These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested When A D is off it will not consume any current other than minor leakage current The power down current spec includes any such leakage from the A D module 2 VREF current is from RAS pin or VDD pin whichever is selected as reference input DS30390E page 217 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 14 A D CONVERSION TIMING BSF ADCONO GOX 134 Tosc 2 1 Q4 A D CLK 1325 Xr OGOCGOCOGOGOCOGOC OLD DATA X NEW DATA A D DATA ADRES ADIF SAMPLE SAMPLING STOPPED Note 1 Ifthe A D
69. Se an Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne ee FIGURE 5 1 BLOCK DIAGRAM OF RA3 RAO AND RA5 PINS Q ME cea Data Latch D Q cK LG TRIS Latch RD TRIS TTL input buffer Q RD PORT Es To A D Converter 4 Note 1 I O pins have protection diodes to VDD and Vss FIGURE 5 2 BLOCK DIAGRAM OF RA4 TOCKI PIN d Je Data Latch Y e D Q Vss Trigger GET input TRIS Latch buffer e d i Ne Schmitt V RD TRIS RD PORT TMRO clock input lt Note 1 1 O pin has protection diodes to Vss only 1997 Microchip Technology Inc DS30390E page 43 PIC16C7X TABLE 5 1 PORTA FUNCTIONS Name Bit Buffer Function RAO ANO bitO TTL Input output or analog input RA1 AN1 bit TTL Input output or analog input RA2 AN2 bit2 TTL Input output or analog input RAS ANS VREF bit3 TTL Input output or analog input or VREF RA4 TOCKI bit4 ST Input output or external clock input for TimerO Output is open drain type RA5 SS AN4 bit5 TTL Input output or slave select input for synchronous serial port or analog input Legend TTL TTL input ST Schmitt Trigger input TABLE 5 2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Neue on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bi
70. TABLE 20 12 USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 125 TdtV2ckL SYNC RCV MASTER amp SLAVE Data setup before CK J DT setup time 15 ns 126 TckL2dtl Data hold after CK J DT hold time 15 ns T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 237 PIC16C7X 72 74 Applicable Devices 72 73 73A 74A 76 77 TABLE 20 13 A D CONVERTER CHARACTERISTICS PIC16C76 77 04 Commercial Industrial Extended PIC16C76 77 10 Commercial Industrial Extended PIC16C76 77 20 Commercial Industrial Extended PIC16LC76 77 04 Commercial Industrial Param Sym Characteristic Min Typt Max Units Conditions No A01 NR Resolution 8 bits bit VREF VDD 5 12V VSS VAIN VREF A02 Eass Total Absolute error Kg t1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF A03 EiL Integral linearity error t1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF A04 EDL Differential linearity error t1 LSb VREF VDD 5 12V VSS VAIN VREF A05 EFs Full scale error ES t1 LSb VREF VDD 5 12V VSS VAIN VREF A06 Eorr Offset error em
71. Three operating modes editor emulator simulator A project manager Customizable tool bar and key mapping A status bar with project information Extensive on line help MPLAB allows you to Edit your source files either assembly or C One touch assemble or compile and download to PIC16 17 tools automatically updates all project information Debug using source files absolute listing file Transfer data dynamically via DDE soon to be replaced by OLE Run up to four emulators on the same PC The ability to use MPLAB with Microchip s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools 16 10 Assembler MPASM The MPASM Universal Macro Assembler is a PC hosted symbolic assembler It supports all microcon troller series including the PIC12C5XX PIC14000 PIC16C5X PIC16CXXX and PIC17CXX families MPASM offers full featured Macro capabilities condi tional assembly and several source and listing formats It generates various object code formats to support Microchip s development tools as well as third party programmers MPASM allows full symbolic debugging from PICMASTER Microchip s Universal Emulator System DS30390E page 164 1997 Microchip Technology Inc PIC16C7X MPASM has the following features to assist in develop ing software for s
72. are included for more reliable power up These tim ers are invoked selectively to avoid unnecessary delays on power up and wake up PORTB has weak pull ups and interrupt on change feature TOCKI pin is also a port pin RA4 now FSR is made a full eight bit register In circuit serial programming is made possible The user can program PIC16CXX devices using only five pins VDD Vss MCLR VPP RB6 clock and RB7 data in out PCON status register is added with a Power on Reset status bit POR Code protection scheme is enhanced such that portions of the program memory can be pro tected while the remainder is unprotected Brown out protection circuitry has been added Controlled by configuration word bit BODEN Brown out reset ensures the device is placed in a reset condition if VDD dips below a fixed set point 1997 Microchip Technology Inc PIC16C7X APPENDIX B COMPATIBILITY To convert code written for PIC16C5X to PIC16CXX the user should take the following steps 1 Remove any program memory page select operations PA2 PA1 PAO bits for CALL GOTO Revisit any computed jump operations write to PC or add to PC etc to make sure page bits are set properly under the new scheme Eliminate any data memory page switching Redefine data variables to reallocate them Verify all writes to STATUS OPTION and FSR registers since these have changed Change reset vector to 0000h DS30390E
73. bit 6 TX9 9 bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled bit 5 Note SREN CREN overrides TXEN in SYNC mode bit 4 SYNC USART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 bit 2 Unimplemented Read as 0 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed Note or use the PIC16C76 77 For the PIC16C73 73A 74 74A the asynchronous high speed mode BRGH 1 may expe rience a high rate of receive errors It is recommended that BRGH 0 If you desire a higher baud rate than BRGH 0 can support refer to the device errata for additional information W Writable bit U Unimplemented bit read as 0 n Value at POR reset bitO 0 Low speed Synchronous mode Unused in this mode TRMT Transmit Shift Register Status bit 1 TSR empty 0 TSR full bit 1 bit 0 TX9D 9th bit of transmit data Can be parity bit 1997 Microchip Technology Inc DS30390E page 99 PIC16C7X FIGURE 12 2 RCSTA RECEIVE STATUS AND CONTROL REGISTER ADDRESS 18h R W 0 R W 0 R W 0 R W 0 U 0 R 0 R 0 R x SPEN RX9 SREN CREN FERR OERR RX9D R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 SPEN Serial Port Enable bit
74. incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write Internal phase clock OSC2 CLKOUT RC mode Fetch INST PC Execute INST PC 1 Fetch INST PC 1 Execute INST PC Fetch INST PC 2 xecute EXAMPLE 3 1 INSTRUCTION PIPELINE FLOW TcyO Tcy1 Tcy2 Tcy3 Fetch 1 Execute 1 MOVWF PORTB Fetch 2 Execute 2 CALL SUB 1 Fetch 3 MOVLW 55h Execute 3 BSF PORTA BIT3 Forced NOP Fetch 4 Flush Fetch SUB 1 Execute SUB 1 Instruction address SUB 1 All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed 1997 Microchip Technology Inc DS30390E page 17 PIC16C7X NOTES DS30390E page 18 1997 Microchip Technology Inc PIC16C7X For those devices with less than 8K program memory accessing a location above the physically implemented 4 0 MEMORY ORGANIZATION FIGURE 4 2 PIC16C73 73A 74 74A Applicable Devices PROGRAM MEMORY MAP 72 73 73A 74 74A 76 77
75. when enabled these pins must be properly configured as input or output bit 4 CKP Clock Polarity Select bit In SPI mode 1 Idle state for clock is a high level Transmit happens on falling edge receive on rising edge 0 Idle state for clock is a low level Transmit happens on rising edge receive on falling edge In C mode SCK release control 1 Enable clock 0 Holds clock low clock stretch Used to ensure data setup time bit 3 0 SSPM3 SSPMO Synchronous Serial Port Mode Select bits 0000 SPI master mode clock Fosc 4 0001 SPI master mode clock Fosc 16 0010 SPI master mode clock Fosc 64 0011 SPI master mode clock TMR2 output 2 0100 SPI slave mode clock SCK pin SS pin control enabled 0101 SPI slave mode clock SCK pin SS pin control disabled SS can be used as UO pin 0110 I C slave mode 7 bit address 0111 C slave mode 10 bit address 1011 C firmware controlled Master Mode slave idle 1110 C slave mode 7 bit address with start and stop bit interrupts enabled 1111 IC slave mode 10 bit address with start and stop bit interrupts enabled 1997 Microchip Technology Inc DS30390E page 79 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11 2 1 OPERATION OF SSP MODULE IN SPI MODE Applicable Devices 72 73 73A 74 74A 76 77 The SPI mode allows 8 bits of data to be synchro nously transmitted and received simultaneous
76. 1367 TINTETINT2 PS0OA OPTIONS5 05 TJ2 40 1 222 TD 21 770 the prescaler is sharedwithe 40 W 40 Source Edge Select bit TOSE OPTION 4 Clearing bit TOSE selects the rising edge Restrictions on the external clock input are discussed in detail in Section 7 2 The prescaler is mutually exclusively shared between the TimerO module and the Watchdog Timer The pres caler assignment is controlled in software by control bit PSA OPTION lt 3 gt Clearing bit PSA will assign the prescaler to the TimerO module The prescaler is not readable or writable When the prescaler is assigned to the TimerO module prescale values of 1 2 1 4 1 256 are selectable Section 7 3 details the operation of the prescaler 7 1 TimerO Interrupt Applicable Devices 72 73 73A 74 74A 76 77 The TMRO interrupt is generated when the TMRO reg ister overflows from FFh to 00h This overflow sets bit TOIF INTCON 2 The interrupt can be masked by clearing bit TOIE INTCON 5 Bit TOIF must be cleared in software by the TimerO module interrupt ser vice routine before re enabling this interrupt The TMRO interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP See Figure 7 4 for TimerO interrupt timing FIGURE 7 2 TIMERO TIMING INTERNAL CLOCK NO PRESCALE 1997 Microchip Technology Inc DS30390E page 59 PIC16C7X FIGURE 7 3 TIMEROTIMING INTERNAL CLOCK PRESCALE 1 2 PC Q1 o2 03 04
77. 18 pin DIP SOIC SOIC SOIC 20 pin SSOP 20 pin SSOP 20 pin SSOP Packages All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high UO current capability All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7 Note 1 Please contact your local Microchip sales office for availability of these devices E 6 PIC16C62X and PIC16C64X Family of Devices PIC16C620 PIC16C621 PIC16C622 PIC16C642 PIC16C662 Ron EPROM Program Memory Memory x14 words Data Memory bytes Timer Module s DETTE TER Comparators s 2 2 2 2 2 Internal Reference Voltage Interrupt Sources UO Pins Voltage Range Volts 13 13 2 5 6 0 2 5 6 0 2 5 6 0 3 0 6 0 3 0 6 0 Yes Yes Yes Yes Yes Brown out Reset Features Packages 18 pin DIP 18 pin DIP 18 pin DIP 28 pin PDIP 40 pin PDIP SOIC SOIC SOIC SOIC Windowed 20 pin SSOP 20 pin SSOP 20 pin SSOP Windowed CDIP CDIP 44 pin PLCC MQFP All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capability All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7 EE ee 1997 Microchip Technology Inc DS30390E page 267 PIC16C 7X
78. 2 W TOS 5 PC None 11 O1xx kkkk kkkk The W register is loaded with the eight bit literal k The program counter is loaded from the top of the stack the return address This is a two cycle instruction 1 2 Q1 Q2 Q3 Q4 Decode Read No Write to W literal k Operation Pop from the Stack No No No No Operation Operation Operation Operation CALL TABLE W contains table offset value S W now has table value D D ADDWF PC W offset RETLW k1 Begin table RETLW k2 D D D RETLW kn End of table Before Instruction W 0x07 After Instruction W value of k8 RETURN Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity 1st Cycle 2nd Cycle Example Return from Subroutine abel RETURN None TOS 5 PC None 00 0000 0000 1000 Return from subroutine The stack is POPed and the top of the stack TOS is loaded into the program counter This is a two cycle instruction 2 Q1 Q2 Q3 Q4 Decode No No Pop from Operation Operation the Stack No No No No Operation Operation RETURN After Interrupt PC DS30390E page 158 1997 Microchip Technology Inc PIC16C7X RLF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Rotate Left f through Carry lab
79. 250 10 000 ns XT osc mode 250 250 ns HS osc mode 04 100 250 ns HS osc mode 10 50 250 ns HS osc mode 20 5 us LP osc mode 2 Tcv Instruction Cycle Time Note 1 200 Tcv DC ns Tcy 4 Fosc 3 TosL External Clock in OSC1 High or 100 ns XT oscillator TosH Low Time 2 5 us LP oscillator 15 ns HSoscillator 4 TosR External Clock in OSC1 Rise or 25 ns XT oscillator TosF Fall Time 50 ns LP oscillator 15 ns HSoscillator T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Instruction cycle period Tcv equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current con sumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the Max cycle time limit is DC no clock for all devices 1997 Microchip Technology Inc DS30390E page 207 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 3 CLKOUT AND I O TIMING CLKOUT UO Pin input See old value
80. 4 88 kHz 19 53 kHz 78 12 kHz 156 3 kHz 208 3 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value OxFF OxFF OxFF Ox3F Ox1F 0x17 Maximum Resolution bits 10 10 10 8 7 5 5 TABLE 10 4 REGISTERS ASSOCIATED WITH CAPTURE COMPARE AND TIMER1 Value on Value on Address Name Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh OCh PIR1 PsPIF 2 ApiF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 oDh 2 PIR2 CCP2IF generee 0 SCH PIE1 PSPIE 2 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8pn PIE2 CCP2IE 0 0 87h TRISC PORTO Data Direction Register 1111 1111 1111 1111 OEh TMR1L Holding register for the Least Significant Byte of the 16 bit TMR1 register XXXX XXXX uuuu uuuu OFh TMR1H Holding register for the Most Significant Byte of the 16 bit TMR1register XXXX XXXX uuuu uuuu 10h T1CON T1CKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMR1ON 00 0000 uu uuuu 15h CCPRIL Capture Compare PWM register1 LSB XXXX XXXx uuuu uuuu 16h CCPR1H Capture Compare PWM register MSB XXXX XXXX uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1MO 00 0000 00 0000 1Bh CCPR2L Capture Compare PWM register LSB xxx
81. AN6 1 111 channel 7 RE2 AN7 bit 2 GO DONE A D Conversion Status bit If ADON 1 1 A D conversion in progress setting this bit starts the A D conversion 0 A D conversion not in progress This bit is automatically cleared by hardware when the A D conversion is complete bit 1 Unimplemented Read as 0 bit O0 ADON A D On bit 1 A D converter module is operating 0 A D converter module is shutoff and consumes no operating current Note 1 A D channels 5 6 and 7 are implemented on the PIC16C74 74A 77 only 1997 Microchip Technology Inc DS30390E page 117 PIC16C7X FIGURE 13 2 ADCON1 REGISTER ADDRESS 9Fh U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 PCFG2 PCFG1 PCFGO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 3 Unimplemented Read as 0 bit 2 0 PCFG2 PCFGO A D Port Configuration Control bits PCFG2 PCFGO RAO RA1 RA2 RAS RA3 REO REI RE2 VREF 000 A A A A A A A A VDD 001 A A A A VREF A A A RA3 010 A A A A A D D D VDD 011 A A A A VREF D D D RA3 100 A A D D A D D D VDD 101 A A D D VREF D D D RA3 11x D D D D D D D D A Analog input D Digital I O Note 1 REO RE1 and RE2 are implemented on the PIC16C74 74A 77 only DS30390E page 118 1997 Microchip Technology Inc The ADRES register cont
82. AND I O TIMING CLKOUT UO Pin input See old value A i new value i Note Refer to Figure 17 1 for load conditions TABLE 17 3 CLKOUT AND I O TIMING REQUIREMENTS Parameter Sym Characteristic i Max Conditions No 10 TosH2ckL OSC1T to CLKOUTL 75 200 ns Note 1 11 TosH2ckH OSC1T to CLKOUTT 75 200 ns Note 1 12 TckR CLKOUT rise time 85 100 ns Note 1 13 TckF CLKOUT fall time 35 100 ns Note 1 14 TckL2ioV CLKOUT J to Port out valid 0 5TcY 20 ns Note 1 TioV2ckH Port in valid before CLKOUT T TckH2iol Port in hold after CLKOUT T ns Note 1 TosH2ioV OSC1T Q1 cycle to 50 150 ns Port out valid TosH2iol OSC1T Q2 cycle to PIC16C72 ns Port input invalid 1 O in PIC16LC72 PS ns hold time TioV2osH Port input valid to OSC1T I O in setup time ns 20 TioR Port output rise time PIC16C72 10 40 ns PIC16LC72 80 ns 21 TioF Port output fall time PIC16C72 10 40 ns PIC16LC72 80 ns Eng Tinp INT pin high or low time TCY Ge ns 23tt Trbp RB7 RB4 change INT high or low time TCY x ns These parameters are characterized but not tested TData in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested tt These parameters are asynchronous events not related to any internal clock edges Note 1 Measurements are
83. Affected Encoding Description Words Cycles Q Cycle Activity 1st Cycle 2nd Cycle Example Call Subroutine abel CALL k 0 lt k lt 2047 PC 1 TOS k PC lt 10 0 gt PCLATH lt 4 3 gt PC lt 12 11 gt None 10 Okkk kkkk kkkk Call Subroutine First return address PC 1 is pushed onto the stack The eleven bit immediate address is loaded into PC bits lt 10 0 gt The upper bits of the PC are loaded from PCLATH CALL is a two cycle instruction 1 2 Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data PC Push PC to Stack No No No No Operation Operation Operation Operation HERE CALL THERE Before Instruction PC Address HERE After Instruction PC Address THERE TOS Address HERE 1 1997 Microchip Technology Inc DS30390E page 151 PIC16C7X CLRF Clear f Syntax label CLRF f Operands 0 lt f lt 127 Operation 00h f 12Z Status Affected Z Encoding 00 0001 1fff ffff Description The contents of register f are cleared and the Z bit is set Words 1 Cycles 1 Q Cycle Activity Example Q1 Q2 Q3 Q4 Decode Read Process Write register data register f T CLRF FLAG REG Before Instruction FLAG REG 0x5A After Instruction FLAG REG 0x00 Z Li 1 CLRW Syntax Operands Operation Status Affected Encoding Description Words Cycles
84. CCP ON Load CCP1CON with this value MOVWF CCP1CON 10 2 Compare Mode Applicable Devices 72 73 73A 74 74A 76 77 In Compare mode the 16 bit CCPR1 register value is constantly compared against the TMR1 register pair value When a match occurs the RC2 CCP1 pin is Driven High Driven Low Remains Unchanged The action on the pin is based on the value of control bits CCP1M3 CCP1MO CCP1CON lt 3 0 gt At the same time interrupt flag bit CCP1IF is set FIGURE 10 3 COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will reset Timer1 but not set interrupt flag bit TMR1IF PIR1 lt 0 gt and set bit GO DONE ADCON0 lt 2 gt which starts an A D conversion CCP1 only for PIC16C72 CCP2 only for PIC16C73 73A 74 74A 76 77 Special Event Trigger A Set flag bit CCP1IF PIR1 lt 2 gt CCPR1H CCPRIL Q S Y EN F Output Comparator R Logic match RC2 CCP1 Pin TRISC 2 SE ser TMR1H TMR1L Output Enable CCP4CON 3 0 Mode Select 10 2 1 CCP PIN CONFIGURATION The user must configure the RC2 CCP1 pin as an out put by clearing the TRISC lt 2 gt bit Note Clearing the CCP1CON register will force the RC2 CCP1 compare output latch to the default low level This is not the data latch 10 22 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro nized Counter mode if the CCP module is using the compare feat
85. CZAA EE 15 PIC16G760 2 rere cete epe 14 PIC16C77 ee SIE EE WISEN POP p POR ipee Heg P Op ve et MR Oscillator Start up Timer OST Power Control Register PCON Power on Reset DOP Power up Timer PWRT esses 129 134 Power Up Timer PWRT eese 134 Time out Sequence see 135 Time out Sequence on Power up sse 139 ROR o isst ede erede ues 39 135 Port RB Interr pt rrr eene nens 143 PORTA eerie tertii enr rit n ers 29 136 PORTA Register ANA 23 25 27 43 PORTB nent eie t ep n its 29 136 PORTB Register 23 25 27 45 Kiel KEE 29 136 PORTC Register 23 25 27 48 PORTD a nia etie cete Paese dates 29 136 PORTD Register 25 27 50 Riet 29 136 PORTE Register 25 27 51 Power down Mode SLEEP wee 145 PR2 nee etae dbi a RE 29 PR2 TIET 26 28 69 Prescaler Switching Between TimerO and WDT 63 PRO MATE Universal Programmer Program Branches ceceeeeeeeeeneceeeeteseesseeseneeeseeeneenees Program Memory SC Us e EE A0 Program Memory Maps len Le 19 PIC16C73 PIC16C73A PIC16C74 E A E E A E E PIC16C74A m Program Verification sese 146 BS nire nb a a eibi ag e reet dt PS1 bit a RS MEME PSA Dit iaceat e CH EE us PSPIE bit ast PSPIF bite
86. Crystal E e EE 248 Pin Compatible Devices 271 DS30390E page 284 1997 Microchip Technology Inc PIC16C6X ON LINE SUPPORT Microchip provides two methods of on line support These are the Microchip BBS and the Microchip World Wide Web WWW site Use Microchip s Bulletin Board Service BBS to get current information and help about Microchip products Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts To provide you with the most responsive service possible the Microchip systems team monitors the BBS posts the latest component data and software tool updates provides technical help and embedded systems insights and discusses how Microchip products pro vide project solutions The web site like the BBS is used by Microchip as a means to make files and information easily available to customers To view the site the user must have access to the Internet and a web browser such as Netscape or Microsoft Explorer Files are also available for FTP download from our FTP site Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to www microchip com The file transfer site is available by using an FTP ser vice to connect to ftp ftp futureone com pub microchip The web site and file transfer site provide a variety of
87. DS30390E page 128 1997 Microchip Technology Inc PIC16C7X 14 0 SPECIAL FEATURES OF THE CPU Applicable Devices 72 73 73A 74 74A 76 77 What sets a microcontroller apart from other proces sors are special circuits to deal with the needs of real time applications The PIC16CXX family has a host of such features intended to maximize system reliability minimize cost through elimination of external compo nents provide power saving operating modes and offer code protection These are Oscillator selection Reset Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Brown out Reset BOR Interrupts Watchdog Timer WDT SLEEP Code protection D locations In circuit serial programming The PIC16CXX has a Watchdog Timer which can be shut off only through configuration bits It runs off its own RC oscillator for added reliability There are two timers that offer necessary delays on power up One is the Oscillator Start up Timer OST intended to keep the chip in reset until the crystal oscillator is stable The other is the Power up Timer PWRT which provides a fixed delay of 72 ms nominal on power up only designed to keep the part in reset while the power sup ply stabilizes With these two timers on chip most applications need no external reset circuitry SLEEP mode is designed to offer a very low current power down mode The user can wake up from SLEEP through e
88. One bit of PORTD sponding data direction bits of the TRISE register Set interrupt flag __ TRISE lt 2 0 gt must be configured as inputs set and PE Doro CET the A D port configuration bits PCFG2 PCFGO ADCON1 lt 2 0 gt must be set which will configure pins SG RE2 REO as digital I O There are actually two 8 bit latches one for data out Read _ from the PIC16 17 and one for data input The user u writes 8 bit data to PORTD data latch and reads data Chip Select from the port pin latch note that they have the same T address In this mode the TRISD register is ignored Wri S x e F rite since the microprocessor is controlling the direction of ud data flow A write to the PSP occurs when both the CS and WR Note I O pin has protection diodes to VDD and Vss lines are first detected low When either the CS or WR lines become high level triggered then the Input Buffer Full status flag bit IBF TRISE lt 7 gt is set on the Q4 clock cycle following the next Q2 cycle to signal the write is complete Figure 5 12 The interrupt flag bit PSPIF PIR1 lt 7 gt is also set on the same Q4 clock cycle IBF can only be cleared by reading the PORTD input latch The input Buffer Overflow status flag bit IBOV TRISE lt 5 gt is set if a second write to the Parallel Slave Port is attempted when the previous byte has not been read out of the buffer A read from the PSP occurs when both the CS and RD lines are first detected low The
89. PIC16C7X Device ENEE 7 3 0 Architectural OVervlew 5 2 erre rr ere te rre evertere vases eee rer e Pere Er eer Ren ei rer env HERE Re re tn 9 4 0 Memory Organization 19 5 0 WO Ports 43 6 0 Overview of Timer Modules 7 0 TimerO Module vu 8 0 Timert Module 65 9 0 Timer2 Module 69 10 0 Capture Compare PWM Module s sise 71 11 0 Synchronous Serial Port SSP Module 77 12 0 Universal Synchronous Asynchronous Receiver Transmitter USART iii 99 13 0 Analog to Digital Converter A D Module sise 117 14 0 Special Features of the CPU 15 0 Instr cti ri Set S mmaty EE 16 0 Develo prrient SUPPO Last ren ns Eier ee NEED RR PUR e TUS geed 17 0 Electrical Characteristics for PIC16C72 e 18 0 Electrical Characteristics for PIC16C73 74 essssssssssssessseeeeeneeeneene nenne nennen then nretnen re trrt re tnrtnr etre NENEA EAEE Enen enne 183 19 0 Electrical Characteristics for PIC16C73A 74A nennen nnne nre nhe treten etre trennen etre eren enne trennen 201 20 0 Electrical Characteristics for PIC16C76 77 he 21 0 DC and AC Characteristics Graphs and Tables is 241 22 0 Packaging Information zo ee rre e tne nare di Eee Verne nn ane ne FER e Ve VR e RR xU dine PER VAS EN eO Ee ER NER 251 Appendix A a Appendix B Compatibility ed corrente e C a da es ce Ce eee eee a eee Appendix Gr Whats New EE Appendix D What s Chan
90. REGISTER ADDRESS OBh 8Bh 10Bh 18Bh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W x GIE PEIE TOIE INTE RBIE TOIF INTF RBIF R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit7 GIE Global Interrupt Enable bit 1 Enables all un masked interrupts 0 Disables all interrupts bit 6 PEIE Peripheral Interrupt Enable bit 1 Enables all un masked peripheral interrupts 0 Disables all peripheral interrupts bit 5 TOIE TMRO Overflow Interrupt Enable bit 1 Enables the TMRO interrupt 0 Disables the TMRO interrupt bit 4 INTE RBO INT External Interrupt Enable bit 1 Enables the RBO INT external interrupt 0 Disables the RBO INT external interrupt bit 3 RBIE RB Port Change Interrupt Enable bit 1 Enables the RB port change interrupt 0 Disables the RB port change interrupt bit 2 TOIF TMRO Overflow Interrupt Flag bit 1 TMRO register has overflowed must be cleared in software 0 2 TMRO register did not overflow bit 1 INTF RBO INT External Interrupt Flag bit 1 The RBO INT external interrupt occurred must be cleared in software 0 The RBO INT external interrupt did not occur bit 0 RBIF RB Port Change Interrupt Flag bit 1 At least one of the RB7 RB4 pins changed state must be cleared in software 0 None of the RB7 RB4 pins have changed state Note 1 For the PIC16C73 and PIC16C74 if an interrupt
91. RWO0 RWO Bt WCOL SSPOV SSPEN ckP SSPM3 ssPve ssPMt SSPMO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit7 WCOL Write Collision Detect bit 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision bit 6 SSPOV Receive Overflow Detect bit In SPI mode 1 A new byte is received while the SSPBUF register is still holding the previous data In case of overflow the data in SSPSR register is lost Overflow can only occur in slave mode The user must read the SSP BUF even if only transmitting data to avoid setting overflow In master mode the overflow bit is not set since each new reception and transmission is initiated by writing to the SSPBUF register 0 No overflow In 2C mode 1 A byte is received while the SSPBUF register is still holding the previous byte SSPOV is a don t care in transmit mode SSPOV must be cleared in software in either mode 0 No overflow bit 5 SSPEN Synchronous Serial Port Enable bit In SPI mode 1 Enables serial port and configures SCK SDO and SDI as serial port pins 0 Disables serial port and configures these pins as UO port pins In C mode 1 Enables the serial port and configures the SDA and SCL pins as serial port pins 0 Disables serial port and configures these pins as UO port pins In both modes
92. SSP BUF register which also loads the SSPSR register Then pin RC3 SCK SCL should be enabled by setting bit CKP SSPCON 4 The master must monitor the SCL pin prior to asserting another clock pulse The slave devices may be holding off the master by stretch ing the clock The eight data bits are shifted out on the falling edge of the SCL input This ensures that the SDA signal is valid during the SCL high time Figure 11 26 An SSP interrupt is generated for each data transfer byte Flag bit SSPIF must be cleared in software and the SSPSTAT register is used to determine the status of the byte Flag bit SSPIF is set on the falling edge of the ninth clock pulse As a slave transmitter the ACK pulse from the mas ter receiver is latched on the rising edge of the ninth SCL input pulse If the SDA line was high not ACK then the data transfer is complete When the ACK is latched by the slave the slave logic is reset resets SSPSTAT register and the slave then monitors for another occurrence of the START bit If the SDA line was low ACK the transmit data must be loaded into the SSPBUF register which also loads the SSPSR reg ister Then pin RC3 SCK SCL should be enabled by setting bit CKP FIGURE 11 26 12C WAVEFORMS FOR TRANSMISSION 7 BIT ADDRESS RAM 1 Receiving Address NT X A6X ASX A4X A3 A2 X A1 SDA ACK Transmitting Data ACK D7 X D6 X D5 X D4 X D3 X D2 X D1 X DO N SCL em
93. SSP Interrupt Flag bit SSPIF to be set SSP Interrupt if enabled START condition STOP condition Data transfer byte transmitted received Master mode of operation can be done with either the slave mode idle SSPM3 SSPMO 1011 or with the slave active When both master and slave modes are enabled the software needs to differentiate the source s of the interrupt 11 5 8 MULTI MASTER MODE In multi master mode the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free The STOP P and START S bits are cleared from a reset or when the SSP module is disabled The STOP P and START S bits will toggle based on the START and STOP conditions Control of the IC bus may be taken when bit P SSPSTAT lt 4 gt is set or the bus is idle and both the S and P bits clear When the bus is busy enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs In multi master operation the SDA line must be moni tored to see if the signal level is the expected output level This check only needs to be done when a high level is output If a high level is expected and a low level is present the device needs to release the SDA and SCL lines set TRISC lt 4 3 gt There are two stages where this arbitration can be lost these are Address Transfer Data Transfer When the slave logic is enabled the slave continues to receive If arbitration
94. SSPSTAT register is used to determine the address match occurs the R W bit of the SSPSTAT reg ister is cleared The received address is loaded into the SSPBUF register When the address byte overflow condition exists then no acknowledge ACK pulse is given An overflow con dition is defined as either bit BF SSPSTAT 0 is set or bit SSPOV SSPCON 6 is set status of the byte FIGURE 11 25 12C WAVEFORMS FOR RECEPTION 7 BIT ADDRESS Receiving Address R W 0 Receiving Data ACK Receiving Data ACK a SDA Vi ATXABXASXA4XASXAZXAT YOX DeX DEN DND DEEN D D7Z D6XD5XDAD3XD2XD1 DO n ft ser IS LA AAALAABAAMABABSIAR IAA AMAIA 6 I le Bus Master l terminates transfer SSPIF PIR1 lt 3 gt Cleared in software l T l BF SSPSTAT lt 0 gt SSPBUF register is read SSPOV SSPCON lt 6 gt De Bit SSPOV is set because the SSPBUF register is still full A ACK is not sent 1997 Microchip Technology Inc DS30390E page 95 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11 5 1 3 TRANSMISSION When the R W bit of the incoming address byte is set and an address match occurs the R W bit of the SSPSTAT register is set The received address is loaded into the SSPBUF register The ACK pulse will be sent on the ninth bit and pin RC3 SCK SCL is held low The transmit data must be loaded into the
95. TppS 4 Ts I C specifications only T E Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 TOCKI io UO port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings S E Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance C only AA output access High High BUF Bus free Low Low Tcc sr IC specifications only HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 18 1 LOAD CONDITIONS Load condition 1 Load condition 2 VDD 2 RL RL 4640 CL 50pF forall pins except OSC2 but including PORTD and PORTE outputs as ports 15pF for OSC2 output Note PORTD and PORTE are not implemented on the PIC16C73 DS30390E page 188 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18 5 Timing Diagrams and Specifications FIGURE 18 2 EXTERNAL CLOCK TIMING CLKOUT TABLE 18 2 EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No Fosc External CLKIN Frequency DC E 4 MHz XT and RC osc mode Note 1 DC 4 MHz HS osc mode 04 DC 10 MHz HS osc mode 10 DC 20 MHz HS osc mode 20 DC 200 kHz LP osc mode Oscillator F
96. Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR VPP pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input volt ages 3 Negative current is defined as current sourced by the pin In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt trigger input It is not recommended that the DS30390E page 170 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C Ta lt 4125 C for extended 40 C TA 85 C for industrial and 0 C TA lt 70 C for commercial Operating voltage VDD range as described in DC spec Section 17 1 and Section 17 2 Param Characteristic Sym Min Typ Max Units Conditions No t Output High Voltage D090 I O ports Note 3 VoH VDD 0 7 V IOH 3 0 mA VDD 4 5V 40 C to 85 C DO90A VDD 0 7 V IOH 2 5 mA VDD 4 5V 40 C to 125 C D092 OSC2 CLKOUT RC osc config VoD 0 7 V IOH 1 3 mA VDD 4 5V 40 C to 85 C D092A VDD 0 7 V IOH 1 0 mA VDD 4 5V 40 C to 125 C D
97. UO 72 z3 zaAp4p4A vep7 PORT lnitial PORT settings PORTB lt 7 4 gt Inputs 5 6 1 BI DIRECTIONAL I O PORTS g PORTB lt 3 0 gt Outputs PORTB lt 7 6 gt have external pull ups and are Any instruction which writes operates internally as a not connected to other circuitry read followed by a write operation The BCF and BSF instructions for example read the register into the PORT latch PORT pins CPU execute the bit operation and write the result back GENEE d we VUE ME EN NE to the register Caution must be used when these BOEM PORTE 4 ODER pppp 11pp pppp instructions are applied to a port with both inputs and BOF PORTB m 7 LOPP PPPE 11pp Pppp outputs defined For example a BSF operation on bit5 BSE STE P M et BCF TRISB 7 10pp pppp llpp pppp of PORTB will cause all eight bits of PORTB to be read BCF TRISB 6 EE TOPP DPPP into the CPU Then the BsF operation takes place on bits and PORTB is written to the output latches If Note that the user may have expected the another bit of PORTB is used as a bi directional I O pin pin values to be 00pp ppp The 2nd BCF e g bit0 and it is defined as an input at this time the caused RB7 to be latched as the pin value input signal present on the pin itself would be read into high the CPU and rewritten to the data latch of this particular A pin actively outputting a Low or High should not be pin overwriting the previous content As long as the pin driven from external device
98. Watchdog Timer Oscillator Start up Timer and Power up Timer Timing 228 Brown out Reset Timing 228 TimerO and Timer1 External Clock Timings eene 229 Capture Compare PWM Timings CCP1 and CCP2 sss 230 Parallel Slave Port Timing PIG16C77 oci 231 1997 Microchip Technology Inc DS30390E page 281 PIC16C7X Figure 20 9 Figure 20 10 Figure 20 11 Figure 20 12 Figure 20 13 Figure 20 14 Figure 20 15 Figure 20 16 Figure 20 17 Figure 21 1 Figure 21 2 Figure 21 3 Figure 21 4 Figure 21 5 Figure 21 6 Figure 21 7 Figure 21 8 Figure 21 9 Figure 21 10 Figure 21 11 Figure 21 12 Figure 21 13 Figure 21 14 Figure 21 15 Figure 21 16 Figure 21 17 Figure 21 18 Figure 21 19 Figure 21 20 Figure 21 21 Figure 21 22 Figure 21 23 Figure 21 24 Figure 21 25 Figure 21 26 SPI Master Mode Timing CKE O 232 SPI Master Mode Timing CKE 1 232 SPI Slave Mode Timing CKE 0 233 SPI Slave Mode Timing CKE 1 233 DC Bus Start Stop Bits Timing 235 DC Bus Data Timing ssssss 236 USART Synchronous Transmission Master Slave Timing 237 USART Synchronous Receive Master Slave Timing 237 A D Conversion Timing sese 239 Typical IPD vs VDD WDT Disabled RG Mod
99. X NEW DATA A D DATA ADRES ADIF SAMPLE SAMPLING STOPPED Note 1 Ifthe A D clock source is selected as RC a time of TCY is added before the A D clock starts This allows the SLEEP instruction to be executed TABLE 18 14 A D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 130 TAD A D clock period PIC16C73 74 1 6 us Tosc based VREF gt 3 0V PIC16LC73 74 2 0 us Tosc based VREF full range PIC16C73 74 2 0 4 0 6 0 us A D RC Mode PIC16LC73 74 3 0 6 0 9 0 us A D RC Mode 131 TCNV Conversion time not including S H time 9 5 TAD Note 1 132 TACQ Acquisition time Note 2 20 us 5 m us The minimum time is the amplifier settling time This may be used if the new input voltage has not changed by more than 1 LSb i e 20 mV 9 5 12V from the last sampled voltage as stated on CHOLD 134 TGO Q4 to A D clock start Tosc 2 Ifthe A D clock source is selected as RC a time of Tcv is added before the A D clock starts This allows the SLEEP instruction to be executed 135 Tswc Switching from convert sample time 1 58 TAD These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidan
100. active operation mode are OSC1 external square wave from rail to rail all UO pins tristated pulled to VoD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VOD and Vss 4 For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula Ir VDD 2Rext mA with Rext in kOhm 5 Timer1 oscillator when enabled adds approximately 20 uA to the specification This value is from charac terization and is for design guidance only This is not tested 6 The A current is the additional current consumed when this peripheral is enabled This current should be added to the base IDD or IPD measurement 1997 Microchip Technology Inc DS30390E page 169 PIC16C7X 72 73 73A 74 74A 76 77 PIC16C72 04 Commercial Industrial Extended PIC16C72 10 Commercial Industrial Extended PIC16C72 20 Commercial Industrial Extended PIC16LC72 04 Commercial Industrial Applicable Devices 17 3 DC Characteristics Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended 40 C lt Ta lt 85 C for industrial and DC CHARACTERISTICS 0 C lt TA lt 70 C for commercial Operating voltage VDD range
101. and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear 1997 Microchip Technology Inc DS30390E page 107 PIC16C7X 12 2 2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 12 10 The data is received on the RC7 RX DT pin and drives the data recovery block The data recovery block is actually a high speed shifter operating at x16 times the baud rate whereas the main receive serial shifter oper ates at the bit rate or at FOSC Once Asynchronous mode is selected reception is enabled by setting bit CREN RCSTA 4 The heart of the receiver is the receive serial shift reg ister RSR After sampling the STOP bit the received data in the RSR is transferred to the RCREG register if it is empty If the transfer is complete flag bit RCIF PIR1 lt 5 gt is set The actual interrupt can be enabled disabled by setting clearing enable bit RCIE PIE1 lt 5 gt Flag bit RCIF is a read only bit which is cleared by the hardware It is cleared when the RCREG register has been read and is empty The RCREG is a FIGURE 12 10 USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK double buffered register i e it is a two deep FIFO It is possible for two bytes of data to be received and trans ferred to the RCREG FIFO and a third byte begin shift ing to the RSR register On the detection of the STOP bit of the third byte if the RCREG register is still full then overrun error bi
102. bit address with start and stop bit interrupts enabled 1111 DC slave mode 10 bit address with start and stop bit interrupts enabled DS30390E page 84 1997 Microchip Technology Inc Applicable Devices 72 73 73A 76 77 PIC1 6C7X 11 3 1 SPI MODE FOR PIC16C76 77 The SPI mode allows 8 bits of data to be synchro nously transmitted and received simultaneously To accomplish communication typically three pins are used Serial Data Out SDO RC5 SDO Serial Data In SDI RC4 SDI SDA Serial Clock SCK RC3 SCK SCL Additionally a fourth pin may be used when in a slave mode of operation Slave Select SS RA5 SS AN4 When initializing the SPI several options need to be specified This is done by programming the appropriate control bits in the SSPCON register SSPCON lt 5 0 gt and SSPSTAT lt 7 6 gt These control bits allow the fol lowing to be specified Master Mode SCK is the clock output Slave Mode SCK is the clock input Clock Polarity Idle state of SCK Clock edge output data on rising falling edge of SCK Clock Rate Master mode only Slave Select Mode Slave mode only The SSP consists of a transmit receive Shift Register SSPSR and a buffer register SSPBUF The SSPSR shifts the data in and out of the device MSb first The SSPBUF holds the data that was written to the SSPSR until the received data is ready Once the 8 bits of data have be
103. clock source is selected as RC a time of TCY is added before the A D clock starts This allows the SLEEP instruction to be executed TABLE 19 14 A D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 130 TAD A D clock period PIC16C73A 74A 1 6 us Tosc based VREF 2 3 0V PIC16LC73A 74A 2 0 us Tosc based VREF full range PIC16C73A 74A 2 0 4 0 6 0 us A D RC Mode PIC16LC73A 74A 3 0 6 0 9 0 us A D RC Mode 131 TcNv Conversion time not including S H time 9 5 TAD Note 1 132 TACQ Acquisition time Note 2 20 us 5 us The minimum time is the amplifier settling time This may be used if the new input voltage has not changed by more than 1 LSb i e 20 0 mV 9 5 12V from the last sampled voltage as stated on CHOLD 134 TGO Q4 to A D clock start Tosc 2 Ifthe A D clock source is selected as RC a time of TCY is added before the A D clock starts This allows the SLEEP instruction to be executed 135 Tswc Switching from convert sample time 1 58 TAD These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested S This specification ensured by design 1 ADRES register may be read on the following Tcy cycle See Section 13 1 for min conditio
104. converted The A D operation is independent of the state of the CHS2 CHSO bits and the TRIS bits Note 1 When reading the port register all pins configured as analog input channels will read as cleared a low level Pins config ured as digital inputs will convert an ana log input Analog levels on a digitally configured input will not affect the conver sion accuracy Note 2 Analog levels on any pin that is defined as a digital input including the AN7 ANO pins may cause the input buffer to con sume current that is out of the devices specification TABLE 13 1 TAD vs DEVICE OPERATING FREQUENCIES AD Clock Source TAD Device Frequency Operation ADCS1 ADCSO 20 MHz 5 MHz 1 25 MHz 333 33 kHz 2Tosc 00 100 ns 400 ns 2 1 6 us 6 us 8Tosc 01 400 nsl 1 6 us 6 4 us 24 us 9 32TOSC 10 1 6 us 6 4 us 25 6 us 96 us Rc 11 2 6 ust14 2 6 us 14 2 6 ust14 2 6 ust Legend Shaded cells are outside of recommended range Note 1 The RC source has a typical TAD time of 4 us 2 These values violate the minimum required TAD time 3 For faster conversion times the selection of another clock source is recommended 4 When device frequency is greater than 1 MHz the RC A D conversion clock source is recommended for sleep operation only 5 For extended voltage devices LC please refer to Electrical Specifications section 1997 Microchip Technology Inc DS
105. data T MOVF FSR O0 After Instruction W value in FSR register Z 1 MOVLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example MOVWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Move Literal to W label MOVLW k 0 lt k lt 255 k W None i1 00xx kkkk kkkk The eight bit literal k is loaded into W register The don t cares will assemble as O s 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data W MOVLW 0x5A After Instruction W Ox5A Move W to f label MOVWF f O lt f lt 127 W f None 00 0000 IL fff ffff Move data from W register to register IT Q1 Q2 Q3 Q4 Decode Read Process Write register data register f T MOVWF OPTION REG Before Instruction OPTION OxFF W Ox4F After Instruction OPTION Ox4F W Ox4F DS30390E page 156 1997 Microchip Technology Inc PIC16C7X NOP No Operation Syntax label NOP Operands None Operation No operation Status Affected None Encoding 00 0000 Oxx0 0000 Description No operation Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No No No Operation Operation Operation Example NOP OPTION Load Option Regis
106. data and wake the device from sleep FIGURE 11 10 SPI MASTER SLAVE CONNECTION PIC16C76 77 SPI Slave SSPM3 SSPMO 010xb Serial Input Buffer SSPBUF 1 Shift Register SSPBUF 1 Shift Register Serial Input Buffer SSPSR PROCESSOR 1 Serial Clock SSPSR DS30390E page 86 1997 Microchip Technology Inc Applicable Devices D C 1 6C7X 72 73 73A 74 74A 76 77 The SS pin allows a synchronous slave mode The SPI must be in slave mode SSPCON lt 3 0 gt 04h Note When the SPI is in Slave Mode with SS pin and the TRISA lt 5 gt bit must be set for the synchro control enabled SSPCON lt 3 0 gt 0100 nous slave mode to be enabled When the SS pin is the SPI module will reset if the SS pin is set low transmission and reception are enabled and to VDD the SDO pin is driven When the SS pin goes high the SDO pin is no longer driven even if in the mid dle of a transmitted byte and becomes a floating Note If the SPI is used in Slave Mode with CKE 1 then the SS pin control must be output If the SS pin is taken low without resetting SEBES SPI mode the transmission will continue from the To emulate two wire communication the SDO pin can point at which it was taken high External pull up be connected to the SDI pin When the SPI needs to pull down resistors may
107. deg Synchronous Slave Transmit ssss Transmit Block Diagram eesees UV Erasable Devices AA Ww W Register BLEU DEE Wake up from SLEEP ss Watchdog Timer WDT m WEOL cas Est eerta NN tre ARIS Block Diagram E Du io Programming Considerations s 144 Timeout Er Mio mE H WR pin nr X XMIT MODE raaa a aan A dees 98 Z EE 30 LIST OF EXAMPLES Example 3 1 Instruction Pipeline Flow 17 Example 4 1 Call of a Subroutine in Page 1 from Page EE Example 4 2 Indirect Addressing Example 5 1 Initializing PORTA Example 5 2 Initializing PORTB Example 5 3 Initializing PORTO sseeess Example 5 4 Read Modify Write Instructions on an NVO Port three ecd 53 Example 7 1 X Changing Prescaler Timer0WDT 63 Example 7 2 Changing Prescaler WDT Timer0 63 Example 8 1 Reading a 16 bit Free Running Timer 67 Example 10 1 Changing Between Capture Prescalets rece 73 Example 10 2 PWM Period and Duty Cycle Calculation eege idee 75 Example 11 1 Loading the SSPBUF SSPSR Reglster ss sense 80 Example 11 2 Loading the SSPBUF SSPSR Register PIC16C76 77 Example 12 1 Calculating Baud Rate Error Equation 13 1 A D Minimum Charging Time Example 13 1 Calculating the Minim
108. does not include Dambar protrusion allowable Dambar protrusion shall be 0 08m m 0 003 max 3 This outline conforms to JEDEC MS 026 1997 Microchip Technology Inc DS30390E page 259 PIC16C7X 22 10 Package Marking Information 28 Lead SSOP Example XXXXXXXXXXXX PIC16C72 XXXXXXXXXXXX 201 58025 n AABBCAE cy 9517SBP 28 Lead PDIP Skinny DIP Example MMMMMMMMMMMM PIC16C73 10 SP XXXXXXXXXXXXXXX O AABBCDE O O AABBCDE O O LAN MICROCHIP O LAN MICROCHIP 28 Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX PIC16C73 JW D C XXXXXXXXXXX D MICROCHIP AABBCDE MICROCHIP 951 7CAT 28 Lead SOIC Example MMMMMMMMMMMMMMMM PIC16C73 10 SO XXXXXXXXXXXXXXXXXXXX AN AABBCDE AN 945 CAA O O Legend MM M Microchip part number information XX X Customer specific information AA Year code last 2 digits of calender year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured C Chandler Arizona U S A S Tempe Arizona U S A D4 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Note Standard OTP marking consi
109. edge appears on the RBO INT pin flag bit INTF INTCON lt 1 gt is set This interrupt can be disabled by clearing enable bit INTE INTCON lt 4 gt Flag bit INTF must be cleared in software in the interrupt service rou tine before re enabling this interrupt The INT interrupt can wake up the processor from SLEEP if bit INTE was set prior to going into SLEEP The status of global inter rupt enable bit GIE decides whether or not the proces sor branches to the interrupt vector following wake up See Section 14 8 for details on SLEEP mode 14 5 2 TMRO INTERRUPT An overflow FFh 00h in the TMRO register will set flag bit TOIF INTCON lt 2 gt The interrupt can be enabled disabled by setting clearing enable bit TOIE INTCON 5 Section 7 0 14 5 8 PORTB INTCON CHANGE An input change on PORTB lt 7 4 gt sets flag bit RBIF INTCON lt 0 gt The interrupt can be enabled disabled by setting clearing enable bit RBIE INTCON 4 Section 5 2 Note Forthe PIC16C73 74 if a change on the UO pin should occur when the read opera tion is being executed start of the Q2 cycle then the RBIF interrupt flag may not get set EXAMPLE 14 1 SAVING STATUS W AND PCLATH 14 6 Context Saving During Interrupts Applicable Devices 72 73 73A 74 74A 76 77 During an interrupt only the return PC value is saved on the stack Typically users may wish to save ke
110. for each received byte of data except for the last byte To signal the end of data to the slave transmitter the master does not generate an acknowledge not acknowledge The slave then releases the SDA line so the master can generate the STOP condition The master can also generate the STOP condition during the acknowledge pulse for valid termination of data transfer 11110 A9 A8 R W ACK A7 A6 A5 A4 A3 A2 A1 AO ACK If the slave needs to delay the transmission of the next sent by slave 4 byte holding the SCL line low will force the master into 8 0 for write a wait state Data transfer continues when the slave Kg SE releases the SCL line This allows the slave to move the ACK Acknowledge received data or fetch the data it needs to transfer before allowing the clock to start This wait state tech nique can also be implemented at the bit level Figure 11 18 The slave will inherently stretch the clock when it is a transmitter but will not when it is a receiver The slave will have to clear the SSPCON lt 4 gt bit to enable clock stretching when it is a receiver 11 4 8 TRANSFER ACKNOWLEDGE All data must be transmitted per byte with no limit to the number of bytes transmitted per data transfer After each byte the slave receiver generates an acknowl edge bit ACK Figure 11 17 When a slave receiver doesn t acknowledge the slave address or received data the master must abort t
111. iP mode 32 kHz 3 0V 32 kHz 3 0V IPD 0 9 uA typ at 4 0V IPD 13 5 uA max at3 0V IPD 13 5 uA max at 3 0V Freq 200 kHz max Freq 200 kHz max Freq 200 kHz max The shaded sections indicate oscillator selections which are tested for functionality but not for MIN MAX specifications It is recommended that the user select the device type that ensures the specifications required 1997 Microchip Technology Inc DS30390E page 183 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18 1 DC Characteristics PIC16C73 74 04 Commercial Industrial PIC16C73 74 10 Commercial Industrial PIC16C73 74 20 Commercial Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for industrial and 0 C TA 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 4 0 6 0 V XT RC and LP osc configuration D001A 4 5 5 5 V HS osc configuration D002 RAM Data Retention VDR 1 5 V Voltage Note 1 DOOS VDD start voltage to VPOR Vss V See section on Power on Reset for details ensure internal Power on Reset signal D004 VDD rise rate to ensure SvDD 0 05 V ms See section on Power on Reset for details internal Power on Reset signal D010 Supply Current Note 2 5 IDD 2 7 5 mA XT RC osc
112. if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line TR max tsu DAT 1000 250 1250 ns according to the standard mode DC bus specification before the SCL line is released 1997 Microchip Technology Inc DS30390E page 236 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 15 USART SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING pin RC7 RX DT pin M TEE 121 gt 120 Note Refer to Figure 20 1 for load conditions TABLE 20 11 USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 120 TckH2dtV SYNC XMIT MASTER amp SLAVE PIC16C76 77 a 80 ns Clock high to data out valid PIC16LC76 77 100 ns 121 Tckrf Clock out rise time and fall time PIC16C76 77 45 ns Master Mode PIC16LC76 77 m 50 ns 122 Tdtrf Data out rise time and fall time PIC16C76 77 45 ns PIC16LC76 77 50 ns T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 20 16 USART SYNCHRONOUS RECEIVE MASTER SLAVE TIMING RC6 TX CK pin 125 RC7 RX DT pin X Note Refer to Figure 20 1 for load conditions
113. iret herren eter TMRTIF bit citt brat goes det ens TMR1L TMR1L Register A TMRION bit inne tenet cen nacta eie dian TMR2 TMRe Register sise TMRP2IE TI TMR2IF bit TMR2ON bit TO bit TOUTPSO bit TOUTPS bit TOUTPS2 bit TOUTPSS bit TRISA TRISA Register TRISB TRISG ee TRISD rte ret rm trate o P ag e TRISD Register RRE TRISE Register ern nene Two s Complement TXIE Dit E a XIE D S ee extet Den Ld Ke TXREG s RRE ERR EE DS30390E page 278 1997 Microchip Technology Inc PIC16C7X Ainsi neti Sets ied 78 83 Universal Synchronous Asynchronous Receiver Transmitter USART iur an cays trates shea oe D Per enn 99 Update Address bit UA ssseesee 78 83 USART Asynchronous Mode 106 Asynchronous Receiver 108 Asynchronous Reception 109 Asynchronous Transmission e Asynchronous Transmitter 106 Baud Rate Generator BRG sss 101 Receive Block Diagram LA SAMPLING 2 5 6 n Pc te eei Synchronous Master Mode nescence Synchronous Master Reception ve Synchronous Master Transmission eeeeeeeeeee 110 Synchronous Slave Mode s es Synchronous Slave Reception
114. not implemented on the Note The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF PIR1 lt 0 gt Timer1 must be configured for either timer or synchro nized counter mode to take advantage of this feature If Timer1 is running in asynchronous counter mode this reset operation may not work In the event that a write to Timer1 coincides with a spe cial event trigger from CCP1 or CCP2 the write will take precedence In this mode of operation the CCPRxH CCPRXL regis ters pair effectively becomes the period register for Timer1 8 6 Resetting of Timer1 Register Pair TMR1H TMR1L Applicable Devices 72 73 73A 74 74A 76 77 TMR1H and TMR1L registers are not reset to 00h ona POR or any other reset except by the CCP1 and CCP2 special event triggers T1CON register is reset to 00h on a Power on Reset or a Brown out Reset which shuts off the timer and leaves a 1 1 prescale In all other resets the register is unaffected 8 7 Timer1 Prescaler Applicable Devices 72 73 73A 74 74A 76 77 The prescaler counter is cleared on writes to the TMR1H or TMR1L registers TABLE 8 2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF
115. pF 10 22 pF These values are for design guidance only See notes at bottom of page Resonators Used 455 kHz Panasonic EFO A455K04B 0 3 2 0 MHz Murata Erie CSA2 00MG 0 5 4 0 MHz Murata Erie CSA4 00MG 0 5 8 0 MHz Murata Erie CSA8 00MT 0 5 16 0 MHz Murata Erie CSA16 00MX 0 5 All resonators used did not have built in capacitors TABLE 14 2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Type T Ee SE LP 32 KHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 200 kHz 47 68 pF 47 68 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 33 pF 15 33 pF 15 33 pF 15 33 pF These values are for design guidance only See notes at bottom of page Crystals Used 32 kHz Epson C 001R32 768K A 20 PPM 200 kHz STD XTL 200 000KHz 20 PPM 1MHz ECS ECS 10 13 1 50 PPM 4 MHz ECS ECS 40 20 1 50 PPM 8 MHz EPSON CA 301 8 000M C 30 PPM 20 MHz EPSON CA 301 20 000M C 30 PPM Note 1 Recommended values of C1 and C2 are identical to the ranges tested Table 14 1 2 Higher capacitance increases the stability of oscillator but also increases the start up time 8 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropri ate values of external components 4 Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive lev
116. pin is a Schmitt Trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin DS30390E page 204 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended 40 C TA 85 C for industrial and DC CHARACTERISTICS 0 C lt TA 70 C for commercial Operating voltage VDD range as described in DC spec Section 19 1 and Section 19 2 Param Characteristic Sym Min Typ Max Units Conditions No Output High Voltage D090 O ports Note 3 VoH VDD 0 7 V IOH 3 0 mA VDD 4 5V 40 C to 85 C DO90A VDD 0 7 V IOH 2 5 mA VDD 4 5V 40 C to 125 C D092 OSC2 CLKOUT RC osc config VoD 0 7 V oHe 1 83 mA VDD ADM 40 C to 85 C D092A VDD 0 7 V IOH 1 0 mA VDD 4 5V 40 C to 125 C D150 Open Drain High Voltage VoD 14 V RAA pin Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 15 pF In XT HS and LP modes when exter nal clock is used to drive OSC1
117. prescaler Timer1 16 bit timer counter with prescaler can be incremented during sleep via external crystal clock Timer2 8 bit timer counter with 8 bit period register prescaler and postscaler Capture Compare PWM module s Capture is 16 bit max resolution is 12 5 ns Compare is 16 bit max resolution is 200 ns PWM max resolution is 10 bit Low power high speed CMOS EPROM Brown out Reset BOR technology Fully static design PIC16C7X Features 72 73 73A 74 74A 76 77 Program Memory EPROM x 14 2K 4K 4K 4K 4K 8K 8K Data Memory Bytes x 8 128 192 192 192 192 368 368 I O Pins 22 22 22 33 33 22 33 Parallel Slave Port Yes Yes Yes Capture Compare PWM Modules 1 2 2 2 2 2 2 Timer Modules 3 3 3 3 3 3 3 A D Channels 5 5 5 8 8 5 8 Serial Communication SPI PC SPC SPI C SPI C SPI PC SPII C SPI PC USART USART USART USART USART USART In Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes Brown out Reset Yes Yes Yes Yes Yes Interrupt Sources 8 11 11 12 12 11 12 1997 Microchip Technology Inc DS30390E page 1 PIC16C7X Pin Diagrams SDIP SOIC Windowed Side Brazed Ceramic MCLR VPP VY RB7 MCLR VPP RB7 RAO ANO lt gt RB6 RAO ANO lt gt RB6 RA1 AN1 RB5 RA1 AN1 RB5 RA2 AN2 lt RB4 RA2 AN2 RB4 RA3 AN3 VREF ap RB3 RA3 AN3 VREF lt t RB3
118. programming clock RB7 40 44 17 VO TTL ST Interrupt on change pin Serial programming data Legend I input O output UO input output P power Not used TTL TTL input ST Schmitt Trigger input Note 1 This buffer is a Schmitt Trigger input when configured as an external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode 3 This buffer is a Schmitt Trigger input when configured as general purpose UO and a TTL input when used in the Parallel Slave Port mode for interfacing to a microprocessor bus 4 This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise 1997 Microchip Technology Inc DS30390E page 15 PIC16C7X TABLE 3 3 PIC16C74 74A 77 PINOUT DESCRIPTION Con di DIP PLCC QFP I O P Buffer Pin Name Pin Pin Pin Type Type Description PORTE is a bi directional I O port RCO T1OSO T1CKI 15 16 32 yo ST RCO can also be the Timer1 oscillator output or a Timer1 clock input RC1 T10SI CCP2 16 18 35 UO ST RC1 can also be the Timer oscillator input or Capture2 input Compare2 output PWM2 output RC2 CCP1 17 19 36 yo ST RC2 can also be the Capture1 input Compare1 output PWM output RC3 SCK SCL 18 20 37 yo ST RC3 can also be the synchronous serial clock input output for both SPI and DC modes RC4 SDI SDA 23 25 42 yo ST RC4 can also be the SPI Data In SPI mode or data I O I2C
119. reduce quan tization error is to increase the resolution of the A D converter Offset error measures the first actual transition of a code versus the first ideal transition of a code Offset error shifts the entire transfer function Offset error can be calibrated out of a system or introduced into a sys tem through the interaction of the total leakage current and source impedance at the analog input Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error This error appears as a change in slope of the transfer function The difference in gain error to full scale error is that full scale does not take offset error into account Gain error can be calibrated out in soft ware Linearity error refers to the uniformity of the code changes Linearity errors cannot be calibrated out of the system Integral non linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code Differential non linearity measures the maximum actual code width versus the ideal code width This measure is unadjusted The maximum pin leakage current is 1 LA In systems where the device frequency is low use of the A D RC clock is preferred At moderate to high fre quencies TAD should be derived from the device oscil lator TAD must not violate the minimum and should be lt 8 us for preferred operation This is because TAD
120. result is placed in the W register 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data W IORLW 0x35 Before Instruction W Ox9A After Instruction W OxBF Z 1 1997 Microchip Technology Inc DS30390E page 155 PIC16C7X IORWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example MOVF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Inclusive OR W with f label IORWF fd O lt f lt 127 de 0 1 W OR f destination Z 00 0100 dfff ffff Inclusive OR the W register with regis ter f If d is O the result is placed in the W register If d is 1 the result is placed back in register f 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination T IORWF RESULT 0 Before Instruction RESULT 0x13 W 0x91 After Instruction RESULT 0x13 W 0x93 Z 1 Move f label MOVF fd O lt f lt 127 de 0 1 f destination Z 00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d If d 0 destination is W register If d 1 the destination is file register f itself d 1 is useful to test a file regis ter since status flag Z is affected 1 1 Q1 Q2 Q3 Q4 Write to destination Decode Read Process register
121. services Users may download files for the latest Development Tools Data Sheets Application Notes User s Guides Articles and Sample Programs A vari ety of Microchip specific business information is also available including listings of Microchip sales offices distributors and factory representatives Other data available for consideration is Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Connecting to the Microchip BBS Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications net work Internet You can telnet or ftp to the Microchip BBS at the address mchipbbs microchip com CompuServe Communications Network When using the BBS via the Compuserve Network in most cases a local call is your only expense The Microchip BBS connection does not use CompuServe membership services therefore you do not need CompuServe membership to join Microchip s BBS There is no charge for connecting to the Microchip BBS The procedure to connect will vary slightly from country to country Please check with your local CompuServe agent for details if you have a problem CompuServe service allow multiple users various baud rates depending on the local point of access The following co
122. shown in Example 4 2 in page 0 000h 7FFh EXAMPLE 4 2 INDIRECT ADDRESSING moviw 0x20 initialize pointer movwf FSR to RAM NEXT CLEE INDF clear INDF register incf FSR F inc pointer btfss FSR 4 all done goto NEXT no clear next CONTINUE yes continue FIGURE 4 18 DIRECT INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1 RPO 6 from opcode 7 FSR register L J N A J V V V V bank select location select bank select location select N c Data Memory 7Fh FFh 17Fh 1FFh Bank 0 Bank1 Bank2 Bank 3 For register file map detail see Figure 4 4 and Figure 4 5 1997 Microchip Technology Inc DS30390E page 41 PIC16C7X NOTES DS30390E page 42 1997 Microchip Technology Inc PIC16C7X 5 0 1 0 PORTS Applicable Devices 72 73 73A 74 74A 76 77 Some pins for these I O ports are multiplexed with an alternate function for the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose O pin 5 1 PORTA and TRISA Registers Applicable Devices 72 vapaAp4pa4A e 77 PORTA is a 6 bit latch The RA4 TOCKI pin is a Schmitt Trigger input and an open drain output All other RA port pins have TTL input levels and full CMOS output drivers All pins have data direction bits TRIS registers which can configure these pins as output or input
123. taken in RC Mode where CLKOUT output is 4 x TOSC DS30390E page 174 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING PWRT Time out 32 OSC SC d Time out Internal i d RESET i Watchdog r d Timer RESET i FIGURE 17 5 BROWN OUT RESET TIMING TABLE 17 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 30 TmcL MCLR Pulse Width low 2 us VDD 5V 40 C to 125 C 31 Twdt Watchdog Timer Time out Period 7 18 33 ms VDD 5V 40 C to 125 C No Prescaler 32 Tost Oscillation Start up Timer Period 1024Tosc Tosc OSC period 33 Tpwrt Power up Timer Period 28 72 132 ms VDD 5V 40 C to 125 C 34 Tioz UO Hi impedance from MCLR Low 2 1 us or Watchdog Timer Reset 35 TBOR Brown out Reset pulse width 100 us VDD lt BVDD D005 R These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 175 PIC16C7X A
124. that the user needs to update the address in the SSPADD register 0 Address does not need to be updated bit 0 BF Buffer Full Status bit Receive SPI and C modes 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty Transmit I2C mode only 1 Transmit in progress SSPBUF is full 0 Transmit complete SSPBUF is empty 1997 Microchip Technology Inc DS30390E page 83 D C 1 6C7X Applicable Devices T2 73 73A174 74A176 77 FIGURE 11 8 SSPCON SYNC SERIAL PORT CONTROL REGISTER ADDRESS 14h PIC16C76 77 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO R Readable bit U Unimplemented bit read as 0 n Value at POR reset bit7 WCOL Write Collision Detect bit 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision bit 6 SSPOV Receive Overflow Indicator bit In SPI mode 1 A new byte is received while the SSPBUF register is still holding the previous data In case of overflow the data in SSPSR is lost Overflow can only occur in slave mode The user must read the SSPBUF even if only transmitting data to avoid setting overflow In master mode the overflow bit is not set since each new reception and transmission is initiated by writing to the SSPBUF register 0 No ove
125. the ID location are used 14 11 In Circuit Serial Programming Applicable Devices 72 73 73A 74 74A 76 77 PIC16CXX microcontrollers can be serially pro grammed while in the end application circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product This also allows the most recent firmware or a custom firm ware to be programmed The device is placed into a program verify mode by holding the RB6 and RB7 pins low while raising the MCLR VPP pin from VIL to VIHH see programming specification RB6 becomes the programming clock and RB7 becomes the programming data Both RB6 and RB7 are Schmitt Trigger inputs in this mode After reset to place the device into programming verify mode the program counter PC is at location 00h A 6 bit command is then supplied to the device Depending on the command 14 bits of program data are then sup plied to or from the device depending if the command was a load or a read F TD311etthe tailits os5 er 15alde pro DS30390E page 146 1997 Microchip Technology Inc PIC16C7X 15 0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14 bit word divided into an OPCODE which specifies the instruction type and one or more operands which further spe
126. uuuu uuuu 07h PORTC PORTO Data Latch when written PORTC pins when read XXXX xxxx uuuu uuuu 08h PORTD PORTD Data Latch when written PORTD pins when read Xxxx xxxx uuuu uuuu o9h PORTE RE2 RE1 REO xxx uuu oAh 1 4 PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 OBh 2 INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u OCh PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 0000 0000 0000 0000 ODh PIR2 CCP2IF Q 0 OEh TMR1L Holding register for the Least Significant Byte of the 16 bit TMR1 register XXXX XXXX uuuu uuuu OFh TMR1H Holding register for the Most Significant Byte of the 16 bit TMR1 register XXXX xxxx uuuu uuuu 10h TICON T1CKPS1 T1CKPSO T OSCEN TISYNC TMR1CS TMR1ON 00 0000 uu uuuu 11h TMR2 Timer2 module s register 0000 0000 0000 0000 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 15h CCPR1L Capture Compare PWM Register1 LSB XXXX xxxx uuuu uuuu 16h CCPR1H Capture Compare PWM Register1 MSB XXXX xxxx uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1MO 00 0000 00 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 19h TXREG U
127. when derived from TOSC is kept away from on chip phase clock transitions This reduces to a large extent the effects of digital switching noise This is not possi ble with the RC derived clock The loss of accuracy due to digital switching noise can be significant if many I O pins are active In systems where the device will enter SLEEP mode after the start of the A D conversion the RC clock source selection is required In this mode the digital noise from the modules in SLEEP are stopped This method gives high accuracy 13 7 Effects of a RESET Applicable Devices 72 73 73A 74 74A 76 77 A device reset forces all registers to their reset state This forces the A D module to be turned off and any conversion is aborted The value that is in the ADRES register is not modified for a Power on Reset The ADRES register will contain unknown data after a Power on Reset DS30390E page 124 1997 Microchip Technology Inc PIC16C7X 13 8 Use of the CCP Trigger Applicable Devices 72 73 73A 74 74A 76 77 Note In the PIC16C72 the special event trig ger is implemented in the CCP1 module An A D conversion can be started by the special event trigger of the CCP2 module CCP1 on the PIC16C72 only This requires that the CCP2M3 CCP2M0 bits CCP2CON lt 3 0 gt be programmed as 1011 and that the A D module is enabled ADON bit is set When the trigger occurs the GO DONE bit will be set s
128. 0 Supply Current Note 2 5 D013 10 20 mA HS osc configuration Fosc 20 MHz VDD 5 5V D015 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 D020 Power down Current IPD 10 5 42 pA VDD 4 0V WDT enabled 40 C to 85 C D021 Note 3 5 1 5 16 uA VDD 4 0V WDT disabled 0 C to 70 C D021A 15 19 uA VDD 4 0V WDT disabled 40 C to 85 C D021B 25 19 uA VDD 4 0V WDT disabled 40 C to 125 C D023 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 These parameters are characterized but not tested T Daetain Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as UO pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all UO pins tristated pulled to VoD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode w
129. 0 Before Instruction REG1 0xA5 After Instruction REGI 0xA5 W Ox5A TRIS Load TRIS Register Syntax abe TRIS f Operands 5 lt f lt 7 Operation W gt TRIS register f Status Affected None Encoding 00 0000 Qi NOTTE Description The instruction is supported for code compatibility with the PIC16C5X prod ucts Since TRIS registers are read able and writable the user can directly address them Words 1 Cycles 1 Example To maintain upward compatibility with future PIC16CXX products do not use this instruction 1997 Microchip Technology Inc DS30390E page 161 PIC16C7X XORLW Exclusive OR Literal with W Syntax labe XORLW k Operands 0 lt k lt 255 Operation W XOR k gt W Status Affected Z Encoding 11 1010 kkkk kkkk Description The contents of the W register are XOR ed with the eight bit literal k The result is placed in the W regis ter Words 1 Cycles 1 Q Cycle Activity Example Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data W XORLW OxAF Before Instruction W OxB5 After Instruction W OxlA XORWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Exclusive OR W with f labe XORWF fd O lt f lt 127 de 0 1 W XOR f gt destination Z 00 0110 dfff ffff Exclusive OR the contents of the W register with reg
130. 0 TMR10ON Timer1 On bit 1 Enables Timeri 0 Stops Timer1 1997 Microchip Technology Inc DS30390E page 65 PIC16C7X 8 1 Timer1 Operation in Timer Mode Applicable Devices 72 73 73A 74 74A 76 77 Timer mode is selected by clearing the TMR1CS TICON lt 1 gt bit In this mode the input clock to the timer is Fosc 4 The synchronize control bit TISYNC T1CON lt 2 gt has no effect since the internal clock is always in sync 8 2 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS In this mode the timer increments on every rising edge of clock input on pin RC1 T1OSI CCP2 when bit T1OSCEN is set or pin RCO T1OSO T1CKI when bit TIOSCEN is cleared If TTSYNC is cleared then the external clock input is synchronized with internal phase clocks The synchro nization is done after the prescaler stage The pres caler stage is an asynchronous ripple counter In this configuration during SLEEP mode Timer1 will not increment even if the external clock is present since the synchronization circuit is shut off The pres caler however will continue to increment FIGURE 8 2 TIMER1 BLOCK DIAGRAM Set flag bit TMRAIF on Overflow B 8 2 1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in syn chronized counter mode it must meet certain require ments The external clock requirement is
131. 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 Unimplemented Read as 0 bit 6 3 TOUTPS3 TOUTPSO Timer2 Output Postscale Select bits 0000 1 1 Postscale 0001 1 2 Postscale 1111 1 16 Postscale bit 2 TMR2ON Timer2 On bit 1 Timer2 is on 0 Timer2 is off bit 1 0 T2CKPS1 T2CKPSO Timer2 Clock Prescale Select bits 00 Prescaler is 1 01 Prescaler is 4 1x Prescaler is 16 TABLE 9 1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh OCH PIR1 PSPIF 2 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRAIF 0000 0000 0000 0000 SCH PIE1 PSPIE 2 ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRAIE 0000 0000 0000 0000 11h TMR2 Timer2 modules register 0000 0000 0000 0000 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Timer2 module Note 1 Bits PSPI
132. 0 kHz mode 4 7 us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 1 3 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 102 TR SDA and SCL rise 100 kHz mode 1000 ns time 400 kHz mode 20 0 1Cb 300 ns Cbis specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode 300 ns 400 kHz mode 20 0 1Cb 300 ns Cbis specified to be from 10 to 400 pF 90 TSU STA START condition 100 kHz mode 4 7 us Only relevant for repeated setup time 400 kHz mode 0 6 Z uS START condition 91 THD STA START condition hold 100 kHz mode 4 0 us After this period the first clock time 400 kHz mode 0 6 SS us pulse is generated 106 THD DAT Data input hold time 100 kHz mode 0 ns 400 kHz mode 0 0 9 us 107 TSU DAT Data input setup time 100 kHz mode 250 ns Note 2 400 kHz mode 100 Ce ns 92 TSU STO STOP condition setup 100 kHz mode 4 7 us time 400 KHz mode 0 6 us 109 TAA Output valid from 100 kHz mode 3500 ns Note 1 clock 400 kHz mode ns 110 TBUF Bus free time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 1 3 Z us before a new transmission can start Cb Bus capacitive loading 400 pF Note 1 Asatransmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of START or STOP conditions 2 Afast mode 400 kHz I C bus device can be used in a standard mod
133. 0000 000x 0000 000u 10Bh 18Bh DCH PIR1 PsPIF 2 ADIF RCIF TXIF2 SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PSPIE 2 ADIE RCIE TXIEO SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 Holding register for the Least Significant Byte of the 16 bit TMR1 register XXXX XXXX UUUU uuuu Holding register for the Most Significant Byte of the 16 bit TMR1 register XXXX XXXX UUUU uuuu 10h TICON T1CKPS1 T1CKPSO TIOSCEN TISYNC THR1CS TMRION 00 0000 uu uuuu Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Timer1 module Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear 2 The PIC16C72 does not have a Parallel Slave Port or a USART these bits are unimplemented read as 0 DS30390E page 68 1997 Microchip Technology Inc PIC16C7X 9 0 TIMER2 MODULE Applicable Devices 72 73 73A 74 74A 76 77 Timer2 is an 8 bit timer with a prescaler and a postscaler It can be used as the PWM time base for PWM mode of the CCP module s The TMR2 register is readable and writable and is cleared on any device reset The input clock Fosc 4 has a prescale option of 1 1 1 4 or 1 16 selected by control bits T2CKPS1 T2CKPS0 T2CON lt 1 0 gt The Timer2 module has an 8 bit period register PR2 Timer2 increments from 00h until it matches PR2 and then resets to O0h on the next increment cycle PR
134. 150 Open Drain High Voltage VOD 14 V RAA pin Capacitive Loading Specs on Out put Pins D100 OSC2 pin Cosc2 15 pF in XT HS and LP modes when external clock is used to drive OSC1 D101 All UO pins and OSC2 in RC mode Cio 50 pF D102 SCL SDA in PC mode CB 400 pF These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR VPP pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input volt ages 3 Negative current is defined as current sourced by the pin 1997 Microchip Technology Inc DS30390E page 171 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17 4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 TCC ST IC specifications only 2 TppS 4 Ts I C specifications only T E Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di S
135. 1Dh Unimplemented a E 1Eh ADRES A D Result Register XXXX xxxx uuuu uuuu 1Fh ADCONO ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON 0000 00 0 0000 00 0 Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Shaded locations are unimplemented read as 0 Note 1 These registers can be addressed from either bank 2 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose contents are transferred to the upper byte of the program counter 3 Other non power up resets include external reset through MCLR and Watchdog Timer Reset 4 The IRP and RP1 bits are reserved on the PIC16C72 always maintain these bits clear 1997 Microchip Technology Inc DS30390E page 23 PIC16C7X TABLE 4 1 PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY Cont di Value on Value on all Address Name Bit7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 3 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 81h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 82h PCL Program Counter s PC Lea
136. 2 is a readable and writable register The PR2 register is ini tialized to FFh upon reset The match output of TMR2 goes through a 4 bit postscaler which gives a 1 1 to 1 16 scaling inclusive to generate a TMR2 interrupt latched in flag bit TMR2IF PIR1 lt 1 gt Timer2 can be shut off by clearing control bit TMR2ON T2CON 2 to minimize power consumption Figure 9 2 shows the Timer2 control register 9 1 Timer2 Prescaler and Postscaler Applicable Devices 72 73 73A 74 74A 76 77 The prescaler and postscaler counters are cleared when any of the following occurs awrite to the TMR2 register awrite to the T2CON register any device reset Power on Reset MCLR reset Watchdog Timer reset or Brown out Reset TMR2 is not cleared when T2CON is written 9 2 Output of TMR2 Applicable Devices 72 73 73A 74 74A 76 77 The output of TMR2 before the postscaler is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock FIGURE 9 1 TIMER2 BLOCK DIAGRAM Sets flag TMR2 bit TMR2IF output 1 Reset Prescaler TMR2 reg 1 1 1 4 1 16 V Comparator mu PR2 reg Postscaler 1 1 to 1 16 Note 1 TMR2 register output can be software selected by the SSP Module as a baud clock 1997 Microchip Technology Inc DS30390E page 69 PIC16C7X FIGURE 9 2 T2CON TIMER2 CONTROL REGISTER ADDRESS 12h U 0 R W
137. 20 9 12C BUS START STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No 90 TSU STA START condition 100 kHz mode 4700 ep Only relevant for repeated START Setup time 400 KHz mode 600 condition 91 THD STA START condition 100 kHz mode 4000 m After this period the first clock Hold time 400 kHz mode 600 pulse is generated 92 Tsu sTO STOP condition 100 kHz mode 4700 ER Setup time 400 kHz mode 600 93 THD STO STOP condition 100 kHz mode 4000 h Hold time 400 kHz mode 600 1997 Microchip Technology Inc DS30390E page 235 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 o MEE Out i Note Refer to Figure 20 1 for load conditions FIGURE 20 14 CC BUS DATA TIMING 103 TABLE 20 10 12C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No 100 THIGH Clock high time 100 kHz mode 4 0 ZI us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 0 6 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 101 TLow Clock low time 100 kHz mode 4 7 us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 1 3 us Device must operate at a m
138. 22 22 22 UO TTL RB2 23 23 23 UO TTL RB3 24 24 24 UO TTL RB4 25 25 25 UO TTL Interrupt on change pin RB5 26 26 26 UO TTL Interrupt on change pin RB6 27 27 27 VO TTL ST Interrupt on change pin Serial programming clock RB7 28 28 28 UO TTL sT Interrupt on change pin Serial programming data PORTE is a bi directional I O port RCO T1OSO T1CKI 11 11 11 UO ST RCO can also be the Timer1 oscillator output or Timer1 clock input RC1 T1OSI 12 12 12 yo ST RC1 can also be the Timer1 oscillator input RC2 CCP1 13 13 13 yo ST RC2 can also be the Capture1 input Compare1 output PWM output RC3 SCK SCL 14 14 14 UO ST RC3 can also be the synchronous serial clock input output for both SPI and DC modes RC4 SDI SDA 15 15 15 yo ST RC4 can also be the SPI Data In SPI mode or data HO IC mode RC5 SDO 16 16 16 UO ST RC5 can also be the SPI Data Out SPI mode RC6 17 17 17 UO ST RC7 18 18 18 UO ST Vss 8 19 8 19 8 19 P Ground reference for logic and I O pins VDD 20 20 20 P Positive supply for logic and I O pins Legend input O output I O input output P power Not used TTL TTL input ST Schmitt Trigger input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode 3 This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise 1997 Microchip Technology Inc DS30390E pa
139. 25 27 29 71 CCPR1L Register CCPR2H Register A 25 27 29 71 CCPR2L Register neee 25 27 29 71 CCPxMO bit CCPxM1 bit CCPxM2 bit CCPxM3 bit iss COPXX Diss o c eet Lees bc nd Eos EEN Te EE e gl TEE CKE oaaisennnn CKP Clock Polarity Select bit CKP esuesssss Clock Polarity SPI Mode 81 Clocking Scheme AAA 17 Code Examples Call of a Subroutine in Page 1 from Page O 41 Changing Between Capture Prescalers aud Changing Prescaler TimerO to WDT 63 Changing Prescaler WDT to TimerO UO Programming Indirect Addressing Initializing PORTA Initializing PORTB Initializing PORTC Loading the SSPBUF Register 80 85 Code Protection ssion eri iinan iinan Computed GOTO Configuration Bits 2 nri ei Hee eed 129 Configuration Word seen 129 Connecting Two Microcontrollers GREN Dit ne teen P D RO Ee Un eer est 100 en EE 54 D DIA Se oue nr A ned creek 78 83 Data Address bit D A Be 20 DC Characteristics PIG16Q72 3 siint eO OE EO ROS 168 PRICES eerte eripiet PO nd 184 PIGIOC73A n i cen enden S 202 PIC16C74 PIG16G74A cte eee eet n 202 PIC16C76 PIC16C77 Development Support eee 5 163 Development Tools ss 163 Digit Carry bit Direct Addressing seene 41 E Electrical Characteristics PIG16Q72 5e A eR 167 PIC16C73
140. 2C508 PIC12C509 PIC12C671 PIC12C672 Maximum Frequency 4 4 4 4 of Operation MHz M EPROM Program Memory 512x 12 1024 x 12 1024 x 14 2048 x 14 emor y Data Memory bytes 25 41 128 128 Timer Module s TMRO TMRO TMRO TMRO Peripherals A D Converter 8 bit Channels 4 4 Wake up from SLEEP on Yes Yes Yes Yes pin change UO Pins 5 5 5 5 Input Pins Internal Pull ups Voltage Range Volts 2 5 5 5 2 5 5 5 2 5 5 5 2 5 5 5 In Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 35 35 Packages 8 pin DIP SOIC 8 pin DIP SOIC 8 pin DIP SOIC 8 pin DIP SOIC All PIC12C5XX devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capability All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GPO E 2 PIC14C000 Family of Devices PIC14C000 Clock Maximum Frequency of Operation MHz 20 EPROM Program Memory x14 words 4K Memory Data Memory bytes 192 Timer Module s TMRO ADTMR HERE Serial Ports I C with SMBus P SPI I2C USART Support Slope A D Converter Channels 8 External 6 Internal Interrupt Sources 11 UO Pins 22 Voltage Range Volts 2 7 6 0 In Circuit Serial Programming Yes Additional On chip Features Internal 4MHz Oscillator Bandgap Reference Temperature Sensor Calibration Factors Low Voltage Detector SLEEP HIBERNATE Comparators with Programmable Referen
141. 3 73A 74 74A 76 77 000 0000 000 0000 uuu uuuu 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu PIE2 72 73 73A 74 74A 76 77 D J Qv I uem u PCON 72 73 73A 74 74A 76 77 0 u ECCO PUE 72 73 73A 74 TAA 76 77 Ou uu uu PR2 72 73 73A 74 74A 76 77 1111 1111 1111 1111 1111 1111 Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Note 1 One or more bits in INTCON PIR1 and or PIR2 will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h 3 See Table 14 7 for reset value for specific condition 1997 Microchip Technology Inc DS30390E page 137 PIC16C7X TABLE 14 8 INITIALIZATION CONDITIONS FOR ALL REGISTERS Cont d Register Applicable Devices Power on Reset MCLR Resets Wake up via WDT Brown out Reset WDT Reset or Interrupt SSPADD 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu SSPSTAT 72 73 73A 74 74A 76 77 00 0000 00 0000 uu uuuu TXSTA 72 73 73A 74 74A 76 77 0000 010 0000 010 uuuu uuu SPBRG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu ADCON1 72 73 73A 74 74A 76 77 000 000 uuu Legend u unchanged x unknown
142. 3 Tpwrt Power up Timer Period 28 72 132 ms VDD 5V 40 C to 85 C 34 Tioz 1 O Hi impedance from MCLR Low 100 ns or Watchdog Timer Reset These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 191 PIC16C7X Applicable Devices 72 73 73A 74 74A v6 77 FIGURE 18 5 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS RA4 TOCKI A TMRO or TMR1 Note Refer to Figure 18 1 for load conditions TABLE 18 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns Parameter 42 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns parameter 42 42 TtOP TOCKI Period No Prescaler Tcy 40 ns With Prescaler Greater of ns N prescale value 20 or Tcv 40 2 4 256 N 45 TtH T1CKI High Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ns 2 4 8 As
143. 3 10 PIC16C73 20 PIC16LC73 04 i ES PIC16C74 04 PIC16C74 10 PIC16C74 20 PIC16LC74 04 weeks VDD 4 0V to 6 0V Vop 4 5V to 5 5V VDD 4 5V to 5 5V VDD 3 0V to 6 0V VDD 4 0V to 6 0V RC IDD 5 mA max at 5 5V IDD 2 7 mAtyp at5 5V IDD 2 7 mA typ at 5 5V IDD 3 8 mA max at 3 0V IDD 5 mA max at 5 5V IPD 21 uA max at AN IPD 1 5 pA typ at AN IPD 1 5 uA typ at AN IPD 13 5 uA max at 3V IPD 21 WA max at AN Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max VDD 4 0V to 6 0V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 3 0V to 6 0V VDD 4 0V to 6 0V XT IDD 5 mA max at 5 5V IDD 2 7 mA typ at 5 5V IDD 2 7 mA typ at 5 5V IDD 3 8 mA max at3 0V IDD 5 mA max at 5 5V IPD 21 pA max at AN IPD 1 5 uA typ at AN IPD 1 5 uA typ at AN IPD 13 5 uA max at 3V IPD 21 WA max at AN Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V HS IDD 13 5 mAtyp at5 5V op 15 mA max at5 5V IDD 30 mA max at 5 5V Not recommended for IDD 30 mA max at 5 5V IPD 1 5pAtyp at4 5V lp 1 5pgAtyp at4 5V IPD 1 5 pA typ at 4 5V use in HS mode IPD 1 5 pA typ at 4 5V Freq 4 MHz max Freq 10 MHz max Freq 20 MHz max Freq 20 MHz max VDD 4 0V to 6 0V VDD 3 0V to 6 0V VDD 3 0V to 6 0V IDD 52 5 uA typ at Natracommeancedhon Nawrecommeandedion IDD 48 LA max at IDD 48 uA max at LP 32 kHz 4 0V use in UP mode usa in
144. 30390E page 121 PIC16C7X 13 4 A D Conversions Applicable Devices 72 73 73A 74 74A 76 77 Example 13 2 shows how to perform an A D conver sion The RA pins are configured as analog inputs The analog reference VREF is the device VDD The A D interrupt is enabled and the A D conversion clock is FRc The conversion is performed on the RAO pin channel 0 EXAMPLE 13 2 A D CONVERSIO Note The GO DONE bit should NOT be set in the same instruction that turns on the A D Clearing the GO DONE bit during a conversion will abort the current conversion The ADRES register will NOT be updated with the partially completed A D con version sample That is the ADRES register will con tinue to contain the value of the last completed conversion or the last value written to the ADRES reg ister After the A D conversion is aborted a 2TAD wait is required before the next acquisition is started After this 2TAD wait an acquisition is automatically started on the selected channel BSF STATUS RPO Select Bank 1 BCF STATUS RP1 PIC16C76 77 only CLRF ADCON1 Configure A D inputs BSF PIEL ADIE Enable A D interrupts BCF STATUS RPO Select Bank 0 MOVLW 0xC1 RC Clock A D is on Channel 0 is selected MOVWF ADCONO BCF PIRI ADIF Clear A D interrupt flag bit BSF INTCON PEIE Enable peripheral interrupts BSF INTCON GIE Enable all interrupts Ensure that the required sampling time for
145. 4 EDL Differential linearity error Ee t1 LSb VREF VDD 5 12V VSS VAIN VREF A05 Ers Full scale error m lt 1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF Offset error Se lt 1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF Monotonicity guaranteed VSs lt VAIN lt VREF A20 VREF Reference voltage 3 0V VDD 0 3 V A25 VAIN Analog input voltage Vss 0 3 mE VREF 0 3 V A30 ZAIN Recommended impedance of 10 0 kQ analog voltage source A40 IAD A D conversion current VDD PIC16C72 180 uA Average current consump PIC16LC72 pue 90 deg uA tion when A D is on Note 1 A50 IREF VREF input current Note 2 10 1000 uA During VAIN acquisition Based on differential of VHOLD to VAIN to charge CHOLD see Section 13 1 x E 10 uA During A D Conversion cycle These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested When A D is off it will not consume any current other than minor leakage current The power down current spec includes any such leakage from the A D module 2 VREF current is from RAS pin or VDD pin whichever is selected as reference input 1997 Microchip Technology Inc DS30390E page 181 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 11 A D CONVERSION TIMING
146. 4A 25 45 ns 54 TecF CCP1 and CCP2 output fall time PIC16C73A 74A 10 25 ns PIC16LC73A 74A 25 45 ns These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 211 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 8 PARALLEL SLAVE PORT TIMING PIC16C74A RE2 CS RE1 WR RD7 RDO Note Refer to Figure 19 1 for load conditions TABLE 19 7 PARALLEL SLAVE PORT REQUIREMENTS PIC16C74A Parameter Sym Characteristic i Conditions No 62 TdtV2wrH Data in valid before WRT or CST setup time Extended Range Only TwrH2dtl WRT or CST to data in invalid hold time PIC16C74A PIC16LC74A 35 ns 64 TrdL2dtV RD and CS to data out valid 80 ns 90 ns Extended Range Only 65 TrdH2dtl RDT or CS to data out invalid 10 30 ns These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 212 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 9 S
147. 6 64 76 92 0 16 51 75 76 1 36 32 77 82 1 32 22 96 96 15 0 16 51 95 24 0 79 41 96 15 0 16 25 94 20 1 88 18 300 294 1 1 96 16 307 69 2 56 12 312 5 4 17 7 298 3 0 57 5 500 500 0 9 500 0 7 500 0 4 NA HIGH 5000 0 4000 0 2500 0 1789 8 0 LOW 19 53 255 15 625 255 9 766 255 6 991 255 FOSC 5 0688 MHz 4 MHz 3 579545 MHz 1 MHz 32 768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE KBAUD 96 value KBAUD K value KBAUD K value KBAUD 96 value BAUD K value K ERROR decimal ERROR decimal ERROR decimal ERROR decimal ERROR decimal 0 3 NA NA NA NA 0 303 41 14 26 1 2 NA NA NA 1 202 40 16 207 1 170 2 48 6 24 NA NA NA 2 400 40 16 103 NA 9 6 9 6 0 131 9 615 40 16 103 9 622 0 23 92 9 615 40 16 25 NA 19 2 19 2 0 65 19 231 40 16 51 19 04 0 83 46 19 24 0 16 12 NA 76 8 79 2 3 13 15 76 923 0 16 12 74 57 2 90 11 83 34 48 51 2 NA 96 97 48 41 54 12 1000 4 17 9 99 43 43 57 8 NA NA 300 316 8 45 60 3 NA 298 3 0 57 2 NA NA 500 NA NA NA NA NA HIGH 1267 0 100 0 894 9 0 250 0 8 192 0 LOW 4 950 255 3 906 255 3 496 255 0 9766 255 0 032 255 TABLE 12 4 BAUD RATES FOR ASYNCHRONOUS MODE BRGH 0 BAUD FOSC 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG 7 15909 MHz SPBRG RATE 96 value 96 value 96 value 96 value K KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal KBAUD ERROR decimal 0 3 NA
148. 7 04 PIC16C77 10 PIC16C77 20 PIC16LC77 04 Voo 4 0V to 6 0V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VpD 4 0V to 6 0V IDD 5 mA max IDD 2 7 mA typ IDD 2 7 mA typ We SS SE IDD 5 mA max at 5 5V at 5 5V at 5 5V at 3 0V at 5 5V IPD 16 LA max IPD 1 5 uA typ IPD 1 5 uA typ IPD 5 WA max at 3V IPD 16 LA max at 4V at 4V at 4V Freq 4 MHz max at 4V Freq 4 MHz max Freq 4 MHz max Freq 4 MHZ max Freq 4 MHz max 4 0V to 6 0V VDD 4 5V to 5 5V VDD 4 5V to 5 5V 2 5V to 6 0V VDD 4 0V to 6 0V 5 mA max IDD 2 7 mA typ IDD 2 7 mA typ 38 mA max IDD 5 mA max at 5 5V at 5 5V at 5 5V St 3 0V at 5 5V 16 uA max IPD 1 5 uA typ IPD 1 5 uA typ 5 A mac at ey IPD 16 LA max at 4V at 4V at 4V ree at 4V 4 MHz max Freq 4 MHz max Freq 4 MHz max i Freq 4 MHz max 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V 13 5 mA typ IDD 10 mA max IDD 20 mA max IDD 20 mA max at 5 5V at 5 5V at 5 5V Not recommended for at 5 5V 1 5 uA typ IPD 1 5 LA typ IPD 1 5 pA typ use in HS mode IPD 1 5 pA typ at 4 5V at 4 5V at 4 5V at 4 5V 4 MHz max Freq 10 MHz max Freq 20 MHz max Freq 20 MHz max 4 0V to 6 0V VDD 2 5V to 6 0V Voo 2 5V to 6 0V 52 5 uA typ IDD 48 uA max IDD 48 uA max at 32 kHz 4 0V Not recommended for Not recommended for at 32 kHz 3 0V at 32 kHz 3 0V 0 9 uA typ use in LP mode use in LP mode IPD 5 0 uA max IPD 5 0 uA max at 4 0V at 3 0V at 3 0V 200 kHz max Freq 200 kHz m
149. 74 74A 76 77 000 0000 000 0000 uuu uuuu SSPBUF 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu SSPCON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu CCPR1L 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu CCPR1H 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu CCP1CON 72 73 73A 74 74A 76 77 00 0000 00 0000 uu uuuu RCSTA 72 73 73A 74 74A 76 77 0000 00x 0000 00x uuuu uuu TXREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu RCREG 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu CCPR2L 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu CCPR2H 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu CCP2CON 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu ADRES 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu ADCONO 72 73 73A 74 74A 76 77 0000 00 0 0000 00 0 uuuu uu u OPTION 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISA 72 73 73A 74 74A 76 77 11 1111 11 1111 uu uuuu TRISB 72 73 73A 74 74A 76 77 ITIL CC 1111 1111 uuuu uuuu TRISC 72 73 73A 74 74A 76 77 1111 1111 LETT Tiii uuuu uuuu TRISD 72 73 73A 74 74A 76 77 1111 1111 1111 1111 uuuu uuuu TRISE 72 73 73A 74 74A 76 77 0000 111 0000 111 uuuu uuu 72 73 73A 74 74A 76 77 0 0000 0 0000 u uuuu PIE1 72 7
150. 9 6 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS RA4 TOCKI A TMRO or TMR1 Note Refer to Figure 19 1 for load conditions TABLE 19 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 Ed ns parameter 42 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns parameter 42 42 TtOP TOCKI Period No Prescaler Tcy 40 ns With Prescaler Greater of ns N prescale value 20 or Tcv 40 2 4 256 N 45 TtH T1CKI High Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 46 TOL T1CKI Low Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 E ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 47 TtiP T1CKI input period Synchronous PIC16C7X Greater of ns N prescale value 30 op Tcv 40 1 2 4 8 N PIC16LC7X Greater of N prescale value 50 op Tcv 40 1 2 4 8 N Asynchronous PIC16C7X 60
151. 923 and PIC16C924 in the PLCC package It will also support future 44 pin PLCC microcontrollers with a LCD Module All the neces sary hardware and software is included to run the basic demonstration programs The user can pro gram the sample microcontrollers provided with the PICDEM 3 board on a PRO MATE II program mer or PICSTART Plus with an adapter socket and easily test firmware The PICMASTER emulator may also be used with the PICDEM 3 board to test firm ware Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket s Some of the features include an RS 232 interface push button switches a potenti ometer for simulated analog input a thermistor and separate headers for connection to an external LCD module and a keypad Also provided on the PICDEM 3 board is an LCD panel with 4 commons and 12 seg ments that is capable of displaying time temperature and day of the week The PICDEM 3 provides an addi tional RS 232 interface and Windows 3 1 software for showing the demultiplexed LCD signals on a PC A sim ple serial interface allows the user to construct a hard ware demultiplexer for the LCD signals 16 9 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8 bit microcon troller market MPLAB is a windows based application which contains Afull featured editor
152. 9A seco nro DEI a eus PIC16G74 WEE PIC16C74A PIC16C 76 E DECHE AIR M nm en mme MPASM Assembler S MPLAB C EE MPSIM Software Simulator 163 165 O OERR bIt 5 5 yn eese YO ER CREE OPCODE OPTION ne Ee ete oa dee ERR ce tnt sente tend OPTION Register serment 31 Orthogonal OSG selection Etienne et 129 Oscillator were D RCE AT TO AE e p nie oise mage Oscillator Configurations Output of TMR2 eec tenete gea tene e P PE PEE 78 83 Packaging 28 Lead Ceramic w Window 251 28 Lead PDIP 28 Lead SOIC 3 28 Lead SSOP siemens 256 40 Lead CERDIP w Window sesesss 252 40 Lead PDIP 254 44 Lead MQFP 258 44 Lead PLCC 257 44 Lead TQFP 259 Paging Program Memory eene 40 Parallel Slave Port 50 54 POFGO DIE einem rere aree teo mi anis 118 PCFG1 bit 118 PGEG2 Itineraires 118 PCL Register 23 24 25 26 27 28 29 40 POLATH eR EE 136 PCLATH Register 28 24 25 26 27 28 29 40 PECON Register steve tee retento eee estes 29 39 135 PD BIE 2 3 redeo eee mie 30 133 135 PICDEM 1 Low Cost PIC16 17 Demo Board 163 164 PICDEM 2 Low Cost PIC16CXX Demo Board 163 164 PICDEM 3 Low Cost PIC16C9XXX Demo Board 164 PICMASTER In Circuit Emulator ccccccccsccceesseeeeeseees 163 1997 Mi
153. A pins Slave Mode START oaaae STOP eee Transfer Acknowledge Transmission IDLE MODE het In Circuit Serial Programming m UNE e dec its le De es INDF Register Indirect Addressing esseeeeeee 41 Initialization Condition for all Register 136 Instruction Cycle Instruction Flow Pipelining G Instruction Format ssseeenenee 147 DS30390E page 274 1997 Microchip Technology Inc PIC16C7X Instruction Set ADDEW tnter e EB e E e RE E E Pad 149 CLRWDT COMF DECF DECFSZ GOTO IORLW e E OPTION RETFIE Summary Table EE 148 INT Interrupt ie INTOON RTL INTCON Register ssseeeeeeeeneee 32 INTEDG DN 143 Internal Sampling Switch Rss Impedance 120 Ju uer 129 PortB Change 148 RB7 RB4 Port Change seen 45 Section nes 141 TMRO 143 IFE ARE danse er EE eege 20 L Loading of EE 40 M MGER EE 133 136 Memory Data Memory serres 20 Program Memory sessseeeeeeeeeneeenenennen 19 Program Memory Maps ele 19 PICI6C7S nre tete oto be n ee 19 PIG10G79A i mem ene 19 PIC16C74 leet EE 19 PIGT6C 76 EE 20 PIC16G77 EE 20 Register File Maps BIG10672 dn Or GER ENG 21 PIC16C73 PICGTOC 7
154. AND STACK 4 1 Program Memory Organization PC lt 12 0 gt The PIC16C7X family has a 13 bit program counter GE AA 13 capable of addressing an 8K x 14 program memory Ge space The amount of program memory available to each device is listed below Stack Level 1 Device Mk Address Range Y Stack Level 8 PIC16C72 2K x 14 0000h 07FFh PIC16C73 4K x 14 0000h 0FFFh Reset Vector PIC16C73A 4K x 14 0000h 0FFFh PIC16C74 4K x 14 0000h 0FFFh PIC16C74A 4K x 14 0000h 0FFFh B Interrupt Vector PIC16C76 8K x 14 0000h 1FFFh S 5 m O n chip Program PIC16C77 8K x 14 0000h 1FFFh 2 S Memory Page 0 5 OI e 2 chip P address will cause a wraparound Menon Page 1 The reset vector is at 0000h and the interrupt vector is at 0004h FIGURE 4 1 PIC16C72 PROGRAM MEMORY MAP AND STACK PC lt 12 0 gt CALL RETURN RETFIE RETLW iS Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector User Memory Space On chip Program Memory 1997 Microchip Technology Inc DS30390E page 19 PIC16C7X FIGURE 4 3 PIC16C76 77 PROGRAM MEMORY MAP AND STACK CALL RETURN RETFIE RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector H e e Interrupt Vector On Chip Page 0 On Chip Page 1 User Memory Space On Chip Page 2 On Chip Page 4 2 Data Memory Organization Applic
155. C SOIC SOIC SOIC SOIC SSOP SOIC SSOP 20 pin SSOP 20 pin SSOP 20 pin SSOP Clock Maximum Frequency of Oper 20 20 20 20 ation MHz EPROM Program Memory 4K 4K 8K 8K x14 words Data Memory bytes 192 192 368 368 Timer Module s TMRO TMRO TMRO TMRO TMR1 TMR1 TMR1 TMR1 TMR2 TMR2 TMR2 TMR2 Capture Compare PWM Mod 2 2 2 2 Peripherals ule s Serial Port s SPI I C US ART Parallel Slave Port Yes Gm Yes A D Converter 8 bit Channels 5 8 5 8 Interrupt Sources 11 12 11 12 UO Pins 22 33 22 33 Voltage Range Volts 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 In Circuit Serial Programming Yes Yes Yes Yes Brown out Reset Yes Yes Yes Yes Packages 28 pin SDIP 40 pin DIP 28 pin SDIP 40 pin DIP SOIC 44 pin PLCC SOIC 44 pin PLCC MQFP TQFP MQFP TQFP All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capabil ity All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7 Note 1 Please contact your local Microchip sales office for availability of these devices 1997 Microchip Technology Inc DS30390E page 6 PIC16C7X 2 0 PIC16C7X DEVICE VARIETIES A variety of frequency ranges and packaging options are available Depending on application and production requirements the proper device option can be selected using the information in the PIC16C7X Product Iden
156. C SPEN and CSRC 3 f interrupts are desired then set enable bit TXIE 4 If 9 bit transmission is desired then set bit TX9 5 Enable the transmission by setting bit TXEN 6 f 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Start transmission by loading data to the TXREG register DS30390E page 110 1997 Microchip Technology Inc PIC16C7X TABLE 12 8 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION MALU On Value on all Address Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit 2 Bit 1 Bit 0 POR other Resets BOR OCh PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Master Transmission Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear FIGURE 12 12 SYNCHRONOUS TRANSMISSION arfoe agfasia aa as a4ta1 acfas asar azlasjastar a2 asfad ob okdocbdobdocbdob paasa o4a ozpa Get
157. C TO 85 C 200 400 800 1000 1200 1400 1600 1800 Shaded area is Frequency kHz beyond recommended range 1997 Microchip Technology Inc DS30390E page 245 Data based on matrix samples See first page of this section for details Data based on matrix samples See first page of this section for details PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 16 TYPICAL IDD vs FREQUENCY RC MODE 300 pF 25 C 300 400 Frequency kHz FIGURE 21 17 MAXIMUM IDD vs FREQUENCY RC MODE 300 pF 40 C TO 85 C 300 400 Frequency kHz DS30390E page 246 1997 Microchip Technology Inc FIGURE 21 18 TYPICAL IDD vs CAPACITANCE 500 kHz RC MODE 100 pF Capacitance pF TABLE 21 1 RC OSCILLATOR FREQUENCIES Average Cext Rext Fosc 9 5V 25 C 22 pF 5k 4 12 MHz 1 4 10k 2 35 MHz t 1 4 100k 268 kHz 1 1 100 pF 3 3k 1 80 MHz 1 0 5k 1 27 MHz 1 0 10k 688 kHz 1 2 100k 77 2 kHz 1 0 300 pF 3 3k 707 kHz 1 496 5k 501 kHz 1 2 10k 269 kHz t 1 6 100k 28 3 kHz t 1 196 The percentage variation indicated here is part to part variation du
158. CIRCUIT To Other 330 kQ 330 kQ Devices NW 74AS04 74AS04 PIC16CXX AW 74AS04 0 1 uF D XTAL CLKIN 14 2 4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings The RC oscillator frequency is a function of the supply voltage the resis tor Rext and capacitor Cext values and the operat ing temperature In addition to this the oscillator frequency will vary from unit to unit due to normal pro cess parameter variation Furthermore the difference in lead frame capacitance between package types will also affect the oscillation frequency especially for low Cext values The user also needs to take into account variation due to tolerance of external R and C compo nents used Figure 14 7 shows how the R C combina tion is connected to the PIC16CXX For Rext values below 2 2 kQ the oscillator operation may become unstable or stop completely For very high Rext values e g 1 MQ the oscillator becomes sensitive to noise humidity and leakage Thus we recommend to keep Rext between 3 kQ and 100 kQ Although the oscillator will operate with no external capacitor Cext 0 pF we recommend using values above 20 pF for noise and stability reasons With no or small external capacitance the oscillation frequency can vary dramatically due to changes in external capacitances such as PCB trace capacitance or pack age lead frame capacita
159. CL PCL PCL 182h STATUS STATUS STATUS STATUS 183h FSR FSR FSR FSR 184h PORTA TRISA 185h PORTB TRISB PORTB TRISB 186h PORTC TRISC 187h PORTD TRISD 188h PORTE OI TRISE ee 15h PCLATH PCLATH PCLATH PCLATH 18Ah INTCON INTCON INTCON INTCON 18Bh PIR1 PIE1 18Ch PIR2 PIE2 18Dh TMR1L PCON 18bh TMR1H 18Fh T1CON 190h TMR2 191h T2CON PR2 192h SSPBUF SSPADD 193h SSPCON SSPSTAT 194h CCPRIL 195h CCPR1H 196h CCP1CON General General 197h Purpose Purpose RCSTA Register Register 198h TXREG 16 Bytes 16 Bytes 199h RCREG 19Ah CCPR2L 19Bh CCPR2H 19Ch CCP2CON 19Dh ADRES 19Eh ADCONO ADCON1 19Fh 1A0h General General General General Purpose Purpose Purpose Purpose Register Register Register Register 96 Bytes 80 Bytes ER 80 Bytes 80 Bytes accesses FOh accesses accesses 70h 7Fh 70h 7Fh 70h 7Fh 7Fh FFh Bank 0 Bank 1 Bank 2 Bank 3 D unimptementea data memory locations read as 0 Not a physical register Note 1 PORTD PORTE TRISD and TRISE are unimplemented on the PIC16C76 read as O Note The upper 16 bytes of data memory in banks 1 2 and 3 are mapped in Bank 0 This may require relocation of data memory usage in the user application
160. CNT 1 Before Instruction CNT OxFF Z H After Instruction DS30390E page 154 1997 Microchip Technology Inc PIC16C7X INCFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity If Skip Example Increment f Skip if 0 label INCFSZ fd O lt f lt 127 de 0 1 f 1 destination skip if result 0 None 00 1111 dfff ffff The contents of register f are incre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f If the result is 1 the next instruction is executed If the result is 0 a NOP is executed instead making it a 2TCY instruction 1 1 2 Q1 Q2 Q3 Q4 Decode Read Process Write to register f data destination 2nd Cycle Q1 Q2 Q3 Q4 No No No No Operation Operation Operation Operation HERE INCFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction CNT CNT 1 if CNT 0 PC address CONTINUE if CNT 0 PC address HERE 41 IORLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Inclusive OR Literal with W abel IORLW k 0 lt k lt 255 W OR k gt W Z 11 1000 kkkk kkkk The contents of the W register is OR ed with the eight bit literal k The
161. D HS MODE 25 C 20 MHz 33 pF 33 pF 8 MHz 33 pF 33 pF Startup Time ms 20 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 4 5 5 0 Vpb Volts FIGURE 21 24 TYPICAL XTAL STARTUP TIME vs VDD XT MODE 25 C NI eo o eo a CH B kHz 68 pF 68 pF CO CH n e 200 kHz 47 pF 47 pF Startup Time ms 1 MHz 15 pF 15 pF t TABLE 21 2 4 MHz 15 pF 15 pF CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS Osc Type SE SE be LP 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 200 kHz 47 68 pF 47 68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF HS 4 MHz 15 pF 15 pF 8 MHz 15 33 pF 15 33 pF 20 MHz 15 33 pF 15 33 pF Crystals Used 32 kHz Epson C 001R32 768K A 20 PPM 200 kHz STD XTL 200 000KHz 20 PPM 1 MHz ECS ECS 10 13 1 50 PPM 4 MHz ECS ECS 40 20 1 50 PPM 8 MHz EPSON CA 301 8 000M C 30 PPM 20 MHz EPSON CA 301 20 000M C 30 PPM 1997 Microchip Technology Inc DS30390E page 248 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 25 TYPICAL IDD vs FREQUENCY FIGURE 21 27 TYPICAL IDD vs FREQUENCY LP MODE 25 C XT MODE 25 C 100
162. D Pin at hi imped ance D061 MCLR RA4 TOCKI uA Vss lt VPIN lt VDD D063 OSC1 5 uA Vss VPIN VDD XT HS and LP osc configuration Output Low Voltage D080 O ports VOL 0 6 V jloL 8 5 mA VDD 4 5V 40 C to 85 C D083 OSC2 CLKOUT RC osc config 0 6 V loL 1 6 mA VDD 4 5V 40 C to 85 C Output High Voltage D090 O ports Note 3 VoH VDD 0 7 V Jones 3 0 mA VDD 4 5V 40 C to 85 C D092 OSC2 CLKOUT RC osc config VDD 0 7 V lOH 1 3 mA VDD 4 5V 40 C to 85 C D150 Open Drain High Voltage VoD S 14 V RAA pin These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin DS30390E page 186 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions unless otherwise stated Operating temperature 40C l
163. D101 Al I O pins and OSC2 in RC Clo 50 pF D102 model SCL SDA in PC mode CB 400 pF These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 1997 Microchip Technology Inc DS30390E page 205 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19 4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 TCC ST IC specifications only 2 TppS 4 Ts I C specifications only T E Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 TOCKI io UO port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings S E Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi imp
164. DC bits from the STATUS register For other instructions not affecting any status bits see the Instruction Set Summary Note 1 For those devices that do not use bits IRP and RP1 STATUS lt 7 6 gt maintain these bits clear to ensure upward compatibility with future products Note 2 The C and DC bits operate as a borrow and digit borrow bit respectively in sub traction See the SUBLW and SUBWF instructions for examples FIGURE 4 7 STATUS REGISTER ADDRESS 03h 83h 103h 183h R W 0 R W 0 R W 0 R 1 R 1 R W x R W x R W x IRP RP1 RPO TO PD Z DC C R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 IRP Register Bank Select bit used for indirect addressing 1 Bank 2 3 100h 1FFh 0 Bank 0 1 00h FFh bit 6 5 11 Bank 3 180h 1FFh 10 Bank 2 100h 17Fh 01 Bank 1 80h FFh 00 Bank 0 00h 7Fh Each bank is 128 bytes RP1 RPO Register Bank Select bits used for direct addressing DC Digit carry borrow bit ADDWF ADDLW SUBLW SUBWF instructions for borrow the polarity is reversed bit 4 TO Time out bit 1 After power up CLRWDT instruction or SLEEP instruction 0 AWDT time out occurred bit 3 PD Power down bit 1 After power up or by the CLRWDT instruction 0 By execution of the SLEEP instruction bit 2 Z Zero bit 1 The result of an arithme
165. DD 4 5V to 5 5V VDD 2 5V to 6 0V VDD 4 0V to 6 0V RC IDD 5 mA max at 5 5V IDD 2 7 mAtyp at5 5V IDD 2 7 mAtyp at5 5V IDD 3 8 mA max at3 0V IDD 5 mA max at 5 5V IPD 16 uA max at 4V IPD 1 5 uA typ at 4V IPD 1 5 uA typ at AN IPD 5 uA max at 3V IPD 16 uA max at AN Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max VDD 4 0V to 6 0V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 2 5V to 6 0V VDD 4 0V to 6 0V XT IDD 5 mA max at 5 5V IDD 2 7 mA typ at5 5V IDD 2 7 mAtyp at5 5V IDD 3 8 mA max at3 0V IDD 5 mA max at 5 5V IPD 16 uA max at 4V IPD 1 5 uA typ at 4V IPD 1 5 uA typ at AN IPD 5 uA max at 3V IPD 16 uA max at 4V Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max Freq 4 MHz max VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V HS IDD 13 5 mA typ at 5 5V IDD 10 mA max at5 5V IDD 20 mA max at 5 5V Not recommended for IDD 20 mA max at 5 5V IPD 1 5 uA typ at 4 5V IPD 1 5uAtyp at4 5V IPD 1 5 LA typ at 4 5V use in HS mode IPD 1 5 pA typ at 4 5V Freq 4 MHz max Freq 10 MHz max Freq 20 MHz max Freq 20 MHz max Vop 4 0V to 6 0V VDD 2 5V to 6 0V VDD 2 5V to 6 0V LP pee e us Not recommended for Not recommended for P d po mas al IDB e pa ma at IPD 0 9 uA typ at 4 0V WEL mE veem LP moe IPD 5 0 uA max at3 0V IPD 5 0 uA max at 3 0V Freq 200 kHz max Freq 200 kHz max Freq 200 kHz max The shaded sections indicate oscillator s
166. DI sc SCK do SDO ss SS dt Data in t0 TOCKI io UO port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings S E Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance C only AA output access High High BUF Bus free Low Low Tcc sr IC specifications only HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 17 1 LOAD CONDITIONS Load condition 1 Load condition 2 VDD 2 o 4640 50 pF forall pins except OSC2 15pF for OSC2 output DS30390E page 172 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17 5 Timing Diagrams and Specifications FIGURE 17 2 EXTERNAL CLOCK TIMING CLKOUT TABLE 17 2 EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No Fosc External CLKIN Frequency DC E 4 MHz XT and RC osc mode Note 1 DC 4 MHz HS osc mode 04 DC 10 MHz HS osc mode 10 DC 20 MHz HS osc mode 20 DC 200 kHz LP osc mode Oscillator Frequency DC 4 MHz RC osc mode Note 1 0 1 4 MHz XT osc mode 4 20 MHz HS osc mode 5 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 ns XT and RC osc mode Note 1 250 ns HS osc mode 04 100 ns HS osc mode 10 50 ns HS
167. Default is d 1 label Label name TOS Top of Stack PC Program Counter PCLATH Program Counter High Latch GIE Global Interrupt Enable bit WDT Watchdog Timer Counter TO Time out bit PD Power down bit dest Destination either the W register or the specified register file location Options Contents Assigned to lt gt Register bit field In the set of italics User defined term font is courier The instruction set is highly orthogonal and is grouped into three basic categories Byte oriented operations Bit oriented operations Literal and control operations All instructions are executed within one single instruc tion cycle unless a conditional test is true or the pro gram counter is changed as a result of an instruction In this case the execution takes two instruction cycles with the second cycle executed as a NOP One instruc tion cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 us If a conditional test is true or the program counter is changed as a result of an instruc tion the instruction execution time is 2 us Table 15 2 lists the instructions recognized by the MPASM assembler Figure 15 1 shows the general formats that the instruc tions can have Note To maintain upward compatibility with future PIC16CXX products do not use
168. E and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear 2 The PIC16C72 does not have a Parallel Slave Port or a USART these bits are unimplemented read as 0 DS30390E page 70 1997 Microchip Technology Inc PIC16C7X 10 0 CAPTURE COMPARE PWM MODULE s Applicable Devices 72 73 73A 74 74A 76 77 CCP1 72 73 73A 74 74A 76 77 CCP2 Each CCP Capture Compare PWM module contains a 16 bit register which can operate as a 16 bit capture register as a 16 bit compare register or as a PWM master slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation with the exception of the operation of the special event trigger Table 10 1 and Table 10 2 show the resources and interactions of the CCP module s In the following sec tions the operation of a CCP module is described with CCP1 module Capture Compare PWM Register CCPR1 is com prised of two 8 bit registers CCPR1L low byte and CCPR1H high byte The CCP1CON register controls the operation of CCP1 All are readable and writable CCP2 module Capture Compare PWM Register2 CCPR2 is com prised of two 8 bit registers CCPR2L low byte and CCPR2H high byte The CCP2CON register controls the operation of CCP2 All are readable and writable For use of the CCP modules refer to the Embedded Control Handbook Using the CCP Modules AN594 TABLE 10 1 CCP MODE TIMER
169. E2 RE1 REO XXX uuu 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 111 0000 111 OCh PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 0000 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the Parallel Slave Port 1997 Microchip Technology Inc DS30390E page 55 PIC16C7X NOTES DS30390E page 56 1997 Microchip Technology Inc PIC16C7X 6 0 OVERVIEW OF TIMER MODULES Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C72 PIC16C73 73A PIC16C74 74A PIC16C76 77 each have three timer modules Each module can generate an interrupt to indicate that an event has occurred i e timer overflow Each of these modules is explained in full detail in the following sections The timer modules are e TimerO Module Section 7 0 Timer1 Module Section 8 0 Timer2 Module Section 9 0 6 1 TimerO Overview Applicable Devices The TimerO module is a simple 8 bit overflow counter The clock source can be either the internal system clock Fosc 4 or an external clock When the clock source is an external clock the TimerO module can be selected to increment on either the rising or falling edge The TimerO module also has a programmable pres caler
170. EMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 70 TssL2scH SS to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time slave mode Tcv 4 20 ns 72 TscL SCK input low time slave mode Tcv 4 20 EE ns 73 TdiV2scH Setup time of SDI data input to SCK 100 ns TdiV2scL edge 74 TscH2diL Hold time of SDI data input to SCK 100 ns TscL2diL edge 75 TdoR SDO data output rise time 10 25 ns 76 TdoF SDO data output fall time 10 25 ns 77 TssH2doZ SST to SDO output hi impedance 10 50 ns 78 Tech SCK output rise time master mode 10 25 ns 79 TscF SCK output fall time master mode 10 25 ns 80 TscH2doV SDO data output valid after SCK 50 ns TscL2doV edge 81 TdoV2scH SDO data output setup to SCK TCY ns TdoV2scL edge 82 TssL2doV SDO data output valid after SSL 50 ns edge 83 TscH2ssH SS T after SCK edge 1 5TCY 40 ns TscL2ssH These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 234 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 13 CC BUS START STOP BITS TIMING Condition Condition Note Refer to Figure 20 1 for load conditions TABLE
171. ES The PIC16CXX can be operated in four different oscil lator modes The user can program two configuration bits FOSC1 and FOSCO to select one of these four modes e LP Low Power Crystal e XT Crystal Resonator HS High Speed Crystal Resonator e RC Resistor Capacitor 14 2 2 CRYSTAL OSCILLATOR CERAMIC RESONATORS In XT LP or HS modes a crystal or ceramic resonator is connected to the OSC1 CLKIN and OSC2 CLKOUT pins to establish oscillation Figure 14 3 The PIC16CXX Oscillator design requires the use of a par allel cut crystal Use of a series cut crystal may give a frequency out of the crystal manufacturers specifica tions When in XT LP or HS modes the device can have an external clock source to drive the OSC1 CLKIN pin Figure 14 4 FIGURE 14 3 CRYSTAL CERAMIC RESONATOR OPERATION HS XT OR LP OSC CONFIGURATION To internal logic XTAL ist SLEEP PIC16CXX OSC2 RS Le Note See Table 14 1 and Table 14 2 for recommended values of C1 and C2 Note 1 A series resistor may be required for AT strip cut crystals FIGURE 14 4 EXTERNAL CLOCK INPUT OPERATION HS XT OR LP OSC CONFIGURATION Clock from OSC1 ext system PIC16CXX Open OSC2 TABLE 14 1 CERAMIC RESONATORS Ranges Tested Mode Freq OSC1 OSC2 XT 455 kHz 68 100pF 68 100 pF 2 0 MHz 15 68 pF 15 68 pF 4 0 MHz 15 68 pF 15 68 pF HS 8 0 MHz 10 68 pF 10 68 pF 16 0 MHz 10 22
172. Hz 4 0V fin ILI mece I LIP nets 32 kHz 3 0V 32 kHz 3 0V PD 0 9 uA typ at 4 0V IPD 5 0 uA max at3 0V IPD 5 0 uA max at 3 0V Freq 200 kHz max Freq 200 kHz max Freq 200 kHz max The shaded sections indicate oscillator selections which are tested for functionality but not for MIN MAX specifications It is recommended that the user select the device type that ensures the specifications required 1997 Microchip Technology Inc DS30390E page 167 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17 1 DC Characteristics PIC16C72 04 Commercial Industrial Extended PIC16C72 10 Commercial Industrial Extended PIC16C72 20 Commercial Industrial Extended DC CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended 40C lt Ta lt 85 C for industrial and 0 C TA lt 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 4 0 6 0 V XT RC and LP osc configuration D001A 4 5 5 5 V HS osc configuration D002 RAM Data Retention VDR 1 5 V Voltage Note 1 D003 VDD start voltage to VPOR Vss V See section on Power on Reset for details ensure internal Power on Reset Signal D004 VbDDrise rate to ensure SVDD 0 05 V ms See section on Power on Reset for details internal Power on Rese
173. IC16LC7X Greater of N prescale value 50 OR TCY 40 1 2 4 8 N Asynchronous PIC16C7X 60 ns PIC16LC7X 100 ns Ft1 Timer1 oscillator input frequency range DC 200 kHz oscillator enabled by setting bit T1OSCEN 48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc 7Tosc i These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 176 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 7 CAPTURE COMPARE PWM TIMINGS CCP1 RC2 CCP1 Capture Mode RC2 CCP1 Compare or PWM Mode 53 Note Refer to Figure 17 1 for load conditions TABLE 17 6 CAPTURE COMPARE PWM REQUIREMENTS CCP1 Param Sym Characteristic Min Typt Max Units Conditions No 50 TccL CCP1 input low time No Prescaler O 5TCY 20 ns With Prescaler PIC16C72 10 ns PIC16LC72 20 m ns 51 TecH CCP1 input high time No Prescaler 0 5TcY 20 ns With Prescaler PIC16C72 10 ns PIC16LC72 20 ns 52 TecP CCP1 input period 3Tcy 40 a ns N prescale N value 1 4 or 16 53 TccR CCP1 output rise time PIC16C72 10 25 ns PIC16LC72 25 45 ns 54 TccF CCP1
174. IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE 2 ADIE RCIE TXIE 2 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTO Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX xxxx uuuu uuuu 14h SSPCON WCOL ssPov SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 85h TRISA PORTA Data Direction Register 11 1111 11 1111 94h ssPsT ne P E RW UA BF 00 0000 00 0000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the SSP in SPI mode Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A always maintain these bits clear 2 The PIC16C72 does not have a Parallel Slave Port or USART these bits are unimplemented read as 0 DS30390E page 82 1997 Microchip Technology Inc Applicable Devices P C 1 6C7X 72 73 73A 74 74A 76 77 11 3 SPI Mode for PIC16C76 77 This section contains register definitions and opera tional characteristics of the SPI module on the PIC16C76 and PIC16C77 only FIGURE 11 7 SSPSTAT SYNC SERIAL PORT STATUS REGISTER ADDRESS 94h PIC16C76 77 R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 SMP CKE D A P S RAN UA BF R Readable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 SMP SPI data input sample phase SPI M
175. ISA PORTA Data Direction Register 1 111 11 1111 86h TRISB PORTB Data Direction Register 111 111 1111 1111 87h TRISC PORTC Data Direction Register 111 111 1111 1111 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h9 TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 111 0000 111 8Ah 1 4 PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIEG ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 0000 8Dh PIE2 CCP2IE Q 0 8Eh PCON POR BOR qq uu 8Fh Unimplemented 90h Unimplemented 91h Unimplemented 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port IC mode Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D A P S R W UA BF 0000 0000 0000 0000 95h Unimplemented 96h Unimplemented 97h Unimplemented 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah Unimplemented 9Bh Unimplemented 9Ch Unimplemented 9Dh Unimplemented 9Eh Unimplemented 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged q value depends on condition un
176. MICROCHIP PIC1 6C7X 8 Bit CMOS Microcontrollers with A D Converter Devices included in this data sheet Wide operating voltage range 2 5V to 6 0V High Sink Source Current 25 25 mA e PIC16C72 e PIC16C74A PIC16C73 PIC16C76 ee Industrial and Extended temperature E MIE Low power consumption PIC16C74 e lt 2 mA SV 4 MHz e 15 uA typical 3V 32 kHz e lt 1 uA typical standby current High performance RISC CPU PIC16C7X Peripheral Features Only 35 single word instructions to learn All single cycle instructions except for program branches which are two cycle Operating speed DC 20 MHz clock input DC 200 ns instruction cycle Up to 8K x 14 words of Program Memory up to 368 x 8 bytes of Data Memory RAM Interrupt capability Eight level deep hardware stack Direct indirect and relative addressing modes Power on Reset POR 8 bit multichannel analog to digital converter Power up Timer PWRT and Synchronous Serial Port SSP with Oscillator Start up Timer OST SPI and IPC Watchdog Timer WDT with its own on chip RC Universal Synchronous Asynchronous Receiver oscillator for reliable operation Transmitter USART SCI Programmable code protection Parallel Slave Port PSP 8 bits wide with Power saving SLEEP mode external RD WR and CS controls Selectable oscillator options Brown out detection circuitry for PIC16C7X Microcontroller Core Features TimerO 8 bit timer counter with 8 bit
177. Microchip Technology Inc PIC16C7X 12 0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER USART Applicable Devices 72 73 73A 74 74A 76 77 The Universal Synchronous Asynchronous Receiver Transmitter USART module is one of the two serial UO modules USART is also known as a Serial Com munications Interface or SCI The USART can be con figured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT ter minals and personal computers or it can be configured as a half duplex synchronous system that can commu nicate with peripheral devices such as A D or D A inte grated circuits Serial EEPROMs etc The USART can be configured in the following modes Asynchronous full duplex Synchronous Master half duplex Synchronous Slave half duplex Bit SPEN RCSTA lt 7 gt and bits TRISC lt 7 6 gt have to be set in order to configure pins RC6 TX CK and RC7 RX DT as the Universal Synchronous Asynchronous Receiver Transmitter FIGURE 12 1 TXSTA TRANSMIT STATUS AND CONTROL REGISTER ADDRESS 98h R W 0 R W 0 R W 0 R W 0 U 0 R W 0 R 1 R W 0 CSRC TX9 TXEN SYNC BRGH TRMT TX9D R Readable bit bit7 bit 7 CSRC Clock Source Select bit Asynchronous mode Don t care Synchronous mode 1 Master mode Clock generated internally from BRG 0 Slave mode Clock from external source
178. N is set the RC1 T1OSI CCP2 and RCO T1OSO T1CKI pins become inputs That is the TRISC lt 1 0 gt value is ignored For the PIC16C73 74 when the Timer1 oscillator is enabled T1OSCEN is set RC1 T1OSI CCP2 pin becomes an input however the RCO T1OSO T1CKI pin will have to be configured as an input by setting the TRISC lt 0 gt bit FIGURE 8 1 T1CON TIMER1 CONTROL REGISTER ADDRESS 10h U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 T1CKPS1 T1CKPSO T1OSCEN TISYNC TMR1CS TMR1ON R Readable bit bit 7 6 Unimplemented Read as 0 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 5 4 T1CKPS1 T1CKPSO Timer1 Input Clock Prescale Select bits 11 1 8 Prescale value 10 1 4 Prescale value 01 1 2 Prescale value 00 1 1 Prescale value bit 3 T1OSCEN Timer1 Oscillator Enable Control bit 1 Oscillator is enabled 0 Oscillator is shut off Note The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2 T1SYNC Timer External Clock Input Synchronization Control bit TMRICS 1 1 Do not synchronize external clock input 0 Synchronize external clock input TMR1CS 0 This bit is ignored Timer uses the internal clock when TMR1CS 0 bit 1 TMR1CS Timeri Clock Source Select bit 1 External clock from pin RCO T1OSO T1CKI on the rising edge 0 Internal clock Fosc 4 bit
179. NIW ISO 9001 QS 9000 REGISTERED FIRM gt e a 79 m m e ASIA PACIFIC continued Singapore Microchip Technology Singapore Pte Ltd 200 Middle Road 3107 02 Prime Centre Singapore 188980 Tel 65 334 8870 Fax 65 334 8850 Taiwan R O C Microchip Technology Taiwan 10F 1C 207 Tung Hua North Road Taipei Taiwan ROC Tel 886 2 2717 7175 Fax 886 2 2545 0139 EUROPE United Kingdom Arizona Microchip Technology Ltd 505 Eskdale Road Winnersh Triangle Wokingham Berkshire England RG41 5TU Tel 44 118 921 5858 Fax 44 118 921 5835 Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1 3 Ballerup DK 2750 Denmark Tel 45 4420 9895 Fax 45 4420 9910 France Arizona Microchip Technology SARL Parc d Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A ler Etage 91300 Massy France Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav Heinemann Ring 125 D 81739 M nchen Germany Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V Le Colleoni 1 20041 Agrate Brianza Milan Italy Tel 39 039 65791 1 Fax 39 039 6899883 11 15 99 Microchip received QS 9000 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona in July 1999 The Company s quality syste
180. NT pin INTF flag INTCON lt 1 gt Interrupt Latency Note 2 INTGON 75 l Processor in e r SLEEP i INSTRUCTION FLOW pc X PC Pod X SC PC 2 X 0004h 0005h Instruction fetched i Inst PC SLEEP Ins PC e 1 Instruction J executed 1 Inst PC 1 SLEEP Note 1 XT HSorLP oscillator mode assumed Inst PC 2 Inst 0004h Inst 0005h Inst PC 1 Dummy cycle Dummy cycle Inst 0004h 2 Tosr 1024Tosc drawing not to scale This delay will not be there for RC osc mode 3 GIE 1 assumed In this case after wake up the processor jumps to the interrupt routine If GIE 0 execution will continue in line 4 CLKOUT is not available in these osc modes but shown here for timing reference 14 9 Program Verification Code Protection Applicable Devices 72 73 73A 74 74A 76 77 If the code protection bit s have not been pro grammed the on chip program memory can be read out for verification purposes Note Microchip does not recommend code pro tecting windowed devices 14 10 ID Locations Applicable Devices 72 73 73A 74 74A 76 77 Four memory locations 2000h 2003h are designated as ID locations where the user can store checksum or other code identification numbers These locations are not accessible during normal execution but are read able and writable during program verify It is recom mended that only the 4 least significant bits of
181. ON ADRES ADCONO ADCON1 7Fh General Purpose Register General Purpose Register Bank 0 Bank 1 Unimplemented data memory locations read as wm Note 1 Not a physical register FIGURE 4 5 File Address PIC16C73 73A 74 74A REGISTER FILE MAP File Address 00h INDF INDF 80h Oth TMRO OPTION 81h 02h PCL PCL 03h STATUS STATUS 04h 05h FSR PORTA FSR TRISA 06h PORTB TRISB 07h PORTC TRISC PORTD2 TRISD PORTE 2 TRISE PCLATH PCLATH INTCON INTCON PIR1 PIE1 PIR2 PIE2 TMR1L PCON TMR1H T1CON TMR2 T2CON PR2 SSPBUF SSPADD SSPCON SSPSTAT CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCONO ADCON1 General Purpose Register General Purpose Register Bank 0 Bank 1 EI Unimplemented data memory locations read as 0 Note 1 Not a physical register 2 These registers are not physically imple mented on the PIC16C73 73A read as 0 1997 Microchip Technology Inc DS30390E page 21 PIC16C7X FIGURE 4 6 PIC16C76 77 REGISTER FILE MAP File Address Indirect addr Indirect addr Indirect addr Indirect addr 80h TMRO OPTION TMRO OPTION 181h PCL P
182. ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 15h CCPRIL Capture Compare PWM register1 LSB XXXX XXXx uuuu uuuu 16h CCPR1H Capture Compare PWM register1 MSB XXXX XXXx uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1MO0 00 0000 00 0000 1Bh CCPR2L Capture Compare PWM register2 LSB XXXX xxxx uuuu uuuu 1Ch CCPR2H Capture Compare PWM register2 MSB XXXX xxxx uuuu uuuu 1Dh 2 CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2MO0 00 0000 00 0000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by PWM and Timer2 Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear 2 The PIC16C72 does not have a Parallel Slave Port USART or CCP2 module these bits are unimplemented read as 0 DS30390E page 76 1997 Microchip Technology Inc Applicable Devi raaraa PIC16C7X 11 0 SYNCHRONOUS SERIAL PORT SSP MODULE 11 1 SSP Module Overview The Synchronous Serial Port SSP module is a serial interface useful for communicating with other periph eral or microcontroller devices These peripheral devices may be Serial EEPROMs shift registers dis play drivers A D converters etc The SSP module can operate in one of two modes Serial Peripheral Interface SPI Inter Integrated Circuit PC The SSP mod
183. ON lt 3 0 gt allow one of the following IC modes to be selected 12C Slave mode 7 bit address 12C Slave mode 10 bit address 12C Slave mode 7 bit address with start and stop bit interrupts enabled 12C Slave mode 10 bit address with start and stop bit interrupts enabled 12C Firmware controlled Master Mode slave is idle Selection of any 1 C mode with the SSPEN bit set forces the SCL and SDA pins to be open drain pro vided these pins are programmed to inputs by setting the appropriate TRISC bits The SSPSTAT register gives the status of the data transfer This information includes detection of a START or STOP bit specifies if the received byte was data or address if the next byte is the completion of 10 bit address and if this will be a read or write data transfer The SSPSTAT register is read only The SSPBUF is the register to which transfer data is written to or read from The SSPSR register shifts the data in or out of the device In receive operations the SSPBUF and SSPSR create a doubled buffered receiver This allows reception of the next byte to begin before reading the last byte of received data When the complete byte is received it is transferred to the SSPBUF register and flag bit SSPIF is set If another complete byte is received before the SSPBUF register is read a receiver overflow has occurred and bit SSPOV SSPCON lt 6 gt is set and the byte in the SSPSR is lost The SSPADD register holds
184. OR reset bit 7 RBPU PORTB Pull up Enable bit bit 6 bit 5 bit 4 bit 3 bit 2 0 1 PORTB pull ups are disabled 0 PORTB pull ups are enabled by individual port latch values INTEDG Interrupt Edge Select bit 1 2 Interrupt on rising edge of RBO INT pin 0 Interrupt on falling edge of RBO INT pin TOCS TMRO Clock Source Select bit 1 Transition on RA4 TOCKI pin 0 Internal instruction cycle clock CLKOUT TOSE TMRO Source Edge Select bit 1 Increment on high to low transition on RA4 TOCKI pin 0 Increment on low to high transition on RA4 TOCKI pin PSA Prescaler Assignment bit 1 Prescaler is assigned to the WDT 0 Prescaler is assigned to the TimerO module PS2 PS0 Prescaler Rate Select bits Bit Value TMRO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 TE 1 256 1 128 1997 Microchip Technology Inc DS30390E page 31 PIC16C7X 4 2 2 3 INTCON REGISTER Applicable Devices Note Interrupt flag bits get set when an interrupt 72173 73A 74 74AT76777 condition occurs regardless of the state of LOADS A its corresponding enable bit or the global The INTCON Register is a readable and writable regis enable bit GIE INTCON lt 7 gt ter which contains various enable and flag bits for the TMRO register overflow RB Port change and External RBO INT pin interrupts FIGURE 4 9 INTCON
185. Old uy eg 1S09 MO7 enin oi LHVLSOld lapow e4e jos v 99ueJnpu3 EJOL J0 eJouox opo suoneoiddy n EMSAUG dN JOO og 91607 Azzn4 uonip3 1840Idx3 diW HO3 L zzny Jejiduio5 9 w 1d SI001 a1eEMYOS 1ueuiuoJiAu3 jueuidojo eg po1jeJbo1u wav Idi Joyeynuy 11n2412 uJ SO9D MO7 914291 LOESOH XX9 6 160 e geire v J0je nui3 11n24125 uJ 39 431SVN9Id HALSVINDId sjonpoig 10 enwa 00 S9H XX9S2 XSLOLLDId XVOLLOId XX699L91d X899L91d XXZ 9L ld X999L ld XXX 9L ld XS99L91Id OOOVLOId XXSOSLOld 002S9H XXotc 1997 Microchip Technology Inc DS30390E page 166 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17 0 ELECTRICAL CHARACTERISTICS FOR PIC16C72 Absolute Maximum Ratings T Ambient temperature urder bias cic tec irr tete ree eine dira die decer aged 55 to 125 C Storage temperatures tente edd pe De a i E ed e e E UR anni unes 65 C to 150 C Voltage on any pin with respect to Vss except VDD MCLR and RAA 0 3V to VDD 0 3V Voltage on VDD with respect to VSS issues 0 3 to 7 5V Voltage on MCLR with respect to VSS Note 2 0 to 14V Voltage on RA4 with respecto VSS eere ce ede ec anode tese a ex dc tbe edd de descen 0 to 14V Total power dissipation Notoe 1 rerit tenet iere teni trt ars r tre MR eR REL ent es HERRERA ee UNE HER
186. Output Buffer Full sta tus flag bit OBF TRISE lt 6 gt is cleared immediately Figure 5 13 indicating that the PORTD latch is waiting to be read by the external bus When either the CS or RD pin becomes high level triggered the interrupt flag bit PSPIF is set on the Q4 clock cycle following the next Q2 cycle indicating that the read is complete OBF remains low until data is written to PORTD by the user firmware When not in Parallel Slave Port mode the IBF and OBF bits are held clear However if flag bit IBOV was previ ously set it must be cleared in firmware An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE PIE1 lt 7 gt DS30390E page 54 1997 Microchip Technology Inc PIC16C7X FIGURE 5 12 PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD lt 7 0 gt IBF OBF TABLE 5 11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT value ON Value on all Address Name Bit7 Bit6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 08h PORTD _ Port data latch when written Port pins when read XXXX XXXX uuuu uuuu 09h PORTE R
187. P mode d Interrupt to CPU TXIF TXIE SSPIF SSPIE p amm CCP1IF CCPIIE TMR2IF TMR2IEA TMR1IF TMR1IE CCP2IF zm CCP2IE The following table shows which devices have which interrupts Device RCIF TXIF CCP1IF TMR2IF TMR1IF CCP2IF PIC16C72 Yes Yes Yes PIC16C73 Yes Yes Yes PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16C77 OSCH CLKOUT 3 INT pin NEU INTF flag i i INTCON lt 1 gt l GIE bit INTCON lt 7 gt INSTRUCTION FLOW Interrupt Latency 2 Instruction fetched Inst PC Inst PC 1 Inst 0004h Inst 0005h Inst PC 1 Inst PC Dummy Cycle executed PC lt PC X PC X PCH X mon Instruction Dummy Cycle Inst 0004h Note 1 INTF flag is sampled here every Q1 2 Interrupt latency 3 4 Tcy where JEE cycle time Latency is the Same whether Inst PC is a single cycle or a 2 cycle instruction 3 CLKOUT is available only in RC oscillator mode 4 For minimum width of INT pulse refer to AC specs 5 INTF is enabled to be set anytime during the Q4 Q1 cycles DS30390E page 142 1997 Microchip Technology Inc PIC16C7X 14 5 1 INT INTERRUPT External interrupt on RBO INT pin is edge triggered either rising if bit INTEDG OPTION 6 is set or fall ing if the INTEDG bit is clear When a valid
188. PBUF register Addi tionally the SSP status register SSPSTAT indicates the various status conditions FIGURE 11 3 SSP BLOCK DIAGRAM SPI MODE Internal data bus Write SSPSR reg RC4 SDI SDA bitO RC5 SDO SS Control Enable D RA5 SS AN4 Edge Select 2 Ri Select SSPM3 SSPMO TMR2 output 4 2 Prescaler TCY 4 16 64 RC3 SCK SCL TRISC lt 3 gt DS30390E page 80 1997 Microchip Technology Inc Applicable Devices 72 73 73A 74 74A PIC16C7X To enable the serial port SSP enable bit SSPEN SSPCON lt 5 gt must be set To reset or reconfigure SPI mode clear enable bit SSPEN re initialize SSPCON register and then set enable bit SSPEN This config ures the SDI SDO SCK and SS pins as serial port pins For the pins to behave as the serial port function they must have their data direction bits in the TRIS reg ister appropriately programmed That is e SDI must have TRISC lt 4 gt set e SDO must have TRISC lt 5 gt cleared SCK Master mode must have TRISC lt 3 gt cleared SCK Slave mode must have TRISC lt 3 gt set e SS must have TRISA lt 5 gt set if implemented Any serial port function that is not desired may be over ridden by programming the corresponding data direc tion TRIS register to the opposite value An example wo
189. PI MODE TIMING Note Refer to Figure 19 1 for load conditions TABLE 19 8 SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 70 TssL2scH SSJ to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time slave mode Tcv 20 ns 72 TscL SCK input low time slave mode Tcv 20 ns 73 TdiV2scH Setup time of SDI data input to SCK 100 ns TdiV2scL edge 74 TscH2diL Hold time of SDI data input to SCK 100 ns TscL2diL edge 75 TdoR SDO data output rise time 10 25 ns 76 TdoF SDO data output fall time 10 25 ns 77 TssH2doZ SST to SDO output hi impedance 10 50 ns 78 TscR SCK output rise time master mode 10 25 ns 79 TscF SCK output fall time master mode 10 25 ns 80 TscH2doV SDO data output valid after SCK 50 ns TscL2doV edge t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 213 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 10 IC BUS START STOP BITS TIMING Condition Condition Note Refer to Figure 19 1 for load conditions TABLE 19 9 12C BUS START STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Unit
190. Peer entr Re 1 0W Maximum current out of VSS pin onec rer eia edion Ea aade caue e eurer sve estara nee de rings 300 mA Maximum current into VDD IP issn chase RUE phe edet ete Ra ne inner eae 250 mA Input clamp current liK VI 0 or VI gt VDD ire 20 mA Output clamp current IOK VO lt 0 or VO gt VDD eee 20 mA Maximum output current sunk by any I O pin iii Maximum output current sourced by any I O pin iii Maximum current sunk by PORTA and PORTB combined Maximum current sourced by PORTA and PORTB combined Maximum current sunk by PORTO sesseeemem Maximum current sourced by PORTC Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Y 10H X VDD VOH x loH X Vol x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability TABLE 17 1 CROSS REFERENCE OF DEVICE SPECS FO
191. QA to A D clock start 135 Tswc Switching from convert sample time Min 1 6 2 0 2 0 3 0 158 These parameters are characterized but not tested Applicable Devices 72 73 73A 74 74A 76 77 Typt Tosc 2 Max Units TAD Conditions Tosc based VREF 2 3 0V Tosc based VREF full range A D RC Mode A D RC Mode The minimum time is the amplifier settling time This may be used if the new input voltage has not changed by more than 1 LSb i e 20 0 mV 9 5 12V from the last sampled voltage as stated on CHOLD If the A D clock source is selected as RC a time of Tcv is added before the A D clock starts This allows the SLEEP instruction to be executed Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not T tested S This specification ensured by design 1 See Section 13 1 for min conditions ADRES register may be read on the following Tcy cycle 1997 Microchip Technology Inc DS30390E page 239 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 NOTES DS30390E page 240 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 21 0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed
192. R 0 x x o Illegal PD is set on PO 1 0 x x Brown out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake up from SLEEP TABLE 14 7 RESET CONDITION FOR SPECIAL REGISTERS u Program STATUS PCON PCON Condition Counter Register Register Register PIC16C73 74 PIC16C72 73A 74A 76 77 Power on Reset 000h 0001 1xxx 0 9 Ox MCLR Reset during normal operation 000h 000u uuuu Sect Sous uu MCLR Reset during SLEEP 000h 0001 Ouuu u uu WDT Reset 000h 0000 1uuu u uu WDT Wake up PC 1 uuu0 Ouuu Ep eue N LES uu Brown out Reset 000h 0001 luuu NA u0 Interrupt wake up from SLEEP PC 1 uuul Ouuu Sen esse uu Legend u unchanged x unknown unimplemented bit read as 0 Note 1 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h TABLE 14 8 INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power on Reset MCLR Resets Wake up via WDT Brown out Reset WDT Reset or Interrupt W 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu INDF 73A 74 TMRO 73A 74 XXXX XXXX uuuu uuuu uuuu uuuu STATUS 73A 74 0001 1xxx 000q quuu uuuq quuu PORTA 73A 74 0x 0000 0u 0000 uu uuuu PORTC 73A 74 XXXX XXXX uuuu uuuu uuuu uuuu PORTE 73A 74 Legen
193. R OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION COMMERCIAL DEVICES PIC16C72 04 PIC16C72 10 PIC16C72 20 PIC16LC72 04 JW Devices DD 4 0V to 6 0V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 2 5V to 6 0V VDD 4 0V to 6 0V DD 5 mA max at 5 5V IDD 2 7 mA typ at 5 5V D 2 7 mAtyp at5 5V Ipb 3 8 mA max at 3 0V IDD 5 mA max at 5 5V PD 16 uA max at 4V IPD 1 5 uA typ at 4V D 1 5 uA typ at 4V IPD 5 0 uA max at 3V IPD 16 uA max at AN req 4 MHZ max Freq 4 MHz max eq 4 MHz max Freq 4 MHz max Freq 4 MHz max DD 4 0V to 6 0V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 2 5V to 6 0V VDD 4 0V to 6 0V DD 5 mA max at 5 5V IDD 2 7 mA typ at 5 5V D 2 7 mAtyp at5 5V Ipb 3 8 mA max at 3 0V IDD 5 mA max at 5 5V PD 16 uA max at 4V IPD 1 5 uA typ at 4V D 1 5 uA typ at 4V IPD 5 0 uA max at 3V IPD 16 uA max at AN eq 4 MHZ max Freq 4 MHz max eq 4 MHz max Freq 4 MHz max Freq 4 MHz max DD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V VDD 4 5V to 5 5V 13 5 mA typ at 5 5V IDD 10 mA max at5 5V IDD 20 mA max at 5 5V Not recommended for use IDD 20 mA max at 5 5V 1 5uAtyp at4 5V IPD 1 5 pA typ at 4 5V PD 1 5 pA typ at 4 5V in HS mode IPD 1 5 LA typ at 4 5V 4 MHz max Freq 10 MHz max Freq 20 MHz max Freq 20 MHz max 4 0V to 6 0V VDD 2 5V to 6 0V VDD 2 5V to 6 0V Dec a Not recommended for use Not recommended for use BBF AS HA mar at ESS MA max dl 32 k
194. R bit is a Don t Care bit and is not necessarily predictable if the Brown out Reset circuitry is disabled by clearing bit BODEN in the Configuration Word Bit is POR Power on Reset Status bit It is cleared on a Power on Reset and unaffected otherwise The user must set this bit following a Power on Reset TABLE 14 3 TIME OUT IN VARIOUS SITUATIONS PIC16C73 74 Oscillator Configuration Power up Wake up from SLEEP PWRTE 1 PWRTE 0 XT HS LP 72 ms 1024Tosc 1024Tosc 1024 Tosc RC 72 ms TABLE 14 4 TIME OUT IN VARIOUS SITUATIONS PIC16C72 73A 74A 76 77 Oscillator Configuration Power up Browaut Wake up from SLEEP PWRTE 0 PWRTE 1 XT HS LP 72 ms 1024Tosc 1024Tosc 72 ms 1024Tosc 1024Tosc RC 72 ms 72 ms TABLE 14 5 STATUS BITS AND THEIR SIGNIFICANCE PIC16C73 74 POR TO PD 0 1 1 Power on Reset 0 0 x Illegal TO is set on POR 0 x 0 Illegal PD is set on POR 1 0 1 WDT Reset 1 0 0 WDT Wake up 1 u u MCLR Reset during normal operation 1 1 0 MCLR Reset during SLEEP or interrupt wake up from SLEEP Legend u unchanged x unknown 1997 Microchip Technology Inc DS30390E page 135 PIC16C7X TABLE 14 6 STATUS BITS AND THEIR SIGNIFICANCE PIC16C72 73A 74A 76 77 POR BOR TO PD 0 x 1 1 Power on Reset 0 x 0 x llegal TO is set on PO
195. RATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Qi Q2 Q3 Q4 Note PC X PC X PC 1 X Instruction MOVWE PORTB MOVE PORTB W X PC 2 X PC 3 This example shows a write to PORTB followed by a read from PORTE Note that data setup time 0 25TCY TPD fetched write to NOP NOP PORTB RB7 RBO where TCY instruction cycle ror an here TPD propagation delay Le Therefore at higher clock frequencies executed a write followed by a read may be prob MOVF PORTB W lematic MOVWF PORTB write to PORTB f i i 1 i 1 Instruction i 1 i 1 i 1 i 1997 Microchip Technology Inc DS30390E page 53 PIC16C7X 5 7 Parallel Slave Port FIGURE 5 11 PORTD AND PORTE BLOCK DIAGRAM PARALLEL SLAVE PORT Applicable Devices 72 73 73A 74 74A 76 77 PORTD operates as an 8 bit wide Parallel Slave Port or microprocessor port when control bit PSPMODE TRISE 4 is set In slave mode it is asynchronously readable and writable by the external world through RD control input pin REO RD AN5 and WR control input pin RE1 WR ANG It can directly interface to an 8 bit microprocessor data bus The external microprocessor can read or write the PORTD latch as an 8 bit latch Setting bit PSPMODE enables port pin REO RD ANB to be the RD input RE1 WR ANG to be the WR input and RE2 CS AN7 to be the L CS chip select input For this functionality the corre
196. RC7 RX DT pin x Bo OC Bit 1 X Bit 2 X lt 6 Bit7 X BD xX BUX WORD 1 et Write to 1 L gt a WORD 2 TXREG reg H s RC6 TX CK pin rite word2 TXIF bit Interrupt flag TRMT bit TXENbit 55 Note Sync master mode SPBRG 0 Continuous transmission of two 8 bit words FIGURE 12 13 SYNCHRONOUS TRANSMISSION THROUGH TXEN 1997 Microchip Technology Inc DS30390E page 111 PIC16C7X 12 3 2 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected reception is enabled by setting either enable bit SREN RCSTA 5 or enable bit CREN RCSTA lt 4 gt Data is sampled on the RC7 RX DT pin on the falling edge of the clock If enable bit SREN is set then only a single word is received If enable bit CREN is set the recep tion is continuous until CREN is cleared If both bits are set then CREN takes precedence After clocking the last bit the received data in the Receive Shift Register RSR is transferred to the RCREG register if it is empty When the transfer is complete interrupt flag bit RCIF PIR1 lt 5 gt is set The actual interrupt can be enabled disabled by setting clearing enable bit RCIE PIE1 lt 5 gt Flag bit RCIF is a read only bit which is reset by the hardware In this case it is reset when the RCREG register has been read and is empty The RCREG is a double b
197. REMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No Fosc External CLKIN Frequency DC 4 MHz XT and RC osc mode Note 1 DC 4 MHz HS osc mode 04 DC 10 MHz HS osc mode 10 DC 20 MHz HS osc mode 20 DC 200 kHz LP osc mode Oscillator Frequency DC 4 MHz RC osc mode Note 1 0 1 4 MHz XT osc mode 4 20 MHz HS osc mode 5 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 ns XT and RC osc mode Note 1 250 ns HS osc mode 04 100 ns HS osc mode 10 50 ns HS osc mode 20 5 us LP osc mode Oscillator Period 250 ns RBC osc mode Note 1 250 10 000 ns XT osc mode 250 250 ns HS osc mode 04 100 250 ns HS osc mode 10 HS osc mode 20 50 250 ns 5 us LP osc mode 2 Tcv Instruction Cycle Time Note 1 200 Tcv DC ns TCY 4 Fosc 3 TosL External Clock in OSC1 High or 100 m ns XT oscillator TosH Low Time 2 5 us LP oscillator 15 ns HSoscillator 4 TosR External Clock in OSC1 Rise or 25 ns XT oscillator TosF Fall Time 50 ns LP oscillator 15 ns HSoscillator T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Instruction cycle period Tcv equals four times the input oscillator time base perio
198. S30390E page 126 1997 Microchip Technology Inc PIC16C7X TABLE 13 3 SUMMARY OF A D REGISTERS PIC16C73 73A 74 74A 76 77 Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR other Resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh DCH PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 ODh PIR2 CCP2IF g 0 8Dh PIE2 CCP2IE 0 0 1Eh ADRES A D Result Register XXXX XXXX uuuu uuuu 1Fh ADCONO ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON 0000 00 0 0000 00 0 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 05h PORTA RA5 RA4 RA3 RA2 RA1 RAO 0x 0000 Ou 0000 85h TRISA PORTA Data Direction Register 11 1111 11 1111 09h PORTE T RE2 RE1 REO xxx uuu 89h TRISE IBF OBF IBOV PSPMODE MA PORTE Data Direction Bits 0000 111 0000 111 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used for A D conversion Note 1 Bits PSPIE and PSPIF are reserved on the PIC6C73 73A 76 always maintain these bits clear DS30390E page 127 1997 Microchip Technology Inc PIC16C7X NOTES
199. SART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture Compare PWM Register2 LSB XXXX xxxx uuuu uuuu 1Ch CCPR2H Capture Compare PWM Register2 MSB XXXX xxxx uuuu uuuu 1Dh CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2MO 00 0000 00 0000 1Eh ADRES A D Result Register XXXX xxxx uuuu uuuu 1Fh ADCONO ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON 0000 00 0 0000 00 0 Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Note 1 300 Qi oom Shaded locations are unimplemented read as 0 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con tents are transferred to the upper byte of the program counter Other non power up resets include external reset through MCLR and Watchdog Timer Reset Bits PSPIE and PSPIF are reserved on the PIC16C73 73A always maintain these bits clear These registers can be addressed from either bank PORTD and PORTE are not physically implemented on the PIC16C73 73A read as 0 Brown out Reset is not implemented on the PIC16C73 or the PIC16C74 read as 0 The IRP and RP1 bits are reserved on the PIC16C73 73A 74 74A always maintain these bits clear 1997 Microchip Technology Inc DS30390E page 25 PIC16C7X
200. SSPBUF register while bit SSPOV is cleared through software The SCL clock input must have a minimum high and low for proper operation The high and low times of the IC specification as well as the requirement of the SSP module is shown in timing parameter 100 and param eter 101 11 5 1 1 ADDRESSING Once the SSP module has been enabled it waits for a START condition to occur Following the START condi tion the 8 bits are shifted into the SSPSR register All incoming bits are sampled with the rising edge of the clock SCL line The value of register SSPSR 7 1 is compared to the value of the SSPADD register The address is compared on the falling edge of the eighth clock SCL pulse If the addresses match and the BF and SSPOV bits are clear the following events occur a The SSPSR register value is loaded into the SSPBUF register b The buffer full bit BF is set c An ACK pulse is generated d SSP interrupt flag bit SSPIF PIR1 lt 3 gt is set interrupt is generated if enabled on the falling edge of the ninth SCL pulse In 10 bit address mode two address bytes need to be received by the slave Figure 11 16 The five Most Sig nificant bits MSbs of the first address byte specify if this is a 10 bit address Bit R W SSPSTAT lt 2 gt must specify a write so the slave device will receive the sec ond address byte For a 10 bit address the first byte would equal 1111 0 A9 A8 0 where A9 and A8 are the
201. Shaded locations are unimplemented read as 0 Note 1 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con tents are transferred to the upper byte of the program counter Other non power up resets include external reset through MCLR and Watchdog Timer Reset Bits PSPIE and PSPIF are reserved on the PIC16C76 always maintain these bits clear These registers can be addressed from any bank PORTD and PORTE are not physically implemented on the PIC16C76 read as 0 1997 Microchip Technology Inc DS30390E page 27 PIC16C7X TABLE 4 3 PIC16C76 77 SPECIAL FUNCTION REGISTER SUMMARY Cont d Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 2 Bank 1 80h 4 INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 81h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PSI PSO 111 111 1111 1111 82h4 PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 83h 4 STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer XXXX xxxx uuuu uuuu 85h TR
202. TO Functions s seseeneeee eeaeee ennenen 48 Table 5 6 Summary of Registers Associated With PORTG risiini aaan 49 Table 5 7 PORTD Functions sessssss 50 Table 5 8 Summary of Registers Associated with PORT D aeiia tirnisa naeted 50 Table 5 9 PORTE Functions 52 Table 5 10 Summary of Registers Associated with PORTE sssesseeeeeeenene 52 Table 5 11 Registers Associated with Parallel Slave Port 55 Table 7 1 Registers Associated with TimerO 63 Table 8 1 Capacitor Selection for the Timer Oscillator 5 inerte 67 Table 8 2 Registers Associated with Timer1 as a Timer Counter ccceeceeeseeeeeeeeeees 68 Table 9 1 Registers Associated with Timer2 as a Timer Counter 70 Table 10 1 CCP Mode Timer Resource 71 Table 10 2 Interaction of Two CCP Modules 71 Table 10 3 Example PWM Frequencies and Resolutions at 20 MHz 75 Table 10 4 Registers Associated with Capture Compare and Timer1 75 Table 10 5 Registers Associated with PWM and LEE 76 Table 11 1 Registers Associated with SPI Operation essseenene 82 Table 11 2 Registers Associated with SPI Operation PIC16C76 77 88 Table 11 3 DC Bus Terminology 89 Table 11 4 Data Transfer Received Byte Actions
203. TTL Input output port pin or read control input in parallel slave port mode or analog input RD 1 2 Not a read operation 0 Read operation Reads PORTD register if chip selected RE1 WR AN6 bit1 ST TTL Input output port pin or write control input in parallel slave port mode or analog input WR 1 Nota write operation 0 Write operation Writes PORTD register if chip selected RE2 CS AN7 bit2 ST TTL Input output port pin or chip select control input in parallel slave port mode or analog input CS 1 Device is not selected 0 Device is selected Legend ST Schmitt Trigger input TTL TTL input Note 1 Input buffers are Schmitt Triggers when in I O mode and TTL buffers when in Parallel Slave Port Mode TABLE 5 10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE folem Value on all Address Name Bit 7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 09h PORTE RE2 RE1 REO xxx uuu 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits 0000 111 0000 111 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by PORTE eee eee a DS30390E page 52 1997 Microchip Technology Inc PIC16C7X 5 6 UO Programming Considerations EXAMPLE 5 4 READ MODIFY WRITE Applicable Devices INSTRUCTIONS ON AN
204. Tim er Timing rir tenter 191 TimerO and Timer1 External Clock Timings ene 192 Capture Compare PWM Timings CCP1 and CCP2 sss 193 Parallel Slave Port Timing PIC16C74 sse SPI Mode Timing eeeeceeeeceeeeeeeneees DC Bus Start Stop Bits Timing S DC Bus Data Timing USART Synchronous Transmission Master Slave Timing 198 USART Synchronous Receive Master Slave Timing A D Conversion Timing M Load Conditions External Clock Timing CLKOUT and I O Timing 208 Reset Watchdog Timer Oscillator Start up Timer and Power up Timer Timing 209 Brown out Reset Timing 209 TimerO and Timer External Clock Timings eene 210 Capture Compare PWM Timings CCP1 and CCP2 sess 211 Parallel Slave Port Timing PIC16C744A oo eeeeseeneeeeeeteeeeeeneeneeeeeeaes 212 SPI Mode Timing 213 DC Bus Start Stop Bits Timing 214 DC Bus Data Timing 215 USART Synchronous Transmission Master Slave Timing 216 USART Synchronous Receive Master Slave Timing 216 A D Conversion Timing 218 Load Conditions 225 External Clock Timing 226 CLKOUT and I O Timing 227 Reset
205. UO pins tristated pulled to VoD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VOD and Vss 4 For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula Ir VDD 2Rext mA with Rext in kOhm 5 Timer1 oscillator when enabled adds approximately 20 uA to the specification This value is from charac terization and is for design guidance only This is not tested 6 The A current is the additional current consumed when this peripheral is enabled This current should be added to the base IDD or IPD measurement DS30390E page 168 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 17 2 DC Characteristics PIC16LC72 04 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 85 C for industrial and DU CHARACTERISTICS 0 C lt TA 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 2 5 6 0 V LB XT RC osc configuration DC 4 MHz D002 RAM Data Retention Volt VDR 1 5 V age Note 1 D003 VDD start voltage to VPOR Vss V ee section on Power on Reset
206. V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 178 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 9 1 C BUS START STOP BITS TIMING Condition Condition Note Refer to Figure 17 1 for load conditions TABLE 17 8 12C BUS START STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No 90 TSU STA START condition 100 kHz mode 4700 ep Only relevant for repeated START Setup time 400 KHz mode 600 condition 91 THD STA START condition 100 kHz mode 4000 m After this period the first clock Hold time 400 kHz mode 600 pulse is generated 92 Tsu sTO STOP condition 100 kHz mode 4700 ER Setup time 400 kHz mode 600 93 THD STO STOP condition 100 kHz mode 4000 h Hold time 400 kHz mode 600 1997 Microchip Technology Inc DS30390E page 179 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 10 IC BUS DATA TIMING 108 o MEE Out Se ds Note Refer to Figure 17 1 for load conditions TABLE 17 9 1 C BUS DATA REQUIREMENTS Parameter Sy
207. VDD 5V 40 C to 125 C 31 Twdt Watchdog Timer Time out Period 7 18 33 ms VDD 5V 40 C to 125 C No Prescaler 32 Tost Oscillation Start up Timer Period 1024Tosc Tosc OSC period 33 Tpwrt Power up Timer Period 28 72 132 ms VDD DM 40 C to 125 C UO Hi impedance from MCLR Low or Watchdog Timer Reset Brown out Reset pulse width VpD lt BVDD D005 These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 228 1997 Microchip Technology Inc PIC16C7X 73 72 T9A 74 74A 76 77 Applicable Devices FIGURE 20 6 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS RA4 TOCKI RCO T1OSO T1CKI TMRO or TMR1 Note Refer to Figure 20 1 for load conditions TABLE 20 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 Sie ns parameter 42 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns parameter 42 42 TtOP TOCKI Period No Prescaler Tcy 40 ns With Prescaler Greater of ns N prescale v
208. W 0x17 FSR OxC2 After Instruction W 0x17 FSR 0x02 1997 Microchip Technology Inc DS30390E page 149 PIC16C7X BCF Bit Clear f Syntax labe BCF bh Operands 0 lt f lt 127 O lt b lt 7 Operation 0 gt f lt b gt Status Affected None Encoding 01 00bb bfff ffff Description Bit b in register f is cleared Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register data register f T Example BCF FLAG REG 7 Before Instruction FLAG REG 0xC7 After Instruction FLAG REG 0x47 BSF Bit Set f Syntax label BSF f b Operands O lt f lt 127 O lt b lt 7 Operation 1 gt f lt b gt Status Affected None Encoding 01 Olbb bfff ffff Description Bit b in register f is set Words 1 Cycles 1 Q Cycle Activity Example Q1 Q2 Q3 Q4 Decode Read Process Write register data register f T BSF FLAG REG 7 Before Instruction FLAG REG 0x0A After Instruction FLAG REG 0x8A BTFSC Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity If Skip Example Bit Test Skip if Clear label BTFSC fb 0 lt f lt 127 O0 lt b lt 7 skip if f lt b gt 0 None 01 10bb bfff ffff If bit b in register f is 1 then the next instruction is executed If bit b in register f is 0 then the next instruction is discar
209. X Family devices use serial programming with clock pin RB6 and data pin RB7 E 9 PIC16C9XX Family Of Devices Maximum Frequency of Operation MHz PIC16C923 PIC16C924 ALLER SPI I2C USART 8 8 M EPROM Program Memory 4K 4K emor d Data Memory bytes 176 176 Timer Module s TMRO TMRO TMR1 TMR1 TMR2 TMR2 Capture Compare PWM Module s 1 1 Serial Port s SPI C SPI I C Parallel Slave Port A D Converter 8 bit Channels 5 LCD Module 4 Com 4 Com 32 Seg 32 Seg Interrupt Sources 8 9 UO Pins 25 25 Input Pins 27 27 Voltage Range Volts 3 0 6 0 3 0 6 0 In Circuit Serial Programming Yes Yes Brown out Reset Packages 64 pin SDIP 64 pin SDIP TQFP TQFP 68 pin PLCC 68 pin PLCC Die Die All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capa bility All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7 DS30390E page 269 1997 Microchip Technology Inc PIC16C 7X E 10 PIC17CXXX Family of Devices Maximum Frequency of Operation MHz Memory Peripherals Features PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 33 33 33 33 33 EPROM Program Memory 2K 4K 8K words ROM Program Memory 2K m 4K words RAM Data Memo
210. a1 02 03 04 01 02 03 04 01 02 03 04 1 a2 a3 a4 o a2 03 04 01 G2 03 04 Q1 o2 03 G4 Program MOVWF TMRO MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W MOVF TMRO W Instruction Fetch NTO 1 YX eg E up ot cg wq oq Execute A WriteTMRO ReadTMRO ReadTMRO ReadTMRO ReadTMRO ReadTMRO executed reads NTO reads NTO reads NTO reads NTO reads NTO 1 TMRO TO Tori X Counter SCH PC XO SES RER ER ER EE XO POA POS Y PC 6 FIGURE 7 4 TIMERO INTERRUPT TIMING at a2 a3 aa at a as 04 ai a2 a a4 at a 03 aa at a2 a3 as GE ASEA EN ky AR PER ee eC a Ya A es CLKOUT 3 TimerO TOIF bit INTCON lt 2 gt GIE bit INTCON lt 7 gt FLOW INSTRUCTION i Inst PC Inst PC 1 Inst 0004h Inst 0005h Instruction fetched Inst PC Dumny cycle Dumny cycle Inst 0004h executed PC X PC 1 X i 0004h X 0005h Instruction Inst PC 1 Note 1 Interrupt flag bit TOIF is sampled here every Q1 2 Interrupt latency 4Tcy where Tcy instruction cycle time 3 CLKOUT is available only in RC oscillator mode DS30390E page 60 1997 Microchip Technology Inc PIC16C7X 7 2 Using TimerO with an External Clock Applicable Devices 72 73 73A 74 74A 76 77 When an external clock input is used for TimerO it must meet certain requirements The requirements ensure the external clock can be synchronized with the inte
211. ability and reducing power consumption There are four oscillator options of which the single pin RC oscillator provides a low cost solution the LP oscil lator minimizes power consumption XT is a standard crystal and the HS is for High Speed crystals The SLEEP power down feature provides a power saving mode The user can wake up the chip from SLEEP through several external and internal interrupts and resets A highly reliable Watchdog Timer with its own on chip RC oscillator provides protection against software lock up A UV erasable CERDIP packaged version is ideal for code development while the cost effective One Time Programmable OTP version is suitable for production in any volume The PIC16C7X family fits perfectly in applications rang ing from security and remote sensors to appliance con trol and automotive The EPROM technology makes customization of application programs transmitter codes motor speeds receiver frequencies etc extremely fast and convenient The small footprint packages make this microcontroller series perfect for all applications with space limitations Low cost low power high performance ease of use and O flexibility make the PIC16C7X very versatile even in areas where no microcontroller use has been considered before e g timer functions serial communication capture and compare PWM functions and coprocessor appli cations 1 1 Family and Upward Compatibility Users familiar with t
212. able Devices 72 73 73A 74 74A 76 77 The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers Bits RP1 and RPO are the bank select bits RP1 RPO STATUS lt 6 5 gt 00 Bank 01 Banki 10 Bank2 11 Bank Each bank extends up to 7Fh 128 bytes The lower locations of each bank are reserved for the Special Function Registers Above the Special Function Regis ters are General Purpose Registers implemented as static RAM All implemented banks contain special function registers Some high use special function registers from one bank may be mirrored in another bank for code reduction and quicker access 4 2 1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi rectly through the File Select Register FSR Section 4 5 DS30390E page 20 1997 Microchip Technology Inc PIC16C7X FIGURE 4 4 File Address MAP PIC16C72 REGISTER FILE File Address 00h INDF INDF 80h Oth TMRO OPTION 81h PCL PCL 82h STATUS STATUS 83h FSR FSR 84h PORTA TRISA 85h PORTB TRISB 86h PORTC TRISC PCLATH PCLATH INTCON INTCON PIR1 PIE1 TMR1L TMR1H PCON T1CON TMR2 T2CON PR2 SSPBUF SSPADD SSPCON SSPSTAT CCPR1L CCPR1H CCP1C
213. able bit and interrupt flag bit set one of the following will occur If the interrupt occurs before the execution of a SLEEP instruction the SLEEP instruction will com plete as a NOP Therefore the WDT and WDT postscaler will not be cleared the TO bit will not be set and PD bits will not be cleared f the interrupt occurs during or after the execu tion of a SLEEP instruction the device will imme diately wake up from sleep The SLEEP instruction will be completely executed before the wake up Therefore the WDT and WDT postscaler will be cleared the TO bit will be set and the PD bit will be cleared Even if the flag bits were checked before executing a SLEEP instruction it may be possible for flag bits to become set before the SLEEP instruction completes To determine whether a SLEEP instruction executed test the PD bit If the PD bit is set the SLEEP instruction was executed as a NOP To ensure that the WDT is cleared a CLRWDT instruc tion should be executed before a SLEEP instruction 1997 Microchip Technology Inc DS30390E page 145 PIC16C7X FIGURE 14 20 WAKE UP FROM SLEEP THROUGH INTERRUPT atl l a3l ail az asl a4 oul oscit AVV AF NA CLKOUT 4 __ ZA ZA ol aal ol Q4 ail l as Q4 ol al a3 la olosloal a4 NA AN ANR ER EN E CEA 1 4 TosT 2 I
214. ack normal VoD limits QTP SOIC Skinny plastic dip pattern 301 PDIP Package PIC16LC76 041 SO PLCC Industrial Temp SOIC SSOP package 4 MHz 0 C to 70 C extended VDD limits 40 C to 85 C PIC16C74A 10E P ACCES C Automotive Temp 200 kHz PIC16C7X 04 PDIP package 10 MHz 4 MHz ME 10 MHz normal VDD limits 20 MHz Device PIC16C7X Vpp range 4 0V to 6 0V PIC16C7XT Vpp range 4 0V to 6 0V Tape Reel PIC16LC7X Vpp range 2 5V to 6 0V PIC16LC7XT Vpp range 2 5V to 6 0V Tape Reel Temperature Range Frequency Range JW Devices are UV erasable and can be programmed to any device configuration JW Devices meet the electrical requirement of each oscillator type including LC devices Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds To determine if an errata sheet exists for a particular device please contact one of the following 1 The Microchip Website at www microchip com 2 Your local Microchip sales office see following page 3 The Microchip Corporate Literature Center U S FAX 602 786 7277 4 The Microchip s Bulletin Board via your local CompuServe number CompuServe membership NOT required Please specify which device revision of silicon and Data Sheet include Literature you are using For latest version information and upgrade kits for Microchip Developmen
215. age type and VDD Vss and MCLR pin locations are said to be pin compatible This allows these different devices to operate in the same socket Compatible devices may only requires minor software modification to allow proper operation in the application socket ex PIC16C56 and PIC16C61 devices Not all devices in the same package size are pin compatible for example the PIC16C62 is compatible with the PIC16C63 but not the PIC16C55 Pin compatibility does not mean that the devices offer the same features As an example the PIC16C54 is pin compatible with the PIC16C71 but does not have an A D converter weak pull ups on PORTB or interrupts TABLE E 1 PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508 PIC12C509 PIC12C671 PIC12C672 8 pin PIC16C154 PIC16CR154 PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 PIC16C52 PIC16C54 PIC16C54A PIC16CR54A PIC16C56 PIC16C58A PIC16CR58A PIC16C61 PIC16C554 PIC16C556 PIC16C558 PIC16C620 PIC16C621 PIC16C622 PIC16C641 PIC16C642 PIC16C661 PIC16C662 PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16F83 PIC16CR83 PIC16F84A PIC16CR84 18 pin 20 pin PIC16C55 PIC16C57 PIC16CR57B 28 pin PIC16CR62 PIC16C62A PIC16C63 PIC16CR63 PIC16C66 PIC16C72 PIC16C73A PIC16C76 28 pin PIC16CR64 PIC16C64A PIC16C65A PIC16CR65 PIC16C67 PIC16C74A PIC16C77 40 pin PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 40 pin
216. ailable including three timer counters two Cap ture Compare PWM modules and two serial ports The Synchronous Serial Port can be configured as either a 3 wire Serial Peripheral Interface SPI or the two wire Inter Integrated Circuit IC bus The Universal Syn chronous Asynchronous Receiver Transmitter USART is also known as the Serial Communications Interface or SCI Also a 5 channel high speed 8 bit A D is provided The 8 bit resolution is ideally suited for applications requiring low cost analog interface e g thermostat control pressure sensing etc The PIC16C74 74A devices have 192 bytes of RAM while the PIC16C77 has 368 bytes of RAM Each device has 33 I O pins In addition several peripheral features are available including three timer counters two Capture Compare PWM modules and two serial ports The Synchronous Serial Port can be configured as either a 3 wire Serial Peripheral Interface SPI or the two wire Inter Integrated Circuit I C bus The Uni versal Synchronous Asynchronous Receiver Transmit ter USART is also known as the Serial Communications Interface or SCI An 8 bit Parallel Slave Port is provided Also an 8 channel high speed 8 bit A D is provided The 8 bit resolution is ideally suited for applications requiring low cost analog inter face e g thermostat control pressure sensing etc The PIC16C7X family has special features to reduce external components thus reducing cost enhancing system reli
217. ains the result of the A D con version When the A D conversion is complete the result is loaded into the ADRES register the GO DONE bit ADCONO 2 is cleared and A D interrupt flag bit ADIF is set The block diagrams of the A D module are shown in Figure 13 3 After the A D module has been configured as desired the selected channel must be acquired before the con version is started The analog input channels must have their corresponding TRIS bits selected as an input To determine acquisition time see Section 13 1 After this acquisition time has elapsed the A D conver sion can be started The following steps should be fol lowed for doing an A D conversion 1 Configure the A D module Configure analog pins voltage reference and digital UO ADCON1 Select A D input channel ADCONO Select A D conversion clock ADCONO Turn on A D module ADCONO 2 Configure A D interrupt if desired Clear ADIF bit Set ADIE bit Set GIE bit FIGURE 13 3 A D BLOCK DIAGRAM VIN BO PIC16C7X Wait the required acquisition time Start conversion Set GO DONE bit ADCONO Wait for A D conversion to complete by either Polling for the GO DONE bit to be cleared OR Waiting for the A D interrupt Read A D Result register ADRES clear bit ADIF if required For next conversion go to step 1 or step 2 as required The A D conversion time per bit is defined as TAD A minimum wait of 2TAD is required be
218. alue 20 or Tcv 40 2 4 256 N 45 TtiH T1CKI High Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 46 TOL T1CKI Low Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 47 TtiP T1CKI input period Synchronous PIC16C7X Greater of ns N prescale value 30 oR Tcv 40 1 2 4 8 N PIC16LC7X Greater of N prescale value 50 or Tcv 40 1 2 4 8 N Asynchronous PIC16C7X 60 ns PIC16LC7X 100 ns Ft1 Timer1 oscillator input frequency range DC 200 kHz oscillator enabled by setting bit TT OSCEN 48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc 7Tosc These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 229 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 7 CAPTURE COMPARE PWM TIMINGS CCP1 AND CCP2 RC1 T1OSI CCP2 and RC2 CCP1 Capture Mode RC1 T1OSI CCP2 a
219. amples FIGURE 12 5 RX PIN SAMPLING SCHEME BRGH 1 PIC16C73 73A 74 74A Start Bit baud clk _ Baud clk for all but start bit First falling edge after RX pin goes low K xAck Second rising edge 2 Q2 Q4 clk Ay Samples DS30390E page 104 1997 Microchip Technology Inc PIC16C7X FIGURE 12 6 RX PIN SAMPLING SCHEME BRGH 0 OR BRGH 1 PIC16C76 77 x EN Start bit Bito R RC7 RX DT pin Baud CLK for all but start bit baud CLK x16 CLK 12 13 14 15 Samples 1997 Microchip Technology Inc DS30390E page 105 PIC16C7X 12 2 USART Asynchronous Mode Applicable Devices 72 73 73A 74 74A 76 77 In this mode the USART uses standard nonreturn to zero NRZ format one start bit eight or nine data bits and one stop bit The most common data format is 8 bits An on chip dedicated 8 bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator The USART transmits and receives the LSb first The USART s transmitter and receiver are functionally independent but use the same data form
220. ap ture or the 16 bit Compare and must be synchronized to the device 6 3 Timer2 Overview Applicable Devices 72 73 73A 74 74A 76 77 Timer2 is an 8 bit timer with a programmable prescaler and postscaler as well as an 8 bit period register PR2 Timer2 can be used with the CCP1 module in PWM mode as well as the Baud Rate Generator for the Synchronous Serial Port SSP The prescaler option allows Timer2 to increment at the following rates 1 1 1 4 1 16 The postscaler allows the TMR2 register to match the period register PR2 a programmable number of times before generating an interrupt The postscaler can be programmed from 1 1 to 1 16 inclusive 6 4 CCP Overview Applicable Devices 72 73 73A 74 74A 76 77 The CCP module s can operate in one of these three modes 16 bit capture 16 bit compare or up to 10 bit Pulse Width Modulation PWM Capture mode captures the 16 bit value of TMR1 into the CCPRxH CCPRxL register pair The capture event can be programmed for either the falling edge rising edge fourth rising edge or the sixteenth rising edge of the CCPx pin Compare mode compares the TMR1H TMR1L register pair to the CCPRxH CCPRxL register pair When a match occurs an interrupt can be generated and the output pin CCPx can be forced to given state High or Low TMR1 can be reset CCP1 or TMR1 reset and start A D conversion CCP2 This depends on the con trol bits CCPXM3 CCPXMO PWM mode compares the TMR2 reg
221. ap W TEMP into W 1997 Microchip Technology Inc DS30390E page 143 PIC16C7X 14 7 Watchdog Timer WDT Applicable Devices 72 73 73A 74 74A 76 77 The Watchdog Timer is as a free running on chip RC oscillator which does not require any external compo nents This RC oscillator is separate from the RC oscil lator of the OSC1 CLKIN pin That means that the WDT will run even if the clock on the OSC1 CLKIN and OSC2 CLKOUT pins of the device has been stopped for example by execution of a SLEEP instruction Dur ing normal operation a WDT time out generates a device RESET Watchdog Timer Reset If the device is in SLEEP mode a WDT time out causes the device to wake up and continue with normal operation Watch dog Timer Wake up The WDT can be permanently disabled by clearing configuration bit WDTE Section 14 1 14 7 1 WDT PERIOD The WDT has a nominal time out period of 18 ms with no prescaler The time out periods vary with tempera ture VDD and process variations from part to part see DC specs If longer time out periods are desired a prescaler with a division ratio of up to 1 128 can be assigned to the WDT under software control by writing to the OPTION register Thus time out periods up to 2 3 seconds can be realized The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT and prevent it from timing out and generating a devic
222. as described in DC spec Section 17 1 and Section 17 2 Param Characteristic Sym Min Typ Max Units Conditions No Input Low Voltage I O ports VIL D030 with TTL buffer Vss 0 15VDD V For entire VDD range D030A Vss 0 8V V 4 5 lt Vbpp lt 5 5V D031 with Schmitt Trigger buffer Vss 02VDD V D032 MCLR OSC1 in RC mode Vss 0 2VoD V D033 OSC1 in XT HS and LP Vss 0 8VDD V Note Input High Voltage I O ports VIH D040 with TTL buffer 2 0 VDD V 4 5 lt Vpp lt 5 5V D040A 0 25VDD VDD V For entire VDD range 0 8V D041 with Schmitt Trigger buffer 0 8VDD VDD V For entire VDD range D042 MCLR 0 8VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note D043 OSC1 in RC mode 0 9VDD VDD V D070 PORTB weak pull up current IPURB 50 250 400 uA VDD 5V VPIN VSS Input Leakage Current Notes 2 3 D060 UO ports liL 1 HA Vss VPIN lt VDD Pin at hi impedance D061 MCLR RA4 TOCKI uA Vss VPIN lt VDD D063 OSC1 5 HA Vss VPIN VDD XT HS and LP osc configuration Output Low Voltage D080 UO ports VoL 0 6 V loL 8 5 mA VDD 4 5V 40 C to 85 C D080A 0 6 V loL 7 0 mA VDD 4 5V 40 C to 125 C D083 OSC2 CLKOUT RC osc config 0 6 V lo 1 6 mA VDD 4 5V 40 C to 85 C D083A 0 6 V oi 1 2 mA VDD 4 5V 40 C to 125 C These parameters are characterized but not tested T Data in
223. aster Mode 1 Input data sampled at end of data output time 0 Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6 CKE SPI Clock Edge Select Figure 11 11 Figure 11 12 and Figure 11 13 CKP 0 1 Data transmitted on rising edge of SCK 0 Data transmitted on falling edge of SCK CKP 1 1 Data transmitted on falling edge of SCK 0 Data transmitted on rising edge of SCK bit 5 D A Data Address bit I C mode only 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address bit 4 P Stop bit IC mode only This bit is cleared when the SSP module is disabled or when the Start bit is detected last SSPEN is cleared 1 Indicates that a stop bit has been detected last this bit is 0 on RESET 0 Stop bit was not detected last bit 3 S Start bit IC mode only This bit is cleared when the SSP module is disabled or when the Stop bit is detected last SSPEN is cleared 1 Indicates that a start bit has been detected last this bit is 0 on RESET 0 Start bit was not detected last bit 2 R W Read Write bit information FC mode only This bit holds the R W bit information following the last address match This bit is only valid from the address match to the next start bit stop bit or ACK bit 1 Read 0 Write bit 1 UA Update Address 10 bit C mode only 1 Indicates
224. at and baud rate The baud rate generator produces a clock either x16 or x64 of the bit shift rate depending on bit BRGH TXSTA lt 2 gt Parity is not supported by the hardware but can be implemented in software and stored as the ninth data bit Asynchronous mode is stopped during SLEEP Asynchronous mode is selected by clearing bit SYNC TXSTA lt 4 gt The USART Asynchronous module consists of the fol lowing important elements Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver 12 2 1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 12 7 The heart of the transmitter is the transmit serial shift register TSR The shift register obtains its data from the read write transmit buffer TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the STOP bit has been transmitted from the previous load As soon as the STOP bit is transmitted the TSR is loaded with new data from the TXREG register if available Once the TXREG register transfers the data to the TSR register occurs in one Tcv the TXREG register is empty and FIGURE 12 7 USART TRANSMIT BLOCK DIAGRAM Data Bus flag bit TXIF PIR1 lt 4 gt is set This interrupt can be enabled disabled by setting clearing enable bit TXIE PIE1 lt 4 gt Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be c
225. ates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address bit 4 P Stop bit IC mode only This bit is cleared when the SSP module is disabled SSPEN is cleared 1 Indicates that a stop bit has been detected last this bit is 0 on RESET 0 Stop bit was not detected last bit 3 S Start bit lC mode only This bit is cleared when the SSP module is disabled SSPEN is cleared 1 Indicates that a start bit has been detected last this bit is 0 on RESET 0 Start bit was not detected last bit 2 R W Read Write bit information C mode only This bit holds the R W bit information following the last address match This bit is valid from the address match to the next start bit stop bit or ACK bit 1 Read 0 Write bit 1 UA Update Address 10 bit EC mode only 1 Indicates that the user needs to update the address in the SSPADD register 0 Address does not need to be updated bit 0 BF Buffer Full Status bit Receive SPI and C modes 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty Transmit I2C mode only 1 Transmit in progress SSPBUF is full 0 Transmit complete SSPBUF is empty DS30390E page 78 1997 Microchip Technology Inc Applicable Devices P C 1 6C7X 72 73 73A 74 74A 76 77 FIGURE 11 2 SSPCON SYNC SERIAL PORT CONTROL REGISTER ADDRESS 14h RW 0 RW 0 R W 0 R W 0 RWO
226. ax Freq 200 kHz max The shaded sections indicate oscillator selections which are tested for functionality but not for MIN MAX specifications It is recommended that the user select the device type that ensures the specifications required DS30390E page 220 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20 1 DC Characteristics PIC16C76 77 04 Commercial Industrial Extended PIC16C76 77 10 Commercial Industrial Extended PIC16C76 77 20 Commercial Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA 4125 C for extended DE CHARACTERISTICS 40 C lt TA lt 85 C for industrial and 0 C TA 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 4 0 6 0 V XT RC and LP osc configuration D001A 4 5 5 5 V HS osc configuration D002 RAM Data Retention VDR 1 5 V Voltage Note 1 D003 VDD start voltage to VPOR S Vss V See section on Power on Reset for details ensure internal Power on Reset signal D004 VDD rise rate to ensure SvDD 0 05 V ms See section on Power on Reset for details internal Power on Reset signal D005 Brown out Reset Voltage BVDD 3 7 40 43 V BODEN bit in configuration word enabled 3 7 40 44 V Extended Range Only D010 Supply Current Note 2 5 IDD 27 5 mA XT RC osc configuration
227. be desirable depending on the operate as a receiver the SDO pin can be configured as application an input This disables transmissions from the SDO The SDI can always be left as an input SDI function since it cannot create a bus conflict FIGURE 11 11 SPI MODE TIMING MASTER MODE PIC16C76 77 SCK CKP 0 CKE 0 SCK CKP 0 CKE 1 SCK CKP 1 CKE 0 SCK CKP 1 CKE 1 SDO Ech ou X mi bis X bi X bits X bi X bit X TE OX Ss sO bit7 Ee A Cp dE Eq bit7 FIGURE 11 12 SPI MODE TIMING SLAVE MODE WITH CKE 0 PIC16C76 77 SS optional SCK CKP 0 SCK CKP 1 SDO E ou X ml mi bite X bis X bt X bu X bio X SDI SMP 0 i 4 E 4 1997 Microchip Technology Inc DS30390E page 87 D l C 1 6C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 11 13 SPI MODE TIMING SLAVE MODE WITH CKE 1 PIC16C76 77 SS not optional SCK CKP 0 SCK CKP 1 SDI SMP 0 2 gt S gt SSPIF TABLE 11 2 REGISTERS ASSOCIATED WITH SPI OPERATION PIC16C76 77 Val
228. bis specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode 300 ns 400 kHz mode 20 0 1Cb 300 ns Cbis specified to be from 10 to 400 pF 90 TSU STA START condition 100 kHz mode 4 7 us Only relevant for repeated setup time 400 kHz mode 0 6 Z uS START condition 91 THD STA START condition hold 100 kHz mode 4 0 us After this period the first clock time 400 kHz mode 0 6 SS us pulse is generated 106 THD DAT Data input hold time 100 kHz mode 0 ns 400 kHz mode 0 0 9 us 107 TSU DAT Data input setup time 100 kHz mode 250 ns Note 2 400 kHz mode 100 Ce ns 92 TSU STO STOP condition setup 100 kHz mode 4 7 us time 400 KHz mode 0 6 us 109 TAA Output valid from 100 kHz mode 3500 ns Note 1 clock 400 kHz mode ns 110 TBUF Bus free time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 1 3 Z us before a new transmission can start Cb Bus capacitive loading 400 pF Note 1 Asatransmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of START or STOP conditions 2 Afast mode 400 kHz I C bus device can be used in a standard mode 100 kHz 2C bus system but the requirement tsu DAT gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal i
229. bit X 25042 225 baud rate generator The SPBRG register controls the Ss Calculated Baud Rate 16000000 64 25 1 period of a free running 8 bit timer In asynchronous Rp ta HABT mode bit BRGH TXSTA 2 also controls the baud 9615 rate In synchronous mode bit BRGH is ignored Error Calculated Baud Rate Desired Baud Rate Table 12 1 shows the formula for computation of the Desired Baud Rate baud rate for different USART modes which only apply z 9615 9600 9600 in master mode internal clock SE Given the desired baud rate and Fosc the nearest inte ger value for the SPBRG register can be calculated using the formula in Table 12 1 From this the error in It may be advantageous to use the high baud rate baud rate can be determined BRGH 1 even for slower baud clocks This is because the Fosc 16 X 1 equation can reduce the Example 12 1 shows the calculation of the baud rate baud rate error in some cases error for the following conditions Fosc 16 MHz Note For the PIC16C73 73A 74 74A the asyn Desired Baud Rate 9600 chronous high speed mode BRGH 1 BRGH 0 may experience a high rate of receive SYNC 0 errors It is recommended that BRGH 0 If you desire a higher baud rate than BRGH 0 can support refer to the device errata for additional information or use the PIC16C76 77 Writing a new value to the SPBRG register causes the BRG timer to be reset or cleared this ens
230. buffer Vss 0 15VbpD V For entire VDD range D030A Vss 0 8V 4 5V lt VDD lt 5 5V D031 with Schmitt Trigger buffer Vss O2VDD V D032 MCLR OSC1 in RC mode Vss 0 2VDD V D033 OSC1 in XT HS and LP Vss 0 8VDD V Note1 Input High Voltage I O ports VIH D040 with TTL buffer 2 0 VDD V 4 5V lt VDD lt 5 5V D040A 0 25VDD VDD V For entire VDD range 0 8V D041 with Schmitt Trigger buffer 0 8VDD VDD V For entire VDD range D042 MCLR 0 8VDD VDD V D042A OSC1 XT HS and LP 0 7VDD VDD V Note D043 OSC1 in RC mode 0 9VDD VDD V D070 PORTB weak pull up current IPURB 50 250 400 uA VDD 5V VPIN VSS Input Leakage Current Notes 2 3 D060 WO ports liL 1 uA Vss VPIN lt VDD Pin at hi imped ance D061 MCLR RA4 TOCKI uA Vss lt VPIN lt VDD D063 OSC1 5 uA Vss VPIN VDD XT HS and LP osc configuration Output Low Voltage D080 WO ports VoL 0 6 V Jos 8 5 mA VDD 4 5V 40 C to 85 C D080A 0 6 V oi 7 0 mA VDD 4 5V 40 C to 125 C D083 OSC2 CLKOUT RC osc config 0 6 V loL 1 6 mA VDD 4 5V 40 C to 85 C D083A 0 6 V Jos 1 2 mA VDD 4 5V 40 C to 125 C These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN
231. but with all EPROM locations and configuration options already programmed by the factory Certain code and prototype verification procedures apply before produc tion shipments are available Please contact your local Microchip Technology sales office for more details 2 4 Serialized Quick Turnaround Production SQTPS Devices Microchip offers a unique programming service where a few user defined locations in each device are pro grammed with different serial numbers The serial num bers may be random pseudo random or sequential Serial programming allows each device to have a unique number which can serve as an entry code password or ID number 1997 Microchip Technology Inc DS30390E page 7 PIC16C7X NOTES DS30390E page 8 1997 Microchip Technology Inc PIC16C7X 3 0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features com monly found in RISC microprocessors To begin with the PIC16CXX uses a Harvard architecture in which program and data are accessed from separate memo ries using separate buses This improves bandwidth over traditional von Neumann architecture in which pro gram and data are fetched from the same memory using the same bus Separating program and data buses further allows instructions to be sized differently than the 8 bit wide data word Instruction opcodes are 14 bits wide making it possible to have all sing
232. by the pin DS30390E page 224 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20 4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 TCC ST IC specifications only 2 TppS 4 Ts EC specifications only T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc OSC ck CLKOUT rd RD cs CS rw RD or WR di SDI SC SCK do SDO SS SS dt Data in tO TOCKI io UO port ti T1CKI mc MCLR Wr WR Uppercase letters and their meanings F Fall P Period H High R Rise Invalid Hi impedance V Valid L Low Z Hi impedance PC only AA output access High High BUF Bus free Low Low Tcc sr lC specifications only CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 20 1 LOAD CONDITIONS Load condition 1 Load condition 2 VDD 2 o 4640 50 pF forall pins except OSC2 but including PORTD and PORTE outputs as ports 15pF for OSC2 output Note PORTD and PORTE are not implemented on the PIC16C76 1997 Microchip Technology Inc DS30390E page 225 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20 5 Timing Diagrams and Specifications FIGURE 20 2 EXTERNAL CLOCK TIMING Q4 Q1 CLKOUT TABLE 20 2 EXTERNAL CLOCK TIMING REQUI
233. ce only and are not tested S This specification ensured by design 1 ADRES register may be read on the following Tcy cycle See Section 13 1 for min conditions DS30390E page 200 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19 0 ELECTRICAL CHARACTERISTICS FOR PIC16C73A 74A Absolute Maximum Ratings T Ambient temperature trder bias cie te cm ioter eine draft 55 to 125 C Storage temperature 65 C to 150 C 0 3V to VDD 0 3V Voltage on any pin with respect to VSs except VDD MCLR and RA4 Voltage on VDD with respect to VSS 0 3 to 7 5V Voltage on MCLR with respect to VSS Note 2 nennen 0 to 14V Voltage on RA4 with respecto VSS eere ce ede ec anode tese a ex dc tbe edd de descen 0 to 14V Total power dissipation Notoe 1 rerit tenet iere teni trt ars r tre MR eR REL ent es HERRERA ee UNE HER Peer entr Re 1 0W Maximum current out of VSS pin onec rer eia edion Ea aade caue e eurer sve estara nee de rings 300 mA Maximum current into VDD IP issn chase RUE phe edet ete Ra ne inner eae 250 mA Input clamp current liK VI 0 or VI gt VDD ire 20 mA Output clamp current IOK VO lt 0 or VO gt VDD eee 20 mA Maximum output current sunk by any I O pin Maximum output current sourced by any I O pin ne
234. ces 2 Packages 28 pin DIP 300 mil SOIC SSOP 1997 Microchip Technology Inc DS30390E page 265 PIC16C 7X E 3 PIC16C15X Family of Devices PIC16C154 PIC16CR154 PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 Maximum Frequency 20 20 of Operation MHz EPROM Program Memory 2K x12 words Memory ROM Program Memory 2K x12 words RAM Data Memory bytes 73 73 NOS OI Timer Module s TMRO TMRO I O Pins 12 12 Voltage Range Volts 3 0 5 5 2 5 5 5 ATTI Number of Instructions 33 33 Packages 18 pin DIP 18 pin DIP 18 pin DIP 18 pin DIP 18 pin DIP 18 pin DIP SOIC SOIC SOIC SOIC SOIC SOIC 20 pin SSOP 20 pin SSOP 20 pin SSOP 20 pin SSOP 20 pin SSOP 20 pin SSOP All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capability E 4 PIC16C5X Family of Devices PIC16C52 PIC16C54 PIC16C54A PIC16CR54A PIC16C55 PIC16C56 Maximum Frequency 4 20 20 20 20 20 of Operation MHz EPROM Program Memory 384 512 512 512 1K x12 words ROM Program Memory 512 x12 words RAM Data Memory bytes 25 25 Mz s OIEN Timer Module s TMRO TMRO TMRO TMRO TMRO TMRO UO Pins 12 12 12 12 20 12 Voltage Range Volts 2 5 6 25 2 5 6 25 2 0 6 25 2 0 6 25 2 5 6 25 2 5 6 25 Number of Instruct
235. cify the operation of the instruction The PIC16CXX instruction set summary in Table 15 2 lists byte oriented bit ori ented and literal and control operations Table 15 1 shows the opcode field descriptions For byte oriented instructions f represents a file reg ister designator and d represents a destination desig nator The file register designator specifies which file register is to be used by the instruction The destination designator specifies where the result of the operation is to be placed If d is zero the result is placed in the W register If d is one the result is placed in the file register specified in the instruction For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation while f represents the number of the file in which the bit is located For literal and control operations k represents an eight or eleven bit constant or literal value TABLE 15 1 OPCODE FIELD DESCRIPTIONS Field Description t Register file address 0x00 to Ox7F w Working register accumulator b Bn address within an 8 bit file register k x Literal field constant data or label Don t care location 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools a Destination select d 0 store result in W d 1 store result in file register f
236. code if upgrading to the PIC16C76 77 DS30390E page 22 1997 Microchip Technology Inc PIC16C7X 4 2 2 The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device These registers are implemented as static RAM SPECIAL FUNCTION REGISTERS The special function registers can be classified into two sets core and peripheral Those registers associated with the core functions are described in this section and those related to the operation of the peripheral fea tures are described in the section of that peripheral fea ture TABLE 4 1 PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 3 Bank 0 oon INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 01h TMRO TimerO modules register XXXX XXXX uuuu uuuu 02h PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP 4 RP14 RPO TO PD Z DC G 0001 1xxx 0004 quuu Dan FSR Indirect data memory address pointer XXXX xxxx uuuu uuuu 05h PORTA PORTA Data Latch when written PORTA pins when read 0x 0000 0u 0000 06h PORTB PORTB Data Latch when writte
237. configuration Fosc 4 MHz VDD 5 5V Note 4 D013 13 5 30 mA HS osc configuration Fosc 20 MHz VDD 5 5V D020 Power down Current IPD 10 5 42 pA VDD 4 0V WDT enabled 40 C to 85 C D021 Note 3 5 1 5 21 uA VDD 4 0V WDT disabled 0 C to 70 C D021A 1 5 24 uA VDD 4 0V WDT disabled 40 C to 85 C These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as UO pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all UO pins tristated pulled to VoD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode does not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VOD and Vss 4 For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula Ir Vbb 2Rext mA with Rext in kOhm 5 Timer1 oscillat
238. cro controllers The compiler provides powerful integration capabilities and ease of use not found with other compilers For easier source level debugging the compiler pro vides symbol information that is compatible with the MPLAB IDE memory display PICMASTER emulator software versions 1 13 and later 16 13 Fuzzy Logic Development System fuzzyTECH MP fuzzyTECH MP fuzzy logic development tool is avail able in two versions a low cost introductory version MP Explorer for designers to gain a comprehensive working knowledge of fuzzy logic system design and a full featured version fuzzyTECH MP edition for imple menting more complex systems Both versions include Microchip s fuzzyLAB demon stration board for hands on experience with fuzzy logic Systems implementation 16 14 MP DriveWay Application Code Generator MP DriveWay is an easy to use Windows based Appli cation Code Generator With MP DriveWay you can visually configure all the peripherals in a PIC16 17 device and with a click of the mouse generate all the initialization and many functional code modules in C language The output is fully compatible with Micro chips MPLAB C C compiler The code produced is highly modular and allows easy integration of your own code MP DriveWay is intelligent enough to maintain your code through subsequent code generation 16 15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designers Kit
239. crochip Technology Inc DS30390E page 275 PIC16C7X PICSTART Low Cost Development System 163 PIET Register errore nre AE 29 33 PIE2 Register Pin Compatible Devices sessies 271 Pin Functions MGLR VEP eei tpe ate rage rs 13 14 15 OSC1 CLKIN AA 13 14 15 QSO2 CLKOUT eee o 13 14 15 RAO ANO RAT ANT ie 13 14 15 RAD AND 3 cce tee Nee cete de etg dede 13 14 15 RAS ANS VREF eeeeeeee 18 14 15 RAA TOGK sin torte 18 14 15 RAb ANA SS sienne 13 14 15 RHBO INIT eerte 18 14 15 RB Iiae e nian 18 14 15 RBZ RS STE 13 14 15 RB3 EE 13 14 15 RBA E 13 14 15 EE 13 14 15 RBO ne Mist he EE 13 14 15 HB RER Re sos das cass nn ue 13 14 15 RCO T1OSO T1CKI sss 13 14 16 RO1 TAOSI a icem eene eec 13 RC1 T1OSI CCP2 sees 14 16 RC2 CCP1 13 14 16 RCS3 SGK SGL ss ntt ene 13 14 16 RCA SDI SDA essen 13 14 16 RC5 SDO 18 14 16 PGB M 13 RC6 TX CK RC7 RG7 RXIBT eie oce 14 16 99 114 RDO PSPO RD1 PSP1 RD2 PSP2 RD3 PSP3 RD4 PSP4 RD5 PSP5 RD6 PSP6 RD7 PSP7 ids REQO RD AND 354 nhe eto ere arian tin 16 RETANR ANO cernentes 16 RE2 CS ANT nn 16 E EE 80 82 Kiop M PH EE 80 82 RI WEEN 80 82 ER 80 82 KENE 13 14 16 MSS ag osea e Bee ane 13 14 16 Pinout Descriptions Ren LEE 13 PIC16C73 14 PIC16C73A 14 PIC16C74 ENK PIGT
240. ction will clear the prescaler along with the Watchdog Timer The pres caler is not readable or writable available which is mutually exclusively shared between Note Writing to TMRO when the prescaler is the TimerO module and the Watchdog Timer Thus a assigned to TimerO will clear the prescaler prescaler assignment for the TimerO module means count but will not change the prescaler that there is no prescaler for the Watchdog Timer and assignment vice versa FIGURE 7 6 BLOCK DIAGRAM OF THE TIMERO WDT PRESCALER CLKOUT Fosc 4 Data Bus E RA4 TOCKI pin 1 m TMRO reg WW Set flag bit TOIF on Overflow Watchdog Timer WDT Enable bit WDT Time out Note TOCS TOSE PSA PS2 PS0 are OPTION lt 5 0 gt DS30390E page 62 1997 Microchip Technology Inc PIC16C7X 7 8 1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con trol i e it execution can be changed on the fly during program Note To avoid an unintended device RESET the following instruction sequence shown in Example 7 1 must be executed when changing the prescaler assignment from TimerO to the WDT This sequence must be followed even if the WDT is disabled EXAMPLE 7 1 CHANGING PRESCALER TIMERO WDT 1 BSF STATUS RPO Bank 1 Lines 2 a
241. ctually incremented Figure 7 5 shows the delay from the external clock edge to the timer incrementing FIGURE 7 5 TIMERO TIMING WITH EXTERNAL CLOCK Q11 Q21 Q3 Q4 External Clock Inpyt or Prescaler output 2 External Clock Prescaler Output after sampling Increment TimerO Q4 Q11 Q2 Q3I Q4 Q11 Q21 Q3I Q4 Q11 Q2 Q3I Q4 Small pulse X misses sampling TimerO TO 1 Note 1 Delay from clock input change to TimerO increment is 3Tosc to 7Tosc Duration of Q Tosc Therefore the error in measuring the interval between two edges on Timer0 input 4Tosc max 2 External clock if no prescaler selected Prescaler output otherwise 3 The arrows indicate the points in time where sampling occurs 1997 Microchip Technology Inc DS30390E page 61 PIC16C7X 7 3 Prescaler The PSA and PS2 PS0 bits OPTION lt 3 0 gt determine Applicable Devices the prescaler assignment and prescale ratio 72 73 73A 74 74A 76 77 An 8 bit counter is available as a prescaler for the TimerO module or as a postscaler for the Watchdog Timer respectively Figure 7 6 For simplicity this counter is being referred to as prescaler throughout this data sheet Note that there is only one prescaler When assigned to the TimerO module all instructions writing to the TMRO register e g CLRF 1 MOVWF 1 BSF 1 x etc will clear the prescaler When assigned to WDT a CLRWDT instru
242. current IOK VO lt 0 or VO gt VDD eee 20 mA Maximum output current sunk by any HO pin iii Maximum output current sourced by any UO pin Maximum current sunk by PORTA PORTB and PORTE combined Note 3 Maximum current sourced by PORTA PORTB and PORTE combined Note 3 Maximum current sunk by PORTC and PORTD combined Note 3 Maximum current sourced by PORTC and PORTD combined Note 3 Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Y 10H X VDD VOH x loH X Vol x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss PORTD and PORTE are not implemented on the PIC16C73 Note 3 T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability TABLE 18 1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION COMMERCIAL DEVICES PIC16C73 04 PIC16C7
243. current is the additional current consumed when this peripheral is enabled This current should be added to the base IDD or IPD measurement DS30390E page 222 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20 8 DC Characteristics PIC16C76 77 04 Commercial Industrial Extended PIC16C76 77 10 Commercial Industrial Extended PIC16C76 77 20 Commercial Industrial Extended PIC16LC76 77 04 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended 40 C lt Ta 85 C for industrial and DC CHARACTERISTICS 0 C TA lt 70 C for commercial Operating voltage VDD range as described in DC spec Section 20 1 and Section 20 2 Characteristic Sym Min Typ Max Units Conditions t Input Low Voltage I O ports with TTL buffer 0 15VDD For entire VDD range 0 8V 4 5V lt VDD 5 5V with Schmitt Trigger buffer 0 2VDD MCLR OSC1 in RC mode 0 2VDD OSC1 in XT HS and LP 0 3VDD Input High Voltage IO ports with TTL buffer 2 0 4 5V lt VDD 5 5V 0 25VDD For entire VDD range 0 8V with Schmitt Trigger buffer 0 8VDD For entire VDD range MCLR 0 8VDD OSC1 XT HS and LP 0 7VDD Note1 OSC1 in RC mode 0 9VDD PORTB weak pull up current VDD 5V VPIN VSS Input Leakage Current Notes 2 3 D060 WO ports liL 1 uA Vss VPIN lt VDD Pin at hi i
244. d A acknowledge SDA low S Start Condition From slave to master P Stop Condition FIGURE 11 20 MASTER RECEIVER SEQUENCE For 7 bit address S Slave Address R WA Data A Data A P 1 read L data transferred n bytes acknowledge A master reads a slave immediately after the first byte A acknowledge SDA low S Start Condition From slave to master P Stop Condition FIGURE 11 21 COMBINED FORMAT read or write r n bytes acknowledge From master to slave A not acknowledge SDA high read For 10 bit address S Slave Address R W A1 Slave Address A2 First 7 bits Second byte write Data A Data e A master transmitter addresses a slave receiver with a 10 bit address For 10 bit address S Slave Address R W A1 Slave Address First 7 bits Second byte write SriSlave Address R W A3 DatajA Data A P First 7 bits y A master transmitter addresses a slave receiver with a 10 bit address Slave Address R W A Data A A Sr Slave Address R W A Data A A P read Sr repeated write Start Condition Direction of transfer may change at this point Transfer direction of data and acknowledgment bits depends on R W bits
245. d All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current con sumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the Max cycle time limit is DC no clock for all devices DS30390E page 226 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 3 CLKOUT AND UO TIMING CLKOUT UO Pin input UO Pin output old value new value Note Refer to Figure 20 1 for load conditions TABLE 20 3 CLKOUT AND I O TIMING REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 10 TosH2ckL OSC1T to CLKOUTL 75 200 ns Note 1 11 TosH2ckH OSC1T to CLKOUTT 75 200 ns Note 1 TckR CLKOUT rise time 35 100 ns Note 1 TckF CLKOUT fall time 35 100 ns Note 1 TckL2ioV CLKOUT 1 to Port out valid 0 5Tcy 20 ns Note 1 TioV2ckH Port in valid before CLKOUT T ns Note 1 TckH2iol Port in hold after CLKOUT T ns Note 1 TosH2ioV OSC1T Q1 cycle to 50 150 ns Port out valid TosH2iol OSC11 Q2 cycl
246. d u a x 0 0000 0 0000 u uuuu unknown unimplemented bit read as 0 q value depends on condition Note 1 One or more bits in INTCON PIR1 and or PIR2 will be affected to cause wake up 2 When the wake up is due to an interrupt and the GIE bit is set the PC is loaded with the interrupt vector 0004h 3 See Table 14 7 for reset value for specific condition DS30390E page 136 1997 Microchip Technology Inc PIC16C7X TABLE 14 8 INITIALIZATION CONDITIONS FOR ALL REGISTERS Cont d Register Applicable Devices Power on Reset MCLR Resets Wake up via WDT Brown out Reset WDT Reset or Interrupt INTCON 72 73 73A 74 74A 76 77 0000 000x 0000 000u uuuu uuuuU 72 73 73A 74 74A 76 77 0 0000 0 0000 u uuuu PIR1 72 73 73A 74 74A 76 77 000 0000 000 0000 uuu uuuu 72 73 78A 74 74A 76 77 0000 0000 0000 0000 dutu ett PIR2 72 73 73A 74 74A 76 77 o up m SOA PR SR SZ BAU TMR1L 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu TMR1H 72 73 73A 74 74A 76 77 XXXX XXXX uuuu uuuu uuuu uuuu T1CON 72 73 73A 74 74A 76 77 00 0000 uu uuuu uu uuuu TMR2 72 73 73A 74 74A 76 77 0000 0000 0000 0000 uuuu uuuu T2CON 72 73 73A
247. ded Control Handbook Implementing Wake Up on Key Stroke AN552 Note Forthe PIC16C73 74 if a change on the I O pin should occur when the read opera tion is being executed start of the Q2 cycle then interrupt flag bit RBIF may not get set The interrupt on change feature is recommended for wake up on key depression operation and operations where PORTB is only used for the interrupt on change feature Polling of PORTB is not recommended while using the interrupt on change feature 1997 Microchip Technology Inc DS30390E page 45 PIC16C7X FIGURE 5 4 RBPUO BLOCK DIAGRAM OF FIGURE 5 5 BLOCK DIAGRAM OF RB7 RB4 PINS PIC16C73 74 Data bus WR Port WR TRIS Data Latch RD TRIS RD Port RB7 RB4 PINS PIC16C72 73A 74A 76 77 REPU Set a a From other RB7 RB4 pins CU Data Latch D Q Data bus WR Port CK TRIS Latch 6 D Q WRTRIS bCK NX Buffer Buffer RD TRIS RD Port Set dH RB7 RB6 in serial programming mode MER KE From other RB7 RB4 pins Note 1 1 O pins have diode protection to VDD and Vss 2 To enable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit OPTION lt 7 gt RB7 RB6 in serial programming mode Note 1 UO pins have diode prot
248. ded and a NOP is executed instead making this a 2TCY instruction 1 1 2 Q1 Q2 Q3 Q4 Decode Read Process No register f data Operation 2nd Cycle Q1 Q2 Q3 Q4 No No No No Operation Operation Operation Operation HERE BTFSC FALSE GOTO TRUE s FLAG 1 PROCESS_CODE Before Instruction PC After Instruction if FLAG lt 1 gt 0 PC address TRUE if FLAG lt 1 gt 1 PC address FALSE address HERE DS30390E page 150 1997 Microchip Technology Inc PIC16C7X BTFSS Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity If Skip Example Bit Test f Skip if Set label BTFSS fb 0 lt f lt 127 0O lt b lt 7 skip if f lt b gt 1 None 01 11bb bfff ffff If bit b in register f is 0 then the next instruction is executed If bit b is 1 then the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction 1 1 2 Q1 Q2 Q3 Q4 Decode Read Process No register f data Operation 2nd Cycle Q1 Q2 Q3 Q4 No No No No Operation Operation Operation Operation HERE BTFSC FLAG 1 FALSE GOTO PROCESS CODE TRUE Before Instruction PC After Instruction if FLAG lt 1 gt 0 PC address FALSE if FLAG lt 1 gt 1 PC address TRUE address HERE CALL Syntax Operands Operation Status
249. dfff EEFE Add the contents of the W register with register f If d is O the result is stored in the W register If d is 1 the result is stored back in register f 1 1 Q1 Q2 Q3 Q4 Write to destination Decode Read Process register data T ADDWF FSR 0 Before Instruction W 0x17 FSR 0xC2 After Instruction W 0xD9 FSR 0xC2 ANDLW AND Literal with W Syntax label ANDLW k Operands 0 lt k lt 255 Operation W AND k gt W Status Affected Z Encoding 11 1001 kkkk kkkk Description The contents of W register are AND ed with the eight bit literal k The result is placed in the W register Words 1 Cycles 1 Q Cycle Activity Example ANDWF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data W ANDLW Ox5F Before Instruction W 0x43 After Instruction W 0x03 AND W with f label ANDWF fd O lt f lt 127 de 0 1 W AND f destination Z 00 0101 dfff ffff AND the W register with register f If d is 0 the result is stored in the W regis ter If d is 1 the result is stored back in register f 1 1 Q1 Q2 Q3 Q4 Write to destination Decode Read Process register data T ANDWF FSR 1 Before Instruction
250. ds the data to the bus Receiver The device that receives the data from the bus Master The device which initiates the transfer generates the clock and terminates the transfer Slave The device addressed by a master Multi master More than one master device in a system These masters can attempt to control the bus at the same time without corrupting the message Arbitration Procedure that ensures that only one of the master devices will control the bus This ensure that the transfer data does not get corrupted Synchronization Procedure where the clock signals of two or more devices are synchronized 1997 Microchip Technology Inc DS30390E page 89 D C 1 6C7X Applicable Devices 72 73 73A 74 74A176 77 11 4 2 ADDRESSING IC DEVICES FIGURE 11 17 SLAVE RECEIVER There are two address formats The simplest is the ACKNOWLEDGE 7 bit address format with a R W bit Figure 11 15 The Data more complex is the 10 bit address with a RW bit Toy L X X 7 Figure 11 16 For 10 bit address format two bytes Data aie must be transmitted with the first five bits specifying this Output by EY to be a 10 bit address Receiver SCL from acknowledge FIGURE 11 15 7 BIT ADDRESS FORMAT Clock Pulse for Condition Acknowledgment Slave address If the master is receiving the data master receiver it generates an acknowledge signal
251. due to internal phase clock Tosc synchronization Also there is a delay in the actual incrementing of TMR1 after syn chronization When the prescaler is 1 1 the external clock input is the same as the prescaler output The synchronization of T1CKI with the internal phase clocks is accom plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Therefore it is necessary for T1CKI to be high for at least 2Tosc and a small RC delay of 20 ns and low for at least 2Tosc and a small RC delay of 20 ns Refer to the appropri ate electrical specifications parameters 45 46 and 47 When a prescaler other than 1 1 is used the external clock input is divided by the asynchronous ripple counter type prescaler so that the prescaler output is symmetrical In order for the external clock to meet the sampling requirement the ripple counter must be taken into account Therefore it is necessary for T1CKI to have a period of at least 4Tosc and a small RC delay of 40 ns divided by the prescaler value The only requirement on T1CKI high and low time is that they do not violate the minimum pulse width requirements of 10 ns Refer to the appropriate electrical specifica tions parameters 40 42 45 46 and 47 Synchronized clock input TMR1ON on off gt TIOSCEN Fosc 4 Enable um Internal Oscillator Clock RCO T1OSO T1CKI ES RC1 T1OSI CCP22 Note 1 2 The CCP2 modul
252. e 0111 Capture mode every 16th rising edge 1000 Compare mode set output on match CCPXxIF bit is set 1001 Compare mode clear output on match CCPXxIF bit is set 1010 Compare mode generate software interrupt on match CCPXxIF bit is set CCPx pin is unaffected 1011 Compare mode trigger special event CCPXIF bit is set CCP1 resets TMR1 CCP2 resets TMR1 and starts an A D conversion if A D module is enabled 11xx PWM mode 10 1 Capture Mode Applicable Devices 72 73 73A 74 74A 76 77 In Capture mode CCPR1H CCPR1L captures the 16 bit value of the TMR1 register when an event occurs on pin RC2 CCP1 An event is defined as Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3 CCP1MO CCP1CON lt 3 0 gt When a capture is made the inter rupt request flag bit CCP1IF PIR1 lt 2 gt is set It must be cleared in software If another capture occurs before the value in register CCPR1 is read the old captured value will be lost 10 1 14 CCP PIN CONFIGURATION In Capture mode the RC2 CCP1 pin should be config ured as an input by setting the TRISC 2 bit Note If the RC2 CCP1 is configured as an out put a write to the port can cause a capture condition FIGURE 10 2 CAPTURE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF PIR1 lt 2 gt Prescaler 1 4 16 deg CCPR1H CCPRIL In
253. e 100 kHz 2C bus system but the requirement tsu DAT gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line TR max tsu DAT 1000 250 1250 ns according to the standard mode DC bus specification before the SCL line is released 1997 Microchip Technology Inc DS30390E page 197 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 11 USART SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING pin RC7 RX DT pin a 121 gt 120 Note Refer to Figure 18 1 for load conditions TABLE 18 11 USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 120 TckH2dtV SYNC XMIT MASTER amp SLAVE PIC16C73 74 80 ns Clock high to data out valid PIC16LC73 74 100 ns 121 Tckrf Clock out rise time and fall time PIC16C73 74 45 ns Master Mode PIC16LC73 74 50 ns 122 Tdtrf Data out rise time and fall time PIC16C73 74 45 ns PIC16LC73 74 50 ns T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 18 12 USART SYNCHRONOUS RECEIVE MASTER SLAVE TIMING
254. e TXREG register While flag bit TXIF indicates the status of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register TRMT is a read only bit which is set when the TSR is empty No inter rupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty The TSR is not mapped in data memory so it is not available to the user Transmission is enabled by setting enable bit TXEN TXSTA lt 5 gt The actual transmission will not occur until the TXREG register has been loaded with data The first data bit will be shifted out on the next available rising edge of the clock on the CK line Data out is sta ble around the falling edge of the synchronous clock Figure 12 12 The transmission can also be started by first loading the TXREG register and then setting bit TXEN Figure 12 13 This is advantageous when slow baud rates are selected since the BRG is kept in reset when bits TXEN CREN and SREN are clear Setting enable bit TXEN will start the BRG creating a shift clock immediately Normally when transmission is first started the TSR register is empty so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG Back to back trans fers are possible Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter The DT and CK pins will revert to hi im
255. e to PIC16C76 77 ns Port input invalid 1 O in PIC16LC76 77 ns hold time TioV20sH Port input valid to OSC1T I O in setup time ns TioR Port output rise time PIC16C76 77 10 40 ns PIC16LC76 77 80 ns TioF Port output fall time PIC16C76 77 10 40 ns PIC16LC76 77 80 ns 22tt Tinp INT pin high or low time TCY ns 23tt Trop RB7 RB4 change INT high or low time TCY ns These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested tt These parameters are asynchronous events not related to any internal clock edges Note 1 Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC 1997 Microchip Technology Inc DS30390E page 227 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING Time out OSC Time out Internal RESET Watchdog Timer I O Pins Note Refer to Figure 20 1 for load conditions FIGURE 20 5 BROWN OUT RESET TIMING TABLE 20 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 30 TmcL MCLR Pulse Width low 2 us
256. e tristes ches e 241 Maximum IPD vs VDD WDT Disabled RC Mode 241 Typical IPD vs VDD 25 C WDT Enabled RC Mode 242 Maximum IPD vs VDD WDT Enabled RC Mode 242 Typical RC Oscillator Frequency vs VDD eseeeeeeeee 242 Typical RC Oscillator Frequency vs Ve 242 Typical RC Oscillator Frequency vs VD 242 Typical IPD vs VDD Brown out Detect Enabled RC Mode 243 Maximum IPD vs VDD Brown out Detect Enabled 85 C to 40 C RC Mode 243 Typical IPD vs Timer1 Enabled 32 kHz RCO RC1 33 pF 33 pF Maximum IPD vs Timer1 Enabled 32 kHz RCO RC1 33 pF 33 pF 85 C to 40 C RC Mode 243 Typical IDD vs Frequency RC Mode 22 pF 25 C 244 Maximum IDD vs Frequency RC Mode 22 pF 40 C to 85 C 244 Typical IDD vs Frequency RC Mode 100 pF 25 C 245 Maximum IDD vs Frequency RC Mode 100 pF 40 C to 85 C 245 Typical IDD vs Frequency RC Mode 300 pF 25 C 246 Maximum IDD vs Frequency RC Mode 300 pF 40 C to 85 C 246 Typical IDD vs Capacitance 500 kHz RC Mode eese 247 Transconductance gm of HS Oscillator vs VDD 247 Transconductance gm of LP Oscillator vs Von 247 Transconductance gm of XT Oscillator vs VDD seessesess 247 Typical XTAL Startup Time vs VDD
257. e RESET con dition The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out 14 7 2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions VDD Min Temperature Max and max WDT prescaler it may take several seconds before a WDT time out occurs Note When a CLRWDT instruction is executed and the prescaler is assigned to the WDT the prescaler count will be cleared but the prescaler assignment is not changed FIGURE 14 18 WATCHDOG TIMER BLOCK DIAGRAM From TMRO Clock Source Figure 7 6 WDT Timer WDT Enable Bit Postscaler A 8 8 to 1 MUX PS2Z PSO nm To TMPO Figure 7 6 Note PSA and PS2 PSO are bits in the OPTION register ot v MUX t WDT Time out FIGURE 14 19 SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config bits 1 BODEN CPO PWRTEU WDTE FOSC1 FOSCO 81h 181h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO Legend Shaded cells are not used by the Watchdog Timer Note 1 See Figure 14 1 and Figure 14 2 for operation of these bits DS30390E page 144 1997 Microchip Technology Inc PIC16C7X 14 8 Power down Mode SLEEP Applicable Devices 72 73 73A 74 74A 76 77 Power down mode is entered by executing a SLEEP instruct
258. e bit RCIE was set 8 Read the RCSTA register to get the ninth bit if enabled and determine if any error occurred during reception 9 Read the 8 bit received data by reading the RCREG register If any error occurred clear the error by clearing bit CREN 10 TABLE 12 9 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value oh Value on all Address Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit 2 Bit 1 Bit 0 POR other Resets BOR OCh PIR1 PsPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 9000 00x 0000 00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Master Reception Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear DS30390E page 112 1997 Microchip Technology Inc PIC16C7X FIGURE 12 14 SYNCHRONOUS RECEPTION MASTER MODE SREN ajasoda1 adadad ai a3osadja adasladailaaaslalaildasladr azjaslos b la2laslaat laz asia4 b loz oso lei od ado RC7 RX DT pin bitO bit7
259. e is not implemented in the PIC16C72 3 Forthe PIC16C73 and PIC16C74 the Schmitt Trigger is Synchronize f det SLEEP input Prescaler o T1CKPS1 T1CKPS0 TMR1CS H When the T1OSCEN bit is cleared the inverter and feedback resistor are turned off This eliminates power drain not implemented in external clock mode DS30390E page 66 1997 Microchip Technology Inc PIC16C7X 8 3 Timer1 Operation in Asynchronous Counter Mode Applicable Devices 72 73 73A 74 74A 76 77 If control bit TISYNC TICON lt 2 gt is set the external clock input is not synchronized The timer continues to increment asynchronous to the internal phase clocks The timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake up the processor However special precautions in soft ware are needed to read write the timer Section 8 3 2 In asynchronous counter mode Timeri can not be used as a time base for capture or compare operations 8 3 1 EXTERNAL CLOCK INPUT TIMING WITH UNSYNCHRONIZED CLOCK If control bit TTSYNC is set the timer will increment completely asynchronously The input clock must meet certain minimum high time and low time requirements Refer to the appropriate Electrical Specifications Sec tion timing parameters 45 46 and 47 8 3 2 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running fr
260. e these two bits unim plemented read as 0 1997 Microchip Technology Inc DS30390E page 97 D C 1 6C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 11 27 OPERATION OF THE I C MODULE IN IDLE MODE RCV MODE OR XMIT MODE IDLE MODE 7 bit if Addr match Set interrupt if R W 1 Send ACK 0 set XMIT MODE else if R W 0 set RCV MODE RCV MODE if SSPBUF Full OR SSPOV 1 Set SSPOV Do not acknowledge else transfer SSPSR SSPBUF send ACK 0 Receive 8 bits in SSPSR Set interrupt XMIT_MODE While SSPBUF Empty AND CKP 0 Hold SCL Low Send byte Set interrupt if ACK Received 1 End of transmission Go back to IDLE MODE else if ACK Received 0 Go back to XMIT_MODE IDLE_MODE 10 Bit If High_byte_addr_match AND R W 0 PRIOR_ADDR_MATCH FALSE Set interrupt if SSPBUF Full OR SSPOV 1 Set SSPOV Do not acknowledge else Set UA 1 Send ACK 0 While SSPADD not updated Hold SCL low Clear UA 0 Receive Low_addr_byte Set interrupt Set UA 1 If Low byte addr match PRIOR_ADDR_MATCH TRUE Send ACK 0 while SSPADD not updated Hold SCL low Clear UA 0 Set HCH MODE else if High byte addr match AND DAN 1 if PRIOR_ADDR_MATCH send ACK 0 set XMIT MODE else PRIOR ADDR MATCH FALSE DS30390E page 98 1997
261. e to normal process distribution The variation indicated is 3 standard deviation from average value for VDD 5V PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 19 TRANSCONDUCTANCE gm OF HS OSCILLATOR vs VDD Max 40 C lt E o 35 40 45 5 0 Shaded area is Vop Volts beyond recommended range FIGURE 21 20 TRANSCONDUCTANCE gm OF LP OSCILLATOR vs VDD 90 80 70 60 50 40 30 20 LT 10 Min ET 96 2 5 3035 40 45 5 0 55 60 65 7 0 Shaded areas are Vop Volts beyond recommended range FIGURE 21 21 TRANSCONDUCTANCE gm OF XT OSCILLATOR vs VDD X 25 3 0 3 5 4 0 45 50 55 60 65 7 0 Vpp Volts Shaded areas are beyond recommended range 1997 Microchip Technology Inc DS30390E page 247 Data based on matrix samples See first page of this section for details Data based on matrix samples See first page of this section for details PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 21 22 TYPICAL XTAL STARTUP TIME vs VDD LP MODE 25 C 32 kHz 33 pF 33 pF E o c o o o 2 D E 2 2 T bo f e 200 kHz 15 pF 15 pF FIGURE 21 23 TYPICAL XTAL STARTUP TIME vs Vo
262. eceiver Slave transmitter and Master receiver TABLE 11 3 12C BUS TERMINOLOGY In both cases the master generates the clock signal The output stages of the clock SCL and data SDA lines must have an open drain or open collector in order to perform the wired AND function of the bus External pull up resistors are used to ensure a high level when no device is pulling the line down The num ber of devices that may be attached to the DC bus is limited only by the maximum bus loading specification of 400 pF 11 4 1 INITIATING AND TERMINATING DATA TRANSFER During times of no data transfer idle time both the clock line SCL and the data line SDA are pulled high through the external pull up resistors The START and STOP conditions determine the start and stop of data transmission The START condition is defined as a high to low transition of the SDA when the SCL is high The STOP condition is defined as a low to high transition of the SDA when the SCL is high Figure 11 14 shows the START and STOP conditions The master generates these conditions for starting and terminating data trans fer Due to the definition of the START and STOP con ditions when data is being transmitted the SDA line can only change state when the SCL line is low FIGURE 11 14 START AND STOP CONDITIONS Change of Data Allowed Change of Data Allowed Condition Condition Term Description Transmitter The device that sen
263. ection to VDD and Vss 2 To enable weak pull ups set the appropriate TRIS bit s and clear the RBPU bit OPTION lt 7 gt TABLE 5 3 PORTB FUNCTIONS Name Bit Buffer Function RBO INT bitO TTL ST Input output pin or external interrupt input Internal software programmable weak pull up RB1 bit1 TTL Input output pin Internal software programmable weak pull up RB2 bit2 TTL Input output pin Internal software programmable weak pull up RB3 bit3 TTL Input output pin Internal software programmable weak pull up RB4 bit4 TTL Input output pin with interrupt on change Internal software programmable weak pull up RB5 bit5 TTL Input output pin with interrupt on change Internal software programmable weak pull up RB6 bit6 TTL ST Input output pin with interrupt on change Internal software programmable weak pull up Serial programming clock RB7 bit7 TTL ST Input output pin with interrupt on change Internal software programmable weak pull up Serial programming data Legend TTL TTL input ST Schmitt Trigger input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode T DS30390E page 46 1997 Microchip Technology Inc PIC16C7X TABLE 5 4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on all Address Name Bit 7 Bit 6 Bit5 Bit4
264. edance C only AA output access High High BUF Bus free Low Low Tcc sr IC specifications only HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 19 1 LOAD CONDITIONS Load condition 1 Load condition 2 VDD 2 o 4640 50 pF forall pins except OSC2 but including PORTD and PORTE outputs as ports 15pF for OSC2 output Note PORTD and PORTE are not implemented on the PIC16C73A DS30390E page 206 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19 5 Timing Diagrams and Specifications FIGURE 19 2 EXTERNAL CLOCK TIMING CLKOUT TABLE 19 2 EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No Fosc External CLKIN Frequency DC E 4 MHz XT and RC osc mode Note 1 DC 4 MHz HS osc mode 04 DC 10 MHz HS osc mode 10 DC 20 MHz HS osc mode 20 DC 200 kHz LP osc mode Oscillator Frequency DC 4 MHz RC osc mode Note 1 0 1 4 MHz XT osc mode 4 20 MHz HS osc mode 5 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 ns XT and RC osc mode Note 1 250 ns HS osc mode 04 100 ns HS osc mode 10 50 ns HS osc mode 20 5 us LP osc mode Oscillator Period 250 ns RC osc mode Note 1
265. ee eeee 146 Typical In Circuit Serial Programming Connection General Format for Instructions T Load Conditions External Clock Timing CLKOUT and I O Timing Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 Figure 17 8 Figure 17 9 Figure 17 10 Figure 17 11 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 18 7 Figure 18 8 Figure 18 9 Figure 18 10 Figure 18 11 Figure 18 12 Figure 18 13 Figure 19 1 Figure 19 2 Figure 19 3 Figure 19 4 Figure 19 5 Figure 19 6 Figure 19 7 Figure 19 8 Figure 19 9 Figure 19 10 Figure 19 11 Figure 19 12 Figure 19 13 Figure 19 14 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure 20 5 Figure 20 6 Figure 20 7 Figure 20 8 Reset Watchdog Timer Oscillator Start up Timer and Power up Timer BELTS Ree mine fe rt 175 Brown out Reset Timing 175 TimerO and Timer1 External Clock Timings eene 176 Capture Compare PWM Timings CCPI SPI Mode Timing a CC Bus Start Stop Bits Timing DC Bus Data Timing ssis A D Conversion Timing Load Conditions External Clock Timing di CLKOUT and I O Timing Reset Watchdog Timer Oscillator Start up Timer and Power up
266. el RLF O lt f lt 127 de 0 1 fd See description below C 00 1101 dfff ffff The contents of register f are rotated one bit to the left through the Carry Flag If d is 0 the result is placed in the W register If d is 1 the result is stored back in register f Register f EE Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination T RLF REG1 0 Before Instruction REG1 1110 0110 C 0 After Instruction REG1 1110 0110 W 1100 1100 C I RRF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Rotate Right f through Carry label RRF f O lt f lt 127 de 0 1 See description bi C 00 1100 d elow dfff ffff The contents of register are rotated one bit to the right through the Carry Flag If d is O the result is placed in the W register If d is 1 the result is placed back in register f gt C gt Register f Sa 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination T RRF REG1 0 Before Instruction REG1 1110 0110 C p After Instruction REG1 1110 0110 W 0111 0011 C 0 1997 Microchip Technology Inc DS30390E page 159 PIC16C7X SLEEP Syntax abel SLEEP Operands None Operation 00h gt WDT 0 WDT prescaler 19 TO
267. el specification 1997 Microchip Technology Inc DS30390E page 131 PIC16C7X 14 2 3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built Prepack aged oscillators provide a wide operating range and better stability A well designed crystal oscillator will provide good performance with TTL gates Two types of crystal oscillator circuits can be used one with series resonance or one with parallel resonance Figure 14 5 shows implementation of a parallel reso nant oscillator circuit The circuit is designed to use the fundamental frequency of the crystal The 74AS04 inverter performs the 180 degree phase shift that a par allel oscillator requires The 4 7 kQ resistor provides the negative feedback for stability The 10 kQ potenti ometer biases the 74AS04 in the linear region This could be used for external oscillator designs FIGURE 14 5 EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other Devices 74AS04 PIC16CXX CLKIN Figure 14 6 shows a series resonant oscillator circuit This circuit is also designed to use the fundamental fre quency of the crystal The inverter performs a 180 degree phase shift in a series resonant oscillator cir cuit The 330 kQ resistors provide the negative feed back to bias the inverters in their linear region FIGURE 14 6 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR
268. elections which are tested for functionality but not for MIN MAX specifications It is recommended that the user select the device type that ensures the specifications required EEE 1997 Microchip Technology Inc DS30390E page 201 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19 1 DC Characteristics PIC16C73A 74A 04 Commercial Industrial Extended PIC16C73A 74A 10 Commercial Industrial Extended PIC16C73A 74A 20 Commercial Industrial Extended Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended BO CHARACTERISTICS 40 C lt TA lt 85 C for industrial and 0 C TA 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 4 0 6 0 V XT RC and LP osc configuration D001A 4 5 5 5 V HS osc configuration D002 RAM Data Retention VDR 1 5 V Voltage Note 1 DOOS VDD start voltage to VPOR Vss V See section on Power on Reset for details ensure internal Power on Reset signal D004 VDD rise rate to ensure SvDD 0 05 V ms See section on Power on Reset for details internal Power on Reset signal D005 Brown out Reset Voltage BVDD 8 7 40 43 V BODEN bit in configuration word enabled 3 7 4 0 4 4 V Extended Range Only DD 2 7 5 mA _ XT RC osc configuration Fosc 4 MHz VDD 5 5V Note 4 D01
269. emented 106h PORTB PORTB Data Latch when written PORTB pins when read XXXX XXXX uuuu uuuu 107h Unimplemented 108h Unimplemented 109h Unimplemented 10Ah 1 4 PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 10Bh 4 INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u VE Unimplemented Bank 3 180h 4 INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 181h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 182h 4 PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 183h 4 STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 0004 quuu 184h 4 FSR Indirect data memory address pointer XXXX xxxx uuuu uuuu 185h Unimplemented 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h Unimplemented 188h Unimplemented 189h Unimplemented 18Ah t 9 PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 18Bh 4 INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u EC Unimplemented Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Shaded locations are unimplemented read as 0 Note 1 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con ten
270. emented read as 0 Note 1 These registers can be addressed from either bank 2 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose contents are transferred to the upper byte of the program counter 3 Other non power up resets include external reset through MCLR and Watchdog Timer Reset 4 The IRP and RP1 bits are reserved on the PIC16C72 always maintain these bits clear DS30390E page 24 1997 Microchip Technology Inc PIC16C7X TABLE 4 2 PIC16C73 73A 74 74A SPECIAL FUNCTION REGISTER SUMMARY Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 2 Bank 0 ooh INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 01h TMRO TimerO modules register XXXX xxxx uuuu uuuu o2n 9 PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 03h STATUS IRPO RP10 RPO TO PD Z DC C 0001 1xxx 0004 quuu 04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA PORTA Data Latch when written PORTA pins when read 0x 0000 0u 0000 06h PORTB PORTB Data Latch when written PORTB pins when read xxxx xxxx
271. en received that byte is moved to the SSPBUF register Then the buffer full detect bit BF SSPSTAT lt 0 gt and interrupt flag bit SSPIF PIR1 lt 3 gt are set This double buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received Any write to the SSPBUF register during transmission reception of data will be ignored and the write collision detect bit WCOL SSPCON lt 7 gt will be set User software must clear the WCOL bit so that it can be determined if the following write s to the SSPBUF register completed success fully When the application software is expecting to receive valid data the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF Buffer full bit BF SSPSTAT 0 indicates when SSPBUF has been loaded with the received data transmission is complete When the SSPBUF is read bit BF is cleared This data may be irrelevant if the SPI is only a transmitter Generally the SSP Interrupt is used to determine when the transmission reception has completed The SSPBUF must be read and or writ ten If the interrupt method is not going to be used then software polling can be done to ensure that a write col lision does not occur Example 11 2 shows the loading of the SSPBUF SSPSR for data transmission The shaded instruction is only required if the received data is meaningful EXAMPLE 11 2 LOADING THE SSPBUF SSPSR REGISTER
272. en the A D oscillator may be changed Example 13 3 shows a comparison of time required for a conversion with 4 bits of resolution ver sus the 8 bit resolution conversion The example is for devices operating at 20 MHz and 16 MHz The A D clock is programmed for 32TOSC and assumes that immediately after 6TAD the A D clock is programmed for 2Tosc The 2Tosc violates the minimum TAD time since the last 4 bits will not be converted to correct values Resolution Freq MHz 20 16 Tosc 20 50 ns 50 ns 16 62 5 ns 62 5 ns 2TAD N TAD 8 N 2TOSC 20 10 us 16 us 16 12 5 us 20 us Note 1 PIC16C7X devices have a minimum TAD time of 1 6 us 1997 Microchip Technology Inc DS30390E page 123 PIC16C7X 13 5 A D Operation During Sleep Applicable Devices 72 73 73A 74 74A 76 77 The A D module can operate during SLEEP mode This requires that the A D clock source be set to RC ADCS1 ADCSO 11 When the RC clock source is selected the A D module waits one instruction cycle before starting the conversion This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion When the conver sion is completed the GO DONE bit will be cleared and the result loaded into the ADRES register If the A D interrupt is enabled the device will wake up from SLEEP If the A D interrupt is not enabled the A D mod ule will then be turned off altho
273. er at any time because it controls the SCK The master determines when the slave Processor 2 is to broadcast data by the firmware protocol In master mode the data is transmitted received as soon as the SSPBUF register is written to If the SPI is only going to receive the SCK output could be disabled programmed as an input The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate As each byte is received it will be loaded into the SSPBUF register as if a normal received byte interrupts and status bits appropriately Set This could be useful in receiver applications as a line activity monitor mode In slave mode the data is transmitted and received as the external clock pulses appear on SCK When the last bit is latched the interrupt flag bit SSPIF PIR1 lt 3 gt is set The clock polarity is selected by appropriately program ming bit CKP SSPCON lt 4 gt This then would give waveforms for SPI communication as shown in Figure 11 11 Figure 11 12 and Figure 11 13 where the MSB is transmitted first In master mode the SPI clock rate bit rate is user programmable to be one of the following Fosc 4 or TCY Fosc 16 or 4 TCY Fosc 64 or 16 Tcv Timer2 output 2 This allows a maximum bit clock frequency at 20 MHz of 5 MHz When in slave mode the external clock must meet the minimum high and low times In sleep mode the slave can transmit and receive
274. errupt Enable bit 1 Enables the CCP1 interrupt 0 Disables the CCP1 interrupt bit 1 TMR2IE TMR2 to PR2 Match Interrupt Enable bit 1 Enables the TMR2 to PR2 match interrupt 0 Disables the TMR2 to PR2 match interrupt bit 0 TMRIIE TMR1 Overflow Interrupt Enable bit 1 Enables the TMR1 overflow interrupt 0 Disables the TMR1 overflow interrupt 1997 Microchip Technology Inc DS30390E page 33 PIC16C7X FIGURE 4 11 PIE1 REGISTER PIC16C73 73A 74 74A 76 77 ADDRESS 8Ch R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PSPIE DS30390E page 34 1997 Microchip Technology Inc PIC16C7X ou PERC E Note Interrupt flag bits get set when an interrupt Applicable Devices condition occurs regardless of the state of 72 r3 T3A 74 74A 76 77 its corresponding enable bit or the global This register contains the individual flag bits for the enable bit GIE INTCON lt 7 gt User soft Peripheral interrupts ware should ensure the appropriate inter rupt flag bits are clear prior to enabling an interrupt FIGURE 4 12 PIR1 REGISTER PIC16C72 ADDRESS 0Ch R W 0 R W 0 R W 0 R W 0 R W 0 nF ET TMRIIF IR Readable bit bit7 bit 7 bit 6 bit 5 4 bit 3 bit 2 bit 1 bit 0 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset Unimplemented Read as 0 ADIF A D Converter Interrupt Flag bit 1 An A D conve
275. es Interrupt Sources 8 8 11 11 10 11 UO Pins 33 33 22 33 Voltage Range Volts 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 In Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown out Reset Yes Yes Yes Yes Yes Yes Packages 40 pin DIP 40 pin DIP 40 pin DIP 40 pin DIP 28 pin SDIP 40 pin DIP 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin SOIC 44 pin MOER TQFP MQFP TQFP MOER TQFP PLCC PLCC MQFP MQFP TQFP TQFP All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capability All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7 a EE DS30390E page 268 1997 Microchip Technology Inc ES PIC16C8X Family of Devices Maximum Frequency of Operation MHz PIC16C 7X Memory KAU Ua Timer Module s als 10 10 10 10 Flash Program Memory 512 1K EEPROM Program Memory T E Em E ROM Program Memory 512 1K Data Memory bytes 36 36 68 68 Data EEPROM bytes 64 64 64 64 TMRO TMRO TMRO TMRO Interrupt Sources 4 4 4 4 UO Pins 13 13 13 13 Voltage Range Volts 2 0 6 0 2 0 6 0 2 0 6 0 2 0 6 0 Packages 18 pin DIP 18 pin DIP 18 pin DIP 18 pin DIP SOIC SOIC SOIC SOIC All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high I O current capabil ity All PIC16C8
276. es Jas OC Dee SE 1 dd DyEs 0 101 i 4 Do P p Seating 0 38 A PN gt os VAN F B E2 si AA i 4 EE 0 38 I Le Dias F6 N ES x LT Y Ee 007 ld EO 0 812 0 661 0 254 0 254 PA Ka 010 Max _ 7 010 Max NA 032 026 0 508 1524 02m Dua 060 M C L 1 651 1 651 0 64 0 533 0 331 065 065 oe Min gt WIER R 1 14 0 64 R 140 64 gees 0457 025 045 025 Sm lA F G D E Package Group Plastic Leaded Chip Carrier PLCC Millimeters Inches Symbol Min Max Notes Min Max Notes A 4 191 4 572 0 165 0 180 Al 2 413 2 921 0 095 0 115 D 17 399 17 653 0 685 0 695 D1 16 510 16 663 0 650 0 656 D2 15 494 16 002 0 610 0 630 D3 12 700 12 700 Reference 0 500 0 500 Reference E 17 399 17 653 0 685 0 695 E1 16 510 16 663 0 650 0 656 E2 15 494 16 002 0 610 0 630 E3 12 700 12 700 Reference 0 500 0 500 Reference N 44 44 44 44 CP 0 102 0 004 LT 0 203 0 381 0 008 0 015 1997 Microchip Technology Inc DS30390E page 257 PIC16C7X 22 8 44 Lead Plastic Surface Mount MOER 10x10 mm Body 1 6 0 15 mm Lead Form PQ Av 0 20 W c A B DG QD 0 20 M neo p AA 0 05 mm mm A B ig 0 20 min area 8 p
277. eset Voltage BVDD 3 7 4 0 43 V BODEN bit in configuration word enabled D010 Supply Current Note 2 5 IDD 2 0 3 8 mA XT RC osc configuration Fosc 4 MHz VDD 3 0V Note 4 D010A 22 5 48 uA LP osc configuration Fosc 32 kHz VDD 3 0V WDT disabled D015 Brown out Reset Current AIBOR 350 425 pA BOR enabled VDD 5 0V Note 6 D020 Power down Current IPD 7 5 30 uA VDD 3 0V WDT enabled 40 C to 85 C D021 Note 3 5 0 9 5 uA VDD 3 0V WDT disabled 0 C to 70 C D021A 0 9 5 uA VDD 3 0V WDT disabled 40 C to 85 C D023 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all UO pins tristated pulled to VoD MCLR VDD WDT enabled disabled as specified 3 The power down current in SLEEP mode d
278. et enable bit CREN 5 Flag bit RCIF will be set when reception is com plete and an interrupt will be generated if enable bit RCIE was set 6 Read the RCSTA register to get the ninth bit if enabled and determine if any error occurred during reception 7 Read the 8 bit received data by reading the RCREG register 8 If any error occurred clear the error by clearing bit CREN DS30390E page 114 1997 Microchip Technology Inc PIC16C7X TABLE 12 10 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION NAME ON Value on all Address Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit 2 Bit 1 Bit 0 Soe other Resets DCH PIR1 PsPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRAIE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used for Synchronous Slave Transmission Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear TABLE 12 11 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
279. f ffff 1 2 3 IORWF fd Inclusive OR W with f 1 00 0100 afff ffff Z 1 2 MOVF fd Move f 1 00 000 afff ffff Z 1 2 MOVWF f Move W to f 1 00 0000 1fff ffff NOP No Operation 1 00 0000 Oxx0 0000 RLF fd Rotate Left f through Carry 1 00 01 dfff ffff C 1 2 RRF f d Rotate Right f through Carry 1 00 00 afff ffff C 1 2 SUBWF fd Subtract W fromf 1 00 0010 afff ffff C DC Z 1 2 SWAPF Ld Swap nibbles in f 1 00 10 dfff ffff 1 2 XORWF fd Exclusive OR W with f 1 00 0110 afff ffff Z 1 2 BIT ORIENTED FILE REGISTER OPERATIONS BCF f b BitClearf 1 01 00bb bfff ffff 1 2 BSF f b BitSetf 1 01 Olbb bfff ffff 1 2 BTFSC fb Bit Test f Skip if Clear 1 2 01 Obb bfff ffff 3 BTFSS fb Bit Test f Skip if Set 1 2 01 bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 1x kkkk kkkk C DC Z ANDLW k AND literal with W 1 11 001 kkkk kkkk Z CALL k Call subroutine 2 10 Okkk kkkk kkkk CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TO PD GOTO k Go to address 2 10 kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 000 kkkk kkkk Z MOVLW k Move literal to W 1 It O0xx kkkk kkkk RETFIE Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 IT Olxx kkkk kkkk RETURN Return from Subroutine 2 00 0000 0000 1000 SLEEP Go into standby mode 1 00 0000 0110 0011 TOPD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C DC Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
280. for details ensure internal Power on Reset signal D004 VDD rise rate to ensure SvDD 0 05 V ms See section on Power on Reset for details internal Power on Reset signal D005 Brown out Reset Voltage Bvbb 3 7 4 0 43 V BODEN bit in configuration word enabled D010 Supply Current IDD 2 0 38 mA XT RC osc configuration Note 2 5 Fosc 4 MHz VpD 3 0V Note 4 D010A 22 5 48 uA LP osc configuration Fosc 32 kHz VDD 3 0V WDT disabled D015 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 D020 Power down Current IPD 7 5 30 uA VDD 3 0V WDT enabled 40 C to 85 C D021 Note 3 5 0 9 5 uA VDD 3 0V WDT disabled 0 C to 70 C D021A 0 9 5 uA VDD 3 0V WDT disabled 40 C to 85 C D023 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as UO pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in
281. fore next acquisition starts CHS2 CHSO RE2 AN7 n e RE1 AN6 REO AN5 RAS AN4 Input voltage A D Converter RAS ANS VREF RA2 AN2 RA1 AN1 PX XI PS DX DA DX DS RAO ANO Reference voltage PCFG2 PCFGO Note 1 Notavailable on PIC16C72 73 73A 76 DS30390E page 119 1997 Microchip Technology Inc PIC16C7X 13 1 A D Acquisition Requirements Applicable Devices 72 73 73A 74 74A 76 77 For the A D converter to meet its specified accuracy the charge holding capacitor CHOLD must be allowed to fully charge to the input channel voltage level The analog input model is shown in Figure 13 4 The source impedance Rs and the internal sampling switch Rss impedance directly affect the time required to charge the capacitor CHOLD The sampling switch Rss imped ance varies over the device voltage VDD Figure 13 4 The source impedance affects the offset voltage at the analog input due to pin leakage current The maxi mum recommended impedance for analog sources is 10 kQ After the analog input channel is selected changed this acquisition must be done before the con version can be started To calculate the minimum acquisition time Equation 13 1 may be used This equation calculates the acquisition time to within 1 2 LSb error is used 512 steps for the A D The 1 2 LSb error is the maximum error allowed fo
282. g write s to the SSPBUF completed successfully When the application software is expecting to receive valid data the SSPBUF register should be read before the next byte of data to transfer is written to the SSPBUF register The Buffer Full bit BF SSPSTAT 0 indicates when the SSPBUF register has been loaded with the received data transmission is complete When the SSPBUF is read bit BF is cleared This data may be irrelevant if the SPI is only a transmitter Generally the SSP Interrupt is used to determine when the transmission reception has com pleted The SSPBUF register must be read and or writ ten If the interrupt method is not going to be used then software polling can be done to ensure that a write col lision does not occur Example 11 1 shows the loading ofthe SSPBUF SSPSR register for data transmission The shaded instruction is only required if the received data is meaningful EXAMPLE 11 1 LOADING THE SSPBUF SSPSR REGISTER BSF STATUS RPO Specify Bank 1 LOOP BTFSS SSPSTAT BF Has data been received transmit complete GOTO LOOP No BCF STATUS RPO Specify Bank 0 MOVF SSPBUF W W reg contents of SSPBUF MOVWF RXDATA Save in user RAM MOVF TXDATA W W reg contents of TXDATA MOVWF SSPBUF New data to xmit The block diagram of the SSP module when in SPI mode Figure 11 3 shows that the SSPSR register is not directly readable or writable and can only be accessed from addressing the SS
283. ge 13 PIC16C7X TABLE 3 2 PIC16C73 73A 76 PINOUT DESCRIPTION Pin Name DIP SOIC VOF Butter Description Pin Pin Type Type OSC1 CLKIN 9 9 ST CMOS Oscillator crystal input external clock source input OSC2 CLKOUT 10 10 O Oscillator crystal output Connects to crystal or resonator in crystal oscillator mode In RC mode the OSC2 pin outputs CLKOUT which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate MGLR VPP 1 1 VP ST Master clear reset input or programming voltage input This pin is an active low reset to the device PORTA is a bi directional UO port RAO ANO 2 2 1 0 TTL RAO can also be analog inputO RA1 AN1 3 3 1 0 TTL RAT can also be analog input1 RA2 AN2 4 4 VO TTL RA2 can also be analog input2 RA3 AN3 VREF 5 5 1 0 TTL RAS can also be analog input3 or analog reference voltage RA4 TOCKI 6 6 UO ST RA4 can also be the clock input to the TimerO module Output is open drain type RA5 SS AN4 7 7 1 0 TTL RAS can also be analog input4 or the slave select for the synchronous serial port PORTB is a bi directional UO port PORTB can be software programmed for internal weak pull up on all inputs RBO INT 21 21 UO TTL sT RBO can also be the external interrupt pin RB1 22 22 VO TTL RB2 23 23 1 0 TTL RB3 24 24 1 0 TTL RB4 25 25 1 0 TTL Interrupt on change pin RB5 26 26 1 0 TTL Interrupt on change pin RB6 27 27 VO TTLST Interrupt on change pin Serial programming cl
284. ge 50 1997 Microchip Technology Inc PIC16C7X 5 5 PORTE and TRISE Register Note On a Power on Reset these pins are con Applicable Devices figured as analog inputs 72 73 73A 74 74Al76 77 FIGURE 5 8 PORTE BLOCK DIAGRAM IN PORTE has three pins REO RD AN5 RE1 WR AN6 1 0 PORT MODE and RE2 CS AN7 which are individually configurable Data as inputs or outputs These pins have Schmitt Trigger bus D ol input buffers WR UO PORTE becomes control inputs for the micropro PORT I CK cessor port when bit PSPMODE TRISE 4 is set In this mode the user must make sure that the EE TRISE lt 2 0 gt bits are set pins are configured as digital D Q inputs and that register ADCON1 is configured for dig WR ital UO In this mode the input buffers are TTL IRIS ck Schmitt Figure 5 9 shows the TRISE register which also con TRIS Latch input trols the parallel slave port operation PORTE pins are multiplexed with analog inputs The operation of these pins is selected by control bits in the ADCON register When selected as an analog input these pins will read as O s TRISE controls the direction of the RE pins they are being used as analog in make sure to keep the pi using them as a 1997 Microchip Technology Inc DS30390E page 51 PIC16C7X TABLE 5 9 PORTE FUNCTIONS Name Bit Buffer Type Function REO RD AN5 bitO ST
285. ged m Appendix E PIG16 17 Microcontrollers certior teen RE er RC E eee een 265 iR COMPARER ge eege ee a da ne me a td er MS EE 271 Index 278 List of Examples 279 List of Figures 280 List of Tables 283 Reader Response esses 286 PIC16C7X Product Identification System siennes 287 For register and module descriptions in this data sheet device legends show which devices apply to those sections As an example the legend below would mean that the following section applies only to the PIC16C72 PIC16C73A and PIC16C74A devices Applicable Devices 72 73 73Af74 74Af76 77 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation We have spent an exceptional amount of time to ensure that these documents are correct However we realize that we may have missed a few things If you find any information that is missing or appears in error please use the reader response form in the back of this data sheet to inform us We appreciate your assistance in making this a better document DS30390E page 4 1997 Microchip Technology Inc PIC16C7X 1 0 GENERAL DESCRIPTION The PIC16C7X is a family of low cost high perfor mance CMOS fully static 8 bit microcontrollers with integrated analog to digital A D converters in the PIC16CXX mid range family All PIC16 17 microcontrollers employ an advanced RISC architec
286. h to the inter rupt vector 0004h Steps to follow when setting up a Synchronous Slave Transmission 1 Enable the synchronous slave serial port by set ting bits SYNC and SPEN and clearing bit CSRC 2 Clear bits CREN and SREN 3 f interrupts are desired then set enable bit TXIE 4 If 9 bit transmission is desired then set bit TX9 5 Enable the transmission by setting enable bit TXEN 6 f 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Start transmission by loading data to the TXREG register 12 42 USART SYNCHRONOUS SLAVE RECEPTION The operation of the synchronous master and slave modes is identical except in the case of the SLEEP mode Also bit SREN is a don t care in slave mode If receive is enabled by setting bit CREN prior to the SLEEP instruction then a word may be received during SLEEP On completely receiving the word the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set the interrupt generated will wake the chip from SLEEP If the global interrupt is enabled the program will branch to the interrupt vector 0004h Steps to follow when setting up a Synchronous Slave Reception 1 Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC 2 f interrupts are desired then set enable bit RCIE 3 If 9 bit reception is desired then set bit RX9 4 To enable reception s
287. haracteristic Min Typt Max Units Conditions No 125 TdtV2ckL SYNC RCV MASTER amp SLAVE Data setup before CK J DT setup time 15 ns 126 TckL2dtl Data hold after CK J DT hold time 15 ns t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 216 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 19 13 A D CONVERTER CHARACTERISTICS PIC16C73A 74A 04 Commercial Industrial Extended PIC16C73A 74A 10 Commercial Industrial Extended PIC16C73A 74A 20 Commercial Industrial Extended PIC16LC73A 74A 04 Commercial Industrial Param Sym Characteristic Min Typt Max Units Conditions No A01 NR Resolution 8 bits bit VREF VDD 5 12V VSS VAIN VREF A02 EABS Total Absolute error E lt 1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF A03 EiL Integral linearity error lt 1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF A04 EDL Differential linearity error t1 LSb VREF VDD 5 12V VSS VAIN VREF A05 Ers Full scale error See lt 1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF Offset error lt 1 LSb VREF VDD 5 12V Vss lt VAIN lt VREF Monotonicity guaranteed Vss lt VAIN lt VREF A20 VREF
288. he PIC16C5X microcontroller fam ily will realize that this is an enhanced version of the PIC16C5X architecture Please refer to Appendix A for a detailed list of enhancements Code written for the PIC16C5X can be easily ported to the PIC16CXX fam ily of devices Appendix B 1 2 Development Support PIC16C7X devices are supported by the complete line of Microchip Development tools Please refer to Section 16 0 for more details about Microchip s development tools 1997 Microchip Technology Inc DS30390E page 5 PIC16C7X TABLE 1 1 PIC16C7XX FAMILY OF DEVCES H 6 P 6 H 6 H 6 H 6 H OCR Maximum Frequency 20 20 20 20 20 20 of Operation MHz EPROM Program Memory 512 1K 1K 2K 2K x14 words O ROM Program Memory m 2K 14K words Data Memory bytes 36 36 68 128 128 128 Timer Module s TMRO TMRO TMRO TMRO TMRO TMRO TMR1 TMR1 TMR2 TMR2 _ Capture Compare 1 1 SDS PWM Module s Serial Port s E SPI IFC SPI IFC SPI I2C USART Parallel Slave Port E A D Converter 8 bit Channels 4 4 4 4 5 5 Interrupt Sources 4 4 4 4 8 8 UO Pins 13 13 13 13 22 22 Voltage Range Volts 3 0 6 0 3 0 6 0 3 0 6 0 3 0 5 5 2 5 6 0 3 0 5 5 In Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown out Reset Yes Yes Yes Yes Yes Packages 18 pin DIP 18 pin DIP 18 pin DIP 18 pin DIP 28 pin SDIP 28 pin SDIP SOI
289. he SSPBUF register as if a normal received byte interrupts and status bits appropriately Set This could be useful in receiver applications as a line activity monitor mode In slave mode the data is transmitted and received as the external clock pulses appear on SCK When the last bit is latched interrupt flag bit SSPIF PIR1 3 is set The clock polarity is selected by appropriately program ming bit CKP SSPCON lt 4 gt This then would give waveforms for SPI communication as shown in Figure 11 5 and Figure 11 6 where the MSB is trans mitted first In master mode the SPI clock rate bit rate is user programmable to be one of the following Fosc 4 or TCY Fosc 16 or 4 e TCY e Fosc 64 or 16 e Tcv Timer2 output 2 This allows a maximum bit clock frequency at 20 MHz of 5 MHz When in slave mode the external clock must meet the minimum high and low times In sleep mode the slave can transmit and receive data and wake the device from sleep Serial Input Buffer SSPBUF register 1 Shift Register SSPBUF register 1 Shift Register Serial Input Buffer SSPSR PROCESSOR 1 1997 Microchip Technology Inc Serial Clock SSPSR DS30390E page 81 D C 1 6C7X Applicable Devices 72 73 73A 74 74A 76 77 The SS pin allows a synchronous slave mode The point at wh
290. he corresponding peripheral section for the correct RD TRIS Trigger TRIS bit settings Peripheral OE EXAMPLE 5 3 INITIALIZING PORTC BCF STATUS RPO BCF STATUS RP1 CLRF PORTC Select Bank 0 PIC16C76 77 only Peripheral input Initialize PORTC by clearing output data latches Select Bank 1 Value used to Note 1 I O pins have diode protection to VDD and Vss 2 Port Peripheral select signal selects between port data and peripheral output 3 Peripheral OE output enable is only activated if peripheral select is active BSF STATUS RPO MOVLW OxCF initialize data direction Set RC 3 0 as inputs RC lt 5 4 gt as outputs RC 7 6 as inputs MOVWF TRISC Se Ne Ne Ne Ne Ne Ne Ne Ne Ne en ee TABLE 5 5 PORTC FUNCTIONS Name Bit Buffer Type Function RCO T1OSO T1CK D ST Input output port pin or Timer1 oscillator output Timer1 clock input RC1 T1OSI CCP2 bitl ST Input output port pin or Timer1 oscillator input or Capture2 input Compare2 output PWM output RC2 CCP1 bit2 ST Input output port pin or Capture input Compare1 output PWM1 output RC3 SCK SCL bits ST RC3 can also be the synchronous serial clock for both SPI and PC modes RC4 SDI SDA bit4 ST RC4 can also be the SPI Data In SPI mode or data I O PC mode RC5 SDO bit5 ST Input output port pin or Synchronous Serial Port data output RC6 TX CK 2 bit6 ST Input output port pin or USART Asynchronou
291. he transfer The slave must leave SDA high so that the master can generate the STOP condition Figure 11 14 FIGURE 11 18 DATA TRANSFER WAIT STATE X A X A A ES ae GE GE MSB acknowledgment acknowledgment signal from receiver byte complete signal from receiver interrupt with receiver clock line held low while interrupts are serviced SCL j Start E Ee Condition Address RW ACK Hid Data ACK Condition DS30390E page 90 1997 Microchip Technology Inc Applicable Devices 72 73 73A 74 74A 76 77 PIC1 6C7X Figure 11 19 and Figure 11 20 show Master transmit ter and Master receiver data transfer sequences When a master does not wish to relinquish the bus by generating a STOP condition a repeated START con dition Sr must be generated This condition is identi cal to the start condition SDA goes high to low while SCL is high but occurs after a data transfer acknowl edge pulse not the bus free state This allows a mas ter to send commands to the slave and then receive the requested information or to address a different slave device This sequence is shown in Figure 11 21 FIGURE 11 19 MASTER TRANSMITTER SEQUENCE For 7 bit address S Slave Address R W A Data A Data NA P 0 write data transferred n bytes acknowledge A master transmitter addresses a slave receiver with a 7 bit address The transfer direction is not change
292. i A1 A Gelle el je iB i 4 D1 Package Group Ceramic Side Brazed Dual In Line CER p Millimeters Inches mbo d Min Max Notes Min Max Notes a 0 10 0 10 A 3 937 5 030 0 155 0 198 Al 1 016 1 524 0 040 0 060 A2 2 921 3 506 0 115 0 138 A3 1 930 2 388 0 076 0 094 B 0 406 0 508 0 016 0 020 B1 1 219 1 321 Typical 0 048 0 052 C 0 228 0 305 Typical 0 009 0 012 D 35 204 35 916 1 386 1 414 D1 32 893 33 147 Reference 1 295 1 305 E 7 620 8 128 0 300 0 320 E1 7 366 7 620 0 290 0 300 el 2 413 2 667 Typical 0 095 0 105 eA 7 366 7 874 Reference 0 290 0 310 eB 7 594 8 179 0 299 0 322 L 3 302 4 064 0 130 0 160 N 28 28 28 28 S 1 143 1 397 0 045 0 055 S1 0 533 0 737 0 021 0 029 1997 Microchip Technology Inc DS30390E page 251 PIC16C7X 22 2 40 Lead Ceramic CERDIP Dual In line with Window 600 mil JW N I LI LI EST LI LI LI LI 1 i 1 E1 E A ER ve er Le PT M C Pin No 1 7 S Indicator I I e eA se Area lt eB gt ra S Base Plane Seating Plane B1 B Package Group Ceramic CERDIP Dual In Line CDP Millimeters Inches Symbol Min Max Notes Min Max Notes Typical Typical Typical Typical Reference Reference
293. ich it was taken high External pull up SPI must be in slave mode SSPCON lt 3 0 gt 04h pull down resistors may be desirable depending on the and the TRISA lt 5 gt bit must be set the for synchro application nous slave mode foe enabled When the SS pin is To emulate two wire communication the SDO pin can low transmission and reception are enabled and be connected to the SDI pin When the SPI needs to the SDO pinis driven When the SS P dq high operate as a receiver the SDO pin can be configured as the SDO pin is no longer driven even if in the mid an input This disables transmissions from the SDO dle of a transmitted byte and becomes a floating The SDI can always be left as an input SDI function output If the SS pin is taken low without resetting sinceit cannot create abus contia SPI mode the transmission will continue from the FIGURE 11 5 SPI MODE TIMING MASTER MODE OR SLAVE MODE W O SS CONTROL TABLE 11 1 REGISTERS ASSOCIATED WITH SPI OPERATION Value on Value on Address Name Bit 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 POR all other BOR resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u DCH PIR1 PsPIF 2 ADIF RCIF xiF 2 ssP
294. implemented read as 0 Note 1 Shaded locations are unimplemented read as 0 The upper byte of the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con tents are transferred to the upper byte of the program counter Other non power up resets include external reset through MCLR and Watchdog Timer Reset Bits PSPIE and PSPIF are reserved on the PIC16C76 always maintain these bits clear These registers can be addressed from any bank PORTD and PORTE are not physically implemented on the PIC16C76 read as 0 DS30390E page 28 1997 Microchip Technology Inc PIC16C7X TABLE 4 3 PIC16C76 77 SPECIAL FUNCTION REGISTER SUMMARY Cont d Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 2 Bank 2 100h 4 INDF Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 101h TMRO TimerO modules register XXXX XXXXx uuuu uuuu 102h 4 PCL Program Counter s PC Least Significant Byte 0000 0000 0000 0000 103h 4 STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu 104h 4 FSR Indirect data memory address pointer XXXX XXXX uuuu uuuu 105h Unimpl
295. ini mum of 10 MHz SSP Module 1 5TCY 102 TR SDA and SCL rise 100 kHz mode 1000 ns time 400 kHz mode 20 0 1Cb 300 ns Cbis specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode 300 ns 400 kHz mode 20 0 1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU STA START condition 100 kHz mode 4 7 us Only relevant for repeated setup time 400 kHz mode 0 6 us START condition 91 THD STA START condition hold 100 kHz mode 4 0 us After this period the first clock time 400 kHz mode 0 6 us pulse is generated 106 THD DAT Data input hold time 100 kHz mode 0 ns 400 kHz mode 0 0 9 us 107 TSU DAT Data input setup time 100 kHz mode 250 ns Note 2 400 kHz mode 100 ns 92 Tsu sTO STOP condition setup 100 kHz mode 4 7 us time 400 kHz mode 0 6 us 109 TAA Output valid from 100 kHz mode 3500 ns Note 1 clock 400 kHz mode ns 110 TBUF Bus free time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 13 us before a new transmission can start Cb Bus capacitive loading 400 pF Note 1 Asatransmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of START or STOP conditions 2 Afast mode 400 kHz I C bus device can be used in a standard mode 100 kHz 2C bus system but the requirement tsu DAT gt 250 ns must then be met This will automatically be the case
296. input when used in serial programming mode 3 This buffer is a Schmitt Trigger input when configured as general purpose UO and a TTL input when used in the Parallel Slave Port mode for interfacing to a microprocessor bus 4 This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise DS30390E page 16 1997 Microchip Technology Inc PIC16C7X 3 1 Clocking Scheme Instruction Cycle The clock input from OSC1 is internally divided by four to generate four non overlapping quadrature clocks namely Q1 Q2 Q3 and Q4 Internally the pro gram counter PC is incremented every Q1 the instruction is fetched from the program memory and latched into the instruction register in Q4 The instruc tion is decoded and executed during the following Q1 through Q4 The clocks and instruction execution flow is shown in Figure 3 4 FIGURE 3 4 _CLOCK INSTRUCTION CYCLE 3 2 Instruction Flow Pipelining An Instruction Cycle consists of four Q cycles Q1 Q2 Q3 and Q4 The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change e g GOTO then two cycles are required to complete the instruction Example 3 1 A fetch cycle begins with the program counter PC
297. interrupt enable bit GIE INTCON lt 7 gt enables if set all un masked interrupts or disables if cleared all interrupts When bit GIE is enabled and an interrupt s flag bit and mask bit are set the interrupt will vector immediately Individual interrupts can be dis abled through their corresponding enable bits in vari ous registers Individual interrupt bits are set regardless of the status of the GIE bit The GIE bit is cleared on reset The return from interrupt instruction RETFIE exits the interrupt routine as well as sets the GIE bit which re enables interrupts The RBO INT pin interrupt the RB port change interrupt and the TMRO overflow interrupt flags are contained in the INTCON register The peripheral interrupt flags are contained in the spe cial function registers PIR1 and PIR2 The correspond ing interrupt enable bits are contained in special function registers PIE1 and PIE2 and the peripheral interrupt enable bit is contained in special function reg ister INTCON When an interrupt is responded to the GIE bit is cleared to disable any further interrupt the return address is pushed onto the stack and the PC is loaded with 0004h Once in the interrupt service routine the source s of the interrupt can be determined by polling the interrupt flag bits The interrupt flag bit s must be cleared in software before re enabling interrupts to avoid recursive interrupts For external interrupt even
298. ion If enabled the Watchdog Timer will be cleared but keeps running the PD bit STATUS 3 is cleared the TO STATUS 4 bit is set and the oscillator driver is turned off The I O ports maintain the status they had before the SLEEP instruction was executed driving high low or hi impedance For lowest current consumption in this mode place all UO pins at either VDD or Vss ensure no external cir cuitry is drawing current from the I O pin power down the A D disable external clocks Pull all I O pins that are hi impedance inputs high or low externally to avoid switching currents caused by floating inputs The TOCKI input should also be at VDD or Vss for lowest current consumption The contribution from on chip pull ups on PORTB should be considered The MCLR pin must be at a logic high level VIHMC 14 8 1 WAKE UP FROM SLEEP The device can wake up from SLEEP through one of the following events 1 External reset input on MCLR pin 2 Watchdog Timer Wake up if WDT was enabled 3 Interrupt from INT pin RB port change or some Peripheral Interrupts External MCLR Reset will cause a device reset All other events are considered a continuation of program execution and cause a wake up The TO and PD bits in the STATUS register can be used to determine the cause of device reset The PD bit which is set on power up is cleared when SLEEP is invoked The TO bit is cleared if a WDT time
299. ion number and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price DS30390E page 262 1997 Microchip Technology Inc APPENDIX A The following are the list of modifications over the PIC16C5X microcontroller family 1 ER 10 11 12 13 14 15 16 17 18 Instruction word length is increased to 14 bits This allows larger page sizes both in program memory 2K now as opposed to 512 before and register file 128 bytes now versus 32 bytes before A PC high latch register PCLATH is added to handle program memory paging Bits PA2 PA1 PAO are removed from STATUS register Data memory paging is redefined slightly STATUS register is modified Four new instructions have been added RETURN RETFIE ADDLW and SUBLW Two instructions TRIS and OPTION are being phased out although they are kept for compati bility with PIC16C5X OPTION and TRIS registers are made address able Interrupt capability is added Interrupt vector is at 0004h Stack size is increased to 8 deep Reset vector is changed to 0000h Reset of all registers is revisited Five different reset and wake up types are recognized Reg isters are reset differently Wake up from SLEEP through interrupt is added Two separate timers Oscillator Start up Timer OST and Power up Timer PWRT
300. ions No 50 CCP1 and CCP2 No Prescaler 0 5TcY 20 Oe PIC16C73 74 10 With Prescaler 5ic16L 673 74 20 CCP1 and CCP2 No Prescaler 0 5Tcy 20 input high time PIC16C73 74 With Prescaler PICI6LC73 74 CCP1 and CCP2 input period STCY 40 N prescale value 1 4 or 16 CCP1 and CCP2 output fall time PIC16C73 74 PIC16LC73 74 CCP1 and CCP2 output fall time PIC16C73 74 PIC16LC73 74 These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 193 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 7 PARALLEL SLAVE PORT TIMING PIC16C74 RE2 CS Note Refer to Figure 18 1 for load conditions TABLE 18 7 PARALLEL SLAVE PORT REQUIREMENTS PIC16C74 Parameter Sym Characteristic Min Typt Max Units Conditions No 62 TdtV2wrH Data in valid before WRT or CST setup time 20 ns 63 TwrH2dtl WRT or CST to data in invalid hold time PIC16C74 20 ns PIC16LC74 35 ns 64 TrdL2dtV RD and CS to data out valid 80 ns 65 TrdH2dtl RD or CS to data out invalid 10 30 ns These parameters are characterized but not tested t Data in Typ c
301. ions 33 33 33 33 33 33 Packages 18 pin DIP 18 pin DIP 18 pin DIP 18 pin DIP 28 pin DIP 18 pin DIP SOIC SOIC SOIC SOIC SOIC SOIC 20 pin SSOP 20 pin SSOP 20 pin SSOP SSOP 20 pin SSOP PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A Maximum Frequency of Operation MHz EPROM Program Memory x12 words 2K ROM Program Memory x12 words RAM Data Memory bytes 2K 72 73 2K 73 Idi Timer Module s TMRO TMRO TMRO TMRO UO Pins 20 20 12 12 Voltage Range Volts 2 5 6 25 2 5 6 25 2 0 6 25 2 5 6 25 Number of Instructions 33 33 33 33 Packages 28 pin DIP 28 pin DIP SOIC 18 pin DIP SOIC 18 pin DIP SOIC SOIC SSOP 20 pin SSOP 20 pin SSOP All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer except PIC16C52 selectable code protect and high UO current capability DS30390E page 266 1997 Microchip Technology Inc PIC16C 7X E 5 PIC16C55X Family of Devices PIC16C554 PIC16C556 1 PIC16C558 Maximum Frequency of Operation MHz M EPROM Program Memory x14 words lemor y Data Memory bytes 80 80 128 Timer Module s Mis 3E Comparators s Internal Reference Voltage Interrupt Sources 3 3 3 UO Pins 13 13 13 Voltage Range Volts 2 5 6 0 2 5 6 0 2 5 6 0 x MEM Brown out Reset 18 pin DIP 18 pin DIP
302. ip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING PWRT Time out 32 OSC SC d Time out Internal i d RESET i Watchdog r d Timer RESET i FIGURE 19 5 BROWN OUT RESET TIMING TABLE 19 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REQUIREMENTS Parameter Sym_ Characteristic Min Typt Max Units Conditions No 30 TmcL MCLR Pulse Width low 2 us VDD 5V 40 C to 125 C 31 Twdt Watchdog Timer Time out Period 7 18 33 ms VDD 5V 40 C to 125 C No Prescaler 32 Tost Oscillation Start up Timer Period 1024Tosc Tosc OSC period 33 Tpwrt Power up Timer Period 28 72 132 ms VDD 5V 40 C to 125 C 34 Tioz UO Hi impedance from MCLR Low 2 1 us or Watchdog Timer Reset 35 TBOR Brown out Reset pulse width 100 us VDD lt BVDD D005 R These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 209 PIC16C7X 72 74 77 74A 76 73 73A Applicable Devices FIGURE 1
303. ister f If d is O the result is stored in the W register If d is 1 the result is stored back in register f 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination e XORWFE REG 1 Before Instruction REG OxAF W OxB5 After Instruction REG Ox1A W 0xB5 DS30390E page 162 1997 Microchip Technology Inc PIC16C7X 16 0 DEVELOPMENT SUPPORT 16 1 Development Tools The PIC16 17 microcontrollers are supported with a full range of hardware and software development tools PICMASTER PICMASTER CE Real Time In Circuit Emulator e ICEPIC Low Cost PIC16C5X and PIC16CXXX In Circuit Emulator PRO MATE II Universal Programmer PICSTART Plus Entry Level Prototype Programmer PICDEM 1 Low Cost Demonstration Board PICDEM 2 Low Cost Demonstration Board PICDEM 3 Low Cost Demonstration Board MPASM Assembler MPLAB SIM Software Simulator MPLAB C C Compiler Fuzzy logic development system fuzzyTECH MP 16 2 PICMASTER High Performance Universal In Circuit Emulator with MPLAB IDE The PICMASTER Universal In Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12C5XX PIC14C000 PIC16C5X PIC16CXXX and PIC17CXX families PICMASTER is supplied with the MPLAB Integrated Development Environment IDE which allows editing make and do
304. ister to a 10 bit duty cycle register CCPRxH CCPRxL lt 5 4 gt as well as to an 8 bit period register PR2 When the TMR2 reg ister Duty Cycle register the CCPx pin will be forced low When TMR2 PR2 TMR2 is cleared to 00h an interrupt can be generated and the CCPx pin if an out put will be forced high 1997 Microchip Technology Inc DS30390E page 57 PIC16C7X NOTES DS30390E page 58 1997 Microchip Technology Inc PIC16C7X 7 0 TIMERO MODULE The TimerO module timer counter has the following fea tures 8 bit timer counter Readable and writable 8 bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Figure 7 1 is a simplified block diagram of the TimerO module Timer mode is selected by clearing bit TOCS OPTION 5 In timer mode the TimerO module will increment every instruction cycle without prescaler If the TMRO register is written the increment is inhibited for the following two instruction cycles Figure 7 2 and Figure 7 3 The user can work around this by writing an adjusted value to the TMRO register Counter mode is selected by setting bit TOCS OPTION 5 In counter mode TimerO will increment either on every rising or falling edge of pin RA4 TOCKI The incrementing edge is determined by the TimerO FIGURE 7 1 TIMERO BLOCK DIAGRAM Note 1 TOCS s1
305. it any current flowing into MCLR from external capacitor C in the event of MCLR VPP pin break down due to Electrostatic Discharge ESD or Electrical Overstress EOS FIGURE 14 14 EXTERNAL BROWN OUT PROTECTION CIRCUIT 1 PIC16CXX This circuit will activate reset when VDD goes below Vz 0 7V where Vz Zener voltage Internal brown out detection on the PIC16C72 73A 74A 76 77 should be dis abled when using this circuit Resistors should be adjusted for the char acteristics of the transistor FIGURE 14 15 EXTERNAL BROWN OUT PROTECTION CIRCUIT 2 MCLR PIC16CXX This brown out circuit is less expensive albeit less accurate Transistor Q1 turns off when VDD is below a certain level such that R1 serie rau VDD RT R2 Internal brown out detection on the PIC16C72 73A 74A 76 77 should be disabled when using this circuit Resistors should be adjusted for the characteristics of the transistor DS30390E page 140 1997 Microchip Technology Inc PIC16C7X 14 5 Interrupts Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C7X family has up to 12 sources of interrupt The interrupt control register INTCON records individ ual interrupt requests in flag bits It also has individual and global interrupt enable bits Note Individual interrupt flag bits are set regard less of the status of their corresponding mask bit or the GIE bit A global
306. ith all I O pins in hi impedance state and tied to VOD and Vss 4 For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula Ir VDD 2Rext mA with Rext in kOhm 5 Timer1 oscillator when enabled adds approximately 20 uA to the specification This value is from charac terization and is for design guidance only This is not tested 6 The A current is the additional current consumed when this peripheral is enabled This current should be added to the base IDD or IPD measurement DS30390E page 202 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19 2 DC Characteristics PIC16LC73A 74A 04 Commercial Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt Ta lt 85 C for industrial and 0 C TA 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 2 5 6 0 V LB XT RC osc configuration DC 4 MHz D002 RAM Data Retention VDR 1 5 V Voltage Note 1 D003 VDD start voltage to VPOR Vss V See section on Power on Reset for details ensure internal Power on Reset signal D004 VDop rise rate to ensure SvDD 0 05 E V ms See section on Power on Reset for details internal Power on Reset signal D005 Brown out R
307. ld be written to TX9D TXSTA lt 0 gt The ninth bit must be written before writing the 8 bit data to the TXREG reg ister This is because a data write to the TXREG regis ter can result in an immediate transfer of the data to the TSR register if the TSR is empty In such a case an incorrect ninth data bit maybe loaded in the TSR regis ter TXREG register Pin Buffer and Control DS30390E page 106 RC6 TX CK pin 1997 Microchip Technology Inc PIC16C7X Steps to follow when setting up an Asynchronous 4 f9 bit transmission is desired then set transmit Transmission bit TX9 1 Initialize the SPBRG register for the appropriate 5 Enable the transmission by setting bit TXEN baud rate If a high speed baud rate is desired which will also set bit TXIF set bit BRGH Section 12 1 6 f 9 bit transmission is selected the ninth bit 2 Enable the asynchronous serial port by clearing should be loaded in bit TX9D bit SYNC and setting bit SPEN 7 Load data to the TXREG register starts trans 3 f interrupts are desired then set enable bit mission TXIE FIGURE 12 8 ASYNCHRONOUS MASTER TRANSMISSION C Write to TXREG d b BRG output Word 1 outpu shift clock Ls l Lo 0 N Start Bit lt Bito x Bii Xx 0 X BR y StopBit m RC6 TX CK pin WORD 1 TXIF bit 9 Transmit buffer reg empty flag l e WORD 1
308. le 2 Example 3 Subtract W from f label SUBWF fd O lt f lt 127 de 0 1 f W gt destination C DC Z 00 0010 dfff ffff Subtract 2 s complement method W reg ister from register f If d is O the result is stored in the W register If d is 1 the result is stored back in register f 1 1 Q1 Q2 Q3 Q4 Write to destination Read Process register f data Decode SUBWF REG1 1 Before Instruction REG1 W C Z NN D After Instruction REG1 W C Z result is positive G D Before Instruction REG1 W C Z Ss After Instruction REG1 W C Z Sch Before Instruction REG1 W C Z After Instruction REG1 OxFF W 2 C 0 result is negative Z 0 NN ND ND result is zero M r ND zk M OH SWAPF Syntax Operands Operation Status Affected Swap Nibbles in f label SWAPF LO O lt f lt 127 de 0 1 f lt 3 0 gt destination lt 7 4 gt f lt 7 4 gt gt destination lt 3 0 gt None Encoding 00 1110 dfff ffff Description The upper and lower nibbles of register IT are exchanged If d is O the result is placed in W register If d is 1 the result is placed in register f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f data destination Example SWAPF REG
309. le 20 5 Table 20 6 Table 20 7 Table 20 8 Table 20 9 Table 20 10 Table 20 11 Table 20 12 Table 20 13 Table 20 14 Table 21 1 Table 21 2 Table E 1 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices 220 External Clock Timing Requirements cceceseeesstesseeceseeneseeoneees 226 CLKOUT and UO Timing Requirements 227 Reset Watchdog Timer Oscillator Start up Timer Power up Timer and brown out reset Requirements esee 228 TimerO and Timer1 External Clock Requirements eene 229 Capture Compare PWM Requirements CCP1 and CCP2 230 Parallel Slave Port Requirements PIG16G77 aite ter tiet SPI Mode requirements DC Bus Start Stop Bits Requirements 235 DC Bus Data Requirements 236 USART Synchronous Transmission Requirements eren 237 USART Synchronous Receive Requirements eeeeeeeenene 237 A D Converter Characteristics 238 PIC16C76 77 04 Commercial Industrial Extended PIC16C76 77 10 Commercial Industrial Extended PIC16C76 77 20 Commercial Industrial Extended PIC16LC76 77 04 Commercial Industrial A D Conversion Requirements RC Oscillator Frequencies Capacitor Selection for
310. le word instructions A 14 bit wide program memory access bus fetches a 14 bit instruction in a single cycle A two stage pipeline overlaps fetch and execution of instruc tions Example 3 1 Consequently all instructions 35 execute in a single cycle 200 ns 20 MHz except for program branches The table below lists program memory EPROM and data memory RAM for each PIC16C7X device Device Program Data Memory Memory PIC16C72 2K x 14 128 x 8 PIC16C73 4K x 14 192 x 8 PIC16C73A 4K x 14 192 x 8 PIC16C74 4K x 14 192 x 8 PIC16C74A 4K x 14 192 x 8 PIC16C76 8K x 14 368 x 8 PIC16C77 8K x 14 386 x 8 The PIC16CXX can directly or indirectly address its register files or data memory All special function regis ters including the program counter are mapped in the data memory The PIC16CXX has an orthogonal sym metrical instruction set that makes it possible to carry out any operation on any register using any addressing mode This symmetrical nature and lack of special optimal situations make programming with the PIC16CXX simple yet efficient In addition the learning curve is reduced significantly PIC16CXX devices contain an 8 bit ALU and working register The ALU is a general purpose arithmetic unit It performs arithmetic and Boolean functions between the data in the working register and any register file The ALU is 8 bits wide and capable of addition sub traction shift and logical operati
311. leared in soft ware It will reset only when new data is loaded into the TXREG register While flag bit TXIF indicated the sta tus of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register Sta tus bit TRMT is a read only bit which is set when the TSR register is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty Note 1 The TSR register is not mapped in data memory so it is not available to the user Note 2 Flag bit TXIF is set when enable bit TXEN is set Transmission is enabled by setting enable bit TXEN TXSTA lt 5 gt The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator BRG has produced a shift clock Figure 12 7 The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN Normally when transmission is first started the TSR register is empty so a transfer to the TXREG register will result in an immediate trans fer to TSR resulting in an empty TXREG A back to back transfer is thus possible Figure 12 9 Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmit ter As a result the RC6 TX CK pin will revert to hi impedance In order to select 9 bit transmission transmit bit TX9 TXSTA lt 6 gt should be set and the ninth bit shou
312. lifier output It is enabled by setting control bit TI OSCEN T1CON 3 The oscilla tor is a low power oscillator rated up to 200 kHz It will continue to run during SLEEP It is primarily intended for a 32 kHz crystal Table 8 1 shows the capacitor selection for the Timer1 oscillator The Timer1 oscillator is identical to the LP oscillator The user must provide a software time delay to ensure proper oscillator start up TABLE 8 1 CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq C1 C2 LP 32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only Crystals Tested 32 768 kHz Epson C 001R32 768K A 20 PPM 100 kHz Epson C 2 100 00 KC P 20 PPM 200 kHz STD XTL 200 000 kHz 20 PPM Note 1 Higher capacitance increases the stability of oscillator but also increases the start up time 2 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropri ate values of external components 1997 Microchip Technology Inc DS30390E page 67 PIC16C7X 8 5 Resetting Timer1 using a CCP Trigger Output Applicable Devices 72 73 73A 74 74A 76 77 The CCP2 module PIC16C72 device If the CCP1 or CCP2 module is configured in compare mode to generate a special event trigger CCP1M3 CCP1MO 1011 this signal will reset Timer is
313. ltage is software select able to either the device s positive supply voltage VDD or the voltage level on the RA3 AN3 VREF pin FIGURE 13 1 ADCONO REGISTER ADDRESS 1Fh The A D converter has a unique feature of being able to operate while the device is in SLEEP mode To operate in sleep the A D conversion clock must be derived from the A D s internal RC oscillator The A D module has three registers These registers are A D Result Register ADRES A D Control Register 0 ADCONO A D Control Register 1 ADCON1 The ADCONO register shown in Figure 13 1 controls the operation of the A D module The ADCON1 regis ter shown in Figure 13 2 configures the functions of the port pins The port pins can be configured as ana log inputs RAS can also be a voltage reference or as digital I O R W 0 R W 0 R W 0 R W 0 R W 0 ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON R Readable bit bit7 bit 7 6 ADCS1 ADCSO A D Conversion Clock Select bits 00 Fosc 2 01 Fosc 8 10 Fosc 32 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset 11 FRC clock derived from an internal RC oscillator bit 5 3 CHS2 CHSO Analog Channel Select bits 000 channel 0 RAO ANO 001 channel 1 RA1 AN1 010 channel 2 RA2 AN2 011 channel 3 RA3 AN3 100 channel 4 RA5 AN4 101 channel 5 REO AN5 1 110 channel 6 RE1
314. ly To accomplish communication typically three pins are used Serial Data Out SDO Serial Data In SDI Serial Clock SCK Additionally a fourth pin may be used when in a slave mode of operation Slave Select SS When initializing the SPI several options need to be specified This is done by programming the appropriate control bits in the SSPCON register SSPCON 5 0 These control bits allow the following to be specified Master Mode SCK is the clock output Slave Mode SCK is the clock input e Clock Polarity Output Input data on the Rising Falling edge of SCK Clock Rate Master mode only Slave Select Mode Slave mode only The SSP consists of a transmit receive Shift Register SSPSR and a Buffer register SSPBUF The SSPSR shifts the data in and out of the device MSb first The SSPBUF holds the data that was written to the SSPSR until the received data is ready Once the 8 bits of data have been received that byte is moved to the SSPBUF register Then the Buffer Full bit BF SSPSTAT lt 0 gt and flag bit SSPIF are set This double buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received Any write to the SSPBUF register during transmission reception of data will be ignored and the write collision detect bit WCOL SSPCON lt 7 gt will be set User software must clear bit WCOL so that it can be determined if the followin
315. m Characteristic Min Max Units Conditions No 100 THIGH Clock high time 100 kHz mode 4 0 ZI us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 0 6 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 101 TLow Clock low time 100 kHz mode 4 7 us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 1 3 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 102 TR SDA and SCL rise 100 kHz mode 1000 ns time 400 kHz mode 20 0 1Cb 300 ns Cbis specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode 300 ns 400 kHz mode 20 0 1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU STA START condition 100 kHz mode 4 7 us Only relevant for repeated setup time 400 kHz mode 0 6 us START condition 91 THD STA START condition hold 100 kHz mode 4 0 us After this period the first clock time 400 kHz mode 0 6 us pulse is generated 106 THD DAT Data input hold time 100 kHz mode 0 ns 400 kHz mode 0 0 9 us 107 TSU DAT Data input setup time 100 kHz mode 250 ns Note 2 400 kHz mode 100 ns 92 Tsu sTO STOP condition setup 100 kHz mode 4 7 us time 400 kHz mode 0 6 us 109 TAA Output valid from 100 kHz mode 3500 ns Note 1 clock 400 kHz mode ns 110 TBUF Bus free time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 13 us before a new transmission can start Cb Bus capacitive loading 400 pF
316. m processes and procedures are QS 9000 compliant for its PICmicro 8 bit MCUs KEELO code hopping devices Serial EEPROMs and microperipheral products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 certified Printed on recycled paper Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information or infringement of patents or other intellectual property rights arising from such use or otherwise Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any intellectual property rights The Microchip logo and name are registered trademarks of Microchip Technology Inc in the U S A and other countries All rights reserved All other trademarks mentioned herein are the property of their respective companies 1999 Microchip Technology Inc
317. mber cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Standard OTP marking consists of Microchip part number year code week code facility code mask revision number and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price 1997 Microchip Technology Inc DS30390E page 261 PIC16C7X Package Marking Information Cont d 44 Lead TQFP Example NI S MMMMMMMM PIC16C74A XXXXXXXXXX 10 TQ XXXXXXXXXX O AABBCDE o AABBCDE Legend MM M Microchip part number information XX X Customer specific information AA Year code last 2 digits of calender year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured C Chandler Arizona U S A S Tempe Arizona U S A D4 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information Standard OTP marking consists of Microchip part number year code week code facility code mask revis
318. mode RC5 SDO 24 26 43 yo ST RC5 can also be the SPI Data Out SPI mode RC6 TX CK 25 27 44 UO ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock RC7 RX DT 26 29 1 yo ST RC7 can also be the USART Asynchronous Receive or Synchronous Data PORTD is a bi directional UO port or parallel slave port when interfacing to a microprocessor bus RDO PSPO 19 21 38 VO ST TTL RD1 PSP1 20 22 39 VO ST TTL RD2 PSP2 21 23 40 VO ST TTL RD3 PSP3 22 24 41 VO STATTL RD4 PSP4 27 30 2 VO srrTLG RD5 PSP5 28 31 3 VO Str RD6 PSP6 29 32 4 VO srrTLG RD7 PSP7 30 33 5 VO STATTL PORTE is a bi directional UO port REO RD AN5 8 9 25 VO ST TTL REO can also be read control for the parallel slave port or analog input5 RE1 WR AN6 9 10 26 UO ST TTL RE1 can also be write control for the parallel slave port or analog input6 RE2 CS AN7 10 11 27 UO ST TTL RE2 can also be select control for the parallel slave port or analog input7 Vss 12 31 13 34 6 29 P Ground reference for logic and I O pins VDD 11 32 12 35 7 28 P Positive supply for logic and UO pins NC 1 17 28 12 13 These pins are not internally connected These pins should 40 33 34 be left unconnected Legend input O output I O input output P power Not used TTL TTL input ST Schmitt Trigger input Note 1 This buffer is a Schmitt Trigger input when configured as an external interrupt 2 This buffer is a Schmitt Trigger
319. mode is also supported This device will communicate with both standard and fast mode devices if attached to the same bus The clock will determine the data rate The I C interface employs a comprehensive protocol to ensure reliable transmission and reception of data When transmitting data one device is the master which initiates transfer on the bus and generates the clock signals to permit that transfer while the other device s acts as the slave All portions of the slave protocol are implemented in the SSP module s hard ware except general call support while portions of the master protocol need to be addressed in the PIC16CXX software Table 11 3 defines some of the 12C bus terminology For additional information on the IC interface specification refer to the Philips docu ment The UC bus and how to use it 939839340011 which can be obtained from the Philips Corporation In the 12C interface protocol each device has an address When a master wishes to initiate a data trans fer it first transmits the address of the device that it wishes to talk to All devices listen to see if this is their address Within this address a bit specifies if the master wishes to read from write to the slave device The master and slave are always in opposite modes transmitter receiver of operation during a data trans fer That is they can be thought of as operating in either of these two relations Master transmitter and Slave r
320. mped ance D061 MCLR RA4 TOCKI 5 uA Vss lt VPIN lt VDD D063 OSC1 5 uA Vss VPIN lt VDD XT HS and LP osc configuration Output Low Voltage D080 IO ports VoL 06 V loL 8 5 mA VDD 4 5V 40 C to 85 C D080A 06 V loL 7 0 mA VDD 4 5V 40 C to 125 C D083 OSC2 CLKOUT RC osc config 0 6 V loL 1 6 mA VDD 4 5V 40 C to 85 C D083A 06 V loL 1 2 mA VDD 4 5V 40 C to 125 C These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 1997 Microchip Technology Inc DS30390E page 223 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended DC CHARACTERISTICS 40C lt TA lt 85 C for industrial and
321. n PORTB pins when read XXXX xxxx UUUU uuuu 07h PORTC PORTO Data Latch when written PORTC pins when read XXXX xxxx uuuu uuuu 08h Unimplemented 09h Unimplemented oAh 2 PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 OBh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u OCh PIR1 ADIF SSPIF CCP1IF TMR2IF TMRIIF 0 0000 0 0000 O0Dh Unimplemented OEh TMR1L Holding register for the Least Significant Byte of the 16 bit TMR1 register XXXX XXXX uuuu uuuu OFh TMR1H Holding register for the Most Significant Byte of the 16 bit TMR1 register XXXX XXXX uuuu uuuu 10h T1CON T1CKPS1 T1CKPSO TIOSCEN TISYNC TMR1CS TMR1ON 00 0000 uu uuuu 11h TMR2 Timer2 module s register 0000 0000 0000 0000 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 15h CCPR1L Capture Compare PWM Register LSB XXXX XXXX uuuu uuuu 16h CCPR1H Capture Compare PWM Register MSB XXXX XXXX uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1MO 00 0000 00 0000 18h Unimplemented 19h Unimplemented Ss 1Ah Unimplemented m 1Bh Unimplemented 1Ch Unimplemented
322. n Line PLA Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 10 0 10 A 5 080 0 200 Typical Typical Typical Typical Reference Reference Typical Typical Reference Reference L 2 921 3 683 0 115 0 145 N 40 40 40 40 S 1 270 0 050 S1 0 508 0 020 1997 Microchip Technology Inc DS30390E page 254 PIC16C7X 22 5 28 Lead Plastic Surface Mount SOIC Wide 300 mil Body SO e B a h x 45 A i 11 m Index Area H a AL EN VET NY Chamfer hx45 E 2 3 Y lt D gt Base Seating Gs p d H H Plane Plane A1 A Package Group Plastic SOIC SO Millimeters Inches Symbol Min Max Notes Min Max Notes a 0 8 0 8 A 2 362 2 642 0 093 0 104 A1 0 101 0 300 0 004 0 012 B 0 355 0 483 0 014 0 019 C 0 241 0 318 0 009 0 013 D 17 703 18 085 0 697 0 712 E 7 416 7 595 0 292 0 299 e 1 270 1 270 Typical 0 050 0 050 Typical H 10 007 10 643 0 394 0 419 h 0 381 0 762 0 015 0 030 L 0 406 1 143 0 016 0 045 N 28 28 28 28 CP 0 102 0 004 1997 Microchip Technology Inc DS30390E page 255 PIC16C7X
323. n out OSC2 CLKOUT Reset MCLR VDD Vss Time Timer2 Synchronous Serial Port Note 1 Higher order bits are from the STATUS register DS30390E page 10 1997 Microchip Technology Inc PIC16C7X FIGURE 3 2 PIC16C73 73A 76 BLOCK DIAGRAM Device Program Memory Data Memory RAM PIC16C73 4K x 14 192x8 PIC16C73A 4K x 14 192x8 PIC16C76 8K x14 368 x8 13 Z Program Counter RAO ANO EPROM f RA1 AN1 Program RA2 AN2 Memory 8 Level Stack RAM RA3 AN3 VREF 13 bit File RA4 TOCKI Registers RA5 SS AN4 Program Bus 14 Instruc DT RBO INT 7 Indirect Direct Addr Addr FSR reg x RB7 RB1 STATUS reg RCO T1OSO T1CKI RC1 T1OSI CCP2 RC2 CCP1 Power up RC3 SCK SCL Timer RC4 SDI SDA Instruction Oscillator RC5 SDO Decode amp Start up Timer BC6 TX CK Control Power on RC7 RX DT Reset e Timing Watchdog DK Generation Timer OSC1 CLKIN Brown gyt OSC2 CLKOUT Reset il MCLR VDD Vss TimerO Timer1 Timer2 i Synchronous Serial Port
324. nc DS30390E page 133 PIC16C7X 14 4 Power on Reset POR Power up Timer PWRT and Oscillator Start up Timer OST and Brown out Reset BOR Applicable Devices 72 73 73A 74 74A 76 77 14 4 1 POWER ON RESET POR A Power on Reset pulse is generated on chip when VDD rise is detected in the range of 1 5V 2 1V To take advantage of the POR just tie the MCLR pin directly or through a resistor to VDD This will elimi nate external RC components usually needed to create a Power on Reset A maximum rise time for VDD is specified See Electrical Specifications for details When the device starts normal operation exits the reset condition device operating parameters voltage frequency temperature must be met to ensure operation If these conditions are not met the device must be held in reset until the operating conditions are met Brown out Reset may be used to meet the startup conditions For additional information refer to Application Note AN607 Power up Trouble Shooting 14 4 POWER UP TIMER PWRT The Power up Timer provides a fixed 72 ms nominal time out on power up only from the POR The Power up Timer operates on an internal RC oscillator The chip is kept in reset as long as the PWRT is active The PWRT s time delay allows VDD to rise to an acceptable level A configuration bit is provided to enable disable the PWRT FIGURE 14 9 BROWN OUT SITUATIONS Internal Re
325. nce See characterization data for desired device for RC fre quency variation from part to part due to normal pro cess variation The variation is larger for larger R since leakage current variation will affect RC frequency more for large R and for smaller C since variation of input capacitance will affect RC frequency more See characterization data for desired device for varia tion of oscillator frequency due to VDD for given Rext Cext values as well as frequency variation due to oper ating temperature for given R C and VDD values The oscillator frequency divided by 4 is available on the OSC2 CLKOUT pin and can be used for test pur poses or to synchronize other logic see Figure 3 4 for waveform FIGURE 14 7 RC OSCILLATOR MODE Internal wm clock PIC16CXX OSC2 CLKOUT Fosc 4 DS30390E page 132 1997 Microchip Technology Inc PIC16C7X 143 Reset Applicable Devices 72 73 73A 74 74A 76 77 The PIC16CXX differentiates between various kinds of reset Power on Reset POR e MCLR reset during normal operation e MCLR reset during SLEEP WDT Reset normal operation e Brown out Reset BOR PIC16C72 73A 74A 76 7T Some registers are not affected in any reset condition their status is unknown on POR and unchanged in any other reset Most other registers are reset to a reset state on Power on Reset POR on the MCLR and WDT Reset on MCLR reset during SLEEP and Brown
326. nd 3 do NOT have to 2 MOVLW b xx0x0xxx Select clock source and prescale value of be included if the final desired 3 movwr oPTION REG other than 1 1 prescale value is other than 1 1 4 BCF STATUS RPO Bank 0 If 1 1 is final desired value then i 5 CLRF TMRO Clear TMRO and prescaler a temporary prescale value is set in lines 2 and 3 and the final BSF STATUS REL pBan ot prescale value will be set in lines 7 MOVLW pb xxxxlxxx Select WDT do not change prescale value 10 and 11 8 MOVWF OPTION REG 9 CLRWDT Clears WDT and prescaler 10 MOVLW Db xxxxlxxx Select new prescale value and WDT 11 MOVWF OPTION REG 12 BCF STATUS RPO Bank 0 To change prescaler from the WDT to the Timer0 mod ule use th e sequence shown in Example 7 2 EXAMPLE 7 2 CHANGING PRESCALER WDT TIMERO CLRWDT BSF MOVLW MOVWF BCF Clear WDT and prescaler STATUS RPO Bank 1 b xxxxO0xxx Select TMRO new prescale value and OPTION REG clock source STATUS RPO Bank 0 TABLE 7 1 REGISTERS ASSOCIATED WITH TIMERO Value on Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito por Value on all other resets BOR 01h 101h TMRO TimerO modules register XXXX XXXX uuuu uuuu OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh 81h 181h OPTION RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 85h TRISA
327. nd RC2 CCP1 Compare or PWM Mode Note Refer to Figure 20 1 for load conditions TABLE 20 6 CAPTURE COMPARE PWM REQUIREMENTS CCP1 AND CCP2 Param Sym Characteristic Min Typt Max Units Conditions No 50 TecL CCP1 and CCP2 No Prescaler 05TcY 20 ns TS Une PIC16C76 77 10 Da ee IK With Prescaler Bic 16L76 77 20 sie 51 TccH CCP41 and CCP2 No Prescaler 0 5TcY 20 ns input high time PIC16C76 77 10 ns With Prescaler 5 GLC76 77 20 MEN a ee 52 TecP CCP1 and CCP2 input period 3Tcv 40 ns N prescale N value 1 4 or 16 53 TccR CCP1 and CCP2 output rise time pIC16C76 77 10 25 ns PIC16LC76 77 25 45 ns 54 TccF CCP1 and CCP2 output fall time pIC16C76 77 10 25 ns PIC16LC76 77 25 45 ns These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 230 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 8 PARALLEL SLAVE PORT TIMING PIC16C77 RE2 CS RE1 WR RD7 RDO Note Refer to Figure 20 1 for load conditions TABLE 20 7 PARALLEL SLAVE PORT REQUIREMENTS PIC16C77 Parameter Sym Characteristic Min Typ
328. nnect procedure applies in most loca tions 1 Set your modem to 8 bit No parity and One stop 8N1 This is not the normal CompuServe setting which is 7E1 Dial your local CompuServe access number 3 Depress the Enter key and a garbage string will appear because CompuServe is expecting a 7E1 setting 4 Type depress the Enter key and Host Name will appear 5 Type MCHIPBBS depress the Enter key and you will be connected to the Microchip BBS IW In the United States to find the CompuServe phone number closest to you set your modem to 7E1 and dial 800 848 4480 for 300 2400 baud or 800 331 7166 for 9600 14400 baud connection After the system responds with Host Name type NETWORK depress the Enter key and follow CompuServe s directions For voice information or calling from overseas you may call 614 723 1550 for your local CompuServe number Microchip regularly uses the Microchip BBS to distribute technical information application notes source code errata sheets bug reports and interim patches for Microchip systems software products For each SIG a moderator monitors scans and approves or disap proves files submitted to the SIG No executable files are accepted from the user community in general to limit the spread of computer viruses Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides System users a listing of the latest version
329. nnen enne nen nennen Maximum current sunk by PORTA PORTB and PORTE combined Note 3 Maximum current sourced by PORTA PORTB and PORTE combined Note 3 Maximum current sunk by PORTC and PORTD combined Note 3 Maximum current sourced by PORTC and PORTD combined Note 3 Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Y 10H X VDD VOH x loH X Vol x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss PORTD and PORTE are not implemented on the PIC16C73A Note 3 T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability TABLE 19 1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION COMMERCIAL DEVICES PIC16C73A 04 PIC16C73A 10 PIC16C73A 20 PIC16LC73A 04 ose PIC16C74A 04 PIC16C74A 10 PIC16C74A 20 PIC16LC74A 04 rires VDD 4 0V to 6 0V Vop 4 5V to 5 5V V
330. ns DS30390E page 218 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 20 0 ELECTRICAL CHARACTERISTICS FOR PIC16C76 77 Absolute Maximum Ratings T Ambient temperature trder bias cie te cm e irren ege dede ir dd finale 55 to 125 C Storage temperature tente tede pe Rene pec E p E UR ini unes 65 C to 150 C Voltage on any pin with respect to Vss except VDD MCLR and RAA 0 3V to VDD 0 3V Voltage on VDD with respect to VSS eesessseeeseseeeeeenenen tenerent nennen nennen entere tenen esten tenen nns 0 3 to 7 5V Voltage on MCLR with respect to VSS Note 2 nennen 0 to 14V Voltage on RA4 with respecto VSS eere ce ede ec anode tese a ex dc tbe edd de descen 0 to 14V Total power dissipation Notoe 1 rerit tenet iere teni trt ars r tre MR eR REL ent es HERRERA ee UNE HER Peer entr Re 1 0W Maximum current out of VSS pin onec rer eia edion Ea aade caue e eurer sve estara nee de rings 300 mA Maximum current into VDD IP issn chase RUE phe edet ete Ra ne inner eae 250 mA Input clamp current liK VI 0 or VI gt VDD ire 20 mA Output clamp current IOK VO lt 0 or VO gt VDD eee 20 mA Maximum output current sunk by any HO pin iii 25 mA Maximum output current sourced by any I O pin nennen enne nen nennen 25 mA Maximum current
331. occurs while the GIE bit is being cleared the GIE bit may be unintentionally re enabled by the RETFIE instruction in the user s Interrupt Service Routine Refer to Section 14 5 for a detailed description Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt DS30390E page 32 1997 Microchip Technology Inc PIC16C7X 4 2 2 4 PIE REGISTER Applicable Devices Note Bit PEIE INTCON 6 must be set to 72 73 73A 74 74A 76 77 enable any peripheral interrupt This register contains the individual enable bits for the peripheral interrupts FIGURE 4 10 PIE1 REGISTER PIC16C72 ADDRESS 8Ch U 0 R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 ADIE SSPIE CCP1IE TMR2IE TMR1IE R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 Unimplemented Read as 0 bit 6 ADIE A D Converter Interrupt Enable bit 1 Enables the A D interrupt 0 Disables the A D interrupt bit 5 4 Unimplemented Read as 0 bit 3 SSPIE Synchronous Serial Port Interrupt Enable bit 1 Enables the SSP interrupt 0 Disables the SSP interrupt bit 2 CCP1IE CCP1 Int
332. ock RB7 28 28 UO TTL ST Interrupt on change pin Serial programming data PORTE is a bi directional UO port RCO T1OSO T1CKI 11 11 yo ST RCO can also be the Timer1 oscillator output or Timer1 clock input RC1 T1OSI CCP2 12 12 VO ST RC1 can also be the Timer1 oscillator input or Capture2 input Compare2 output PWM2 output RC2 CCP1 13 13 VO ST RC2 can also be the Capture1 input Compare1 output PWM1 output RC3 SCK SCL 14 14 1 0 ST RC3 can also be the synchronous serial clock input output for both SPI and EC modes RCA SDI SDA 15 15 UO ST RC4 can also be the SPI Data In SPI mode or data I O I C mode RC5 SDO 16 16 VO ST RC5 can also be the SPI Data Out SPI mode RC6 TX CK 17 17 VO ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock RC7 RX DT 18 18 1 0 ST RC7 can also be the USART Asynchronous Receive or Synchronous Data Vss 8 19 8 19 P Ground reference for logic and I O pins VDD 20 20 P Positive supply for logic and I O pins Legend input O output UO input output P power Not used TTL TTL input ST Schmitt Trigger input Note 1 This buffer is a Schmitt Trigger input when configured as the external interrupt 2 This buffer is a Schmitt Trigger input when used in serial programming mode 3 This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise DS30390E page 14 1997 Microchip Technology Inc PIC16C7X
333. ode See DC SSPADD5 iih oreet butt fee nee ebd oe tests 93 SSPADD Register sese 24 26 28 29 SSBB E LR ee nt te tte 29 93 SSPBUF Register sssssssssseeenee 25 27 E ee WEE 79 84 SSPCON Register icri perte eb re nentes 25 27 SSPEN EE 79 84 EE EIERE Eed 33 SSPIF bit 95 36 SSPMS3S SSPMO inst an Fette eere re 79 84 SSPOV un 79 84 94 SSPSTAT Zero nune tese iE 78 93 SSPSTAT Register 24 26 28 29 83 e s Ren semen atem mente EUN 40 QV6eHIOWS Sege needs neri 40 ll ot VE A0 Start bit S STATUS Register eg Geert 29 30 Stop bit x sone SoA ee UHR 78 83 Synchronous Serial Port SSP Block Diagram SPI Mode sss 80 SPI Master Slave Diagram eee 81 SPI Mode Synchronous Serial Port Enable bit SSPEN 79 84 DS30390E page 277 PIC16C7X Synchronous Serial Port Mode Select bits SSPMS SSPMQ nete ir eta teg 79 84 Synchronous Serial Port Module Synchronous Serial Port Status Register 83 T TOGS bit amp Aske AR nn Men Een 31 TICKPSO bit 65 T1CKPS1 bit 65 T CON ME 29 le el RTE ET 29 65 T1OSCEN bit RRE die T2CKPSO0 bit T2CKPS1 bit T2CON Register iinitan 29 70 NEE 121 Timer Modules Overview eese 57 TimerO EE PELO RETE 136 Timers TimerO Block Diagram 2 8 unies 59 E
334. oes not depend on the oscillator type Power down current is measured with the part in SLEEP mode with all I O pins in hi impedance state and tied to VOD and Vss 4 For RC osc configuration current through Rext is not included The current through the resistor can be esti mated by the formula Ir VDD 2Rext mA with Rext in kOhm 5 Timer1 oscillator when enabled adds approximately 20 uA to the specification This value is from charac terization and is for design guidance only This is not tested 6 The A current is the additional current consumed when this peripheral is enabled This current should be added to the base IDD or IPD measurement 1997 Microchip Technology Inc DS30390E page 203 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 19 3 DC Characteristics PIC16C73A 74A 04 Commercial Industrial Extended PIC16C73A 74A 10 Commercial Industrial Extended PIC16C73A 74A 20 Commercial Industrial Extended PIC16LC73A 74A 04 Commercial Industrial Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA lt 125 C for extended DC CHARACTERISTICS 40 C lt TA lt 85 C for industrial and 0 C TA lt 70 C for commercial Operating voltage VDD range as described in DC spec Section 19 1 and Section 19 2 Param Characteristic Sym Min Typ Max Units Conditions No Input Low Voltage I O ports VIL D030 with TTL
335. olumn is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 194 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 8 SPI MODE TIMING Note Refer to Figure 18 1 for load conditions TABLE 18 8 SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 70 TssL2scH SSJ to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time slave mode Tcv 20 ns 72 TscL SCK input low time slave mode Tcv 20 ns 73 TdiV2scH Setup time of SDI data input to SCK 50 ns TdiV2scL edge 74 TscH2diL Hold time of SDI data input to SCK 50 ns TscL2diL edge 75 TdoR SDO data output rise time 10 25 ns 76 TdoF SDO data output fall time 10 25 ns 77 TssH2doZ SST to SDO output hi impedance 10 50 ns 78 TscR SCK output rise time master mode 10 25 ns 79 TscF SCK output fall time master mode 10 25 ns 80 TscH2doV SDO data output valid after SCK 50 ns TscL2doV edge t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 195 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 9 I C BUS START STOP BITS TIMING
336. om an external asynchronous clock will guarantee a valid read taken care of in hardware However the user should keep in mind that reading the 16 bit timer in two 8 bit values itself poses certain problems since the timer may overflow between the reads For writes it is recommended that the user simply stop the timer and write the desired values A write conten tion may occur by writing to the timer registers while the register is incrementing This may produce an unpre dictable value in the timer register Reading the 16 bit value requires some care Example 8 1 is an example routine to read the 16 bit timer value This is useful if the timer cannot be stopped EXAMPLE 8 1 READING A 16 BIT FREE RUNNING TIMER All interrupts are disabled MOVF TMRIH W Read high byte MOVWF TMPH MOVF TMRIL W Read low byte MOVWF TMPL MOVE TMR1H W Read high byte SUBWF TMPH W Sub 1st read with 2nd read BTFSC STATUS Z Is result 0 GOTO CONTINUE Good 16 bit read TMRIL may have rolled over between the read of the high and low bytes Reading the high and low bytes now will read a good value Se se Ne Ne Ne MOVF TMR1H W Read high byte MOVWF TMPH MOVF TMRIL W Read low byte MOVWF TMPL Re enable the Interrupt if required CONTINUE Continue with your code 8 4 Timer1 Oscillator Applicable Devices 72 73 73A 74 74A 76 77 A crystal oscillator circuit is built in between pins T10SI input and T1OSO amp
337. on of the PWM frequency The postscaler could be used to have a servo update rate at a different fre quency than the PWM output 10 3 2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON lt 5 4 gt bits Up to 10 bit resolution is available the CCPR1L contains the eight MSbs and the CCP1CON lt 5 4 gt contains the two LSbs This 10 bit value is represented by CCPR1L CCP1CON 5 4 The following equation is used to calculate the PWM duty cycle in time PWM duty cycle CCPRIL CCP1CON 5 45 Tosc TMR2 prescale value CCPR1L and CCP1CON lt 5 4 gt can be written to at any time but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs i e the period is complete In PWM mode CCPR1H is a read only register The CCPR1H register and a 2 bit internal latch are used to double buffer the PWM duty cycle This double buffering is essential for glitchless PWM operation When the CCPR1H and 2 bit latch match TMR2 con catenated with an internal 2 bit Q clock or 2 bits of the TMR2 prescaler the CCP1 pin is cleared Maximum PWM resolution bits for a given PWM frequency Note If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared DS30390E page 74 1997 Microchip Technology Inc PIC16C7X EXAMPLE 10 2 PWM PERIOD AND DUTY CYCLE CALCULATION Desired PWM frequency is 78 125 kHz Fo
338. ons Unless otherwise mentioned arithmetic operations are two s comple ment in nature In two operand instructions typically one operand is the working register W register The other operand is a file register or an immediate con stant In single operand instructions the operand is either the W register or a file register The W register is an 8 bit working register used for ALU operations It is not an addressable register Depending on the instruction executed the ALU may affect the values of the Carry C Digit Carry DC and Zero Z bits in the STATUS register The C and DC bits operate as a borrow bit and a digit borrow out bit respectively in subtraction See the SUBLW and SUBWF instructions for examples 1997 Microchip Technology Inc DS30390E page 9 PIC16C7X FIGURE 3 1 PIC16C72 BLOCK DIAGRAM Data Bus EPROM Program Counter lt RAO ANO Program RA1 AN1 Memory RAM RA2 AN2 8 Level Stack File RA3 AN3 VREF 2k x 14 13 bit Registers RA4 TOCKI RA5 SS AN4 Program Bus i Instruction reg RBO INT Direct Addr 7 RB7 RB1 STATUS reg RCO T1OSO T1CKI RC1 T1OSI RE RC2 CCP1 Power up RC3 SCK SCL Timer RC4 SDI SDA Instruction Oscillator RC5 SDO Decode amp Start up Timer RC6 Gontro Power on RC7 Reset Timing Watchdog k Generation Timer OSC1 CLKIN Brow
339. option This prescaler can be assigned to either the TimerO module or the Watchdog Timer Bit PSA OPTION lt 3 gt assigns the prescaler and bits PS2 PSO OPTION lt 2 0 gt determine the prescaler value TimerO can increment at the following rates 1 1 when pres caler assigned to Watchdog timer 1 2 1 4 1 8 1 16 1 32 1 64 1 128 and 1 256 TimerO only Synchronization of the external clock occurs after the prescaler When the prescaler is used the external clock frequency may be higher then the device s fre quency The maximum frequency is 50 MHz given the high and low time requirements of the clock 6 2 Timer1 Overview Applicable Devices 72 73 73A 74 74A 76 77 Timer1 is a 16 bit timer counter The clock source can be either the internal system clock Fosc 4 an external clock or an external crystal Timeri can operate as either a timer or a counter When operating as a counter external clock source the counter can either operate synchronized to the device or asynchronously to the device Asynchronous operation allows Timer1 to operate during sleep which is useful for applications that require a real time clock as well as the power sav ings of SLEEP mode Timer1 also has a prescaler option which allows Timer1 to increment at the following rates 1 1 1 2 1 4 and 1 8 Timer1 can be used in conjunction with the Capture Compare PWM module When used with a CCP module Timer1 is the time base for 16 bit C
340. or when enabled adds approximately 20 uA to the specification This value is from charac terization and is for design guidance only This is not tested DS30390E page 184 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18 2 DC Characteristics PIC16LC73 74 04 Commercial Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for industrial and 0 C TA 70 C for commercial Param Characteristic Sym Min Typt Max Units Conditions No D001 Supply Voltage VDD 3 0 6 0 V LB XT RC osc configuration DC 4 MHz D002 RAM Data Retention VDR 1 5 V Voltage Note 1 D003 VDD start voltage to VPOR Vss S V See section on Power on Reset for details ensure internal Power on Reset signal D004 VDD rise rate to ensure SvpD 0 05 Vims See section on Power on Reset for details internal Power on Reset signal D010 Supply Current Note 2 5 IDD 2 0 3 8 mA XT RC osc configuration Fosc 4 MHz VDD 3 0V Note 4 D010A S 22 5 48 uA LP osc configuration Fosc 32 kHz VDD 3 0V WDT disabled D020 Power down Current IPD 7 5 30 HA D021 Note 3 5 0 9 13 5 LA D021A 0 9 18 LA D OCOZOPIIS CILQICCOUUTCEG ICSQISRCIHEDCOCIRIUI C RULLUELCLIILLELELCEOU E CCEGLECOANAUILIE QHEGLCULANSIIOUREZELT 1997 Microchip Technology Inc DS30390E page 185 PIC16C7X
341. osc mode 20 5 us LP osc mode Oscillator Period 250 ns RC osc mode Note 1 250 10 000 ns XT osc mode 250 250 ns HS osc mode 04 100 250 ns HS osc mode 10 50 250 ns HS osc mode 20 5 us LP osc mode 2 Tcv Instruction Cycle Time Note 1 200 DC ns Tcy 4 Fosc 3 TosL External Clock in OSC1 High or 100 ns XT oscillator TosH Low Time 2 5 us LP oscillator 15 ns HSoscillator 4 TosR External Clock in OSC1 Rise or 25 ns XT oscillator TosF Fall Time 50 ns LP oscillator 15 ns HSoscillator T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Instruction cycle period Tcv equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current con sumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the Max cycle time limit is DC no clock for all devices 1997 Microchip Technology Inc DS30390E page 173 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 3 CLKOUT
342. out occurred and caused wake up The following peripheral interrupts can wake the device from SLEEP 1 TMR1 interrupt Timeri must be operating as an asynchronous counter SSP Start Stop bit detect interrupt SSP transmit or receive in slave mode SPI PC CCP capture mode interrupt Parallel Slave Port read or write A D conversion when A D clock source is RC Special event trigger Timer1 in asynchronous mode using an external clock 8 USART TX or RX synchronous slave mode SERGE Other peripherals cannot generate interrupts since dur ing SLEEP no on chip Q clocks are present When the SLEEP instruction is being executed the next instruction PC 1 is pre fetched For the device to wake up through an interrupt event the corresponding interrupt enable bit must be set enabled Wake up is regardless of the state of the GIE bit If the GIE bit is clear disabled the device continues execution at the instruction after the SLEEP instruction If the GIE bit is set enabled the device executes the instruction after the SLEEP instruction and then branches to the inter rupt address 0004h In cases where the execution of the instruction following SLEEP is not desirable the user should have a NOP after the SLEEP instruction 14 8 2 WAKE UP USING INTERRUPTS When global interrupts are disabled GIE cleared and any interrupt source has both its interrupt en
343. output fall time PIC16C72 10 25 ns PIC16LC72 25 45 ns T These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 177 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 17 8 SPI MODE TIMING 79 78 80 eme m f i 1 NS Lafen j 75 76 CC 0 09 ds 78 Note Refer to Figure 17 1 for load conditions TABLE 17 7 SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 70 TssL2scH SSJ to SCK or SCKT input Tcv ns TssL2scL 71 TscH SCK input high time slave mode Tcv 20 ns 72 TscL SCK input low time slave mode Tcv 20 ns 73 TdiV2scH Setup time of SDI data input to SCK 50 ns TdiV2scL edge 74 TscH2diL Hold time of SDI data input to SCK 50 ns TscL2diL edge 75 TdoR SDO data output rise time 10 25 ns 76 TdoF SDO data output fall time 10 25 ns 77 TssH2doZ SST to SDO output hi impedance 10 50 ns 78 TscR SCK output rise time master mode 10 25 ns 79 TscF SCK output fall time master mode 10 25 ns 80 TscH2doV SDO data output valid after SCK 50 ns TscL2doV edge t Data in Typ column is at 5
344. ow Note 1 PIC16C73 73A 76 devices do not have a Parallel Slave Port implemented this bit location is reserved on these devices always maintain this bit clear Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON 7 User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt DS30390E page 36 1997 Microchip Technology Inc PIC16C7X 4 2 2 6 PIE2 REGISTER Applicable Devices 72 73 73A 74 74A 76 77 This register contains the individual enable bit for the CCP2 peripheral interrupt FIGURE 4 14 PIE2 REGISTER ADDRESS 8Dh U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 CCP2IE Ip Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 1 Unimplemented Read as 0 bit 0 CCP2IE CCP2 Interrupt Enable bit 1 Enables the CCP2 interrupt 0 Disables the CCP2 interrupt 1997 Microchip Technology Inc DS30390E page 37 PIC16C7X 4 2 2 7 PIR2 REGISTER Applicable Devices Note Interrupt flag bits get set when an interrupt 72173 73A 74174A 76177 condition occurs regardless of the state of its corresponding enable bit or the global This register contains the CCP2 in
345. page 263 PIC16C7X APPENDIX C WHAT S NEW Added the following devices PIC16C76 PIC16C77 Removed the PIC16C710 PIC16C71 PIC16C711 from this datasheet Added PIC16C76 and PIC16C77 devices The PIC16C76 77 devices have 368 bytes of data memory distributed in 4 banks and 8K of program memory in 4 pages These two devices have an enhanced SPI that supports both clock phase and polarity The USART has been enhanced When upgrading to the PIC16C76 77 please note that the upper 16 bytes of data memory in banks 1 2 and 3 are mapped into bank 0 This may require relocation of data memory usage in the user application code Added Q cycle definitions to the Instruction Set Sum mary section APPENDIX D WHAT S CHANGED Minor changes spelling and grammatical changes Added the following note to the USART section This note applies to all devices except the PIC16C76 and PIC16C77 For the PIC16C73 73A 74 74A the asynchronous high speed mode BRGH 1 may experience a high rate of receive errors It is recommended that BRGH 0 If you desire a higher baud rate than BRGH 0 can support refer to the device errata for additional information or use the PIC16C76 77 Divided SPI section into SPI for the PIC16C76 77 and SPI for all other devices DS30390E page 264 1997 Microchip Technology Inc PIC16C 7X APPENDIX E PIC16 17 MICROCONTROLLERS E 1 PIC12CXXX Family of Devices PIC1
346. parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested S This specification ensured by design 1 ADRES register may be read on the following Tcy cycle See Section 13 1 for min conditions DS30390E page 182 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18 0 ELECTRICAL CHARACTERISTICS FOR PIC16C73 74 Absolute Maximum Ratings T Ambient temperature trder bias cic te cm irre tee eg eine dd dee decere 55 to 125 C TT 65 C to 150 C 0 3V to VDD 0 3V Storage temperature Voltage on any pin with respect to VSs except VDD MCLR and RA4 Voltage on VDD with respect to VSS 0 3 to 7 5V Voltage on MCLR with respect to VSS Note 2 nennen 0 to 14V Voltage on RA4 with respecto VSS eere ce ede ec anode tese a ex dc tbe edd de descen 0 to 14V Total power dissipation Notoe 1 rerit tenet iere teni trt ars r tre MR eR REL ent es HERRERA ee UNE HER Peer entr Re 1 0W Maximum current out of VSS pin onec rer eia edion Ea aade caue e eurer sve estara nee de rings 300 mA Maximum current into VDD IP issn chase RUE phe edet ete Ra ne inner eae 250 mA Input clamp current liK VI 0 or VI gt VDD ire 20 mA Output clamp
347. pecific use applications Provides translation of Assembler source code to object code for all Microchip microcontrollers Macro assembly capability Produces all the files Object Listing Symbol and special required for symbolic debug with Microchip s emulator systems Supports Hex default Decimal and Octal source and listing formats MPASM provides a rich directive language to support programming of the PIC16 17 Directives are helpful in making the development of your assemble source code shorter and more maintainable 16 11 Software Simulator MPLAB SIM The MPLAB SIM Software Simulator allows code development in a PC host environment It allows the user to simulate the PIC16 17 series microcontrollers on an instruction level On any given instruction the user may examine or modify any of the data areas or provide external stimulus to any of the pins The input output radix can be set by the user and the execution can be performed in single step execute until break or in a trace mode MPLAB SIM fully supports symbolic debugging using MPLAB C and MPASM The Software Simulator offers the low cost flexibility to develop and debug code out side of the laboratory environment making it an excel lent multi project software development tool 16 12 C Compiler MPLAB C The MPLAB C Code Development System is a complete C compiler and integrated development environment for Microchip s PIC16 17 family of mi
348. ped ance If either bit CREN or bit SREN is set during a transmission the transmission is aborted and the DT pin reverts to a hi impedance state for a reception The CK pin will remain an output if bit CSRC is set internal clock The transmitter logic however is not reset although it is disconnected from the pins In order to reset the transmitter the user has to clear bit TXEN If bit SREN is set to interrupt an on going transmission and receive a single word then after the single word is received bit SREN will be cleared and the serial port will revert back to transmitting since bit TXEN is still set The DT line will immediately switch from hi impedance receive mode to transmit and start driving To avoid this bit TXEN should be cleared In order to select 9 bit transmission the TX9 TXSTA lt 6 gt bit should be set and the ninth bit should be written to bit TX9D TXSTA lt 0 gt The ninth bit must be written before writing the 8 bit data to the TXREG register This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register if the TSR is empty If the TSR was empty and the TXREG was written before writing the new TX9D the present value of bit TX9D is loaded Steps to follow when setting up a Synchronous Master Transmission 1 Initialize the SPBRG register for the appropriate baud rate Section 12 1 2 Enable the synchronous master serial port by setting bits SYN
349. peration Operation HERE DECFSZ CNT 1 GOTO LOOP CONTINUE Before Instruction PC address HERE After Instruction CNT CNT 1 if CNT 0 PC address CONTINUE if CNT 0 PC address HERE 1 1997 Microchip Technology Inc DS30390E page 153 PIC16C7X GOTO Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity 1st Cycle 2nd Cycle Example Unconditional Branch abel GOTO k 0 lt k lt 2047 k PC 10 0 PCLATH 4 3 PC lt 12 11 gt None 10 lkkk kkkk kkkk GOTO is an unconditional branch The eleven bit immediate value is loaded into PC bits lt 10 0 gt The upper bits of PC are loaded from PCLATH lt 4 3 gt GOTO is a two cycle instruction 1 2 Q1 Q2 Q3 Q4 Decode Read Process Write to literal k data PC No No No No Operation Operation Operation Operation GOTO THERE After Instruction PC Address THERE INCF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Example Increment f label INCF f d 0 lt f lt 127 de 0 1 f 1 destination Z 00 1010 dfff ffff The contents of register f are incre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination T INCF
350. pins For the pins to behave as the serial port function they must have their data direction bits in the TRISC register appro priately programmed That is SDI must have TRISC 4 set e SDO must have TRISC lt 5 gt cleared SCK Master mode must have TRISC lt 3 gt cleared SCK Slave mode must have TRISC lt 3 gt set e SS must have TRISA lt 5 gt set Any serial port function that is not desired may be over ridden by programming the corresponding data direc tion TRIS register to the opposite value An example would be in master mode where you are only sending data to a display driver then both SDI and SS could be used as general purpose outputs by clearing their corresponding TRIS register bits Figure 11 10 shows a typical connection between two microcontrollers The master controller Processor 1 initiates the data transfer by sending the SCK signal Data is shifted out of both shift registers on their pro grammed clock edge and latched on the opposite edge of the clock Both processors should be programmed to same Clock Polarity CKP then both controllers would send and receive data at the same time Whether the data is meaningful or dummy data depends on the application firmware This leads to three scenarios for data transmission Master sends data Slave sends dummy data Master sends data Slave sends data Master sends dummy data Slave sends data The master can initiate the data transf
351. pplicable Devices 72 73 73A 74 74A v6 77 FIGURE 17 6 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS RA4 TOCKI A TMRO or TMR1 Note Refer to Figure 17 1 for load conditions TABLE 17 5 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 40 TtOH TOCKI High Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns Parameter 42 41 TtOL TOCKI Low Pulse Width No Prescaler 0 5TCY 20 ns Must also meet With Prescaler 10 ns parameter 42 42 TtOP TOCKI Period No Prescaler Tcy 40 ns With Prescaler Greater of ns N prescale value 20 or Tcv 40 2 4 256 N 45 TtH T1CKI High Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 46 TOL T1CKI Low Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ee ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 47 TOP T1CKI input period Synchronous PIC16C7X Greater of ns N prescale value 30 op Tcv 40 1 2 4 8 N P
352. r the A D to meet its specified accuracy EQUATION 13 1 A D MINIMUM CHARGING TIME VHOLD VREF VREF 512 e 1 e TCAP CHOLD RIc RSS RS Given VHOLD VREF 512 for 1 2 LSb resolution The above equation reduces to Tcap 51 2 pF 1 kQ Rss Rs In 1 511 Example 13 1 shows the calculation of the minimum required acquisition time TACQ This calculation is based on the following system assumptions CHOLD 51 2 pF Rs 10 ko 1 2 LSb error FIGURE 13 4 ANALOG INPUT MODEL VDD 5V gt Rss 7 ko Temp application system max 50 C VHOLD 0 t 0 Note 1 The reference voltage VREF has no effect on the equation since it cancels itself out Note 2 The charge holding capacitor CHOLD is not discharged after each conversion Note 3 The maximum recommended impedance for analog sources is 10 kQ This is required to meet the pin leakage specifi cation Note 4 After a conversion has completed a 2 0TAD delay must complete before acqui sition can begin again During this time the holding capacitor is not connected to the selected A D input channel EXAMPLE 13 1 CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ Amplifier Settling Time Holding Capacitor Charging Time Temperature Coefficient TACQ 5 us TCAP Temp 25 C 0 05 us C TCAP CHOLD RIC Rss RS In 1 511 51 2 pF 1 KQ 7 KQ 10 kQ In 0 0020 51 2 pF 18 kQ In 0 0020 0 921 us 6 2364 5 747 u
353. rcial Industrial Extended PIC16C72 20 Commercial Industrial Extended PIC16LC72 04 Commercial Industrial 181 A D Conversion Requirements 182 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices 183 1997 Microchip Technology Inc DS30390E page 283 PIC16C7X Table 18 2 Table 18 3 Table 18 4 Table 18 5 Table 18 6 Table 18 7 Table 18 8 Table 18 9 Table 18 10 Table 18 11 Table 18 12 Table 18 13 Table 18 14 Table 19 1 Table 19 2 Table 19 3 Table 19 4 Table 19 5 Table 19 6 Table 19 7 Table 19 8 Table 19 9 Table 19 10 Table 19 11 Table 19 12 Table 19 13 Table 19 14 external Clock Timing Requirements esee 189 CLKOUT and UO Timing Requirements eerte 190 Reset Watchdog Timer Oscillator Start up Timer and Power up Timer Requirements eese 191 TimerO and Timer1 External Clock Requirements eerte 192 Capture Compare PWM Requirements CCP1 and CCP2 193 Parallel Slave Port Requirements PIC16G 74 oit tente p SPI Mode Requirements DC Bus Start Stop Bits Requirements DC Bus Data Requirements USART Synchronous Transmission Requirements eese 198 usart Synchronous Receive PIC16C73 74 04 Commercial Indu
354. re 10 4 shows a simplified block diagram of the CCP module in PWM mode For a step by step procedure on how to set up the CCP module for PWM operation see Section 10 3 3 FIGURE 10 4 SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON lt 5 4 gt Duty cycle registers ean CCPR1L Reeg CCPR1H S arator RC2 CCP1 Note 1 Comparator TRISC lt 2 gt Clear Timer AS CCP1 pin and latch D C PR2 Note 1 8 bit timer is concatenated with 2 bit internal Q clock or 2 bits of the prescaler to create 10 bit time base A PWM output Figure 10 5 has a time base period and a time that the output stays high duty cycle The frequency of the PWM is the inverse of the period 1 period FIGURE 10 5 PWM OUTPUT a R a Duty Cycle TMR2 PR2 i TMR2 Duty Cycle TMR2 PR2 10 3 1 PWM PERIOD The PWM period is specified by writing to the PR2 reg ister The PWM period can be calculated using the fol lowing formula PWM period PR2 1 4 Tosc TMR2 prescale value PWM frequency is defined as 1 PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle TMR2 is cleared The CCP1 pin is set exception if PWM duty cycle 0 the CCP1 pin will not be set The PWM duty cycle is latched from CCPR1L into CCPR1H Note The Timer2 postscaler see Section 9 1 is not used in the determinati
355. rentiation between a Power on Reset The BOR status bit is a don t care and is POR to an external MCLR Reset or WDT Reset not necessarily predictable if the brown out Those devices with brown out detection circuitry con circuit E pue by clearing the BODEN tain an additional bit to differentiate a Brown out Reset bit in the Configuration word condition from a Power on Reset condition FIGURE 4 16 PCON REGISTER ADDRESS 8Eh U 0 U 0 U 0 U 0 U 0 U 0 R W 0 R W q ue POR BORU Readable bit bit 7 2 Unimplemented Read as 0 bit 1 POR Power on Reset Status bit 1 No Power on Reset occurred R bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset 0 A Power on Reset occurred must be set in software after a Power on Reset occurs bit 0 BOR Brown out Reset Status bit 1 No Brown out Reset occurred 0 A Brown out Reset occurred must be set in software after a Brown out Reset occurs Note 1 Brown out Reset is not implemented on the PIC16C73 74 1997 Microchip Technology Inc DS30390E page 39 PIC16C7X 4 3 PCL and PCLATH Applicable Devices 72 73 73A 74 74A 76 77 The program counter PC is 13 bits wide The low byte comes from the PCL register which is a readable and writable register The upper bits PC lt 12 8 gt are not readable but are indirectly writable through the PCLATH register On any reset the upper bits of the
356. requency DC 4 MHz RC osc mode Note 1 0 1 4 MHz XT osc mode 4 20 MHz HS osc mode 5 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 ns XT and RC osc mode Note 1 250 ns HS osc mode 04 100 ns HS osc mode 10 50 ns HS osc mode 20 5 us LP osc mode Oscillator Period 250 ns RC osc mode Note 1 250 10 000 ns XT osc mode 250 250 ns HS osc mode 04 100 250 ns HS osc mode 10 50 250 ns HS osc mode 20 5 us LP osc mode 2 Tcv Instruction Cycle Time Note 1 200 DC ns Tcy 4 Fosc 3 TosL External Clock in OSC1 High or 50 ns XT oscillator TosH Low Time 2 5 us LP oscillator 15 ns HSoscillator 4 TosR External Clock in OSC1 Rise or 25 ns XT oscillator TosF Fall Time 50 ns LP oscillator 15 ns HSoscillator T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Instruction cycle period Tcv equals four times the input oscillator time base period All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current con sumption All devices are tested to operate at min value
357. result is stored back in register f 1 1 Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination T COMF REG1 0 Before Instruction REG1 0x13 After Instruction REG1 0x13 W OxEC Decrement f label DECF f d O lt f lt 127 d e 0 1 f 1 destination Z 00 0011 dfff ffff Decrement register f If d is O0 the result is stored in the W register If d is 1 the result is stored back in register f 1 1 Q1 Q2 Q3 Q4 Write to destination Decode Read Process register data T DECF CNT i Before Instruction CNT 0x01 Z gt H After Instruction CNT 0x00 Z 1 DECFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity If Skip Example Decrement f Skip if 0 abel DECFSZ f d O lt f lt 127 de 0 1 f 1 destination skip if result 0 None 00 1011 dfff ffff The contents of register f are decre mented If d is O the result is placed in the W register If d is 1 the result is placed back in register f If the result is 1 the next instruction is executed If the result is 0 then a NOP is executed instead making it a 2TCY instruc tion 1 1 2 Q1 Q2 Q3 Q4 Decode Read Process Write to register f data destination 2nd Cycle Q1 Q2 Q3 Q4 No No No No Operation Operation O
358. rflow In 2C mode 1 A byte is received while the SSPBUF register is still holding the previous byte SSPOV is a don t care in transmit mode SSPOV must be cleared in software in either mode 0 No overflow bit 5 SSPEN Synchronous Serial Port Enable bit In SPI mode 1 Enables serial port and configures SCK SDO and SDI as serial port pins 0 Disables serial port and configures these pins as UO port pins In 2C mode 1 Enables the serial port and configures the SDA and SCL pins as serial port pins 0 Disables serial port and configures these pins as UO port pins In both modes when enabled these pins must be properly configured as input or output bit 4 CKP Clock Polarity Select bit In SPI mode 1 Idle state for clock is a high level 0 Idle state for clock is a low level In C mode SCK release control 1 Enable clock 0 Holds clock low clock stretch Used to ensure data setup time bit 3 0 SSPM3 SSPMO Synchronous Serial Port Mode Select bits 0000 SPI master mode clock Fosc 4 0001 SPI master mode clock Fosc 16 0010 SPI master mode clock Fosc 64 0011 SPI master mode clock TMR2 output 2 0100 SPI slave mode clock SCK pin SS pin control enabled 0101 SPI slave mode clock SCK pin SS pin control disabled SS can be used as I O pin 0110 C slave mode 7 bit address 0111 C slave mode 10 bit address 1011 IC firmware controlled master mode slave idle 1110 IC slave mode 7
359. rnal Reset BVDD Max BVDD Min Internal Reset DS30390E page 134 1997 Microchip Technology Inc PIC16C7X 14 4 5 TIME OUT SEQUENCE On power up the time out sequence is as follows First PWRT time out is invoked after the POR time delay has expired Then OST is activated The total time out will vary based on oscillator configuration and the status of the PWRT For example in RC mode with the PWRT disabled there will be no time out at all Figure 14 10 Figure 14 11 and Figure 14 12 depict time out sequences on power up Since the time outs occur from the POR pulse if MCLR is kept low long enough the time outs will expire Then bringing MCLR high will begin execution immediately Figure 14 11 This is useful for testing purposes or to synchronize more than one PIC16CXX device operat ing in parallel Table 14 7 shows the reset conditions for some special function registers while Table 14 8 shows the reset conditions for all the registers 14 4 6 POWER CONTROL STATUS REGISTER PCON Applicable Devices 72 73 73A 74 74A 76 77 The Power Control Status Register PCON has up to two bits depending upon the device BitO is not imple mented on the PIC16C73 or PIC16C74 BitO is Brown out Reset Status bit BOR Bit BOR is unknown on a Power on Reset It must then be set by the user and checked on subsequent resets to see if bit BOR cleared indicating a BOR occurred The BO
360. rnal phase clock TOSC Also there is a delay in the actual incrementing of TimerO after synchronization 7 2 1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used the external clock input is the same as the prescaler output The synchronization of TOCKI with the internal phase clocks is accom plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Figure 7 5 Therefore it is necessary for TOCKI to be high for at least 2Tosc and a small RC delay of 20 ns and low for at least 2Tosc and a small RC delay of 20 ns Refer to the electrical specification of the desired device When a prescaler is used the external clock input is divided by the asynchronous ripple counter type pres caler so that the prescaler output is symmetrical For the external clock to meet the sampling requirement the ripple counter must be taken into account There fore it is necessary for TOCKI to have a period of at least 4Tosc and a small RC delay of 40 ns divided by the prescaler value The only requirement on TOCKI high and low time is that they do not violate the mini mum pulse width requirement of 10 ns Refer to param eters 40 41 and 42 in the electrical specification of the desired device 7 2 2 TMRO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks there is a small delay from the time the external clock edge occurs to the time the TimerO mod ule is a
361. rrupt will be generated if enable bit RCIE was set Read the RCSTA register to get the ninth bit if enabled and determine if any error occurred during reception 2 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN Read the 8 bit received data by reading the 3 f interrupts are desired then set enable bit RCREG register RCIE If any error occurred clear the error by clearing 4 If 9 bit reception is desired then set bit RX9 enable bit CREN 5 Enable the reception by setting bit CREN TABLE 12 7 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR Resets OCh PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN RX9D USART Receive Register PSPIE ADIE RCIE CCP1IE TMR2IE TMR1IE 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented locations read as 0 Shaded cells are not used for Asynchronous Reception Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear 1997 Microchip Technology Inc DS30390E page 109 PIC16C7X 12 3 USART Synchronous Master Mode Applicable Devices 72 73 73A 74 74A 76 77 In Synchronous Master mode the data is tran
362. rsion completed must be cleared in software 0 The A D conversion is not complete Unimplemented Read as 0 SSPIF Synchronous Serial Port Interrupt Flag bit 1 The transmission reception is complete must be cleared in software 0 Waiting to transmit receive CCP1IF CCP1 Interrupt Flag bit Capture Mode 1 A TMR1 register capture occurred must be cleared in software 0 No TMR1 register capture occurred Compare Mode 12A TMR1 register compare match occurred must be cleared in software 0 No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF TMR2 to PR2 Match Interrupt Flag bit 1 TMR2 to PR2 match occurred must be cleared in software 0 2 No TMR2 to PR2 match occurred TMR1IF TMR1 Overflow Interrupt Flag bit 1 TMR1 register overflowed must be cleared in software 0 TMR1 register did not overflow Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt 1997 Microchip Technology Inc DS30390E page 35 PIC16C7X FIGURE 4 13 PIR1 REGISTER PIC16C73 73A 74 74A 76 77 ADDRESS 0Ch R W 0 R W 0 R 0 R 0 R W 0 R W 0 R W 0 R W 0 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R Readable bit bit7 bito W Wri
363. ry bytes 232 232 454 454 454 Timer Module s TMRO TMRO TMRO TMRO TMRO TMR1 TMR1 TMR1 TMR1 TMR1 TMR2 TMR2 TMR2 TMR2 TMR2 TMR3 TMR3 TMR3 TMR3 TMR3 Captures PWM Module s 2 2 2 2 2 Serial Port s USART Yes Yes Yes Yes Yes Hardware Multiply Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 I O Pins 33 33 33 33 33 Voltage Range Volts 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 2 5 6 0 Number of Instructions 58 58 58 58 58 Packages 40 pin DIP 40 pin DIP 40 pin DIP 40 pin DIP 40 pin DIP 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin PLCC 44 pin PLCC MOER TQFP MQFP TQFP MQFP TQFP MQFP TQFP MQFP TQFP Maximum Frequency 33 33 of Operation MHz EPROM Program Memory 8K 16K words ROM Program Memory words RAM Data Memory bytes 454 902 Timer Module s TMRO TMRO TMR1 TMR1 TMR2 TMR2 TMR3 TMR3 Captures PWM Module s 4 3 4 3 Serial Port s USART 2 2 Hardware Multiply Yes Yes External Interrupts Yes Yes Interrupt Sources 18 18 I O Pins 50 50 Voltage Range Volts 3 0 6 0 3 0 6 0 Number of Instructions 58 58 Packages 64 pin DIP 64 pin DIP 68 pin LCC 68 pin LCC 68 pin TQFP 68 pin TQFP All PIC16 17 Family devices have Power on Reset selectable Watchdog Timer selectable code protect and high UO current capability 1997 Microchip Technology Inc DS30390E page 270 PIC16C 7X PIN COMPATIBILITY Devices that have the same pack
364. s TACQ 5 us 5 747 us 50 C 25 C 0 05 us C 10 747 us 1 25 us 11 997 us Sampling Switch leakage DAC capacitance 500 G 51 2 pF Legend CPIN input capacitance VT threshold voltage various junctions Ric interconnect resistance SS sampling switch I leakage leakage current at the pin due to CHOLD sample hold capacitance from DAC 567891011 DS30390E page 120 Sampling Switch kQ 1997 Microchip Technology Inc PIC16C7X 13 2 Selecting the A D Conversion Clock Applicable Devices 72 73 73A 74 74A 76 77 The A D conversion time per bit is defined as TAD The A D conversion requires 9 5TAD per 8 bit conversion The source of the A D conversion clock is software selectable The four possible options for TAD are e 2TOSC e 8TOSC e 32TOSC Internal RC oscillator For correct A D conversions the A D conversion clock TAD must be selected to ensure a minimum TAD time of 1 6 us Table 13 1 shows the resultant TAD times derived from the device operating frequencies and the A D clock Source selected 13 3 Configuring Analog Port Pins Applicable Devices 72 73 73A 74 74A 76 77 The ADCON1 TRISA and TRISE registers control the operation of the A D port pins The port pins that are desired as analog inputs must have their correspond ing TRIS bits set input If the TRIS bit is cleared out put the digital output level VOH or VOL will be
365. s Conditions No 90 TSU STA START condition 100 kHz mode 4700 m Only relevant for repeated START Setup time 400 kHz mode 600 condition 91 THD STA START condition 100 kHz mode 4000 m After this period the first clock Hold time 400 kHz mode 600 pulse is generated 92 Tsu sTO STOP condition 100 kHz mode 4700 Setup time 400 kHz mode 600 93 THD STO STOP condition 100 kHz mode 4000 Ge Hold time 400 kHz mode 600 DS30390E page 214 1997 Microchip Technology Inc PIC16C7X Out Note Refer to Figure 19 1 for load conditions FIGURE 19 11 CC BUS DATA TIMING Applicable Devices 72 T3 73A 74 74A 76 77 TABLE 19 10 12C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No 100 THIGH Clock high time 100 kHz mode 4 0 us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 0 6 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 101 TLow Clock low time 100 kHz mode 4 7 us Device must operate at a mini mum of 1 5 MHz 400 kHz mode 1 3 us Device must operate at a mini mum of 10 MHz SSP Module 1 5TCY 102 TR SDA and SCL rise 100 kHz mode 1000 ns time 400 kHz mode 20 0 1Cb 300 ns C
366. s Transmit or USART Synchronous Clock RC7 RX DT bit7 ST Input output port pin or USART Asynchronous Receive or USART Synchronous Data Legend ST Schmitt Trigger input Note 1 The CCP2 multiplexed function is not enabled on the PIC16C72 2 The TX CK and RX DT multiplexed functions are not enabled on the PIC16C72 DS30390E page 48 1997 Microchip Technology Inc PIC16C7X TABLE 5 6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC yade on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RCO XXXX XXXX uuuu uuuu 87h TRISC PORTC Data Direction Register TE LL LATE 21132 Legend x unknown u unchanged 1997 Microchip Technology Inc DS30390E page 49 PIC16C7X 5 4 PORTD and TRISD Registers FIGURE 5 7 PORTD BLOCK DIAGRAM IN Applicable Devices 1 0 PORT MODE EE PORTD is an 8 bit port with Schmitt Trigger input buff Q e ES ers Each pin is individually configurable as an input or UO pin output FCK A Data Latch D Q PORTD can be configured as an 8 bit wide micropro cessor port parallel slave port by setting control bit PSPMODE TRISE lt 4 gt In this mode the input buffers are TTL o Schmitt Trigger input buffer V TRIS Latch RD TRIS RD PORT 3
367. s at the same time in order stays in the input mode no problem occurs However if to change the level on this pin wired or wired and bitO is switched to an output the content of the data The resulting high output currents may damage the latch may now be unknown chip Reading the port register reads the values of the port pins Writing to the port register writes the value to the SES SUCCESSIVE ORERATIONS ONIVO PORTS port latch When using read modify write instructions The actual write to an UO port happens at the end of an ex BCF BSF etc on a port the value of the port pins instruction cycle whereas for reading the data must be is read the desired operation is done to this value and valid at the beginning of the instruction cycle Figure 5 this value is then written to the port latch 10 Therefore care must be exercised if a write fol Example 5 4 shows the effect of two sequential read lowed by a read operation is carried out on the same modify write instructions on an I O port O port The sequence of instructions should be such to allow the pin voltage to stabilize load dependent before the next instruction which causes that file to be read into the CPU is executed Otherwise the previous state of that pin may be read into the CPU rather than the new state When in doubt it is better to separate these instructions with a NOP or another instruction not accessing this UO port FIGURE 5 10 SUCCESSIVE 1 0 OPE
368. s of all of Microchip s development systems software products Plus this line provides information on how customers can receive any currently available upgrade kits The Hot Line Numbers are 1 800 755 2345 for U S and most of Canada and 1 602 786 7302 for the rest of the world 970301 Trademarks The Microchip name logo PIC PICSTART PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U S A and other countries FlexROM MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U S A fuzzyTECH is a registered trademark of Inform Software Corporation IBM IBM PC AT are registered trademarks of International Business Machines Corp Pentium is a trademark of Intel Corporation Windows is a trademark and MS DOS Microsoft Windows are registered trade marks of Microsoft Corporation CompuServe is a regis tered trademark of CompuServe Incorporated All other trademarks mentioned herein are the property of their respective companies 1996 Microchip Technology Inc DS30390E page 285 PIC16C6X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 602 786 7578
369. s with an external clock applied to the OSC1 CLKIN pin When an external clock input is used the Max cycle time limit is DC no clock for all devices 1997 Microchip Technology Inc DS30390E page 189 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 3 CLKOUT AND I O TIMING TABLE 18 3 CLKOUT AND I O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 10 TosH2ckL OSC1T to CLKOUTL 75 200 ns Note 1 11 llosH2ck 18140 OSC1 TJ F11 toPKtiide 1 11569 Tf12 226 478 DS30390E page 190 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 18 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING Internal POR PWRT Time out OSC Time out Internal RESET Watchdog Timer RESET I O Pins Note Refer to Figure 18 1 for load conditions TABLE 18 4 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typt Max Units Conditions No 30 TmcL MCLR Pulse Width low 100 ns VDD 5V 40 C to 85 C 31 Twdt Watchdog Timer Time out Period 7 18 33 ms VDD 5V 40 C to 85 C No Prescaler 32 Tost Oscillation Start up Timer Period 1024Tosc Tosc OSC period 3
370. sages keys to enter commands and a modular detachable socket assembly to support various package types In stand alone mode the PRO MATE II can read verify or pro gram PIC16C5X PIC16CXXX PIC17CXX and PIC14000 devices It can also set configuration and code protect bits in this mode 16 5 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy to use low cost prototype programmer It connects to the PC via one of the COM RS 232 ports MPLAB Integrated Development Environment software makes using the programmer simple and efficient PICSTART Plus is not recommended for production programming PICSTART Plus supports all PIC12C5XX PIC14000 PIC16C5X PIC16CXXX and PIC17CXX devices with up to 40 pins Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket 1997 Microchip Technology Inc DS30390E page 163 PIC16C7X 16 6 PICDEM 1 Low Cost PIC16 17 Demonstration Board The PICDEM 1 is a simple board which demonstrates the capabilities of several of Microchip s microcontrol lers The microcontrollers supported are PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X PIC16C71 PIC16C8X PIC17C42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The users can program the sample microcontrollers provided with the PICDEM 1 board on a PRO MATE Il or PICSTART 16B programmer and easily tes
371. sc 20 MHz TMR2 prescale 1 1 78 125 kHz PR2 1 4 1 20 MHz 1 12 8us PR2 Us Ae 50 ns 1 PR2 63 Find the maximum resolution of the duty cycle that can be used with a 78 125 kHz frequency and 20 MHz oscillator 1 78 125 kHz 2PWM RESOLUTION 1 20 MHz e 1 12 8 us 2PWM RESOLUTION 50 ns o 1 256 2PWM RESOLUTION log 256 PWM Resolution e log 2 8 0 PWM Resolution At most an 8 bit resolution duty cycle can be obtained from a 78 125 kHz frequency and a 20 MHz oscillator Le 0 lt CCPR1L CCP1CON lt 5 4 gt lt 255 Any value greater than 255 will result in a 100 duty cycle In order to achieve higher resolution the PWM fre quency must be decreased In order to achieve higher PWM frequency the resolution must be decreased Table 10 3 lists example PWM frequencies and resolu tions for Fosc 20 MHz The TMR2 prescaler and PR2 values are also shown 10 8 3 SET UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation 1 Setthe PWM period by writing to the PR2 regis ter 2 Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON lt 5 4 gt bits 3 Make the CCP1 pin an output by clearing the TRISC 2 bit 4 Setthe TMR2 prescale value and enable Timer2 by writing to T2CON 5 Configure the CCP1 module for PWM operation TABLE 10 3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1 22 kHz
372. scale 1 2 cicci 60 TimerO Interrupt Timing 60 TimerO Timing with External Clock 61 Block Diagram of the Timer0 WDT Prescaler eon 62 Figure 8 1 Figure 8 2 Figure 9 1 Figure 9 2 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 11 7 Figure 11 8 Figure 11 9 Figure 11 10 Figure 11 11 Figure 11 12 Figure 11 13 Figure 11 14 Figure 11 15 Figure 11 16 Figure 11 17 Figure 11 18 Figure 11 19 Figure 11 20 Figure 11 21 Figure 11 22 Figure 11 23 Figure 11 24 Figure 11 25 Figure 11 26 Figure 11 27 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 T1CON Timer1 Control Register Address 10h Timer1 Block Diagram T Timer2 Block Diagram T2CON Timer2 Control Register Address 12h tene 70 CCP1CON Register Address 17h CCP2CON Register Address 1Dh 72 Capture Mode Operation Block Diagram sees 72 Compare Mode Operation Block Diagram eese 73 Simplified PWM Block Diagram 74 PWM Output 74 SSPSTAT Sync Serial Port Status Register Address 94h 78 SSPCON Sync Serial Port Control Register Address 14h 79 SSP Block Diagram SPI Mode 80 SPI Master Slave Connection
373. set VDD The power up time delay will vary from chip to chip due to VDD temperature and process variation See DC parameters for details 14 4 8 OSCILLATOR START UP TIMER OST The Oscillator Start up Timer OST provides 1024 oscillator cycle from OSC1 input delay after the PWRT delay is over This ensures that the crystal oscil lator or resonator has started and stabilized The OST time out is invoked only for XT LP and HS modes and only on Power on Reset or wake up from SLEEP 14 4 4 BROWN OUT RESET BOR Applicable Devices 72 73 73A 74 74A 76 77 A configuration bit BODEN can disable if clear pro grammed or enable if set the Brown out Reset cir cuitry If VDD falls below 4 0V 3 8V 4 2V range for greater than parameter 35 the brown out situation will reset the chip A reset may not occur if VDD falls below 4 0V for less than parameter 35 The chip will remain in Brown out Reset until VDD rises above BVDD The Power up Timer will now be invoked and will keep the chip in RESET an additional 72 ms If VDD drops below BVDD while the Power up Timer is running the chip will go back into a Brown out Reset and the Power up Timer will be initialized Once VDD rises above BVDD the Power up Timer will execute a 72 ms time delay The Power up Timer should always be enabled when Brown out Reset is enabled Figure 14 9 shows typi cal brown out situations BVpp Min BVDD Min Inte
374. smitted in a half duplex manner i e transmission and reception do not occur at the same time When transmitting data the reception is inhibited and vice versa Synchronous mode is entered by setting bit SYNC TXSTA 4 In addition enable bit SPEN RCSTA 7 is set in order to configure the RC6 TX CK and RC7 RX DT UO pins to CK clock and DT data lines respectively The Master mode indicates that the processor transmits the master clock on the CK line The Master mode is entered by setting bit CSRC TXSTA 7 12 3 1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 12 7 The heart of the transmitter is the transmit serial shift register TSR The shift register obtains its data from the read write transmit buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the last bit has been transmitted from the previous load As Soon as the last bit is transmitted the TSR is loaded with new data from the TXREG if available Once the TXREG register transfers the data to the TSR register occurs in one Tcycle the TXREG is empty and inter rupt bit TXIF PIR1 lt 4 gt is set The interrupt can be enabled disabled by setting clearing enable bit TXIE PIE1 lt 4 gt Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft ware It will reset only when new data is loaded into th
375. sseeeaeeeae 173 189 207 226 IPG BUS Data 2 cse 180 197 215 236 DC Bus Start Stop bits 179 196 214 235 CC Clock Synchronization sse DC Data Transfer Wait State DC Multi Master Arbitration DC Reception 7 bit Address Parallel Slave Port seene Power up Timer So Reset sss SPI Master Mode AAA SPI Mode edet UR 178 195 213 SPI Mode Master Slave Mode No SS Control 82 SPI Mode Slave Mode With SS Control 82 SPI Slave Mode CKE 1 88 SPI Slave Mode Timing CKE 0 87 Start up Timer ususss 175 191 209 228 Time out Sequence see 139 TimerQ oic 59 176 192 210 229 TimerO Interrupt Timing eene 60 TimerO with External Clock sesser 61 TIME i eoi eter Per ste 176 192 210 229 USART Asynchronous Master Transmission 107 USART Asynchronous Reception 108 USART RX Pin Sampling USART Synchronous Receive USART Synchronous Reception 113 USART Synchronous Transmission 111 198 216 237 Wake up from Sleep via Interrupt 146 Watchdog Timer ss 175 191 209 228 uud TMRO Register EP TMRI CS Dil ttp retis uiu PL TMR1H Register TMRTIE DIE
376. st Significant Byte 0000 0000 0000 0000 83h STATUS IRP 4 RP1 4 RPO TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer XXXX XXXX uuuu uuuu 85h TRISA PORTA Data Direction Register 1 111 11 1111 86h TRISB PORTB Data Direction Register 111 111 1111 1111 87h TRISC PORTO Data Direction Register 111 111 1111 1111 88h Unimplemented 89h Unimplemented 8Ah 2 PCLATH Write Buffer for the upper 5 bits of the PC 0 0000 0 0000 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 ADIE SSPIE CCP1IE TMR2IE TMRAIE 0 0000 0 0000 8Dh Unimplemented 8Eh PCON POR BOR qq uu 8Fh SCH Unimplemented 90h Unimplemented 91h Unimplemented 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port IC mode Address Register 0000 0000 0000 0000 94h SSPSTAT D A P S R W UA BF 00 0000 00 0000 95h Unimplemented 96h Unimplemented 97h Unimplemented az 98h Unimplemented 99h Unimplemented 9Ah Unimplemented 9Bh Unimplemented 9Ch Unimplemented 9Dh Unimplemented 9Eh Unimplemented 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged q value depends on condition unimplemented read as 0 Shaded locations are unimpl
377. st Street Suite 590 San Jose CA 95131 Tel 408 436 7950 Fax 408 436 7955 All rights reserved 1999 Microchip Technology Incorporated Printed in the USA 11 99 DNV Certification Inc ANSI RAB AMERICAS continued Toronto Microchip Technology Inc 5925 Airport Road Suite 200 Mississauga Ontario L4V 1W1 Canada Tel 905 405 6279 Fax 905 405 6253 ASIA PACIFIC Hong Kong Microchip Asia Pacific Unit 2101 Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong N T Hong Kong Tel 852 2 401 1200 Fax 852 2 401 3431 Beijing Microchip Technology Beijing Unit 915 6 Chaoyangmen Bei Dajie Dong Erhuan Road Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel 86 10 85282100 Fax 86 10 85282104 India Microchip Technology Inc India Liaison Office No 6 Legacy Convent Road Bangalore 560 025 India Tel 91 80 229 0061 Fax 91 80 229 0062 Japan Microchip Technology Intl Inc Benex S 1 6F 3 18 20 Shinyokohama Kohoku Ku Yokohama shi Kanagawa 222 0033 Japan Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Microchip Technology Korea 168 1 Youngbo Bldg 3 Floor Samsung Dong Kangnam Ku Seoul Korea Tel 82 2 554 7200 Fax 82 2 558 5934 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg 2077 Yan an Road West Hong Qiao District Shanghai PRC 200335 Tel 86 21 6275 5700 Fax 86 21 6275 5060 DNV MSC USA The Netherlands Accredited by the RvA IDI
378. strial PIC16C73 74 10 Commercial Industrial PIC16C73 74 20 Commercial Industrial PIC16LC73 74 04 Commercial Industrial 199 A D Conversion Requirements 200 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation Commercial Devices 201 External Clock Timing Requirements eere 207 CLKOUT and UO Timing Requirements eese 208 Reset Watchdog Timer Oscillator Start up Timer Power up Timer and brown out reset Requirements 209 TimerO and Timer1 External Clock Requirements sese 210 Capture Compare PWM Requirements CCP1 and CCP2 211 Parallel Slave Port Requirements PIC16C74A aE SPI Mode Requirements DC Bus Start Stop Bits Requirements 214 DC Bus Data Requirements 215 USART Synchronous Transmission Requirements esee 216 USART Synchronous Receive Requirements esee 216 A D Converter Characteristics 217 PIC16C73A 74A 04 Commercial Industrial Extended PIC16C73A 74A 10 Commercial Industrial Extended PIC16C73A 74A 20 Commercial Industrial Extended PIC16LC73A 74A 04 Commercial Industrial 217 A D Conversion Requirements 218 Table 20 1 Table 20 2 Table 20 3 Table 20 4 Tab
379. sts of Microchip part number year code week code facility code mask revision number and assembly code For OTP marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price DS30390E page 260 1997 Microchip Technology Inc PIC16C7X Package Marking Information Cont d 40 Lead PDIP Example MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX AABBCDE O AN MICROCHIP D PIC16C74 04 P 9512CAA O AN MICROCHIP O 40 Lead CERDIP Windowed S MICROCHIP MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX AABBCDE 44 Lead PLCC MICROCHIP MMMMMMMM O XXXXXXXXXX XXXXXXXXXX AABBCDE Ex ample NS MICROCHIP PIC16C74 JW AABBCDE Example MICROCHIP PIC16C74 O 10 L AABBCDE 44 Lead MQFP Example D NN MMMMMMMM PIC16C74 XXXXXXXXXX 10 PQ XXXXXXXXXX D AABBCDE O AABBCDE Legend MM M Microchip part number information XX X Customer specific information AA Year code last 2 digits of calender year BB Week code week of January 1 is week 01 C Facility code of the plant at which wafer is manufactured C Chandler Arizona U S A S Tempe Arizona U S A D4 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled Note In the event the full Microchip part nu
380. sunk by PORTA PORTB and PORTE combined Note 3 200 mA Maximum current sourced by PORTA PORTB and PORTE combined Note 3 200 mA Maximum current sunk by PORTC and PORTD combined Note 3 200 mA Maximum current sourced by PORTC and PORTD combined Note 3 200 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Y 10H X VDD VOH x loH X Vol x IOL Note 2 Voltage spikes below Vss at the MCLR pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 1000 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss Note 3 PORTD and PORTE are not implemented on the PIC16C76 T NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1997 Microchip Technology Inc DS30390E page 219 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 TABLE 20 1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION COMMERCIAL DEVICES PIC16C76 04 PIC16C76 10 PIC16C76 20 PIC16LC76 04 JW Devices PIC16C7
381. supports all Microchip 2 wire and 3 wire Serial EEPROMs The kit includes everything necessary to read write erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials The Total Endurance Disk is included to aid in trade off analysis and reliability calculations The total kit can significantly reduce time to market and result in an optimized system 16 16 TrueGauge Intelligent Battery Management The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelli gent Battery Management IC System design verifica tion can be accomplished before hardware prototypes are built User interface is graphically oriented and measured data can be saved in a file for exporting to Microsoft Excel 16 17 KEELoc Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products The HCS eval uation kit includes an LCD display to show changing codes a decoder to decode transmissions and a pro gramming interface to program test transmitters 1997 Microchip Technology Inc DS30390E page 165 PIC16C7X DEVELOPMENT TOOLS FROM MICROCHIP TABLE 16 1 Va uonenje a 600133 IN3QDIld c IN3G9ld L IN3G9ld yy Sjeufisoq o 1VA33S gt ouwutwue16oid 600111 gt gt Jouue160o1d jesieaIuNn Il gS LVIN Old Wy Ae Iesieaiun 1S09 M07 SNid LYVLS
382. t Max Units Conditions No 62 TdtV2wrH Data in valid before WRT or CST setup time 20 ns 25 ns Extended Range Only 63 TwrH2dtl WRT or CST to data in invalid hold time PIC16C77 20 ns PIC16LC77 35 ns 64 TrdL2dtV RD and CS to data out valid 80 ns 90 ns Extended Range Only 65 TrdH2dtl RDT or CS to data out invalid 10 30 ns These parameters are characterized but not tested t Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested 1997 Microchip Technology Inc DS30390E page 231 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 9 SPI MASTER MODE TIMING CKE 0 E ER E SCK CKP 1 Refer to Figure 20 1 for load conditions DS30390E page 232 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 20 11 SPI SLAVE MODE TIMING CKE 0 SCK CKP 1 Refer to Figure 20 1 for load conditions 1997 Microchip Technology Inc DS30390E page 233 PIC16C7X Applicable Devices 72 73 v3A 74 74A 76 77 TABLE 20 8 SPI MODE REQUIR
383. t Signal D005 Brown out Reset Voltage BVDD 8 7 40 43 V BODEN bit in configuration word enabled 3 7 40 44 V Extended Only D010 Supply Current IDD 2 7 5 0 mA XT RC osc configuration Note 2 5 Fosc 4 MHz VDD 5 5V Note 4 D013 S 10 20 mA HS osc configuration Fosc 20 MHz VDD 5 5V D015 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 D020 Power down Current IPD 10 5 42 pA VDD 4 0V WDT enabled 40 C to 85 C D021 Note 3 5 1 5 16 uA VDD 4 0V WDT disabled 0 C to 70 C D021A 1 5 19 uA VDD 4 0V WDT disabled 40 C to 85 C D021B 2 5 19 uA VDD 4 0V WDT disabled 40 C to 125 C D023 Brown out Reset Current AIBOR 350 425 uA BOR enabled VDD 5 0V Note 6 These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 This is the limit to which VDD can be lowered without losing RAM data 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as UO pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all
384. t 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 05h PORTA RA5 RA4 RA3 RA2 RA1 RAO 0x 0000 0u 0000 85h TRISA PORTA Data Direction Register 11 1111 11 1111 9Fh ADCON1 PCFG2 PCFG1 PCFGO 000 000 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by PORTA DS30390E page 44 1997 Microchip Technology Inc PIC16C7X 5 2 PORTB and TRISB Registers Applicable Devices 72 73 73A 74 74A 76 77 PORTB is an 8 bit wide bi directional port The corre sponding data direction register is TRISB Setting a bit in the TRISB register puts the corresponding output driver in a hi impedance input mode Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin s EXAMPLE 5 2 INITIALIZING PORTB BCF STATUS RPO CLRF PORTB Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data BSF STATUS RPO MOVLW OxCF direction Set RB lt 3 0 gt as inputs RB lt 5 4 gt as outputs RB 7 6 as inputs MOVWF TRISB Se an Ne Ne Ne Ne Ne Ne Ne Ne ve Each of the PORTB pins has a weak internal pull up A single control bit can turn on all the pull ups This is performed by clearing bit RBPU OPTION lt 7 gt The weak pull up is automatically turned off when the port pin is configured as an output The pull ups are dis abled on a Power on Reset
385. t OERR RCSTA lt 1 gt will be set The word in the RSR will be lost The RCREG register can be read twice to retrieve the two bytes in the FIFO Overrun bit OERR has to be cleared in software This is done by resetting the receive logic CREN is cleared and then set If bit OERR is set transfers from the RSR register to the RCREG register are inhibited so it is essential to clear error bit OERR if it is set Framing error bit FERR RCSTA 2 is set if a stop bit is detected as clear Bit FERR and the 9th receive bit are buffered the same way as the receive data Reading the RCREG will load bits RX9D and FERR with new values therefore it is essential for the user to read the RCSTA register before reading RCREG register in order not to lose the old FERR and RX9D information Baud Rate Generator RC7 RX DT Pin Buffer Data and Control Recovery SPEN Interrupt er FIGURE 12 11 ASYNCHRONOUS RECEPTION RCREG register Ge 8 e e Re GE SE gt n V DS30390E page 108 1997 Microchip Technology Inc PIC16C7X Steps to follow when setting up an Asynchronous 6 Flag bit RCIF will be set when reception is com Reception 1 Initialize the SPBRG register for the appropriate baud rate If a high speed baud rate is desired set bit BRGH Section 12 1 plete and an inte
386. t TA lt 85 C for industrial and DC CHARACTERISTICS 0 C lt TA lt 70 C for commercial Operating voltage VDD range as described in DC spec Section 18 1 and Section 18 2 Characteristic Sym Min Typ Max Units Conditions t Capacitive Loading Specs on Output Pins D100 OSC2 pin Cosc2 15 pF In XT HS and LP modes when exter nal clock is used to drive OSC1 D101 All I O pins and OSC2 in RC CIO 50 pF D102 model SCL SDA in PC mode CB 400 pF These parameters are characterized but not tested T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 In RC oscillator configuration the OSC1 CLKIN pin is a Schmitt Trigger input It is not recommended that the PIC16C7X be driven with external clock in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 1997 Microchip Technology Inc DS30390E page 187 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18 4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats 1 TppS2ppS 3 TCC ST IC specifications only 2
387. t Tools please call 1 800 755 2345 or 1 602 786 7302 DS30390E page 287 1997 Microchip Technology Inc MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 786 7200 Fax 480 786 7277 Technical Support 480 786 7627 Web Address http www microchip com Atlanta Microchip Technology Inc 500 Sugar Mill Road Suite 200B Atlanta GA 30350 Tel 770 640 0034 Fax 770 640 0307 Boston Microchip Technology Inc 5 Mount Royal Avenue Marlborough MA 01752 Tel 508 480 9990 Fax 508 480 8575 Chicago Microchip Technology Inc 333 Pierce Road Suite 180 Itasca IL 60143 Tel 630 285 0071 Fax 630 285 0075 Dallas Microchip Technology Inc 4570 Westgrove Drive Suite 160 Addison TX 75248 Tel 972 818 7423 Fax 972 818 2924 Dayton Microchip Technology Inc Two Prestige Place Suite 150 Miamisburg OH 45342 Tel 937 291 1654 Fax 937 291 9175 Detroit Microchip Technology Inc Tri Atria Office Building 32255 Northwestern Highway Suite 190 Farmington Hills MI 48334 Tel 248 538 2250 Fax 248 538 2260 Los Angeles Microchip Technology Inc 18201 Von Karman Suite 1090 Irvine CA 92612 Tel 949 263 1888 Fax 949 263 1338 New York Microchip Technology Inc 150 Motor Parkway Suite 202 Hauppauge NY 11788 Tel 631 273 5305 Fax 631 273 5335 San Jose Microchip Technology Inc 2107 North Fir
388. t firm ware The user can also connect the PICDEM 1 board to the PICMASTER emulator and download the firmware to the emulator for testing Additional pro totype area is available for the user to build some addi tional hardware and connect it to the microcontroller socket s Some of the features include an RS 232 interface a potentiometer for simulated analog input push button switches and eight LEDs connected to PORTB 16 7 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 is a simple demonstration board that supports the PIC16C62 PIC16C64 PIC16C65 PIC16C73 and PIC16C74 microcontrollers All the necessary hardware and software is included to run the basic demonstration programs The user can program the sample microcontrollers provided with the PICDEM 2 board on a PRO MATE II pro grammer or PICSTART 16C and easily test firmware The PICMASTER emulator may also be used with the PICDEM 2 board to test firmware Additional prototype area has been provided to the user for adding addi tional hardware and connecting it to the microcontroller socket s Some of the features include a RS 232 inter face push button switches a potentiometer for simu lated analog input a Serial EEPROM to demonstrate usage of the EC bus and separate headers for connec tion to an LCD module and a keypad 16 8 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 is a simple demonstration board that supports the PIC16C
389. t must output the next data bit to the SDA line TR max tsu DAT 1000 250 1250 ns according to the standard mode DC bus specification before the SCL line is released 1997 Microchip Technology Inc DS30390E page 215 PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 FIGURE 19 12 USART SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING pin RC7 RX DT pin a 121 gt 120 Note Refer to Figure 19 1 for load conditions TABLE 19 11 USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typt Max Units Conditions No 120 TckH2dtV SYNC XMIT MASTER amp SLAVE PIC16C73A 74A 80 ns Clock high to data out valid PIC16LC73A 74A 100 ns 121 Tckrf Clock out rise time and fall time PIC16C73A 74A 45 ns Master Mode PIC16LC73A 74A 50 ns 122 Tdtrf Data out rise time and fall time PIC16C73A 74A 45 ns PIC16LC73A 74A 50 ns T Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested FIGURE 19 13 USART SYNCHRONOUS RECEIVE MASTER SLAVE TIMING RC6 TX CK VN pin 125 A RC7 RX DT a pin X SCH 126 w Note Refer to Figure 19 1 for load conditions TABLE 19 12 USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym C
390. table bit U Unimplemented bit read as 0 n Value at POR reset bit7 X PSPIF Parallel Slave Port Read Write Interrupt Flag bit 1 A read or a write operation has taken place must be cleared in software 0 No read or write has occurred bit 6 ADIF A D Converter Interrupt Flag bit 1 An A D conversion completed must be cleared in software 0 The A D conversion is not complete bit 5 RCIF USART Receive Interrupt Flag bit 1 The USART receive buffer is full cleared by reading RCREG 0 The USART receive buffer is empty bit 4 TXIF USART Transmit Interrupt Flag bit 1 The USART transmit buffer is empty cleared by writing to TXREG 0 The USART transmit buffer is full bit 3 SSPIF Synchronous Serial Port Interrupt Flag bit 1 The transmission reception is complete must be cleared in software 0 Waiting to transmit receive bit 2 CCP1IF CCP1 Interrupt Flag bit Capture Mode 1 A TMR1 register capture occurred must be cleared in software 0 No TMR register capture occurred Compare Mode 1 A TMR1 register compare match occurred must be cleared in software 0 No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1 TMR2IF TMR2 to PR2 Match Interrupt Flag bit 1 TMR2 to PR2 match occurred must be cleared in software 0 2 No TMR2 to PR2 match occurred bit 0 TMR1IF TMR1 Overflow Interrupt Flag bit 1 TMR1 register overflowed must be cleared in software 0 TMR1 register did not overfl
391. tarting the A D conversion and the Timer1 counter will be reset to zero Timer1 is reset to automatically repeat the A D acquisition period with minimal software overhead moving the ADRES to the desired location The appropriate analog input channel must be selected and the minimum acquisition done before the special event trigger sets the GO DONE bit starts a conversion If the A D module is not enabled ADON is cleared then the special event trigger will be ignored by the A D module but will still reset the Timer1 counter 13 9 Connection Considerations Applicable Devices If the input voltage exceeds the rail values VSs or VDD by greater than 0 2V then the accuracy of the conver sion is out of specification An external RC filter is sometimes added for anti alias ing of the input signal The R component should be selected to ensure that the total source impedance is kept under the 10 kQ recommended specification Any external components connected via hi impedance to an analog input pin capacitor zener diode etc should have very little leakage current at the pin 13 10 Transfer Function Applicable Devices 72 73 73A 74 74A 76 77 The ideal transfer function of the A D converter is as follows the first transition occurs when the analog input voltage VAIN is Analog VREF 256 Figure 13 5 FIGURE 13 5 A D TRANSFER FUNCTION Pe 2 a E 2 o o ke 9 o E e a 256 LSb f
392. te of the 16 bit TMR1 register XXXX XXXX uuuu uuuu Holding register for the Most Significant Byte of the 16 bit TMR1 register XXXX XXXX uuuu uuuu TICKPS1 T1CKPSO T1OSCEN T1SYNC TMR1CS TMR1ON 00 0000 uu uuuu Timer2 modules register 0000 0000 0000 0000 T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 000 0000 SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX XXXX uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 CCPRIL Capture Compare PWM Register1 LSB XXXX xxxx uuuu uuuu CCPR1H Capture Compare PWM Register1 MSB XXXX xxxx uuuu uuuu CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1MO 00 0000 00 0000 SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x USART Transmit Data Register 0000 0000 0000 0000 USART Receive Data Register 0000 0000 0000 0000 CCPR2L Capture Compare PWM Register LSB XXXX XXXX uuuu uuuu CCPR2H Capture Compare PWM Register2 MSB XXXX xxxx uuuu uuuu CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2MO 00 0000 00 0000 1Eh ADRES A D Result Register XXXX xxxx uuuu uuuu 1Fh ADCONO ADCS1 ADCSO CHS2 CHS1 CHSO GO DONE ADON 0000 00 0 0000 00 0 Legend x unknown u unchanged q value depends on condition unimplemented read as 0
393. ter Syntax label OPTION Operands None Operation W OPTION Status Affected None Encoding 00 0000 0110 0010 Description The contents of the W register are loaded in the OPTION register This instruction is supported for code com patibility with PIC16C5X products Since OPTION is a readable writable register the user can directly address it Words 1 Cycles 1 Example To maintain upward compatibility with future PIC16CXX products do not use this instruction RETFIE Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity 1st Cycle 2nd Cycle Example Return from Interrupt abel RETFIE None TOS 5 PC 1 GIE None 00 0000 0000 1001 Return from Interrupt Stack is POPed and Top of Stack TOS is loaded in the PC Interrupts are enabled by setting Global Interrupt Enable bit GIE INTCON 7 This is a two cycle instruction 1 2 Q1 Q2 Q3 Q4 Decode No Setthe Pop from Operation GIE bit the Stack No No No No Operation Operation Operation Operation RETFIE After Interrupt PC TOS GIE 1 1997 Microchip Technology Inc DS30390E page 157 PIC16C7X RETLW Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity 1st Cycle 2nd Cycle Example TABLE Return with Literal in W abel RETLW k 0 lt k lt 255 k
394. terrupt flag bit enable bit GIE INTCON lt 7 gt User soft ware should ensure the appropriate inter rupt flag bits are clear prior to enabling an interrupt FIGURE 4 15 PIR2 REGISTER ADDRESS 0Dh U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 CCP2IF Ip Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 1 Unimplemented Read as 0 bit 0 CCP2IF CCP2 Interrupt Flag bit Capture Mode 1 A TMR1 register capture occurred must be cleared in software 0 No TMR1 register capture occurred Compare Mode 1 A TMR1 register compare match occurred must be cleared in software 0 No TMR1 register compare match occurred PWM Mode Unused Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit GIE INTCON lt 7 gt User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt DS30390E page 38 1997 Microchip Technology Inc PIC16C7X 4 2 2 8 PCON REGISTER Note BOR is unknown on Power on Reset It Applicable Devices must then be set by the user and checked 72 73 73A 7A4 74A 76 77 on subsequent resets to see if BOR is The Power Control PCON register contains a flag bit Wise leet ST LT hes aes ens to allow diffe
395. the OPTION and TRIS instructions All examples use the following format to represent a hexadecimal number Oxhh where h signifies a hexadecimal digit FIGURE 15 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations 13 8 7 6 OPCODE d f FILE d 0 for destination W d 1 for destination f f 7 bit file register address Bit oriented file register operations 13 10 9 7 6 OPCODE b BIT 8 f FILE b 3 bit bit address f 7 bit file register address Literal and control operations General 13 8 7 OPCODE k literal k 8 bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE k literal k 11 bit immediate value 1997 Microchip Technology Inc DS30390E page 147 PIC16C7X TABLE 15 2 PIC16CXX INSTRUCTION SET Mnemonic Description Cycles 14 Bit Opcode Status Notes Operands MSb LSp Affected BYTE ORIENTED FILE REGISTER OPERATIONS ADDWF fd Add W and f 1 00 0111 afff ffff C DC Z 1 2 ANDWF fd AND W with f 1 00 0101 afff ffff Z 1 2 CLRF f Clear f 1 00 0001 1fff ffff Z 2 CLRW Clear W 1 00 0001 Oxxx xxxx Z COMF fd Complement f 1 00 001 dfff ffff Z 1 2 DECF fd Decrementf 1 00 0011 afff ffff 2Z 1 2 DECFSZ fd Decrement f Skip if 0 1 2 00 011 dfff TEEF 1 2 3 INCF fd Increment f 1 00 010 dfff ffff Z 1 2 INCFSZ fd Increment f Skip if 0 1 2 00 127 dEtf
396. the ninth push overwrites the value that was stored from the first push The tenth push overwrites the second push and so on DS30390E page 40 1997 Microchip Technology Inc PIC16C7X Example 4 1 shows the calling of a subroutine in 4 5 Indirect Addressing INDF and FSR page 1 of the program memory This example assumes Registers that PCLATH is saved and restored by the interrupt ser PIE PA Applicable Devices vice routine if interrupts are used 72 73 73A 74 74A 76 77 EXAMPLE 4 1 CALL OF A SUBROUTINE IN The INDF register is nota physical register Addressing PAGE 1 FROM PAGE 0 the INDF register will cause indirect addressing ORG 0x500 Indirect addressing is possible by using the INDF reg BSF PCLATH 3 Select page 1 800h FFFh ister Any instruction using the INDF register actually BCF PCLATH 4 Only on gt 4K devices accesses the register pointed to by the File Select Reg CALI SE EE ister FSR Reading the INDF register itself indirectly jbage d EE PER FSR 0 will read 00h Writing to the INDF register indirectly results in a no operation although status bits ORG das may be affected An effective 9 bit address is obtained SUB1_P1 called subroutine by concatenating the 8 bit FSR register and the IRP bit page 1 800h FFFh STATUS lt 7 gt as shown in Figure 4 18 A simple program to clear RAM locations 20h 2Fh RETURN probum EN EL SubrouEiNS using indirect addressing is
397. the program counter is not directly accessible PCLATH is a holding register for the PC lt 12 8 gt whose con DS30390E page 26 1997 Microchip Technology Inc PIC16C7X TABLE 4 3 PIC16C76 77 SPECIAL FUNCTION REGISTER SUMMARY Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR 2 Bank 0 Addressing this location uses contents of FSR to address data memory not a physical register 0000 0000 0000 0000 TimerO modules register XXXX XXXX uuuu uuuu Program Counter s PC Least Significant Byte 0000 0000 0000 0000 STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 0004 quuu FSR Indirect data memory address pointer XXXX XXXX uuuu uuuu PORTA PORTA Data Latch when written PORTA pins when read 0x 0000 Ou 0000 PORTB Data Latch when written PORTB pins when read XXXX XXXX uuuu uuuu PORTO Data Latch when written PORTC pins when read XXXX xxxx uuuu uuuu PORTD Data Latch when written PORTD pins when read XXXX XXXX uuuu uuuu ogn PORTE RE2 RE1 REO xxx uuu QAn t PCLATH Write Buffer for the upper 5 bits of the Program Counter 0 0000 0 0000 oBh 4 INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 0000 0000 0000 0000 CCP2IF 0 0 Holding register for the Least Significant By
398. the selected input channel has elapsed Then the conversion may be started BSF ADCONO GO Start A D Conversion The ADIF bit will be set and the GO DONE bit is cleared upon completion of the A D Conversion DS30390E page 122 1997 Microchip Technology Inc PIC16C7X 13 4 1 FASTER CONVERSION LOWER RESOLUTION TRADE OFF Not all applications require a result with 8 bits of reso lution but may instead require a faster conversion time The A D module allows users to make the trade off of conversion speed to resolution Regardless of the res olution required the acquisition time is the same To speed up the conversion the clock source of the A D module may be switched so that the TAD time violates the minimum specified time see the applicable electri cal specification Once the TAD time violates the mini mum specified time all the following A D result bits are not valid see A D Conversion Timing in the Electrical Specifications section The clock sources may only be switched between the three oscillator versions cannot be switched from to RC The equation to determine the time before the oscillator can be switched is as fol lows Conversion time 2TAD N TAD 8 N 2TOSC Where N number of bits of resolution required EXAMPLE 13 3 4 BIT vs 8 BIT CONVERSION TIMES Since the TAD is based from the device oscillator the user must use some method a timer software loop etc to determine wh
399. the slave address In 10 bit mode the user first needs to write the high byte of the address 1111 0 A9 A8 0 Following the high byte address match the low byte of the address needs to be loaded A7 A0 1997 Microchip Technology Inc DS30390E page 93 Applicable Devices PIC16C7X 72 73 73A 74 74A 76 77 11 5 1 SLAVE MODE In slave mode the SCL and SDA pins must be config ured as inputs TRISC 4 3 set The SSP module will override the input state with the output data when required slave transmitter When an address is matched or the data transfer after an address match is received the hardware automati cally will generate the acknowledge ACK pulse and then load the SSPBUF register with the received value currently in the SSPSR register There are certain conditions that will cause the SSP module not to give this ACK pulse These are if either or both a The buffer full bit BF SSPSTAT 0 was set before the transfer was received b The overflow bit SSPOV SSPCON 6 was set before the transfer was received In this case the SSPSR register value is not loaded into the SSPBUF but bit SSPIF PIR1 3 is set Table 11 4 shows what happens when a data transfer byte is received given the status of bits BF and SSPOV The shaded cells show the condition where user soft ware did not properly clear the overflow condition Flag bit BF is cleared by reading the
400. tic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 1 A carry out from the 4th low order bit of the result occurred 0 No carry out from the 4th low order bit of the result bit 0 C Carry borrow bit ADDWF ADDLW SUBLW SUBWF instructions 1 A carry out from the most significant bit of the result occurred 0 No carry out from the most significant bit of the result occurred Note For borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either the high or low order bit of the source register DS30390E page 30 1997 Microchip Technology Inc PIC16C7X 4 2 2 2 The OPTION register is a readable and writable regis OPTION REGISTER Applicable Devices Note 72 73 73A 74 74A 76 77 To achieve a 1 1 prescaler assignment for the TMRO register assign the prescaler to the Watchdog Timer ter which contains various control bits to configure the TMRO WDT prescaler the External INT Interrupt TMRO and the weak pull ups on PORTB FIGURE 4 8 OPTION REGISTER ADDRESS 81h 181h R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 RBPU INTEDG TOCS TOSE PSA PS2 PS1 PSO R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at P
401. tifi cation System section at the end of this data sheet When placing orders please use that page of the data sheet to specify the correct part number For the PIC16C7X family there are two device types as indicated in the device number 1 C as in PIC16C74 These devices have EPROM type memory and operate over the standard voltage range 2 LC as in PIC16LC74 These devices have EPROM type memory and operate over an extended voltage range 2 1 UV Erasable Devices The UV erasable version offered in CERDIP package is optimal for prototype development and pilot programs This version can be erased and reprogrammed to any of the oscillator modes Microchip s PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C7X 2 2 One Time Programmable OTP Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications The OTP devices packaged in plastic packages per mit the user to program them once In addition to the program memory the configuration bits must also be programmed 2 3 Quick Turnaround Production QTP Devices Microchip offers a QTP Programming Service for fac tory production orders This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabi lized The devices are identical to the OTP devices
402. trames inner one dde n 36 PSPMODE bit iecit 50 51 54 RSR TN MEE 40 RBIF Dit erect titi tb ete acc ntes RBPU bit RC Oscillator ere 132 135 RGIE biE eege EE 24 RCIF bit RCREG RCSTA Register sss 29 100 ROV MODE iii 98 RD pin Read Write bit Information DAN 78 83 Read Modify Write sis 53 Receive Overflow Detect bit SSPOV uz 79 Receive Overflow Indicator bit SSPOV 84 Register Elle euet erre een cedens 20 DS30390E page 276 1997 Microchip Technology Inc PIC16C7X Registers FSR SUMMA ege Ie a ut ann ee 29 INDF Emfang 29 Initialization Conditions eene 136 INTCON SUMMA Ee 29 Maps PIC16C72 sse PICTO CTS EE PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16G74 5 atrii pee feet OPTION Summary icit cec npe ez 29 PCL Summary sse 29 PCLATH SUMMA 4455 2 ee er 29 PORTB SUMMANY age E ede ao nae 29 Reset Conditions parre 136 SSPBUF SOCOM EE ee nr 80 SSPCON RE ET 79 SSPSR SECON eie eic de EAR 80 SSPSTAT Diagramme 78 Section A essere 78 STATUS SOSS er het deb denn 29 SUMMANY eoe cedet to renard 25 27 TMRO Summary is 29 TRISB SUMMALY n nete eri pe dee 29 KEE 129 133 Reset Conditions for Special Registers 136 RPO bit RX9D bit S E 78 83 SG TIME 80 sS 94 Serial Communication Interface SCI Module See USART Ser
403. ts such as the INT pin or PORTB change interrupt the interrupt latency will be three or four instruction cycles The exact latency depends when the interrupt event occurs Figure 14 17 The latency is the same for one or two cycle instructions Individual interrupt flag bits are set regard less of the status of their corresponding mask bit or the GIE bit Note For the PIC16C73 74 if an interrupt occurs while the Global Interrupt Enable GIE bit is being cleared the GIE bit may uninten tionally be re enabled by the user s Inter rupt Service Routine the RETFIE instruction The events that would cause this to occur are 1 An instruction clears the GIE bit while an interrupt is acknowledged 2 The program branches to the Interrupt vector and executes the Interrupt Ser vice Routine 3 The Interrupt Service Routine com pletes with the execution of the RET FIE instruction This causes the GIE bit to be set enables interrupts and the program returns to the instruction after the one which was meant to dis able interrupts Perform the following to ensure that inter rupts are globally disabled LOOP BCF INTCON GIE Disable global BTFSC INTCON GIE GOTO LOOP interrupt bit Global interrupt disabled NO try again Yes continue with program flow 1997 Microchip Technology Inc DS30390E page 141 PIC16C7X FIGURE 14 16 INTERRUPT LOGIC Wake up If in SLEE
404. ts are transferred to the upper byte of the program counter 2 Other non power up resets include external reset through MCLR and Watchdog Timer Reset 3 Bits PSPIE and PSPIF are reserved on the PIC16C76 always maintain these bits clear 4 These registers can be addressed from any bank 5 PORTD and PORTE are not physically implemented on the PIC16C76 read as 0 1997 Microchip Technology Inc DS30390E page 29 PIC16C7X 4 2 2 1 STATUS REGISTER Applicable Devices 72 7373A74 74A 76 77 The STATUS register shown in Figure 4 7 contains the arithmetic status of the ALU the RESET status and the bank select bits for data memory The STATUS register can be the destination for any instruction as with any other register If the STATUS register is the destination for an instruction that affects the Z DC or C bits then the write to these three bits is disabled These bits are set or cleared according to the device logic Furthermore the TO and PD bits are not writable Therefore the result of an instruction with the STATUS register as destination may be different than intended For example CLRF STATUS will clear the upper three bits and set the Z bit This leaves the STATUS register as 000u uluu where u unchangedl It is recommended therefore that only BCF BSF SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z C or
405. ture The PIC16CXX microcontroller fam ily has enhanced core features eight level deep stack and multiple internal and external interrupt sources The separate instruction and data buses of the Harvard architecture allow a 14 bit wide instruction word with the separate 8 bit wide data The two stage instruction pipeline allows all instructions to execute in a single cycle except for program branches which require two cycles A total of 35 instructions reduced instruction set are available Additionally a large register set gives some of the architectural innovations used to achieve a very high performance PIC16CXX microcontrollers typically achieve a 2 1 code compression and a 4 1 speed improvement over other 8 bit microcontrollers in their class The PIC16C72 has 128 bytes of RAM and 22 I O pins In addition several peripheral features are available including three timer counters one Capture Compare PWM module and one serial port The Synchronous Serial Port can be configured as either a 3 wire Serial Peripheral Interface SPI or the two wire Inter Inte grated Circuit ZC bus Also a 5 channel high speed 8 bit A D is provided The 8 bit resolution is ideally suited for applications requiring low cost analog inter face e g thermostat control pressure sensing etc The PIC16C73 73A devices have 192 bytes of RAM while the PIC16C76 has 368 byes of RAM Each device has 22 UO pins In addition several peripheral features are av
406. two MSbs of the address The sequence of events for 10 bit address is as follows with steps 7 9 for slave transmitter 1 Receive first high byte of Address bits SSPIF BF and bit UA SSPSTAT 1 are set 2 Update the SSPADD register with second low byte of Address clears bit UA and releases the SCL line 3 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 4 Receive second low byte of Address bits SSPIF BF and UA are set 5 Update the SSPADD register with the first high byte of Address if match releases SCL line this will clear bit UA 6 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 7 Receive repeated START condition 8 Receive first high byte of Address bits SSPIF and BF are set 9 Read the SSPBUF register clears bit BF and clear flag bit SSPIF TABLE 11 4 DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF Generate ACK SSP Interrupt occurs BF SSPOV SSPSR SSPBUF Pulse if enabled 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes DS30390E page 94 1997 Microchip Technology Inc Applicable Devices P C 1 6C7X 72 73 73A 74 74A 76 77 11 5 1 2 RECEPTION An SSP interrupt is generated for each data transfer De byte Flag bit SSPIF PIR1 lt 3 gt must be cleared in soft When the R W bit of the address byte is clear and an ware The
407. ue on Value on Address POR all other BOR resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh OCh PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register XXXX xxxx uuuu uuuu SSPCON SSPEN CKP SSPM3 SSPM2 0000 0000 0000 0000 TRISA PORTA Data Direction Register 11 1111 11 1111 94h SSPSTAT SMP CKE D A P S RW UA BF 0000 0000 0000 0000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by the SSP in SPI mode Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C76 always maintain these bits clear IR NAR NC M a DS30390E page 88 1997 Microchip Technology Inc Applicable Devices 72 73 73A 74 74A PIC16C7X 76 77 11 4 12C Overview This section provides an overview of the Inter Inte grated Circuit I2C bus with Section 11 5 discussing the operation of the SSP module in I C mode The I C bus is a two wire serial interface developed by the Philips Corporation The original specification or standard mode was for data transfers of up to 100 Kbps The enhanced specification fast
408. uffered register i e it is a two deep FIFO It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register On the clocking of the last bit of the third byte if the RCREG register is still full then overrun error bit OERR RCSTA 1 is set The word in the RSR will be lost The RCREG register can be read twice to retrieve the two bytes in the FIFO Bit OERR has to be cleared in software by clearing bit CREN If bit OERR is set transfers from the RSR to the RCREG are inhibited so it is essential to clear bit OERR if it is set The 9th receive bit is buffered the same way as the receive data Reading the RCREG register will load bit RX9D with a new value therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information Steps to follow when setting up a Synchronous Master Reception 1 Initialize the SPBRG register for the appropriate baud rate Section 12 1 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC 3 Ensure bits CREN and SREN are clear 4 f interrupts are desired then set enable bit RCIE 5 f9 bit reception is desired then set bit RX9 6 If a single reception is required set bit SREN For continuous reception set bit CREN 7 Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enabl
409. ugh the ADON bit will remain set When the A D clock source is another clock option not RC a SLEEP instruction will cause the present conver sion to be aborted and the A D module to be turned off though the ADON bit will remain set Turning off the A D places the A D module in its lowest current consumption state T Note For the A D module to operate in SLEEP the A D clock source must be set to RC ADCS1 ADCSO 11 To perform an A D conversion in SLEEP ensure the SLEEP instruction immediately follows the instruc tion that sets the GO DONE bit 13 6 A D Accuracy Error Applicable Devices The absolute accuracy specified for the A D converter includes the sum of all contributions for quantization error integral error differential error full scale error off Set error and monotonicity It is defined as the maxi mum deviation from an actual transition versus an ideal transition for any code The absolute error of the A D converter is specified at 1 LSb for VDD VREF over the device s specified operating range However the accuracy of the A D converter will degrade as VDD diverges from VREF For a given range of analog inputs the output digital code will be the same This is due to the quantization of the analog input to a digital code Quantization error is typically 1 2 LSb and is inherent in the analog to dig ital conversion process The only way to
410. uld be in master mode where you are only sending data to a display driver then both SDI and SS could be used as general purpose outputs by clearing their corresponding TRIS register bits Figure 11 4 shows a typical connection between two microcontrollers The master controller Processor 1 initiates the data transfer by sending the SCK signal Data is shifted out of both shift registers on their pro grammed clock edge and latched on the opposite edge of the clock Both processors should be programmed to the same Clock Polarity CKP then both controllers would send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software This leads to three scenarios for data transmission Master sends data Slave sends dummy data Master sends data Slave sends data Master sends dummy data Slave sends data FIGURE 11 4 SPI MASTER SLAVE CONNECTION The master can initiate the data transfer at any time because it controls the SCK The master determines when the slave Processor 2 is to broadcast data by the software protocol In master mode the data is transmitted received as soon as the SSPBUF register is written to If the SPI is only going to receive the SCK output could be disabled programmed as an input The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate As each byte is received it will be loaded into t
411. ule in IC mode works the same in all PIC16C7X devices that have an SSP module However the SSP Module in SPI mode has differences between the PIC16C76 77 and the other PIC16C7X devices The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C76 77 and the other PIC16C7X devices The default reset values of both the SPI modules is the same regardless of the device 11 2 SPI Mode for PIC16C72 73 73A 74 T4A 78 11 8 SPI Mode for PIC16C76 77 83 11 4 12CTM Overview a se aa a aiaa 89 11 5 SSP 12C Operation 93 Refer to Application Note AN578 Use of the SSP Module in the 12C Multi Master Environment 1997 Microchip Technology Inc DS30390E page 77 D l C 1 6C7X Applicable Devices 72 73 73A 74 74A 76 77 11 2 SPI Mode for PIC16C72 73 73A 74 74A This section contains register definitions and opera tional characteristics of the SPI module for the PIC16C72 PIC16C73 PIC16C73A PIC16C74 PIC16C74A FIGURE 11 1 SSPSTAT SYNC SERIAL PORT STATUS REGISTER ADDRESS 94h U 0 U 0 R 0 R 0 R 0 R 0 R 0 R 0 D A P S R W UA BF R Readable bit bit7 bito W Writable bit U Unimplemented bit read as 0 n Value at POR reset bit 7 6 Unimplemented Read as 0 bit 5 D A Data Address bit I C mode only 1 Indic
412. ull scale Analog input voltage 13 11 References A very good reference for understanding A D convert ers is the Analog Digital Conversion Handbook third edition published by Prentice Hall ISBN 0 13 03 2848 0 1997 Microchip Technology Inc DS30390E page 125 PIC16C7X FIGURE 13 6 FLOWCHART OF A D OPERATION Start of A D Finish Conversion A D glock Conversion Delayed 1 Instruction Cycle Nate TM Abort Conversion ini i Wake u Device in G Finish Conversio Fron Sleep Wait 2 TAD O LEEP GO 0 E ADIESO ADIF 1 Finish Conversion SLEEP Stay in Slee GO 0 Power down A D Wait e TAD Power down A D ADIF 1 Wait 2 TAD TABLE 13 2 REGISTERS BITS ASSOCIATED WITH A D PIC16C72 value on Value on all Address Name Bit 2 POR other Resets BOR OBh 8Bh INTCON TOIF 0000 000x 0000 000u DCH PIR1 CCP1IF TMR2IF TMR1IF 0000 0 0000 8Ch PIE1 CCPIIE TMR2IE TMR1IE 0000 0 0000 ADRES A D Result Register ADCONO ADCS1 ADCSO CHS2 GO DONE ADCON1 PCFG2 05h PORTA RA5 RA4 RA3 RA2 RA1 RAO 0x 0000 0u 0000 85h TRISA PORTA Data Direction Register 11 1111 11 1111 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used for A D conversion D
413. um Required Acquisition Time 120 Example 13 2 A D Conversion 122 Example 13 3 4 bit vs 8 bit Conversion Times 123 Example 14 1 Saving STATUS W and PCLATH Registers in RAM 143 1997 Microchip Technology Inc DS30390E page 279 PIC16C7X LIST OF FIGURES Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 4 14 Figure 4 15 Figure 4 16 Figure 4 17 Figure 4 18 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 PIC16C72 Block Diagram PIC16C73 73A 76 Block Diagram PIC16C74 74A 77 Block Diagram ad Clock Instruction Cycle PIC16C72 Program Memory Map and Stack iu uei erede 19 PIC16C73 73A 74 74A Program Memory Map and Stack 19 PIC16C76 77 Program Memory Map and Stack sese 20 PIC16C72 Register File Map 21 PIC16C73 73A 74 74A Register File Map si eccccpcadensnredtsascheasdusdestuctnastesecssen 21 PIC16C76 77 Register File Map
414. ure In Asynchronous Counter mode the compare operation may not work 10 23 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected Only a CCP interrupt is generated if enabled 10 2 4 SPECIAL EVENT TRIGGER In this mode an internal hardware trigger is generated which may be used to initiate an action The special event trigger output of CCP1 resets the TMR1 register pair This allows the CCPR1 register to effectively be a 16 bit programmable period register for Timer1 The special trigger output of CCP2 resets the TMR1 register pair and starts an A D conversion if the A D module is enabled For the PIC16C72 only the special event trigger output of CCP1 resets the TMR1 register pair and starts an A D conversion if the A D module is enabled Note The special event trigger from the CCP1and CCP2 modules will not set inter rupt flag bit TMR1IF PIR1 lt 0 gt 1997 Microchip Technology Inc DS30390E page 73 PIC16C7X 10 3 PWM Mode Applicable Devices 72 73 73A 74 74A 76 77 In Pulse Width Modulation PWM mode the CCPx pin produces up to a 10 bit resolution PWM output Since the CCP1 pin is multiplexed with the PORTC data latch the TRISC lt 2 gt bit must be cleared to make the CCP1 pin an output Note Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level This is not the PORTC I O data latch Figu
415. ures the BRG does not wait for a timer overflow before output ting the new baud rate TABLE 12 1 BAUD RATE FORMULA SYNC BRGH 0 Low Speed BRGH 1 High Speed 0 Asynchronous Baud Rate Fosc 64 X 1 Baud Rate Fosc 16 X 1 1 Synchronous Baud Rate Fosc 4 X 1 NA X value in SPBRG 0 to 255 TABLE 12 2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value an Value on all Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO POR other resets BOR 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D 0000 010 0000 010 18h RCSTA SPEN RX9 SREN CREN FERR OERR RX9D 0000 00x 0000 00x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend x unknown unimplemented read as 0 Shaded cells are not used by the BRG 1997 Microchip Technology Inc DS30390E page 101 PIC16C7X TABLE 12 3 BAUD RATES FOR SYNCHRONOUS MODE BAUD FOSC 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG 7 15909 MHz SPBRG RATE K value value K value value K KBAUD ERROR decimal KBAUD ERROR decimal REAUD ERROR decimal K AUR ERROR decimal 0 3 NA NA NA NA 1 2 NA NA NA NA 24 NA NA NA NA 9 6 NA NA 9 766 41 73 255 9 622 0 23 185 19 2 19 53 1 73 255 19 23 0 16 207 19 23 0 16 129 19 24 0 23 92 76 8 76 92 0 1
416. vices One Time Programmable OTP ssssss Quick Turnaround Production QTP Serialized Quick Turnaround Production SQTP 7 Slave Mode SMP its geret SPBRG 1997 Microchip Technology Inc SPBRG Regisler o ye GU e n aieas 26 28 Special Event Trigger sen 125 Special Features of the CPU ssssee 129 Special Function Registers PIG16Q72 assu ea am ee 23 PIC16C73 e PIG16C 9A EE PIGAG C74 nne UP SUO PIC16C74A x See EE PIG16 Qf ie ote ter eee PN TIRE Special Function Registers Section SPEN bit 3 iioi te ttes SPI Block Diagram sssseseeeeeeeen 80 85 Master Mode AA 86 Master Mode Timing eseseeeeees 87 MOd6 EE 80 Serial Clock 35 Age eegene annie nines 85 Serial Data In ssssssssssseseeenee 85 Serial Data Out eidem etie etre 85 Slave Mode Timing eee 88 Slave Mode Timing Diagram ssssss 87 Slave Select niin rein Re ates 85 SPI clock nin C UNS C ee SPI Mode SSPOONU EE SSPSTAT EE SPI Clock Edge Select bit CKE SPI Data Input Sample Phase Select bit SMP 83 SPI Mode ren ven sr eem eO EH 80 ete Le 80 SSP Mod le OverVieW sic icici racine 77 SECTION sy is onec een dei ee SSPBU E ee tete sania E A SSPCON elc MEME SSPSTAT nacen ede eene res diee des SSP in C M
417. was lost during the address trans fer stage communication to the device may be in progress If addressed an ACK pulse will be generated If arbitration was lost during the data transfer stage the device will need to re transfer the data at a later time TABLE 11 5 REGISTERS ASSOCIATED WITH EC OPERATION Xue on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other resets BOR OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh DCH PIR1 PsPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer Transmit Register FORO OCDOC uuum uuuu 93h SSPADD Synchronous Serial Port IC mode Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 0000 0000 94h SSPSTAT SMP CKE D A P S R W UA BF 0000 0000 0000 0000 87h TRISC PORTO Data Direction register 1111 1111 1111 1111 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used by SSP module in SPI mode PSPIF and PSPIE are reserved on the PIC16C73 73A 76 always maintain these bits clear 2 The SMP and CKE bits are implemented on the PIC16C76 77 only All other PIC16C7X devices hav
418. wnload and source debugging from a single environment Interchangeable target probes allow the system to be easily reconfigured for emulation of different proces sors The universal architecture of the PICMASTER allows expansion to support all new Microchip micro controllers The PICMASTER Emulator System has been designed as a real time emulation system with advanced features that are generally found on more expensive development tools The PC compatible 386 and higher machine platform and Microsoft Windows 3 x environment were chosen to best make these fea tures available to you the end user A CE compliant version of PICMASTER is available for European Union EU countries 16 3 ICEPIC Low cost PIC16CXXX In Circuit Emulator ICEPIC is a low cost in circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8 bit OTP microcontrollers ICEPIC is designed to operate on PC compatible machines ranging from 286 AT through Pentium based machines under Windows 3 x environment ICEPIC features real time non intrusive emulation 16 4 PRO MATE Il Universal Programmer The PRO MATE II Universal Programmer is a full fea tured programmer capable of operating in stand alone mode as well as PC hosted mode The PRO MATE Il has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability It has an LCD display for displaying error mes
419. x xxxx uuuu uuuu 1Ch0 CCPR2H Capture Compare PWM register2 MSB XXXX XXXX uuuu uuuu 1Dh0 CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2MO 00 0000 00 0000 Legend x unknown u unchanged unimplemented read as 0 Shaded cells are not used by Capture and Timer1 Note 1 Bits PSPIE and PSPIF are reserved on the PIC16C73 73A 76 always maintain these bits clear 2 The PIC16C72 does not have a Parallel Slave Port USART or CCP2 module these bits are unimplemented read as 0 1997 Microchip Technology Inc DS30390E page 75 PIC16C7X TABLE 10 5 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Address Name Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR all other BOR resets OBh 8Bh INTCON GIE PEIE TOIE INTE RBIE TOIF INTF RBIF 0000 000x 0000 000u 10Bh 18Bh OCh PIR1 PSPIF 2 ADIF RCIF TxiF SSPIF CCPIIF TMR2IF TMRIIF 0000 0000 0000 0000 ODh PIR2 CCP2IF 0 0 8Ch PIE1 PSPIEU 2 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 0000 0000 0000 0000 8Dh PIE2 CCP2IE 9 0 87h TRISC PORTO Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 modules register 0000 0000 0000 0000 92h PR2 Timer2 module s period register 1111 1111 1111 1111 12h T2C
420. xternal Clock 61 External Clock Timing 61 Increment Delay 61 Interrupt 59 Interrupt Timing 60 Overview 57 Prescaler 62 Prescaler Block Diagram 62 ET EE 59 Switching Prescaler Assignment 63 Synchronization 61 TOGK rss 61 TOUR ina ra Ne IRE 143 Rn WEE 59 TMRO Interrupt eesee 143 Timer1 Asynchronous Counter Mode 67 Block Diagram x Capacitor Selection sssssusss External Clock Input seeren External Clock Input Timing NT Operation in Timer Mode Oscillator Overview Pr scaler saisissant ment Resetting of Timer1 Registers 68 Resetting Timer1 using a CCP Trigger Output 68 Synchronized Counter Mode 66 TICON eut geed DER ERR aetas 65 Timer2 Block Diagram seen 69 Module 69 Overview 57 Postscaler 69 Prescaler 69 TACON E 70 Timing Diagrams A D Conversion eeeses 182 200 218 239 Brown out Reset uuuuesss 134 175 209 228 Capture Compare PWM 177 193 211 230 CLKOUT and WO sss 174 190 208 227 External Clock Timing see
421. xternal reset Watchdog Timer Wake up or through an interrupt Several oscillator options are also made available to allow the part to fit the application The RC oscillator option saves system cost while the LP crystal option saves power A set of configuration bits are used to select various options 14 1 Configuration Bits Applicable Devices 72 73 73A 74 74A 76 77 The configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped in pro gram memory location 2007h The user will note that address 2007h is beyond the user program memory space In fact it belongs to the special test configuration memory space 2000h SFFFh which can be accessed only during program ming FIGURE 14 1 CONFIGURATION WORD FOR PIC16C73 74 CP1 CPO PWRTE WDTE FOSC1 FOSCO Register CONFIG bit13 bito Address 2007h bit 13 5 Unimplemented Read as 1 bit 4 CP1 CP0 Code protection bits 11 Code protection off 10 Upper half of program memory code protected 01 Upper 3 4th of program memory code protected 00 All memory is code protected bit 3 PWRTE Power up Timer Enable bit 1 Power up Timer enabled 0 Power up Timer disabled bit 2 WDTE Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled bit 1 0 FOSC1 FOSCO Oscillator Selection bits 11 RC oscillator 10
422. y reg isters during an interrupt Le W register and STATUS register This will have to be implemented in software Example 14 1 stores and restores the STATUS W and PCLATH registers The register W_TEMP must be defined in each bank and must be defined at the same offset from the bank base address i e if W_TEMP is defined at 0x20 in bank 0 it must also be defined at OxA0 in bank 1 The example a Stores the W register Stores the STATUS register in bank 0 C Stores the PCLATH register o Executes the ISR code Restores the STATUS register and bank select bit f Restores the W and PCLATH registers ba REGISTERS IN RAM MOVWF W TEMP Copy W to TEMP register could be bank one or zero SWAPE STATUS W Swap status to be saved into W CLRE STATUS bank 0 regardless of current bank Clears IRP RP1 RPO MOVWE STATUS TEMP Save status to bank zero STATUS TEMP register MOVF PCLATH W Only required if using pages 1 2 and or 3 MOVWF PCLATH TEMP Save PCLATH into W CLRF PCLATH Page zero regardless of current page BCF STATUS IRP Return to Bank O0 MOVF FSR W Copy FSR to W MOVWE FSR TEMP Copy FSR from W to FSR TEMP ISR MOVF PCLATH TEMP W Restore PCLATH MOVWF PCLATH Move W into PCLATH SWAPF STATUS TEMP W Swap STATUS TEMP register into W sets bank to original state MOVWE STATUS Move W into STATUS register SWAPE W TEMP F Swap W TEMP SWAPE W TEMP W Sw
423. ynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 46 TOL T1CKI Low Time Synchronous Prescaler 1 0 5TCY 20 ns Must also meet Synchronous PIC16C7X 15 ns parameter 47 Prescaler PIC16LC7X 25 ns 2 4 8 Asynchronous PIC16C7X 30 ns PIC16LC7X 50 ns 47 TtiP T1CKI input period Synchronous PIC16C7X Greater of ns N prescale value 30 op Tcv 40 1 2 4 8 N PIC16LC7X Greater of N prescale value 50 op TcY 40 1 2 4 8 N Asynchronous PIC16C7X 60 ns PIC16LC7X 100 ns Ft1 Timer1 oscillator input frequency range DC 200 kHz oscillator enabled by setting bit TT OSCEN 48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc 7Tosc t These parameters are characterized but not tested Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested DS30390E page 192 1997 Microchip Technology Inc PIC16C7X Applicable Devices 72173 73A 74 74A 76 77 FIGURE 18 6 CAPTURE COMPARE PWM TIMINGS CCP1 AND CCP2 RC1 T1OSI CCP2 and RC2 CCP1 Capture Mode RC1 T1OSI CCP2 and RC2 CCP1 Compare or PWM Mode 53 Note Refer to Figure 18 1 for load conditions TABLE 18 6 CAPTURE COMPARE PWM REQUIREMENTS CCP1 AND CCP2 Parameter Characteristic Min Units Condit

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