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FAIRCHILD FQT5P10 100V P-Channel MOSFET datasheet

1. Derate above 25 C 0 016 W C Ty Tera Operating and Storage Temperature Range 55 to 4150 C Maximum lead temperature for soldering purposes TL 300 C 1 8 from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units Rosa Thermal Resistance Junction to Ambient 62 5 C W When mounted on the minimum pad size recommended PCB Mount 2002 Fairchild Semiconductor Corporation Rev B August 2002 OldSLOSA Electrical Characteristics Tc 25 C unless otherwise noted 4 Pulse Test Pulse width lt 300us Duty cycle lt 2 5 Essentially independent of operating temperature 1 Repetitive Rating Pulse width limited by maximum junction temperature 2 L 83mH las 1 0A Vpp 25V Re 25 Q Starting Ty 25 C 3 Isp lt 4 5A di dt lt 300A us Vpp lt BVpss Starting Ty 25 C Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVpss Drain Source Breakdown Voltage Ves 0 V Ip 250 uA 100 V ABypss Breakdown Voltage Temperature lp 250 uA Referenced to 25 C 0 ii AT Coefficient D h e Wee Ipss Vps 100 V Vas 0 V m 4 uA Zero Gate Voltage Drain Current Vps 80 V Tg 125 C 7 A0 lA lassr Gate Body Leakage Current Forward Vas 30 V Vps 0 V
2. 100 nA lassR Gate Body Leakage Current Reverse Ves 30 V Vpg 0V 100 nA On Characteristics Vesith Gate Threshold Voltage Vps Vas lp 250 pA 2 0 4 0 Rps on Static Drain Source Vas 10 V Ip 0 5 A On Resistance Gs i OR Tos Q Ors Forward Transconductance Vps 40 V Ip 2 0 5A Note 4 1 4 Dynamic Characteristics Ciss Input Capacitance Vps 25 V Vas 0 V 190 250 pF Coss Output Capacitance f 1 0 MHz 70 90 pF Crsg Reverse Transfer Capacitance 18 25 pF Switching Characteristics ta on Turn On Delay Time Vpp 50 V Ip 4 5 A 9 30 ns ty Turn On Rise Time Re 25Q 70 150 ns la oft Turn Off Delay Time 12 35 ns tr Turn Off Fall Time bo Ta 30 70 ns Qg Total Gate Charge Vps 80 V Ip 4 5 A 6 3 8 2 nC Qgs Gate Source Charge Vas 10 V 1 7 nC Qga Gate Drain Charge Note 4 5 3 0 E nC Drain Source Diode Characteristics and Maximum Ratings ls Maximum Continuous Drain Source Diode Forward Current 1 0 A Ism Maximum Pulsed Drain Source Diode Forward Current 4 0 A Vsp Drain Source Diode Forward Voltage Ves 0 V Is 1 0 A al ie 4 0 V trr Reverse Recovery Time Vas 0 V Ig 4 5 A 85 ns Qrr Reverse Recovery Charge dle dt 100 A us Note 4 0 27 uC Notes 2002 Fairchild Semiconductor Corporation Rev B August 2002 OldSLO4 Typical Characteristics T E 5 46 7 7 Note e 1 2500 s Pulse Test 2 7 2
3. authorized to use and is not ACEx FACT ImpliedDisconnect PACMAN SPM ActiveArray FACT Quiet series SOPLANAR POP Stealth Bottomless FAST LittleFET Power247 SuperSOT 3 CoolFET FASTr MicroFET PowerTrench SuperSOT 6 CROSSVOLT FRFET MicroPak QFET SuperSOT 8 DOME GlobalOptoisolator MICROWIRE Qs SyncFET EcoSPARK GTO MSX QT Optoelectronics TinyLogic E CMOS HiSeC MSXPro Quiet Series TruTranslation EnSigna 2CT OCX RapidConfigure UHC Across the board Around the world OCXPro RapidConnect UltraFET The Power Franchise OPTOLOGIC SILENT SWITCHER VCX Programmable Active Droop OPTOPLANAR SMART START FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or syst
4. 5C D 2 i 10 10 V Drain Source Voltage V 10 Figure 1 On Region Characteristics 25 20r 8 S 25 a g 15b F T Siol 8 E 05b 3 Note T 25C 0 0 i f 0 3 6 9 lp Drain Current A Figure 3 On Resistance Variation vs Drain Current and Gate Voltage 500 Cy Ca shorted 8 s Capacitance pF 8 Vps Drain Source Voltage V Figure 5 Capacitance Characteristics Ea b 150 C 9 N 25 C T 55 C 3 Notes DRY 2 28 s Pise Test 10 1 1 2 4 6 8 10 V Gate Source Voltage V Figure 2 Transfer Characteristics T EM g 10 o E E 150C 250 5 cor 2 2500 s Pulse Test 107 I 1 1 0 0 05 1 0 15 20 25 30 V Source Drain Voltage V Figure 4 Body Diode Forward Voltage Variation vs Source Current and Temperature 12 10r o 8 r S Ke g et 5 B TNR 8 3 Note 45A 0 i i i i i Ll i 0 1 2 3 4 5 6 7 8 Q Total Gate Charge nC Figure 6 Gate Charge Characteristics 2002 Fairchild Semiconductor Corporation Rev B August 2002 OldSLOSA Typical Characteristics coe 12 P E E BS 107 8 M F SN c 1 Vs 0V T 200UA a 08 L L L L L 100 50 0 50 100 150 200 T Junction Terrperature C lp Drain Current A Figure 7 Breakdown Voltage Variation vs Temperature Operation in This Area i isL
5. DABS RAB Mss ARAM MRE au L FAIRCHILD SEMICONDUCTOR FQT5P10 100V P Channel MOSFET General Description These P Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary planar stripe DMOS technology This advanced technology has been especially tailored to minimize on state resistance provide superior switching performance and withstand high energy pulse in the avalanche and commutation mode These devices are well suited for low voltage applications such as audio amplifier high efficiency switching DC DC converters and DC motor control QFET Features e 1 0A 100V Rpgion 1 050 Q Vas 10 V Low gate charge typical 6 3 nC Low Crss typical 18 pF Fast switching Improved dv dt capability G SOT 223 FQT Series Absol ute Maxi mum Rati ngs Tg 25 C unless otherwise noted Symbol Parameter FQT5P10 Units Voss Drain Source Voltage 100 V Ip Drain Current Continuous Tc 25 C 1 0 A Continuous Tc 70 C 0 8 A lpm Drain Current Pulsed Note 1 4 0 A Vass Gate Source Voltage 30 V Eas Single Pulsed Avalanche Energy Note 2 55 mJ lAR Avalanche Current Note 1 1 0 A EAR Repetitive Avalanche Energy Note 1 0 2 mJ dv dt Peak Diode Recovery dv dt Note 3 6 0 V ns Pp Power Dissipation Tc 25 C 2 0 WwW
6. de Reverse Current SD DUT lkm di dt lzm Body Diode Forward Current Vps Vsp DUT 2002 Fairchild Semiconductor Corporation Rev B August 2002 OLdS 104 Package Dimensions OldSLOSA SOT 223 x lt lt S g 3 00 0 10 ud 8 didi MAX1 80 HU 19 e Em n LE q bes e Je 0 007002 S E 2 30 TYP p 0 70 0 10 a o 0 95 4 603025 0 95 0 25 dos 1 75 0 20 3 50 0 20 7 00 0 30 r 60 ole J 6 50 0 20 SiS 1 60 0 20 Dimensions in Millimeters 2002 Fairchild Semiconductor Corporation Rev B August 2002 TRADEMARKS intended to be an exhaustive list of all such trademarks DISCLAIMER LIFE SUPPORT POLICY CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production The following are registered and unregistered trademarks Fairchild Semiconductor owns or is
7. em or to affect its safety or effectiveness This datasheet contains the design specifications for product development Specifications may change in any manner without notice This datasheet contains preliminary data and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only 2002 Fairchild Semiconductor Corporation Rev I1
8. imitedbyR joy X Notes 1 T 25 C 2 T 150 C 3 Single Pulse 10 10 10 10 V Drain Source Voltage V Figure 9 Maximum Safe Operating Area Normalized On Resistance R Drain Souroe 3 0 257 20 o5r 100 50 0 50 100 150 200 o o m lp Drain Current A e Ds 00 T Junction Temperature C Figure 8 On Resistance Variation vs Temperature 25 50 75 100 125 150 T Case Temperature C Figure 10 Maximum Drain Current vs Case Temperature e t 62 5 C W actor D t t To Pow Ze y Z A Thermal Response single pulse 107 10 10 10 10 t Square Wave Pulse Duration sec Figure 11 Transient Thermal Response Curve 2002 Fairchild Semiconductor Corporation Rev B August 2002 OldSLOSA Gate Charge Test Circuit amp Waveform Resistive Switching Test Circuit amp Waveforms Charge 2002 Fairchild Semiconductor Corporation Rev B August 2002 OldSLOA Peak Diode Recovery dv dt Test Circuit amp Waveforms Compliment of DUT N Channel e dv dt controlled by Ra Isp controlled by pulse period Gate Pulse Width Vop Body Diode Forward Voltage Drop Body Diode Recovery dv dt Vas oo SOR oscar sme ds Gate Pulse Period Driver l Body Dio

FAIRCHILD FQT5P10 100V P-Channel MOSFET datasheet

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