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MICROCHIP PIC18F2423/2523/4423/4523 Data Sheet1

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1. FIGURE 18 4 ASYNCHRONOUS TRANSMISSION Write to TXREG CC BRG Output Nora K Shift Clock Le L pti L T L I TX pin r SX Start bit TB gt bt gt S C btr ZSopbt i t Word 1 a gt TXIF bit i Transmit Buffer 1 TOY Reg Empty Flag S Wordi Cana Shit Transmit Shift Reg Reg Empty Flag fa FIGURE 18 5 ASYNCHRONOUS TRANSMISSION BACK TO BACK Write to TXREG CC Word 1 Word 2 2 Shift Clock A Thit N Start bit Abit lt biti gt VV bit 7 8 7 Stop bit Start bi C bto TXIF bit OTV gt k Word a D To TA n a Mora 2 Interrupt Reg Flag TRMT bit Transmit Shift Reg Empty Flag s5 J Word2 Transmit Shift Reg 1 gt 1TcY Wordi Transmit Shift Reg 55 Note This timing diagram shows two consecutive transmissions TABLE 18 5 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 49 PIR1 PSPIF 1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMRZIP TMRIIP 52 RCSTA SPEN RX9 SREN CREN ADDEN FER
2. Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0 80 BSC Overall Height A 1 20 Molded Package Thickness A2 0 95 1 00 1 05 Standoff A1 0 05 0 15 Foot Length L 0 45 0 60 0 75 Footprint L1 1 00 REF Foot Angle 0 3 5 7 Overall Width E 12 00 BSC Overall Length D 12 00 BSC Molded Package Width E1 10 00 BSC Molded Package Length D1 10 00 BSC Lead Thickness c 0 09 0 20 Lead Width b 0 30 0 37 0 45 Mold Draft Angle Top a 11 12 13 Mold Draft Angle Bottom B 11 12 13 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Chamfers at corners are optional size may vary 3 Dimensions D1 and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 25 mm per side 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04 076B 2007 Microchip Technology Inc Preliminary DS39755B page 371 PIC18F2423 2523 4423 4523 44 Lead Plastic Quad Flat No Lead Package ML 8x8 mm Body QFN Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com pack
3. TABLE 6 2 REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO Valueson page TBLPTRU bit 21 Program Memory Table Pointer Upper Byte TBLPTR lt 20 16 gt 49 TBPLTRH Program Memory Table Pointer High Byte TBLPTR lt 15 8 gt 49 TBLPTRL Program Memory Table Pointer Low Byte TBLPTR lt 7 0 gt 49 TABLAT Program Memory Table Latch 49 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 49 EECON2 JEEPROM Control Register 2 not a physical register 91 EECON1 EEPGD CFGS FREE WRERR WREN WR RD 51 IPR2 OSCFIP CMIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 52 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 52 PIE2 OSCFIE CMIE EEIE BCLIE HLVDIE TMRSIE CCP2IE 52 Legend unimplemented read as 0 Shaded cells are not used during Flash EEPROM access DS39755B page 82 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 7 0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array sep arate from the data RAM and program memory that is used for long term storage of program data It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers SFRs The EEPROM is readable and writable during normal operation over the entire VDD range Five SFRs are used to read and wri
4. TABLE 1 2 PIC18LF2423 2523 PINOUT I O DESCRIPTIONS Pin Number Pin Name PDIP Pin Buffer Description Type Type SOIC QFN ype lyp MCLR VPP RE3 1 26 Master Clear input or programming voltage input MCLR ST Master Clear Reset input This pin is an active low Reset to the device VPP P Programming voltage input RE3 ST Digital input OSC1 CLKI RA7 9 6 Oscillator crystal or external clock input OSC1 l ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode CMOS otherwise CLKI CMOS External clock source input Always associated with pin function OSC1 See related OSC1 CLKI OSC2 CLKO pins RA7 VO TTL General purpose I O pin OSC2 CLKO RA6 10 7 Oscillator crystal or clock output OSC2 O Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode CLKO O In RC mode OSC2 pin outputs CLKO which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate RA6 VO TTL General purpose I O pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Default assignment for CCP2 when Configuration bit CCP2MX is set 2 Alternate assignment for CCP2 when Configuration bit CCP2MX is cleared DS39755B page 12 Preliminary 2007 Microchip Technology lnc PIC18F2423 2523 4423 4523
5. HLVDIF TABLE 26 4 HIGH LOW VOLTAGE DETECT CH T TICS Standard Operating Conditions unless otherwise s Operating temperature 40 C lt TA lt 85 C for industrial prd Sym Characteristic Min Typt Max Units Conditions D420 HLVD Voltage on VoD H L lt 3 0 gt 0000 2 12 2 17 2 22 V Transition High to Low gt 0001 2 18 2 23 2 28 V HL 0 gt 0010 2 31 2 36 2 42 V e 0011 2 38 2 44 2 49 V DL lt 3 0 gt 0100 2 54 2 60 2 66 V HLVDL lt 3 0 gt 0101 2 72 2 79 2 85 V HLVDL lt 3 0 gt 0110 2 82 2 89 2 95 V HLVDL lt 3 0 gt 0111 3 05 3 12 3 19 V HLVDL lt 3 0 gt 1000 3 31 3 39 3 47 V HLVDL lt 3 0 gt 1001 3 46 3 55 3 63 V HLVDL lt 3 0 gt 1010 3 63 3 71 3 80 V HLVDL lt 3 0 gt 1011 3 81 3 90 3 99 V HLVDL lt 3 0 gt 1100 4 01 4 11 4 20 V N HLVDL lt 3 0 gt 1101 4 23 4 33 4 43 V HLVDL lt 3 0 gt 1110 4 48 4 59 4 69 V Production tested at TAMB 25 C Specifications over temperature limits ensured by characterization 2007 Microchip Technology Inc Preliminary DS39755B page 341 PIC18F2423 2523 4423 4523 26 4 AC Timing Characteristics 26 4 1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats 1 TppS2ppS 3 TCC ST 2C specifications on 2 TppS 4 Ts IC specifications IN T F Frequency T Time Lowe
6. Fail Safe Clock Monitor FSCM Generic I O Port High Low Voltage Detect with External Input Interrupt LO C 2 U n Tu Qui oiiire dih MSSP I2C Master Mode aaa MSSP I2C Mode MSSP SPI Mode a On Chip Reset Circuit a PIC18F 2423 2523 PIC18F 4423 4523 PLL CHS Mode ssh an Asien aaa aware PORTD and PORTE Parallel Slave Port PWM Operation Simplified Reads from Flash Program Memory Single Comparator Table Read Operation Table Write Operation Table Writes to Flash Program Memory dest TimerO in 16 Bit Mode TimerO in 8 Bit Mode TIMOR u Aa Gk Timer1 16 Bit Read Write Mode Timer1 LP Oscillator TIMEZ in eth ested de TIME Beste Sas S A Timer3 16 Bit Read Write Mode Watchdog Timer BOW acids battalion andes adhd Matec 285 BA ur nani wh n RR 283 BRG See Baud Rate Generator Brown out Reset BOR 44 Detecting sat Disabling in Sleep Mode a a
7. SCS1 SCS0 bits Changed 91 a Q3 Q1 Q2 Q3 Q4 Q1 AZ AZ INTOSC We oh r is oe a Multiplexer z v 7 osci UYVUJ U HU U UUL TPU Nj elds 2 u s s ee PLL Glock ind nn A Clock on 1 a CPU Clock JA j Transition n ATA a Perpheral MY asa a s FL s AL Progam PC PC 2 K PC 4 OSTS bit Set Note1 Tost 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 2 4 Tosc DS39755B page 36 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 3 3 Sleep Mode The power managed Sleep mode in the PIC 18LF2423 2523 4423 4523 devices is identical to the legacy Sleep mode offered in all other PIC devices It is entered by clearing the IDLEN bit the default state on device Reset and executing the SLEEP instruction This shuts down the selected oscillator Figure 3 5 All clock source status bits are cleared Entering the Sleep mode from any other mode does not require a clock switch This is because no clocks are needed once the controller has entered Sleep If the WDT is selected the INTRC source will continue to operate If the Timer1 oscillator is enabled it will also continue to run When a wake event occurs in Sleep mode by interrupt Reset or WDT time out the device will not be clocked until th
8. FIGURE 11 1 TIMERO BLOCK DIAGRAM 8 BIT MODE Fosc 4 0 9 Sync with Set 1 Internal gt TMROL 1 gt TMROIF TOCKI pin Programmable S Clocks on Overflow Prescaler s TOSE 2 Tcy Delay TOCS h 8 TOPS2 TOPSO 8 PSA Internal Data Bus Note Upon Reset Timer0 is enabled in 8 bit mode with clock input from TOCKI max prescale FIGURE 11 2 TIMERO BLOCK DIAGRAM 16 BIT MODE Fosc 4 0 o Sync with TMRO Set 1 intemal m TMROL High Byte P gt TMR0IF TOCKI pin Programmable _ 1 ocks on Overflow P Prescaler 7X F s Ne TOSE 2 Tcy Delay Tocs 3 Ais Read TMROL TOPS2 TOPSO Write TMROL PSA Lig rite 0 T8 V TMROH 8 lt Z Internal Data Bus Note Upon Reset Timer0 is enabled in 8 bit mode with clock input from TOCKI max prescale DS39755B page 124 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 11 3 An 8 bit counter is available as a prescaler for the Timer0 module The prescaler is not directly readable or writable its value is set by the PSA and TOPS2 TOPSO bits TOCON lt 3 0 gt which determine the prescaler assignment and prescale ratio Prescaler Clearing the PSA bit assigns the prescaler to the Timer0 module When it is assigned prescale values from 1 2 through 1 256 in power of 2 increments are selectable When assigned to the Timer0 module all instructions writing to the TMRO register e g CLRF TMRO MOVWF TMRO BSF TMRO etc clea
9. 318 Indirect Addressing teas 69 INFSNZ zor i aa qa in pQ ah aa 293 Initialization Conditions for all Registers 49 52 Instr etion Gycl e_ a a a a yapaku asa cee 57 Clocking Scheme 57 Instruction Flow Pipelining 57 Instruction Set ADDWF Indexed Literal Offset Mode 319 ADDWFC ANDLW CPFSEQ CPFSGT CPFSLT INCFSZ INFSNZ RETLW RETURN DS39755B page 380 Preliminary 2007 Microchip Technology lnc PIC18F2423 2523 4423 4523 SETF Indexed Literal Offset Mode 319 SEBEP u tn A aa 306 Standard Instructions ae SUBFWB uuu au tear aaa Tua D ie 306 SUBLW SUBWF NY SUBWEB sm aa anna ayaqa ra 308 Summary hnus vade V RA 271 SWAPF 308 TBLRD 309 TBLWT 310 TSTFSZ 311 XORLW 311 XORWE La k apa aS la a 312 INTCON Registers a 93 95 Inter Integrated Circuit See IC Internal Oscillator Block 26 Adj stment_ erna apisan N us yas 26 INTIQ MOd S uu aa u ua cine teenie ty 26 INTOSC Frequency Drift 26 INTOSC Output Frequency 26 OSCTUNE Register
10. I TPwRT PWRT TIME OUT lt TOST OSC1 TO AASV OST TIME OUT INTERNAL RESET FIGURE 4 7 TIME OUT SEQUENCE ON POR w PLL ENABLED MCLR TIED TO Vpp VDD MCLR INTERNAL POR 2 TPWRT PWRT TIME OUT TOST OSC1 SOV OST TIME OUT aes em emas PLL TIME OUT INTERNAL RESET Note Tost 1024 OSC1 cycles TPLL 2 ms max 2007 Microchip Technology Inc Preliminary DS39755B page 47 PIC18F2423 2523 4423 4523 4 6 Most registers are unaffected by a Reset Their status is unknown on POR and unchanged by all other Resets The other registers are forced to a Reset state depending on the type of Reset that occurred Reset State of Registers Most registers are not affected by a WDT wake up since this is viewed as the resumption of normal oper ation Status bits from the RCON register RI TO PD POR and BOR are set or cleared differently in different Reset situations as indicated in Table 4 3 These bits are used in software to determine the nature of the Reset Table 4 4 describes the Reset states for all of the Special Function Registers These are categorized by Power on and Brown out Resets Master Clear and WDT Resets and WDT wake ups TABLE 4 3 STATUS BITS THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Cosas Program RCON Register STKPTR Re
11. a 26 PLL in INTOSC Modes 26 Internal RC Oscillator Use with WDT sasi ir 262 Internet Address a Interrupt Sources a aa A D Conversion Complete Interrupt on Change RB7 RB4 INTI Pitu sasha a hr TMR0 TMR2 to PR2 Match PWM TMR3 Overflow Interrupts i a a e maven ve u yuy as Interrupts Flag Bits Interrupt on Change RB7 RB4 Flag RBIF Bit an aaa asas antay ats aaa sas 108 INTOSC INTRC See Internal Oscillator Block EA A te ike 294 IORWF 294 IPR R GISTOTS ticcceccedecccdiedadicesesdasssccdcesececieechiedevsrvednevsiensed 100 L LES Risks ened Hu tind 295 Low Voltage ICSP Programming See Single Supply ICSP Programming M Master Clear MCLR u 43 Master Synchronous Serial Port MSSP See MSSP Memory Organization Data Memory u Program Memory sin ssa an Memory Programming Requirements k Microchip Internet Web Site Migration from Baseline to Enhanced Devices l u 374 Migration from High End to Enhanced Devices a 375 Migration from Mid Range to Enhanced Devices a 375 MOVE ii is iii au NAN 295 MOVEF
12. Note 1 lnstruction cycle period Tcy eguals four times the input oscillator time base period for all configurations except PLL All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKI pin When an external clock input is used the max cycle time limit is DC no clock for all devices DS39755B page 344 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 TABLE 26 7 PLL CLOCK TIMING SPECIFICATIONS Vpp 4 2V TO 5 5V ta Sym Characteristic Min Typt Max Units C F10 Fosc Oscillator Frequency Range 4 10 MHz o nly F11 Fsys On Chip VCO System Frequency 16 40 de only F12 tre PLL Start up Time Lock Time 2 F13 ACLK CLKO Stability Jitter 2 5 Data in Typ column is at 5V 25 C unless otherwise stated These parameters A guidance only and are not tested TABLE 26 8 AC CHARACTERISTICS INTERNAL RC ACOJRA PIC18F2423 2523 442 STRIAL PIC18LF2423 2523 44 P2ZXINDUSTRIAL PIC18LFX423 X523 Standard Operating Conditia less otherwise stated
13. PORTE Data Latch Register 52 Read and Write to Data Latch TRISE IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISEO 52 ADCON1 VCFG1 VCFGO PCFG3 PCFG2 PCFGI PCFGO 51 Legend unimplemented read as o Shaded cells are not used by PORTE Note 1 Implemented only when Master Clear functionality is disabled MCLRE Configuration bit 0 2 REBis the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 2007 Microchip Technology Inc Preliminary DS39755B page 119 PIC18F2423 2523 4423 4523 10 6 Parallel Slave Port Note The Parallel Slave Port is only available on 40 44 pin devices In addition to its function as a general I O port PORTD can also operate as an 8 bit wide Parallel Slave Port PSP or microprocessor port PSP operation is con trolled by the 4 upper bits of the TRISE register Register 10 1 Setting control bit PSPMODE TRISE lt 4 gt enables PSP operation as long as the Enhanced CCP module is not operating in Dual Output or Quad Output PWM mode In Slave mode the port is asynchronously readable and writable by the external world The PSP can directly interface to an 8 bit micro processor data bus The external microprocessor can read or write the PORTD latch as an 8 bit latch Setting the control bit PSPMODE enables the PORTE I O pins to become control input
14. DS39755B page 58 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 5 3 Data Memory Organization Note The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled See Section 5 5 Data Memory and the Extended Instruction Set for more information The data memory in PIC 18 devices is implemented as static RAM Each register in the data memory has a 12 bit address allowing up to 4096 bytes of data memory The memory space is divided into as many as 16 banks that contain 256 bytes each PIC18LF2423 2523 4423 4523 devices implement all 16 banks Figure 5 5 shows the data memory organization for the PIC18LF2423 2523 4423 4523 devices The data memory contains Special Function Registers SFRs and General Purpose Registers GPRs The SFRs are used for control and status of the controller and peripheral functions while GPRs are used for data storage and scratchpad operations in the user s application Any read of an unimplemented location will read as 0 s The instruction set and architecture allow operations across all banks The entire data memory may be accessed by Direct Indirect or Indexed Addressing modes Addressing modes are discussed later in this subsection To ensure that commonly used registers SFRs and select GPRs can be accessed in a single cycle PIC18 devices implement an Access Bank This is a 25
15. PORTC Register RC3 SCK SCL Pin ereere 177 TRISCG Register Jaana apasaq aaa aus 111 PORTD Associated Registers 116 LATD Register Parallel Slave Port PSP Function 114 PORTD Register 114 TRISD Register asahan a aaa onen 114 PORTE Associated Registers 119 LATE Register 117 PORTE Register 117 PSP Mode Select PSPMODE Bit we 114 TRISE Register 117 Power Managed Modes 33 and A D Operation 234 and Multiple Sleep Commands 34 and PWM Operation w 159 and SPI Operation 169 Clock Transitions and Status Indicators 34 Effects on Clock Sources 31 Entering k Exiting Idle and Sleep Modes 39 by Interrupt a 39 by Reset a by WDT Time out u 39 Without a Start up Delay 40 Idle Modes z PRISIDEE sd TA 38 RG IDLE u NA 39 SEC IDLE Be RunModes stotin Gh Ni is hana 34 PRIIRUN sits cnn cid eave ua raters 34 RC_RUN M SEC RUN uzanan a A 34 Select aru mz imaka maki riSI a suk mimik sa Sleep Mode oF Summary
16. Y Comparator K PR2 1 1 to 1 16 A Set TMR2IF Postscaler TMR2 Output to PWM or MSSP TMR2 PR2 Match Internal Data Bus TABLE 13 1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 49 PIR1 PSPIF 1 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 52 TMR2 Timer2 Register 50 T2CON T20UTPS3 T2OUTPS2 T2OUTP S1 T2OUTPSO TMR2ON T2CKPS1 T2CKPSO 50 PR2 Timer2 Period Register 50 Legend unimplemented read as 0 Shaded cells are not used by the Timer2 module Note 1 These bits are unimplemented on 28 pin devices always maintain these bits clear DS39755B page 134 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 14 0 TIMER3 MODULE A simplified block diagram of the Timer3 module is shown in Figure 14 1 A block diagram of the module s The Timer3 module timer counter incorporates these operation in Read Write mode is shown in Figure 14 2 atas The Timer3 module is controlled through the T3CON e Software selectable operation as a 16 bit timer or register Register 14 1 It also selects
17. 125 Prescaler Select TOPS2 TOPSO Bits 125 Prescaler See Prescaler Timer0 Reads and Writes in 16 Bit Mode 124 Source Edge Select TOSE Bit 124 Source Select TOCS Bit a 124 Switching Prescaler Assignment 125 MINET ailea ae N eaa s 127 16 Bit Read Write Mode 129 Associated Registers te Interr pt hee ccc hake eae ao ch a GA Chois ta Operation aym a a aa lt usa Aus ca Oscillator x Layout Considerations 130 Overflow Interrupt a 127 Resetting Using the CCP Special Event Trigger 130 TMRIH Register s 127 TMRIL Register siriana 127 Use as a Real Time Clock 130 WIMOr 2a e aa anil 133 Associated Registers 134 Interrupt 134 Operation 133 QUU aaa ain naa Q a awa r 134 PR2 Register au ua al a aaa la 144 149 TMR2 to PR2 Match Interrupt sle STANO P aV O IN DN npr 135 16 Bit Read Write Mode 137 Associated Registers s Interri pi zis a stiahni Operation sosna n Oscillator sf Overflow Interrupt a Special Event Trigger CCP 137 TM
18. Note I O pins have diode protection to VDD and Vss DS39755B page 120 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 FIGURE 10 3 PARALLEL SLAVE PORT WRITE WAVEFORMS ai 02 Q3 A ai 02 ga a4 ai 02 ga A CS w LC KK RD i PORTD lt 7 0 gt IBF OBF PSPIF FIGURE 10 4 PARALLEL SLAVE PORT READ WAVEFORMS a Q a o4 Q Q3 a A QI Q2 Q3 Q4 CS sea WA RD PORTD lt 7 0 gt i IBF OBF PSPIF Id a TABLE 10 11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO 52 LATD PORTD Data Latch Register Read and Write to Data Latch 52 TRISD PORTD Data Direction Control Register 52 PORTE RE3 RE2 RE1 REO 52 LATE PORTE Data Latch Register 52 Read and Write to Data Latch TRISE IBF OBF IBOV PSPMODE TRISE2 TRISE1 TRISEO 52 INTCON GIE GIEH PEIE GIEL TMROIF INTOIE RBIE TMROIF INTOIF RBIF 49 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMRZIE TMR1IE 52 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 52 ADCON1 VCFG1 VCFGO PCFG3 PCFG2 PCFG1 PCFGO 51 Legend unimplemented re
19. 48 Rosats un nana 41 253 Brown out Reset BOR c cece eee eeeeeeeeeeee 253 Oscillator Start up Timer OST 253 Power on Reset POR 253 Power up Timer PWRT 253 PREMENE Z k NA N NA wanna BET EW el qo saa Ak kutaka a k dov RETURN S Return Address Stack aa 54 Return Stack Pointer STKPTR 55 Revision History SDO x SEC IDLE Mode saa a nu RSS S 38 SEC RUN Mode ati iciiags alien i Rat ha dae dur 34 2007 Microchip Technology Inc Preliminary DS39755B page 383 PIC18F2423 2523 4423 4523 Serial Clock SEK 11 1 211180200 1021 110x011 Tula SS Cos 161 Serial Data In SDI u 161 Serial Data Out SDO 1 161 Serial Peripheral Interface See SPI Mode SELF sits yumana m a tinh ete aaah 305 Single Supply ICSP Programming Slave Select SS 161 SLEEP Ha teks dls ae sau LAI otek de ther Ei 306 Sleep OSC1 and OSC2 Pin States 31 Software Simulator MPLAB SIM 322 Special Event Trigger See Compare ECCP Mode Special Features of the CPU Special Function Registers oot MAREA PEE O ov SPI Mode
20. 2007 Microchip Technology Inc Preliminary DS39755B page 389 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Duluth GA Tel 678 957 9614 Fax 678 957 1455 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Habour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shangha
21. The interrupt could cause the execution of an ISR VB which would allow the application to perform house keeping tasks and perform a controlled shutdown before the device voltage exits the valid operating range at TB The HLVD thus would give the applica tion a time window represented by the difference between TA and TB to safely exit Voltage TA TB Time Legend VA HLVD trip point VB Minimum valid device operating voltage DS39755B page 250 Preliminary 2007 Microchip Technology Inc 22 6 Operation During Sleep PIC18F2423 2523 4423 4523 When enabled the HLVD circuitry continues to operate during Sleep If the device voltage crosses the trip point the HLVDIF bit will be set and the device will wake up from Sleep Device execution will continue from the interrupt vector address if interrupts have 22 7 Effects of a Reset A device Reset forces all registers to their Reset state This forces the HLVD module to be turned off been globally enabled TABLE 22 1 REGISTERS ASSOCIATED WITH HIGH LOW VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page HLVDCON VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDLO 50 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 49 PIR2 OSCFIF CMIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 52 PIE2 OCSFIE CMIE EEIE BC
22. a GO DONE Bit ee ADCONI Register u u ADCONZ2 Register u u u ADDFSR sn ADDLW ADDWF ADRESH Register acinus s ADRESL Register Juga aaa qaq aaa ease Analog to Digital Converter See A D ANDDWS m sS au 278 ANDWE sizisai van akva 279 Assembler MPASM Assembler nn 322 B Bank Select Register BSR 59 Baud Rate Generator 2007 Microchip Technology Inc Preliminary Block Diagrams AID side ut aaa b Nha Analog Input Model a Baud Rate Generator Capture Mode Operation a 141 Comparator Analog Input Model 241 Comparator I O Operating Modes 238 Comparator Output teeeeeeeees 240 Comparator Voltage Reference 244 Comparator Voltage Reference Output Buffer Example 245 Compare Mode Operation 142 Device Clock 28 Enhanced PWM a 149 EUSART Receive 217 EUSART Transmit 215 External Power on Reset Circuit Slow VDD Power up
23. 184 10 Bit Slave Transmit Mode 184 7 Bit Slave Receive Mode SEN 1 184 7 Bit Slave Transmit Mode 184 Clock Synchronization and the CKP bit Effects of a Reset General Call Address Support 2C Clock Rate w BRG Master Mode Operation suasana aayqa aaa ua awa Becepti fiua ua nuan waywash ui s Repeated Start Condition Timing Start Condition Timing TANSMISSION Es u a hran Multi Master Communication Bus Collision and Arbitration nn nn Multi Master Mode Operation sipaise vana Read Write Bit Information R W Bit Registers zis sla Masia epimers Serial Clock RC3 SCK SCL Slave Mod u aa AA Addressing Reception Transmission u ANAL Na Sleep Operation Stop Condition Timing IB Eo atior1lSiszu oaa ma ui a ias eee INGE V aN INGESZ u eerie taal een ee tn AAA ees 293 In Circuit Debugger u u 270 In Circuit Serial Programming ICSP 253 270 Indexed Literal Offset Addressing and Standard PIC18 Instructions ee 318 Indexed Literal Offset Mode
24. 2007 Microchip Technology Inc Preliminary DS39755B page 365 PIC18F2423 2523 4423 4523 Package Marking Information Continued 44 Lead TQFP Example MICROCHIP MICROCHIP XXXXXXXXXX PIC18F4423 XXXXXXXXXX PT e3 XXXXXXXXXX 0710017 O YYWWNNN O 44 Lead GFN Example S 8 XXXXXXXXXX PIC18F4523 XXXXXXXXXX I ML es XXXXXXXXXX 0710017 YYWWNNN DS39755B page 366 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 28 2 Package Details The following sections give the technical details of the packages 28 Lead Skinny Plastic Dual In Line SP 300 mil Body SPDIP Note For the most current package drawings please see the Microchip Packaging Specification located at http Awww microchip com packaging N Mo a a a s Ea ES h Ps ra i NOTE 1 Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 28 Pitch e 100 BSC Top to Seating Plane A _ _ 200 Molded Package Thickness A2 120 135 150 Base to Seating Plane Al 015 _ _ Shoulder to Shoulder Width E 290 310 335 Molded Package Width E1 240 285 295 Overall Length D 1 345 1 365 1 400 Tip to Seating Plane L 110 130 150 Lead Thickness c 008 010 015 Upper Lead Width b1 040 050 070 Lower Lead Width b 014 018 022 Overa
25. 349 CLKO and I O s Clock Synchronization 185 Clock Instruction Cycle 57 DS39755B page 384 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 EUSART Synchronous Receive Time out Sequence on POR w PLL Enabled Master Slave u 359 MCLR Tied to VDD 47 EUSART Synchronous Transmission Time out Sequence on Power up Master Slave 359 MCLR Rises After TosT Completes 46 Example SPI Master Mode CKE 0 351 Time out Sequence on Power up Example SPI Master Mode CKE 1 Pp MCLR Rises Before TosT Completes 46 Example SPI Slave Mode CKE 0 353 Time out Sequence on Power up Example SPI Slave Mode CKE 1 354 MCLR Tied to VDD VDD Rise lt TPWRT 46 External Clock All Modes Except PLL 344 TimerO and Timer1 External Clock 348 Fail Safe Clock Monitor FSCM 266 Transition for Entry to Idle Mode 38 First Start Bit Timing 193 Transition for Entry to SEC RUN Mode we 935 Full Bridge PWM Output 153 Transition for Entry to S
26. 2 See Register 23 12 and Register 23 13 for DEVID1 and DEVID2 values DEVID registers are read only and cannot be programmed by the user 2007 Microchip Technology Inc Preliminary DS39755B page 253 PIC18F2423 2523 4423 4523 REGISTER 23 1 CONFIG1H CONFIGURATION REGISTER 1 HIGH BYTE ADDRESS 300001h R P 0 R P 0 U 0 U 0 R P 0 R P 1 R P 1 R P 1 IESO FCMEN FOSC3 FOSC2 FOSC1 FOSCO bit 7 bit 0 Legend R Readable bit n Value when device is unprogrammed P Programmable bit U Unimplemented bit read as 0 u Unchanged from programmed state bit 7 IESO Internal External Oscillator Switchover bit 1 Oscillator Switchover mode enabled 0 Oscillator Switchover mode disabled bit 6 FCMEN Fail Safe Clock Monitor Enable bit 1 Fail Safe Clock Monitor enabled 0 Fail Safe Clock Monitor disabled bit 5 4 Unimplemented Read as 0 bit 3 0 FOSC3 FOSCO Oscillator Selection bits 11xx External RC oscillator CLKO function on RA6 101x External RC oscillator CLKO function on RA6 1001 Internal oscillator block CLKO function on RA6 port function on RAZ 1000 Internal oscillator block port function on RA6 and RA7 0111 External RC oscillator port function on RA6 0110 HS oscillator PLL enabled Clock Frequency 4 x FOSC1 0101 EC oscillator port function on RA6 0100 EC oscillator CLKO function on RA6 0011
27. In addition to being a primary clock source the internal oscillator block is available as a power managed mode clock source The INTRC source is also used as the clock source for several special features such as the WDT and Fail Safe Clock Monitor The clock sources for the PIC18LF2423 2523 4423 4523 devices are shown in Figure 2 8 See Section 23 0 Special Features of the CPU for Configuration register details PIC18LF2423 2523 4423 4523 CLOCK DIAGRAM BRS a A OSCTUNE lt 6 gt ae 1 Secondary Oscillator oscz Xx gt OSC1 gt x NCLIOSCEN T1OSO gt Oscillator T1OSI X sT OSCCON lt 6 4 gt lI Internal Oscillator Block 8 MHz Source 8 MHz gt INT INTRC NTOSG Source Postscaler PIC18F2423 2523 4423 4523 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 1 31 kHz 31 kHz INTRC joe LP XT HS RC EC HSPLL INTOSC PLL Peripherals TIOSC MUX Internal Oscillator 10 100 x Control gt 011 gt 010 FOSC3 FOSCO OSCCON lt 1 0 gt 00 Clock Source Option for other Modules OSCTUNE lt 7 gt WDT PWRT FSCM and Two Speed Start up DS39755B page 28 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 2 7 1 OSCILLATOR CONTROL REGISTER The OSCCON register Register 2 2 controls several
28. 4 MHz Without hardware multiply 13 69 8 63 us 27 6 us 69 us 8 x 8 unsigned Hardware multiply 1 1 125 ns 400 ns 1 us Without hardware multiply 33 91 11 4 us 36 4 us 91 us 8 x 8 signed s Hardware multiply 6 6 750 ns 2 4 us 6 us Without hardware multiply 21 242 30 3 us 96 8 us 242 us 16 x 16 unsigned Hardware multiply 28 28 3 5 us 11 2 us 28 us Without hardware multiply 52 254 31 8 us 102 6 us 254 us 16 x 16 signed Hardware multiply 35 40 5 0 us 16 0 us 40 us 2007 Microchip Technology Inc Preliminary DS39755B page 89 PIC18F2423 2523 4423 4523 Example 8 3 shows the sequence to do a 16 x 16 unsigned multiplication Equation 8 1 shows algorithm that is used The 32 bit result is stored in four the EQUATION 8 2 16x 16 SIGNED MULTIPLICATION ALGORITHM registers RES3 RES0 RES3 RESO ARGIH ARGIL ARG2H ARG2L ARGIH e ARG2H e 216 EQUATION 8 1 16 x 16 UNSIGNED ARGIH e ARG2L e 28 MULTIPLICATION ARGIL ARG2H 25 ALGORITHM ARGIL e ARG2L 1 ARG2H lt 7 gt e ARGIH ARGIL e 2 RES3 RESO ARGIH ARGIL ARG2H ARG2L 1 ARGIH lt 7 gt e ARG2H ARGZL e 216 ARGIHe ARG2H e 2 ARGIH e ARG2L e 28 ARGIL ARG2H e 28 EXAMPLE 8 4 16 x 16 SIGNED ORGIES BRGY MULTIPLY ROUTINE OVF ARGIL W EXAMPLE 8 3 16 x 16 UNSIGNED ULWF ARG2L ARG1L ARG2L gt MULTIPLY ROUTINE i PRODH PRO
29. Normal PWM ECCPASE Cleared by Start of Shutdown Shutdown Firmware PWM PWM Period Event Occurs Event Clears Resumes DS39755B page 158 Preliminary 2007 Microchip Technology Inc PIC18F2423 2523 4423 4523 16 4 9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation 1 Configure the PWM pins PIA and P1B and P1C and P1D if used as inputs by setting the corresponding TRIS bits 2 Set the PWM period by loading the PR2 register 3 If auto shutdown is required e Disable auto shutdown ECCPASE 0 Configure source FLTO Comparator 1 or Comparator 2 e Wait for non shutdown condition 4 Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values Select one of the available output configurations and direction with the P1M1 P1M0 bits Select the polarities of the PWM output signals with the CCP1M3 CCP1MO bits 5 Set the PWM duty cycle by loading the CCPRIL register and CCP1CON lt 5 4 gt bits 6 For Half Bridge Output mode set the dead band delay by loading ECCP1DEL lt 6 0 gt with the appropriate