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CIRRUS LOGIC CS1600 Manual

1. gt EE A CIRRUS LOGIC CS1600 Low cost PFC Controller for Electronic Ballasts Features D Lowest PFC System Cost for Electronic Ballasts D Variable Frequency Discontinuous Conduction Mode U Improved Efficiency Due to Variable Switching Frequency LJ EMI Signature Reduction from Digital Noise Shaping Integrated Feedback Compensation LJ Overvoltage Protection with Hysteresis D Overpower Protection with Shutdown D UVLO with Wide Hysteresis D Thermal Shutdown with Hysteresis Advance Product Information Cirrus Logic Inc http www cirrus com Description CS1600 is a high performance Variable Frequency Discontinu ous Conduction Mode VF DCM active Power Factor Correction PFC controller optimized to deliver the lowest PFC system cost for electronic ballast applications A variable ON time variable frequency algorithm is used to achieve near unity power factor This algorithm spreads the EMI frequency spectrum which reduces the conducted EMI filtering requirements The feedback loop is closed through an integrated compensation network within the IC eliminating the need for additional external components Protection features such as overvoltage overcurrent overpower open and short circuit pro tection overtemperature and brownout help protect the device during abnormal transient conditions Pin Assignments NC o NC
2. Cirrus Logic Sales Representative To find one nearest you go to http www cirrus com IMPORTANT NOTICE Advance product information describes products that are in development and subject to development changes Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives con sent for copies to be made of the information only for use within your organizati
3. STBY VDD IAC GD FB GND 8 lead SOIC Copyright Cirrus Logic Inc 2010 All Rights Reserved CS1600 STBYOQ O Rzb R2c C3a Ciink M 7 This document contains information for a product under development Cirrus Logic reserves the right to modify this product without notice JUN 10 DS904A6 CS1600 CIRRUS LOGIC 1 PIN DESCRIPTIONS NC 1 8 NC STBY 2 7 VDD IAC 3 6 GD FB 4 5 GND Table 1 Pin Descriptions Pin Name Pin 1 0 Description No Connect Connect these pins to Vpp to prevent any leakage path that could arise from leaving them unterminated Standby This is an active low pin Shorting this pin to GND disables PFC switch STBY 2 IN ing The input has a pull up resistor and should be driven with an open collector device Leave this pin unterminated when not in use Rectified Line Voltage Sense The IAC pin is used to sense the rectified line volt age This signal in conjunction with the signal on the FB pin is used in the Power IAC 3 IN Factor Correction PFC algorithm A filter capacitor of up to 2 2 nF may be added between this pin and VDD to provide noise immunity Feedback Voltage Sense The FB pin is used to sense the output voltage of the PFC stage This signal in conjunct
4. as a time averaged quantity STBY is designed to be driven by an open collector device The input is internally pulled up with a 600 kQ resistor The package thermal impedance is calculated in accordance with JESD 51 For an output voltage Vout other than 460V the threshold scales by a factor of Vout 460 DS904A6 CIRRUS LOGIC 3 TYPICAL ELECTRICAL PERFORMANCE CS1600 3 5 13 3 C 1 nF fg 70 kHz 25 Ty 25 C Startup UVLO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 Vpp V Figure 1 UVLO Characteristics 0 50 TEMP 9C T 100 150 Figure 2 Start up amp UVLO vs Temperature Ipp 20 mA u UVLO Hysteresis V gt u T 50 0 50 100 150 50 0 50 TEMP C Figure 3 UVLO Hysteresis vs Temperature DS904A6 TEMP C T 100 150 Figure 4 VDD Zener Voltage vs Temperature CIRRUS LOGIC CS1600 E 14 Operating 1 6 q 14 Vpp 13V Source E C 1nF a 12 fsw 70 kHz E c 9 10 O 5 O 0 8 5 Vpp 13 V Q 0 6 source 100 mA S lui 200 mA n 0 4 0 2 Start up Standby 0 Standby H Start up 0 r R i r 50 0 50 100 150 60 40 20 0 20 40 60 80 100 120 140 TEMP C Gate Resistor Rop Ro Temp C Figure 5 Supply Current lag Ist Ipp vs Temperature Figu
5. 08 x 2 _ 4381uH 2 x 70 x 10 x 115 x 460 The RMS current rating for the inductor is estimated using an scaling factor used to account for variations in the input current shape across the AC line cycle over and above the nominally calculated value The nominal value before using the scaling factor is as follows Po l _ x P LB rms del x J2 xn Eq 7 IL B rms MEE eee x 1 35 108x J2 x 0 95 l B rms 1 07A B inductor scaling factor The peak inductor current lj gp may be estimated using the following equation 4xPg Eq 8 FRUI N X Vin min X 4 2 506 _ 4x 115 LB pk 0 95 x 108 x 2 800 3 17 A Inductor tolerances should be considered when estimating the peak currents present in the application The internal control algorithm of the controller dictates that the peak inductor current seen in the application could be as high as a pre defined threshold of 0 001984 times the inverse of the inductor which in this example amounts to 4 72 A Care needs to be taken to ensure that the saturation current rating of the PFC boost inductor factors in this threshold used for the protection schemes For a 40 V ripple and minimum line frequency of 45 Hz the 12 5 1 4 PFC MOSFET The peak voltage stress on the PFC MOSFET is a diode drop above the output voltage Accounting for leakage spikes for the 460 V output application a 600 V FET is recommended The FET should be able to handle th
6. 130 x 10 Rep 3 45MQ DS904A6 Eq 5 Rac Reg Rac 3 45MQ where Reg Feedback resistor used to reflect the PFC output voltage Rac Feedforward resistor used to reflect the rectified line voltage Viink PFC Output Voltage Vpp IC Supply Voltage lref Target reference current used for feedback 1 or lower tolerance resistors are recommended to maximize the tightly toleranced system behavior provided by the unique digital controller in the CS1600 Resistors may be separated into two or more series elements if voltage breakdown and or regulatory compliance is of concern 5 1 2 PFC Input Filter Capacitor For a typical 115 W PFC output stage required to power up a 108 W fluorescent ballast an input filter capacitance of 0 33 uF is recommended Capacitor tolerances and the value of the EMI filter capacitor need to be considered when selecting the value of the capacitor to be used in this application 11 CIRRUS LOGIC CS1600 5 1 3 PFC Boost Inductor Equation 3 can be rewritten to calculate the PFC boost Inductor Lp as follows V Vise ae x 90V x 4B V nk 90V 400V x x Eq 6 400V Vin min Viink Vintmin X 42 Vink _ Mink 90V 1 Viin 39g X 90V x 42 E sank x OY X _ 0 937 in min Viink Vin min X V2 Vink Vintmin X V2 V 2 link in min Ea 6 Lg axnX Vintmin X 2 x fmax X Po x Vink Eq 6 Lg 0 937 x 0 95x 108 x 480 1
7. ING PLANE L l MILLIMETERS DIM MIN MAX A 1 35 1 75 A1 0 10 0 25 B 0 33 0 51 C 0 19 0 25 D 4 80 5 00 E 3 80 4 00 e 1 02 1 52 H 5 80 6 20 L 0 40 1 27 oc 0 8 JEDEC MS 012 16 DS904A6 CIRRUS LOGIC 7 ORDERING INFORMATION CS1600 Part Temperature Range Package Description CS1600 FSZ 40 C to 125 C 8 lead SOIC Lead Pb Free 8 ENVIRONMENTAL MANUFACTURING amp HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating Max Floor Life CS1600 FSZ 260 C 2 365 Days a MSL Moisture Sensitivity Level as specified by IPC JEDEC J STD 020 b Stored at 30 C 60 relative humidity DS904A6 17 CS1600 CIRRUS LOGIC 9 REVISION HISTORY Revision Date Changes A1 OCT 2009 Initial Advance Information release A2 MAR 2010 Revised feature list product description and parametric table to reflect the CO version of silicon A3 MAR 2010 Revised to reflect the update in switching frequency and variation of frequency over line A4 APR 2010 Revised parametric table and equations to reflect the C1 version of silicon A5 MAY 2010 Updated with additional test bench data for EP level A6 JUN 2010 Added R 3 ang ROJc in electrical specifications section Contacting Cirrus Logic Support For all product questions and inquiries contact a
8. Vj is 9096 of its nominal value the device operates in the start up mode It continues operating in this mode till the nominal Vj voltage is reached The start up algorithm provides an ON time which is varied in proportion to the sensed rectified voltage while changing the switching frequency to provide maximum power During this start up phase of operation the switching frequency could be significantly lower than the normal operating frequency and the input current waveform is forced into following a trapezoidal envelope in phase with the line voltage to maximize energy transfer The ON time and the switching frequency of the IC ensure that peak currents are kept controlled to prevent saturation of the boost inductor during this period Normal mode Once Vj reaches its nominal value the chip operates in the normal mode Here the frequency follows the profile shown in Figure 7 and the ON time is varied to achieve PFC Any drop in Vink to below its undervoltage threshold as defined in Section 2 2 Electrical Characteristics re triggers the start up mode of operation A simplified illustration of operation in these two modes is shown below in Figure 11 Normal Mode Startup Mode Startup Mode t ms Figure 11 Start up and Normal Modes DS904A6 i CIRRUS LOGIC CS1600 4 1 2 Burst Mode In addition to the start up mode and normal mode of operation the controller enters the burst mode of op
9. Vpp 13V t 32 45 ns DS904A6 3 i CIRRUS LOGIC CS1600 Parameter Condition Symbol Min Typ Max Unit Fall Time C 1 nF Vpp 13V t 15 25 ns Output Voltage Low IGD 200 mA VDD 13 V VOL 0 9 1 3 V Output Voltage High IGD 100 mA VDD 13 V VoH 11 3 11 8 V Feedback and Protection Reference Current let 127 130 133 uA Overvoltage Protection Threshold loyp lref 105 107 110 Overvoltage Protection Current Hysteresis lovP Hy z 4 Undervoltage Protection Threshold luvellret 83 85 87 Undervoltage Protection Current Hysteresis luvP Hy 10 96 Overpower Protection Threshold 34 123 125 127 of full load as defined by Eq 3 Overpower Protection Recovery 35 49 60 Input Brownout Protection Threshold Vout 460V GDRV turns off VBP th 82 86 90 Vrms Input Brownout Recovery Threshold Vout 460V GDRYV turns on VBR 94 97 100 Vrms Thermal Protection Thermal Shutdown Threshold Tsp 130 143 155 oC Thermal Shutdown Hysteresis Tsp Hy 9 oC STBY Input Logic Threshold 5 Low 0 8 High Vpp 0 8 E 2 3 Thermal Characteristics Symbol Parameter Value Unit R 4 Thermal Resistance Junction to Ambient 159 C W R c Thermal Resistance Junction to Case 39 C IW Specifications guaranteed by NOU W R design amp characterization Specifications measured as an instantaneous quantity NOT
10. e same peak current as that seen through the inductor This would amount to 3 96 A The scaling factor to determine the RMS current through the MOSFET for a 108 V input is about 1 15 and the minimum RMS current rating lFET rms required for the FET is calculated as follows Po SK Eq 9 FET rms Vincmin X 2 xn Y li B rms ta x 1 15 108 x 2 x 0 95 l_B rms 0 91A where y FET scaling factor 5 1 5 PFC Diode The PFC diode peak current is equal to the inductor peak current Eq 10 10010 LB pk 3 17 A D pk The PFC diode average current is calculated as follows P O p avg V ink Eq 11 215 D avg 460 In avg 0 25A 5 1 6 PFC Output Capacitor The output capacitor needs to be designed to meet the voltage ripple and hold up time requirements In the case of a cost sensitive ballast application the hold up requirement is not a key requirement To address the output ripple requirements the following equation may be used as a guide Po l Eq 12 out 27 X fline min X Viink X AV link rip where Cout Output Capacitance value Po Output Power fiime min Minimum Line Frequency Viink PFC Output Voltage AV ink Peak Peak Voltage Ripple on the PFC Output DS904A6 H CS1600 CIRRUS LOGIC output capacitance needed is calculated as The voltage rating on the capacitor needs to account for the operation of the device before it hits the overvoltage p
11. eration when the estimated output power Po is lt 5 of its nominal value During this stage the PFC driver is disabled intermittently over a full line cycle period as shown in Figure 12 The period of time for which the PFC drive is disabled depends on the level of loading present Burst Mode Active t ms Vin PFC M Disable t ms Figure 12 Burst Mode of Operation 4 2 Input Feedforward and Output Regulation The CS1600 continuously monitors the rectified AC line and the PFC output voltage through sense resistors tied to the IAC and the FB pins to monitor the voltages scaled as currents The rectified AC line sense resistor Rac needs to be the same size of the resistor Reg used for current feedback from the PFC output voltage These currents are effectively compared against an internal reference current to provide adaptive PFC control The resistor values are calculated as follows Viink Vpp Reg TT Eq 1 ref Rac Res Eq 2 where Rep Feedback resistor used to sense the PFC output voltage Rac Feedforward resistor used to sense the rectified line voltage Viink PFC Output Voltage Vpp IC Supply Voltage DS904A6 lef Target Reference current used for feedback Viink Figure 13 Output Feedback Viink Figure 14 Input Feedforward 4 3 Protection Features 4 3 1 Overvoltage Protection If the PFC output voltage Via exceeds the overvoltage threshold as scaled by the curre
12. f brownout for a period of 56 ms disables the gate drive The device continues to monitor the input voltage while in this condition The CS1600 exits the brownout mode when the input current scales up to and stays above 56 496 of its nominal value for a period of 56 ms To minimize false detects the brownout detection circuit increases the brownout detection time by a factor of 1 6 mS V for every volt differential between the minimum operating voltage and the brownout threshold following half of a line cycle of exceeding the brownout threshold The following diagram illustrates the brownout sequence whereby the CS1600 enters standby and upon recovery from brownout enters normal operation T Brownout 56 ms Brownout 56 ms Thresholds Upper Lower Timer b Enter Standby Exit Standby Start Timer Figure 15 Brownout 4 3 6 Over temperature Protection Over temperature protection is activated and PFC switching is disabled when the die temperature of the device exceeds 125 C There is a hysteresis of about 30 C before resumption of normal operation 4 4 Standby STBY Function The standby STBY pin may be used as a means to force the CS1600 into a non operating low power state The STBY input should be driven by an open collector open drain device Internal to the pin there is a pull up resistor connected to the VDD pin as shown in Figure 16 A filter capacitance of about 1000 pF is recommended w
13. hile this pin is being used CAP CS1600 Figure 16 STBY Pin Connection DS904A6 CIRRUS LOGIC CS1600 5 FLUORESCENT BALLAST APPLICATION EXAMPLE The following section gives an example for a front end PFC stage design for an electronic ballast application The equations that follow may be used as guidelines for any other requirements using the CS1600 D5 L1 D6 e FYYYX e e e O R R R1a R2a ABR1 ABRI CS1600 R2b O hd z 2 C3a Ciink m S NC STBYQ O R2c gt 4 Mains U E 12V R3 lt Q1 e 6 RBS GDO ABR1 ABR1 5 a e e O Figure 17 CS1600 Basic Application Circuit 5 1 Component Selection Guidelines The following design example is for a wide input voltage fluorescent ballast application using 2 T5 lamps in series for a total nominal power of 108W The target specifications for the PFC portion of the design assuming a 9496 efficient second stage are as follows Vin min 108 VAC Vin max 305 VAC V link 460 V Po 115 W n 95 5 1 1 The rectified line voltage Vac and the output voltage of the PFC boost converter Viink are scaled as currents by using sense resistors whose values are estimated based on the equations below Inc and lrp Sense Resistors Vink Vad Rep Eq 4 ref 460 12 Reg NOME
14. internal digital control engine self compensates the feedback error signal using an adaptive control algorithm Protection Features The CS1600 provides various protection features such as undervoltage overcurrent overpower open and short circuit protection and brownout It also provides the user with the option of using the STBY pin to disable switching of the device CIRRUS LOGIC 4 1 PFC Implementation The PFC switching frequency profile over the line period has been discussed in detail in Section 4 In addition the digital control algorithm tracks changes the AC input and operates in different frequency bands at different line voltages as illustrated in Figure 8 and Figure 9 below fsw kHz 100 Burst Mode Max fsw Min fsw 5 50 100 PS W Figure 8 Switching Frequency vs Output Power Vin lt 165 VAC fsw kHz 60 Burst Mode Max f 48 a 24 Min fsw gt 5 50 100 Po W Figure 9 Switching Frequency vs Output Power Vin gt 165 VAC The CS1600 primarily operates in the DCM mode with a properly sized inductor However it will move into a quasi CS1600 CRM mode near the peaks of the input line in order to enable maximum power delivery as illustrated in Figure 10 below Figure 10 DCM and quasi CRM Operation with CS1600 4 1 1 Start up Mode vs Normal Mode CS1600 operates in two discrete states Start up mode When the output voltage of the PFC stage
15. ion with the signal on the IAC pin is used in the FB 4 IN Power Factor Correction PFC algorithm A filter capacitor of up to 2 2 nF may be added between this pin and VDD to provide noise immunity GND 5 Ground GND is a common reference for all the functional blocks in this device Gate Drive GD is the output of the device with a source capability of 0 5 A and a SP B SEE current sink capacity of 1 A IC Supply Voltage Vpp is the input used to provide bias to the device This pin VDD 7 IN has an internal shunt to ground An external bias needs to be applied for steady state operation A low ESR ceramic decoupling capacitor at this pin is recommended for reliable operation of this device 2 DS904A6 i CIRRUS LOGIC CS1600 2 CHARACTERISTICS AND SPECIFICATIONS 2 1 Absolute Maximum Ratings Pin Symbol Parameter Value Unit 7 Vpp IC Supply Voltage Vz V 2 3 4 Vin Input Voltage 0 5 to Vpp V 3 4 lin Input Current 50 mA 6 VGD Gate Drive Voltage 0 3 to Vpp V 6 lop Gate Drive Current 1 0 0 5 A 1 2 3 4 5 6 8 ESD Human Body Model 2000 V 1 2 3 4 5 6 8 ESD Machine Model 200 V 1 2 3 4 5 6 8 ESD Charged Device Model 500 V i Pp Total Power Dissipation at 50 C 600 mW Tj Junction Temperature Operating Range 40 to 125 C Tstg Storage Temperature Range 65 to 150 C Notes 1 The CS1600 has an internal shunt regulator tha
16. nt monitored by the sense resistors the CS1600 provides protection by disabling the gate drive A nominal hysteresis is provided to allow the system to recover from the fault condition before switching is resumed 4 3 2 Overcurrent Protection The CS1600 s digital controller algorithm limits the ON time of the Power MOSFET by the following equation lt 0 001126 Ton V rect Where To is the max time that the power MOSFET is turned on and Vie is the rectified line voltage In the event of a sudden line surge or sporadic high dv dt line voltages this equation may not limit the ON time appro priately For this type of line disturbance additional pro tection mechanisms such as fusible resistors fast blow fuses or other current limiting devices are recommend ed CIRRUS LOGIC CS1600 4 3 3 Overpower Protection The nominal output power is estimated internally by the CS1600 from the following equation P Vio ye 0 xn X Vinimin X 2 X fmax Lex Vick Eq 3 where Po rated output power of the system n efficiency of the boost converter estimated as 100 by the internal PFC algorithm Vin min minimum RMS line voltage for operation Viink PFC output voltage fmax Maximum switching frequency Lg boost inductor used in the application V link Vink Ta jaa 42 Viink Vin min X 2 i SAB A 400V V in min Operation estimated to be at power levels higher
17. on with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROP ERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRIT ICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK AND CIR RUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER IF THE CUSTOMER OR CUSTOM ER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS CUSTOMER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY INCLUDING AT TORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks or se
18. re 6 Gate Resistance Roy Roi vs Temperature 6 DS904A6 T uA ia CIRRUS LOGIC CS1600 4 INTRODUCTION CS1600 is a digitally controlled Power Factor Correction PFC controller that operates in the Variable Frequency Discontinuous Conduction Mode VF DCM The CS1600 uses a proprietary digital algorithm to optimize control of the power switch to deliver highly efficient performance for electronic ballast applications With this control scheme the total number of external components needed is minimized in comparison to conventional control techniques thus reducing the overall system cost Digital control is achieved by constantly monitoring two voltages the PFC output voltage Vj at pin FB and the rectified AC line voltage Vrect at pin IAC This is done by measuring the currents that flow into the respective pins These currents are then fed to the inputs of two analog to digital converters ADCs and are compared against an internal target current lef The digital outputs of the two ADCs are then processed in a control algorithm which determines the behavior of the CS1600 during start up normal operation and under fault conditions such as brownout overvoltage overcurrent overpower and over temperature Details of operation during these conditions are discussed in later sections of this document Some of the key features of the CS1600 are as follows Discontinuous Conduction Mode wi
19. rotection Cas 22 115 threshold This is typically 105 of nominal value which is 2m x 45 x 460 x 40 483 V With the ripple voltage factored in 22uF of capacitance rated at 500 V would suffice for this application DS904A6 13 CIRRUS LOGIC CS1600 5 2 Bill of Materials for Application Example shown in Figure 17 Designator Value Description Part Number Ria 1 5 MQ R1b 1 5 MQ R1c 1 5 MQ R2a 1 5 MQ R2b 1 5 MQ R2c 1 5 MQ R3 24 9Q C1 0 47uF C2 4 7uF C3a 23 5UF 2 47uF 250V caps in series C3b BR1 4A 600V Bridge diode GBU4J BP D5 1 A 600 1N4005 D6 3A 600V MURS360 L1 360uH max TBD Premier Magnetics Q1 9A 600V FCP9N60N CS1600 CS1600 FSZ 14 DS904A6 E CS1600 CIRRUS LOGIC 5 3 Summary of Equations Eq Equation 1 4 Vink Vpp Rep gt ref Sk Rac Rep 2 _ Viink Vinmin X 4 2 3 6 Po AXNX Vinmin X O in min 2 X fmax Lax Visa P 7 o X LB rms Wini ewer B B 4xPo ia N X Vin min X 42 9 TEN ENT FET rms Vinoniny TE 10 bons D pk LB pk 11 Po Davo Vink 12 RC RN out 2m X fline min X Viink X AViink rip 15 DS904A6 CS1600 CIRRUS LOGIC 6 PACKAGE DRAWING 8L SOIC 150 MIL BODY PACKAGE DRAWING 4 SEAT
20. rvice marks of their respective owners 18 DS904A6
21. t controls the nominal operating voltage on the VDD pin 2 Long term operation at the maximum junction temperature will result in reduced product life Derate internal power dissipation at the rate of 50 mW C for variation over temperature 2 2 Electrical Characteristics Recommended operating conditions unless otherwise specified T4 T 40 to 125 C Vpp 10 to 15 V GND 0 V Typical values are at T 25 C Parameter Condition Symbol Min Typ Max Unit Vpp Supply Voltage Vpp Turn on Threshold Voltage Vpp increasing Vth st 8 4 8 8 9 3 V Vpp Turn off Threshold Voltage Vpp decreasing Vih stp 7 1 7 4 7 9 V UVLO Hysteresis VHys 1 3 V Zener Voltage lbp 20 mA Vz 17 0 17 9 18 5 V Supply Current Section Start up Supply Current Vpp lt Vincst Ist 68 80 uA Standby Supply Current STBY lt 0 8V Isp 80 112 uA Operating Supply Current C 1nF fg 70 kHz Inp 1 7 1 9 mA PFC Gate Drive Section Maximum Operating Frequency Normal mode Vpp 13 V fsw max 62 66 70 kHz Minimum Operating Frequency Normal mode Vpp 13 V fsw min 20 22 23 kHz Minimum Duty Cycle Vpp 13 V STBY lt 0 8 V DC min 0 Maximum Duty Cycle Vpp 13 V Dus 64 66 68 Minimum On Time Vpp 13V ton_min 0 45 0 5 0 55 us Output Source Resistance lgp 100 mA Vpp 13 V Rou 9 Q Output Sink Resistance lap 200 mA Vpp 13 V Roi 6 Q Rise Time C 1 nF
22. th Continuously Variable Switching Frequency The PFC switching frequency is varied every switching cycle This allows for a spread spectrum which minimizes the conducted EMI peaks at any given frequency thereby minimizing the size and cost of the EMI filter required at the front end During start up the control algorithm limits the maximum ON time and adjusts the frequency to avoid inductor sat uration and provides a near trapezoidal envelope for the input current during every half cycle During normal oper ation as the line voltage changes over half of a line cycle DS904A6 the frequency varies approximately 2 1 as shown in Figure 7 below Switching Frequency of Max Line Voltage of Max of Max 0 45 90 135 180 Rectified Line Voltage Phase Deg Figure 7 Switching Frequency vs Phase Angle Maximum power transfer occurs at the peak of the AC line voltage at which time the frequency reaches its maxi mum value Switching losses are minimized during peri ods of low power transfer by switching at lower frequencies near the zero crossing of the AC line This switching frequency profile helps reduce total BOM cost through savings in the size of the boost inductor and the EMI filter components while at the same time im proving overall system efficiency Integrated Feedback Control No external feedback compensation components are re quired for the CS1600 The
23. than that calculated by Eq 3 above is tracked by the IC as an overpower condition During this phase the PFC output voltage Vj is reduced and will continue to decrease as the power draw increases When Vj reaches its undervoltage threshold it goes into the start up mode as explained in section 4 1 1 At this point the overpower protection timer is activated If this condition continues to exist for 112 ms the gate drive is disabled for a period of about 3 seconds This hiccup mode of operation continues until the fault is removed If a value of the boost inductor other than that obtained from Eq 3 above is used the total output power capability as well as the thresholds for the different operating conditions will scale accordingly 4 3 4 Open short circuit protection The CS1600 protects the system in case the feedforward resistor tied to the IAC pin or the feedback resistor tied to the FB pin is open or shorted to ground A fault seen on the resistor going into the FB pin would imply no current being fed into the pin which would trigger the Vj undervoltage algorithm as described in Section 4 3 1 A fault detected on the IAC pin would trigger the brownout condition discussed in Section 4 3 5 below 4 3 5 Brownout Protection Brownout occurs when the current representing the rectified input voltage nominally 10096 of the reference current used 10 for the output voltage drops to 4996 of its nominal value Detection o

CIRRUS LOGIC CS1600 Manual

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