GSI TECHNOLOGY GS842Z18/36AB-180/166/150/100 Manual
Contents
1. a LLL Rev 1 03a 10 2006 16 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 AC Electrical Characteristics Parameter Symbol i i e 2 Unit Min Max Min Max Min Max Min Max Clock Cycle Time tKC 9 1 10 0 12 0 15 0 ns Flow Clock to Output Valid tKQ 8 0 8 5 10 0 12 0 ns Through Clock to Output Invalid tKQX 3 0 3 0 3 0 3 0 ns Clock to Output in Low Z DEA 3 0 3 0 3 0 3 0 ns Clock HIGH Time tKH 1 3 1 3 1 3 1 3 ns Clock LOW Time tKL 1 5 1 5 1 5 1 5 ns Clock to Output in High Z tHz 1 5 3 2 1 5 3 5 1 5 3 8 1 5 5 ns G to Output Valid Op 3 2 35 38 5 ns G to output in Low Z tOLZ 0 0 0 0 ns G to output in High Z tOHZ 3 2 3 5 3 8 5 ns Setup time tS 1 5 1 5 1 5 2 0 ns Hold time tH 0 5 0 5 0 5 0 5 ns ZZ setup time tzzs 5 5 5 5 ns ZZ hold time tZZH2 1 1 1 1 ns ZZ recovery tZZR 20 20 20 20 ns Notes 1 These parameters are sampled and are not 100 tested 2 ZZ is an asynchronous signal However In order to be recognized on any given clock cycle ZZ must meet the specified setup2. Parameter Symbol Min Typ Max Unit Notes 3 3 V Supply Voltage Vpp3 3 0 3 3 3 6 V 2 5 V Supply Voltage VDp2 2 3 25 2 7 V 3 3 V Vppq UO Supply Voltage Vppa3 3 0 3 3 3 6 V 2 5 V Vppq UO Supply Voltage Vppaz 23 25 27 V Notes 1 The part numbers of Industrial Temperature Range versions end the character I Unless otherwise noted all performance specifica tions quoted are evaluated for worst case in the temperature range marked on the device 2 Input Under overshoot voltage must be 2 V gt Vi lt Vpp 2 V not to exceed 4 6 V maximum with a pulse width not to exceed 20 tKC Te Rev 1 03a 10 2006 12 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com GS842Z18 36AB 180 166 150 100 Mrcanowe Vppa3 Range Logic Levels Parameter Symbol Min Typ Max Unit Notes Vpp Input High Voltage Vin 2 0 Vpp 0 3 V 1 Voe Input Low Voltage VIL 0 3 0 8 V 1 Vppq I O Input High Voltage Vina 2 0 Vppa 0 3 V 1 3 Vopo UO Input Low Voltage Vita 0 3 0 8 V 1 3 Notes 1 The part numbers of Industrial Temperature Range versions end the character I Unless otherwise noted all performance specifica tions quoted are evaluated for worst case in the temperature range marked on the device 2 Input Under overshoot voltage must be 2 V gt Vi lt Vpp 2 V not to exceed 4 6
3. 1 Input Under overshoot voltage must be 2 V lt Vi lt Vpp 2 V not to exceed 4 6 V maximum with a pulse width not to exceed 20 tTKC d Vi Vin Von 3 OV lt VN lt VIn 4 Output Disable Vouyr 0 to Vppn 5 The TDO output driver is served by the Vppq supply 6 lon 4mA 7 low 4mA 8 lohse 100 uA 9 Jor 100 uA JTAG Port AC Test Conditions Parameter Conditions JTAG Port AC Test Load Input high level Vpop 0 2 V DQ Input low level 0 2 V NW J Input slew rate 1 Vins ln 50 at Input reference level Vppd 2 Kn Vppg2 Ge Vona Distributed Test Jig Capacitance Notes 1 Include scope and jig capacitance 2 Test conditions as shown unless otherwise noted Rev 1 03a 10 2006 25 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra NOLOGY GS842218 36AB 180 166 150 100 JTAG Port Timing Diagram Keele tTKH gt tTKL gt TCK gt tTH tTS TDI TH i TMS jetTka TDO C o O LH tTH gt tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 ns TCK Low to TDO Valid tTKQ 20 ns TCK High Pulse Width tTKH 20 ns TCK Low Pulse Width tTKL 20 ns TDI amp TMS Set Up Time tTS 10 ns TDI amp TMS Hold Time tTH 10 ns m
4. For latest documentation see http www gsitechnology com 29 31 2001 GSI Technology Jol mmm Ordering Information GSI NBT Synchronous SRAMs GS842218 36AB 180 166 150 100 Speed Org Part Number Type Package MH zins Ta Status 128K x36 GS842Z36AGB 150 NBT Pipeline Flow Through RoHS compliant BGA var 1 150 10 C MP 128K x36 GS842Z36AGB 100 NBT Pipeline Flow Through RoHS compliant BGA var 1 100 12 C MP 256K x18 GS842Z18AGB 1801 NBT Pipeline Flow Through RoHS compliant BGA var 1 180 8 MP 256K x 18 GS842Z18AGB 166l NBT Pipeline Flow Through RoHS compliant BGA var 1 166 8 5 MP 256K x 18 GS842Z18AGB 1501 NBT Pipeline Flow Through RoHS compliant BGA var 1 150 10 MP 256K x 18 GS842Z18AGB 1001 NBT Pipeline Flow Through RoHS compliant BGA var 1 100 12 MP 128K x36 GS842Z36AGB 1801 NBT Pipeline Flow Through RoHS compliant BGA var 1 180 8 MP 128K x36 GS842Z36AGB 166l NBT Pipeline Flow Through RoHS compliant BGA var 1 166 8 5 MP 128K x 36 GS842Z36AGB 1501 NBT Pipeline Flow Through RoHS compliant BGA var 1 150 10 MP 128K x36 GS842Z36AGB 1001 NBT Pipeline Flow Through RoHS compliant BGA var 1 100 12 MP Notes 1 Customers requiring delivery in Tape and Reel should add the character T to the end of the part number Example GS842Z36AB 100IT 2 The speed column indicates the cycle frequency MHz of the device in
5. point to point applications See the Output Driver Characteristics chart for details Mode Pin Functions Mode Name Pin Name State Function D L Linear Burst Burst Order Control LBO H Interleaved Burst L Flow Through Output Register Control FT H or NC Pipeline e Bebe z Lor NC Active ower Down Contro 7 Standby Le lop L Dual Cycle Deselect Single Dual Cycle Deselect Control SCD H or NC Single Cycle Deselect L High Drive Low Impedance FLXDrive Output Impedance Control ZQ H or NC Low Drive High Impedance Lor NC Activate DQPx I Os x18 x3672 mode 9th Bit Enable PE H Deactivate DQPx I Os x16 x3272 mode Note There isa are pull up devices on the ZQ SCD and FT pins and a pull down device on the ZZ pin so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables Rev 1 03a 10 2006 10 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A 1 0 A 1 0 A 1 0 A 1 0 A 1 0 A 1 0 A 1 0 A 1 0 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3
6. 2 1 0 Control Signals TMS TCK Test Access Port TAP Controller Identification ID Register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in Capture DR state with the IDCODE command loaded in the Instruction Register The code is loaded from a 32 bit on chip ROM It describes various attributes of the RAM as indicated below The register is then placed between the TDI and TDO pins when the controller is moved into Shift DR state Bit 0 in the register is the LSB and the first to reach TDO when shifting begins REN Rev 1 03a 10 2006 21 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY G 842218 36AB 180 166 150 100 Tap Controller Instruction Set ID Register Contents S 2 Die un GSI Technology ZS Revision Not Used Confiauration JEDEC Vendor g Code g ID Code S g Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131 12 11 10 9 8 716 5 4 3 211 0 x72 X X X IX O0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x36 X X XIX O O0 O0 XI 17070717070 0 0 1 0 0 0 0 010 1 1 0 1 1 0 0 1 1 x32 X X X X O0 0 0 0 0 0 0 0 0 0 0 0 111 0 0 0 010 1 1 0 1 1 0 0 1
7. Gs L Run Test Idle yO SelectDR Select IR A 0 Y H Capture DR mee Capture IR 0 gf 0 Yy y Shit Cp J e a 0 1 l 1 Y LU Exit DR Exit1 IR 0 0 Yy y PauseDR dei Pause IR 1 0 1 y Yy Update DR Update IR 1 0 1 0 AA Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO This occurs when the TAP controller is moved to the Shift DR state This allows the board level scan path to be shortened to facili tate testing of other devices in the scan path SAMPLE PRELOAD SAMPLE PRELOAD is a Standard 1149 1 mandatory public instruction When the SAMPLE PRELOAD instruction is loaded in the Instruction Register moving the TAP controller into the Capture DR state loads the data in the RAMs input and T O buffers into the Boundary Scan Register Boundary Scan Register locations are not associated with an input or I O pin and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet Because the RAM clock is independent from the TAP Clock TCK it is possible for the TAP to attempt to capture the I O ring contents while the input buffers are in transition i e in a metastable state Although allowing the TAP to sample metastable inputs will not harm the device repeatable results cannot be expected RAM input signals must
8. Pipeline mode and the latency ns in Flow Through mode Each device is Pipeline Flow Through mode selectable by the user 3 Ta C Commercial Temperature Range T Industrial Temperature Range 4 MP Mass Production 5 GSI offers other versions this type of device in many different configurations and with a variety of different features only some of which are covered in this data sheet See the GSI Technology web site www gsitechnology com for a complete listing of current offerings 2001 GSI Technology NN Rev 1 03a 10 2006 30 31 Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Jol mmm G 842218 36AB 180 166 150 100 4Mb Synchronous NBT Datasheet Revision History Old T f Chan SS DS DateRev Code Old ypes of Changes Page Revisions Reason New Format or Content 842Z18A_r1 e Creation of new datasheet e Updated power numbers in table on page 1 and Operating Currents table e Updated pinout for x18 e Content e Updated Pin Description table 842Z18A_r1_01 SE e Removed ByteSafe references e Changed DP and QE to NC e Delete PE from entire document changed to NC 842Z18A r1 01 e Removed 200 MHz speed bin 842Z18A r1 02 Content Removed pin locations from pin description table e Updated format 842Z18A_r1_02 Format Content e Updated timing diagrams 842Z18A_r1_03 e Added variation information to package mechanical e Re
9. and hold times as specified above Rev 1 03a 10 2006 17 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 Pipeline Mode Timing Write A Read B Suspend Read C Write D writeno op Read E Deselect tKH tKC tKL CK bk GS A Cp D 0 a gt ts CKE ADV DQ mm Rev 1 03a 10 2006 18 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS842218 36AB 180 166 150 100 Flow Through Mode Timing Write A Write B Write B 1 Read C Cont Read D Write E Read F Write G tKL tKH tKC CK z 4E oe P a P H A DS o x lt A0 An LB gt gt tS DQ DA _D B D B 1 KC Q D G Ol Note E High False if E1 1 or E2 0 or E3 1 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149 1 1990 a serial boundary scan interface standard commonly referred to as JTAG The JTAG Port input interface levels scale with Vpp The JTAG output drivers are powered by Vppo Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port The port is reset at power up and will remain inactive unless clocked TCK TDI and TMS
10. are designed with internal pull up circuits To assure normal operation of the RAM with the JTAG Port unused TCK TDI and TMS may be left floating or tied to either Vpp or Vss TDO should be left unconnected E Rev 1 03a 10 2006 19 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 JTAG Port Registers JTAG Pin Descriptions Pin Pin Name UO Description TCK Test Clock ii Clocks all TAP events All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK The TMS input is sampled on the rising edge of TCK This is the command input for the TAP TMS Test Mode Select In controller state machine An undriven TMS input will produce the same result as a logic one input level The TDI input is sampled on the rising edge of TCK This is the input side of the serial registers placed between TDI and TDO The register placed between TDI and TDO is determined by the TDI Test Data In In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register refer to the TAP Controller State Diagram An undriven TDI pin will produce the same result as a logic one input level Output that is active depending on the state of the TAP state machine Output changes in response to the falling edge of TCK This is the out
11. be stabilized for long enough to meet the TAPs input data capture set up plus hold time tTS plus tTH The RAMs clock inputs need not be paused for any other TAP operation except capturing the I O ring contents into the Boundary Scan Register Moving the controller to Shift DR state then places the boundary scan register between the TDI and TDO pins EXTEST EXTEST is an IEEE 1149 1 mandatory public instruction It is to be executed whenever the instruction register is loaded with all logic 0s The EXTEST command does not block or override the RAM s input pins therefore the RAM s internal state is still determined by its input pins a Rev 1 03a 10 2006 23 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS842218 36AB 180 166 150 100 Typically the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE PRELOAD command Then the EXTEST command is used to output the Boundary Scan Register s contents in parallel on the RAM s data output drivers on the falling edge of TCK when the controller is in the Update IR state Alternately the Boundary Scan Register may be loaded in parallel using the EXTEST command When the EXTEST instruc tion is selected the sate of all the RAM s input and I O pins as well as the default values at Scan Register locations not asso ciated with a pin are transferred in paral
12. 1 x18 X X XIX O O0 O0 XI 1707071707070 0 110 1 0 0 0 10 1 1 0 1 1 0 0 1 1 x16 X X XIX O 0 0 07 0 0 0 0 0 0 0 0 14 1 1 0 0 0 10 1 1 0 1 1 0 0 1 1 Overview There are two classes of instructions defined in the Standard 1149 1 1990 the standard Public instructions and device specific Private instructions Some Public instructions are mandatory for 1149 1 compliance Optional Public instructions must be implemented in prescribed ways The TAP on this device may be used to monitor all input and I O pads and can be used to load address data or control signals into the RAM or to preload the I O buffers When the TAP controller is placed in Capture IR state the two least significant bits of the instruction register are loaded with 01 When the controller is moved to the Shift IR state the Instruction Register is placed between TDI and TDO In this state the desired instruction is serially loaded through the TDI input while the previous contents are shifted out at TDO For all instructions the TAP executes newly loaded instructions only when the controller is moved to Update IR state The TAP instruction set for this device is listed in the following table Rev 1 03a 10 2006 22 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 JTAG Tap Controller State Diagram Z Test Logic Reset La 0
13. Begin Burst R External L H L L H X L Hy L HY L High Z 2 Dummy Read Continue Burst B Next L H L H XIXIXIXIXJIHI L High Z 1 2 10 Write Cycle Begin Burst W External L H L L L bL bL H L YX L D 3 Write Cycle Continue Burst B Next L H L H XILIXIXI XIXIL D 1 3 10 Write Abort Continue Burst B Next L H L H X H X X X X L High Z 1 2 3 10 Deselect Cycle Power Down D None LH L L X X H X X X L High Z Deselect Cycle Power Down D None LH L L X X X X AH X L High Z Deselect Cycle Power Down D None LH L L X X X bL X X L High Z Deselect Cycle D None LH L L L H L H 4 Lb X L High Z 1 Deselect Cycle Continue D None LH L H X X X X X X L High Z 1 Sleep Mode None X X X X X X X XIX H High Z Clock Edge Ignore Stall Current Hr H X XIXIX I XIXIXIL 4 Notes 1 Continue Burst cycles whether read or write use the same control inputs A Deselect continue cycle can only be entered into if a Dese lect cycle is executed first E 2 Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed 3 G can be wired low to minimize the number of control signals provided to the SRAM Output drivers will automatically turn off during write cycles A If CKE High occurs during a pipelined read cycle the DQ bus will re
14. Captures I O ring contents Places the Boundary Scan Register between TDI and 1 PRELOAD TDO GSI 101 GSI private instruction 1 RFU 110 Do not use this instruction Reserved for Future Use I Replicates BYPASS instruction Places Bypass Register between TDI and TDO BYPASS 111 Places Bypass Register between TDI and TDO 1 Notes 1 Instruction codes expressed in binary MSB on left LSB on right 2 Default instruction automatically loaded at power up and in test logic reset state Rev 1 03a 10 2006 24 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS842218 36AB 180 166 150 100 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min Max Unit Notes 3 3 V Test Port Input High Voltage Vun 2 0 Vpp3 0 3 V 1 3 3 V Test Port Input Low Voltage Vum 0 3 0 8 V 1 2 5 V Test Port Input High Voltage Vun 0 6 VDp2 Vopp2 0 3 V 1 2 5 V Test Port Input Low Voltage Vun 0 3 0 3 VDp2 V 1 TMS TCK and TDI Input Leakage Current Iw 300 1 uA 2 TMS TCK and TDI Input Leakage Current Iw 1 100 uA 3 TDO Output Leakage Current low 1 1 uA 4 Test Port Output High Voltage Mou k V 5 6 Test Port Output Low Voltage Voy 0 4 V 5 7 Test Port Output CMOS High VoHJC Vppq 100 mV V 5 8 Test Port Output CMOS Low Voie 100 mV V 5 9 Notes
15. Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Bump RS Not all vendors offer this option however most mark Bump R5 as Vpp or Vppq on pipelined parts and Vgg on flow through parts GSI NBT SRAMs are fully compatible with these sockets Rev 1 03a 10 2006 11 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 Absolute Maximum Ratings All voltages reference to Vgs Symbol Description Value Unit Von Voltage on Vpp Pins 0 5 to 4 6 V VDpa Voltage in Vppg Pins 0 5 to 4 6 V Vio Voltage on I O Pins 0 5 to Vppg 0 5 lt 4 6 V max y Vu Voltage on Other Input Pins 0 5 to Vpp 0 5 lt 4 6 V max y lin Input Current on Any Pin 20 mA Jour Output Current on Any I O Pin 20 mA Pp Package Power Dissipation 1 5 W Tore Storage Temperature 55 to 125 DC Tous Temperature Under Bias 55 to 125 DC Note Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded Operation should be restricted to Recommended Operating Conditions Exposure to conditions exceeding the Absolute Maximum Ratings for an extended period of time may affect reliability of this component Power Supply Voltage Ranges
16. Low Low Impedance High Drive High High Impedance Low Drive NC No Connect TMS Scan Test Mode Select TDI Scan Test Data In TDO O Scan Test Data Out TCK Scan Test Clock Von Core power supply Vss I O and Core Ground Vppa Output driver power supply CK Clock Input Signal active high nnn EN Rev 1 03a 10 2006 4 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 Functional Details Clocking Deassertion of the Clock Enable CKE input blocks the Clock input from reaching the RAM s internal circuits It may be used to suspend RAM operations Failure to observe Clock Enable set up or hold requirements will result in erratic operation Pipelined Mode Read and Write Operations All inputs with the exception of Output Enable Linear Burst Order and Sleep are synchronized to rising clock edges Single cycle read and write operations must be initiated with the Advance Load pin ADV held low in order to load the new address Device activation is accomplished by asserting all three of the Chip Enable inputs E1 E2 and E3 Deassertion of any one of the Enable inputs will deactivate the device Function W Ba Be Bc Bo Read H X X X X Write Byte a L L H H H Write Byte b L H L H H Write Byte c L H H L H Write Byte d L H H H L Write
17. State Diagram Rev 1 03a 10 2006 9 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Jol mmm Burst Cycles GS 842218 36AB 180 166 150 100 Although NBT RAMs are designed to sustain 100 bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write multiple back to back reads or writes may also be performed NBT SRAMs provide an on chip burst address generator that can be utilized if desired to further simplify burst read or write implementations The ADV control pin when driven high commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low into Load mode Burst Order The burst address counter wraps around to its initial state after four addresses the loaded address and three more have been accessed The burst sequence is determined by the state of the Linear Burst Order pin LBO When this pin is low a linear burst sequence is selected When the RAM is installed with the LBO pin tied high interleaved burst sequence is selected See the tables below for details FLXDrive The ZQ pin allows selection between NBT RAM nominal drive strength ZQ low for multi drop bus applications and low drive strength ZQ floating or high
18. T Pipeline Flow Through BGA var 1 150 10 MP 128K x 36 GS842Z36AB 1001 NBT Pipeline Flow Through BGA var 1 100 12 MP 256K x 18 GS842Z18AGB 180 NBT Pipeline Flow Through RoHS compliant BGA var 1 180 8 C MP 256K x 18 GS842Z18AGB 166 NBT Pipeline Flow Through RoHS compliant BGA var 1 166 8 5 C MP 256K x18 GS842Z18AGB 150 NBT Pipeline Flow Through RoHS compliant BGA var 1 150 10 C MP 256K x 18 GS842Z18AGB 100 NBT Pipeline Flow Through RoHS compliant BGA var 1 100 12 C MP 128K x36 GS842Z36AGB 180 NBT Pipeline Flow Through RoHS compliant BGA var 1 180 8 C MP 128K x36 GS842Z36AGB 166 NBT Pipeline Flow Through RoHS compliant BGA var 1 166 8 5 C MP ame requiring delivery in Tape and Reel should add the character T to the end of the part number Example GS842Z36AB 100IT 2 The speed column indicates the cycle frequency MHz of the device in Pipeline mode and the latency ns in Flow Through mode Each device is Pipeline Flow Through mode selectable by the user 3 Ta C Commercial Temperature Range T Industrial Temperature Range 4 MP Mass Production 5 GSI offers other versions this type of device in many different configurations and with a variety of different features only some of which are covered in this data sheet See the GSI Technology web site www gsitechnology com for a complete listing of current offerings Rev 1 03a 10 2006 Specifications cited are subject to change without notice
19. TEGNOLOGY GS842Z18 36AB 180 166 150 100 119 Bump BGA Commercial Temp Industrial Temp 4Mb Pipelined and Flow Through Synchronous NBT SRAMs 180 MHz 100 MHz 3 3 V Vo 2 5 V and 3 3 V Vppa Features e 256K x 18 and 128K x 36 configurations e User configurable Pipeline and Flow Through mode e NBT No Bus Turn Around functionality allows zero wait read write read bus utilization e Fully pin compatible with both pipelined and flow through NtRAM NoBL and ZBT SRAMs e Pin compatible with 2M 8M and 16M devices e 3 3 V 10 10 core power supply e 2 5 V or 3 3 V I O supply e LBO pin for Linear or Interleave Burst mode e Byte write operation 9 bit Bytes e 3 chip enable signals for easy depth expansion e Clock Control registered address data and control e ZZ Pin for automatic power down e JEDEC standard 119 bump BGA package e RoHS compliant package available Functional Description The GS842Z18 36AB is a 4Mbit Synchronous Static SRAM GSI s NBT SRAMs like ZBT NtRAM NoBL or other pipelined read double late write or flow through read single late write SRAMs allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles Because it is a synchronous device address data inputs and read write control inputs are captured on the rising edge of the input clock Burst order control LBO must be tied to a power rail for proper operation Asynchronous inputs inc
20. V maximum with a pulse width not to exceed 20 tKC 3 Viho max is voltage on Vppq pins plus 0 3 V Vppa2 Range Logic Levels Parameter Symbol Min Typ Max Unit Notes Vpp Input High Voltage Vu 0 6 Vpp Von 0 3 V 1 Vpp Input Low Voltage Vu 0 3 0 3 Vpp V 1 Vppq I O Input High Voltage Vina 0 6 Vpp Vppa 0 3 V 1 3 Vppq IO Input Low Voltage Vo 0 3 0 3 Vpp V 1 3 Notes 1 The part numbers of Industrial Temperature Range versions end the character I Unless otherwise noted all performance specifica tions quoted are evaluated for worst case in the temperature range marked on the device 2 Input Under overshoot voltage must be 2 V gt Vi lt Vppn t2 V not to exceed 4 6 V maximum with a pulse width not to exceed 20 tKC 3 Vue max is voltage on Vppq pins plus 0 3 V Recommended Operating Temperatures Parameter Symbol Min Typ Max Unit Notes Ambient Temperature Commercial Range Versions Ta 0 25 70 C 2 Ambient Temperature Industrial Range Versions Ta 40 25 85 C 2 Notes 1 The part numbers of Industrial Temperature Range versions end the character I Unless otherwise noted all performance specifica tions quoted are evaluated for worst case in the temperature range marked on the device 2 Input Under overshoot voltage must be 2 V gt Vi lt Vppn t2 V not to exceed 4 6 V maximum with a pulse width not
21. all Bytes L L L L L Write Abort NOP L H H H H Read operation is initiated when the following conditions are satisfied at the rising edge of clock CKE is asserted low all three chip enables E1 E2 and E3 are active the write enable input signal W is deasserted high and ADV is asserted low The address presented to the address inputs is latched in to address register and presented to the memory core and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins Write operation occurs when the RAM is selected CKE is active and the write input is sampled low at the rising edge of clock The Byte Write Enable inputs BA Bs Bc and Bp determine which bytes will be written All or none may be activated A write cycle with no Byte Write inputs active is a no op cycle The Pipelined NBT SRAM provides double late write functionality matching the write command versus data pipeline length 2 cycles to the read command versus data pipeline length 2 cycles At the first rising edge of clock Enable Write Byte Write s and Address are registered The Data In associated with that address is required at the third rising edge of clock Flow through Mode Read and Write Operations Operation of the RAM in Flow T
22. bject to change without notice For latest documentation see http www gsitechnology com Jol mmm Ordering Information GSI NBT Synchronous SRAMs GS842Z18 36AB 180 166 150 100 Speed Org Part Number Type Package MH zins Ti Status 256K x 18 GS842Z18AB 180 NBT Pipeline Flow Through BGA var 1 180 8 C MP 256K x 18 GS842Z18AB 166 NBT Pipeline Flow Through BGA var 1 166 8 5 C MP 256K x 18 GS842Z18AB 150 NBT Pipeline Flow Through BGA var 1 150 10 C MP 256K x 18 GS842Z18AB 100 NBT Pipeline Flow Through BGA var 1 100 12 C MP 128K x 36 GS842Z36AB 180 NBT Pipeline Flow Through BGA var 1 180 8 C MP 128K x 36 GS842Z36AB 166 NBT Pipeline Flow Through BGA var 1 166 8 5 C MP 128K x 36 GS842Z36AB 150 NBT Pipeline Flow Through BGA var 1 150 10 C MP 128K x 36 GS842Z36AB 100 NBT Pipeline Flow Through BGA var 1 100 12 C MP 256K x 18 GS842Z18AB 1801 NBT Pipeline Flow Through BGA var 1 180 8 MP 256K x 18 GS842Z18AB 166l NBT Pipeline Flow Through BGA var 1 166 8 5 MP 256K x 18 GS842Z18AB 1501 NBT Pipeline Flow Through BGA var 1 150 10 MP 256K x 18 GS842Z18AB 1001 NBT Pipeline Flow Through BGA var 1 100 12 MP 128K x 36 GS842Z36AB 1801 NBT Pipeline Flow Through BGA var 1 180 8 MP 128K x 36 GS842Z36AB 166l NBT Pipeline Flow Through BGA var 1 166 8 5 MP 128K x36 GS842Z36AB 1501 NB
23. hrough mode is very similar to operations in Pipeline mode Activation of a read cycle and the use of the Burst Address Counter is identical In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM rather than holding new data until the following second clock edge Therefore in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode Write operations are initiated in the same way as well but differ in that the write pipeline is one cycle shorter as well preserving the ability to turn the bus from reads to writes without inserting any dead cycles While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed Therefore in Flow Through mode address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock Rev 1 03a 10 2006 5 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 Synchronous Truth Table Operation Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ DQ Notes Read Cycle Begin Burst R External L H L L HIXJILI HIJLILJ L Q Read Cycle Continue Burst B Next L H L H XIXIXIXIXIJLIL Q 1 10 NOP Read
24. ice For latest documentation see http www gsitechnology com Mra NOGU GS842Z18 36AB 180 166 150 100 GS842Z18A Pad Out 119 Bump BGA Top View Packge B mmm Rev 1 03a 10 2006 2 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra NOGU GS842Z18 36AB 180 166 150 100 GS842Z36A Pad Out 119 Bump BGA Top View Package B mm Rev 1 03a 10 2006 3 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mrcanowe G 842218 36AB 180 166 150 100 GS842Z18 36A Pin Description Symbol Type Description Ao A1 Address field LSBs and Address Counter Preset Inputs An Address Inputs DQaA an IO Data Input and Output pins DQp Ba Ba Bc BD Byte Write Enable for DQ DQB DQc DQa I Os active low x36 Version CK Clock Input Signal active high CKE Clock Input Buffer Enable active low W Write Enable Writes all enabled bytes active low E Chip Enable active low Chip Enable active high G Output Enable active low ADV Burst address counter advance enable active high ZZ Sleep Mode control active high FT Flow Through or Pipeline mode active low LBO Linear Burst Order mode active low 20 FLXDrive Output Impedance Control
25. lel into the Boundary Scan Register on the rising edge of TCK in the Capture DR state the RAM s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ ated IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture DR mode and places the ID register between the TDI and TDO pins in Shift DR mode The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test Logic Reset state SAMPLE Z If the SAMPLE Z instruction is loaded in the instruction register all RAM outputs are forced to an inactive drive state high Z and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift DR state RFU These instructions are Reserved for Future Use In this device they replicate the BYPASS instruction JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO 1 2 Captures I O ring contents Places the Boundary Scan Register between TDI and SAMPLE Z 010 TDO 1 Forces all RAM output drivers to High Z Do not use this instruction Reserved for Future Use RPS ot Replicates BYPASS instruction Places Bypass Register between TDI and TDO l SAMPLE 100
26. lude the sleep mode enable ZZ and Output Enable Output Enable can be used to override the synchronous control of the output drivers and turn the RAM s output drivers off at any time Write cycles are internally self timed and initiated by the rising edge of the clock input This feature eliminates complex off chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing The GS842Z18 36AT may be configured by the user to operate in Pipeline or Flow Through mode Operating as a pipelined synchronous device in addition to the rising edge triggered registers that capture input signals the device incorporates a rising edge triggered output register For read cycles pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock The GS842Z18 36AT is implemented with GSI s high performance CMOS technology and is available in a JEDEC standard 119 bump BGA package when the device is switched from read to write cycles Parameter Synopsis 180 166 150 100 Pipeline tCycle 5 5ns 6 0 ns 6 6 ns 10 ns 3 1 1 1 tka 3 2 ns 3 5 ns 3 8 ns 4 5 ns lop 335mA 310mA 280mA 190mA Flow tka 8 ns 8 5 ns 10 ns 12 ns Through Cycle 9 1ns 10 ns 12ns 15 ns 2 1 1 1 lop 210mA 190mA 165mA 135mA Rev 1 03a 10 2006 1 31 2001 GSI Technology Specifications cited are subject to change without not
27. main active Low Z If CKE High occurs during a write cycle the bus will remain in High Z 5 X Don t Care H Logic High L Logic Low Bx High All Byte Write signals are high Bx Low One or more Byte Write signals are Low _ All inputs except G and ZZ must meet setup and hold times of rising clock edge Wait states can be inserted by setting CKE high This device contains circuitry that ensures all outputs are in High Z during power up A 2 bit burst counter is incorporated 0 The address counter is incriminated for all Burst continue cycles SEI E SO NN EE Rev 1 03a 10 2006 6 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra NOGU GS842Z18 36AB 180 166 150 100 Pipelined and Flow Through Read Write Control State Diagram D D Key Notes Input Command Code 1 The Hold command CKE Low is not shown because it prevents any state change L Senge p Transition 2 W R B and D represent input command indi i th Table Current State n Next State n 1 codes as indicated in the Synchronous Truth Table n n 1 n 2 n 3 Current State Next State Current State and Next State Definition for Pipelined and Flow Through Read Write Control State Diagram Rev 1 03a 10 2006 7 31 2001 GSI Technology Specifications cited are subject to change without notice Fo
28. mm Rev 1 03a 10 2006 26 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra NOLOGY GS842218 36AB 180 166 150 100 Output Driver Characteristics TBD mmm Rev 1 03a 10 2006 27 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS842218 36AB 180 166 150 100 Package Dimensions 119 Bump FPBGA Package B Variation 1 Pin 1 Corner e G0 10 OTC BOTTOM VIEW Al 60 30 C As BS 0 60 0 90 119x 123 45 67 Va 76543 2 R A By A x rer A B OO000000 B OO O O O 0 0 c D GE D S S BO0O0000 E z H eoopooo F G s ooo0o0o0o0o0 G a 2 E S OOOOO OO fE j z a amp 0 0 6 6 0 J K EE E ELE K L O000000 L M O000000 M N CO00Q000 N P O000000 P z ooo0o o0oo0o0 R S Oo00v000 T S y L oooh eee U S p IT pl a070 REF 24 lt q O H Ie 7 62 gt Al 14 0 20 gt F 0 20 4x ZG EIE gele Sells 30TYP Si ara De SH Y a wou D d 7 SEATING PLANE L Ss g S amp rail pi as O CH BPR 1999 05 18 Rev 1 03a 10 2006 28 31 2001 GSI Technology Specifications cited are su
29. put side of the serial registers placed between TDI and TDO TDO Test Data Out Ou Note This device does not have a TRST TAP Reset pin TRST is optional in IEEE 1149 1 The Test Logic Reset state is entered while TMS is held high for five rising edges of TCK The TAP Controller is also reset automaticly at power up Overview The various JTAG registers refered to as Test Access Port orTAP Registers are selected one at a time via the sequences of 1s and Os applied to TMS as TCK is strobed Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK When a register is selected it is placed between the TDI and TDO pins Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run Test Idle or the various data register states Instructions are 3 bits long The Instruction Register can be loaded when it is placed between the TDI and TDO pins The Instruction Register is automatically preloaded with the IDCODE instruction at power up or whenever the controller is placed in Test Logic Reset state Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO It allows serial test data to be passed through the RAM s JTAG Port to another device in the scan chain with as little delay as pos
30. r latest documentation see http www gsitechnology com Mra OLOGY GS842218 36AB 180 166 150 100 Pipeline Mode Data I O State Diagram Interm diate Intermediate Intermediate High Z Data In Data Out Q Valid D A Intermediate Key Notes Input Command Code Ko 1 The Hold command CKE Low is not shown because it prevents any state change Cu Transition Transition p 2 W R B and D represent input command Current State n Intermediate State N 1 Next State n 2 codes as indicated in the Truth Tables n n 1 n 2 n 3 Clock CK Command Current State Intermediate Next State State Current State and Next State Definition for Pipeline Mode Data UO State Diagram Rev 1 03a 10 2006 8 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY G 842218 36AB 180 166 150 100 Flow Through Mode Data I O State Diagram Data Out Q Valid High Z Data In Key Notes Input Command Code 1 The Hold command CKE Low is not shown because it prevents any state change CF tension 2 W R B and D represent input command Current State n Next State n 1 codes as indicated in the Truth Tables n 1 Clock CK Command Current State Next State Current State and Next State Definition for Pipelined and Flow Through Read Write Control
31. rameter Symbol Test Conditions Min Max Input Leakage Current Vin 0 toV except mode pins IL IN 010 Von SES P Vbo 2 Vin2 Vin 1 uA 1uA ZZN put Gunrani m 0V lt Vin lt Mu Au 100uA Vop2 Vin 2 Vit 100 uA 1 uA FT SCD ZQ Input Current IN2 OVEVine Ve Auk 1uA Output Leakage Current loL Output Disable Voyy 0 to Vpp 1 uA 1 uA Output High Voltage VoH2 lon 8 mA Vppo 2 375 V 1 7 V Output High Voltage Vous lon 8 mA Vppo 3 135 V 24V Output Low Voltage VoL Io 8 mA 0 4 V mmm Rev 1 03a 10 2006 15 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS 842218 36AB 180 166 150 100 Operating Currents Parameter Test Conditions Symbol Oto 40to Oto 40to Oto 40to Oto 40to Unit 70 C 85 C 70 C 85 C 70 C 85 C 70 C 85 C Device Selected Bp 335 345 310 320 280 290 190 200 mA Operating All other inputs Pipeline Current gt V or lt Vil IDD Outputopen FowThru 210 220 190 200 165 175 135 145 mA IsB Re 2 30 20 30 20 30 20 30 A Standby ZZ gt Vwo Pipeline 0 m Current 0 2V IsB Flow Thru 20 30 20 30 20 30 20 30 mA IDD j Deier 55 65 50 60 50 60 40 50 mA Deselect Device Deselected Pipeline All other inputs Current gt Vior lt Vi Go 40 50 40 50 35 45 35 45 mA Flow Thru
32. rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note Note The burst counter wraps to initial state on the 5th clock The burst counter wraps to initial state on the 5th clock BPR 1999 05 18 8 Sleep Mode During normal operation ZZ must be pulled low either by the user or by its internal pull down resistor When ZZ is pulled high the SRAM will enter a Power Sleep mode after 2 cycles At this time internal state of the SRAM is preserved When ZZ returns to low the SRAM operates normally after 2 cycles of wake up time Sleep mode is a low current power down mode in which the device is deselected and current is reduced to Igg2 The duration of Sleep Mode is dictated by the length of time the ZZ is in a high state After entering Sleep mode all inputs except ZZ become disabled and all outputs go to High Z The ZZ pin is an asynchronous active high input that causes the device to enter Sleep mode When the ZZ pin is driven high Lon is guaranteed after the time tZZI is met Because ZZ is an asynchronous input pending operations or operations in progress may not be properly completed if ZZ is asserted Therefore Sleep mode must not be initiated until valid pending operations are completed Similarly when exiting Sleep mode during tZZR only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode Sleep Mode Timing Diagram gt tKH ke tKL CK Designing for
33. sible Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM s input or I O pins The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port s TDO pin The Boundary Scan Register also includes a number of place holder flip flops always set to a logic 1 The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following The Boundary Scan Register under the control of the TAP Controller is loaded with the contents of the RAMs I O ring when the controller is in Capture DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift DR state SAMPLE Z SAMPLE PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register mmm Rev 1 03a 10 2006 20 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Mra OLOGY GS842218 36AB 180 166 150 100 JTAG TAP Block Diagram Jor ae i Boundary Scan Register kb ell La gt lt S i Bypass Register ama 2 i0 Instruction Register TDI TDO ID Code Register NE T
34. to exceed 20 tKC EE 2001 GSI Technology Rev 1 03a 10 2006 13 31 Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com lru Undershoot Measurement and Timing GS842Z18 36AB 180 166 150 100 Overshoot Measurement and Timing 50 tKC Vpp 2 0 V 50 Wen Vss 2 0 V Ga 50 tKC Vit Capacitance Ta 25 C f 1 MHZ Vpp 2 5 V Parameter Symbol Test conditions Typ Max Unit Input Capacitance Cin Vin 0V 4 5 pF Input Output Capacitance Cio Vout 0 V 6 7 pF Note These parameters are sample tested AC Test Conditions Parameter Conditions Input high level Vpp 0 2 V Input low level 0 2 V Input slew rate 1 Vins Input reference level Vpp 2 Output reference level Vppa 2 Output load Fig 1 Notes 1 Include scope and jig capacitance 2 Test conditions as specified with output loading as shown in Fig 1 unless otherwise noted 3 Device is deselected as defined by the Truth Table Output Load 1 Vppaz Distributed Test Jig Capacitance mmm 14 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com Rev 1 03a 10 2006 Mra OLOGY GS 842218 36AB 180 166 150 100 DC Electrical Characteristics Pa
35. v1 03a added RoHS compliant information Rev 1 03a 10 2006 31 31 2001 GSI Technology Specifications cited are subject to change without notice For latest documentation see http www gsitechnology com
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GSI TECHNOLOGY GS842Z18/36AB 180/166/150/100 Manual