Home

ANALOG DEVICES AD7730/AD7730L Manual

1. Plastic DIP N 24 Yi 1 275 32 30 1 125 28 60 a 13 0 280 7 11 12 ke i 6 10 9 325 8 25 0 300 7 62 0 195 4 95 0 060 1 52 0 115 2 93 ud 38 0 150 3 81 MIN 0 125 3 18 ll lt 0 015 0 015 0 381 381 0 022 0 558 0 100 2 54 0 070 1 E SEATING 0 008 0 204 0 014 0 356 0 045 1 15 PLANE Small Outline R 24 0 6141 15 60 0 5985 15 w 13 JENNEN 88 8 8 vle gig THEE N IN 1 12 lo g MA FINT 0 1043 2 65 0 0291 0 74 5 0 0926 2 35 M 0 0098 0 25 fh F gr 0 0500 1 27 0 0118 0 30 0 0500 0 0192 0 49 i 0 0 0157 0 40 0 0040 010 127 0 0138 0 35 PLANE 0 0125 0 32 0 0091 0 23 Thin Shrink Small Outline RU 24 0 311 7 90 0 303 7 70 a 0 256 6 50 0 246 6 25 0 177 4 50 0 169 4 30 2 a 0 006 0 15 0 002 0 05 0 0433 AAA 110 LU TA F mil X F 8 0 028 0 70 0 0256 0 65 0 0118 0 30 0 SEATING 00256 0 65 0 0118 0 30 0 0079 0 20 90200050 0 0035 0 090 PLANE BS 0 0075 0 19 REV A 51 86 T 8 69ZEJ V S N NI GALNIdd 52
2. Span and Offset Limits Whenever a system calibration mode is used there are limits on the amount of offset and span which can be accommodated T he overriding requirement in determining the amount of offset and gain which can be accommodated by the part is the require ment that the positive full scale calibration limit is 1 05 x FS where FS is 10 mV 20 mV 40 mV or 80 mV depending on the RN 1 RNO bits in the M ode Register T his allows the input range to go 596 above the nominal range T he built in head room in the AD 7730 s analog modulator ensures that the part will still operate correctly with a positive full scale voltage that is 596 beyond the nominal 31 AD7730 AD7730L Therange of input span in both the unipolar and bipolar modes has a minimum value of 0 8 FS and a maximum value of 2 1 x FS However the span which is the difference between the bottom of the AD 7730 s input range and the top of its input range has to take into account the limitation on the positive full scale voltage T he amount of offset which can be accommo dated depends on whether the unipolar or bipolar mode is being used Once again the offset has to take into account the limita tion on the positive full scale voltage In unipolar mode there is considerable flexibility in handling negative with respect to AIN offsets In both unipolar and bipolar modes the range of positive offsets that can be handled by the part depends on the sel
3. 3 7 32 5 105 V min to V max V min to V max mA max mA max mA max mA max uA max mW max mW max uW max With AGND 0 V External CLK Digital 0 V or DVpp All Input Ranges Except 0 mV to 10 mV and 10 mV T ypically 2 7 mA Input Ranges of 0 mV to 10 mV and 10 mV Only T ypically 4 mA DVpp Of 2 7 V to 3 3 V T ypically 0 3 mA DVpp of 4 75 V to 5 25 V T ypically 0 75 mA T ypically 13 uA External M CLK IN 20 V or DVpp AV pp DVpp 5 V D igital I Ps OV DVpp All Input Ranges Except 0 mV to 10 mV and 10 mV T ypically 15 mW Input Ranges of 0 mV to 10 mV and 10 mV Only T ypically 23 75 mW T ypically 65 uW External CLK IN 20V or DV pp 46 REV A AD7730 AD7730L NOTES 1T emperature range 40 C to 85 C 2Sample tested during initial release he offset or zero numbers with CHP 1 are typically 3 uV precalibration Internal zero scale calibration reduces this by about 1 uV Offset numbers with 0 can be up to 1 mV precalibration Internal zero scale calibration reduces this to 2 uV typical System zero scale calibration reduces offset numbers with CHP 1 and CHP 0 to the order of the noise Gain errors can be up to 3000 ppm precalibration with CHP 0 and CHP 1 Performing internal full scale calibrations on the 80 mV range reduces the gain error to less than 100 ppm for the 80 mV and 40 mV ranges to about 250 ppm for the 20 mV range and to
4. 44 REV A AD7730L SPECIFICATIONS 5v ov0 3vo0r 5v rerine AD7730 AD7730L AVpp REF IN AGND DGND 0 V 2 4576 MHz All specifications to Tmax unless otherwise noted Parameter B Version Units Conditions C omments STATIC PERFORMANCE CHP 1 No Missing Codes 24 Bits min Output N oise and U pdate Rates2 SeeTables XXI amp XXII Integral N onlinearity 22 ppm of F SR max Offset Error See Note 3 Offset Error and Offset D rift Refer to Both Offset D rift vs T emperature2 5 nV C typ Unipolar Offset and Bipolar Zero Errors Offset D rift vs Time 25 nV 1000 H ours typ Positive Full Scale Error 5 See N ote 3 Positive Full Scale D rift vs T emp 9 3 ppm of FS C max Positive Full Scale D rift vs Time 10 ppm of F S 1000 H ours typ Gain Error 8 See N ote 3 Gain Drift vs T emperature 9 9 3 ppm C max Gain Drift vs T ime 10 ppm 1000 H ours typ Bipolar N egative F ull Scale Error See N ote 3 N egative F ull Scale D rift vs T emp 6 3 ppm of FS C max Power Supply Rejection 120 dB typ M easured with Zero D ifferential Voltage Common M ode Rejection CM R 118 dB min At DC M easured with Zero D ifferential Voltage Analog Input DC Bias Current 40 nA max Analog Input DC Bias Current D rift 100 pA C typ Analog Input D C Offset C urrent2 10 nA max Analog Input DC Offset Current Drift 50 pA C typ STATIC PERFORMANCE CHP 0 No Missing Codes 24 Bits min SKIP 202 Output N oise and U pd
5. 0 3V to AV pp 0 3 V Lead Temperature Soldering AE A AIN REF IN Current Indefinite 30 mA Vapor Phase 60 sec 215 Digital Input VoltagetoDGND 0 3V to DVpp 0 3 V Infrared 15 sec 220 Digital Output Voltage to DGND O 3VtoDVpp 03V Output Voltage ACX ACX DO D1 to DGND Stresses above those listed under Absolute M aximum Ratings may cause RUNI 0 3 V to AV pp 0 3 V permanent damage to the device T his is a stress rating only functional operation of the device at these or any other conditions above those listed Operating T emperature Range the operational sections of this specification is not implied Exposure to Industrial B Version 40 C to 85 C absolute maximum rating conditions for extended periods may affect device Storage T emperatureRange 65 C to 150 C reliability Junction Temperature 150 C ORDERING GUIDE Temperature Package Package Model Range Description Options AD7730BN 40 C to 85 C Plastic D IP N 24 AD7730BR 40 C to 85 C Small Outline R 24 AD7730BRU 40 to 85 Thin Shrink Small Outline RU 24 EVAL AD7730EB Evaluation Board AD7730L BR 40 to 85 Small Outline R 24 AD 7730L BRU 40 to 85 Thin Shrink Small Outline RU 24 EVAL AD7730LEB Evaluation Board Is k 8004A AT DVpp 5V 100 AT DVpp 3V 1 6V IcouncE 200QpA AT DVpp
6. 5V 100pA AT DVpp 3V Figure 1 Load Circuit for Access Time and Bus Relinquish Time CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING accumulate on the human body and test equipment and can discharge without detection Although the AD 7730 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges T herefore proper ESD precautions recommended to avoid performance degradation loss of functionality SENSITIVE DEVICE REV A 5 AD7730 AD7730L BUFFER ANPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES SEE PAGE 24 BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A TRANSDUCER HAS BURNT OUT OR GONE OPEN CIRCUIT SEE PAGE 25 O AIN1 E M AIN2 D1 m AIN2 DO n ANALOG MULTIPLEXER A TWO CHANNEL DIFFERENTIAL MULTIPLEXER SWITCHES ONE OF THE TWO DIFFERENTIAL INPUT CHANNELS TO THE BUFFER AMPLIFIER THE MULTIPLEXER IS CONTROLLED VIA THE SERIAL INTERFACE SEE PAGE 24 AC EXCITATION E A lt lt gen EXCITATION OUTPUT DRIVERS DIFFERENTIAL REFERENCE PROGRAMMABLE GAIN AMPLIFIER THE REFERENCE INPUT TO THE PART IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION THE REFERENCE VOLTAGE
7. T he internal full scale calibration is a two step sequence that runs when an internal full scale calibration command is written to the AD 7730 One part of the calibration is a zero scale cali bration and as a result the contents of the Offset C alibration Register are altered during this Internal F ull Scale C alibration T he user must therefore perform a zero scale calibration either internal or system AFTER the internal full scale calibration T his zero scale calibration should be performed at the operating input range T his means that internal full scale calibrations cannot be performed in isolation T he calibration is performed with dc excitation regardless of the status of the ac bit T he duration time of the calibration de pends upon the CHP bit of the Filter Register With CHP 1 the duration is 44 x 1 Output Rate with CHP 0 the duration is 48 x 1 O utput Rate At this time the MD2 MD1 and bits in the M ode Register return to 0 0 0 Sync or Idle M ode for the AD 7730 T he RDY line goes high when calibration is initiated and returns low when calibration is complete N ote that the part has not performed a conversion at this time T he REV A AD7730 AD7730L user must write either 0 0 1 or 0 1 0 to the M D2 M D1 M DO bits of the M ode Register to initiate a conversion If RDY is low before or goes low during the calibration com mand write to the M ode Register it may take up to one modulator cycle
8. 0 The RDY output and bit go high when calibration is initiated and return low when this full scale calibra tion is complete to indicate that the part is back in Sync M ode and ready for further operations 16 REV A AD7730 AD7730L Bit Location Bit Mnemonic Description MRI2 11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 B U DEN 01 00 WL HIREF ZERO RN1 RN0 CLKDIS Bipolar U nipolar Bit A 0 in this bit selects bipolar operation and the output coding is 00 000 for negative full scale input 10 000 for zero input and 11 111 for positive full scale input A 1 in this bit selects unipolar operation and the output coding is 00 000 for zero input and 11 111 for positive full scale input Digital Output Enable Bit With this bit at 1 the AIN2 D 1 and AIN 2 D 0 pins assume their digital output functions and the output drivers connected to these pins are enabled In this mode the user effectively has two port bits which can be programmed over the serial interface Digital Output Bits T hese bits determine the digital outputs on the AIN 2 D 1 and AIN 2 D 0 pins respectively when the DEN bit is a 1 For example a 1 written to the D 1 bit of the M ode Register with the DEN bit also a 1 will put a logic 1 on the AIN2 D1 pin T his logic 1 will remain on this pin until a 0 is written to the D 1 bit in which case the AIN 2 D 1 pin goes to a
9. 600 Hz 23 4 Hz 512 41 6 ms 6 6 ms 300 225 135 110 1200Hz 46 8Hz 256 20 8 ms 3 3 ms 435 315 210 150 Table IV Peak to Peak Resolution vs Input Range Update Rate CHP 0 Peak to Peak Resolution in Counts Bits Output 3dB SF Settiing Time Settling Time Input Range InputRange Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40 mV 20mV 10mV 150 Hz 5 85 Hz 2048 166 ms 26 6 ms 165k 17 5 120k 17 80k 16 5 55k 16 200 Hz 7 8 Hz 1536 125 ms 20 ms 140k 17 100k 16 5 70k 16 45k 15 5 300 Hz 11 7 Hz 1024 83 3 ms 13 3 ms 115k 17 90k 16 5 65k 16 40k 15 5 600 Hz 23 4 Hz 512 41 6 ms 6 6 ms 90k 16 5 60k 16 50k 15 5 30k 15 1200 Hz 46 8 Hz 256 20 8 ms 3 3 ms 60k 16 43k 15 5 32k 15 20k 14 5 ON CHIP REGISTERS T he AD 7730 contains thirteen on chip registers which can be accessed via the serial port of the part T hese registers are summarized in Figure 4 and in T able V and described in detail in the following sections REV A COMMUNICATIONS REGISTER OFFSET REGISTER x3 11 Figure 4 Register Overview REGISTER SELECT DECODER AD7730 AD7730L Table V Summary of On Chip Registers Power On R eset Function Register Name Type Size Default Value Communications Write Only 8 Bits Not Applicable Register WEN ZERO RW1 RWO ZERO RS2 RSI RSO Status R egister Read Only 8 Bits CX Hex RDY STDY STBY NOREF MS3 M S2 MS1 MS0 Data Reg
10. M CLK IN 32 before RDY goes high to indicate that calibration is in progress T herefore RDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the M ode Register System Zero Scale Calibration System calibration allows the AD 7730 to compensate for system gain and offset errors as well as its own internal errors System calibration performs the same slope factor calculations as self calibration but uses voltage values presented by the system to the AIN inputs for the zero and full scale points A system zero scale calibration is initiated on the AD 7730 by writing the appropriate values 1 1 0 to the M D2 MD1 and M DO bits of the M ode Register In this calibration mode with a unipolar input range the zero scale point used in determin ing the calibration coefficients is the bottom end of the trans fer function T he system s zero scale point is applied to the AD 7730 s AIN input before the calibration step and this voltage must remain stable for the duration of the system zero scale calibration T he PGA is set for the selected gain as per the RN 1 RNO bits in the M ode Register for this system zero scale calibration conversion T he allowable range for the system zero scale voltage is discussed in the Span and Offsets Section T he calibration is performed with either ac or dc excitation depending on the status of the AC bit T he duration time of the calibration de
11. read back the contents of the T est Register depending on the test mode in which the part has been placed 20 REV A AD7730 AD7730L READING FROM AND WRITING TO THE ON CHIP REGISTERS The AD7730 contains a total of thirteen on chip registers T hese registers are all accessed over a three wire interface As a result addressing of registers is via a write operation to the topmost register on the part the Communications Register Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers F igure 6 gives a flowchart for writing to the different registers on the part again summarizing the sequence and words to be written to the AD 7730 START Byte W ByteY ByteZ Register Hex Hex Hex CONTINUOUS Status R egister 10 20 30 Data Register 11 21 30 REQUIRED M ode R egister 12 22 30 Filter Register 13 N A N A DAC Register 14 N A Offset Register 15 N A N A COMMUNICATIONS REGISTER Gain Register 16 N A N A SEE ACCOMPANYING TABLE T est R egister 17 N JAX N WRITE COMMUNICATIONS REGISTER ACCOMPANYING TABLE READ REGISTER STOP CONTINUOUS N A NotApplicable Continuous reads of these registers does not make sense as the register contents would remain the same since they are only changed by a write operation READ REGISTER REA
12. the rising edge of SYNC starts conversion and the falling edge of RDY indicates when conversion is com plete T he disadvantage of this scheme is that the settling time of the filter has to be taken into account for every data register update Writing 0 1 0 to the M D2 M D1 M DO bits of the M ode regis ter has the same effect T his initiates a single conversion on the AD 7730 with the part returning to idle mode at the end of conversion Once again the full settling time of the filter has to elapse before the D ata Register is updated REV A AD7730 AD7730L Reset Input The RESET input on the AD 7730 resets all the logic the digital filter and the analog modulator while all on chip registers are reset to their default state RDY is driven high and the AD 7730 ignores all communications to any of its registers while the RESET input is low When the RESET input returns high the AD 7730 starts to process data and RDY will return low after the filter has settled indicating a valid new word in the data register H owever the AD 7730 operates with its default setup conditions after a RESET and it is generally necessary to set up all registers and carry out a calibration after a RESET command The AD 7730 s on chip oscillator circuit continues to function even when the RESET input is low T he master clock signal continues to be available on the M CLK OUT pin Therefore in applications where the system clock is provide
13. 40 ms 325 245 160 110 150Hz 5 85 Hz 1024 166 ms 26 6 ms 410 215 180 130 300Hz 11 7 Hz 512 83 ms 13 3 ms 590 370 265 180 600 Hz 23 4 Hz 256 41 6 ms 6 6 ms 910 580 350 220 Table XXIV Peak to Peak Resolution vs Input Range and U pdate Rate CHP 0 Peak to Peak Resolution in Counts Bits Output 3dB SF Settiing Time Settling Time InputRange InputRange Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40mV 20mV 10 75 Hz 2 9 Hz 2048 332 ms 53 2 ms 85k 16 5 62k 16 49k 15 5 33k 15 100 Hz 3 9 Hz 1536 250 ms 40 ms 82k 16 5 55k 15 5 42k 15 5 30k 15 150 Hz 5 85 Hz 1024 166 ms 26 6 ms 65k 16 48k 15 5 36k 15 25k 14 5 300 Hz 11 7 Hz 512 83 ms 13 3 ms 45k 15 5 36k 15 25k 14 5 18k 14 600 Hz 23 4 Hz 256 41 6 ms 6 63 ms 30k 15 23k 14 5 19k 14 15k 14 REV A 49 AD7730 AD7730L PAGE INDEX Topless upa sas eee giaa a ap Page FEATURES us ay aa 1 GENERAL DESCRIPTION 1 AD7730 SPECIFICATIONS 2 TIMING CHARACTERISTICS 4 ABSOLUTE MAXIMUM RATINGS 5 ORDERING GUIDE ect Ber iue dus 5 DETAILED FUNCTIONAL BLOCK DIAGRAM 6 SIGNAL PROCESSING CHAIN 7 PIN CONFIGURATION 7 PIN FUNCTION DESCRIPTION 7 TERMINOLOGY piia sami em sai e 9 OUTPUT NOISE A
14. Communications Register Write Operation 0 0 0 Status Register Read Operation 0 0 1 Data Register 0 1 0 M ode Register 0 1 1 Filter Register 1 0 0 DAC Register 1 0 1 1 1 0 1 1 1 Status Register RS2 RSO 0 0 0 Power On Reset Status CX Hex T he Status Register is an 8 bit read only register T o access the Status Register the user must write to the Communications egister selecting either a single shot read or continuous read mode and load bits RS2 RS1 RSO with 0 0 0 T able IX outlines the bit desig nations for the Status Register SRO through SR7 indicate the bit location SR denoting the bits are in the Status Register SR7 denotes the first bit of the data stream Figure 5 shows a flowchart for reading from the registers on the AD 7730 T he number in brackets indicates the power on reset default status of that bit Table IX Status Register SR7 SR6 SR5 SR4 SR3 SR2 SR1 SRO RDY 1 STDY 1 STBY 0 NOREF 0 MS3 X MS2 X MSO X Bit Bit Location Mnemonic Description SR7 RDY Ready Bit T his bit provides the status of the RDY flag from the part T he status and function of this bit is the same as the RDY output pin A number of events set the RDY bit high as indi cated in T able XVIII SR6 STDY Steady Bit T his bit is updated when the filter writes a result to the D ata Register If the filter is in FAST Step mode see F ilter Register section and responding to a step input the STDY
15. DVpp 4 75 V to 5 25 V 80 ns max DVpp 2 75 V to 3 3 V th 0 ns min CS Falling Edge to D ata Valid D elay 60 ns max DVpp 2 44 75 V to 45 25 V 80 ns max DVpp 42 7 V to 43 3 V tc 100 ns min SCLK High Pulsewidth t 100 ns min SCLK Low Pulsewidth ts 0 ns min CS Rising Edgeto SCLK Inactive Edge H old Time ta 10 ns min Bus Relinquish Time after SCLK Inactive Edge 80 ns max tio 100 ns max SCLK Active Edge to RDY High Write Operation tu 0 ns min CS Falling Edge to SCLK Active Edge Setup Time ti 30 ns min Data Valid to SCLK Edge Setup T ime 25 5 Data Valid to SCLK Edge Hold T ime tu 100 ns min SCLK High Pulsewidth tis 100 ns min SCLK Low Pulsewidth tig 0 ns min CS Rising Edge to SCLK Edge H old Time NOTES 1S ample tested during initial release to ensure compliance All input signals are specified with tr tf 5 ns 10 to 90 of DV pp and timed from a voltage level of 1 6 V See Figures 18 and 19 SCLK active edge is falling edge of SCLK with POL 1 SCLK active edge is rising edge of SCLK with POL 0 T hese numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vo or Vou limits his specification only comes into play if CS goes low while SCLK islow POL 1 or if CS goes low while SCLK is high POL 0 It is primarily required for interfacing to DSP machines 8T hese numbers are derived from the measured time taken by the data output to change 0 5
16. From 59 Hzto 61 Hz Common M ode 50 H z Rejection 120 dB min From 49 Hzto 51 Hz Common M ode 60 H z Rejection 120 dB min From 59 Hzto 61 Hz Analog Inputs D ifferential Input Voltage Ranges Assuming 2 5 V or 5 V Reference with HIREF Bit Set Appropriately Oto 10 or 10 mV nom Gain 250 0 to 20 or 20 mV nom Gain 125 0 to 40 or 40 mV nom Gain 62 5 0 to 80 or 80 mV nom Gain 31 25 Absolute C ommon M ode Voltage AGND 1 2V V min AV pp 0 95 V V max Reference Input REF IN REF IN Voltage 2 5 V nom HIREF Bit of M Register 0 REF IN REF IN Voltage 5 V nom HIREF Bit of M ode Register 1 Absolute C ommon M ode Voltage AGND 30 mV V min AV pp 30 mv V max NO REF Trigger Voltage 0 3 V min NO REF Bit Active If Vag Below T his Voltage 0 65 V max NO REF Bit Inactive If Vage Above T his Voltage 2 REV A AD7730 AD7730L Parameter B Version Units Conditions Comments LOGIC INPUTS Input Current 10 max All Inputs Except SCLK and M CLK IN Vini Input Low Voltage 0 8 V max DVpp 45V Vini Input Low Voltage 0 4 V max DVpp 43V Vinn Input High Voltage 2 0 V min SCLK Only Schmitt T riggered Input Vou 1 4 3 V min to V max DVpp 5 Vi 1 2 5 V min to V max DVpp 3 V 0 8 1 4 V to V DVpp 5 V V 0 4 1 1 V min to V max DVpp 3 Vr 0 4 0 8 V min to V max DVpp 5 V Vr Vy 0 4 0 8 V min to V max DVpp 3 MCLK I
17. OUT provides an inverted clock sig nal T his clock can be used to provide a clock source for external circuits and M CLK OUT is capable of driving one CM OS load If the user does not require it MCLK OUT can beturned off with the CLK D IS bit of the M ode Register T his ensures that the part is not burning unnecessary power driving capacitance on the M CLK OUT pin Clock Polarity Logic Input T his determines the polarity of the serial clock If the active edge for the proces sor is a high to low SC L K transition this input should be low In this mode the AD 7730 puts out data on the DATA OUT line a read operation on low to high transition of SCLK and clocks in data from the DAT A IN line in a write operation on a high to low transition of SCLK In applications with a noncontinuous serial clock such as most microcontroller applications this means that the serial clock should idle low between data transfers If the active edge for the processor is a low to high SCLK transition this input should be high In this mode the AD 7730 puts out data on the DATA OUT line in a read operation on a high to low transi tion of SCLK and clocks in data from the DATA IN line in a write operation on a low to high transition of SCLK In applications with a noncontinuous serial clock such as most microcontroller applications this means that the serial clock should idle high between data transfers Logic Input that allows for synchronization of the digital
18. Register goes to 0 Figure 15 shows the different responses to a step input with FASTStep mode enabled and disabled T he vertical axis shows the code value returned by the AD 7730 and indicates the set tling of the output to the input step change T he horizontal axis shows the number of outputs it takes for that settling to occur T he positive input step change occurs at the fifth output In FASTStep mode the output has settled to the final value by the eighth output In normal mode the output has not reached close to its final value until after the 25th output 20000000 15000000 10000000 CODE 5000000 0 0 5 10 15 20 25 NUMBER OF OUTPUTS Figure 15 Step Response for FASTStep and Normal Operation REV A In FASTStep mode the part has settled to the new value much faster With chopping enabled the F AST Step mode settles to its value in two outputs while the normal mode settling takes 23 outputs Between the second and 23rd output the F AST Step mode produces a settled result but with additional noise com pared to the specified noise level for its operating conditions It starts at a noise level that is comparable to SKIP mode and as the averaging increases ends up at the specified noise level T he complete settling time to where the part is back within the specified noise number is the same for FAST Step mode and normal mode As can be seen from Figure 13 the FAST Step mode gives a
19. The AD7730 contains two 100 nA constant current generators one source current from AV pp to AIN and one sink current from AIN to AGN D The currents are switched to the se lected analog input pair Both currents are either on or off depending on the BO bit of the M ode Register T hese currents can be used in checking that a transducer is still operational before attempting to take measurements on that channel If the currents are turned on allowed flow in the transducer a mea surement of the input voltage on the analog input taken and the voltage measured is full scale it indicates that the transducer has gone open circuit If the voltage measured is 0 V it indicates that the transducer has gone short circuit For normal operation these burnout currents are turned off by writing a 0 to the BO bit T he current sources work over the normal absolute input voltage range specifications REFERENCE INPUT The AD 7730 s reference inputs REF IN and REF IN provide a differential reference input capability T he common mode range for these differential inputs is from AGND to AV pp T he nominal reference voltage REF IN REF IN for specified operation is 2 5 V with the HIREF bit at 0 V and 5 V with the HIREF bit at 1 The part is also functional with of 2 5 V with the HIREF bit at 1 T his results in a halving of all input ranges T he resolution in nV will be unaltered but will appear halved in term
20. Update Rate CHP 1 Typical Output RMS Noise in nV Output 3dB SF Settiing Time Settling Time Input Range InputRange InputRange Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40 mV 20mV 10mV 25 Hz 0 98 Hz 2048 920 ms 120 ms 245 140 105 70 50 Hz 1 97 Hz 1024 460 ms 60 ms 340 220 160 100 75 Hz 2 96 Hz 683 306 ms 40 ms 420 270 170 110 100Hz 3 95Hz 512 230 ms 30 ms 500 290 180 130 200 Hz 7 9 Hz 256 115 ms 15 ms 650 490 280 165 Power On D efault Table XXII Peak to Peak Resolution vs Input Range and Update Rate CHP 1 Peak to Peak Resolution in Counts Bits Output 3dB SF Settiing Time Settling Time Input Range InputRange Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40 mV 20mV 10 25 Hz 0 98 Hz 2048 920 ms 120 ms 110 17 94k 16 5 64k 16 46 15 5 50 Hz 1 97 Hz 1024 460 ms 60 ms 80k 16 5 60k 16 42k 15 5 33k 15 75Hz 2 96 Hz 683 306 ms 40 ms 62k 16 50k 15 5 39k 15 31k 15 100Hz 3 95Hz 512 230 ms 30 ms 53k 15 5 46k 15 5 36k 15 25k 14 5 200 Hz 7 9Hz 256 115 ms 15 ms 44k 15 5 27k 15 24k 14 5 20k 14 5 Power On D efault Output Noise CHP 0 Table XXIII shows the output rms noise for some typical output update rates and 3 dB frequencies for the AD 7730L when used in nonchopping mode C H P of Filter Register 0 with a master clock frequency of 2 4576 M Hz T hese numbers are
21. V when loaded with the circuit of Figure 1 T he measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor T his means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances TRDY returns high after the first read from the device after an output update T he same data can be read again if required while RDY is high although care should be taken that subsequent reads do not occur close to the next output update REV A 47 AD7730 AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730L can be programmed to operate in either chop mode or nonchop mode T he chop mode can be enabled in ac excited or dc excited applications it is optional in dc excited applications but chop mode must be enabled in ac excited applications T hese options are discussed in more detail in earlier sections T he chop mode has the advantage of lower drift numbers and better noise immunity but the noise is approximately 20 higher for a given 3 dB frequency and output data rate It is envisaged that the major ity of weigh scale users of the AD 7730L will operate the part in chop mode to avail themselves of the excellent drift performance and noise immunity when chopping is enabled T he following tables outline the noise performance of the part in both chop and nonchop modes over all input ranges for a selecti
22. been performed on the part T he first method is to select the AIN 1 AIN 1 input chan nel arrangement In this case the differential inputs to the AD 7730 are internally shorted together to provide a zero differ ential voltage for the analog modulator External to the device the AIN 1 input should be connected to a voltage which is within the allowable common mode range of the part T he second scheme is to evaluate the part with a voltage near input full scale T his can be achieved by again using input pair AIN 1 but by adding a differential voltage via the TARE DAC This allows the user to evaluate noise performance with a near full scale voltage T he software in the evaluation board package allows the user to look at the noise performance in terms of counts bits and nV Once the user has established that the noise performance of the part is satisfactory in this mode an external input voltage can then be applied to the device incorporating more of the signal chain REV A AD7730 AD7730L SERIAL INTERFACE The AD7730 s programmable functions are controlled via a set of on chip registers A ccess to these registers is via the part s serial interface After power on or RESET the device expects a write to its Communications R egister T he data written to this register determines whether the next operation to the part is a read or a write operation and also determines to which register this read or write operation occ
23. bit remains high as the initial conversion results become available The RDY output and bit are set low on these initial conversions to indicate that a result is available If the STDY is high however it indicates that the result being provided is not from a fully settled second stage FIR filter When the FIR filter has fully settled the STDY bit will go low coincident with RDY If the part is never placed into its FAST Step mode the STDY bit will go low at the first D ata Register read and it is not cleared by subsequent D ata Register reads A number of events set the STDY bit high as indicated in T able X VIII STDY is set high along with RDY by all events in the table except a D ata Register read SR5 ST BY Standby Bit T his bit indicates whether the AD 7730 is in its Standby M ode or normal mode of operation T he part can be placed in its standby mode using the STANDBY input pin or by writing 011 to the M D2 to M DO bits of the M ode Register T he power on reset status of this bit is 0 assuming the STANDBY pin is high SR4 NOREF No Reference Bit If the voltage between the REF IN and REF IN pins is below 0 3 V or either of these inputs is open circuit the NOREF bit goes to 1 If NOREF isactive on comple tion of a conversion the D ata Register is loaded with all 1s If NOREF is active on completion of a calibration updating of the calibration registers is inhibited SR3 SRO M S3 M 50 T hese bits are for factory use T he power on
24. data and produces a result at an output rate determined by the SF word Operating in nonchop mode can result in a 2096 reduction in noise for a given band width but without the excellent drift and noise rejection ben efits which accrue from chopping the part T he output update and first notch of this first stage filter correspond and are deter mined by the relationship fouk IN 1 Output Rate e where SF is the decimal equivalent of the data loaded the SF bits of the Filter Register and fci iy is the master clock frequency REV A Chop Mode With chop mode enabled on the AD 7730 the signal processing chain is synchronously chopped at the analog input and at the output of the first stage filter T his means that for each output of the first stage filter to be computed the full settling time of the filter has to elapse T his results in an output rate from the filter that is three times lower than for a given SF word than for nonchop mode T he output update and first notch of this first stage filter correspond and are determined by the relationship fouk iN 1 tput Rate aU where SF isthe decimal equivalent of the data loaded to the SF bits of the Filter Register and fc in is the master clock frequency Second Stage Filter As stated earlier the second stage filter has three distinct modes of operation which result in a different overall filter profile for the part T he modes of operatio
25. dee aa ha 29 Internal Zero Scale Calibration 30 Internal Full Scale Calibration 30 System Zero Scale Calibration 31 System Full Scale Calibration 31 Span and Offset Limits 31 Power Up and Calibration 32 Drift Considerations 32 USING THE AD7730 LRL Tau da 32 Clocking and Oscillator Circuit 32 System Synchronization 33 Single Shot Conversions 33 Reset bu m REN UO TUS EEG 33 Standby Mode 33 Digital Outputs 33 POWER SUPPLIES aciari ill IEEE EVER 34 Grounding and Layout 34 Evaluating the AD 7730 Performance SERIAL INTERFACE Write Operation Read Operation CONFIGURING THE AD7730 MICROCOMPUTER MICROPROCESSOR INTERFACING u a hy e a Een CR PRODR 38 AD 7730 to 68HC11 Interface 38 AD 7730 to 8051 Interface 38 AD7730to ADSP 2105 Interface 39 APPEICATIONS S S eek Rr RE Een pwe de 40 DC Excitation of Bridge 40 AC Excitation of Bridge 41 Bipolar Excitation of Bridge 42 APPENDIX A AD7730L SPECIFICATIONS 43 SPECIFICATIONS u dcr e awa ha
26. equalize the thermocouples on each leg of the differen tial input to minimize the differential voltage generated AD7730 STANDBY Q SYNC MCLK IN nu SERIAL INTERFACE ru Figure 23 Typical Connections for DC Excited Bridge Application 40 REV A AD7730 AD7730L Long lead lengths from the bridge to the AD 7730 facilitate the pickup of mains frequency on the analog input the reference input and the power supply T he analog inputs to the AD 7730 are buffered which allows the user to connect whatever noise reduction capacitors are necessary in the application T he AD 7730 boasts excellent common mode and normal mode rejection of mains frequency on both the analog and reference inputs In CHOP mode care must be taken in choosing the output update rate so it does not result in reducing line frequency rejection see DIGITAL FILTERING section T he input offset current on the AD 7730 is 10 nA maximum which results in a maxi mum dc offset voltage of 1 75 mV in a 350 Q bridge applica tion Care should taken with inserting large source impedances on the reference input pins as these inputs are not buffered and the source impedances can result in gain errors In many load cell applications a portion of the dynamic range of the bridge output is consumed by a pan weight or tare weight In such applications the 6 bit TARE DAC of the AD 7730 can be used to adjust out this tare weight as outlined previousl
27. ext Operation as Write to Filter Register Write 800010 H ex to Serial Port Writes to Filter Register Setting a 50 Hz Output Rate in CHOP M ode W rite 04 H ex to Serial Port Writes to Communications Register Setting N ext Operation as Write to DAC Register Write 23 H ex to Serial Port Writes to DAC Register Setting Subtraction Value of 7 5 mV 5 V Refer ence on the T ARE DAC Write 02 H ex to Serial Port Writes to Communications Register Setting N ext O peration as Write to M ode Register Write B180 H ex to Serial Port Writes to M ode Register Initiating Internal Full Scale Calibration for 0 mV to 10 mV Input Range Waitfor RDY Low Wait for RD Y pin to go low to indicate end of calibration cycle Write 02 H ex to Serial Port f Writes to Communications Register Setting N ext O peration as Write to M ode Register Write 9180 H ex to Serial Port Writes to M ode Register Initiating Internal Zero Scale Calibration for 0 mV to 10 mV Input Range Waitfor RDY Low Wait for RD Y pin to go low to indicate end of calibration cycle f T he part has now completed self calibration and is in idle mode 1T his operation is not necessary if the default values of the Filter Register or the DAC Register the values used in the application Table XX Pseudo C ode for Setting Up AD 7730 for Continuous Conversion and Continuous Read Operation Write 02 H ex to Serial Port Writes to Communications Regist
28. filters and analog modulators when using a number of AD 7730s While SYNC is low the nodes of the digital filter the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state SYNC does not affect the digital interface but does reset RDY to a high state if it is low While SYNC is asserted the M ode Bits may be set up for a subsequent operation which will commence when the SYNC pin is deasserted Logic Input Active low input that resets the control logic interface logic digital filter analog modulator and all on chip registers of the part to power on status Effectively everything on the part except for the clock oscillator is reset when the RESET pin is exercised Analog Output T his analog output is an internally generated voltage used as an internal operating bias point T his output is not for use external to the AD 7730 and it is recommended that the user does not connect any thing to this pin Ground reference point for analog circuitry Analog Positive Supply Voltage The AV pp to AGND differential is 5 V nominal Analog Input Channel 1 Positive input of the differential programmable gain primary analog input pair T he differential analog input ranges are 0 mV to 10 mV 0 mV to 20 mV 0 mV to 40 mV and 0 mV to 80 mV in unipolar mode and 10 mV 20 mV 40 mV and 80 mV in bipolar mode Analog Input Channel 1 N egative input of the differential programmable gain p
29. for full detail Table XVII Calibration Operations Calibration Type MD2 MD1 MDO Duration to RDY Low CHP 1 Duration to RDY Low CHP 0 Calibration Sequence Internal Zero Scale Internal Full Scale System Zero Scale System F ull Scale 1 0 0 1 0 1 1 1 0 1 1 1 22 x 1 Output Rate 44 x 1 Output Rate 22 x 1 Output Rate 22 x 1 Output Rate 24 x 1 Output Rate 48 x 1 Output Rate 24 x 1 Output Rate 24 x 1 Output Rate Calibration on internal shorted input with PGA set for selected input range T he ac bit is ignored for this calibra tion sequence T he sequence is performed with dc excitation T he Offset C alibration Register for the selected channel is updated at the end of this calibration sequence F or full self calibration this calibration should be preceded by an Internal Full Scale calibration F or applications which require an Internal Zero Scale and System F ull Scale calibration this Internal Zero Scale calibration should be performed first Calibration on internally generated input full scale with PGA set for selected input range T he ac bit is ignored for this calibration sequence T he sequence is performed with dc excitation The Gain Calibration Register for the selected channel is updated at the end of this calibration sequence It is recommended that internal full scale calibrations are performed on the 80 mV range regardless of the subsequent oper
30. from the output shift register of the AD 7730 With the POL input at a logic high the data is clocked out of the output shift register on the falling edge of SCLK With the POL input at a logic low the data is clocked out of the output shift register on the rising edge of SCLK Figure 19 also shows the CS input being used to decode the read operation to the AD 7730 However this CS input can be used in a number of different ways It is possible to operate the part in three wire mode where the CS input is permanently tied low In this case the SCLK line should idle high between data transfer when the POL input is high and should idle low be tween data transfers when the POL input is low For POL 1 the first falling edge of SC L K clocks data from the output shift register onto the DOUT line of the AD 7730 It is then clocked into the microcontroller on the next rising edge of SCLK For POL 0 the first clock edge that clocks data from the AD 7730 onto the DOUT lineis a rising edge It is then clocked into the microcontroller on the next falling edge of SCLK In other microcontroller applications which require a decoding of the AD 7730 CS can be generated from a port line In this case CS would go low well in advance of the first falling edge of SCLK POL 1 or the first rising edge of SCLK POL 0 Clocking of each bit of data is as just described 35 AD7730 AD7730L In DSP applications the SCL K is generally a continuous c
31. he output update rate is selected via the SFO to SF 11 bits of the F ilter Register TablelV meanwhile shows the output peak to peak resolution in counts for the same output update rates T he numbers in brackets are the effective peak to peak resolution in bits rounded to the nearest 0 5 LSB It is important to note that the numbers in T able IV represent the resolution for which there will be no code flicker within a six sigma limit T hey are not calculated based on rms noise but on peak to peak noise The numbers are generated for the bipolar input ranges When the part is operated in unipolar mode the output noise will be the same as the equivalent bipolar input range As a result the numbers in T able III will remain the same for unipolar ranges while the numbers in T able IV will change T o calculate the number for T able IV for unipolar input ranges simply divide the peak to peak resolution number in counts by two or subtract one from the peak to peak resolution number in bits 10 REV A AD7730 AD7730L Tablelll Output Noise vs Input Range and Update Rate CHP 0 Typical Output RMS Noise in nV Output 3dB SF SettlingTime Settling Time InputRange InputRange InputRange Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40 mV 20mV 10mV 150 Hz 5 85 Hz 2048 166 ms 26 6 ms 160 110 80 60 200 Hz 7 8 Hz 1536 125 ms 20 ms 190 130 95 75 300 Hz 11 7 Hz 1024 83 3 ms 13 3 ms 235 145 100 80
32. in appli cations where there are long lead lengths from the bridge to the AD7730 It means that the converter could encounter errors because it is processing signals which are not fully settled T he AD7730 addresses this problem by allowing the user to program a delay of up to 48 75 us between the switching of the AC X signals and the processing of data at the analog inputs T his is achieved using the DL bits of the Filter Register TheAD 7730 also scales the ACX switching frequency in accor dance with the output update rate T his avoids situations where the bridge is switched at an unnecessarily faster rate than the system requires T he fact that the AD 7730 can handle reference voltages which are the same as the excitation voltages is particularly useful in ac excitation where resistor divider arrangements on the reference input add to the settling time associated with the Switching AD7730 SIGMA DELTA A D CONVERTER 1 SIGMA PROGRAMMABLE DELTA DIGITAL MODULATOR FILTER 1 O STANDBY SERIAL INTERFACE AND CONTROL LOGIC Figure 24 Typical Connections for AC Excited Bridge Application REV A 41 AD7730 AD7730L Bipolar E xcitation of the Bridge As mentioned previously some applications will require that the AD 7730 handle inputs from a bridge that is excited by a bipolar voltage T he number of applications requiring this are limited but with the addition of some exter
33. it gives the best shielding D igital and analog ground planes should only be joined in one place If the AD 7730 is the only device requiring an AGND to DGND connection the ground planes should be connected at the AGND and DGND pins of the AD 7730 If the AD 7730 is in a system where multiple devices require AGN D to DGND connections the connection should still be made at one point only a star ground point that should be established as closely as possible to the AD 7730 Avoid running digital lines under the device as these will couple noise onto the die T he analog ground plane should be allowed to run under the AD 7730 to avoid noise coupling T he power supply lines to the AD 7730 should use as large a trace as pos sibleto provide low impedance paths and reduce the effects of glitches on the power supply line F ast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs Avoid crossover of digital 34 and analog signals T races on opposite sides of the board should run at right angles to each other T his will reduce the effects of feedthrough through the board A microstrip technique is by far the best but is not always possible with a double sided board In this technique the component side of the board is dedicated to ground planes while signals are placed on the solder side Good decoupling is i
34. normal FIR filter as the second stage filter With FAST Step mode enabled the second stage filter will continue to process steady state inputs with the filter in its normal FIR mode of operation H owever the part is continuously monitoring the output of the first stage filter and comparing it with the second previous output If the difference between these two outputs is greater than a predeter mined threshold 196 of full scale the second stage filter switches to a simple moving average computation W hen the step change is detected the STDY bit of the Status Register goes to 1 and will not return to 0 until the FIR filter is back in the processing loop Theinitial number of averages in the moving average computa tion is either 2 chop enabled or 1 chop disabled T he num ber of averages will be held at this value as long as the threshold is exceeded Once the threshold is no longer exceeded the step on the analog input has settled the number of outputs used to compute the moving average output is increased T he first and second outputs from the first stage filter where the threshold is no longer exceeded is computed as an average by two then four outputs with an average of four eight outputs with an average of eight and six outputs with an average of 16 At this time the second stage filter reverts back to its normal FIR mode of opera tion When the second stage filter reverts back to the normal FIR the STDY bit of the Status
35. of 55 Hz will result in a 6 dB attenuated aliased frequency of 5 H z with only a further 25 dB attenuation based on the filter profile T his number is based on the filter roll off and Figure 11 can be used as a reference by dividing the frequency scale by a factor of 4 Choosing 57 Hz as the output rate will give better than 90 dB attenuation of the aliased line frequency which appears as a 7 Hz signal Similarly multiples of the line frequency should be avoided as the output rate because harmonics of the line fre quency will not be fully attenuated T he programmability of the AD 7730 s output rate should allow the user to readily choose an output rate that overcomes this issue An alternative is to use the part in nonchop mode Figure 13 shows the frequency response for the AD 7730 with the second stage filter set for normal FIR operation chop mode disabled the decimal equivalent of the word in the SF bits set to 1536 and a master clock frequency of 4 9152 M H z T he response is analogous to that of Figure 11 with the three times larger SF word producing the same 200 H z output rate Once again the response will scale proportionally with master clock frequency T he response is shown from dc to 100 Hz T he rejection at 50 Hz 1Hz and 60 Hz 1Hzis better than 88 dB GAIN dB 10 20 30 4 5 6 70 80 90 100 FREQUENCY Hz Figure 13 Detailed Full Frequency Response of AD7730 Se
36. of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1998 AD7730 SPECIFICATIONS 1 5 speciation Tan to Tx unless oterse nated Parameter B Version Units Conditions Comments STATIC PERFORMANCE CHP 1 No Missing C odes 24 Bits min Output N oise and U pdate Rates See T ables amp 11 Integral N onlinearity 18 ppm of FSR max Offset Error See N ote 3 Offset Error and Offset D rift Refer to Both Offset D rift vs T emperature 5 nV C typ U nipolar Offset and Bipolar Zero Errors Offset D rift vs T ime 25 nV 1000 H ours typ Positive F ull Scale Error 5 See Note 3 Positive ull Scale D rift vs T emp 9 7 2 ppm 5 max Positive F ull Scale D rift vs T ime 10 ppm of FS 1000 H ours typ Gain Error 8 See Note 3 Gain D rift vs T emperature 6 9 2 ppm C max Gain Drift vs T ime 10 ppm 1000 H ours typ Bipolar N egative Full Scale Error See N ote 3 N egative Full Scale D rift vs T emp 6 2 ppm 5 max Power Supply Rejection 120 dB typ easured with Zero Differential Voltage Common M ode Rejection CM R 120 dB min At DC easured with Zero Differential Voltage Analog Input DC Bias Current 50 nA ma
37. parameters in the design it is recom mended that the user enable chopping on the part If the input signal is dc excited the user has the option of operating the part in either chop or nonchop mode If the input signal is ac excited both the ac bit and the CH P bit must be set to 1 T he chop rate on the ACX and ACX signals is one half of the programmed output rate of the part and thus the chopping frequency varies with the programmed output rate D elay Selection Bits T hese four bits program the delay in modulator cycles to be inserted after each chop edge when the CHP bit is 1 One modulator cycle is M CLK IN 16 and is 3 25 us at MCLK IN 4 9152 M Hz A delay should only be required when in ac mode Its purpose is to cater for external delays between the switching signals AC X and ACX and when the analog inputs are actually switched and settled D uring the specified number of cycles between 0 and 15 the modulator is held in reset and the filter does not accept any inputs If CHP 1 the output rate is IN 16x DL 3xSF where DL is the value loaded to bits DLO DL3 T he chop rate is always one half of the output rate T his chop period takes into account the programmed delay and the fact that the sinc filter must settle every chop cycle With CHP 0 the output rate is 1 SF REV A 19 AD7730 AD7730L DAC Register RS2 RS0 1 0 0 Power On Reset Status 20 Hex The DAC Register is an 8 bit register fro
38. shot read or write operations once the subsequent read or write operation to the selected register is complete the interface returns to where it expects a write op eration to the Communications Register T his is the default state of the interface and on power up or after a RESET the AD 7730 is in this default state waiting for a write operation to the Communications Register In situations where the interface sequence is lost a write operation of at least 32 serial clock cycles with DIN high returns the AD 7730 to this default state by resetting the part T able VI outlines the bit designations for the Communications Register CRO through CR7 indicate the bit location CR denot ing the bits are in the Communications Register C R 7 denotes the first bit of the data stream TableVI Communications Register CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Bit Bit Location Mnemonic Description CR7 WEN Write Enable Bit A 0 must be written to this bit so the write operation to the Communications Register actually takes place If a 1 is written to this bit the part will not clock on to subsequent bits in the register It will stay at this bit location until a 0 is written to this bit Once a 0 is writ ten to the WEN bit the next seven bits will be loaded to the Communications R egister CR6 ZERO A zero must be written to this bit to ensure correct operation of the AD 7730 CR5 CR4 RW1 Read W rite M ode Bits T hesetwo bits determine the natur
39. to V max DVpp Voltage 2 7 to 45 25 V min to V max WithAGND 0V Power Supply Currents External MCLK Digital I Ps 0 V or DVpp AV pp Current N ormal M ode 10 3 mA max All Input Ranges Except 0 mV to 10 mV and 10 mV AV pp Current N ormal M ode 22 3 mA max Input Ranges of 0 mV to 10 mV and 10 mV Only DVpp Current N ormal M ode 1 3 mA max DVpp of 2 7 V to 3 3 V DVpp Current N ormal M ode 2 7 mA max DVpp of 4 75 V to 5 25 V AVpp DVpp Current Standby M 25 LA max Typically 10 uA External IN 20V or DV pp Power Dissipation AV pp DVpp 5 V Digital I PS 0 V or DVpp N ormal M ode 65 mW max All Input Ranges Except 0 mV to 10 mV and 10 mV 125 mW max Input Ranges of 0 mV to 10 mV and 10 mV Only Standby M ode 125 uW max Typically 50 uW External CLK IN 20V or DVpp REV A 3 AD7730 AD7730L NOTES 1T emperature range 40 C to 85 C 2Sample tested during initial release he offset or zero numbers with CHP 1 are typically 3 uV precalibration Internal zero scale calibration reduces this by about 1 uV Offset numbers with 0 can be up to 1 mV precalibration Internal zero scale calibration reduces this to 2 pV typical System zero scale calibration reduces offset numbers with CHP 1 and CHP 0 to the order of the noise Gain errors can be up to 3000 ppm precalibration with 0 and CHP 1 Performing internal full scale calibrations on the 80 mV range reduces the gain error to le
40. to the device CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchro nization signal in communicating with the AD 7730 20 RDY Logic Output U sed as a status output in both conversion mode and calibration mode In conversion mode a logic low on this output indicates that a new output word is available from the AD 7730 data register T he RDY pin will return high upon completion of a read operation of a full output word If no data read has taken place after an output update the RDY line will return high prior to the next output update remain high while the update is taking place and return low again T his gives an indication of when a read operation should not be initiated to avoid initiating a read from the data register as it is being updated In calibration mode RDY goes high when calibration is initiated and it returns low to indicate that calibration is complete A number of different events on the AD 7730 set the RDY high and these are outlined in T able X VIII 21 DOUT Serial D ata Output with serial data being read from the output shift register on the part T his output shift register can contain information from the calibration registers mode register status register filter register DAC register or data register depending on the register selection bits of the Communications Register 22 DIN Serial D ata Input with serial data being written to the input shift register on the pa
41. wired to a logic high The AD 7730 is not capable of full duplex operation If the AD 7730 is configured for a write operation no data appears on the DAT A OUT lines even when the SCLK input is active When the AD 7730 is configured for continuous read operation data presented to the part on the DATA IN lineis monitored to determine when to exit the continuous read mode DVpp DVpp 68HC11 Figure 20 AD7730 to 68HC11 Interface AD 7730 to 8051 Interface An interface circuit between the AD 7730 and the 8X C51 mi crocontroller is shown in Figure 21 T he diagram shows the minimum number of interface connections with CS on the AD 7730 hardwired low In the case of the 8X C 51 interface the minimum number of interconnects is just two In this scheme the RDY bit of the Status Register is monitored to determine when the D ata Register is updated T he alternative scheme which increases the number of interface lines to three is to monitor the RDY output line from the AD 7730 T he monitor ing of the RDY line can be done in two ways First RDY can be connected to one of the 8X C51 s port bits such as P 1 0 which is configured as an input T his port bit is then polled to deter mine the status of RDY T he second scheme is to use an inter rupt driven system in which case the RDY output is connected to the INT1 input of the 8X C51 For interfaces that require control of the CS input on the AD 7730 one of the port bits of the 8X
42. within the converter depends primarily upon the temperature tracking of the internal capacitors It is not affected by leakage currents When operating the part in CHOP mode CHP 1 the signal chain including the first stage filter is chopped T his chopping reduces the overall offset drift to 5 nV C Integral and differen tial linearity errors are not significantly affected by temperature changes Care must also be taken with external drift effects in order to achieve optimum drift performance T he user has to be espe cially careful to avoid as much as possible thermocouple effects from junctions of different materials D evices should not be placed in sockets when evaluating temperature drift there should be no links in series with the analog inputs and care must be taken as to how the input voltage is applied to the input pins T he true offset drift of the AD 7730 itself can be evaluated by performing temperature drift testing of the part with the AIN AIN input channel arrangement i e internal shorted input test mode USING THE AD7730 Clocking and Oscillator Circuit The AD 7730 requires a master clock input which may be an external CM OS compatible clock signal applied to the M CLK IN pin with OUT pin left unconnected Alternatively a crystal or ceramic resonator of the correct frequency can be connected between M CLK IN and MCLK OUT in which case the clock circuit will function as an oscillator pro
43. 0 or 10 mV nom Gain 250 0 to 20 or 20 mV nom Gain 125 0 to 40 or 40 mV nom Gain 62 5 0 to 80 or 80 mV nom Gain 31 25 Absolute C ommon M ode Voltage AGND 1 2V V min AV pp 0 95 V V max Reference Input REF IN REF IN Voltage 2 5 V nom HIREF Bit of M Register 0 REF IN REF IN Voltage 5 V nom HIREF Bit of Mode Register 1 Absolute Common M ode Voltage 3 AGND 30 mV V min AV pp 30 mV V max NO REF Trigger Voltage 0 3 V min NO REF Bit Active If Vagr Below T his Voltage 0 65 V max NO REF Bit Inactive If Vage Above T his Voltage REV A 45 AD7730 AD7730L Parameter B Version Units Conditions C omments LOGIC INPUTS Input Current 10 uA max All Inputs Except SCLK and M CLK IN Vini Input Low Voltage 0 8 V max DVpp 45V Vini Input Low Voltage 0 4 V max DVpp 3 V Vina Input High Voltage 2 0 V min SCLK Only Schmitt T rigerred Input Vr 1 4 3 V min to V max DVpp 45V 12 5 V to V DVpp 3 V 0 8 1 4 V to V DVpp 5 V Vi 0 4 1 1 V min to V max DVpp 3 0 4 0 8 V to V DVpp 45V V 0 4 0 8 V min to V max DVpp 3 IN Only Vini Input Low Voltage 0 8 V max DVpp 5 V Vini Input Low Voltage 0 4 V max DVpp 3 V Vina Input High Voltage 3 5 V min DVpp 5 V Vinn Input High Voltage 2 5 V min DVpp 43V LOGIC OUTPUTS Including MCLK OUT Vor Output Low Volt
44. 3 140 5 6 70 80 FREQUENCY Hz Figure 11 Detailed Full Frequency Response of AD7730 Second Stage Filter as Normal FIR Chop Enabled Figure 12 shows the frequency response for the same set of conditions as for Figure 11 but in this case the response is shown out to 600 H z T his response shows that the attenuation of input frequencies close to 200 H z and 400 H z is significantly less than at other input frequencies T hese peaks in the fre quency response are a by product of the chopping of the input T he plot of Figure 12 is the amplitude for different input fre quencies N ote that because the output rate is 200 H z for the conditions under which F igure 12 is plotted if something ex isted in the input frequency domain at 200 Hz it would be aliased and appear in the output frequency domain at dc GAIN dB 0 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY Hz Figure 12 Expanded Full Frequency Response of AD7730 Second Stage Filter as Normal FIR Chop Enabled 27 AD7730 AD7730L Because of this effect care should be taken in choosing an out put rate that is close to the line frequency in the application If the line frequency is 50 Hz an output update rate of 50 Hz should not be chosen as it will significantly reduce the AD 7730 s line frequency rejection the 50 H z will appear as a dc effect with only 6 dB attenuation Choosing an output rate
45. 45 INDEX iusso ace iex et kayaspa eR e 50 OUTLINE DIMENSIONS 51 TABLE INDEX Table Title Page Table 1 Output N oise vs Input Range and Update Rate CH P 1 10 T ablell Peak to P eak Resolution vs Input Range and U pdate Rate CHP 1 10 Table lll Output N oise vs Input Range and Update Rate CH P 0 11 Table IV Peak to Peak Resolution vs Input Range and Update Rate CH P 0 11 Table V Summary of On C hip Registers 12 Table VI Communications R egister 13 T able VII Read W rite M ode 13 T able VIII Register Selection 14 Table lX Status Register 14 Table X M ode Register 15 Table XI Operating M odes 15 Table XII Input Range Selection 17 Table XIII Channel Selection 18 Table XIV Filter Register 18 Table XV SF Ranges 19 Table XVI DAC Register 20 TableXVII Calibration Operations 22 Table XVIII Reset Events 23 Table XIX Pseudo C ode for Initiating a Self C alibration after P ower O n R eset 37 Table XX Pseudo C ode for Setting Up AD 7730 for Continuous Conversion and Continuous Read Operation 37 Table XXI Output N oise vs Input Range and Update Rate CHP 1 48 Table XXII Peak to Peak Resolution vs Input Range and U pdate Rate CH P 1 48 Table XXIII Output Noise vs Input Range and Update Rate CH P 0 49 TableXXIV Peak to Peak Resolution vs Input Range and U pdate Rate CH P 0 49 50 REV A AD7730 AD7730L OUTLINE DIMENSIONS Dimensions shown in inches and mm
46. 7730 cs TOP VIEW Not to Scale 18 STANDBY AGND AVpp AIN1 ACX ACX REF IN AIN1 REF IN AIN2 DO AIN2 D1 PIN FUNCTION DESCRIPTIONS No Mnemonic Function 1 SCLK Serial Clock Schmitt T riggered Logic Input An external serial clock is applied to this input to transfer serial data to or from the AD 7730 T his serial clock can be a continuous clock with all data transmitted in a con tinuous train of pulses Alternatively it can be a noncontinuous clock with the information being transmitted to or from the AD 7730 in smaller batches of data 2 MCLK IN M aster Clock signal for the device T his can be provided in the form of a crystal resonator or external clock A crystal resonator can be tied across the MCLK IN and MCLK OUT pins Alternatively the MCLK IN pin can be driven with a CM OS compatible clock and OUT left unconnected T he AD 7730 is specified with a clock input frequency of 4 9152 M Hz while the AD 77301 is specified with a clock input frequency of 2 4576 M Hz REV A 7 AD7730 AD7730L Pin No Mnemonic Function 3 11 12 13 14 15 16 17 MCLK OUT SYNC AIN1 AIN2 D1 AIN2 DO REF IN REF IN ACX ACX When the master clock for the device is a crystal resonator the crystal resonator is connected between M CLK IN and M CLK OUT If an external clock is applied to the M CLK IN MCLK
47. AL NOMINAL ZERO SCALE POINT ZERO SCALE CALIBRATIONS LLL INPUT RANGE UP OR DOWN LOWER LIMIT AD7730 s OS XFS VOLTAGE CANNOT EXCEED THIS Figure 16 Span and Offset Limits Power Up and Calibration On power up the AD 7730 performs an internal reset which sets the contents of the internal registers to a known state T here are default values loaded to all registers after a power on or reset The default values contain nominal calibration coefficients for the calibration registers T o ensure correct calibration for the device a calibration routine should be performed after power up 32 T he power dissipation and temperature drift of the AD 7730 are low and no warm up time is required before the initial calibra tion is performed If however an external reference is being used this reference must have stabilized before calibration is initiated Similarly if the clock source for the part is generated from a crystal or resonator across the M C L K pins the start up time for the oscillator circuit should elapse before a calibration is initiated on the part see below Drift Considerations T he AD 7730 uses chopper stabilization techniques to minimize input offset drift Charge injection in the analog multiplexer and dc leakage currents at the analog input are the primary sources of offset voltage drift in the part T he dc input leakage current is essentially independent of the selected gain Gain drift
48. ANALOG DEVICES Bridge Transducer ADC AD7730 AD7730L KEY FEATURES Resolution of 230 000 Counts Peak to Peak Offset Drift 5 nV C Gain Drift 2 Line Frequency Rejection 2150 dB Buffered Differential Inputs Programmable Filter Cutoffs Specified for Drift Over Time Operates with Reference Voltages of 1 V to 5 V ADDITIONAL FEATURES Two Channel Programmable Gain Front End On Chip DAC for Offset TARE Removal FASTStep Mode AC or DC Excitation Single Supply Operation APPLICATIONS Weigh Scales Pressure Measurement GENERAL DESCRIPTION TheAD7730 is a complete analog front end for weigh scale and pressure measurement applications T he device accepts low level signals directly from a transducer and outputs a serial digital word T he input signal is applied to a proprietary pro grammable gain front end based around an analog modulator The modulator output is processed by a low pass programmable digital filter allowing adjustment of filter cutoff output rate and settling time T he part features two buffered differential programmable gain analog inputs as well as a differential reference input T he part operates from a single 5 V supply It accepts four unipolar analog input ranges 0 mV to 10 mV 20 mV 40 mV and 80 mV and four bipolar ranges 10 mV 20 mV 40 mV and 80 mV T he peak to peak resolution achievable directly from the part is 1 in 230 000 counts An on chip 6 bit DAC allows t
49. C51 such as P1 1 which is configured as an output can be used to drive the CS input T he 8X C51 is configured in its M ode 0 serial interface mode Its serial interface contains a single data line As a result the DATA OUT and DATA IN pins of the AD 7730 should be connected together T his means that the AD 7730 must not be REV A AD7730 AD7730L configured for continuous read operation when interfacing to the 8X C51 T he serial clock on the 8X C51 idles high between data transfers and therefore the POL input of the AD 7730 should be hardwired to a logic high T he 8X C51 outputs the LSB first in a write operation while the AD 7730 expects the M SB first so the data to be transmitted has to be rearranged before being written to the output serial register Similarly the AD 7730 outputs the M SB first during a read operation while the 8X C51 expects the LSB first T herefore the data read into the serial buffer needs to be rearranged before the correct data word from the AD 7730 is available in the accumulator n RESET POL AD7730 Figure 21 AD7730 to 8XC51 Interface REV A AD 7730 to ADSP 2103 AD SP 2105 Interface Figure 22 shows an interface between the AD 7730 and the ADSP 2105 DSP processor In the interface shown the RDY bit of the Status Register is again monitored to determine when the D ata Register is updated T he alternative scheme is to use an interrupt driven system in which case the RDY output i
50. CAN BE SELECTED TO BE NOMINALLY 2 5V 5V THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS FOUR UNIPOLAR AND FOUR BIPOLAR INPUT RANGES FROM 10mV TO 80mV SEE PAGE 24 SEE PAGE 25 AD7730 SIGMA DELTA MODULATOR SERIAL INTERFACE AND CONTROL LOGIC CALIBRATION MICROCONTROLLER O O AGND DGND OFFSET TARE DAC SIGMA DELTA A D CONVERTER PROGRAMMABLE DIGITAL FILTER CLOCK GENERATION PROGRAMMABLE SIGMA DELTA ADC DIGITAL FILTER THE SIGMA DELTA ARCHITECTURE ENSURES 24 BITS NO MISSING CODES THE ENTIRE SIGMA DELTA ADC CAN BE CHOPPED TO REMOVE DRIFT ERRORS TWO STAGE FILTER THAT ALLOWS PROGRAMMING OF OUTPUT UPDATE RATE AND SETTLING TIME AND WHICH HAS A FAST STEP MODE SEE FIGURE 3 SEE PAGE 26 SEE PAGE 26 STANDBY MODE THE STANDBY MODE REDUCES POWER CONSUMPTION TO 5pA SEE PAGE 33 O STANDBY CLOCK OSCILLATOR CIRCUIT THE CLOCK SOURCE FOR THE PART CAN BE PROVIDED BY AN EXTERNALLY APPLIED CLOCK OR BY CONNECTING A CRYSTAL OR CERAMIC RESONATOR ACROSS THE CLOCK PINS SEE PAGE 32 SERIAL INTERFACE SPI COMPATIBLE OR DSP COMPATIBLE SERIAL INTERFACE WHICH CAN BE OPERATED FROM JUST THREE WIRES ALL FUNCTIONS ON THE PART CAN BE ACCESSED VIA THE SERIAL INTERFACE SEE PAGE 35 REGISTER BANK FOR AC EXCITED BRIDGE APPLICATIONS THE ACX OUTPUTS PROVIDE SIGNALS THAT CAN BE USED TO SWITCH THE POLARITY OF THE BRIDGE EXCITATION VOLTAGE THE SECOND ANALOG INPUT CHA
51. D OPERATION WRITE BYTE Z TO COMMUNICATIONS REGISTER SEE ACCOMPANYING TABLE Figure 5 Flowchart for Reading from the AD7730 Registers Register Byte Y Hex Communications R egister 00 WRITE BYTE Y TO Data Register Read Only Register SEE ACCOMPANYING TABLE Ape DAC Register 04 WRITE TO REGISTER Offset R egister 05 Gain Register 06 T est Register User is advised not to change contents of T est R egister Figure 6 Flowchart for Writing to the AD7730 Registers REV A 21 AD7730 AD7730L CALIBRATION OPERATION SUMMARY The AD7730 contains a number of calibration options as outlined previously T able X VII summarizes the calibration types the operations involved and the duration of the operations T here are two methods of determining the end of calibration T he first is to monitor the hardware RDY pin using either interrupt driven or polling routines T he second method is to do a software poll of the RDY bit in the Status Register T his can be achieved by setting up the part for continuous reads of the Status R egister once a calibra tion has been initiated The RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration routine At this time the M D2 M D1 M DO bits of the M ode Register have returned to 0 0 0 The FAST and SK IP bits are treated as 0 for the calibration sequence so the full filter is always used for the calibration routines See Calibration section
52. D 7730 It is then clocked into the input shift register on the next rising edge of SCLK For POL 0 the first clock edge that clocks data from the microcontroller onto theDIN line of the AD 7730 is a rising edge It is then clocked into the input shift register on the next falling edge of SCLK In other microcontroller applications which require a decoding of the AD 7730 CS can be generated from a port line In this case CS would go low well in advance of the first falling edge of SCLK POL 1 or the first rising edge of SCLK POL 0 Clocking of each bit of data is as just described In DSP applications the SCLK is generally a continuous clock In these applications the CS input for the AD 7730 is generated from a frame synchronization signal from the D SP For proces sors with the rising edge of SCLK as the active edge the POL input should be tied high For processors with the falling edge of SCLK asthe active edge the POL input should be tied low In these applications the first edge after CS goes low is the active edge T he M SB of the data to be shifted into the AD 7730 must be set up prior to this first active edge Read Operation T he reading of data from the part is from an output shift regis ter On initiation of a read operation data is transferred from the specified register to the output shift register T his is a paral lel shift and is transparent to the user Figure 19 shows a timing diagram for a read operation
53. D of the AD 7730 must be biased negative with respect to system ground so the analog input voltage does not go within 1 2 V of AGND Care should taken to ensure that the differential between either AV pp or DVpp and this biased AGND does not exceed 5 5 V T his is discussed in more detail in the Applications section Programmable Gain Amplifier T he output from the buffer amplifier is summed with the output of the 6 bit Offset DAC before it is applied to the input of the on chip programmable gain amplifier PGA The PGA can handle four different unipolar input ranges and four bipolar ranges With the HIREF bit of the M ode Register at 0 and a 42 5 V reference or the HIREF bit at 1 and a 5 V reference the unipolar ranges are 0 mV to 10 mV 0 mV to 20 mV 0 mV to 40 mV and 0 mV to 80 mV while the bipolar ranges are 10 mV 20 mV 40 mV and 80 mV T hese are the nominal ranges that should appear at the input to the on chip PGA 24 Offset DAC T he purpose of the Offset DAC isto either add or subtract an offset so the input range at the input to the PGA is as close as possible to the nominal If the output of the 6 bit Offset DAC is 0 V the differential voltage ranges that appear at the analog input to the part will also appear at the input to the PGA If however the Offset DAC has an output voltage other than 0 V the input range to the analog inputs will differ from that applied to the input of the PGA T he Offset DAC
54. H owever care must be taken in this scheme to ensure that the REF IN voltage does not exceed AV pp and that the REF IN voltage does not go below AGND SIGMA PROGRAMMABLE DELTA DIGITAL MODULATOR FILTER cec STANDBY Tu MCLK IN SERIAL INTERFACE AND CONTROL LOGIC CALIBRATION MICROCONTROLLER l Rum C H Figure 25 AD7730 with Bipolar Excitation of the Bridge 42 REV A APPENDIX A AD 7730L SPECIFICATIONS 43 ANALOG DEVICES LOW POWER BRIDGE TRANSDUCER ADC KEY FEATURES Resolution of 110 000 Counts Peak to Peak Power Consumption 15 mW typ Offset Drift lt 1 ppm C Gain Drift 3 Line Frequency Rejection gt 150 dB Buffered Differential Inputs Programmable Filter Cutoffs Specified for Drift Over Time Operates with Reference Voltages of 1 V to 5 V ADDITIONAL FEATURES Two Channel Programmable Gain Front End On Chip DAC for Offset TARE Removal FASTStep Mode AC or DC Excitation Single Supply Operation APPLICATIONS Portable Weigh Scales APPENDIX AD7730L GENERAL DESCRIPTION TheAD7730L is a complete low power analog front end for weigh scale and pressure measurement applications T he device accepts low level signals directly from a transducer and outputs a serial digital word T he input signal is applied to a proprietary programmable gain front end based around an analog modula tor T
55. LK OUT signal is buffered with a CM OS buffer before being applied to the rest of the circuit System Synchronization The SYNC input allows the user to reset the modulator and digital filter without affecting any of the setup conditions on the part T his allows the user to start gathering samples of the ana log input from a known point in time i e the rising edge of SYNC If multiple AD 7730s are operated from a common master clock they can be synchronized to update their output registers simul taneously A falling edge on the SYNC input resets the digital filter and analog modulator and places the AD 7730 into a con sistent known state Whilethe SYNC input is low the AD 7730 will be maintained in this state On the rising edge of SYNC the modulator and filter are taken out of this reset state and on the next clock edge the part starts to gather input samples again In a system using multiple AD 7730s a common signal to their SYNC inputs will synchronize their operation T his would nor mally be done after each AD 7730 has performed its own cali bration or has had calibration coefficients loaded to it T he output updates will then be synchronized with the maximum possible difference between the output updates of the individual AD 7730s being one M CLK IN cycle Single Shot Conversions The SYNC input can also be used as a start convert command allowing the AD 7730 to be operated in a conventional converter fashion In this mode
56. N Only Vini Input Low Voltage 0 8 V max DVpp 5 Vini Input Low Voltage 0 4 V max DVpp 43V Viny Input High Voltage 3 5 V min DVpp 45V Vinx Input High Voltage 2 5 V min DVpp 3 LOGIC OUTPUTS Including MCLK OUT Vor Output Low Voltage Isink 800 pA Except for MCLK OUT 14 0 4 V max VppP 45V Output Low Voltage Isink 100 pA Except for MCLK OUT 14 0 4 V max VppP 43V Output High Voltage Isource 200 pA Except for OUT 4 0 V min Vpop 45V Output High Voltage Isource 100 pA Except for OUT Vpp 0 6 V V min Vbo 43V Floating State L eakage Current 10 pA max Floating State Output C apacitance 6 pF typ TRANSDUCER BURNOUT AIN1 4 Current 100 nA nom AIN 1 Current 100 nA nom Initial T olerance 25 10 Yo typ Drift 0 1 typ OFFSET TARE DAC Resolution 6 Bit LSB Size 2 3 2 6 mV min mV max 2 5 mV Nominal with 5 V Reference REF IN 2000 DAC Drift 2 5 max DAC Drift vs Time 16 25 ppm 1000 H ours typ Differential Linearity 0 25 0 75 LSB max Guaranteed M onotonic SYSTEM CALIBRATION Positive Full Scale Calibration Limit 1 05 x FS V max FS 15 the Nominal Full Scale Voltage 10 mV 20 mV 40 mV or 80 mV N egative ull Scale Calibration Limit 1 05 x FS V max Offset Calibration Limit 1 05 x FS V max Input Span 0 8xFS V min 2 1xFS V max POWER REQUIREMENTS Power Supply Voltages AVpp AGND Voltage 4 75 to 5 25 V min
57. ND RESOLUTION SPEGIFICAT ION te trepido t e nt 10 ON CHIP REGISTERS 11 Summary Of On Chip Registers 12 Communications Register 13 Status Register 14 Data Register 15 Mode Register 15 Filter Register 18 DAC lt 20 Offset Calibration Register 20 Gain Calibration Register 20 Test Register ice eod e MON Otro pe deutet 20 READING FROM AND WRITING TO THE ON CHIP REGISTERS 21 CALIBRATION OPERATION SUMMARY 22 CIRCUIT DESCRIPTION nmm RR Hee 23 1 24 Analog Input Channels 24 Analog Input Ranges 24 Bipolar Unipolar Inputs 24 Burnout lt 5 25 REFERENCE INPUT 25 Reference Detect 25 SIGMA DELTA MODULATOR 26 DIGITAL FILTERING 26 Filter Architecture 26 First Stage Filter 26 Second Stage Filter 27 CALIBRATION I r ulus ana tid ae aes
58. NGE T his is the range of voltages that the AD 7730 can accept in the system calibration mode and still calibrate full scale correctly INPUT SPAN In system calibration schemes two voltages applied in sequence to the AD 7730 s analog input define the analog input range T he input span specification defines the minimum and maxi mum input voltages from zero to full scale the AD 7730 can accept and still accurately calibrate gain AD7730 AD7730L OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7730 can be programmed to operate in either chop mode or nonchop mode T he chop mode can be enabled in ac excited or dc excited applications it is optional in dc excited applications but chop mode must be enabled in ac excited applications T hese options are discussed in more detail in later sections T he chop mode has the advantage of lower drift numbers and better noise im munity but the noise is approximately 20 higher for a given 3 dB frequency and output data rate It is envisaged that the majority of weigh scale users of the AD 7730 will operate the part in chop mode to avail themselves of the excellent drift performance and noise immunity when chopping is enabled T he following tables outline the noise performance of the part in both chop and nonchop modes over all input ranges for a selection of output rates Settling time refers to the time taken to get an output that is 100 settled to new value Output Noise CHP 1 T his mode is t
59. NNEL CAN BE RECONFIGURED TO BECOME TWO OUTPUT DIGITAL PORT LINES WHICH CAN BE PROGRAMMED ALLOWS A PROGRAMMED VOLTAGE TO BE EITHER ADDED OR SUBTRACTED FROM THE ANALOG INPUT SIGNAL BEFORE IT IS APPLIED TO THE PGA THIRTEEN REGISTERS CONTROL ALL FUNCTIONS ON THE PART AND PROVIDE STATUS INFORMATION AND CONVERSION RESULTS OVER THE SERIAL INTERFACE SEE PAGE 11 SEE PAGE 24 SEE PAGE 41 SEE PAGE 33 SPI IS A TRADEMARK OF MOTOROLA INC Figure 2 Detailed Functional Block Diagram REV A AD7730 AD7730L INPUT CHOPPING SINC3 FILTER SKIP MODE 22 TAP FIR FILTER THE ANALOG INPUT TO THE PART CAN BE THE FIRST STAGE OF THE DIGITAL FILTERING IN SKIP MODE THERE IS NO SECOND IN NORMAL OPERATING MODE THE CHOPPED IN CHOPPING MODE WITH 3 SECOND STAGE OF THE DIGITAL FILTERING AE DYE ATO QNTHEPARTIGTHESNCSFILTER THE STAGE OF FILTERNG ON THE PART THe ON STAAR pi CHOPPING IS INTERNALTO THE DEVICE IN OF THIS FILTER CAN BE PROGRAMMED IN PERFORMED ON THE PART FILTER IN SKIP MODE THIS FIR FILTER IS CHOPPING MODE WITH AC EXCITATION SKIP MODE THE SINC FILTER IS THE BYPASSED WHEN FASTSTEP MODE IS ENABLED THE CHOPPING IS ASSUMED ONLY FILTERING PERFORMED ON THE PART SEE PAGE BB ENABLED AND A STEP INPUT IS TO BE PERFORMED EXTERNAL TO THE PART DETECTED THE SECOND STAGE FILTERING AND NO INTERNAL INPUT CHOPPING IS SEE PAGE de IS PERFORMED BY THE FILTER PERFORMED THE INPUT CHOPPING CAN UNTIL
60. R 1 2 OP213 ALL VOLTAGE VALUES ARE WITH RESPECT TO SYSTEM GROUND SYSTEM GROUND a minimum of 1 2 V The 10 V excitation voltage must be re duced to 5 V before being applied as the reference voltage for the AD 7730 T he resistor string RI R2 and R3 takes the 10 V excitation voltage and generates differential voltage of nominally 5 V Amplifiers A1 and A2 buffer the resistor string voltages and provide the AV pp and AGND voltages as well as the REF IN and REF IN voltages for the AD 7730 T he differential reference voltage for the part is 5 V The AD 7730 retains its ratiometric operation with this reference voltage varying in sym pathy with the analog input voltage T he values of the resistors in the resistor string can be changed to allow a larger D Vpp voltage F or example if R1 3 R2 10 and 7 the AV pp and AGN D voltages become 3 5 V and 1 5 V respectively T his allows the AD 7730 to be used with a 3 6 V DVpp voltage while still allowing the analog input range to be within the specified common mode range An alternate scheme to this is to generate the AV pp and AGND voltages from regulators or Zener diodes driven from the 5 V and 5 V supplies respectively T he reference voltage for the part would be generated in the same manner as just outlined but amplifiers A1 and A2 would not be required to buffer the volt ages as they are now only driving the reference pins of the AD 7730
61. SCLK signal Write Operation T he transfer of data into the part is to an input shift register On completion of a write operation data is transferred to the speci fied register T his internal transfer will not take place until the correct number of bits for the specified register have been loaded to the input shift register For example the transfer of data from the input shift register takes place after eight serial clock cycles for a DAC Register write while the transfer of data from the input shift register takes place after 24 serial clock cycles when writing to the Filter Register Figure 18 shows timing diagram for a write operation to the input shift register of the AD 7730 With the POL input at a logic high the data is latched into the input shift register on the rising edge of SCLK With the POL input at a logic low the data is latched into the input shift register on the falling edge of SCLK Figure 18 also shows the CS input being used to decode the write operation to the AD 7730 H owever this CS input can be used in a number of different ways It is possible to operate the part in three wire mode where the CS input is tied low perma nently In this case the SCLK line should idle high between REV A data transfer when the POL input is high and should idle low between data transfers when the POL input is low For POL 1 the first falling edge of SCLK clocks data from the microcontrol ler onto the DIN line of the A
62. THE OUTPUT OF THIS FILTER BE DISABLED IF DESIRED HAS FULLY SETTLED SEE PAGE 26 SEE PAGE 27 SKIP PGA a ANALOG o CHOP SIGMA DELTA L SINC FILTER CHOP 22 TAP OUTPUT O DIGITAL INPUT MODULATOR FIR FILTER SCALING OUTPUT FASTSTEP FILTER OUTPUT SCALING THE OUTPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT BUFFER PGA SIGMA DELTA MODULATOR OUTPUT CHOPPING THE INPUT SIGNAL IS BUFFERED THE PROGRAMMABLE GAIN CAPABILITY THE OUTPUT OF THE FIRST STAGE ON CHIP BEFORE BEING APPLIED TO OF THE PART IS INCORPORATED OF FILTERING ON THE PART CAN THE SAMPLING CAPACITOR OF THE AROUND THE SIGMA DELTA MODULATOR BE CHOPPED IN CHOPPING MODE SIGMA DELTA MODULATOR THIS THE MODULATOR PROVIDES A HIGH REGARDLESS OF WHETHER AC ISOLATES THE SAMPLING CAPACITOR FREQUENCY 1 BIT DATA STREAM EXCITATION IS ENABLED OR DISABLED CHARGING CURRENTS FROM THE TO THE DIGITAL FILTER THE OUTPUT CHOPPING IS ANALOG INPUT PINS PERFORMED THE CHOPPING CAN SEE PAGE 26 BE DISABLED IF DESIRED SEE PAGE 29 FASTSTEP FILTER WHEN FASTSTEP MODE IS ENABLED AND A STEP CHANGE ON THE INPUT HAS BEEN DETECTED THE SECOND SEE PAGE 24 SEE PAGE 26 STAGE FILTERING IS PERFORMED BY THE FASTSTEP FILTER UNTIL THE FIR FILTER HAS FULLY SETTLED SEE PAGE 29 Figure 3 Signal Processing Chain PIN CONFIGURATION SCLK DGND MCLK IN DVpp MCLK OUT DIN POL DOUT SYNC RDY RESET AD
63. able range for SF words depends on whether the part is operated with CHOP on or off and SKIP on or off T able XV outlines the SF ranges for different setups All output update rates will be one half those quoted in T able XV for the AD 7730L operating with a 2 4576 M Hz clock 18 REV A AD7730 AD7730L Table XV SF Ranges CHOP SKIP SF Range Output U pdate Rate Range Assuming 4 9152 MHz Clock 150 Hz to 2 048 kHz 50 Hz to 1 365 kHz 150 Hzto 7 6 kHz 50 Hzto 5 12 kHz 2048 to 150 2048 to 75 2048 to 40 2048 to 20 Bit Location Bit Mnemonic Description FR11 FR10 FR9 FR7 FR6 FR5 FR3 FRO ZERO SKIP FAST ZERO AC DL3 DLO A zero must be written to these bits to ensure correct operation of the AD 7730 FIR Filter Skip Bit With a 0 in this bit the AD 7730 performs two stages of filtering before shipping a result out of the filter T he first is a sinc filter followed by a 22 tap FIR filter With a lin this bit the FIR filter on the part is bypassed and the output of the sinc is fed directly as the output result of the AD 7730 s filter see Filter Architecture for more details on the filter implementation FASTStep M ode Enable Bit A 1 in this bit enables the FASTStep mode on the AD 7730 In this mode if a step change on the input is detected the FIR calculation portion of the filter is suspended and replaced by a simple movi
64. about 500 ppm on the 10 mV range System full scale calibration reduces this to the order of the noise Positive and negative full scale errors can be calculated from the offset and gain errors T hese numbers are generated during life testing of the part 5Positive Full Scale Error includes Offset Errors U nipolar Offset Error or Bipolar Zero Error and applies to both unipolar and bipolar input ranges Recalibration at any temperature will remove these errors TF ull Scale Drift includes Offset D rift Unipolar Offset D rift or Bipolar Zero Drift and applies to both unipolar and bipolar input ranges 8Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function T he two points used to calculate the gain error are positive full scale and negative full scale See T erminology Gain Error D rift is a span drift and is effectively the drift of the part if zero scale calibrations only were performed 10N o Missing Codes performance with CH P 0 and SKIP 1 is reduced below 24 bits for SF words lower than 180 decimal HThe analog input voltage range on the AIN 1 and AIN 2 inputs is given here with respect to the voltage on the AIN 1 and AIN 2 inputs respectively 12T he common mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed PT he common mode voltage range on the reference input pair REF IN and REF IN
65. age Isinx 800 uA Except for CLK OUT 0 4 V max Vop 4 5 V Vot Output Low Voltage Isink 100 pA Except for M CLK OUT 14 0 4 V max 43V Von Output High Voltage Isource 200 uA Except for M OUT 14 4 0 V min VppP 45V Von Output High Voltage Isource 100 pA Except for M CLK OUT 1 Vpp 0 6V V min 43V Floating State L eakage urrent 10 uA max Floating State Output Capacitance 9 pF typ TRANSDUCER BURNOUT AIN1 Current 100 nA nom AIN1 Current 100 nA nom Initial T olerance 25 C 10 typ Drift 0 1 typ OFFSET TARE DAC Resolution 6 Bit LSB Size 2 3 2 6 mV min mV max 2 5 mV Nominal with 5 V Reference REF IN 2000 DAC Drift 3 5 max DAC Drift vs T ime 16 25 ppm 1000 H ours typ Differential L inearity 0 25 0 75 LSB max Guaranteed M onotonic SYSTEM CALIBRATION Positive ull Scale Calibration Limit 1 05 xFS V max FS 15 Nominal F ull Scale Voltage 10 mV 20 mV 40 mV or 80 mV N egative ull Scale C alibration Limit 1 05 xFS V max Offset Calibration Limit 1 05 xFS V max Input Span 0 8 x FS V min 2 1xFS V max POWER REQUIREMENTS Power Supply Voltages AV pp AGND Voltage DVpp Voltage Power Supply Currents AV pp Current Normal M ode AV pp Current N ormal M ode DVpp Current N ormal M ode D Vpp Current Normal M ode AVpp DVpp Current Standby M ode Power Dissipation Normal M ode Standby M ode 4 75 to 45 25 42 7 to 45 25
66. age specification is obeyed PT he common mode voltage range on the reference input pair REF IN and REF IN applies provided the absolute input voltage specification is obeyed MT hese logic output levels apply to the OUT output only when it is loaded with a single CM OS load 15V pp refers to DV pp for all logic outputs expect D 0 D 1 ACX and ACX where it refers to AV pp In other words the output logic high for these four outputs is determined by AV pp 16T his number represents the total drift of the channel with a zero input and the DAC output near full scale After calibration if the input voltage exceeds positive full scale the converter will output all 1s If the input is less than negative full scale the device outputs all Os 18T hese calibration and span limits apply provided the absolute input voltage specification is obeyed T he offset calibration limit applies to both the unipolar zero point and the bipolar zero point Specifications subject to change without notice AVpp 4 75 V to 5 25 V DVpp 2 7 V to 5 25 V AGND DGND 0 V 4 9152 MHz Tl MI NG CHARACTERI 165 2 Input Logic 0 0 V Logic 1 DVpp unless otherwise noted Limit at T m n to Tmax Parameter B Version Units Conditions Comments M aster Clock Range 1 MHzmin For Specified Performance 5 MHz max ty 50 ns min SYNC Pulsewidth t 50 ns min RESET Pulsewidth Read Operation t5 0 ns min RDY to CS Setup T i
67. applications is to provide a single supply solution something that is aided by the AD 7730 s single supply capabil ity some applications provide a bipolar excitation voltage in order to increase the output voltage from the bridge In such cases the input voltage applied to the AD 7730 can be slightly negative with respect to ground Figure 23 shows how to config ure the AD 7730 to handle this type of input signal DC Excitation of Bridge In dc excitation applications the excitation voltage provided for the bridge is a fixed dc voltage C onnections between the AD 7730 and the bridge are very straightforward in this type of applica tion as illustrated in Figure 23 T he bridge configuration shown is a six lead configuration with separate return leads for the reference lines T his allows a force sense effect on the load cell excitation voltage eliminating voltage drops caused by the exci tation current flowing through the lead resistances In applica tions where the lead lengths are short a four wire configuration EXCITATION VOLTAGE 5V ES sssi OUT AIN2 D1 O AIN2 DO L L ACX NNI ACXO AC EXCITATION CLOCK AND CONTROL LOGIC can be used with the excitation voltage and analog ground con nected local to the AD 7730 s REF IN and REF IN termi nals Illustrating a major advantage of the AD 7730 the 5 V excitation voltage for the bridge can
68. applies provided the absolute input voltage specification is obeyed 14T hese logic output levels apply to the M CLK OUT output only when it is loaded with a single CM OS load BV pp refers to D Vpp for all logic outputs expect D 0 D 1 ACX and ACX where it refers to AV pp In other words the output logic high for these four outputs is determined by AV pp 16T his number represents the total drift of the channel with a zero input and the DAC output near full scale After calibration if the input voltage exceeds positive full scale the converter will output all 1s If the input is less than negative full scale the device outputs all 05 18T hese calibration and span limits apply provided the absolute input voltage specification is obeyed T he offset calibration limit applies to both the unipolar zero point and the bipolar zero point Specifications subject to change without notice AVpp 4 75 V to 5 25 V DVpp 3 V to 5 25 V AGND DGND 0 V 2 4576 MHz TI MI NG CHARACTE RISTICS 2 Input Logic 0 0 V Logic 1 DVpp unless otherwise noted Limitat T min to Tmax Parameter B Version Units Conditions C omments M aster Clock Range 1 MHzmin For Specified Performance 5 MHz max ty 50 ns min SYNC Pulsewidth t 50 ns min RESET Pulsewidth Read Operation t 0 ns min RDY to CS Setup Time t4 0 ns min CS Falling Edge to SCLK Active Edge Setup T ime t 0 ns min SCLK Active Edge to Data Valid Delay 60 ns max
69. ate Rates See Tables XXIII amp XXIV Integral N onlinearity 22 ppm of FSR max Offset Error See Note 3 Offset Error and Offset D rift Refer to Both Offset D rift vs T emperature 0 5 uV C typ Unipolar Offset and Bipolar Zero Errors Offset D rift vs T imet 2 5 uV 1000 H ours typ Positive F ull Scale Error See N ote 3 Positive Full Scale D rift vs T emp 7 0 6 typ Positive Full Scale D rift vs Time 3 uV 1000 H ours typ Gain Error See N ote 3 Gain Drift vs T emperature 2 ppm C typ Gain Drift vs Time 10 ppm 1000 H ours typ Bipolar N egative Full Scale Error See N ote 3 N egative F ull Scale Drift vs T emp 0 6 typ Power Supply Rejection 90 dB typ M easured with Zero Differential Voltage Common M ode Rejection CMR on AIN 105 dB typ At DC Measured with Zero Differential Voltage CMR on REF IN 100 dB typ At DC Measured with Zero Differential Voltage Analog Input DC Bias Current 50 nA max Analog Input DC Bias Current D rift 150 pA C typ Analog Input DC Offset C urrent 25 nA max Analog Input DC Offset Current Drift 75 typ ANALOG INPUTS REFERENCE INPUTS N ormal M ode 50 Hz Rejection 88 dB min From 49 Hzto 51Hz N ormal M ode 60 H z Rejection 88 dB min From 59 Hzto 61Hz Common M ode 50 H z Rejection 120 dB min From 49 Hzto 51Hz Common M ode 60 H z Rejection 120 dB min From 59 Hzto 61 Hz Analog Inputs D ifferential Input Voltage Ranges Assuming 2 5 V or 5 V Reference with HIREF Bit Set Appropriately Oto 1
70. ating range to optimize the post calibration gain error T his calibration should be followed by either an Internal Zero Scale or System Zero Scale calibration T his zero scale calibration should be performed at the operating input range Calibration on externally applied input voltage with PGA set for selected input range T he input applied is assumed to be the zero scale of the system If ac 1 the system continues to use ac excitation for the duration of the calibration For full system calibration this System Zero Scale calibration should be performed first F or applications which require a System Zero Scale and Internal Full Scale calibration this calibration should be preceded by the Internal Full Scale calibration T he Offset Calibration Register for the selected channel is updated at the end of this calibration sequence Calibration on externally applied input voltage with PGA set for selected input range T he input applied is assumed to be the full scale of the system If ac 1 the system continues to use ac excitation for the duration of the calibration T his calibration should be preceded by a System Zero Scale or Internal Zero Scale calibration T he Gain Calibration Register for the selected channel is updated at the end of this calibration sequence 22 REV A AD7730 AD7730L CIRCUIT DESCRIPTION The AD7730 isasigma delta A D converter with on chip digital filtering intended for the measurement of wide
71. be used directly as the refer ence voltage for the AD 7730 eliminating the need for precision matched resistors in generating a scaled down reference T he application is a ratiometric one with variations in the exci tation voltage being reflected in variations in the analog input voltage and reference voltage of the AD 7730 Because the AD 7730 is a truly ratiometric part with the reference voltage and excitation voltages equal it is possible to evaluate its total excitation voltage rejection T his is unlike other converters which give a separate indication of the rejection of reference analog inputs and power supply T he combined total rejection for the AD 7730 when moving the excitation voltage which was also the power supply voltage was better than 115 dB when evaluated with a load cell simulator Drift considerations are a primary concern for load cell applica tions It is recommended for these applications that the AD 7730 is operated in CH OP mode to accrue the benefits of the excel lent drift performance of the part in CHOP mode A common source of unwanted drift effects are parasitic thermocouples T hermocouple effects are generated every time there is a junc tion of two dissimilar metals All components in the signal path should be chosen to minimize thermocouple effects C sockets and link options should be avoided as much as possible While it is impossible to remove all thermocouple effects attempts should be made to
72. cond Stage Filter as Normal FIR Chop Disabled 28 T he 3 dB frequency for the frequency response of the AD 7730 with the second stage filter set for normal FIR operation and chop mode enabled is determined by the following relationship 1 fap 0 CLK IN 0 039 x 16 Xe In this case 7 8 Hz and the stop band where the attentua tion is greater than 64 5 dB is determined by fork in 1 f 0 14 zii lt 16 SF In this case 28 Hz Figure 14 shows the frequency response for the same set of conditions as for Figure 13 but in this case the response is shown out to 600 H z T his plot is comparable to that of F igure 12 T he most notable difference is the absence of the peaks in the response at 200 H z and 400 Hz As a result interference at these frequencies will be effectively eliminated before being aliased back to dc GAIN dB 0 50 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY Hz Figure 14 Expanded Full Frequency Response of AD7730 Second Stage Filter as Normal FIR Chop Disabled REV A AD7730 AD7730L FASTStep Mode T he second mode of operation of the second stage filter is in FASTStep mode which enables it to respond rapidly to step inputs This FASTStep mode is enabled by placing a 1 in the FAST bit of the Filter Register If the FAST bit is 0 the part continues to process step inputs with the
73. crystal oscillator or ceramic resonator across the M CLK IN and M CLK OUT pins the AD 7730 clock is stopped and no conversions take place when the CLKDIS bit is active REV A 17 AD7730 AD7730L Bit Bit Location Mnemonic Description MR2 BO Burnout Current Bit A 1 in this bit activates the burnout currents W hen active the burnout currents connect to the selected analog input pair one source current to the AIN input and one sink current to the AIN input 0 in this bit turns off the on chip burnout currents MRI MRO CH1 CHO Channel Selection Bits T hese bits select the analog input channel to be converted or calibrated as outlined in T able XIII With CH 1 at 1 and CHO at 0 the part looks at the AIN 1 input internally shorted to itself T his can be used as a test method to evaluate the noise performance of the part with no external noise sources In this mode the AIN 1 input should be connected to an external voltage within the allowable common mode range of the part T he Offset and Gain Calibration R egisters on the part are paired T here are three pairs of calibration registers labelled Register Pair 0 through Regis ter Pair 2 T hese are assigned to the input channel pairs as outlined in T able XIII Table XIII Channel Selection Input Channel Pair CH1 CHO Positive Input Negative Input Calibration Register Pair 0 0 AIN 1 AIN 1 Register Pair 0 0 1 AIN 2 AIN 2 Registe
74. d by the AD 7730 s clock the AD 7730 produces an uninterrupted master clock during RESET commands Standby Mode The STANDBY input on the AD 7730 allows the user to place the part in a power down mode when it is not required to pro vide conversion results T he part can also be placed in its standby mode by writing 0 1 1 to theM D2 MD1 bits of the M ode Register T he AD 7730 retains the contents of all its on chip registers including the D ata Register while in standby mode D ata can still be read from the part in Standby M ode T he ST BY bit of the Status Register indicates whether the part is in standby or normal operating mode When the STANDBY pin is taken high the part returns to operating as it had been prior to the STANDBY pin going low The STANDBY input or 0 1 1 theM D2 MD1 MDO bits does not affect the digital interface It does however set the RDY bit and pin high and also sets the STDY bit high When STANDBY goes high again RDY and STDY remain high until set low by a conversion or calibration Placing the part in standby mode reduces the total current to 10 pA typical when the part is operated from an external master clock provided this master clock is stopped If the external clock continues to run in standby mode the standby current increases to 400 pA typical If a crystal or ceramic resonator is used as the clock source then the total current in standby mode is 400 pA typical T his is because t
75. d to the voltage on the respective AIN input For example if AIN is 2 5 V and the AD 7730 is configured for an analog input range of 0 to 10 mV with no DAC offset correction the input voltage range on the AIN input is 42 5 V to 2 51 V Similarly if AIN is 2 5 V and the AD 7730 is configured for an analog input range of 80 mV with no DAC offset correction the analog input range on the AIN input is 2 42 V to 2 58 V i e 2 5 V 80 mV Bipolar or unipolar options are chosen by programming the B U bit of the M ode Register T his programs the selected channel for either unipolar or bipolar operation Programming the chan nel for either unipolar or bipolar operation does not change any of the input signal conditioning it simply changes the data output coding and the points on the transfer function where calibrations occur When the AD 7730 is configured for unipolar operation the output coding is natural straight binary with a zero differential voltage resulting in a code of 000 000 midscale voltage resulting in a code of 100 000 and a full scale input voltage resulting in a code of 111 111 When the AD 7730 is configured for bipolar operation the coding is offset binary with a negative full scale voltage resulting in a code of 000 000 a zero differential voltage resulting in a code of 100 000 and a positive full scale voltage resulting in a code of 111 111 REV A Burnout Currents
76. dynamic range low frequency signals such as those in weigh scale strain gage pressure transducer or temperature measurement applications It contains a sigma delta or charge balancing a calibra tion microcontroller with on chip static RAM a clock oscillator a digital filter and a bidirectional serial communications port T he part consumes 13 mA of power supply current with a standby mode which consumes only 25 uA T he part operates from a single 5 V supply T he clock source for the part can be provided via an external clock or by connecting a crystal oscillator or ceramic resonator across the M CLK IN and M CLK OUT pins T he part contains two programmable gain fully differential analog input channels T he part handles a total of eight different input ranges which are programmed via the on chip registers T here are four differential unipolar ranges 0 mV to 10 mV 0 mV to 20 mV 0 mV to 40 mV and 0 mV to 80 mV and four differen tial bipolar ranges 10 mV 20 mV 40 mV and 80 mV T he AD 7730 employs a sigma delta conversion technique to realize up to 24 bits of no missing codes performance T he sigma delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital informa tion A digital low pass filter processes the output of the sigma delta modulator and updates the data register at a rate that can be programmed over the serial interface T he output data from t
77. e Register When the analog input channel is switched the RDY output goes high and the settling time of the part must elapse before a valid word from the new channel is available in the D ata R egis ter indicated by RDY going low Buffered Inputs T he output of the multiplexer feeds into a high impedance input stage of the buffer amplifier As a result the analog inputs can handle significant source impedances T his buffer amplifier has an input bias current of 50 nA CHP 1 and 60nA CHP 0 T his current flows in each leg of the analog input pair T he offset current on the part is the difference between the input bias on the legs of the input pair T his offset current is less than 10 nA CHP 1 and 30 nA CHP 0 Large source resis tances result in a dc offset voltage developed across the source resistance on each leg but matched impedances on the analog input legs will reduce the offset voltage to that generated by the input offset current Analog Input Ranges T he absolute input voltage range is restricted to between AGND 1 2 V to AV pp 0 95 V which also places restrictions on the common mode range Care must be taken in setting up the common mode voltage and input voltage range so these limits are not exceeded otherwise there will be a degradation in linearity performance In some applications the analog input range may be biased either around system ground or slightly below system ground In such cases the AGN
78. e of the filter has elapsed 0 1 1 Power D own Standby M ode In this mode the AD 7730 goes into its power down or standby state Placing the part in this mode is equivalent to exerting the STANDBY input pin However exerting STANDBY does not actually force these mode bits to 0 1 1 1 0 0 Zero Scale Self C alibration M ode T his activates zero scale self calibration on the channel selected by CH1 and CHO of the M ode Register T his zero scale self calibration is performed at the selected gain on internally shorted zeroed inputs W hen this zero scale self calibration is complete the part updates the contents of the appropriate Offset C alibration Register and returns to Sync M ode with M D2 M D1 and M DO returning to 0 0 0 T he RDY output and bit go high when calibration is initiated and return low when this zero scale self calibration is complete to indicate that the part is back in Sync M ode and ready for further operations 1 0 1 Full Scale Self Calibration M ode T his activates full scale self calibration on the channel selected by CH 1 and CHO of the M ode Register T his full scale self calibration is performed at the selected gain on an internally generated full scale signal When this full scale self calibration is complete the part updates the contents of the appropriate G ain Calibration Register and Offset Calibration Register and returns to Sync M ode with M D2 M D1 and M D 0 returning to 0 0 0 T he RDY output and bit go h
79. e of the subsequent read write opera tion T able VII outlines the four options Table VII Read Write Mode RW1 RW0 Read Write Mode Single Write to Specified R egister Single Read of Specified R egister Start Continuous Read of Specified Register Stop Continuous Read M ode With 0 0 written to these two bits the next operation is a write operation to the register specified by bits RS2 RS1 RS0 Once the subsequent write operation to the specified register has been com pleted the part returns to where it is expecting a write operation to the Communications R egister With 0 1 written to these two bits the next operation is a read operation of the register specified by bits RS2 RS1 RSO Once the subsequent read operation to the specified register has been completed the part returns to where it is expecting a write operation to the Communications Register Writing 1 0 to these bits sets the part into a mode of continuous reads from the register speci fied by bits RS2 RS1 RSO T he most likely registers with which the user will want to use this function are the D ata Register and the Status Register Subsequent operations to the part will consist of read operations to the specified register without any intermediate writes to the C om munications Register T his means that once the next read operation to the specified register has taken place the part will be in a mode where it is expecting a
80. e plot of Figure 10 where the output rate is 600 Hz fork in 4 9152 M Hz and SF 512 the first notch of the filter is at 600 Hz T he notches of this sinc filter are repeated at multiples of the first notch T he filter provides attenuation of better than 100 dB at these notches Programming a different cutoff frequency via SFO SF 11 does not alter the profile of the filter response it changes the fre quency of the notches as outlined in the F ilter Registers section T his response is repeated at either side of the input sampling frequency 307 kH z and at either side of multiples of the input sampling frequency GAIN dB 200 400 600 800 1000 1200 1400 1600 1800 FREQUENCY Hz Figure 10 Frequency Response of First Stage Filter T he first stage filter has two basic modes of operation T he primary mode of operation for weigh scale applications is chop mode which is achieved by placing a 1 in the CHP bit of the Filter Register T he part should be operated in this mode when drift and noise rejection are important criteria in the application T he alternative mode of operation is the nonchop mode with CHP at 0 which would be used when higher throughput rates are a concern or in applications where the reduced rejection at the chopping frequency in chop mode is an issue Nonchop Mode With chop mode disabled on the AD 7730 the first stage filter continuously processes input
81. ected span T herefore in determining the limits for sys tem zero scale and full scale calibrations the user has to ensure that the offset range plus the span range does exceed 1 05 x FS T his is best illustrated by looking at a few examples If the part is used in unipolar mode with a required span of 0 8 x FS the offset range the system calibration can handle is from 1 05 x FS to 0 25 x FS If the part is used in unipolar mode with a required span of F S the offset range the system cali bration can handle is from 1 05 x FS to 0 05 x FS Similarly if the part is used in unipolar mode and required to remove an offset of 0 2 x FS the span range the system calibration can handle is 0 85 x FS If the part is used in bipolar mode with a required span of 0 4 x FS the offset range the system calibration can handle is from 0 65 x FS to 40 65 x FS If the part is used in bipolar mode with a required span of F S the offset range the system calibration can handle is from 0 05 x FS to 0 05 x FS Simi larly if the part is used in bipolar mode and required to remove an offset of 0 2 x FS the span range the system calibration can handle is 0 85 x FS Figure 16 summarizes the span and offset ranges 1 05 x FS c UPPER LIMIT AD7730 s INPUT VOLTAGE CANNOT EXCEED THIS GAIN CALIBRATIONS CONTRACT THE AD7730 s INPUT AD7730 RANGE INPUT RANGE 0 8 x FS TO 2 1 x FS 0V DIFFERENTI
82. el selection bits Controls the amount of averaging in the first stage filter selects the fast step and skip modes and con trols the ac excitation and chopping modes on the part Provides control of the amount of correction per formed by the Offset T ARE DAC Contains a 24 bit word which is the offset calibration coefficient for the part T he contents of this register are used to provide offset correction on the output from the digital filter T here are three Offset R egis ters on the part and these are associated with the input channels as outlined in T able XIII Contains a 24 bit word which is the gain calibration coefficient for the part T he contents of this register are used to provide gain correction on the output from the digital filter T here are three G ain Registers on the part and these are associated with the input channels as outlined in T able XIII Controls the test modes of the part which are used when testing the part The user is advised not to change the contents of this register REV A AD7730 AD7730L Communications Register RS2 RS0 0 0 0 The Communications Register is an 8 bit write only register All communications to the part must start with a write operation to the Communications Register T he data written to the Communications Register determines whether the next operation is a read or write operation the type of read operation and to which register this operation takes place F or single
83. er Setting N ext O peration as Write to M ode Register Write 2180 H ex to Serial Port f Writes to M ode Register Starting Continuous Conversions for 0 mV to 10 mV Input Range Write 21 H ex to Serial Port Writes to Communications Register Setting N ext Operation as Continuous Read From D ata R egister Set DIN Line of AD7730 Low f Ensures Part is not Reset While in Continuous Read M ode READ DATA Wait for RDY Low Wait for RD Y pin to go low to Indicate Output U pdate Read 24 Bit Data From Serial Port Read Conversion Result from AD 7730 s D ata Register Loop to READ DATA Until All Data Gathered Write 30 Hex to Serial Port f Ends Continuous R ead Operation and Places Part in M ode Where It Expects Write to Communications R egister REV A 37 AD7730 AD7730L MICROCOMPUTER MICROPROCESSOR INTERFACING The AD7730 s flexible serial interface allows for easy interface to most microcomputers and microprocessors T he pseudo code of T able XIX and T able outline typical sequences for inter facing a microcontroller or microprocessor to the AD 7730 Figures 20 21 and 22 show some typical interface circuits T he serial interface on the AD 7730 has the capability of operat ing from just three wires and is compatible with SPI interface protocols T he three wire operation makes the part ideal for isolated systems where minimizing the number of interface lines minimizes the number of opto isolators required in the sys
84. essive output is from reverse chopping polarities CALIBRATION The AD 7730 provides a number of calibration options which can be programmed via the M D2 M D1 and bits of the M ode Register T he different calibration options are outlined in the M ode Register and Calibration Operations sections A cali bration cycle may be initiated at any time by writing to these bits of the M ode Register Calibration on the AD 7730 removes offset and gain errors from the device The AD 7730 gives the user access to the on chip calibration registers allowing the microprocessor to read the device s cali bration coefficients and also to write its own calibration coeffi cients to the part from prestored values 2 T his gives the microprocessor much greater control over the AD 7730 s calibration procedure It also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in E PROM T he values in these calibration registers are 24 bits wide In addition the span and offset for the part can be adjusted by the user 29 AD7730 AD7730L Internally in the AD 7730 the coefficients are normalized before being used to scale the words coming out of the digital filter T he offset calibration register contains a value which when normalized is subtracted from all conversion results T he gain calibration register contains a value which
85. fferential reference input to the AD 7730 The REF IN poten tial can lie anywhere between AV pp and AGND Digital Output Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications When ACX is high the bridge excitation is taken as normal and when ACX is low the bridge excitation is reversed chopped If AC 0 ac mode turned off or CHP 0 chop mode turned off the ACX output remains high Digital Output Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications T his output is the complement of AC X In ac mode this means that it toggles in anti phase with ACX If AC 0 ac mode turned off or CH P 0 chop mode turned off theACX output remains low When toggling it is guaranteed to be nonoverlapping with ACX T he non overlap interval when both ACX and ACX are low is one master clock cycle 8 REV A AD7730 AD7730L Pin No Mnemonic Function 18 STANDBY Logic Input T aking this pin low shuts down the analog and digital circuitry reducing current consumption to the 5 uA range T he on chip registers retain all their values when the part is in standby mode 19 CS Chip Select Active low Logic Input used to select the AD 7730 With this input hardwired low the AD 7730 can operate in its three wire interface mode with SCLK DIN and DOUT used to interface
86. g input range for the selected analog input T he dif ferent input ranges are outlined in T able XII T he table is valid for a reference voltage of 5 V with the HIREF bit at 1 or for a reference voltage of 2 5 V with the HIREF bit at a logic 0 Table XII Input Range Selection Input Range B U Bit 0 Bit 1 10 mV to 10 mV 20 mV to 20 mV 40 mV to 40 mV 0 mV to 40 mV 80 mV to 80 mV 0 mV to 80 mV 0 mV to 10 mV 0 mV to 4 20 mV Power O n R eset D efault Note that the input range given in the above table is the range that appears at the input of the PGA after the D AC offset value has been applied If the DAC adjusts out no offset DAC Register is 0010 0000 then this is also the input voltage range at the analog input pins If for example the DAC sub tracts out 50 mV of offset and the part is being operated in bipolar mode with RN 1 and RNO at 0 0 the actual input voltage range at the analog input is 40 mV to 60 mV M aster Clock Disable Bit A 1 in the bit disables the master clock from appearing at the M CLK OUT pin When disabled the M CLK OUT pin is forced low It allows the user the flexibility of using the CLK OUT asa clock source for other devices in the system or of turning off the M CLK OUT asa power saving feature When using an external master clock at the CLK IN pin the AD 7730 contin ues to have internal clocks and will convert normally with the CLK DIS bit active When using a
87. hardware and software events that set or reset status flags and bits in registers T able XVIII summarizes which blocks and flags are affected by the different events Table XVIII Reset E vents Set Registers Mode Filter Analog Reset Serial Set RDY Se STDY Event to Default Bits Reset Power Down Interface Pin Bit Bit Power On Reset Y es 000 Y es Y es Y es Y es Yes RESET Pin Y es 000 Y es No Y es Yes Y es STANDBY Pin No 515 Yes Yes No Yes Yes Mode 011 Write No 011 Yes Yes No Yes Yes SYNC Pin No 515 Yes No No Yes Yes M ode 000 Write No 000 Yes No No Yes Yes Conversion or No N ew Initial No No Yes Yes Cal M ode Write Value Reset Clock 32 1s Yes 000 Yes No Yes Y es Yes D ata Register R ead No 515 No No No Yes No REV A 23 AD7730 AD7730L ANALOG INPUT Analog Input Channels The AD7730 contains two differential analog input channels a primary input channel AIN 1 and a secondary input channel AIN2 T he input pairs provide programmable gain differential channels which can handle either unipolar or bipolar input signals It should be noted that the bipolar input signals are referenced to the respective AIN input of the input pair T he secondary input channel can also be reconfigured as two digital output port bits A two channel differential multiplexer switches one of the two input channels to the on chip buffer amplifier T his multiplexer is controlled by the CH 0 and CH 1 bits of the M od
88. has five magnitude bits and one sign bit T he sign bit determines whether the value loaded to the five magni tude bits is added to or subtracted from the voltage at the ana log input pins Control of the Offset DAC is via theDAC Register which is discussed previously in the On C hip Registers section With a 5 V reference applied between the REF IN pins the resolution of the Offset DAC is 2 5 mV with a range that allows addition or subtraction of 77 5 mV With a 2 5 V refer ence applied between the REF IN pins the resolution of the Offset DAC is 1 25 mV with a range that allows addition or subtraction of 38 75 mV Following is an example of how the Offset DAC works If the differential input voltage range the user had at the analog input pins was 20 mV to 30 mV the Offset DAC should be pro grammed to subtract 20 mV of offset so the input range to the PGA is 0 mV to 10 mV If the differential input voltage range the user had at the analog input pins was 60 mV to 20 mV the Offset DAC should be programmed to add 20 mV of offset so the input range to the PGA is 40 mV Bipolar Unipolar Inputs T he analog inputs on the AD 7730 can accept either unipolar or bipolar input voltage ranges Bipolar input ranges do not imply that the part can handle negative voltages with respect to system ground on its analog inputs unless the AGND of the part is also biased below system ground U nipolar and bipolar signals on the AIN input are reference
89. he ideal AIN voltage AIN 0 5 LSB when operating in the bipolar mode GAIN ERROR T his is a measure of the span error of the ADC It is a measure of the difference between the measured and the ideal span be tween any two points in the transfer function T he two points used to calculate the gain error are full scale and zero scale REV A This is the deviation of the first code transition from the ideal AIN voltage AIN Vage GAIN 0 5 LSB when operat ing in the bipolar mode N egative full scale error is a summation of zero error and gain error POSITIVE FULL SCALE OVERRANGE Positive ull Scale O verrange is the amount of overhead avail able to handle input voltages on AIN input greater than AIN Vagr GAIN for example noise peaks or excess volt ages due to system gain errors in system calibration routines with out introducing errors due to overloading the analog modulator or overflowing the digital filter NEGATIVE FULL SCALE OVERRANGE T his is the amount of overhead available to handle voltages on AIN below AIN Vage GAIN without overloading the analog modulator or overflowing the digital filter OFFSET CALIBRATION RANGE In the system calibration modes the AD 7730 calibrates its offset with respect to the analog input T he Offset Calibration Range specification defines the range of voltages the AD 7730 can accept and still accurately calibrate offset FULL SCALE CALIBRATION RA
90. he modulator output is processed by a low pass program mable digital filter allowing adjustment of filter cutoff output rate and settling time T he part features two buffered differential programmable gain analog inputs as well as a differential reference input T he part operates from a single 5 V supply and typically consumes less than 3 mA It accepts four unipolar analog input ranges 0 mV to 10 mV 20 mV 40 mV and 80 mV and four bipolar ranges 10 mV 20 mV 40 mV and 80 mV T he peak to peak resolution achievable directly from the part is 1 in 110 000 counts An on chip 6 bit DAC allows the removal of T ARE voltages Clock signals for synchronizing ac excitation of the bridge are also provided T he serial interface on the part can be configured for three wire operation and is compatible with microcontrollers and digital signal processors T he AD 7730L contains self calibration and system calibration options and features an offset drift of less than 5 nV C and a gain drift of less than 3 T he part is available in a 24 lead SOIC and 24 lead TSSOP package FUNCTIONAL BLOCK DIAGRAM AVpp DVpp VBIAS O AIN1 O AIN1 AIN2 D1 AIN2 DO Protected by U S Patent No 5 134 401 Other Patent Applications Filed REF INC REFIN O O STANDBY SIGMA PROGRAMMABLE pa DELTA DIGITAL Q SYNC MODULATOR FILTER O MCLK IN CLOC SERIAL INTERFACE Q MCLK OUT AND CONTROL LOGIC
91. he on chip oscillator circuit continues to run when the part is in its standby mode T his is important in applications where the system clock is provided by the AD 7730 s clock so that the AD 7730 produces an uninterrupted master clock even when it is in its standby mode Digital Outputs The AD 7730 has two digital output pins DO and D 1 When the DEN bit of the M ode Register is set to 1 these digital outputs assume the logic status of bits DO and D 1 of the M ode Register It gives the user access to two digital port pins which can be programmed over the normal serial interface of the AD 7730 The two outputs obtain their supply voltage from AV pp thus the outputs operate to 5 V levels even in cases where DVpp 43V 33 AD7730 AD7730L POWER SUPPLIES T here is no specific power sequence required for the AD 7730 either the AV pp or the DVpp supply can come up first While the latch up performance of the AD 7730 is very good it is important that power is applied to the AD 7730 before signals at REF IN AIN or the logic input pins in order to avoid latch up caused by excessive current If this is not possible the current that flows in any of these pins should be limited to less than 30 mA per pin and less than 100 mA cumulative If separate sup plies are used for the AD 7730 and the system digital circuitry the AD 7730 should be powered up first If it is not possible to guarantee this current limiting resi
92. he part is accessed over this serial interface T he cutoff frequency and output rate of this filter can be programmed via on chip registers T he output noise performance and peak to peak reso lution of the part varies with gain and with the output rate as shown in T ables to IV T he analog inputs are buffered on chip allowing the part to handle significant source impedances on the analog input T his means that external C filtering for noise rejection or RFI reduction can be placed on the analog inputs if required Both analog channels are differential with a common mode voltage range that comes within 1 2 V of AGND and 0 95 V of AVpp T he reference input is also differential and the common mode range here is from AGND to AVpp T he part contains a 6 bit DAC that is controlled via on chip registers T his DAC can be used to remove T ARE values of up to 80 mV from the analog input signal range T he resolution on this function is 1 25 mV for a 42 5 V reference and 2 5 mV with a 5 V reference T he AD 7730 can accept input signals from a dc excited bridge It can also handle input signals from an ac excited bridge by using the ac excitation clock signals AC X and ACX to switch the supplies to the bridge ACX and ACX are nonoverlapping clock signals used to synchronize the external ac supplies that drive the transducer bridge T hese ACX clocks are demodulated on the AD 7730 input The AD 7730 contains a number of
93. he primary mode of operation of the device T able shows the output rms noise for some typical output update rates and 3 dB frequencies for the AD 7730 when used in chopping mode C H P of Filter Register 1 with a master clock frequency of 4 9152 M Hz T hese numbers are typical and are generated at a differential analog input voltage of 0 V T he output update rate is selected via the SF 0 to SF 11 bits of the Filter Register T able ll meanwhile shows the output peak to peak resolution in counts for the same output update rates T he numbers in brackets are the effective peak to peak resolution in bits rounded to the nearest 0 5 LSB It is important to note that the numbers in T able II represent the resolution for which there will be no code flicker within a six sigma limit T hey are not calculated based on rms noise but on peak to peak noise The numbers are generated for the bipolar input ranges W hen the part is operated in unipolar mode the output noise will be the same as the equivalent bipolar input range As a result the numbers in T able will remain the same for unipolar ranges while the numbers in T able II will change T o calculate the numbers for T able 11 for unipolar input ranges simply divide the peak to peak resolution number in counts by two or subtract one from the peak to peak resolution number in bits Tablel Output Noise vs Input Range and Update Rate CHP 1 Typical Output RMS Noise in nV Output 3dB SF Se
94. he removal of T ARE voltages Clock signals for synchro nizing ac excitation of the bridge are also provided T he serial interface on the part can be configured for three wire operation and is compatible with microcontrollers and digital signal processors T he AD 7730 contains self calibration and system calibration options and features an offset drift of less than 5 nV C and a gain drift of less than 2 The 7730 is available in a 24 pin plastic DIP a 24 lead SOIC and 24 lead T SSOP package T he AD 7730L is available in a 24 lead SOIC and 24 lead T SSOP package NOTE T he description of the functions and operation given in this data sheet apply to both the AD 7730 and AD 7730L Specifications and performance parameters differ for the parts Specifications for the AD 7730L are outlined in Appendix A FUNCTIONAL BLOCK DIAGRAM AVpp DVpp O O VBIASO AIN1 AIN1 AIN2 D10 AIN2 DO RH REF IN REF IN O REFERENCE basse SERIAL INTERFACE AD7730 SIGMA DELTA A D CONVERTER STANDBY SIGMA PROGRAMMABLE DELTA DIGITAL MODULATOR FILTER t SYNC CLOCK O MCLK IN GENERATION MCLK OUT AND CONTROL LOGIC FAST Step is a trademark of Analog D evices Inc REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements
95. hemselves to adjust the part s zero scale point only When performing a two step full calibra tion care should be taken as to the sequence in which the two Steps are performed If the system zero scale calibration is one part of a full system calibration then it should take place before a system full scale calibration If it takes place in association with an internal full scale calibration then this system zero scale calibration should be performed after the full scale calibration REV A System Full Scale Calibration A system full scale calibration is initiated on the AD 7730 by writing the appropriate values 1 1 1 to the M D2 1 and M DO bits of the M ode Register System full scale calibration is performed using the system s positive full scale voltage T his full scale voltage must be set up before the calibration is initi ated and it must remain stable throughout the calibration step T he system full scale calibration is performed at the selected gain as per the RN 1 RNO bits in the M ode Register The calibration is performed with either ac or dc excitation depending on the status of the ac bit T he duration time of the calibration depends upon the C H P bit of the F ilter Register With CHP 1 the duration is 22 x 1 Output Rate with CHP 0 the duration is 24 x 1 Output Rate At this time the M D2 MD1 and MDO bits in the M ode Register return to 0 0 0 Sync or Idle M ode for the AD 7730 T he RDY line goes
96. high when calibration is initiated and returns low when calibration is complete N ote that the part has not performed a conversion at this time it has simply performed a full scale calibration and updated the Gain Calibration Register for the selected channel T he user must write either 0 0 1 or 0 1 Oto the M D2 MD 1 M DO bits of the M ode R egister to initiate a conversion If RDY 15 low before or goes low during the calibration command write to the M ode R egister it may take up to one modulator cycle M IN 32 before RDY goes high to indicate that calibration is in progress T herefore RDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the M ode Register T he system full scale calibration needs to be performed as one part of a two part full calibration O nce a full calibration has been performed however additional system full scale calibra tions can be performed by themselves to adjust the part s gain calibration point only When performing a two step full calibra tion care should be taken as to the sequence in which the two steps are performed A system full scale calibration should not be carried out unless the part contains valid zero scale coeffi cients T herefore an internal zero scale calibration or a system zero scale calibration must be performed before the system full scale calibration when a full two step calibration operation is being performed
97. igh when calibration is initiated and return low when this full scale self calibration is complete to indicate that the part is back in Sync M ode and ready for further operations 1 1 0 Zero Scale System Calibration M ode T his activates zero scale system calibration on the channel selected by CH1 of the M ode Register Calibration is performed at the selected gain on the input volt age provided at the analog input during this calibration sequence T his input voltage should remain stable for the duration of the calibration When this zero scale system calibration is complete the part updates the contents of the appropriate ffset Calibration Register and returns to Sync M ode with M D2 MD1 and M DO returning to 0 0 0 The output and bit go high when calibration is initiated and return low when this zero scale calibration is complete to indicate that the part is back in Sync M ode and ready for further operations 1 1 1 Full Scale System Calibration M ode T his activates full scale system calibration on the selected input channel Calibration is performed at the selected gain on the input voltage provided at the analog input during this calibration sequence T his input voltage should remain stable for the duration of the calibra tion When this full scale system calibration is complete the part updates the contents of the appropriate Gain Calibration Register and returns to Sync M ode with M D2 MD1 and M DO returning to 0 0
98. ister RS2 RSO 0 1 0 Power On Reset Status 01BO Hex The M ode Register is a 16 bit register from which data can be read or to which data can be written T his register configures the operating modes of the AD 7730 the input range selection the channel selection and the word length of the D ata Register Table X outlines the bit designations for the M ode Register M RO through M R15 indicate the bit location M R denoting the bits are in the M ode Register M R15 denotes the first bit of the data stream T he number in brackets indicates the power on reset default status of that bit Figure 5 shows a flowchart for reading from the registers on the AD 7730 and Figure 6 shows a flowchart for writ ing to the registers on the part Table X Mode Register M R15 M R14 M R13 MR12 MR11 M R10 MR9 M R8 MR7 MR6 5 MR4 MR3 MR2 1 HIREF 1 ZERO 0 LKDIS 0 0 cu1 0 CHO 0 Bit Bit Location Mnemonic Description MR15 MR13 MD2 MDO M ode Bits T hese three bits determine the mode of operation of the AD 7730 as outlined in T able XI The modes are independent such that writing new mode bits to the M ode R egister will exit the part from the mode in which it is operating and place it in the new requested mode immediately after the M ode Register write T he function of the mode bits is described in more detail below Table XI Operating Modes Mode of Operation Sync Idle M ode Power O n Reset D efault C
99. ister Read Only 16 Bits or 24 Bits 000000 H ex M ode Register Read Write 16 Bits 01B0 Hex MD2 MD1 BU DEN D1 DO WL HIREF ZERO RN1 RNO CLKDIS BO CH1 CHO Filter Register Read Write 24 Bits 200010 H ex SFII SF10 SF9 SF8 SF7 SF6 SF5 SF4 SF3 SF2 SF1 SFO ZERO ZERO SKIP FAST ZERO ZERO AC DL2 DLI DLO DAC Register Read Write 8 Bits 20 Hex ZERO ZERO DAC5 DAC4 DAC3 DAC2 DAC1 DACO Offset R egister Read Write 24 Bits 800000 H ex Gain Register Read Write 24 Bits 59AEE7 Hex T est Register Read Write 24 Bits 000000 H ex 12 All operations to other registers are initiated through the Communications Register T his controls whether subsequent operations are read or write operations and also selects the register for that subsequent operation M ost subsequent operations return con trol to the Communications Register except for the continuous read mode of operation Provides status information on conversions calibra tions settling to step inputs standby operation and the validity of the reference voltage Provides the most up to date conversion result from the part Register length can be programmed to be 16 bits or 24 bits Controls functions such as mode of operation uni polar bipolar operation controlling the function of AIN2 D1 and AIN 2 D0 burnout current D ata Register word length and disabling of M C L K OUT It also contains the reference selection bit the range selection bits and the chann
100. lock In these applications the CS input for the AD 7730 is generated from a frame synchronization signal from the D SP In these applications the first edge after CS goes low is the active edge The MSB of the data to be shifted into the D SP must be set up prior to this first active edge U nlike microcontroller applica tions the D SP does not provide a clock edge to clock the M SB from the AD 7730 In this case the CS of the AD 7730 places theMSB onthe DOUT line For processors with the rising edge of SCL K as the active edge the POL input should be tied high In this case the D SP takes data on the rising edge If CS goes low while SCLK islow the M SB isclocked out on the DOU T line from the CS Subsequent data bits are clocked from the falling edge of SCLK For processors with the falling edge of SCLK as the active edge the POL input should be tied low In this case the D SP takes data on the falling edge If CS goes low while SCLK is high the M SB is clocked out on the DOUT line from the CS Subsequent data bits are clocked from the rising edge of SCLK DOUT The RDY line is used as a status signal to indicate when data is ready to be read from the AD 7730 s data register RDY goes low when a new data word is available in the data register It is reset high when a read operation from the data register is com plete It also goes high prior to the updating of the data register to indicate when a read from the data register
101. logic 0 or the digital output function is disabled by writing a 0 to the DEN bit Data Word Length Bit T his bit determines the word length of the D ata Register A 0 in this bit selects 16 bit word length when reading from the data register i e RDY returns high after 16 serial clock cycles in the read operation A 1 in this bit selects 24 bit word length for the D ata Register High Reference Bit T his bit should be set in accordance with the reference voltage which is being used on the part If the reference voltage is 5 V the HIREF bit should be set to 1 If the reference voltage is 2 5 V theHIREF bit should be set to a 0 With the HIREF bit set correctly for the appropriate applied reference voltage the input ranges are 0 mV to 10 mV 20 mV 40 mV and 80 mV for unipolar operation and 10 mV 20 mV 40 mV and 80 mV for bipolar operation Itis possible for a user with a 2 5 V reference to set the HIREF bit to a 1 In this case the part is oper ating with a 2 5 V reference but assumes it has a 5 V reference As a result the input ranges on the part become 0 to 5 mV 10 mV 20 mV and 40 mV for unipolar operation and 5 mV 10 mV 20 mV and 40 mV for bipolar operation H owever the output noise from the part in nV will re main unchanged so the resolution of the part in counts will halve A zero must be written to this bit to ensure correct operation of the AD 7730 Input Range Bits T hese bits determine the analo
102. m which data can either be read or to which data can be written T his register provides the code for the offset compensation D AC on the part T able XVI outlines the bit designations for the DAC Register DRO through DR7 indicate the bit location DR denoting the bits are in the DAC Register DR7 denotes the first bit of the data stream T he number in brackets indicates the power on reset default status of that bit Figure 5 shows a flowchart for reading from the registers on the AD 7730 and Figure 6 shows a flowchart for writing to the registers on the part Table XVI DAC Register DR7 DR6 DR5 DR4 DR3 DR2 DRI DRO ZERO 0 ZERO 0 DAC5 1 DAC4 0 DAC3 0 DAC2 0 DAC1 0 DACO 0 Bit Bit Location Mnemonic Description DR7 DR6 ZERO A zero must be written to these bits to ensure correct operation of the AD 7730 DR5 DRO DAC5 DACO DAC Selection Bits T hese bits program the output of the offset DAC T he DAC is effectively 6 bits with one sign bit D AC5 and five magnitude bits With DAC5 at 1 the DAC output subtracts from the analog input before it is applied to the PGA With DAC5 at 0 theDAC output adds to the analog input before it is applied to the PGA T he DAC output is given by Vagr 62 5 x D 32 Vagr 2000 x D where D is the decimal equivalent of bits DAC4 to DACO T hus for a 5 V reference applied across the REF IN pins theDAC resolution is 2 5 mV and offsets in the range 77 5 mV to 77 5 mV can be removed f
103. me tu 0 ns min CS Falling Edge to SC L K Active Edge Setup T ime t 0 ns min SCLK Active Edge to Data Valid D elay 60 ns max DVpp 4 75 V to 5 25 V 80 ns max DVpp 2 75 V to 3 3 V tsa 5 0 ns min CSFalling Edge to D ata Valid D elay 60 ns max DVpp 4 75 V to 5 25 V 80 ns max DVpp 2 7 V to 3 3 V tc 100 ns min SCLK High Pulsewidth t 100 ns min SCLK Low Pulsewidth tg 0 ns min CS Rising Edge to SCLK Inactive Edge H old Time t 10 ns min Bus Relinquish T ime after SCLK Inactive Edge 80 ns max tio 100 ns max SCLK Active Edge to RDY H igh 7 Write Operation tu 0 ns min CS Falling Edge to SC LK Active Edge Setup T ime 12 30 ns min Data Valid to SCLK Edge Setup T ime 25 ns min Data Valid to SCLK Edge Hold Time tu 100 ns min SCLK High Pulsewidth tas 100 ns min SCLK Low Pulsewidth tie 0 ns min CS Rising Edge to SCLK Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance All input signals are specified with tr tf 5 ns 10 to 90 of DV pp and timed from a voltage level of 1 6 V See F igures 18 and 19 3SCLK active edge is falling edge of SCLK with POL 1 SCLK active edge is rising edge of SCLK with POL 0 T hese numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vo or Vou limits his specification only comes into play if CS goes low while SCLK is low POL 1 or if CS goes low while SCLK 1 high POL 0 Itis primarily re
104. mportant when using high resolution ADCs All analog supplies should be decoupled with 10 uF tantalum in parallel with 0 1 uF ceramic capacitors to AGND T o achieve the best from these decoupling components they have to be placed as close as possible to the device ideally right up against the device All logic chips should be decoupled with 0 1 uF disc ceramic capacitors to DGN D In systems where common supply voltage is used to drive both the AV pp and DV pp of the AD 7730 it is recommended that the system s AV pp supply is used T his supply should have the recom mended analog supply decoupling capacitors between the AV pp pin of the AD 7730 and AGND and the recommended digital supply decoupling capacitor between the D Vpp pin of the AD 7730 Evaluating the AD 7730 Performance A recommended layout for the AD 7730 is outlined in the evalu ation board for the AD 7730 T he evaluation board package includes a fully assembled and tested evaluation board docu mentation software for controlling the board over the printer port of a PC and software for analyzing the AD 7730 s perfor mance on the PC T he evaluation board order number is EVAL AD7730EB N oise levels in the signals applied to the AD 7730 may also affect performance of the part T he AD 7730 allows two tech niques for evaluating the true performance of the part indepen dent of the analog input signal T hese schemes should be used after a calibration has
105. much earlier indication of where the output chan nel is going and its new value T his feature is very useful in weighing applications to give a much earlier indication of the weight or in an application scanning multiple channels where the user does not have to wait the full settling time to see if a channel has changed value SKIP Mode T he final method for operating the second stage filter is where it is bypassed completely T his is achieved by placing a 1 in the SKIP bit of the Filter Register When SKIP mode is enabled it means that the only filtering on the part is the first stage sinc filter As a result the complete filter profile is as described ear lier for the first stage filter and illustrated in Figure 10 In SKIP mode because there is much less processing of the data to derive each individual output the normal mode settling time for the part is shorter As a consequence of the lesser filtering however the output noise from the part will be significantly higher for a given SF word F or example with a 20 mV an SF word of 1536 and CHP 0 the output rms noise increases from 80 nV to 200 nV With a 10 mV input range an SF word of 1024 and CHP 1 the output rms noise goes from 60 nV to 200 nV With chopping disabled and SKIP mode enabled each output from the AD 7730 is a valid result in itself H owever with chop ping enabled and SK IP mode enabled the outputs from the AD 7730 must be handled in pairs as each succ
106. n of the second stage filter are discussed in the following sections along with the different filter profiles which result Normal FIR Operation T he normal mode of operation of the second stage filter is as a 22 tap low pass FIR filter This second stage filter processes the output of the first stage filter and the net frequency response of the filter is simply a product of the filter response of both filters T he overall filter response of the AD 7730 is guaranteed to have no overshoot Figure 11 shows the full frequency response of the AD 7730 when the second stage filter is set for normal FIR operation T his response is for chop mode enabled with the decimal equivalent of the word in the SF bits set to 512 and a master clock frequency of 4 9152 MHz T he response will scale proportionately with master clock frequency T he response is shown from dc to 100 Hz T he rejection at 50 2 1 60 Hz 1 Hz is better than 88 dB T he 3 dB frequency for the frequency response of the AD 7730 with the second stage filter set for normal FIR operation and chop mode enabled is determined by the following relationship E fcik iN 1 0 0395 In this case 7 9 Hz and the stopband where the attenua tion is greater than 64 5 dB is determined by f 1 Fstop 0 14 x C xs In this case 28 Hz REV A AD7730 AD7730L GAIN dB 10 2
107. nal components the AD 7730 is capable of handling such signals F igure 25 outlines one ap proach to the problem T he example shown is a dc excited bridge that is driven from 5 V supplies In such a circuit two issues must be addressed T he first is how to get the AD 7730 to handle input voltages near or below ground and the second is how to take the 10 V excitation voltage which appears across the bridge and generate a suitable reference voltage for the AD 7730 T he circuit of Figure 25 attempts to address these two issues simultaneously The AD 7730 s analog and digital supplies can be split such that AV pp and DV pp can be at separate potentials and AGND and can also be at separate potentials T he only stipulation isthat AV pp or DVpp must not exceed the AGND by 5 5 V In Figure 25 the DVpp is operated at 3 V which allows the AGND to go down to 2 5 V with respect to system ground T his means that all logic signals to the part must not exceed 3 V with respect to system ground T he AV pp is operated at 2 5 V with respect to system ground T he bridge is excited with 10 V across its inputs T he output of the bridge is biased around the midpoint of the excitation volt ages which in this case is system ground or 0 V In order for the common mode voltage of the analog inputs to sit correctly the AGN D of the AD 7730 must be biased below system ground by 1 2 OP284 OR 1 2 OP213 AVpp O RE ner 1 2 OP284 O
108. ng average on the output of the sinc filter Initially two outputs from the sinc filter are used to calculate an AD 7730 output T he number of sinc outputs used to calculate the moving average output is increased from 2 to 4 to 8 to 16 until the STDY bit goes low When the FIR filter has fully settled after a step the STDY bit will become active and the FIR filter is switched back into the processing loop see F ilter Architec ture section for more details on the FAST Step mode A zero must be written to these bits to ensure correct operation of the AD 7730 AC Excitation Bit If the signal source to the AD 7730 is ac excited a 1 must be placed in this bit For dc excited inputs this bit must be 0 T he ac bit has no effect if CHP is 0 With the ac bit at 1 the AD 7730 assumes that the voltage at the AIN 1 and REF IN REF IN input terminals are reversed on alternate input sampling cycles i e chopped N ote that when the AD 7730 is performing internal zero scale or full scale calibrations the ac bit is treated as a 0 i e the device performs these self calibrations with dc excitation Chop Enable Bit T his bit determines if the chopping mode on the part is enabled A 1 in this bit location enables chopping on the part When the chop mode is enabled the part is effectively chopped at its input and output to remove all offset and offset drift errors on the part If offset performance with time and temperature are important
109. nother read from that specified register T he part will remain in this continuous read mode until 30 H ex has been written to the Communications Register When 1 1 is written to these bits and 0 written to bits through CRO the continuous read mode is stopped and the part returns to where it is expecting a write operation to the Communi cations Register N ote the part continues to look at the DIN line on each SCLK edge during continuous read mode to determine when to stop the continuous read mode T herefore the user must be careful not to inadvertently exit the continuous read mode or reset the AD 7730 by writing a series of 1s to the part T he easiest way to avoid this is to place a logic 0 on the DIN line while the part is in continuous read mode Once the part is in continuous read mode the user should ensure that an integer multiple of 8 serial clocks should have taken place before attempting to take the part out of continuous read mode REV A 13 AD7730 AD7730L Bit Bit Location Mnemonic Description CR3 ZERO A zero must be written to this bit to ensure correct operation of the AD 7730 CR2 CR0 RS2 RSO Register Selection Bits RS2 is the M SB of the three selection bits T he three bits select which register type the next read or write operation operates upon as shown in T able VIII Table VIII Register Selection RS2 RSI RSO Register Offset Register Gain Register T est Register 0 0 0
110. on of output rates Output Noise CHP 1 T his mode is the primary mode of operation of the device T able XXI shows the output rms noise for some typical output update rates and 3 dB frequencies for the AD 7730 when used in chopping mode CH P of Filter Register 1 with a master clock frequency of 2 4576 M H z T hese numbers are typical and are generated at a differential analog input voltage of 0 V T he output update rate is selected via the SF 0 to SF 11 bits of the Filter Register T able X XII meanwhile shows the output peak to peak resolu tion in counts for the same output update rates T he numbers in brackets are the effective peak to peak resolution in bits rounded to the nearest 0 5 LSB It is important to note that the numbers in T able X XII represent the resolution for which there will be no code flicker within a six sigma limit T hey are not calculated based on rms noise but on peak to peak noise The numbers are generated for the bipolar input ranges When the part is operated in unipolar mode the output noise will be the same as the equivalent bipolar input range As a result the numbers in T able X XI will remain the same for unipolar ranges while the numbers in T able II will change T o calculate the numbers for T able X XII for unipolar input ranges simply divide the peak to peak resolution number in counts by two or subtract one from the peak to peak resolution number in bits Table XXI Output Noise vs Input Range and
111. onsists of two portions a first stage filter and a second stage filter T he first stage filter is a sin low pass filter T he cutoff frequency and output rate of this first stage filter is programmable T he second stage filter has three distinct modes of operation In its normal mode it provides a low pass FIR filter that processes the output of the first stage filter When a step change is detected on the analog input this second stage filter enters a second mode where it performs a variable number of averages for some time after the step change and then the second stage filter switches back to the FIR filter T he third option for the second stage filter is that it is completely bypassed so the only filtering provided on the AD 7730 is the first stage T he various filter stages and options are discussed in the follow ing sections 26 First Stage Filter T he first stage filter is a low pass sinc or sinx x filter whose primary function is to remove the quantization noise introduced at the modulator T he cutoff frequency and output rate of this filter is programmed via the SFO to SF 11 bits of the Filter Reg ister T he frequency response for this first stage filter is shown in Figure 10 The response of this first stage filter is similar to that of an averaging filter but with a sharper roll off T he output rate for the filter corresponds with the positioning of the first notch of the filter s frequency response T hus for th
112. ontinuous Conversion M ode Single Conversion M ode Power D own Standby M ode Internal Zero Scale Calibration Internal ull Scale Calibration System Zero Scale C alibration System F ull Scale C alibration N a a O O REV 15 AD7730 AD7730L MD2 Operating Mode 0 0 0 Sync Idle M ode In this mode the modulator and filter are held in reset mode and the AD 7730 is not processing any new samples or data Placing the part in this mode is equivalent to exerting the SYNC input pin H owever exerting the SYNC pin does not actually force these mode bits to 0 0 0 T he part returns to this mode after a calibration or after a conversion in Single Conversion M ode T his 15 the default condition of these bits after Power O n R eset 0 0 1 Continuous Conversion M ode In this mode the AD 7730 is continuously processing data and providing conversion results to the D ata R egister at the programmed output update rate as determined by the Filter Register For most applications this would be the normal operating mode of the AD 7730 0 1 0 Single Conversion M ode In this mode the AD 7730 performs a single conversion updates the D ata Register returns to the Sync ode and resets the mode bits to 0 0 0 T he result of the single conversion on the AD 7730 in this mode will not be provided until the full settling tim
113. or the bridge transducer on the analog input also drives the refer ence voltage for the part the effect of the noise in the excita tion voltage will be removed as the application is ratiometric Figure 7 shows how the reference voltage can be connected in a ratiometric fashion in a dc excited bridge application In this case the excitation voltage for the AD 7730 and the transducer is a dc voltage T he HIREF bit of the M ode Register should be set to 1 Figure 8 meanwhile shows how the reference can be connected in a ratiometric fashion in an ac excited bridge REV A AD7730 AD7730L O O REF INT Q EXCITATION VOLTAGE 45V AD7730 Figure 7 Ratiometric Generation of Reference Excited Bridge Application EXCITATION VOLTAGE 5V AGND 7 DGND Figure 8 Ratiometric Generation of Reference in AC Excited Bridge Application application In this case both the reference voltage for the part and the excitation voltage for the transducer are chopped Once again the HIREF bit should be set to 1 If the AD 7730 is not used in a ratiometric application a low noise reference should be used Recommended 2 5 V reference voltage sources for the AD 7730 include the AD 780 REF 43 and REF 192 If any of these references are used as the reference source for the AD 7730 the HIREF bit should be set to 0 It is generally recommended to decouple the output of these references to further
114. parator and a feedback D AC as illustrated in Figure 9 In operation the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC T he difference between these two signals is integrated and fed to the comparator T he output of the comparator provides the input to the feedback D AC so that the system functions as a negative feedback loop that tries to minimize the difference signal T he digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator T his duty cycle data can be recovered as a data word using the digital filter T he sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal T he integrator in the modulator shapes the quantization noise which results from the analog to digital conversion so that the noise is pushed toward one half of the modulator frequency T he digital filter then bandlimits the re sponse to a frequency significantly lower than one half of the modulator frequency In this manner the 1 bit output of the comparator is translated into a bandlimited low noise output from the AD 7730 ANALOG DIFFERENCE INPUT AMP COMPARATOR DIGITAL FILTER DIGITAL DATA Figure 9 Sigma Delta Modulator Block Diagram DIGITAL FILTERING Filter Architecture T he output of the modulator feeds directly into the digital filter T his digital filter c
115. pends upon the C H P bit of the F ilter Register With CHP 1 the duration is 22 x 1 Output Rate with CHP 0 the duration is 24 x 1 O utput Rate At this time the MD2 MD1 and M D 0 bits in the M ode Register return to 0 0 0 Sync or Idle M ode for the AD 7730 The RDY line goes high when calibration is initiated and returns low when calibration is complete N ote that the part has not performed a conversion at this time it has simply performed a zero scale calibration and updated the Offset Calibration Register for the selected channel T he user must write either 0 0 1 or 0 1 0 to the M D2 1 bits of the ode Register to initiate a conversion If RDY is low before or goes low during the cali bration command write to the M ode Register it may take up to one modulator cycle M CLK IN 32 before RD Y goes high to indicate that calibration is in progress T herefore RDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the M ode Register For bipolar input ranges in the system zero scale calibrating mode the sequence is very similar to that just outlined In this case the zero scale point is the midpoint of the AD 7730 s transfer function T he system zero scale calibration needs to be performed as one part of a two part full calibration H owever once a full calibra tion has been performed additional system zero scale calibra tions can be performed by t
116. quired for interfacing to D SP machines 6 hese numbers are derived from the measured time taken by the data output to change 0 5 V when loaded with the circuit of Figure 1 The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor T his means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances TRDY returns high after the first read from the device after an output update T he same data can be read again if required while is high although care should be taken that subsequent reads do not occur close to the next output update ais REV A AD7730 AD7730L ABSOLUTE MAXIMUM RATINGS Plastic DIP Package Power Dissipation 450 mW T4 425 C unless otherwise noted W a da a emperature Soldering SEGI s 9 as i DONE MA SON DU ANA ANA W Ni p x TSSOP Package Power Dissipation 450 mW DV 03 V to 47V Oja Thermal Impedance Le ana ate aye ma enan 128 C W DV to DGND 03V to 47 V Lead T emperature Soldering AG ND DON A Lm 5 V to 03V Vapor Phase 60 sec 215 C ANA SA TO AOU 2V to 45 V Infrared 15 sec IE 220 C DD SOIC Package Power Dissipation 450 mW Analog Input Voltageto AGND 0 3V to AVpp 0 3 V Thermal Impedance 75 C W Reference Input Voltageto AGND
117. r Pair 1 1 0 AIN 1 AIN 1 Register Pair 0 1 1 AIN 1 AIN 2 Register Pair 2 Filter Register RS2 RSO 0 1 1 Power On Reset Status 200010 Hex TheFilter Register is a 24 bit register from which data can be read or to which data can be written T his register determines the amount of averaging performed by the filter and the mode of operation of the filter It also sets the chopping mode and the delay associated with chopping the inputs T able XIV outlines the bit designations for the F ilter Register FRO through FR23 indicate the bit location FR denoting the bits are in the Filter Register FR23 denotes the first bit of the data stream T he number in brackets indicates the power on reset default status of that bit Figure 5 shows a flowchart for reading from the registers on the AD 7730 and Figure 6 shows a flowchart for writing to the registers on the part TableXIV Filter Register FR23 FR22 FR21 FR20 FR19 FR18 FR17 FR16 FR15 FR14 FR13 FR12 FR11 FR10 FR9 FR8 FR7 FR6 FR5 FR4 FR3 FR2 FR1 FRO Bit Mnemonic SF11 SFO Bit Location FR23 FR12 Description Sinc Filter Selection Bits T he AD 7730 contains two filters a sinc filter and an FIR filter T he 12 bits programmed to SF 11 through SF 0 set the amount of averaging the sinc filter performs As a result the number programmed to these 12 bits affects the 3 dB frequency and output update rate from the part see Filter Architecture section T he allow
118. reduce the noise level Reference Detect TheAD7730 includes on chip circuitry to detect if the part has a valid reference for conversions or calibrations If the volt age between the REF IN and REF IN pins goes below 0 3 V or either the REF IN or REF IN inputs is open circuit the AD 7730 detects that it no longer has a valid reference In this case the NO REF bit of the Status Register is set to a 1 If the AD 7730 is performing normal conversions and the NO REF bit becomes active the part places all ones in the D ata Register T herefore it is not necessary to continuously monitor the status of the NO REF bit when performing conversions It is only necessary to verify its status if the conversion result read from the D ata Register is all 1s 25 AD7730 AD7730L If the AD 7730 is performing either an offset or gain calibration and the NOREF bit becomes active the updating of the respec tive calibration register is inhibited to avoid loading incorrect coefficients to this register If the user is concerned about verify ing that a valid reference is in place every time a calibration is performed then the status of the N OREF bit should be checked at the end of the calibration cycle SIGMA DELTA MODULATOR A sigma delta ADC generally consists of two main blocks an analog modulator and a digital filter In the case of the AD 7730 the analog modulator consists of a difference amplifier an inte grator block a com
119. reset status of these bits vary depending on the factory assigned number 14 REV A AD7730 AD7730L Data Register RS2 RSO 0 0 1 Power On Reset Status 000000 H ex The Data Register on the part is a read only register which contains the most up to date conversion result from the AD 7730 Fig ure 5 shows a flowchart for reading from the registers on the AD 7730 T he register can be programmed to be either 16 bits or 24bits wide determined by the status of the WL bit of the M ode Register The RDY output and bit of the Status Register are set low when the D ata Register is updated The RDY pin and RDY bit will return high once the full contents of the register either 16 bits or 24 bits have been read If the D ata Register has not been read by the time the next output update occurs the RDY pin and RDY bit will go high for at least 100 x in indicating when a read from the D ata Register should not be initiated to avoid a transfer from the D ata Register as it is being updated Once the updating of the D ata Register has taken place RDY returns low If the Communications Register data sets up the part for a write operation to this register a write operation must actually take place in order to return the part to where it is expecting a write operation to the Communications Register the default state of the inter face H owever the 16 or 24 bits of data written to the part will be ignored by the AD 7730 Mode Reg
120. rimary analog input pair Analog Input Channel 2 or D igital Output 1 T his pin can be used either as part of a second analog input channel or as a digital output bit as determined by the DEN bit of the M ode Register When selected as an analog input it is the positive input of the differential programmable gain secondary analog input pair T he analog input ranges are 0 mV to 10 mV 0 mV to 20 mV 0 mV to 40 mV and 0 mV to 80 mV in unipo lar mode and 10 mV 20 mV 40 mV and 80 mV in bipolar mode When selected as a digital output this output can programmed over the serial interface using bit D 1 of the M ode Register Analog Input Channel 2 or Digital Output 0 T his pin can be used either as part of a second analog input channel or as a digital output bit as determined by the DEN bit of the M ode Register When selected as an analog input it is the negative input of the differential programmable gain secondary analog input pair W hen selected as a digital output this output can programmed over the serial interface using bit DO of the M ode Register Reference Input Positive terminal of the differential reference input to the AD 7730 REF IN can lie anywhere between AV pp and AGND T he nominal reference voltage the differential voltage between REF IN and REF IN should be 5 V when the HIREF bit of the M ode Register is 1 and 42 5 V when the HIREF bit of the M ode Register is 0 Reference Input N egative terminal of the di
121. rom the analog input signal before it is applied to the PGA Note that the HIREF bit has no effect on the DAC range or resolution it controls the ADC range only Offset Calibration Register RS2 RSO 1 0 1 Power On Reset Status 800000 Hex The AD 7730 contains three 24 bit Offset Calibration Registers labelled Offset Calibration Register 0 to Offset Calibration R eg ister 2 to which data can be written and from which data can be read T he three registers are totally independent of each other T he Offset Calibration Register is used in conjunction with the associated G ain Calibration Register to form a register pair T he calibration register pair used to scale the output is as outlined in T able XIII T he Offset Calibration Register is updated after an offset calibration routine 1 0 0 or 1 1 0 loaded to the M D2 MD1 M DO bits of the M ode Register During subsequent conversions the contents of this register are subtracted from the filter output prior to gain scaling being performed on the word Figure 5 shows a flowchart for reading from the registers on the AD 7730 and Figure 6 shows a flowchart for writing to the regis ters on the part Gain Calibration Register RS2 RSO 1 1 0 Power On Reset Status 593CEA T he AD 7730 contains three 24 bit Gain Calibration Registers labelled Gain Calibration Register 0 to Gain Calibration Register 2 to which data can be written and from which data can be read T he three register
122. rt D ata from this input shift register is transferred to the calibration registers mode register communications register DAC register or filter registers depending on the register selection bits of the Communications R egister 23 DVpp Digital Supply Voltage 3 V or 5 V nominal 24 DGND Ground reference point for digital circuitry TERMINOLOGY BIPOLAR NEGATIVE FULL SCALE ERROR INTEGRAL NONLINEARITY T his is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function T he end points of the transfer function are zero scale not to be confused with bipolar zero a point 0 5 LSB below the first code transi tion 000 000 to 000 001 and full scale a point 0 5 LSB above the last code transition 111 110 to 111 111 The error is expressed as a percentage of full scale POSITIVE FULL SCALE ERROR Positive F ull Scale Error is the deviation of the last code transition 111 110to 111 111 from the ideal AIN voltage Vagr GAIN 3 2 LSBs It applies to both unipolar and bipolar analog input ranges Positive full scale error is a summation of offset error and gain error UNIPOLAR OFFSET ERROR U nipolar Offset Error is the deviation of the first code transition from the ideal AIN voltage AIN 0 5 LSB when oper ating in the unipolar mode BIPOLAR ZERO ERROR This is the deviation of the midscale transition 0111 111 to 1000 000 from t
123. s connected to the IRQ2 input of the ADSP 2105 The RFS and TFS pins of the AD SP 2105 are configured as active low out puts and the AD SP 2105 serial clock line SCLK is also config ured as an output The POL pin of the AD 7730 is hardwired low Because the SCLK from the AD SP 2105 is a continuous clock the CS of the AD 7730 must be used to gate off the clock once the transfer is complete T he CS for the AD 7730 is active when either the RFS or TFS outputs from the AD SP 2105 are active T he serial clock rate on the AD SP 2105 should be lim ited to 3 MHz to ensure correct operation with the AD 7730 DVpp Figure 22 AD7730 to ADSP 2105 Interface 39 AD7730 AD7730L APPLICATIONS Theon chip PGA allows the AD 7730 to handle analog input voltage ranges as low as 10 mV full scale T his allows the user to connect a transducer directly to the input of the AD 7730 T he AD7730 is primarily targeted for weigh scale and load cell applications T he majority of the applications have a strain gage transducer whose resistance changes when subjected to mechanical stress N ormally the gages are configured in a Wheatstone bridge arrangement T he strain gage is a passive device and requires an excitation voltage or in some cases a current to derive a voltage output T wo types of voltage excita tion can be provided for the bridge dc excitation or ac excita tion T hese are discussed in the following sections While the desire in most
124. s are totally independent of each other T he Gain Calibration Register is used in conjunction with the associated Offset Calibration Register to form a register pair T he calibration register pair used to scale the output is as outlined in T able XIII The Gain Calibration Register is updated after a gain calibration routine 1 0 1 or 1 1 1 loaded to the M D2 M D1 M DO bits of the M ode Register D uring subsequent con versions the contents of this register are used to scale the number which has already been offset corrected with the Offset C ali bration Register contents Figure 5 shows a flowchart for reading from the registers on the AD 7730 and Figure 6 shows a flowchart for writing to the registers on the part Test Register RS2 RSO 1 1 1 Power On Reset Status 000000H ex The AD 7730 contains 24 bit T est Register to which data can be written and from which data can be read T he contents of this T est Register are used in testing the device T he user is advised not to change the status of any of the bits in this register from the default Power On or RESET status of all Os as the part will be placed in one of its test modes and will not operate correctly If the part enters one of its test modes exercising RESET or writing 32 successive 1s to the part will exit the AD 7730 from the mode and return all register contents to their power on reset status N ote if the part is placed in one of its test modes it may not be possible to
125. s of counts Both reference inputs provide a high impedance dynamic load T he typical average dc input leakage current over temperature is 8 5 uA with HIREF 1 and 5 V and 2 5 uA with HIREF 0 and 42 5 V Because the input impedance of each reference input is dynamic external resistance capacitance combinations on these inputs may result in gain errors on the part The AD7730 can be operated in either ac or dc mode If the bridge excitation is fixed dc the AD 7730 should be operated in dc mode If the analog input and the reference inputs are externally chopped before being applied to the part the AD 7730 should be operated in ac mode and not dc mode In ac mode it is assumed that both the analog inputs and reference inputs are chopped and as a result change phase every alternate chopping cycle If the chopping is synchronized by the AD 7730 using the ACX signals to control the chopping the part then takes into account the reversal of the analog input and reference input signals T he output noise performance outlined in T ables through IV is for an analog input of 0 V and is unaffected by noise on the reference T o obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD 7730 If the reference noise in the bandwidth of interest is excessive it will degrade the performance of the AD 7730 In applications where the excitation voltage f
126. should not be initiated T his is to ensure that the transfer of data from the data register to the output shift register does not occur while the data register is being updated It is possible to read the same data twice from the output register even though the RDY line returns high after the first read operation C are must be taken however to ensure that the read operations are not initiated as the next output update is about to take place For systems with a single data line the DIN and DOUT lines on the AD 7730 can be connected together but care must be taken in this case not to place the part in continuous read mode as the part monitors DIN while supplying data on DOUT and as a result it may not be possible to take the part out of its continuous read mode Figure 19 Write Cycle Timing Diagram 36 REV A AD7730 AD7730L CONFIGURING THE AD7730 The AD7730 contains twelve on chip registers that can be accessed via the serial interface Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers T able XIX and T able XX outline sample pseudo code for some commonly used routines T he required operating conditions will dictate the values loaded to the M ode Filter and DAC Registers T he values given here are for example purposes only Table XIX Pseudo Code for Initiating a Self Calibration after Power O n Reset Write 03 H ex to Serial Port Writes to Communications Register Setting N
127. ss than 100 ppm for the 80 mV and 40 mV ranges to about 250 ppm for the 20 mV range and to about 500 ppm on the 10 mV range System full scale calibration reduces this to the order of the noise Positive and negative full scale errors can be calculated from the offset and gain errors T hese numbers are generated during life testing of the part Positive Full Scale Error includes Offset Errors U nipolar Offset Error or Bipolar Zero Error and applies to both unipolar and bipolar input ranges See T erminology 5Recalibration at any temperature will remove these errors TF ull Scale Drift includes Offset D rift U nipolar Offset D rift or Bipolar Zero D rift and applies to both unipolar and bipolar input ranges 8Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function T he two points used to calculate the gain error are positive full scale and negative full scale See T erminology Gain Error Drift is a span drift and is effectively the drift of the part if zero scale calibrations only were performed 10N o issing Codes performance with 0 and SKIP 1 is reduced below 24 bits for SF words lower than 180 decimal HT he analog input voltage range on the AIN 1 and AIN 2 inputs is given here with respect to the voltage on the AIN 1 and AIN 2 inputs respectively 12T he common mode voltage range on the input pairs applies provided the absolute input volt
128. status of the ac bit T he duration time of the calibration de pends upon the CHP bit of the Filter Register With CHP 1 the duration is 22 x 1 Output Rate with CHP 0 the duration is 24 x utput Rate At this timetheM D2 1 0 bits in the M ode Register return to 0 0 0 Sync or Idle M ode for the AD 7730 The RDY line goes high when calibration is initiated and returns low when calibration is complete N ote that the part has not performed a conversion at this time it has 30 simply performed a zero scale calibration and updated the Off set Calibration Register for the selected channel T he user must write either 0 0 1 or 0 1 0 to the M D2 M D1 M DO bits of the M ode Register to initiate a conversion If RDY is low before or goes low during the calibration command write to the M ode Register it may take up to one modulator cycle M CL K 13 32 before RDY goes high to indicate that calibration is in progress T herefore RDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the M ode Register For bipolar input ranges in the internal zero scale calibrating mode the sequence is very similar to that just outlined In this case the zero scale point is exactly the same as above but since the part is configured for bipolar operation the output code for zero differential input is 800000 H ex in 24 bit mode T he internal zero scale calibration needs
129. stors should be placed in series with the logic inputs to again limit the current to less than 30 mA per pin and less than 100 mA total Grounding and Layout Since the analog inputs and reference input are differential most of the voltages in the analog modulator are common mode voltages T he excellent common mode rejection of the part will remove common mode noise on these inputs T he analog and digital supplies to the AD 7730 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device T he digital filter will provide rejection of broadband noise on the power supplies except at integer mul tiples of the modulator sampling frequency or multiples of the chop frequency in chop mode T he digital filter also removes noise from the analog and reference inputs provided those noise sources do not saturate the analog modulator As a result the AD 7730 is more immune to noise interference than a conven tional high resolution converter H owever because the resolu tion of the AD 7730 is so high and the noise levels from the AD 7730 so low care must be taken with regard to grounding and layout T he printed circuit board that houses the AD 7730 should be designed so the analog and digital sections are separated and confined to certain areas of the board T his facilitates the use of ground planes that can be easily separated A minimum etch technique is generally best for ground planes as
130. tem Register lengths on the AD 7730 vary from 8 to 16 to 24 bits T he 8 bit serial ports of most microcontrollers can handle communication with these registers as either one two or three 8 bit transfers D SP processors and microprocessors generally transfer 16 bits of data in a serial data operation Some of these processors such as the AD SP 2105 have the facility to program the amount of cycles in a serial transfer T his allows the user to tailor the number of bits in any transfer to match the register length of the required register in the AD 7730 In any case writing 32 bits of data to a 24 bit register is not an issue provided the final eight bits of the word are all 1s T his is because the part returns to the Communications Register following a write operation Even though some of the registers on the AD 7730 are only eight bits in length communicating with two of these registers in successive write operations can be handled as a single 16 bit data transfer if required For example if the DAC Register is to be updated the processor must first write to the Communica tions Register saying that the next operation is a write to the M ode Register and then write eight bits to the DAC Register T his can all be done in a single 16 bit transfer if required be cause once the eight serial clocks of the write operation to the Communications Register have been completed the part imme diately sets itself up for a write operation to
131. ter an internal full scale calibration to correct the Offset Calibration Register contents W hen using system full scale calibration it is recommended that the zero scale calibration either internal or system is performed first Since the calibration coefficients are derived by performing a conversion on the input voltage provided the accuracy of the calibration can only be as good as the noise level the part pro vides in normal mode T o optimize the calibration accuracy it is recommended to calibrate the part at its lowest output rate where the noise level is lowest T he coefficients generated at any output update rate will be valid for all selected output update rates T his scheme of calibrating at the lowest output update rate does mean that the duration of calibration is longer Internal Zero Scale Calibration An internal zero scale calibration is initiated on the AD 7730 by writing the appropriate values 1 0 0 to theM D2 MD1 and M DO bits of the M ode Register In this calibration mode with a unipolar input range the zero scale point used in determining the calibration coefficients is with the inputs of the differential pair internally shorted on the part i e AIN Externally Applied AIN voltage T he PGA is set for the selected gain as per the RN 1 RNO bits in the M ode Register for this internal zero scale calibration conversion T he calibration is performed with dc excitation regardless of the
132. the DAC Register AD 7730 to 68HC 11 Interface Figure 20 shows an interface between the AD 7730 and the 68H C11 microcontroller T he diagram shows the minimum three wire interface with CS on the AD 7730 hardwired low In this scheme the RDY bit of the Status Register is monitored to determine when the D ata Register is updated An alternative scheme which increases the number of interface lines to four is to monitor the RDY output line from the AD 7730 T he moni toring of the RDY line can be done in two ways First RDY can be connected to one of the 68H C 11 s port bits such as PCO which is configured as an input T his port bit is then polled to determine the status of RDY T he second scheme is to use an interrupt driven system in which case the RDY output is con nected to the IRQ input of the 68H C 11 For interfaces which require control of the CS input on the AD 7730 one of the port bits of the 68H C 11 such as PC 1 which is configured as an output can be used to drive the CS input 38 The 68H C11 is configured in the master mode with its CPOL bit set to a logic zero and its CPHA bit set to a logic one When the 68H C11 is configured like this its SCLK line idles low between data transfers T herefore the POL input of the AD 7730 should be hardwired low F or systems where it is preferable that the SCLK idle high the CPOL bit of the 68H C 11 should be set to aLogic 1 and the POL input of the AD 7730 should be hard
133. to be performed as one part of a two part full calibration H owever once a full calibration has been performed additional internal zero scale calibrations can be performed by themselves to adjust the part s zero scale point only When performing a two step full calibration care should be taken as to the sequence in which the two steps are performed If the internal zero scale calibration is one part of a full self calibration then it should take place after an internal full scale calibration If it takes place in association with a system full scale calibration then this internal zero scale calibration should be performed first Internal Full Scale Calibration An internal full scale calibration is initiated on the AD 7730 by writing the appropriate values 1 0 1 to theM D2 MD1 and M DO bits of the M ode Register In this calibration mode the full scale point used in determining the calibration coefficients is with an internally generated full scale voltage T his full scale voltage is derived from the reference voltage for the AD 7730 and the PGA is set for the selected gain as per theRN 1 RNO bits in the M ode Register for this internal full scale calibration conversion In order to meet the post calibration numbers quoted in the specifications it is recommended that internal full scale calibra tions be performed on the 80 mV range T his applies even if the subsequent operating mode is on the 10 mV 20 mV or 40 mV input ranges
134. ttiing Time Settling Time Input Range InputRange InputRange Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40 mV 20mV 10 50 Hz 1 97 Hz 2048 460 ms 60 ms 115 75 55 40 100 Hz 3 95 Hz 1024 230 ms 30 ms 155 105 75 60 150 Hz 5 92 Hz 683 153 ms 20 ms 200 135 95 70 200Hz 7 9Hz 512 115 ms 15 ms 225 145 100 80 400 Hz 15 8 Hz 256 57 5 ms 7 5 ms 335 225 160 110 Power On D efault Tablell Peak to Peak Resolution vs Input Range and Update Rate CHP 1 Peak to Peak Resolution in Counts Bits Output 3dB SF Settiing Time Settling Time Input Range InputRange Input Range Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40 mV 20 10 50 Hz 1 97 Hz 2048 460 ms 60 ms 230k 18 175k 17 5 120k 17 80k 16 5 100 Hz 3 95 Hz 1024 230 ms 30 ms 170k 17 5 125k 17 90k 16 5 55k 16 150 Hz 5 92 Hz 683 153ms 20 ms 130k 17 100k 16 5 70k 16 45k 15 5 200 Hz 7 9Hz 512 115 ms 15 ms 120k 17 90k 16 5 65k 16 40k 15 5 400 Hz 15 8 Hz 256 57 5 ms 7 5 ms 80k 16 5 55k 16 40k 15 5 30k 15 Power On Default Output Noise CHP 0 Table III shows the output rms noise for some typical output update rates and 3 dB frequencies for the AD 7730 when used in non chopping mode CHP of Filter Register 0 with a master clock frequency of 4 9152 M Hz T hese numbers are typical and are gen erated at a differential analog input voltage of 0 V T
135. typical and are generated at a differential analog input voltage of 0 V T he output update rate is selected via the SF 0 to SF 11 bits of the F ilter R egis ter T able XXIV meanwhile shows the output peak to peak resolution in counts for the same output update rates T he numbers in brackets are the effective peak to peak resolution in bits rounded to the nearest 0 5 LSB It is important to note that the numbers in Table XXIV represent the resolution for which there will be no code flicker within a six sigma limit T hey are not calculated based on rms noise but on peak to peak noise The numbers are generated for the bipolar input ranges When the part is operated in unipolar mode the output noise will be the same as the equivalent bipolar input range As a result the numbers in T able X XIII will remain the same for unipolar ranges while the numbers in Table XXIV will change T o calculate the number for T able XXIV for unipolar input ranges simply divide the peak to peak resolution number in counts by two or subtract one from the peak to peak resolution number in bits 48 REV A AD7730 AD7730L Table XXIII Output Noise vs Input Range and U pdate Rate CHP 0 Typical Output RMS Noise in nV Output 3dB SF SettlingTime Settling Time InputRange InputRange InputRange Input Range Data Rate Frequency Word Normal Mode Fast Mode 80mV 40mV 20mV 10mV 75 Hz 2 9 Hz 2048 332 ms 53 2 ms 320 215 135 100 100 Hz 3 9 Hz 1536 250 ms
136. urs T herefore write access to one of the control registers on the part starts with a write opera tion to the Communications Register followed by a write to the selected register Reading from the part s on chip registers can take the form of either a single or continuous read A single read from a register consists of a write to the Communications R egis ter with RW1 0 and RWO 1 followed by the read from the specified register T o perform continuous reads from a register write to the Communications Register with RW1 1 and RWO 0 to place the part in continuous read mode T he speci fied register can then be read from continuously until a write operation to the Communications Register with RW1 1 and RWO 1 which takes the part out of continuous read mode When operating in continuous read mode the part is continu ously monitoring its DIN line The DIN line should therefore be permanently low to allow the part to stay in continuous read mode Figure 5 and Figure 6 shown previously indicate the correct flow diagrams when reading and writing from the AD 7730 s registers The AD 7730 s serial interface consists of five signals CS SCLK DIN DOUT and RDY TheDIN line is used for transferring data into the on chip registers whilethe D OUT line is used for accessing data from the on chip registers SCLK is the serial clock input for the device and all data transfers either on DIN or DOUT take place with respect to this
137. viding the clock source for the part T he input sampling frequency the modulator sampling frequency the 3 dB frequency output update rate and calibration time are all directly related to the master clock frequency fek iw Reducing the master clock frequency by a factor of two will halve the above frequencies and update rate and double the calibration time T he crystal or ceramic resonator is connected across the M CLK IN and OUT pins as per Figure 17 Capacitors C 1 and C2 may or may not be required and may vary in value depend ing on the crystal resonator manufacturer s recommendations T he AD 7730 has a capacitance of 5 pF on M CLK IN and 13 pF on M CLK OUT so in most cases capacitors C 1 and C2 will not be required to get the crystal resonator operating at its cor rect frequency REV A AD7730 Figure 17 Crystal Resonator Connections Theon chip oscillator circuit also has a start up time associated with it before it has attained its correct frequency and correct voltage levels T he typical start up time for the circuit is 6 ms with aDVpp of 5 V and 8 ms with a DVpp of 3 V T he AD 7730 s master clock appears on the M CLK OUT pin of the device T he maximum recommended load on this pin is one CM OS load When using a crystal or ceramic resonator to gen erate the AD 7730 s clock it may be desirable to then use this clock as the clock source for the system In this case it is recom mended that the M C
138. when normalized is multiplied by all conversion results T he offset calibration coeffi cient is subtracted from the result prior to the multiplication by the gain coefficient The AD7730 offers self calibration or system calibration facili ties For full calibration to occur on the selected channel the on chip microcontroller must record the modulator output for two different input conditions T hese are zero scale and full scale points T hese points are derived by performing a conver sion on the different input voltages provided to the input of the modulator during calibration T he result of the zero scale calibration conversion is stored in the Offset Calibration R egis ter for the appropriate channel T he result of the full scale calibration conversion is stored in the Gain Calibration Register for the appropriate channel With these readings the microcon troller can calculate the offset and the gain slope for the input to output transfer function of the converter Internally the part works with 33 bits of resolution to determine its conversion result of either 16 bits or 24 bits T he sequence in which the zero scale and full scale calibration occurs depends upon the type of full scale calibration being performed T he internal full scale calibration is a two step cali bration that alters the value of the Offset Calibration Register T hus the user must perform a zero scale calibration either internal or system af
139. x Analog Input DC Bias Current D rift 100 typ Analog Input DC Offset Current 10 nA max Analog Input DC Offset Current Drift 50 pA C typ STATIC PERFORMANCE CHP 0 NoMissing Codes 24 Bits min SKIP 010 Output N oise and U pdate Rates See T ables 11 amp IV Integral N onlinearity 18 ppm of FSR max Offset Error See N ote 3 Offset Error and Offset D rift Refer to Both Offset D rift vs T emperature 0 5 uV C typ U nipolar Offset and Bipolar Zero Errors Offset D rift vs T ime 2 5 uV 1000 H ours typ Positive F ull Scale Error See N ote 3 Positive F ull Scale D rift vs T 7 0 6 uV C typ Positive ull Scale D rift vs Time 3 uV 1000 ours typ Gain Error See Note 3 Gain Drift vs T emperature 2 ppm C typ Gain Drift vs T ime 10 ppm 1000 H ours typ Bipolar N egative Full Scale Error See N ote 3 N egative F ull Scale D rift vs T emp 0 6 uV C typ Power Supply Rejection 90 dB typ M easured with Zero Differential Voltage Common M ode Rejection CM R on AIN 100 dB typ At DC Measured with Zero Differential Voltage CMR on REF IN 120 dB typ At DC Measured with Zero Differential Voltage Analog Input DC Bias Current 60 nA max Analog Input DC Bias Current D rift 150 typ Analog Input D C Offset Current 30 nA max Analog Input D C Offset Current D rift 100 pA C typ ANALOG INPUTS REFERENCE INPUTS N ormal M ode 50 H z Rejection 88 dB min From 49 Hz to 51 Hz N ormal M ode 60 H z Rejection 88 dB min
140. y AC Excitation of Bridge AC excitation of the bridge addresses many of the concerns with thermocouple offset and drift effects encountered in dc excited applications In ac excitation the polarity of the excitation volt age to the bridge is reversed on alternate cycles T he result is the elimination of dc errors at the expense of a more complex sys tem design Figure 24 outlines the connections for an ac excited bridge application based on the AD 7730 The excitation voltage to the bridge must be switched on alternate cycles Transistors T 1 to T 4 in Figure 24 perform the switching of the excitation voltage T hese transistors can be EXCITATION VOLTAGE 5V T web AIN2 4 D1 Q AIN2 DO E O AC discrete matched bipolar or M OS transistors or a dedicated bridge driver chip such as the 4427 from M icrel can be used to perform the task Since the analog input voltage and the reference voltage are reversed on alternate cycles the AD 7730 must be synchronized with this reversing of the excitation voltage T o allow the AD7730 to synchronize itself with this switching it provides the logic control signals for the switching of the excitation voltage T hese signals are the nonoverlapping C M OS outputs A C X and ACX One of the problems encountered with ac excitation is the set tling time associated with the analog input signals after the excitation voltage is switched T his is particularly true

ANALOG DEVICES AD7730/AD7730L Manual

Contents

Download Pdf Manuals

Related Search

Related Contents