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SILICON LABORATORIES C8051F130/1/2/3 User Manual

1. z MIN NOM MAX D1 mm mm mm A 1 20 eg lame Al 0 05 0 15 2 3 4 57 A2 0 95 1 00 1 05 A E EH a b 0 17 0 22 0 27 C7 Ces Cl 11 CH E D 16 00 EA gt 3 EE E F E1 E DU 14 00 C1 PE Ey e 0 50 UC el a E 16 00 E C1 CU 0 El 14 00 100 CN E E L 0 45 0 60 0 75 PIN 1 DESIGNATOR 1 A2 es i 1 H A Sl U N 1 8 Al Figure 4 3 TQFP 100 Package Drawing Rev 1 4 51 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Oo o o o Q e E Uv OU h QO U OZ 9 3 o o Xx i A II YY A 0 O 2 0 O S S S o o e QO O rr F amp F gt O DD DD D lt E si lol IN lol o lol Sl ol lol st foo pi la lol la o w l JO ol G LO ol fio ai t fed jin Lo 5 S CP1 1 IWRIPO 7 CP1 2 ADO DO P3 0 CPO 3 AD1 D1 P 3 1 CPO 4 AD2 D2 P 3 2 AGND 5 AD3 D3 P3 3 AV 6 AD4 D4 P3 4 VREF 7 C8051F121 AD5 D5 P3 5 VREFA 8 C8051F123 VDD AINO O 9 C8051F125 DGND AINO 1 10 AD6 D6 P3 6 AINO 2 11 C8051F 127 AD7 D7 P3 7 AINO 3 12 A8m A0 P2 0 AINO 4 13 A9m A1 P2 1 AINO 5 14 A10m A2 P2 2 AINO
2. DATA BUS H 8 3 E 8 8 ACCUMULATOR B REGISTER STACK POINTER um 2 TMP1 TMP2 lt E SRAM a PSW lt lt ADDRESS ees ALU REGISTER ko Bi a a E DATA BUS H SFR_ADDRESS BUFFER 55 SFR_CONTROL SFR pe BUS SFR_WRITE_DATA DATA POINTER DE INTERFACE S gt SFR READ DATA A PC INCREMENTER 9 Da MEM ADDRESS PROGRAM COUNTER PC 2 MEM CONTROL lt MEMORY PRGM ADDRESS REG A N INTERFACE MEM WRITE DATA l Q MEM READ DATA AA PIPELINE 55 RESET CONTROL LOGIC SYSTEM_IRQs CLOCK INTERRUPT l ag INTERFACE EMULATION_IRQ STOP qo D POWER CONTROL La coe REGISTER E e Figure 11 1 CIP 51 Block Diagram Programming and Debugging Support A JTAG based serial interface is provided for in system programming of the Flash program memory and communication with on chip debug support logic The re programmable Flash can also be read and changed by the application software using the MOVC and MOVX instructions This feature allows program memory to be used for non volatile data storage as well as updating program code under software control The on chip debug support logic facilitates full speed in circuit debugging allowing the setting of hardware bre
3. SILICON LABORATORIES Rev 1 4 Register Address GE Description Page No page 114 REFOCN OxD1 0 Voltage Reference Control page 116 page 117 RSTSRC OxEF 0 Reset Source page 182 SADDRO OxA9 0 UART 0 Slave Address page 298 SADENO OxB9 0 UART 0 Slave Address Mask page 298 SBUFO 0x99 0 UART 0 Data Buffer page 298 SBUF1 0x99 1 UART 1 Data Buffer page 305 SCONO 0x98 0 UART 0 Control page 296 SCON1 0x98 1 UART 1 Control page 304 SFRLAST 0x86 All Pages SFR Stack Last Page page 143 SFRNEXT 0x85 All Pages SFR Stack Next Page page 143 SFRPAGE 0x84 All Pages SFR Page Select page 142 SFRPGCN 0x96 F SFR Page Control page 142 SMBOADR 0xC3 0 SMBus Slave Address page 269 SMBOCN OxCO 0 SMBus Control page 266 SMBOCR OxCF 0 SMBus Clock Rate page 267 SMBODAT 0xC2 0 SMBus Data page 268 SMBOSTA OxC1 0 SMBus Status page 269 SP 0x81 All Pages Stack Pointer page 151 SPIOCFG Ox9A 0 SPI Configuration page 280 SPIOCKR Ox9D 0 SPI Clock Rate Control page 282 SPIOCN OxF8 0 SPI Control page 281 SPIODAT 0x9B 0 SPI Data page 282 SSTAO 0x91 0 UART 0 Status page 297 TCON 0x88 0 Timer Counter Control page 313 THO 0x8C 0 Timer Counter 0 High Byte page 316 TH1 0x8D 0 Timer Counter 1 High Byte page 316 TLO Ox8A 0 Timer Counter O Low Byte page 315 TL1 0x8B 0 Timer Counter 1 Low Byte page 316 TMOD 0x89 0 Timer Counter Mode page 314 TMR2CF OxC9 0 Timer Counter 2 Configuration pa
4. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Bits7 0 Low byte of ADCO Less Than Data Word ES Rev 1 4 85 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Input Voltage ADC Data ADO O AGND Word REF x 1023 1024 Ox03FF ADWINT not affected 0x0201 0x0200 REF x 512 1024 ADCOLTH ADCOLTL ADWINT 1 REF x 256 1024 0x0100 ADCOGTH ADCOGTL OxOOFF ADWINT not affected 0 0x0000 Given AMXOSL 0x00 AMXOCF 0x00 ADOLJST 0 ADCOLTH ADCOLTL 0x0200 ADCOGTH ADCOGTL 0x0100 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt 0x0200 and gt 0x0100 Input Voltage ADC Data ADO O AGND REF x 1023 1024 ADWINT 1 REF x 512 1024 0x0200 ADCOGTH ADCOGTL OXOLFF BIN 0x0101 not affected REF x 256 1024 0x0100 ADCOLTH ADCOLTL ADWINT 1 Given AMXOSL 0x00 AMXOCF 0x00 ADOLJST O ADCOLTH ADCOLTL 0x0100 ADCOGTH ADCOGTL 0x0200 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is gt 0x0200 or lt Ox0100 Figure 6 6 10 Bit ADCO Window Interrupt Example Right Justified Single Ended Data 86 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Input Voltage ADC
5. VREF Turn on Time 1 VREF Turn on Time 2 0 1 uF ceramic bypass VREF Turn on Time 3 no bypass cap Reference Buffer Power Sup ply Current Power Supply Rejection External Reference REFBE Input Voltage Range AV 0 3 Input Current 1 118 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 10 Comparators Two on chip programmable voltage comparators are included as shown in Figure 10 1 The inputs of each comparator are available at dedicated pins The output of each comparator is optionally available at the package pins via the I O crossbar When assigned to package pins each comparator output can be pro grammed to operate in open drain or push pull modes See Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 238 for Crossbar and port initialization details Ea AG CPORIE S CPOE o D EE Sa CPOMD CPOHYN1 CPOHYNO o Ex Reset cros TNL NY RA Crossbar SE Interrupt Handler SYNCHRONIZER 9 NY AGND Figure 10 1 Comparator Functional Block Diagram ES Rev 1 4 119 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Comparator interrupts can be generated on rising edge and or falling edge output transitions For inter rupt enable and priority control see Section 11 3 Interrupt Handle
6. Bus Control Address Bus Data Bus pol 9 Drv LU ang c R p ER o Drv gt x S S bi PR A Drv e ag R P3 ON Drv LU ang P4 Latch Pi P5 Latch ma P6 Latch lp P7 Latch ma P7 DRV Brig P4 kom DRV 39 lt gt lt gt Ps Fes DRV gt P6 E DRV e Kies gt Figure 1 5 C8051F130 132 Block Diagram Rev 1 4 P0 0 P0 7 P1 0 AIN2 0 P1 7 A1N2 7 P2 0 P2 7 P3 0 P3 7 P4 0 P4 4 P4 5 ALE P4 6IRD P4 7IWR P5 0 A8 P5 7 A15 P6 0 A0 P6 7 A7 P7 0 D0 P7 7 D7 25 C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 VDD B VDD B Port 1 0 VDD EE Config DEND Digital Power DGND BA IL UARTO po ER POD SC SE TA SFR Bus Drv LI P0 7 AV a Analog Power A P1 f p1 ki P1 0 AIN2 0 gt P1 7 A1N2 7 BM s B JTAG Boundary Scan TDI Bn Logic Debug HW 256 byte RAM p2 1 38 P2 0 1 2 4 DP gt UNNOJZO 07 Timer 3 DD RTC A le MONEN BF Monitor WDE PO P1 ag TEE e External Data P2 P3 Y 8 ps XTAL1 8SH External Oscillator Latches XTAL2 Re Circuit Memory Bus PLL Crossbar See Config 7 1 Circuitry Calibrated Internal FLASH Oscillator 128kby
7. 338 SFR Definition 24 5 PCAOH PCAO Counter Timer High Byte 338 SFR Definition 24 6 PCAOCPLn PCAO Capture Module Low Byte 338 SFR Definition 24 7 PCAOCPHn PCAO Capture Module High Byte 339 JTAG Register Definition 25 1 IR JTAG Instruction Register 341 JTAG Register Definition 25 2 DEVICEID JTAG Device ID 343 JTAG Register Definition 25 3 FLASHCON JTAG Flash Control 345 JTAG Register Definition 25 4 FLASHDAT JTAG Flash Data 346 JTAG Register Definition 25 5 FLASHADR JTAG Flash Address 346 18 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 1 System Overview The C8051F12x and C8051F13x device families are fully integrated mixed signal System on a Chip MCUs with 64 digital I O pins 100 pin TQFP or 32 digital I O pins 64 pin TQFP Highlighted features are listed below Refer to Table 1 1 for specific product feature selection e High Speed pipelined 8051 compatible CIP 51 microcontroller core 100 MIPS or 50 MIPS e In system full speed non intrusive debug interface on chip e True 12 or 10 bit 100 ksps ADC with PGA and 8 channel analog multiplexer e True 8 bit 500 ksps ADC with PGA and 8 channel analog multiplexer C8051F12x Family e Two 12 bit DACs with programmable update scheduling C8051F12x Family e 2 cycle 16 by 16 Multiply and Ac
8. Mnemonic Description Bytes ae MOV direct Ri Move indirect RAM to direct byte 2 2 MOV direct data Move immediate to direct byte 3 3 MOV Ri A Move A to indirect RAM 1 2 MOV GRI direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate to indirect RAM 2 2 MOV DPTR data16 Load DPTR with 16 bit constant 3 3 MOVC A A DPTR Move code byte relative DPTR to A 1 3 MOVC A A PC Move code byte relative PC to A 1 3 MOVX A Ri Move external data 8 bit address to A 1 3 MOVX Ri A Move A to external data 8 bit address 1 3 MOVX A DPTR Move external data 16 bit address to A 1 3 MOVX DPTR A Move A to external data 16 bit address 1 3 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A Rn Exchange Register with A 1 1 XCH A direct Exchange direct byte with A 2 2 SCH A ORI Exchange indirect RAM with A 1 2 XCHD A Ri Exchange low nibble of indirect RAM with A 1 2 Boolean Manipulation CLR C Clear Carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV C bit Move direct bit to Carry 2 2 MOV bit C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 3 JNC rel Jump if Carry is not set 2 2 3
9. R W R W R W R W R W R W R W R W Reset Value P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 11111111 E F a i p Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address 0xC8 SFR Page F Bits7 0 P4 7 0 Port4 Output Latch Bits Write Output appears on UO pins 0 Logic Low Output 1 Logic High Output Open Drain if corresponding PAMDOUT n bit 0 See SFR Definition 18 14 Read Returns states of I O pins 0 P4 n pin is logic low 1 P4 n pin is logic high Note P4 7 WR P4 6 RD and P4 5 ALE can be driven by the External Data Memory Interface See Section 17 External Data Memory Interface and On Chip XRAM on page 219 for more information SFR Definition 18 14 PAMDOUT Port4 Output Mode R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x9C SFR Page F Bits7 0 P4MDOUT 7 0 Port4 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull 254 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 SFR Definition 18 15 P5 Port5 Data R W R W R W R W R W R W R W R W Reset Value P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 11111111 3 A 8 F x a Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address 0xD8 SFR Page F Bits7 0 P5 7 0 Port5 Ou
10. Differential Nonlinearity Guaranteed Monotonic LSB Offset Error 0 5 0 3 LSB Full Scale Error Differential mode 1 0 2 LSB Offset Temperature Coefficient 10 ppm C Dynamic Performance 10 kHz sine wave input 1 dB below Full Scale 500 ksps Signal to Noise Plus Distortion 45 47 dB Total Harmonic Distortion Up to the 5th harmonic 51 dB Spurious Free Dynamic Range 52 dB Conversion Rate SAR Clock Frequency MHz Conversion Time in SAR Clocks clocks Track Hold Acquisition Time ns Throughput Rate ksps Analog Inputs Input Voltage Range V Input Capacitance pF Power Specifications Power Supply Current AV supplied to ADC2 Power Supply Rejection Operating Mode 500 ksps HA ES Rev 1 4 103 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 NOTES 104 Rev 1 4 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 8 DACs 12 Bit Voltage Mode C8051F12x Only The C8051F12x devices include two on chip 12 bit voltage mode Digital to Analog Converters DACs Each DAC has an output swing of O V to VREF 1LSB for a corresponding input code range of 0x000 to OxFFF The DACs may be enabled disabled via their corresponding control registers DACOCN and DAC1CN While disabled the DAC output is maintained in a high impedance state and the DAC supply current falls to 1 JA or
11. Table 15 1 Flash Electrical Characteristics Vpp 2 7 to 3 6 V 40 to 85 C Parameter Conditions Min Typ Max Units Flash Size C8051F12x and C8051F130 1 1313282 Bytes Flash Size C8051F132 3 65792 Bytes Endurance 20k 100k Erase Write Erase Cycle Time 10 12 14 ms Write Cycle Time 40 50 60 us Notes 1 Includes 256 byte Scratch Pad Area 2 1024 Bytes at location Ox1FCOO to Ox1FFFF are reserved 15 1 1 Non volatile Data Storage The Flash memory can be used for non volatile data storage as well as program code This allows data such as calibration coefficients to be calculated and stored at run time Data is written and erased using the MOVX write instruction as described in Section 15 1 2 and Section 15 1 3 and read using the MOVC instruction The COBANK bits in register PSBANK SFR Definition 11 1 control which portion of the Flash memory is targeted by writes and erases of addresses above 0x07FFF For devices with 64 kB of Flash the COBANK bits should always remain set to 01 to ensure that Flash write erase and read operations are valid Two additional 128 byte sectors 256 bytes total of Flash memory are included for non volatile data stor age The smaller sector size makes them particularly well suited as general purpose non volatile scratch pad memory Even though Flash memory can be written a single byte at a time an entire sector must be erased first In order to ch
12. 20 2 SPIO Master Mode Operation A SPI master device initiates all data transfers on a SPI bus SPIO is placed in master mode by setting the Master Enable flag MSTEN SPIOCN 6 Writing a byte of data to the SPIO data register SPIODAT when in master mode writes to the transmit buffer If the SPI shift register is empty the byte in the transmit buffer is moved to the shift register and a data transfer begins The SPIO master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK The SPIF SPIOCN 7 flag is set to logic 1 at the end of the transfer If interrupts are enabled an interrupt request is generated when the SPIF flag is set While the SPIO master transfers data to a slave on the MOSI line the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full duplex operation Therefore the SPIF flag serves as both a transmit complete and receive data ready flag The data byte received from the slave is transferred MSB first into the master s shift register When a byte is fully shifted into the register it is moved to the receive buffer where it can be read by the processor by reading SPIODAT When configured as a master SPIO can operate in one of three different modes multi master mode 3 wire single master mode and 4 wire single master mode The default multi master mode is active when NSSMD1 SPIOCN 3 O and NSSMDO S
13. Bito SFR Address OxFF SFR Page All Pages WDT Control Writing OxA5 both enables and reloads the WDT Writing OxDE followed within 4 system clocks by OxAD disables the WDT Writing OxFF locks out the disable feature Watchdog Status Bit when Read Reading the WDTCN 4 bit indicates the Watchdog Timer Status 0 WDT is inactive 1 WDT is active Watchdog Timeout Interval Bits The WDTCN 2 0 bits set the Watchdog Timeout Interval When writing these bits WDTCN 7 must be set to O ES Rev 1 4 181 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 SFR Definition 13 2 RSTSRC Reset Source R W R W R W R R W R W Reset Value CNVRSEF CORSEF SWRSEF WDTRSF MCDRSF PINRSF 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 BitO SFR Address OxEF SFR Page 0 Reserved CNVRSEF Convert Start O Reset Source Enable and Flag Write 0 CNVSTRO is not a reset source 1 CNVSTRO is a reset source active low Read 0 Source of prior reset was not CNVSTRO 1 Source of prior reset was CNVSTRO CORSEF Comparator0 Reset Enable and Flag Write 0 Comparator0 is not a reset source 1 Comparator0 is a reset source active low Read 0 Source of last reset was not Comparatoro 1 Source of last reset was Comparatoro SWRSF Software Reset Force and Flag Write 0 No effect o 1 Forces an internal reset RST pin is not effected Read 0 Source of last reset was not a write to
14. The Mode 1 baud rate equations are shown below where T1M is bit4 of register CKCON TH1 is the 8 bit reload register for Timer 1 and RCAPnH RCAPnL is the 16 bit reload register for Timer 2 3 or 4 Equation 21 1 Mode 1 Baud Rate using Timer 1 When SMODO 0 Model_BaudRate 1 32 Timer1_OverflowRate When SMODO 1 Model BaudRate 1 16 Timerl OverflowRate ES Rev 1 4 289 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 The Timer 1 overflow rate is determined by the Timer 1 clock source T1CLK and reload value TH1 The frequency of T1CLK is selected as described in Section 23 1 Timer 0 and Timer 1 on page 309 The Timer 1 overflow rate is calculated as shown in Equation 21 2 Equation 21 2 Timer 1 Overflow Rate Timer1_OverflowRate TICLK 256 TH1 When Timers 2 3 or 4 are selected as a baud rate source the baud rate is generated as shown in Equation 21 3 Equation 21 3 Mode 1 Baud Rate using Timer 2 3 or 4 Mode1_BaudRate 1 16 Timer234 OverflowRate The overflow rate for Timer 2 3 or 4 is determined by the clock source for the timer TnCLK and the 16 bit reload value stored in the RCAPn register n 2 3 or 4 as shown in Equation 21 4 Equation 21 4 Timer 2 3 or 4 Overflow Rate Timer234 OverflowRate TnCLK 65536 RCAPn 290 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 21 1 3 Mode 2 9 Bit UART F
15. Transmitted by R READ SMBus Interface SLA Slave Address Figure 19 5 Typical Master Receiver Sequence 262 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 19 3 3 Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit If the received slave address matches the address held in register SMBOADR the SMBuso interface generates an ACK SMBus0 will also ACK if the general call address 0x00 is received and the General Call Address Enable bit SMBOADR 0 is set to logic 1 In this case the data direction bit R W will be logic 1 to indicate a READ operation The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial data waiting for an ACK from the master after each byte SMBusO exits slave mode after receiving a STOP condition from the master Received by SMBus S START Interface P STOP N NACK E R READ Transmitted by SLA Slave Address SMBus Interface Figure 19 6 Typical Slave Transmitter Sequence 19 3 4 Slave Receiver Mode Serial data is received on SDA while the serial clock is received on SCL The SMBuso0 interface receives a START followed by data byte containing the slave address and direction bit If the received slave address matches the address held in register SMBOADR the interface gene
16. ADCOLTH ADCOLTL 0x1000 ADCOGTH ADCOGTL OxFFFO An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt 0x1000 and gt OxFFFO 2s complement math Input Voltage ADO 0 ADO 1 REF x 2047 2048 ADOWINT 1 REF x 256 2048 0x1000 ADCOGTH ADCOGTL ADOWINT not affected OxOFFO Ox0000 J OxFFFO ADCOLTH ADCOLTL ADOWINT 1 Given AMXOSL 0x00 AMXOCF 0x01 ADOLJST 1 ADCOLTH ADCOLTL OxFFFO ADCOGTH ADCOGTL 0x1000 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt OxFFFO or gt 0x1000 2s complement math Figure 5 9 12 Bit ADCO Window Interrupt Example Left Justified Differential Data SILICON LABORATORIES Rev 1 4 71 C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Table 5 1 12 Bit ADCO Electrical Characteristics C8051F120 1 4 5 Vpp 3 0 V AV 3 0 V VREF 2 40 V REFBE 0 PGA Gain 1 40 to 85 C unless otherwise specified Parameter Conditions DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient 0 25 ppm C Dynamic Performance 10 kHz sine wave input 0 to 1 dB below Full Scale 100 ksps Signal to Noise Plus Distortion 66 dB Total Harmonic Dis
17. R W R W RIW RIW RIW RIW RIW RIW Reset Value PLLICO1 PLLICOO PLLLP3 PLLLP2 PLLLP1 PLLLPO 00110001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x8F SFR Page F Bits 7 6 UNUSED Read 00b Write don t care Bits 5 4 PLLICO1 0 PLL Current Controlled Oscillator Control Bits Selection is based on the desired output frequency according to the following table PLL Output Clock PLLICO1 0 65 100 MHz 00 45 80 MHz 01 30 60 MHz 10 25 50 MHz 11 Bits 3 0 PLLLP3 0 PLL Loop Filter Control Bits Selection is based on the divided PLL reference clock according to the following table Divided PLL Reference Clock PLLLP3 0 19 30 MHz 0001 12 2 19 5 MHz 0011 7 8 12 5 MHz 0111 5 8 MHz 1111 Table 14 2 PLL Frequency Characteristics 40 to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Input Frequenc m p q y 5 30 MHz Divided Reference Frequency PLL Output Frequency 25 100 MHz Note The maximum operating frequency of the C8051F124 5 6 7 is 50 MHz ES Rev 1 4 195 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Table 14 3 PLL Lock Timing Characteristics 40 to 85 C unless otherwise specified Input Multiplier PILOfIt Output Min Typ Max Units Freguency PIlOmul Setting Freguency 20 0x0F 100 MHz 202 us 13 OxOF 65
18. minimum settling time of 1 5 us is required after any MUX or PGA selection Note that in low power track ing mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR clocks will meet the tracking requirements Where 2 c DE X RroraL CSAMPLE Eguation 6 1 ADCO Settling Time Reguirements SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB tis the reguired settling time in seconds Rrora is the sum of the ADCO MUX resistance and any external source resistance n is the ADC resolution in bits 10 Differential Mode MUX Select AINO x Pl o Ruux 5k Compre 10pF RC npu Rmux kg CsamPLE 1L TU Csampre 10pF AINOy DJ o gre Ruux 5k MUX Select Single Ended Mode MUX Select AINO x x ING SC 10pF 7 SAMPLE RC Input R MUX Figure 6 4 ADCO Equivalent Input Circuits SILICON LABORATORIES Rev 1 4 11 C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 SFR Definition 6 1 AMXOCF AMUX0 Configuration SFR Page O SFR Address OXBA R W R W R W R W R W R W R W R W Reset Value 3 AIN67IC AIN45IC AIN23IC AINO1IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 4 UNUSED Read 0000b Write don t care Bit3 AIN67IC AINO 6 AINO 7 Input Pair Configuration Bit 0 AINO 6 and AINO 7 are independe
19. v Flag Logic MACO Rounding Register MACORNDH MACORNDL MACOSTA Figure 1 10 MACO Block Diagram ES Rev 1 4 31 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 1 5 Programmable Digital UO and Crossbar The standard 8051 8 bit Ports 0 1 2 and 3 are available on the MCUs The devices in the larger 100 pin TQFP packaging have 4 additional ports 4 5 6 and 7 for a total of 64 general purpose port I O The Port I O behave like the standard 8051 with a few enhancements Each Port I O pin can be configured as either a push pull or open drain output Also the weak pullups which are normally fixed on an 8051 can be globally disabled providing additional power saving capabili ties for low power applications Perhaps the most unique enhancement is the Digital Crossbar This is a large digital switching network that allows mapping of internal digital system resources to Port I O pins on PO P1 P2 and P3 See Figure 1 11 Unlike microcontrollers with standard multiplexed digital I O all combinations of functions are supported The on chip counter timers serial buses HW interrupts ADC Start of Conversion inputs comparator out puts and other digital signals in the controller can be configured to appear on the Port I O pins specified in the Crossbar Control registers This allows the user to select the exact mix of general purpose Port I
20. 1 ADCOLTH ADCOLTL 0x2000 ADCOGTH ADCOGTL 0x1000 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt 0x2000 and gt 0x1000 Input Voltage ADO O AGND REF x 1023 1024 ADC Data Word ADWINT 1 REF x 512 1024 0x8000 ADCOGTH ADCOGTL Ox7FCO ADWINT 0x4040 not affected 0x4000 REF x 256 1024 ADCOLTH ADCOLTL ADWINT 1 Given AMXOSL 0x00 AMXOCF 0x00 ADOLJST 1 ADCOLTH ADCOLTL 0x1000 ADCOGTH ADCOGTL 0x2000 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 gt if the resulting ADCO Data Word is lt 0x1000 or gt 0x2000 Figure 6 8 10 Bit ADCO Window Interrupt Example Left Justified Single Ended Data 88 Rev 1 4 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Input Voltage ADC Data ADO O ADO 1 Word REF x 511 512 Ox7FCO ADWINT not affected Sep e A EE REF x 128 512 0x2000 ADCOLTH ADCOLTL ADWINT 1 REFx 1 512 OxFFCO ADCOGTH ADCOGTL OxFF80 ADWINT not affected REF 0x8000 Given AMXOSL 0x00 AMXOCF 0x01 ADOLJST 1 ADCOLTH ADCOLTL 0x2000 ADCOGTH ADCOGTL OxFFCO An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt 0x2000 and gt OxFFCO 2s complement math Input Volt
21. 1d OxFFFO VREF 2 OxFCO0 1024d OxC000 VREF OxF800 2048d 0x8000 For ADOLJST 0 i Gain Code Vin x x 211 n 12 for Single Ended n 11 for Differential VREF S Figure 5 5 ADCO Data Word Example ES Rev 1 4 65 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 5 3 ADCO Programmable Window Detector The ADCO Programmable Window Detector continuously compares the ADCO output to user programmed limits and notifies the system when an out of bound condition is detected This is especially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster system response times The window detector interrupt flag ADOWINT in ADCOCN can also be used in polled mode The high and low bytes of the reference words are loaded into the ADCO Greater Than and ADCO Less Than registers ADCOGTH ADCOGTL ADCOLTH and ADCOLTL Reference comparisons are shown starting on page 68 Notice that the window detector flag can be asserted when the measured data is inside or out side the user programmed limits depending on the programming of the ADCOGTx and ADCOLTx registers SFR Definition 5 7 ADCOGTH ADCO Greater Than Data High Byte SFR Page O SFR Address OXC5 R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Bits7 0 High byte of ADCO Greater Than Data Word
22. 25 2 Flash Programming Commands The Flash memory can be programmed directly over the JTAG interface using the Flash Control Flash Data Flash Address and Flash Scale registers These Indirect Data Registers are accessed via the JTAG Instruction Register Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the IR register Each read or write is then initiated by writing the appropriate Indirect Operation Code IndOpCode to the selected data register Incoming commands to this register have the following format 19 18 17 0 IndOpCode WriteData IndOpCode These bit set the operation to perform according to the following table IndOpCode Operation Ox Poll 10 Read 11 Write The Poll operation is used to check the Busy bit as described below Although a Capture DR is performed no Update DR is allowed for the Poll operation Since updates are disabled polling can be accomplished by shifting in out a single bit The Read operation initiates a read from the register addressed by the DRAddress Reads can be initiated by shifting only 2 bits into the indirect register After the read operation is initiated polling of the Busy bit must be performed to determine when the operation is complete The write operation initiates a write of WriteData to the register addressed by DRAddress Registers of any width up to 18 bits can be written If the registe
23. AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 AD2CMO AD2WINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit7 AD2EN ADC2 Enable Bit 0 ADC2 Disabled ADC2 is in low power shutdown 1 ADC2 Enabled ADC2 is active and ready for data conversions Bit6 AD2TM ADC2 Track Mode Bit 0 Normal Track Mode When ADC is enabled tracking is continuous unless a conversion is in process 1 Low power Track Mode Tracking Defined by AD2CM2 0 bits see below Bit5 AD2INT ADC2 Conversion Complete Interrupt Flag This flag must be cleared by software 0 ADC2 has not completed a data conversion since the last time this flag was cleared 1 ADC2 has completed a data conversion Bit4 AD2BUSY ADC2 Busy Bit Read 0 ADC2 Conversion is complete or a conversion is not currently in progress AD2INT is set to logic 1 on the falling edge of AD2BUSY 1 ADC2 Conversion is in progress Write 0 No Effect 1 Initiates ADC2 Conversion if AD2CM2 0 000b Bits3 1 AD2CM2 0 ADC2 Start of Conversion Mode Select AD2TM 0 000 ADC2 conversion initiated on every write of 1 to AD2BUSY 001 ADC2 conversion initiated on overflow of Timer 3 010 ADC2 conversion initiated on rising edge of external CNVSTR2 011 ADC2 conversion initiated on overflow of Timer 2 1xx ADC2 conversion initiated on write of 1 to ADOBUSY synchronized with ADCO soft ware commanded conversions AD2TM 1 000 Tracking initiated on write of 1 to AD2BUSY for 3 SAR2 clo
24. ADCO track and hold and PGAO is enabled only when the ADOEN bit in the ADCO Control register ADCOCN is set to logic 1 The ADCO subsystem is in low power shutdown when this bit is logic 0 ADCOGTH ADCOGTL ADCOLTH ADCOLTL 24 Comb LA ADOWINT AINO O AINO 1 AINO 2 AINO 3 AINO 4 AINO 5 AINO 6 AINO 7 ADOBUSY W H Timer 3 Overflow E A A SE pad I CNVSTRO a MO olojojo iaaa er loo lv 4 lo Z zz zlo 11 Timer 2 Overflow Claes iss LB Yo Est ko tulo sebo Anal JE Z lt mol 3 zzz lt I lt I lt lt Slolololol jaja Sos oojslolo z aialale gt a alalala z naaalaala O ll Paba kakakakakapaaakakakakagakagaga 2 AMXOCF AMXOSL ADCOCF ADCOCN lt Figure 5 1 12 Bit ADCO Functional Block Diagram 5 1 Analog Multiplexer and PGA Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected to an on chip temperature sensor temperature transfer function is shown in Figure 5 2 AMUX input pairs can be programmed to operate in either differential or single ended mode This allows the user to select the best measurement technigue for each input channel and even accommodates mode changes on the fly The AMUX defaults
25. C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 5 Select the memory mode on chip only split mode without bank select split mode with bank select or off chip only 6 Setup timing to interface with off chip memory or peripherals Each of these five steps is explained in detail in the following sections The Port selection Multiplexed mode selection and Mode bits are located in the EMIOCF register shown in SFR Definition 17 2 17 3 Port Selection and Configuration The External Memory Interface can appear on Ports 3 2 1 and O All Devices or on Ports 7 6 5 and 4 100 pin TQFP devices only depending on the state of the PRTSEL bit EMIOCF 5 If the lower Ports are selected the EMIFLE bit XBR2 1 must be set to a 1 so that the Crossbar will skip over P0 7 WR PO 6 RD and if multiplexed mode is selected P0 5 ALE For more information about the configuring the Crossbar see Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 238 The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latches or to the Crossbar on Ports 3 2 1 and 0 See Section 18 Port Input Output on page 235 for more information about the Crossbar and Port operation and configuration The Port latches should be explicitly configured to park
26. Capture Mode 1 to 0 Transition on TnEX pin causes RCAPnH RCAPnL to capture timer value Auto Reload Mode DCENN 0 1 to 0 transition causes reload of timer and sets the EXFn Flag DCEMn 1 TnEX logic level controls direction of timer up or down Bit2 TRn Timer 2 3 and 4 Run Control This bit enables disables the respective Timer 0 Timer disabled 1 Timer enabled and running counting Bit1 C Tn Counter Timer Select 0 Timer Function Timer incremented by clock defined by TnM1 TNMO TMRNCF 4 TMRNCF 3 1 Counter Function Timer incremented by high to low transitions on external input pin Bit0 CP RLn Capture Reload Select This bit selects whether the Timer functions in capture or auto reload mode 0 Timer is in Auto Reload Mode 1 Timer is in Capture Mode Note Timer 3 and Timer 2 share the T2 and T2EX pins ES Rev 1 4 321 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 SFR Definition 23 9 TMRnCF Timer 2 3 and 4 Configuration R W R W R W R W R W Reset Value TnM1 TnMO TOGn TnOE DCENn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address TMR2CF 0xC9 TMR3CF 0xC9 TMR4CF 0xC9 SFR Page TMR2CF page 0 TMR3CF page 1 TMR4CF Page 2 Bit7 5 Reserved Bit4 3 TnM1 and TnMO Timer Clock Mode Select Bits Bits used to select the Timer clock source The sources can be the System Clock SYSCLK SYSCLK divided by 2 or
27. IRD PO 6 P4 6 ALE PO5IP45 V MR PO 7 P4 7 Y Figure 17 8 Multiplexed 8 bit MOVX without Bank Select Timing ES Rev 1 4 231 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 17 6 2 3 8 bit MOVX with Bank Select EMIOCF 4 2 010 Muxed 8 bit WRITE with Bank Select ADDR 15 8 P2 P6 P2 P6 AD 7 0 P3 P7 P3 P7 RD P0 6 P4 6 ALE PO 5 P4 5 y PO 5 P4 5 Ta MR PO 7 P4 7 y Y PO 7 P4 7 Muxed 8 bit READ with Bank Select ADDR 15 8 P2 P6 AD 7 0 P3 P7 ALE PO 5 P4 5 PO 5IP4 5 MR P0 7 P4 7 Figure 1 17 9 Multiplexed 8 bit MOVX with Bank Select Timing 232 Rev 1 4 ES SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Table 17 1 AC Parameters for External Memory Interface Parameter Description Address Control Setup Time 3X TsySCLK Address Control Pulse Width 1XTsyscix 16 x Tsyscik Address Control Hold Time 0 3 x TsySCLK Address Latch Enable High Time 1xTsyscik 4XTsyscik Address Latch Enable Low Time 1xTsyscik 4X Tsyscik Write Data Setup Time 1xTsyscik 19XTsyscik Write Data Hold Time 3 X TsySCLK Read Data Setup Time Read Data Hold Time Note Tsyscig is equal to one period of the device system clock SYSCLK ES Rev 1 4 233 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3
28. POMDOUT P1MDOUT P2MDOUT P3MDOUT Priority Decoder PCA Comptr Outputs ISYSCLK divided by 1 2 4 or 8 gt NVSTRO 2 27 Digita Crossbar H Figure 18 2 Port I O Functional Block Diagram SILICON LABORATORIES To External Memory Interface EMIF Rev 1 4 External Pins ET Highest Priority 1 Lowest 1 Priority gt 237 C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 18 1 Ports 0 through 3 and the Priority Crossbar Decoder The Priority Crossbar Decoder or Crossbar allocates and assigns Port pins on Port O through Port 3 to the digital peripherals UARTs SMBus PCA Timers etc on the device using a priority order The Port pins are allocated in order starting with PO O and continue through P3 7 if necessary The digital peripher als are assigned Port pins in a priority order which is listed in Figure 18 3 with UARTO having the highest priority and CNVSTR2 having the lowest priority 18 1 1 Crossbar Pin Assignment and Allocation The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in the Crossbar configuration registers XBRO XBR1 and XBR2 shown in SFR Definition 18 1 SFR Definition 18 2 and SFR Definition 18 3 For example if the UARTOEN bit XBRO 2 is set to a logic 1 the TXO and RXO pins will be mapped to PO O
29. and START STOP control and generation 2 SFR Bus SMBOCN SMBOSTA SMBOCR B E S S S A F T SSIS SISI SISS CCS lee eee U NITITIIJA TIO ia ila ela pe ff ae R R R R R RIR R S S AJO El AJAJAJAJAJAJAJA 5 4 3 2 1 0 Y M 7 6 5 4 3 2 1 0 B tt Clock Divide Logic iq SYSCLK sek Fire kA SMBUS CONTROL LOGIC YA ne e Arbitration SMBUS Interrupt e SCL Synchronization SCL far IRQ d Request e Status Generation Control gt gt UN e SCL Generation Master Mode NG I e IRQ Generation O l Data Path SDA Control Control A c GE S rs Port UO i S A B S A al ZN ZS LA i R it ora 8 l H v A SMBODAT ES SDA ER 7 6 5 4 3 2 1 0 lt lt FILTER 4 9 1111111 e y pa 8 8 s s s s s s s gt Or In Ee eee ee VJ vivivivivivivio p 6 s 4 3 2 1 o c Read E SMBOADR a otter Ae ae z SFR Bus Figure 19 1 SMBus0 Block Diagram ES Rev 1 4 259 SILICON LABORATORIES C8051F120 1 2 3 4 5 6 7 C8051F130 1 2 3 Figure 19 2 shows a typical SMBus configuration The SMBus0 interface will work at any voltage between 3 0 and 5 0 V and different devices on the bus may operate at different voltage levels The
30. in assembly CLR EA clear EA bit CLR EA this is a dummy instruction with two byte opcode If an interrupt is posted during the execution phase of a CLR EA opcode or any instruction which clears the EA bit and the instruction is followed by a single cycle instruction the interrupt may be taken How ever a read of the EA bit will return a U inside the interrupt service routine When the CLR EA opcode is followed by a multi cycle instruction the interrupt will not be taken Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR However most are not cleared by

SILICON LABORATORIES C8051F130/1/2/3 User Manual

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