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LINEAR TECHNOLOGY - LTC4258 handbook

1. 602 612 EN 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 10 668 MIN 7 416 7 747 10 160 10 414 400 410 Y r O00 0 520 0 0635 Le gt lt 0 800 TYP RECOMMENDED SOLDER PAD LAYOUT Y 7 417 7 595 1234567 8 9 101112131415 1617 18 292 299 2 463 2 641 2 286 2 387 0 254 0 408 pron saa 090 094 010 016 g lt WEIT 0 8 TYP 0 231 0 3175 0 610 1 016 0 800 0 304 0 431 0 127 0 305_ 0097 0125 024 040 0315 P I I lt 012 017 005 0115 BSC NOTE 1 CONTROLLING DIMENSION MILLIMETERS DIMENSION DOES NOT INCLUDE MOLD FLASH MOLD FLASH 2 DIMENSIONS ARE IN MILLIMETERS SHALL NOT EXCEED 0 152mm 0 006 PER SIDE GW36 SSOP 0502 INCHES DIMENSION DOES NOT INCLUDE INTERLEAD FLASH INTERLEAD FLASH SHALL NOT EXCEED 0 254mm 0 010 PER SIDE 4258fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable y TAR However no responsibility is assumed for its use Linear Technology Corporation makes no represen TECHNOLOGY tation that the interconnection ofits circuits as described herein will not infrin
2. Disconnect Enable Address 13h Disconnect Enable Register Read Write The lower four bits of this register enable or disable DC disconnect detection circuitry at the corresponding port If the DC Discon Enable bit is set the port circuitry will turn off power if the current draw at the port falls below Imn for more than tps Imin is equal to Viyiy Rs where Rg is the sense resistor and should be 0 5Q for IEEE 802 3af compliance If the bit is clear the port will not remove power due to low current Detect Class Enable Address 14h Detection and Clas sification Enable Read Write The lower four bits of this reg ister enable the detection circuitry atthe corresponding port ifthat portis in Auto or Semiauto mode The upper four bits enable the classification circuitry atthe corresponding port if that port is in Auto or Semiauto mode In manual mode setting a bit in this register will cause the LTC4258 to per form one classification or detection cycle on the corre sponding port Writing to the Detect Class Restart PB 18h has the same effect without disturbing the Detect Class Enable bits for other ports Timing Config Address 16h Global Timing Configuration Read Write Bits 0 1 program tpjs the time duration before a port is automatically tuned off after the PD is removed Bits 2 3 program be the time during which a porte current can exceed leur without it being turned off If the current is still above Jeu after Deum the LTC
3. LIC4258 APPLICATIONS INFORMATION IEEE 802 3af COMPLIANCE AND EXTERNAL COMPONENT SELECTION The LTC4258 is designed to control power delivery in IEEE 802 3af compliant Power Sourcing Equipment PSE Because proper operation of the LTC4258 may depend on external signals and power sources like the 48V supply Vee external components such as the sense resistors Rs and possibly software running onan external micro processor using the LTC4258 ina PSE does not guarantee 802 3af compliance Using an LTC4258 does get you most of the way there This section discusses the rest of the elements that go along with the LTC4258 to make an 802 3af complaint PSE Each paragraph below addresses a component which is critical for PSE compliance as well as possible pitfalls that can cause aPSE to be noncompliant For further assistance please contact Linear Technology s Applications department Sense Resistors The LTC4258 is designed to use a 0 5Q sense resistor Rs to monitor the current through each port The value of the sense resistor has been minimized in order to reduce power loss and as a consequence the voltage which the LTC4258 must measure is small Each port may be draw ing up to 450mA with this current flowing through the sense resistor and associated circuit board traces To prevent parasitic resistance on the circuit board from obscuring the voltage drop across the sense resistor the LTC4258 must Kelvin sense the res
4. 0 Figure 4 e 150 180 200 ms tpisi 1 tpiso 1 Figure 4 e 600 720 800 ms tvMIN DC Disconnect Minimum Pulse Vsensen Veg gt SMV VourTn 48V Figure 4 e 0 02 1 ms Width Sensitivity Note 9 VC Timing fscLK Clock Frequency Note 9 e 400 kHz ty Bus Free Time Figure 5 Notes 9 10 e 13 us to Start Hold Time Figure 5 Notes 9 10 e 600 ns t3 SCL Low Time Figure 5 Notes 9 10 e 13 us t4 SCL High Time Figure 5 Notes 9 10 e 600 ns ts Data Hold Time Figure 5 Notes 9 10 e 150 ns tg Data Set Up Time Figure 5 Notes 9 10 e 200 ns t7 Start Set Up Time Figure 5 Notes 9 10 e 600 ns tg Stop Set Up Time Figure 5 Notes 9 10 e 600 ns tr SCL SDAIN Rise Time Figure 5 Notes 9 10 e 20 300 ns tf SCL SDAIN Fall Time Figure 5 Notes 9 10 e 20 150 ns teLTINT Fault Present to INT Pin Low Notes 9 10 11 e 20 150 ns tstopint Stop Condition to INT Pin Low Notes 9 10 11 e 60 200 ns taRAINT ARA to INT Pin High Time Notes 9 10 e 20 300 ns Note 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime Note 2 DGND and AGND should be tied together in normal operation Note 3 An internal clamp limits the GATE pins to a minimum of 12V above Vee Driving this pin beyond the clamp may damage the part Note 4 This IC includes overtemperature prote
5. TECHNOLOGY PD LIC4258 Quad IEEE 802 3af Power over Ethernet Controller FEATURES Controls Four Independent 48V Powered Ethernet Ports Each Port Includes IEEE 802 3af Compliant PD Detection and Classification Output Current Limit with Foldback Short Circuit Protection with Fast Gate Pull Down PD Disconnect Using DC Sensing Power Good Indication Operates Autonomously or by CH Control 4 Bit Programmable Digital Address Allows Control of Up to 64 Ports Programmable INT Pin Eliminates Software Polling Current and Duty Cycle Limits Protect External FETs Available in a 36 Pin SSOP Package APPLICATIONS m EEE 802 3af Compliant Endpoint and Midspan Power Sources m P Phone Systems m DTE Power Distribution CT LT LTC and LTM are registered trademarks of Linear Technology Corporation Hot Swap is a registered trademark of Linear Technology Corporation All other trademarks are the property of their respective owners with Integrated Detection DESCRIPTION The LTC 4258 is a quad 48V Hot Swap controller de signed for use in IEEE 802 3af compliant Power Sourcing Equipment PSE Itconsists of four independent ports each with output current limit short circuit protec tion complete Powered Device PD detection and classi fication capability and programmable PD disconnect using DC sensing Used with power MOSFETs and passives as in Figure 1 the LTC4258 can implement a comp
6. 30 20 LTAGE V 10 0 4258 G09 4258fb AY MUR S LIC4258 TEST TIMING PD INSERTED VporTn OV es U L d PORT Te Vr E TURN ON VGATEn VEE AUTO MODE INT s sees a eae ee tcLsDLy g ae tCLASS 4258 F02 lt DETDLY gt lt tron gt Figure 2 Detect Class and Turn On Timing in Auto or Semiauto Modes VLIM Vout V VSENSEn TO Ver SE Vum ov lt sTART hem INT INT 4258 F04 4258 F03 Figure 3 Current Limit Timing Figure 4 DC Disconnect Timing gt oke E e E e 4258 FOS Figure 5 12C Interface Timing TIMING DIAGRAMS SCL CEE TT ST EIST TIES TT eT nS IL s o s Vkkrikcrkedeg a ar kaska ku kue kuku kue ed er oe os Kose Noe Ac Aen fy X START BY Y ACK BY ACK BY Z ACKBY 4 STOPBY MASTER SLAVE SLAVE SLAVE MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS ADDRESS BYTE 1 REGISTER ADDRESS BYTE Se DATA BYTE a Figure 6 Writing to a Register 1 111111111111111111111111111111111111111111111111111111 I ey eT nad td TT son X s NARAR RA aoe eka KS kuku ka kuya ed Xo RRRA o o7 oe os usus eX A NA Y START BY lt ACKBY ACKBY Z X REPEATED ACK BY NOACKBY Z STOP BY MASTER SLAVE SLAVE START BY SLAVE MASTER MASTER MASTER FRAME 1 FRAME 2 FRAME 1 FRAME 2 S SERIAL BUS ADDRESS BYTE ge REGISTER ADDRESS BYTE R SERIAL BUS ADDRESS BYTE S DATA BYTE Ge Figure 7 Reading from a Register 4258fb 6 LI MUR LIC4258 TIMING DIAGRAMS SCL
7. Bit 7 indicates thatthe LTC4258 die temperature has exceeded its thermal shutdown limit see Note 4 under Electrical Characteris tics The logical OR of bits 4 5 and 7 appears in the Inter rupt register as the Supply Fault bit The remaining bits in 4258fb 10 LS MUR LIC4258 REGISTER FUNCTIONS the register are reserved and will always read as 0 The Supply Event bits latch high and will remain high until cleared by reading from address OBh Supply Event CoR Address OBh Supply Event Register Clear on Read Read this address to clear the Fault Event register Address OBh returns the same dataas address 0Ah and reading address OBh clears all bits at both addresses Status Registers Port 1 Status Address OCh Port 1 Status Register Read Only This register reports the most recent detection and classification results for port 1 Bits 0 2 report the status ofthe mostrecent detection attempt atthe portand bits 4 6 report the status of the most recent classification attempt at the port If power is on these bits report the detection classification status present just before power was turned on If power is turned off at the port for any reason all bits inthis register will be cleared See Table 1 for detection and classification status bit encoding Port 2 Status Address 0Dh Port 2 Status Register Read Only See Port 1 Status Port 3 Status Address OEh Port 3 Status Register Read Only See Port 1 Statu
8. for the affected port s Reset PB Address 1Ah Reset Pushbutton Write Only Bits 0 3 reset the corresponding port by clearing the power enable bit the detect and fault event bits the status regis ter and the detection and classification enable bits for that port Bit 4 returns the entire LTC4258 to the power on reset state all ports are turned off the AUTO pin is reread and all registers are returned to their power on defaults except Vpp UVLO which remains cleared Bit 5 is reserved setting it has no effect Setting bit 6 releases the Interrupt pin if it is asserted without affecting the Event registers or the Interrupt register When the INT pin is released in this way the condition causing the LTC42568 to pull the INT pin down must be removed before the LTC4258 will be able to pull INT down again This can be done by reading and clearing the event registers or by writing a 1 into bit 7 of this register Setting bit 7 releases the Interrupt pin clears allthe Event registers and clears all the bits in the Interrupt register 4258fb 12 LI MUR LIC4258 APPLICATIONS INFORMATION OVERVIEW Over the years twisted pair Ethernet has become the most commonly used method for local area networking The IEEE 802 3 group the originator of the Ethernet standard has defined an extension to the standard known as 802 3af which allows DC power to be delivered simulta neously over the same cable used for data communica ti
9. occurs again The undercurrent circuit includes a glitch filter to filter out noise The DC disconnect feature can be disabled by clearing the corresponding DC Discon Enable bits in the Disconnect register 13h The tpjs timer duration can be programmed by bits 1 and 0 of register 16h The LTC4258 implements a variety of current sense and limit thresholds to control current flowing through the port Figure 16 is a graphical representation of these thresholds and the action the LTC4258 takes when currrent crosses the thresholds 4 CURRENT LIMIT 300mV 600mA y IN tus rom OFF IN teyt t START _ CURRENT LIMIT 250mV 500mA 200mV 400mA A 150mV 300mA NORMAL 100mV 200mA OPERATION 50mV 100mA Y PORT OFF IN tpis EFFECT CIRCUIT 4258 F14 OmV 0mA SENSEn CURRENT DCDIS CUT VOLTAGE Rg 0 5Q CONNECT lcur Ium LIMIT SHORT Figure 16 LTC4258 Current Sense and Limits 4258fb 20 LI MUR LIC4258 APPLICATIONS INFORMATION SERIAL DIGITAL INTERFACE The LTC4258 communicates with a host master using the standard 2 wire interface as described in the SMBus Specification Version 2 0 available at http smbus org The SMBus is an extension of the 12C bus and the LTC4258 is also compatible with the 12C bus standard The Timing Diagrams Figures 5 through 9 show the timing relationship of the signals on the bus The two bus lines SDA and SCL must be high when the b
10. then makes this information available to the host controller which de cides to apply power or not Operating the LTC4258 in Manual mode also lets the controller decide whether to power the ports but the controller must also control detection and classification If the host controller oper ates near the limit of its computing resources it may not be able to guide a Manual mode LTC4258 through detect classification and port turn on in less than the IEEE mandated maximum of 950ms In a typical PSE the LTC4258s will operate in Semiauto mode as this allows the controller to decide to power a port without unduly burdening the controller With an interrupt mask of F4h the LTC4258 will signal to the host after it has successfully detected and classified a PD at which point the host can decide whether enough power is available and command the LTC4258 to turn that port on Similarly the LTC4258 will generate interrupts when a port s power is turned off By reading the LTC4258 s interrupt register the host can determine if a port was turned off due to overcurrent tstarT Or ticur faults or because the PD was removed Disconnect event The host then updates the amount of available power to reflect the power no longer consumed by the disconnected PD Setting the MSB ofthe interrupt mask causes the LTC4258 to communicate fault conditions caused by failures within the PSE so the host does not need to poll to check that the LTC4258s are opera
11. 3af to intermittent behavior and even to excessive voltages that may damage circuitry in both the PSE and PD connected to the ports Detect Pin Diodes During detection and classification the LTC4258 senses the port voltage through the detect diodes Dpzr Excessive voltage drop across Dprr will corrupt the LTC4258 s detect and classification results Select a diode for DpeT that will have less than 0 7V of forward drop at 0 4mA and less than 0 9V of forward drop at 50mA Power Supplies The LTC4258 must be supplied with 3 3V Vpp and 48V Ver Poor regulation on either of these supplies can lead to noncompliance The IEEE requires a PSE Output voltage between 44V and 57V When the LTC4258 begins powering an Ethernet port it controls the current through the port to minimize disturbances on Ver How ever if the Vee supply is underdamped or otherwise unstable its voltage could go outside of the IEEE specified limits causing all ports in the PSE to be noncompliant This scenario can be even worse when a PD is unplugged because the current can drop immediately to zero In both cases the port voltage must always stay between 44V and 57V In addition the 802 3af specification places specific ripple noise and load regulation requirements on the PSE Among other things disturbances on either Von Or Ver can adversely affect detection and classification sensing Proper bypassing and stability of the Von and Vg supplies is importa
12. ISIN YZL 0000 0000 0000 0000 osia LSI Dt HN 0luV1S Huv1S panesey p m s y lEqo wu Duo Du y9 0000 0000 0000 0000 panasay panasay panasay panasay panasay panasay panasay panasay WHY panasay UEL LLELLLLL 0000 0000 Lag pap am aan g qeug Paq rogeu oan Lou een ou een gaqeuzsseig pajqeuzsseig izer Wu lqgu3sse 9A338Q Uyt LLLL 0000 0000 0000 Lujuoosig 20 Zuquoosiqgd Cup ugceg 20 yug uoasia 90 panasey panasey panesay panasey L2ep WY ajqeuz yoauuodsiq UEL LLELLLLL 0000 0000 0 8DON HOd L OPO L und 0opow Z HOd L DOW ZHOd O PONEHOd L PONEHOd Dono Od LOPONpHOd L2er WHY apo Bune1 d0 yZ uoljeunbyuod Lo v y eyevo0 00 v y eyeyoo sn uld oyy panasey SNIS uld OGY SNIS uid Lay SNIS uld ZAY SNIS uld Edy panasey p m s y Ion Ou SNIS Uld ULL 0000 0000 0000 0000 L ap Bund Zajqeuzsemog op oun Fang Iound p009 Bund ZD009 49W0d C pop Iound pPooy Jamod Z p OH SNJEIS 1 MOd YOL 0000 0000 0000 0000 Dame ag Lameg aa Z SNIS oo panasey Dame sep Lampe gep Ssmkel ssp panesey v OH SNIS p Und YO 0000 0000 0000 0000 Dame ag snyeysyajeq Zsnl 11Q panasay Dame sep Lampe gep Z SeS sen Daugeon OY SNIS HOd 430 0000 0000 0000 0000 Dame oa Lange aan z snes 19340 Dougeon Damp sen Lengg sep Z snes sept panasey OY SNIS Z HOd YGO 0000 0000 0000 0000 Dame ag snes aa omg oo Daugeon Dame sep Lampe gep ZSMS s
13. a port is set by the appropriate bits in the Operating Mode register The LTC 4258 will power up with all ports in Shutdown mode if the external AUTO pin is tied low if AUTO is high all ports will wake up in Auto mode The operating mode can be changed at any time via the 12C interface regardless of the state of the AUTO pin e In Manual mode a port will wait for instructions from the host system before taking any action It will run Single detection or classification cycles when com manded and will report results in the Port Status registers When the host system decides it is time to turn on or off power to a port it can do so by setting the appropriate Power On Off bits in the Power Enable PB register regardless of the current status of detec tion or classification In Semiauto mode the port will repeatedly attempt to detect and classify a PD device attached to the link It will report this information in its Port Status register and wait for the host system to set the appropriate Power On bit in the Power Enable PB register before applying power to the port In Auto mode the port will detect and classify a PD device connected to it then immediately turn on the power if detection was successful regardless of the result of classification In Shutdown mode the portis disabled and will not detect or poweraPD Also the detect and fault event bits status bits and enable bits for the port are reset to zero Regardless of whic
14. at both ends and is sent differentially a voltage difference between the transmit pairs and the receive pairs does not affect the data A 10base T 100base TX Ethernet connection only uses 2 of the 4 pairs in the cable The unused or spare pairs can be powered directly as shown in Figure 10 without affecting the data However 1000base T uses all 4 pairs and power must be connected to the transformer center taps for compatibility PSE RJ45 ROUNDTRIP RJ45 PD CMPD3003 IRFM120A PE te 14 0 05uF M SPARE PAIR DATA PAIR DATA PAIR 1N4002 x4 I I 1N4002 4 GND DC DC 1 R PWRGD i CLASS CONVERTER LTC4257 I I I I J git a ei Sei iin ri ai i le Figure 10 PoE System Diagram 4258fb LS UE 13 LIC4258 APPLICATIONS INFORMATION The LTC4258 provides a complete solution for detection and powering of PD devices in an IEEE 802 3af compliant system The LTC4258 consists of four independent ports each with the ability to detect classify and provide iso lated 48V power to a PD device connected to it The LTC4258 senses removal of a PD with IEEE 802 3af compliant DC method and turns off 48V power when the PD is removed An internal control circuit takes care of system configuration and timing and uses an 12C interface to communicate with the host system OPERATING MODES Each LTC4258 port can operate in one of four modes Manual Semiauto Auto or Shutdown The operating mode for
15. be con nected to the return from the 48V supply AGND and DGND should be tied together SENSE4 Pin 22 Port 4 Current Sense Input SENSE4 monitors the external MOSFET current via a 0 5Q sense resistor between SENSE4 and Ver Whenever the voltage across the sense resistor exceeds the overcurrent detec tion threshold Ve the current limit fault timer counts up If the voltage across the sense resistor reaches the current limit threshold Vi iu typically 25mV 50mA higher the GATE4 pin voltage is lowered to maintain constant current in the external MOSFET See Applications Information for further details If the port is unused the SENSE4 pin must be tied to Ver GATE4 Pin 23 Port 4 Gate Drive GATE4 should be connected to the gate of the external MOSFET for port 4 When the MOSFET is turned on a 50uA pull up current source is connected to the pin The gate voltage is clamped to 13V typ above Vee During a current limit condition the voltage at GATE4 will be reduced to maintain constant current through the external MOSFET If the fault timer expires GATE4 is pulled down with 50uA turning the MOSFET off and recording a ticuTr or tstarT event If the port is unused float the GATE4 pin or tie it to Ver OUT4 Pin 24 Port 4 Output Voltage Monitor OUT4 should be connected to the output port through a 10k series resistor A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current l
16. 4258 will in dicate a Deum fault and turn the port off Bits 4 5 program tstart the time duration before an overcurrent condition during port power on is considered a tstart fault and the portis turned off Note that using the Deum and tstart times other than the default is not compliant with IEEE 802 3af and may double or quadruple the energy dissipated by the external MOSFETs during fault conditions Bits 6 7 are re served and should be read written as 0 See Electrical Char acteristics for timer bit encoding Also see the Applications Information for descriptions of tstarz herr and DC discon nect timing 4258fb LS WIR 11 LIC4258 REGISTER FUNCTIONS Misc Config Address 17h Miscellaneous Configuration Read Write Setting bit 7 enables the INT pin If this bit is reset the LTC 4258 will not pull down the INT pin in any condition nor will it respond to the Alert Response Address This bit is set by default Pushbutton Registers Note Regarding Pushbutton Registers Pushbutton reg isters are specialized registers that trigger an event when a1 is written toa bit writing a0 toa bit will do nothing Unlike a standard read write register where setting a single bit involves reading the register to determine its status set ting the appropriate bit in software and writing back the entire register a pushbutton register allows a single bit to be written without knowing or affecting the status of the other bits in
17. 58 4258fb TABLE 1 REGISTER MAP panlesay LLL JUaIINIJGAQ LLL ynog ued OLL OSs0 OLL HOIHY LOL OSseg se peay p u apun LOL Dong 399420 00L Fest 00L reagewozny 19M0d pue sept og ony IL MOTH LLO SS0 LLO uoTnqusnd je 19591 u0 SIUM OM JEMOd UQ WN 0 EM Ing Sept pue 193190 ojnelwas OL p u s y OLO Zeep OLO peay uo 129 9 H09 Jo uid 13934 Aq jas you SI OTAN 0A SIE WU S8 81S U3 M BOURAPY JON INM enue LO AL gt unono uoys 400 Sselg 100 dn 1u6nouq ae s llddns 334 pue 004 u0 peel OY HO Sept pue uona 4O JaMod umopynys 00 umouyun sns Dag 000 umouyun sns ssei 000 y U9IUA Ul Japso ay UO spu d p 10 Aen DNI003N3 1I8 IQON SNLYLS 193130 SNLYLS SSV19 OTAN FPA out 40 ges dn uels UL Bupoau Sdn gu 0000 0000 0000 0000 HOd ou Z Und Jost HOg Josey p Od ou lly 13594 pauasay uld ng 12319 IIV 12919 qog OM gd 19994 UYL 0000 0000 0000 0000 UQ Bund UO 19 0d UO 19 0d Y UQ 13M0d L HO Jamog Z HO Jamog HO 13M0d FU Bund Leh OM gd oU Jamog U6 0000 0000 0000 0000 LJoajaq Hes y ga usa Cat WeISAY p109 Upso Lesen WeIsay een up EsseiQueisey pSSEIQUEISEY izer OM dd Helsey s t UgL suoynqysnd ajqeuy 0000 0001 0000 0001 panesay peesay p ma s y p ma s y peasay peasay peasay uld Jdnuayuy qo MWY 61JU0D
18. ADO Pin 10 Address Bit 0 See ADS 4258fb LS UE n LIC4258 PIN FUNCTIONS DETECT1 Pin 11 Detect Sense Port 1 The LTC4258 Powered Device PD detection and classification hard ware monitors port 1 with this pin Connect DETECT1 to the output port via a low leakage diode see Figure 1 Ifthe port is unused the DETECT1 pin can be tied to AGND or allowed to float DETECT2 Pin 12 Detection Sense Port 2 See DETECT1 DETECTS Pin 13 Detection Sense Port 3 See DETECT1 DETECT4 Pin 14 Detection Sense Port 4 See DETECT1 DGND Pin 15 Digital Ground DGND should be con nected to the return from the 3 3V supply DGND and AGND should be tied together Vpp Pin 16 Logic Power Supply Connect to a 3 3V power supply relative to DGND Vpp must be bypassed to DGND near the LTC4258 with at least a 0 1uF capacitor SHDN1 Pin 17 Shutdown Port 1 Active Low When pulled low SHDN1 shuts down port 1 regardless of the State of the internal registers Pulling SHDN1 low is equivalent to setting the Reset Port 1 bit in the Reset Pushbutton register 1Ah Internal filtering of the SHDN1 pin prevents glitches less than 1s wide from reseting the LTC4258 Pull SHDN1 high with lt 10k or tie to Vpp SHDN2 Pin 18 Shutdown Port 2 Active Low See SHDN1 SHDN3 Pin 19 Shutdown Port 3 Active Low See SHDN1 SHDN4 Pin 20 Shutdown Port 4 Active Low See SHDN1 AGND Pin 21 Analog Ground AGND should
19. Ah The INT signal can be used to generate an interrupt to the host processor eliminating the need for continuous software polling Individual INT events can be disabled using the Int Mask register 01h See Register Functions and Applications Information for more information The INT pin is only updated between H transactions SCL Pin 4 Serial Clock Input High impedance clock input for the 12C serial interface bus The SCL pin should be connected directly to the 12C SCL bus line SDAOUT Pin 5 Serial Data Output Open Drain Data Output for the 12C Serial Interface Bus The LTC4258 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the 12C bus To implement a stan dard bidirectional SDA pin tie SDAOUT and SDAIN together See Applications Information for more information SDAIN Pin 6 Serial Data Input High impedance data input forthe 12C serial interface bus The LTC4258 uses two pins to implement the bidirectional SDA function to simplify optoisolation of the 12C bus To implement a standard bidirectional SDA pin tie SDAOUT and SDAIN together See Applications Information for more information AD3 Pin 7 Address Bit3 Tiethe address pins high or low to set the 2C serial address to which the LTC4258 re sponds This address will be 010A3ApA1Ag p Pull AD3 high or low with lt 10k or tie to Vpp or DGND AD2 Pin 8 Address Bit 2 See AD3 AD1 Pin 9 Address Bit 1 See AD3
20. ECTION PHASE 1 50ms DIV 4258 G01 Current Limit Foldback GND PORT VOLTAGE 20V DIV Powering On a 180uF Load Vpp 3 3V GATE VOLTAGE 10V DIV PORT CURRENT 500mA DIV FOLDBACK C 5ms DIV 425mA CHARGED URRENT LIMIT 4258 G02 INT and SDAOUT Pull Down Voltage vs Load Current 225 450 200 400 175 350 LLI _ 150 300 2 S 125 250 E Q w 2 100 200 fa a 8 gt 75 150 E gt re 5 a 50 F Voy 3 3V 100 Veg 48V 25 TA 25 C x 0 0 8 40 32 24 16 8 0 0 VouTn AGND V 4258 G03 Classification Transient Response to 40mA Load Step PORT _ VOLTAGE 1V DIV oO 18V I S S 40mA PORT A CURRENT lt 20mA DIV o OmA 50us DIV 4258 G07 Classification Current Compliance 0 Vpp 3 3V 2 f Veg 48V 4 Ta 25 C 6 8 10 12 14 PORT VOLTAGE WITH 16 TYPICAL CMPD3003 18 DETECTn 20 PIN VOLTAGE 0 10 20 30 40 5 60 70 CLASSIFICATION CURRENT mA 4258 G08 SUPPLY CURRENT mA 3 0 2 5 0 5 70 60 10 15 LOAD CURRENT mA Vee DC Supply Supply Voltage 20 25 4258 G06 urrent vs Vpp 3 3V REG 12h 00h 50 40 Vee SUPPLY VO
21. LTC4258 reports a Detect Good In this way the host controller implements a MOS FET cooling off period which may be programmed to protect smaller MOSFETs from repeated thermal cycling The LTC4258 has built in duty cycle protection for ticuT and tstart See ticur Timing and tstart Timing sections that is sufficient to protect the MOSFETs shown in Figure 1 Before designing a MOSFET into your system carefully compare its safe operating area SOA with the worst case conditions like powering up a defective PD the device will face Using transient suppressors polyfuses and ex tended wait times after disconnecting a PD are effective Strategies to reduce the extremes applied to the external MOSFETs Surge Suppressors and Circuit Protection IEEE 802 3af Power over Ethernet is achallenging Hot Swap application because it must survive the probably unin tentional abuse of everyone in the building While hot swapping boards in a networking or telecom card cage is done by a trained technician or network administrator anyone in the building can plug a device into the network Moreover in a card cage the physical domain being pow ered is confined to the card cage With Power over Ether net the PSE supplies power to devices up to 100 meters away Ethernet cables could potentially be cut shorted together and so on by all kinds of events from a contrac tor cutting into walls to someone carelessly sticking a screwdriver where it doesn t be
22. OR of these four bits appears in the Interrupt register as eier Fault bit The upper four bits indicate that a Dis connect event has occurred at the corresponding port the logical OR of these four bits appears in the Interrupt reg ister as the Disconnect bit The Fault Event bits latch high and will remain high until cleared by reading from address 07h Fault Event CoR Address 07h Fault Event Register Clear on Read Read this address to clear the Fault Event regis ter Address 07h returns the same data as address 06h and reading address 07h clears all bits at both addresses Leg Event Address 08h tstagr Event Register Read Only The lower four bits in this register indicate thata tsTART fault has occurred atthe corresponding port the logical OR of these four bits appears in the Interrupt register as the tstarT Fault bit The tstart Event bits latch high and will remain high until cleared by reading from address 09h The upper four bits in this register are reserved and will always read as 0 tstart Event CoR Address 09h tstart Event Register Clear on Read Read this address to clear the Fault Event register Address 09h returns the same data as address 08h and reading address 09h clears all bits at both addresses Supply Event Address OAh Supply Event Register Read Only Bit 4 indicates that Ver has dropped below the Ver UVLO level typically 28V Bit5 signals thatthe Vpp supply has dropped belowthe Von UVLO threshold
23. PRR K OP N oY TERRE AA A SDA of i o X START BY MASTER lt _ ACK BY NOACKBY Z STOP BY SLAVE MASTER MASTER FRAME 2 gt FRAME 1 SERIAL BUS ADDRESS BYTE DATA BYTE Figure 8 Reading the Interrupt Register Short Form SDA o o ofi 1 0 ofaa of 1 o faaan X START BY MASTER CK BY SLAVE MASTER ee FRAME 1 ALERT RESPONSE ADDRESS BYTE 1 ACK STOP BY MASTER NOACKBY Z FRAME 2 SERIAL BUS ADDRESS BYTE Figure 9 Reading from Alert Response Address PIN FUNCTIONS RESET Pin 1 Chip Reset Active Low When the RESET pin is low the LTC4258 is held inactive with all ports off and all internal registers reset to their power up states When RESET is pulled high the LTC4258 begins normal operation RESET can be connected to an external capaci tor or RC network to provide a power turn on delay Internal filtering of the RESET pin prevents glitches less than 1us wide from resetting the LTC4258 Pull RESET high with lt 10k or tie to Vpp BYP Pin 2 Bypass Output The BYP pin is used to connect the internally generated 20V supply to an exter nal 0 1uF bypass capacitor Use a 100V rated 0 1uF X7R capacitor Do not connect the BYP pin to any other external circuitry INT Pin 3 Interrupt Output Open Drain INT will pull low when any one of several events occur in the LTC4258 It will return to a high impedance state when bits 6 or 7 are set in the Reset PB register 1
24. TC4267 IEEE802 3af PD Interface with Integrated Switching 100V 400mA UVLO Switch Dual Inrush Current Programmable Regulator Classification 4258fb Linear Technology Corporation LT LWI REV B 1006 PRINTED IN USA 1630 McCarthy Blvd Milpitas CA 95035 7417 ell sl OGY 408 432 1900 FAX 408 434 0507 www linear com LINEAR TECHNOLOGY CORPORATION 2004
25. V to Veg 1V OUT sasana nunus Ver 70V to Ver 70V BYP Current a a aaa 0 1mA Operating Ambient Temperature Range 0 C to 70 C Junction Temperature Note 4 150 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 10 sec 300 C PACKAGE ORDER INFORMATION Tor vw ORDER PART ed e NUMBER e LTC4258CGW SENSE1 OUT2 GATE2 SENSE2 VEE 0UT3 GATE3 SENSE3 0UT4 GATE4 SENSE4 AGND SHDN4 SHDN3 SDAOUT SDAIN AD3 AD2 AD1 ADO DETECT DETECT2 DETECT3 DETECT4 DGND Vpp SHDN1 SHDN2 GW PACKAGE 36 LEAD PLASTIC SSOP Tax 150 C 0 ja 80 C W Order Options Tape and Reel Add TR Lead Free Add PBF Lead Free Tape and Reel Add TRPBF Lead Free Part Marking http www linear com leadfree Consult LTC Marketing for parts specified with wider operating temperature ranges ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at Ta 25 C AGND DGND OV Vpp 3 3V Veg 48V unless otherwise noted Note 5 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supplies Vpp Vpp Supply Voltage e 3 3 3 4 V VEE Vee Supply Voltage To Maintain IEEE Compliant Output Note 6 e 47 57 V Ipp Vpp Supply Current 2 5 5 mA leg Ver Supply Cu
26. acknowledge the Alert Response Address 0001100 b using the receive byte protocol The START and STOP Conditions When the bus is idle both SCL and SDA must be high A bus master typically the host controller signals the beginning of communication with a slave device like the LTC4258 by transmitting a START condition A START condition is generated by transitioning SDA from high to low while SCL is high A REPEATED START condition is functionally the same as a START condition but used to extend the protocol for a change in data transmission direction A STOP condition is not used to set up a REPEATED START condition for this would clear any data already latched in When the master has finished commu nicating with the slave itissues aSTOP condition ASTOP condition is generated by transitioning SDA from low to high while SCL is high The bus is then free for communi cation with another SMBus or 12C device 4258fb LS UE 21 LIC4258 APPLICATIONS INFORMATION TOD CONTROLLER fT ee e e SMBALERT GND CPU U1 FAIRCHILD NC7WZ17 U2 U3 AGILENT HCPL 063L 0 1uF 20092 ISOLATED 3 3V 10uF ISOLATED GND 0 1uF 4258 F15 Figure 17 Optoisolating the 12C Bus 12C ADDRESS 0100000 0100001 0100010 0101110 0101111 4258fb 22 LI WIR LIC4258 APPLICATIONS INFORMATION Acknowledge The Acknowledge signal is used for handshaking between th
27. af specification the PSE may or may not accept resistances in the two ranges of 15k to 19k and 26 5k to 33k Note that the black box in Figure 11 represents the 150Q pair to pair termination used in legacy 802 3 de vices like a computer s network interface card NIC that cannot accept power RESISTANCE 0Q 10k 20k 30k pf ft j fof jj fj 1 jy fy l l TTC PD MH509 NIC 23 75k 2625k PSE 15k h 26 5k 33k 4258 F11 Figure 11 IEEE 802 3af Signature Resistance Ranges 4258fb 14 LI MUR LIC4258 APPLICATIONS INFORMATION The LTC4258 checks for the signature resistance by forcing two test currents on the port via the DETECTn pins in Sequence and measuring the resulting voltages It then subtracts the two V I points to determine the resistive slope while removing voltage offset caused by any series diodes or current offset caused by leakage at the port see Figure 12 The LTC4258 will typically accept any PD resistance between 17k and 29k as a valid PD and report Detect Good 100 binary in the Detect Status bits bits 2 through 0 of the corresponding Port Status register Values outside this range including open and short cir cuits are also reported in the Detect Status bits Refer to Table 1 for a complete decoding of the Detect Status bits The first test point is taken by forcing a test current into the port waiting a short time to allow the line to settle and measuring the resulting voltage This result is
28. aten Ver DN e 30 300 uA len GATE Pin Short Circuit Pull Down VGATEn Veg 2V 50 mA AVGaTE External Gate Voltage Veaten Vee IGaTEn 1HA Note 3 e 10 13 15 V Output Voltage Sense Vpg Power Good Threshold Voltage Voutn VEE e 1 2 3 V lv0UT Out Pin Bias Current OV gt Voutn gt 10V e 6 uA 10V gt Voutn gt 30V e 18 uA Voutn 48V 20 uA Current Sense VcuT Overcurrent Detection Sense Voltage VsENSEn Vee Vout Ver Note 7 166 187 5 199 mV Vim Current Limit Sense Voltage VSENSEn Vee Voutn VEE 201 212 5 224 mV VsENSEn Vee Voutn AGND 30V 201 224 mV VSENSEn Vee VouTn AGND 10V 30 2 mV VMIN DC Disconnect Sense Voltage VSENSEn VEE 2 52 3 75 4 97 mV Vsc Short Circuit Sense Voltage 275 mV ISENSE SENSE Pin Bias Current VSENSEn VEE 50 uA Digital Interface Von Digital Output Low Voltage Ispaout SMA lint 3MA e 0 4 V IspaouT OMA lint 5MA e 0 7 V VILD Digital Input Low Voltage SCL SDAIN RESET SHDNn AUTO ADn e 0 8 V VIHD Digital Input High Voltage SCL SDAIN RESET SHDNn AUT0 ADn e 24 V Rpu Pull Up Resistor to Vpp ADn RESET SHDNn 50 kQ Rpp Pull Down Resistor to DGND AUTO 50 kQ AC Characteristics tpETDLY Detection Delay From Detect Command or Application of PD to Port 170 590 ms to Detect Complete Figure 2 DET Detection Duration Time to Measure PD Signature Resistance Figure 2 170 230 ms tetspty Classification Delay From Successful Detect in Auto or Semiaut
29. ction that is intended to protect the device during momentary overload conditions Junction temperature will exceed 125 C when overtemperature protection is active Continuous operation above the specified maximum operating junction temperature may impair device reliability Note 5 All currents into device pins are positive all currents out of device pins are negative All voltages are referenced to ground AGND and DGND unless otherwise specified Note 6 The LTC4258 is designed to maintain a port voltage of 46 6V to 57V The Veg supply voltage range accounts for the drop across the MOSFET and sense resistor Note 7 The LTC4258 implements overload current detection per IEEE 802 3af The minimum overload current eur is dependent on port voltage leur MIN 19 4W Vport wm An IEEE compliant system using the LTC4258 should maintain port voltage above 46 6V Note 8 Vee supply current while classifying a short is measured indirectly by measuring the DETECT pin current while classifying a short Note 9 Guaranteed by design not subject to test Note 10 Values measured at Vu p and Vum Note 11 If fault occurs during an 12C transaction the INT pin will not be pulled down until a stop condition is present on the 2C bus 4258fb LI MUR LIC4258 TYPICAL PERFORMANCE CHARACTERISTICS Power On Sequence in Auto Mode POWER ON DETECTION HOH TD _ PHASE 2 CLASSIFICATION Nik PORT VOLTAGE 10V DIV DET
30. e master and the slave An Acknowledge active LOW generated by the slave lets the master know that the latest byte of information was received The corresponding SCL clock pulse is always generated by the master The master releases the SDA line HIGH during the Acknowledge clock pulse The slave must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse When the master is reading from a slave device it is the master s responsibility to acknowledge receipt of the data byte in the bit that follows unless the transaction is complete In that case the master will decline to acknowledge and issue the STOP condition to terminate the communication Write Byte Protocol The master initiates communication to the LTC4258 with a START condition and a 7 bit bus address followed by the Write Bit Wr 0 If the LTC4258 recognizes its own address itacknowledges and the master delivers the com mand byte signifying to which internal LTC4258 register the master wishes to write The LTC4258 acknowledges and latches the lower five bits of the command byte into its Register Address register Only the lower five bits of the command byte are checked by the LTC4258 the upper three bits are ignored The master then delivers the data byte The LTC4258 acknowledges once more and latches the data into the appropriate control register Finally the master terminates the communication
31. e voltage is above Vour and the toyz timer counts up Ifthe sense voltage is still above Ve when the Du timer expires the LTC4258 will turn off the power to the port immediately and set the appropriate Deum Fault bit in register O6h 07h The herr timer duration can be pro grammed via register 16h bits 3 and 2 Table 1 The ber timer is an up down counter that is designed to protect the external MOSFET from thermal stress caused by repeatedly operating in current limit The counter counts up whenever the current is above Jeun and counts down at 1 16th the rate when it is not The counter will bottom out at zero to prevent underflow Full count indi cates that the ticur timer has expired and the port will be turned off This count up count down behavior implements duty cycle protection preventing intermittent current limitfaults from causing cumulative thermal stress inthe MOSFET Ifthe port enters current limit but then exits before the timer expires the count will decrease slowly giving the eu timer the ability to turn off sooner in the case of a repetitive fault If the overcurrent duty cycle is less than 6 3 the Deum timer will be fully reset If the tjoyz timer expires and causes the portto shut off the timer will continue to run counting down at the slow 1 16th rate and preventing the port from being repowered until the count returns to zero This protects the MOSFET from damage due to a faulty PD that may still have a valid sig
32. en panasey L OY SNYEIS HOd 490 Sne 409 t09 Juang Ajddng yao 0000 00 0000 1100 p m s y panasey panasay panasey OTAN BA OJAN A panasay dwa Jag Zer OY Wa Ajddng uyo Hp y09 Juang LYS y60 0000 0000 0000 0000 Lyne IHN guney IHN g ney 1UVLS D I p mas y p mas y panasay Dougeon L t Ou juanq 1V1 yg0 409 YO Wou WE 420 0000 0000 0000 0000 L um 1094 Z yney LA g neg 1091 r uneg HIN Joauuodsig Coeuugmeg JeuuoIsIG pyosuuodsig izer OH juanq Wm u90 409 H09 1u9A3 4199480 YSO 0000 0000 0000000 L ajajdwiog yoajaq Z ajajdwiog yoajaq allduj 940 y ajajdwog ao 3llduio9 sse 9 319lduio9 sep ajajdwog sep p oadug ssel9 Let OY Wa 199 9 UvO 8 6ueu9 z 865upu9 afueyg p abueyg ebueyg z abueyg g 6upu9 p abueyg Ho HO 1U9A3 Jamo UE 0000 0000 0000 0000 9 q8Uu3 IM ajqeuy Ad ajqeuy Wd ajqeuy IM D005 Imd D005 Imd D005 Imd D005 Imd L t Ou Wad 1aMOd Vuen S ugA3 0010 0LLL 0000 0001 0 SEN ASEN Z ASEN ASEN Y ASEN G SEN 9 SEN LASEN leqoj9 Wu ASEN IU 40 0000 0001 0000 000 ua ajqeUZ Wd Wa p009 d 199uu009SIG aja dwog oa ajajdwiog sep um Uh DIE Wou Mddne eqo Ou Wm eau 400 UD uld NY M07 Uld ONY sjdnuayul ALVIS 13S38 3LYLS l3S3q 0119 L Lg z La ig t 119 S 1g 9 L19 Lug 140d WY 3WVN Y31S1934 SS3Y00Y LAI M LIC4258 REGISTER FUNCTIONS Interrupt Registers Interrupt Address 00h Interrupt Register Read Only A
33. er GATE is allowed to rise back up and the normal current limit circuit will take over allowing li m current to flow and causing the ticyt timer to count up During a short circuit li jg will be reduced by the foldback feature to 1 7th of the nominal value Figures 14 and 15 show the LTC4258 controlling port current during short circuits In Figure 14 the MOSFET is turned off 0 5us after the port is shorted with 1Q The spike in port voltage and current at the moment the MOSFET turns off is the response of inductance in the system such as the magnetics and the Ethernet cable see Surge Suppressors and Circuit Protection for further details The 0 1 uF port bypass cap see Figure 1 provides some port current for 0 25us after the MOSFET is off In Figure 15 the LTC4258 quickly turns the port off and the spike above ground is again due to inductance It then ramps the MOSFET gate up similar to applying power after a PD is detected bringing the port into a controlled 425mA typ jy current limit When the shortis removed the port current no longer needs to be limited and LTC4258 ramps up its GATE pin to fully enhance the MOSFET Short circuit protection quickly stops excessive current and limits the energy delivered to a short or faulty PD Yet the LTC4258 only stops current briefly so momentary faults typically do not cause the PD to lose power and PDs receive at least 50ms of 400mA to 450mA peak current as required by the 802 3af s
34. esigns share a common mode choke between two adjacent ports Even for nonpowered Ethernet sharing a choke is not recom mended With two ports passing through the choke it cannot limit the common mode current of either port Instead the choke only controls the sum of both ports common mode current Because cabling from the ports generally connects to different devices up to 200m apart a current loop can form In such a loop common mode current flows in one port and out the other and the choke will not prevent this because the sum of the currents is zero Another way to view this interaction between the paired ports is that the choke acts as a transformer coupling the ports common modes together In nonpowered Ethernet common mode current results from nonidealities like ground loops it is not part of normal operation However Power over Ethernet sends power and hence significant current through the ports common mode current is a byproduct of normal opera tion As described in the Choosing External MOSFETs section and under the Power Supplies heading below large transients can occur when a port s power is turned on or off When a powered port is shorted see Surge Suppressors and Circuit Protection a port s common mode current may be excessive Sharing acommon mode choke between two ports couples start up disconnect and fault transients from one port to the other The end result can range from momentary noncompliance with 802
35. ge on existing patent rights LIC4258 TYPICAL APPLICATION ISOLATED 3 3V ISOLATED GND DND AGND I SCL 1 4 SDAIN LTC4258 SDA0UT INT Ve SENSE GATE OUT DDET CMPD3003 Diut Rs 0 5Q NETWORK PHYSICAL LAYER eersten l CHIP Dper CENTRAL SEMI CMPD3003 Drss DIODES INC SMAJ58A L1 PULSE ENG P0473 Q1 FAIRCHILD IRFM120A Rs VISHAY WSL2010 0 50 0 5 T1 PULSE ENG H2009 U1 FAIRCHILD NC7WZ17 U2 U3 AGILENT HCPL 063L s at aj Jj oP E erte Beco 48V IRFM120A e q ns eee i ISOLATED TE S U3 ago 1 2 PULSE CONNECTOR H2009 I I I I I l 2000 PHY I I I 4258 F17 1000pF EN 2000V Figure 19 One Complete Isolated Powered Ethernet Port RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1619 Low Voltage Current Mode PWM Controller 48V to 3 3V at 300mA MSOP Package LTC1694 SMBus I2C Accelerator Improved 12C Rise Time Ensures Data Integrity LTC3803 Current Mode Flyback DC DC Controller in ThinSOT 200kHz Constant Frequency Adjustable Slope Compensation Optimized for High Input Voltage Applications LTC4255 Quad Network Power Controller Non lEEE 802 3af Compliant Current Levels LTC4257 IEEE 802 3af PD Interface Controller 100V 400mA Internal Switch Programmable Classification LTC4257 1 IEEE 802 3af PD Interface Controller 100V 400mA Internal Switch Dual Current Limit LTC4259A 1 Quad IEEE 802 3af Power Over Ethernet Controller With AC Disconnect L
36. h mode it is in the LTC4258 will remove power automatically from any port that generates atstart OF Deum Overcurrent fault event See tur Timing and tstart Timing sections It will also automatically remove power from any port that generates a disconnect event if the appropriate Disconnect Enable bit is set in the Disconnect Enable register The host controller may also remove power at any time by setting the appropriate Power Off bit in the Power Enable PB register Power On RESET At turn on or any time the LTC4258 is reset either by pulling the RESET pin low or writing to the global Reset All bit all the ports turn off and all internal registers go to a predefined state shown in Table 1 Several of the registers assume different states based on the state of the AUTO pin at reset The default states with AUTO high allow the LTC4258 to detect and power up a PD in Automatic mode even if nothing is connected to the 12C interface SIGNATURE DETECTION The IEEE defines a specific pair to pair PD signature resistance that identifies a device that can accept Power over Ethernet in accordance with the 802 3af specification When the port voltage is below 10V an 802 3af compliant PD will have a 25k signature resistance Figure 11 illustrates the relationship between the PD signature resistance white box from 23 75k to 26 25k and required resistance ranges the PSE must accept white box and reject gray boxes According to the 802 3
37. ication with a STOP condition see Figure 8 Alert Response Address and the INT Pin Ina system where several LTC4258s share a common INT line the master can use the Alert Response Address ARA to determine which LTC4258 initiated the interrupt The master initiates the ARA procedure with a START condition and the 7 bit ARA bus address 0001100 b followed by the Read Bit Rd 1 If an LTC4258 is asserting the INT pin it acknowledges and sends its 7 bit bus address 010A3AA Ag b anda 1 see Figure 9 While it is sending its address it monitors the SDAIN pin to see if another device is sending an address at the same time using standard 12C bus arbitration If the LTC4258 is sending a 1 and reads a0 on the SDAIN pin on the rising edge of SCL it assumes another device with a lower address is sending and the LTC4258 immediately aborts its transfer and waits for the next ARA cycle to try again If transfer is successfully completed the LTC4258 will stop pulling down the INT pin When the INT pin is released in this way or if a1 is written into the Clear Interrupt pin bit bit 6 of register 1Ah the condition causing the LTC4258 to pull the INT pin down must be removed before the LTC4258 will be able to pull INT down again This can be done by reading and clearing the event registers or by writing a 1 into the Clear All Interrupts bit bit 7 of register 4258fb LS Lip 23 LIC4258 APPLICATIONS INFORMATION 1Ah The state
38. ignificant energy behind it and must be controlled by the transient suppres sor Choosing a surge suppressor that will not develop more than a few volts of forward voltage while passing more than 10A is important A positive port voltage may forward bias the detect diode Dpetn bringing the LTC4258 s DETECT pin positive as well and engaging the DETECT clamps This will generally not damage the LTC4258 but extreme cases can cause the LTC4258 to reset When it resets the LTC4258 signals an interrupt alerting the host controller which can then return the LTC4258 to normal operating mode A substantial transient surge suppressor can typically protect the LTC4258 and the rest of the PSE from these faults Placing a polyfuse between the RJ 45 connector and the LTC4258 and its associated circuitry can provide additional protection To meet safety requirements place the polyfuse in the ground leg of the PSE s output DC DISCONNECT DC disconnect monitors the sense resistor voltage when ever the power is on to make sure that the PD is drawing the minimum specified current The disconnect timer counts up whenever port current is below 7 5mA typ If the Ines timer runs out the corresponding port will be turned off and the disconnect bit in the fault register will be set If the undercurrent condition goes away before the Ins timer runs out the timer will reset The timer will start counting from the beginning if the undercurrent condition
39. imit threshold when the port voltage is within 18V of AGND The port 4 Power Good bitis set when the voltage from OUT4 to Vee drops below 2V typ A 2 5MQ resistor is connected internally from OUT4 to AGND If the port is unused the OUT4 pin can be tied to AGND or allowed to float SENSES Pin 25 Port3 Current Sense Input See SENSE4 GATES Pin 26 Port 3 Gate Drive See GATE4 OUTS Pin 27 Port 3 Output Voltage Monitor See OUT4 Veg Pin 28 48V Supply Input Connect to a 48V to 57V supply relative to AGND SENSE2 Pin 29 Port2 Current Sense Input See SENSE4 GATE2 Pin 30 Port 2 Gate Drive See GATE4 OUT2 Pin 31 Port 2 Output Voltage Monitor See OUT4 SENSE1 Pin 32 Port 1 Current Sense Input See SENSE4 GATE1 Pin 33 Port 1 Gate Drive See GATE 4 OUT1 Pin 34 Port 1 Output Voltage Monitor See OUT4 AUTO Pin 35 Auto Mode Input Auto mode allows the LTC4258 to detect and power up a PD even if there is no host controller present on the I2C bus The voltage of the AUTO pin determines the state of the internal registers when the LTC4258 is reset or comes out of Vpp UVLO see the Register map in Table 1 The states of these register bits can subsequently be changed via the 12C interface The real time state of the AUTO pin is read at bit 0 in the Pin Status register 11h Pull AUTO high or low with lt 10k or tie to Ven or DGND NC Pin 36 No Internal Connection 4258fb 8 LI UR LIC42
40. istor voltage One way to achieve Kelvin sensing is star grounding shown pictorially in Figure 1 Another option is to use a 48V power plane to connectthe sense resistor and the LTC4258 Ver pin Either of these strategies will prevent voltages developed across parasitic circuit board resistances from affecting the LTC4258 current measurement accuracy The precision of the sense resistor directly affects the measurement of the IEEE parameters linrusu Im Je and Ju Therefore to maintain IEEE compliance use a resistor with 0 5 or better accuracy Power MOSFETs The LTC4258 controls power MOSFETs in order to regu late current flow through the Ethernet ports Under certain conditions these MOSFETs have to dissipate significant power See the Choosing External MOSFETs section for a detailed discussion of the requirements these devices must meet B1100 100uH 10uH Von 3 3V ISOLATED L geg 400mA GND sour 10k SC 100uF 3 32k 10uF dr 6 3V SR 1 6 3V 0 22uF 100V 0 22uF L ISOLATED 100V GND FMMT723 FMMT723 FDC2512 K 1k 0 1002 806 47 5k 56k 1 1 1 VEE 2200pF ISOLATED 5 diese 48V PO Figure 18 48V to 3 3V Boost Converter 4258fb LS Lip Zo LIC4258 APPLICATIONS INFORMATION Common Mode Chokes Both nonpowered and powered Ethernet connections achieve best performance for data transfer power trans fer and EMI when a common mode choke is used on each port In the name of cost reduction some d
41. led no faults will be indicated The tstart timer also implements the duty cycle protec tion described under ticur timing and its duration can be programmed via register 16h bits 5 and 4 Table 1 4258fb LS UE 17 LIC4258 APPLICATIONS INFORMATION Foldback Foldback is designed to limit power dissipation in the MOSFET during power up and momentary short circuit conditions At low port output voltages the voltage across the MOSFET is high and power dissipation will be large if significant current is flowing Foldback monitors the port output voltage and reduces the Vi iw current limit level linearly from its full value 212 5mV typ at a port voltage of 18V to approximately 1 7th of the full value 30mV typ at a port voltage of OV With 0 5Q sense resistors this limits the short circuit current to 60mA typ instead ofthe full 425mA typ current limit When the LTC4258 is in foldback the ticur timer is active Short Circuit Protection H a port is suddenly shorted out the MOSFET power dissipation can rise to very high levels jeopardizing the MOSFET even before the normal current limit circuit can respond A separate short circuit current limit circuit watches for significant overcurrent events erer gt 275mV gt 550mA with a 0 5Q sense resistor and pulls the GATE pin down immediately if such an event occurs shutting offthe MOSFET in less than 1us with no external capacitor on GATE Approximately 100us lat
42. lete IEEE 802 3af compliant PSE The LTC4258 can operate autonomously or be controlled by an 12C serial interface Up to 16 LTC4258s may coexist on the same data bus allowing up to 64 powered Ethernet ports to be controlled with only two digital lines Fault conditions are optionally signaled with the INT pin to eliminate software polling External power MOSFETs current sense resistors and di odes allow easy scaling of current and power dissipation levels and provide protection against voltage and current spikes and ESD events The LTC4258 is available in a 36 pin SSOP package Linear Technology also provides solutions for 802 3af PD applications with the LTC4257 LTC4257 1 and LTC4267 TYPICAL APPLICATION INT SHDN1 SHDN2 SHDN3 SHDN4 RS1 TO RS4 0 5Q Q1 TO Q4 IRFM120A AUTO BYP 100V X7R RESET DETECT1 DETECT2 DETECTS CMPD3003 DIuEIDDN SMAJ58A x4 x4 x4 DETECT4 04 Figure 1 Complete 4 Port Powered Ethernet Power Source 4258fb LS Lip LIC4258 ABSOLUTE MAXIMUM RATINGS Note 1 Supply Voltages Vpp io DGND a anus sua sasa 0 3V to 5V Wer to ENEE 0 3V to 70V DGND to AGND Note 2 0 3V Digital Pins _ SCL SDAIN SDAOUT INT AUTO RESET SHDNn ADn DGND 0 3V to DGND 5V Analog Pins GATEn Note 3 Ver 0 3V to Vee 12V DETECTn DGND 21V to DGND 0 3V SENSE ulasan Vee 0 3
43. long Consequently the Power over Ethernet power source PSE must be designed to handle these events The most dramatic of these is shorting a powered port What the PSE sees depends on how much CAT 5 cable is between it and the short If the short occurs on the far end of a long cable the cable inductance will prevent the 4258fb LS UE 19 LIC4258 APPLICATIONS INFORMATION current in the cable from increasing too quickly and the LTC4258 s built in short circuit protection will take con trol of the situation and turn off the port Some energy is stored in the cable but the transient suppressor on the port clamps the port voltage when the cable inductance causes the voltage to fly back after the MOSFET is turned off Because the cable only had 600mA or so going through it an SMAJ58A or equivalent device can easily control the port voltage during flyback With no cable connected at all a powered port shorted at the PSE s RJ 45 connector can reach high currentlevels before the portis shut down There is no cable inductance to store energy so once the port is shut down the situation is under control A short hence low inductance piece of CAT 5 will not limitthe rapid increase of current when the portis shorted Even though the LTC4258 short circuit shutdown is fast the cable may have many amps flowing through it before the MOSFET can be turned off Due to the high current this short piece of cable flies back with s
44. must charge that capacitor with a current limit of 400mA to 450mA for at least 50ms An even more extreme example is a noncompliant PD that provides the proper signature during detection but then behaves like alow valued resistor say 50Q in parallel with a 1uF capacitor When the PSE has charged this noncompliant PD up to 20V the 50Q resistor will draw 400mA the minimum IEEE prescribed ig current limit keeping the port voltage at 20V for the remainder of tstapr The external MOSFET sees 24V to 37V Vps at 400mA to 450mA dissipating 9 6W to 16 7W for 60ms typ The LTC4258 implements foldback to reduce the current limit when the MOSFET Vps is high see the Foldback section Without foldback the MOSFET could see as much as 25 7W for 60ms typ when powering a shorted or a noncompliant PD with only afew ohms of resistance With foldback the MOSFET sees a maximum of 18W for the duration of tsTART The LTC4258 s duty cycle protection enforces 15 times longer off time than on time preventing successive at tempts to power a defective PD from damaging the MOS FET System software can enforce even longer wait times When the LTC4258 is operated in semiauto or manual mode described in more detail under Operating Modes it will not power ona port until commanded to do so by the host controller By keeping track of tstart and ticyr faults the host controller can delay turning on the port again after one of these faults even if the
45. nature or from errant software that repeatedly writes to the Power On bit The port will not repower until after the heim counter returns to zero In manual and semiauto modes the power enable command must be received after the ticyt counter reaches zero In auto mode the LTC4258 must complete a valid detection cycle after the ticur counter reaches zero tstart Timing To distinguish between normal turn on current limit be havior and current limit faults which occur after power up is complete the LTC4258 starts a timer the tstart timer whenever a power up sequence begins The tstart timer serves three functions First and fore most it allows the user to specify a different current limit timeout tstart instead of her during turn on current limit duty cycle protection remains functional Second the DC disconnect timer is disabled during this period and can only begin counting up after the tstart timer has expired Together these two features let the PD draw the maximum Current ljyRUsH to charge its input capacitance boot up and begin drawing power without triggering a tstart fault Finally if the device is in current limit for the entire tstart period a tsrapr fault will be generated instead of a Deum fault This can be useful for tracking down the cause of a current fault As long as the PD draws less than Jor at the end of tstart and begins drawing the minimum current within tpis after tstart expires if DC disconnect is enab
46. nt Another problem that can affect the Ver supply is insuffi cient power leading to the supply voltage drooping out of the specified range The 802 3af specification states that if a PSE powers a PD it must be able to provide the maximum power level requested by the PD based on the PD s classification The specification does allow a PSE to choose not to power a port because the PD requires more power than the PSE has left to deliver Ifa PSE is built with a Veg supply capable of less than 15 4W number of PSE s Ethernet ports it must implement a power alloca tion algorithm that prevents ports from being powered when there is insufficient power Because the specifica tion also requires the PSE to supply 400mA at up to a 5 duty cycle the Ver supply capability should be at least a few percent more than the maximum total power the PSE will supply to PDs Finally the LTC4258s draw current from Ver If the Vpp supply is generated from Ver that power divided by the switcher efficiency must also be added to the Veg supply s capability Fast VEE transients can damage the LTC4258 Limit the VEE slew rate to 50mV us In most applications existing VEE bypass capacitors will cause the VEE supply to slew much slower than 50mV us 4258fb 20 LI MVR LIC4258 PACKAGE DESCRIPTION GW Package 36 Lead Plastic SSOP Wide 300 Inch Reference LTC DWG 05 08 1642 Y UDDUDDUDDU Die m 15 290 15 544
47. o Mode e 10 1 52 ms to Class Complete From Classify Command in Manual Mode Figure 2 10 1 420 ms tCLASS Classification Duration Figure 2 e 10 1 13 ms tpon Power On Delay Auto Mode From Valid Detect to Port On in Auto Mode Figure 2 130 ms From Port On Command to GATE Pin Current Igon 1 ms Note 9 4258fb OO une TECHNOLOGY 3 LIC4258 ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at Ta 25 C AGND DGND OV Vpp 3 3V Vee 48V unless otherwise noted Note 5 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tsTaRT Maximum Current Limit Duration During tstarts 0 tstarto 0 Figure 3 e 50 60 70 ms Port Start Up tstaati 0 tstarto 1 Figure 3 e 25 30 35 ms tstarti 1 tstarto 0 Figure 3 e 100 120 140 ms tstarti 1 tstarto 1 Figure 3 e 200 240 280 ms ticuT Maximum Current Limit Duration After ticut1 0 ticuro 0 Figure 3 e 50 60 70 ms Port Start Up Deum 0 ticuto 1 Figure 3 e 25 30 35 ms Deum 1 ticuto O Figure 3 e 100 120 140 ms ticut1 1 ticuto 1 Figure 3 e 200 240 280 ms DCcimax Maximum Current Limit Duty Cycle Reg16h 00h e 58 6 3 6 7 Ins Disconnect Delay tpis1 0 tpiso 0 Figure 4 e 300 360 400 ms tpisi 0 tpiso 1 Figure 4 e 75 90 100 ms tpisi 1 tpiso
48. of the INT pin can only change between 12C transactions so an interrupt is cleared or new interrupts are generated after a transaction completes and before new 12C bus communication commences Periodic polling of the alert response address can be used instead of the INT pin if desired If any device acknowledges the alert response address then the INT line if connected would have been low System Software Strategy Control of the LTC4258 hinges on one decision the LTC4258 s operating mode The three choices are de scribed under Operating Modes In Auto mode the LTC4258 can operate autonomously without direction from a host controller Because LTC4258s running in Auto mode will power every valid PD connected to them the PSE must have 15 4W port available To reduce the power require ments of the 48V supply PSE systems can track power usage only turning on ports when sufficient power is available The IEEE describes this as a power allocation algorithm and places two limitations the PSE shall not power a PD unless it can supply the guaranteed power for that PD s class see Table 2 and power allocation may not be based solely ona history of each PD s power consump tion In order for a PSE to implement power allocation the PSE s processor controller must control whether ports are powered the LTC4258 cannot be allowed to operate in Auto mode Semiauto mode fits the bill as the LTC4258 automatically detects and classifies PDs
49. on This promises a whole new class of Ethernet devices including IP telephones wireless access points and PDA charging stations which do not require additional AC wiring or external power transformers a k a wall warts With about 13W of power available small data devices can be powered by their Ethernet connections free from AC wall outlets Sophisticated detection and power monitor ing techniques prevent damage to legacy data only de vices while still supplying power to newer Ethernet powered devices over the twisted pair cable A device that supplies power is called Power Sourcing Equipment PSE a device that draws power from the wire is called a Powered Device PD A PSE is typically an Ethernet switch router hub or other network switching CAT 5 20Q MAX equipment that is commonly found in the wiring closets where cables converge PDs can take many forms digital IP telephones wireless network access points PDA or notebook computer docking stations cell phone charg ers and HVAC thermostats are examples of devices that can draw power from the network A PSE is required to provide a nominal 48V DC between either the signal pairs or the spare pairs but not both as shown in Figure 10 The power is applied as a voltage between two of the pairs typically by powering the center taps of the isolation transformers used to couple the differential data signals to the wire Since Ethernet data is transformer coupled
50. onsistency with the standard the luusen term is used when referring to an initial LerApr power up event When the LTC4258 turns ona port itturns on the MOSFET by pulling up on the gate The LTC4258 is designed to power up the port in current limit limiting the inrush current to linrusu The port voltage will quickly rise to the point where the PD reaches its input turn on threshold and begins to draw current to charge its bypass capacitance slowing the rate of port voltage increase 4258fb 16 LI UR LIC4258 APPLICATIONS INFORMATION Dual Level Current Limit A PD is permitted to draw up to 15 4W continuously and up to 400mA for 50ms The LTC4258 has two correspond ing current limit thresholds Icur 875mA typ and li IM 425mA typ These are given by the equations lout Vour Rs Lim Vuim Rs Rs is the sense resistor and should be 0 5Q for IEEE 802 3af compliance While the LTC4258 allows the port current to exceed leur for a limited time period see ticuT timing below it does not allow the current to exceed im The current limit circuit monitors the port current by monitoring the voltage across the sense resistor and re duces the MOSFET gate voltage as needed to keep the current at or below jy When the current drops below Iw the gate voltage is restored to the full value to keep the MOSFET resistance to a minimum eur Timing Whenever more than Icyt Veyt Rs flows through a port the port s sens
51. orms the classification phase and then powers up the port without further intervention The signature detection circuitry is disabled when the port is in Shutdown mode powered up or the corresponding Detect Enable bit is cleared CLASSIFICATION A PD has the option of presenting a classification signa ture to the PSE to indicate how much power it will draw when powered up This signature consists of a specific constant current draw whenthe PSE port voltage is between 15 5V and 20 5V with the currentlevel indicating the power class to which the PD belongs Per the IEEE 802 3af speci fication the LTC4258 identifies the five classes of PD listed in Table 2 During classification the LTC4258 controls and IEEE 802 3af CLASSIFICATION MAXIMUM MINIMUM PSE CLASS CURRENT AT PSE PD POWER OUTPUT POWER CLASS DESCRIPTION 0 OmA to 5mA 12 95W 15 4W PD Does Not Implement Classification Unknown Power 1 8mA to 13mA 3 84W 4W Low Power PD 2 16mA to 21mA 6 49W 7W Medium Power PD 3 25mA to 31mA 12 95W 15 4W High or Full Power PD 4 35mA to 45mA 12 95W 15 4W Reserved Power as Class 0 4258fb LS UE 15 LIC4258 APPLICATIONS INFORMATION measures the port voltage through the DETECT npin Note that class 4 is presently specified by the IEEE as reserved for future use Figure 13 shows a PD load line starting with the shallow slope of the 25k signature resistor below 10V then drawing the classification cu
52. rrent in this case class 3 between 14 5V and 20 5V The LTC4258 s load line for clas sification is also shown in Figure 13 It has low impedance until current limit is reached at 55mA min The LTC4258 will classify a port immediately after a successful detection cycle in Semiauto or Auto modes or when commanded to in Manual mode It measures the PD classification signature current by applying 18V typ to the portand measuring the resulting current It reports the detected class in the Class Status bits in the correspond ing Port Status register Note that in Auto mode the port will power up regardless of which class is detected The classification circuitry is disabled when the port is in Shutdown mode powered up or the corresponding Class Enable bit is cleared 60 CURRENT mA ao T TYPICAL 0 5 10 15 20 25 VOLTAGE ease 4258 F13 Figure 13 PD Classification POWER CONTROL The primary function of the LTC4258 is to control the delivery of power to the PSE port It does this by control ling the gate drive voltage of an external power MOSFET while monitoring the current via a sense resistor and the output voltage at the OUT pin This circuitry serves to couple the raw isolated 48V input supply to the port in a controlled manner that satisfies the PD s power needs while minimizing disturbances on the 48V backplane Gate Currents Once the decision has been made to turn on power to a por
53. rrent Normal Operation 2 5 mA Classification Into a Short Vpetectn OV Note 8 100 mA VDDMIN Vpp UVLO Voltage 2 7 V VEEMINON Ver UVLO Voltage Turning On Ver AGND 31 V VEEMINOFF Ver UVLO Voltage Turning Off Ver AGND 28 V Detection IDET Detection Current First Point Vpetectn 10V e 235 300 uA Second Point Vnereera 3 5V e 145 190 uA VDET Detection Voltage Compliance Open Circuit Measured at DETECTn Pin e 20 23 V Rpermi Minimum Valid Signature Resistance e 15 2 17 19 kQ Rpetmax Maximum Valid Signature Resistance e 267 29 33 kQ Classification VcLASS Classification Voltage OMA lt IcLass lt 31MA e 16 4 21 V IcLass Classification Current Compliance Into Short Vpetect OV e 55 75 mA 4258fb 2 LI UR LIC4258 ELECTRICAL CHARACTERISTICS The e denotes the specifications which apply over the full operating temperature range otherwise specifications are at Ta 25 C AGND DGND OV Vpp 3 3V Vee 48V unless otherwise noted Note 5 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ItcLass Classification Threshold Current Class 0 1 e 55 6 5 7 5 mA Class 1 2 e 13 14 5 16 mA Class 2 3 e 21 23 25 mA Class 3 4 el 31 33 35 mA Class 4 Overcurrent el 45 48 51 mA Gate Driver lGoN GATE Pin Current Gate On VGATEn VEE e 20 50 70 uA GOFF GATE Pin Current Gate Off Ve
54. s Port 4 Status Address OFh Port 4 Status Register Read Only See Port 1 Status Power Status Address 10h Power Status Register Read Only The lower four bits in this register report the switch on off state for the corresponding ports The upper four bits the power good bits indicate that the drop across the power switch and sense resistor for the corresponding ports is less than 2V typ and power start up is complete The power good bits are latched high and are only cleared when a port is turned off or the LTC4258 is reset Pin Status Address 11h External Pin Status Read Only This register reports the real time status of the AUTO Pin 35 and ADO AD3 Pins 7 10 digital input pins The logic state of the AUTO pin appears at bit 0 andthe ADO AD3 pins at bits 2 5 The remaining bits are reserved and will read as 0 AUTO affects the initial states of some of the LTC4258 configuration registers at start up but has no effect after start up and can be used as a general purpose input if desired as long as it is guaranteed to be in the appropriate state at start up Configuration Registers Operating Mode Address 12h Operating Mode Configu ration Read Write This register contains the mode bits for each of the four ports in the LTC4258 See Table 1 for mode bit encoding At power up all bits in this register will be set to the logic state of the AUTO pin Pin 35 See Operating Modes in the Applications Information section
55. ster Clear on Read Read this address to clear the Power Event register Address 03h returns the same data as address 02h and reading address 03h clears all bits at both addresses Detect Event Address 04h Detect Event Register Read Only The lower four bits in this register indicate that at least one detection cycle for the corresponding port has com pleted the logical OR of these four bits appears in the In terrupt register as the Detect Complete bit The upper four bits indicate that at least one classification cycle for the corresponding port has completed the logical OR of these four bits appears in the Interrupt register as the Class Com plete bit In Manual mode this register indicates that the requested detection classification cycle has completed and the LTC4258 is awaiting further instructions In Semiauto or Auto modes these bits indicate that the Detect Status and Class Status bits in the Port Status registers are valid The Detect Event bits latch high and will remain high until cleared by reading from address O5h Detect Event CoR Address 05h Detect Event Register Clear on Read Read this address to clear the Detect Event register Address 05h returns the same data as address 04h and reading address 05h clears all bits at both addresses Fault Event Address 06h Fault Event Register Read Only The lower four bits in this register indicate that a Deum fault has occurred atthe corresponding port the logi cal
56. stored and the second current is applied to the port allowed to settle and the voltage measured Each point takes about 100ms to measure and an entire detection cycle takes 230ms max FIRST DETECTION POINT SECOND DETECTION POINT WN OFFSET VOLTAGE 4258 F12 Figure 12 PD Detection Table 2 IEEE 802 3af Powered Device Classes The LTC4258 will not report Detect Good if the PD has more than 5uF in parallel with its signature resistor The port s operating mode controls if and when the LTC4258 runs a detection cycle In manual mode the port will sit idle until a Restart Detection register 18h com mand is received It will then run a complete 200ms detection cycle on the selected port report the results in the Detect Status bits in the corresponding Port Status register and return to idle until another command is received In Semiauto mode the LTC4258 autonomously tests valid PDs connected to the ports but it will not apply power until instructed to do so by the host controller It repeatedly queries the port every 320ms and updates the Detect Status bits at the end of each cycle If a Detect Good is reported it will advance to the classification phase and report that result in the Port Status register Until in structed to do otherwise the LTC4258 will continue to repeat detection on the port Behavior in Auto mode is similar to Semiauto however after a Detect Good is reported the LTC4258 perf
57. t the LTC4258 uses a 50uA current source to pull up on the GATE pin Under normal power up circumstances the MOSFET gate will charge up rapidly to Vy the MOSFET threshold voltage the MOSFET current will rise quickly to the current limit level and the GATE pin will be servoed to maintain the proper liunusH charging current When out put charging is complete the MOSFET current will fall and the GATE pin will be allowed to continue rising to fully enhance the MOSFET and minimize its on resistance The final Vgs is nominally 13V When a port is turned off a 50uA current source pulls down on the GATE pin turning the MOSFET off in a controlled manner No External Capacitors No external capacitors are required on the GATE pins for active current limit stability lowering part count and cost This also allows the fastest possible turn off under severe Overcurrent conditions providing maximum safety and protection forthe MOSFETs load devices and board traces Connecting capacitors to the external MOSFET gates can adversely affect the LTC4258 s ability to respond to a shorted port Inrush Control The 802 3af standard lists two separate maximum current limits Iw and Iwpuen Because they have identical val ues the LTC4258 implements both as a single current limit using Vi iM described below Their functions are differentiated through the use of Ier and tstarr respec tively See ticur Timing and tstart Timing sections To maintain c
58. tandard GND PORT VOLTAGE 20V DIV VI EEE e Ep lt FASTPULL DOWN VEE ls ACTIVATED rri GATE 15V C ail p VOLTAGE 10V DIV Vpp 3 3V Veg 48V VEE PORT POND N SHORT APPLIED 250ns DIV 4258 G04 Figure 14 Rapid Response to 1Q Short GND rn Vp 33V PORT d et Vee 48V Y VOLTAGE 20v DIV VEE ee CURRENT LIMIT VEE TA EA OT cate 7 OY VOLTAGE V 1ov DIv EE grut Don PORT CURRENT OmA 500mA DIV SHORT REMOVED SHORT APPLIED 100us DIV 4258 GOS Figure 15 Rapid Response to Momentary 100Q Short 4258fb 18 LI UR LIC4258 APPLICATIONS INFORMATION Choosing External MOSFETs Power delivery to the ports is regulated with external power MOSFETs These MOSFETs are controlled as previ ously described to meet the IEEE 802 3af specification Under normal operation once the port is powered and the PD s bypass capacitor is charged to the port voltage the external MOSFET dissipates very little power This sug gests that a small MOSFET is adequate for the job Unfor tunately other requirements of the IEEE 802 3af mandate a MOSFET capable of dissipating significant power When the port is being powered up the port voltage must reach 30V or more before the PD turns on The port voltage can then drop to OV as the PD s bypass capacitor is charged According to the IEEE the PD can directly connect a 180uF capacitor to the port and the PSE
59. the register Pushbutton registers are write only and will return 00h if read Det Class Restart PB Address 18h Detection Classifi cation Restart Pushbutton Register Write Only Writing a 1 to any bit in this register will start or restart a single detection or classification cycle at the corresponding port in Manual mode It can also be used to set the correspond ing bits in the Detect Class Enable register address 14h for ports in auto or semiauto mode The lower 4 bits affect detection on each port while the upper 4 bits affect classification Power Enable PB Address 19h Power Enable Pushbutton Register Write Only The lower four bits of this register set the Power Enable bit in the corresponding Port Status reg ister the upper four bits clear the corresponding Power Enable bit Setting or clearing the Power Enable bits via this register will turn on or off the power in any mode except shutdown regardless of the state of detection or classifi cation Note that beim tstart and disconnect events if enabled will still turn off power if they occur The Power Enable bit cannot be set if the port has turned off due to aticyz or tstarr fault and the ticyr timer has not yet counted back to zero See Applications Information for more information on eur timing Clearing the Power Enable bits with this register also clears the detect and fault event bits the Port Status register and the Detection and Classification Enable bits
60. this case the SDAIN and SDAOUT pins of the LTC4258 can be connected together to act as a standard 2C SMBus SDA pin If the device is part of a larger system contains serial ports or must be referenced to protective ground for some other reason the Power over Ethernet subsystem including the LTC4258s must be electrically isolated from the rest of the system The LTC4258 includes separate pins SDAIN and SDAOUT for the input and output functions of the bidirectional data line This eases the use of optocouplers to isolate the data path between the LTC4258s and the system controller Figure 17 shows one possible implementation of an isolated inter face The SDAOUT pin of the LTC4258 is designed to drive the inputs of an optocoupler directly buta standard DC device typically cannot U1 is used to buffer 12C signals into the optocouplers from the system controller side Schmitt triggers must be used to prevent extra edges on transitions of SDA and SCL Bus Addresses and Protocols The LTC 4258 is a read write slave device The master can communicate with the LTC4258 using the Write Byte Read Byte and Receive Byte protocols The LTC4258 s primary serial bus address is 010A3A2A4Aq b as desig nated by pins AD3 ADO All LTC4258s also respond to the address 0110000 b allowing the host to write the same command into all of the LTC4258s on a bus in a single transaction If the LTC4258 is asserting pulling low the INT pin it will also
61. ting properly This interrupt driven system architecture provides the controller with the final Say On powering ports at the same time minimizing the controllers computation requirements because inter rupts are only generated when a PD is detected or ona fault condition The LTC4258 can also be used to power older powered Ethernet devices that are not 802 3af compliant and may be detected with other methods Although the LTC4258 does not implement these older detection methods auto matically if software or external circuitry can detect the noncompliant devices the host controller may command the LTC4258 to power the port bypassing IEEE compliant detection and classification and sending power to the noncompliant device LOGIC LEVEL SUPPLY In additon to the 48V used to source power to each port alogic level supply is required to power the digital portion of the LTC4258 To simplify design and meet voltage isolation requirements the logic level supply can be generated from the isolated 48V supply Figure 18 shows an example method using an LTC3803 to control a 48V to 3 3V current mode supply This boost con verter topology uses the LTC3803 current mode control ler and a current mirror which reflects the 3 3V output voltage to the 48V rail improving the regulation toler ance over the more traditional large resistor voltage divider This approach achieves high accuracy with a transformerless design 4258fb 24 LS UR
62. transition to logical 1 of any bit in this register will assert the INT pin Pin 3 ifthe corresponding bit in the Int Mask register is set Each bit is the logical OR of the correspond ing bits inthe Event registers The Interrupt register is Read Only and its bits cannot be cleared directly To clear a bit inthe Interrupt register clear the corresponding bits in the appropriate Status or Event registers or set bit 7 inthe Reset Pushbutton register 1Ah Int Mask Address 01h Interrupt Mask Read Write A logic 1 in any bit of the Int Mask register allows the correspond ing Interrupt register bit to assert the INT pin if itis set A logic 0 in any bit of the Int Mask register prevents the cor responding Interrupt bit from affecting the INT pin The actual Interrupt register bits are unaffected by the state of the Int Mask register Event Registers Power Event Address 02h Power Event Register Read Only The lower four bits in this register indicate that the corresponding port Power Enable status bit has changed the logical OR of these four bits appears in the Interrupt register as the Pwr Enable Event bit The upper four bits indicate that the corresponding port Power Good status bit has changed the logical OR of these four bits appears in the Interrupt register as the Pwr Good Event bit The Power Event bits latch high and will remain high until cleared by reading from address 03h Power Event CoR Address 03h Power Event Regi
63. us is not in use External pull up resistors or current sources such as the LTC1694 SMBus accelerator are required on these lines If the SDA and SCL pull ups are absent not connected to the same positive supply as the LTC4258 s Vpp pin or are not activated when the power is applied to the LTC4258 it is possible for the LTC4258 to see a START condition on the 12C bus The interrupt pin INT is only updated between 12C transactions Therefore if the LTC4258 sees a START condition when it powers up because the SCL and SDA lines were left floating it will not assert an interrupt pull INT low until it sees a STOP condition on the bus In a typical application the 12C bus will immediately have traffic and the LTC4258 will see a STOP so soon after power up thatthis momentary condition will go unnoticed Isolating the Serial Digital Interface IEEE 802 3af requires that network segments be electri cally isolated from the chassis ground of each network interface device However the network segments are not required to be isolated from each other provided that the segments are connected to devices residing within a single building on a single power distribution system For simple devices such as small powered Ethernet switches the requirement can be met by using an iso lated power supply to power the entire device This implementation can only be used if the device has no electrically conducting ports other than twisted pair Ethernet In
64. with a STOP condi tion Upon reception of the STOP condition the Register Address register is cleared see Figure 6 Read Byte Protocol The master initiates communication from the LTC4258 with a START condition and the same 7 bit bus address followed by the Write Bit Wr 0 If the LTC4258 recognizes its own address it acknowledges and the master delivers the command byte signifying which internal LTC4258 register it wishes to read from The LTC4258 acknowledges and latches the lower five bits of the command byte into its Register Address register At this time the master sends a REPEATED START condition and the same 7 bit bus address followed by the Read Bit Rd 1 The LTC4258 acknowledges and sends the contents of the requested register Finally the master declines to acknowledge and terminates communication with a STOP condition Upon reception of the STOP condition the Register Address register is cleared see Figure 7 Receive Byte Protocol Since the LTC4258 clears the Register Address register on each STOP condition the interrupt register register 0 may be read with the Receive Byte Protocol as well as with the Read Byte Protocol In this protocol the master initiates communication with the LTC4258 with a START condition and a 7 bit bus address followed by the Read Bit Rd 1 The LTC4258 acknowledges and sends the contents of the interrupt register The master then de clines to acknowledge and terminates commun

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