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RENESAS M16C/28 Group (M16C/28 M16C/28B) handbook

1. Address Register Symbol After Reset 03C016 A D register 0 ADO XX16 03C116 XX16 03C216 A D register 1 AD1 XX16 03C316 XX16 03C416 A D register 2 AD2 XX16 03C516 XX16 03C616 A D register 3 AD3 XX16 03C716 XX16 03C816 A D register 4 AD4 XX16 03C916 XX16 03CA16 A D register 5 AD5 XX16 03CB16 XX16 03CC16 A D register 6 AD6 XX16 03CD16 XX16 03CE16 A D register 7 AD7 XX16 03CF16 XX16 03D016 03D116 03D216_ A D trigger control register ADTRGCON 0016 03D316_ A D convert status register 0 ADSTATO 00000X002 03D416_ A D control register 2 ADCON2 0016 03D516 03D6 6_ A D control register 0 ADCONO 00000XXX2 03D716_ A D control register 1 ADCON 1 0016 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016_ Port PO register PO XX16 03E116_ Port P1 register P1 XX16 03E216_ Port PO direction register PDO 0016 03E316_ Port P1 direction register PD1 0016 03E416_ Port P2 register P2 XX16 03E516_ Port P3 register P3 XX16 03E616_ Port P2 direction register PD2 0016 03E716_ Port P3 direction register PD3 0016 O3E816 03E916 03EA16 03EB16 03EC16_ Port P6 register P6 XX16 03ED16_ Port P7 register P7 XX16 03EE16_ Port P6 direction register PD6 0016 03EF16_ Port P7 direction register PD7 0016 03F016_ Po
2. o fesio PCLK1 0 fisi0 or fasio S fisio ue Main clock PLL clock or id D on chip oscillator clock PCLK1 1 1 8 t gt 8SIO UARTO 1 4 fzsio RxD0O O TxDo Clock source selection UART reception Receive P H clock cre to CLKO Clock synchronous rO earl ici F110 or fasio ze AM UOBRG type Transmit 2 nternal CKDIR 0 register receive tes fesio 102 Q UART transmission _ Transmit a Ia o 1 n0 1 HHn m1m clock External Transmission control GC Clock synchronous circuit type Clock synchronous type 4 2 when internal clock is selected VE GKDIR 0 Clock synchronous type SGRDIRED CKPOL when external clock is selected 4 CKDIR 1 Clock synchronous type CLK when internal clock is selected polarity CLKOO reversing circuit CTS RTS selected CTS RTS disabled o CRS 1 RTSO CTSO RTSO CRS 0 Vcc CTSIRTS disabled CRD 1 CTSo CTSo from UARTI o CRD 0 RCSP 1 RxD1 OTD Clock source selection 4 16 DART reception o Receive CLK1 to CLKO Gia h Reception clock lock synchronous control circuit i fisio or fasio He EN U1BRG type prs fesio Ho TT CKDIR 0_ register unit 102 UART transmission Transmit fs2sio o 2 1 n1 1 1 16 S Transmission clock External CKDIR 1 SE synchronous control circuit Clock synchronous type 4 2 when internal clock is selected CKDIR 0 Clock synchron
3. NOTES 1 The bits used for transmit receive data are as follows Bit 0 to bit 6 when transfer data is 7 bits long bit 0 to bit 7 when transfer data is 8 bits long bit O to bit 8 when transfer data is 9 bits long 2 Set the bit 4 to bit 5 in the UOC1 and U1C1 registers to 0 The UOIRS U1IRS UORRM and U1RRM bits are included in the UCON register 3 Set the bit 6 to bit 7 in the UOC1 and U1C1 registers to 0 4 Set the bit 7 in the UOMR and U1MR registers to 0 i 0 to 2 Rev 2 00 Jan 31 2007 page 184 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 14 Serial I O Table 14 7 lists the functions of the input output pins in UART mode Table 14 8 lists the P64 pin func tions during UART mode Note that for a period from when the UARTi operation mode is selected to when transfer starts the TxDi pin outputs an H If the N channel open drain output is selected this pin is ina high impedance state Table 14 7 I O Pin Functions in UART model Pin name Function Method of selection TxDi i 0 to 2 Serial data output Outputs H when performing reception only P63 P67 P70 p ap p p RxDi Serial data input PD6_2 bit PD6_6 bit in the PD6 register and the PD7_1 bit in the PD7 register P62 P66 P71 Can be used as an input port when performing transmission only CU Input output port Set the CKDIR bit in the UiMR register to 0 Pen Pes Prap mnm Ih Se
4. ACK interrupt DMA request or NACK interrupt Data is transferred to the U2RB register __ D8 D7 De D5 D4 D3 D2 D1 Contents of the U2RB register 3 When the IICM2 bit is set to 1 UART transmit or receive interrupt and the CKPH bit is set to 0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit bit bit bit bit bit bit bit bit SCL2 spa2 X D7 X Dei Ds X D4 X Ds X D2 X D1 X Do X Ds ACK or NACK A A Receive interrupt Transmit interrupt DMA request A Data is transferred to the U2RB register b0 D7 D6 D5 D4 D3 D2 D1 Contents of the U2RB register 4 When the IICM2 bit is set to 1 and the CKPH bit is set to 1 ist 2nd 3rd 4th 5th 6th 7th 8th 9th bit bit bit bit bit bit bit bit bit SCL2 spa2 X D7 X Dei Ds X D4 X Ds X D2 X D X Do X Ds ACK or NACK A A Receive interrupt Transmit interrupt DMA request A Data is transferred to the U2RB register Data is transferred to the U2RB register b15 b9 b8 b7 b b15 b9 b8 b7 b Dol D7 D D5 D4 D3 D2 D1 D8 D7 D6 D5 D4 D3 D2 D1 Do Contents of the U2RB register Contents of the U2RB register The above timing applies to the following settin
5. Address Register Symbol After Reset 030016 TM WG register 0 G1TMO G1POO XX16 030116 XX16 030216 TM WG register 1 G1TM1 G1PO1 XX16 030316 XX16 030416 TM WG register 2 G1TM2 G1PO2 XX16 030516 XX16 030616 TM WG register 3 G1TM3 G1PO3 XX16 030716 XX16 030816 TM WG register 4 G1TM4 G1PO4 XX16 030916 XX16 030A16 TM WG register 5 G1TM5 G1PO5 XX16 030Bi6 XX16 030C16 TM WG register 6 G1TM6 G1PO6 XX16 030D16 XX16 030E16 TM WG register 7 GI1TM7 G1PO7 XX16 030F 16 XX16 031016 WG control register 0 GiPOCRO 0X00XX002 031116 WG control register 1 GiPOCR1 0X00XX002 031216_ WG control register 2 GiPOCR2 0X00XX002 031316_ WG control register 3 GiPOCR3 0X00XX002 031416 WG control register 4 GiPOCR4 0X00XX002 031516 WG control register 5 GiPOCR5 0X00XX002 031616 WG control register 6 GiPOCR6 0X00XX002 _ 031716 WG control register 7 G1POCR7 0X00XX002 031816 TM control register 0 G1TMCRO 0016 031916 TM control register 1 G1TMCRi 0016 031A16 TM control register 2 G1iTMCR2 0016 031B16 _TM control register 3 G1iTMCR3 0016 031C16 _TM control register 4 G1TMCR4 0016 031D16 _TM control register 5 G1TMCR5 0016 031E16 TM control register 6 G1TMCR6 0016 031Fi6 TM control register 7 G1TMCR7 0016 032016 Base timer register G1BT XX16 032116 XX16 032216 Base timer control register 0 GiBCRO 0016 032316 Base timer control register 1 G1iBCR1 0016 032416
6. Figure 7 9 Examples of Sub Clock Connection Circuit Rev 2 00 Jan 31 2007 page 52 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 7 Clock Generation Circuit 7 3 On chip Oscillator Clock This clock is supplied by a variable on chip oscillator This clock is used as the clock source for the CPU and peripheral function clocks In addition if the PM22 bit in the PM2 register is 1 on chip oscillator clock for the watchdog timer count source this clock is used as the count source for the watchdog timer Refer to 10 3 Count source protective mode Watchdog Timer The on chip oscillator after reset oscillates The on chip oscillator clock f2 ROC divided by 16 is used for the CPU clock It can also be turned off by setting the CM21 bit in the CM2 register to 0 main clock or PLL clock If the main clock stops oscillating when the CM20 bit in the CM2 register is 1 oscillation stop re oscillation detection function enabled and the CM27 bit is 1 oscillation stop re oscillation detection interrupt the on chip oscillator automatically starts operating supplying the necessary clock for the micro computer 7 4 PLL Clock The PLL clock is generated from the main clock by a PLL frequency synthesizer This clock is used as the clock source for the CPU and peripheral function clocks After reset the PLL clock is turned off The PLL frequency synthesizer is activated by setting the PLCO07 bit to
7. 0 PLL Off i it 4 Operation enable bit 1 PLL On 1 Write to this register after setting the PRCO bit of PRCR register to 1 write enable 2 When the PM21 bit in the PM2 register is 1 clock modification disable writing to this register has no effect 3 These three bits can only be modified when the PLCO7 bit is set to 0 PLL turned off The value once written to this bit cannot be modified 4 Before setting this bit to 1 set the CMO07 bit to 0 main clock set the CM17 to CM16 bits to 002 main clock undivided mode and set the CMO6 bit to 0 CM16 and CM17 bits enable Figure 7 7 PLCO Register Rev 2 00 Jan 31 2007 page 50 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 7 Clock Generation Circuit The following describes the clocks generated by the clock generation circuit 7 1 Main Clock The main clock is generated by the main clock oscillation circuit This clock is used as the clock source for the CPU and peripheral function clocks The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins The main clock oscillator circuit contains a feedback resistor which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip The main clock oscillator circuit may also be configured by feeding an externally generated clock to the XIN pin Figure 7 8 shows the examples of main cloc
8. A D Conversion Start Flag 0 A D conversion disabled ADST 4 1 A D conversion started Frequency Select Bit 0 See Table 15 2 CKSO 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 1 Re Symbol Address After Reset ADCON1 03D716 0016 Bit Symbol Bit Name Function A D Sweep Pin Select Bit Function varies with each operation mode SCANO A D Operation Mode Other than repeat sweep mode 1 Select Bit 1 Repeat sweep mode 1 8 10 Bit Mode Select Bit 8 bit mode 10 bit mode Frequency Select Bit 1 See Table 15 2 Vref Connect Bit 2 0 Vref not connected 1 Vref connected Nothing is assigned When write set to 0 When read its content is 0 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 If the VCUT bit is reset from 07 V REF unconnected to 1 V REF connected wait for 1 us or more before starting A D conversion A D Control Register 2 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset ADCON2 03D416 0016 Bit Symbol Bit Name Function SMP A D Conversion Method 0 Without sample and hold Select Bit 1 With sample and hold b2 b1 0 0 Select port P10 group 0 1 Do not set 1 0 Select port PO group ADGSEL1 1 1 Select port P1 P9 grou
9. LES b 0 31 0 35 0 39 b 0 39 0 43 0 47 x 0 08 y 0 10 Rev 2 00 Jan 31 2007 page 381 of 385 RENESAS REJ09B0047 0200 M16C 28 Grou M16C 28 M16C 28B Appendix 2 Functional Comparison Appendix 2 Functional Comparison Appendix 2 1 Difference between M16C 28 Group Normal ver and M16C 28 Group T ver V ver 1 Clock Generation Circuit Description Clock output function function of b1 to bO bits in the CMO register M16C 28 Normal ver Not available reserved bit M16C 28 T ver V ver Available clock output function select bit Reset Low Voltage Detect Circuit function of 001916 001A16 001F 16 Available voltage detect register 1 voltage detect register 2 low voltage detect interrupt register Not available reserved register Three phase Motor Control Timer Three phase port switching function function of 035816 Not available reserved register Available port function select register A D Number of A D input pin 24 channels excluding AN30 to AN32 27 channels including AN30 to AN32 Delayed trigger mode 0 Not available in the 1st chip version and chip version A Available Delayed trigger mode 1 Not available in the 1st chip version and chip version A Available CRC Calculation Available compatible to CRC CCITT and CRC 16 methods Not available all related registers are rese
10. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to 1 write enable To access the two 2K byte data spaces in data block A and data block B set the PM10 bit to 1 The PM10 bit is not available in mask version When the FMR01 bit in the FMRO register is set to 1 enables CPU rewrite mode the PM10 bit is automatically set to 1 Set the PM12 bit to 1 by program Writing 0 by program has no effect When the PM17 bit is set to 1 wait state one wait is inserted when accessing the internal RAM or the internal ROM Figure 6 1 PMO Register PM1 Register Rev 2 00 Jan 31 2007 page 41 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 6 Processor Mode Processeor Mode Register 2 1 b7 b6 b5 b4 b3 XX PELL b2 bi b0 Symbol Address PM2 001E16 Specifying wait when accessing SFR during PLL operation 2 System clock protective bit WDT count source protective bit 3 5 After Reset XXX000002 0 2 wait 1 1 wait 0 Clock is protected by PRCR register RW 1 Clock modification disabled 0 CPU clock is used for the watchdog timer count source 1 On chip oscillator clock is used RW for the watchdog timer count source PM24 b7 b5 P85 NMI configuration bi Nothing is assigned When write set to 0 When read its content is indeterminate 0 P85 function NMI disable 1 NMI function Write to this register a
11. TAIOUT pin function I O port or pulse output Read from timer Count value can be read by reading TAi register Write to timer e When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter e When counting after 1st count source input Value written to TAi register is written to only reload register Transferred to counter when reloaded next Select function e Gate function Counting can be started and stopped by an input signal to TAiIN pin e Pulse output function Whenever the timer underflows the output polarity of TAiOUT pin is inverted When not counting the pin outputs a low Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0 0 0 Symbol TAOMR to TA4MR 039616 to O39A16 0016 Carsetd Lu TMODO Operation mode SE TMOD1 select bit 0 0 Timer mode 0 Pulse is not output MRO Pulse output function TAiOUT pin is a normal port pin select bit 1 Pulse is output TAiOUT pin is a pulse output pin Gate function not available TAiIN pin functions as I O port 1 0 Counts while input on the TAi IN pin is low 1 RW 1 1 Counts while input on the TAI IN pin RW RW WwW Gate function select bit is high ew Set to 0 in timer mode b7 b6 00 fi or f2 01 fs 10 f32 11 fc32 Count source select bit 1 The port direction bit for the TAiIN p
12. CKPH Refer to Table 14 13 Refer to Table 14 13 DL2 to DLO NOTES 1 Not all bits in the register are described above Set those bits to 0 when writing to the registers in 12C bus mode Rev 2 00 Jan 31 2007 page 193 of 385 REJ09B0047 0200 Set the amount of SDA2 digital delay 7tENESAS Set the amount of SDA2 digital delay M16C 28 Group M16C 28 M16C 28B 14 Serial I O Table 14 12 Registers to Be Used and Settings in I2C bus Mode 2 Continued Function Register U2SMR4 STAREQ Master Set this bit to 1 to generate start condition Set to 0 RSTAREQ Set this bit to 1 to generate restart condition Set to 0 STPREQ Set this bit to 1 to generate stop condition Set to 0 STSPSEL Set this bit to 1 to output each condition Set to 0 ACKD Select ACK or NACK Select ACK or NACK ACKC Set this bit to 1 to output ACK data Set this bit to 1 to output ACK data SCLHI Set this bit to 1 to have SCL2 output stopped when stop condition is detected Set to 0 NOTES SWC9 Set to 0 Set this bit to 1 to set the SCL2 to L hold at the falling edge of the 9th bit of clock 1 Not all bits in the register are described above Set those bits to 0 when writing to the registers in 12C bus mode Rev 2 00 Jan 31 2007 page 194 of 38
13. I O Input and output page 20 of 385 Rev 2 00 Jan 31 2007 ztENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 1 Overview Table 1 11 Pin Description 80 pin and 85 pin packages only Continued Classification Serial UO CLK4 Function Inputs and outputs the transfer clock SIN4 Inputs serial data SOUT4 Outputs serial data A D Converter AN04 to ANO7 AN20 to AN23 AN25 to AN27 Analog input pins for the A D converter UO Ports Input O P04 to P07 Pio to P14 P34 to P37 P95 to P97 Output Rev 2 00 Jan 31 2007 REJ09B0047 0200 CMOS UO ports which have a direction register determines an individual pin is used as an input port or an output port A pull up resistor is select able for every 4 input ports I O Input and output page 21 of 385 2tENESAS M16C 28 Group M16C 28 M1i6C 28B 2 Central Processing Unit CPU 2 Central Processing Unit CPU Figure 2 1 shows the CPU registers The register bank is comprised of 7 registers RO R1 R2 R3 AO A1 and FB out of 13 CPU registers Two sets of register banks are provided b8 b7 b ROH R0 s high bits ROL RO s low bits R1H R1 s high bits RIL R1 s low bits n a Vu Data registers R2 R3 AO j Al H Address registers 1 FB 1 Frame base registers b19 b15 INTBH Interrupt table register The upper 4 bits of INTB are INTBH and the lower
14. The TE bit in the U2C1 register is set to 1 transmission enabled The TI bit in the U2C1 register is set to 0 data present in U2TB register Reception start condition e Before reception can start the following requirements must be met The RE bit in the U2C1 register is set to 1 reception enabled Start bit detection Interrupt request e For transmission generation timing When the serial I O finished sending data from the U2TB transfer register U2IRS bit 1 e For reception When transferring data from the UART2 receive register to the U2RB register at completion of reception Error detection e Overrun error 1 This error occurs if the serial I O started receiving the next data before reading the U2RB register and received the bit one before the last stop bit in the the next data e Framing error This error occurs when the number of stop bits set is not detected e Parity error During reception if a parity error is detected parity error signal is output from the TxD2 pin During transmission a parity error is detected by the level of input to the RxD2 pin when a transmission interrupt occurs e Error sum flag This flag is set to 1 when any of the overrun framing and parity errors is encountered NOTES 1 If an overrun error occurs bits 8 to 0 in the U2RB register are undefined The IR bit in the S2RIC register remains unchanged 2 A transmit interrupt request is generated by setting the U2I
15. 1 hardware trigger The ADTRG pin input changes state from H to L after setting the ADST bit to 1 A D conversion started A D Conversion Stop Condition Get the ADST bit to 0 A D conversion halted Interrupt Request Generation Timing None generated Analog Input Pin Select one pin from ANo to AN7 ANOo to ANO7 and AN2o0 to AN27 Readout of A D Conversion Result Readout one of the ADO to AD7 registers that corresponds to the selected pin Example when selecting AN2 to an analog input pin Ch2 to CHO 0102 TT A D pin input voltage sampling L A D pin conversion A D conversion started E E E E E Figure 15 8 Operation Example in Repeat Mode Rev 2 00 Jan 31 2007 page 225 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B A D Control Register 0 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol 0j1 ADCONO Address After Reset 03D616 00000XXX2 Bit Symbol Bit Name Analog Input Pin Select Bit 2 3 Function be bt BO Select ANo Select AN1 Select AN2 Select AN3 Select AN4 Select AN5 Select AN6 Select AN7 A D Operation Mode Select Bit 0 9 Repeat mode Trigger Select Bit 0 Software trigger 1 Hardware trigger AD TRG trigger A D Conversion Start Flag 0 A D conversion disabled 1 A D conversion started Frequency Select Bit 0 Refer to Table 15 2 1 If the ADCONDO regis
16. 11 writing signal START condition setting standby SOI writing signal START condition trigger generation Figure 16 24 The time of generation of RESTART condition 3 limitation of CPU clock When the CM07 bit in the CMO register is set to 1 subclock each register of the 12C bus interface circuit cannot be read or written Read or write data when the CM07 bit is set to 0 main clock PLL clock or on chip oscillator clock Rev 2 00 Jan 31 2007 page 281 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 17 Programmable I O Ports 17 Programmable I O Ports Note Ports P04 to P07 P10 to P14 P34 to P37 and P95 to P97 are not available in M16C 28 64 pin package The programmable input output ports hereafter referred to simply as I O ports consist of 71 lines PO P1 P2 P3 P6 P7 P8 P9 P10 except P94 for the 80 pin package or 55 lines POo to P03 P15 to P17 P2 P30 to P33 P6 P7 P8 P90 to P93 P10 for the 64 pin package Each port can be set for input or output every line by using a direction register and can also be chosen to be or not be pulled high in sets of 4 lines Figures 17 1 to 17 4 show the I O ports Figure 17 5 shows the I O pins Each pin functions as an I O port a peripheral function input output For details on how to set peripheral functions refer to each functional description in this manual If any pin is used as a peripheral functi
17. NOTES 1 This applies to the case where the CKPOL bit in the UiCO register is set to 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock the UILCH bit in the UC register is set to 0 no reverse the STPS bit in the UIMR register is set to 0 1 stop bit and the PRYE bit in the UiMR register is set to 1 parity enabled Figure 14 18 Transfer Format Rev 2 00 Jan 31 2007 page 188 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 14 Serial I O 14 1 2 4 Serial Data Logic Switching Function UART2 The data written to the U2TB register has its logic reversed before being transmitted Similarly the received data has its logic reversed when read from the U2RB register Figure 14 19 shows serial data logic 1 When the U2LCH bit in the U2C1 register is set to 0 no reverse T ce st D0 X D1 X 02 X D3 X DaX Ds X bs Yor P J sp 2 When the U2LCH bit in the U2C1 register is set 1 reverse sl LIT EAL LALLY TEE LLL Ly i et st Coa ara STEET or NOTES ST Start bit 1 This applies to the case where the CKPOL bit in the U2CO register P Parity bit is set to 0 transmit data output at the falling edge of the transfer SP Stop bit clock the UFORM bit in the U2CO register is set to 0 LSB first the STPS bit in the U2MR register is set to 0 1 stop bit and the PRYE bit in the U2MR register is set to 1 parity enabled Tra
18. NOTES 1 Set the following either or both Connect the CE pin to Vcc Connect the RP pin to Vss and the P16 pin to Vcc Figure 18 19 Circuit Application in Standard Serial UO Mode 2 Rev 2 00 Jan 31 2007 page 326 of 385 7tENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 18 Flash Memory Version 18 10 Parallel I O Mode In parallel input output mode the user ROM can be rewritten by a parallel programmer supporting the M16C 28 group Contact your parallel programmer manufacturer for more information on the parallel pro grammer Refer to the user s manual included with your parallel programmer for instructions 18 10 1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read or rewritten Refer to 18 3 Functions To Prevent Flash Memory from Rewriting Rev 2 00 Jan 31 2007 page 327 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 19 Electrical Characteristics 19 Electrical Characteristics The electrical characteristics of the M16C 28 Group Normal ver are listed below Table 19 1 Absolute Maximum Ratings Parameter Condition Supply Voltage 0 3 to 6 5 Analog Supply Voltage 0 3 to 6 5 Input Voltage P0o to P07 P1oto P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 0 3 to Vcc 0 3 P100 to P107 Xin Vref RESET CNVss Output Voltage PO0o to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P7
19. P21 Phase delayed Waveform Output OUTC11 P2o0 INPC1 o OUTC10 Determined by PD20 P20 Determined by PD2o Input to INPC1o is always active P20 or INPC10 Single phase Waveform Output OUTC1o0 SR Waveform Output OUTC10 Al sch 1 sch alo of oO oO Sf oO sch sch a OJ a a a ch CO OO O KX CO CO Of KL CO CO CO KX GO GO CO KX OG GO CO K OO OC amp CO CO o 4 0 O lt lt lt 4 CO O lt KX 4 O OO lt lt Kx o OO amp 4 OO O amp x A CO OO amp x A O OlrX K kK O o O CO amp K KO 4 O amp x CO 4 CO amp XxX OO 4A O amp KK OO A O amp K OO 4 OO amp x CO 4 O x amp Xoj Phase delayed Waveform Output IFE IFEj j 0 to 7 bits in the G1FE register FSC FSCj j 0 to 7 bits in the G1FS register MOD2 to MOD1 Bits in the G1POCRj j 0 to 7 register Rev 2 00 Jan 31 2007 page 163 of 385 REJ09B0047 0200 7tENESAS OUTC10 M16C 28 Group M16C 28 M16C 28B 13 Timer S 13 6 1 INPC17 Alternate Input Pin Selection The input capture pin for IC OC channel 7 can be assigned to one of two package pins The CH7INSEL bit in the G1BCRO register selects IC OC INPC17 from P27 OUTC17 INPC17 or P17 INT5 INPC17 IDU 13 6 2 Digital Debounce Function for Pin P17 INT5 INPC17 The INT5 INPC17 input from the
20. P86 XcouT a o P92 TB2In 4 P91 TB1In P90 TBOIn 4 P84 INT2 ZP ae P77 TA3iIN t gt P95 AN25 CLK4 am NOTES 1 Set PACR2 to PACRO bit in the PACR register to 0112 before you input and output it after resetting to each pin When the PACR register isn t set up the input and output function of some of the pins are disabled Figure 1 6 Pin Assignment Top View of 80 Pin Package Rev 2 00 Jan 31 2007 page 13 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 1 Overview Table 1 9 Pin Characteristics for 80 Pin Package Pin Control No Pin Interrupt Pin Timer Pin Timer S Pin UART Pin Multi master IC bus Pin Analog Pin OINIDO aAlHR oOs ml a TAain U TA40 uT U TASIN TA30 UT TA2N W TA20 UT W TAIIN V CTS2 RTS2 TxD1 TA1O UT V CLK2 RxD1 TAOIN RxD2 SCL2 CLK1 TAoo UT TxD2 SDA2 RTS1 CTS1 CTSo CLKS1 TxD1 RxD1 CLK1 RTS1 CTS1 CTSo CLKS1 Rev 2 00 Jan 31 2007 REJ09B0047 0200 page 14 of 385 ztENESAS M16C 28 Group M16C 28 M16C 28B 1 Overview Table 1 9 Pin Characteristics for 80 Pin Package continued Pin Control No Pin Interrupt Pin Timer Pin Timer S Pin UART Pin RxDo Multi master C bus Pin Analog Pin
21. edge detection circuit Jand charge circuit discharge control CM06 0 1 8 1 16 CM06 0 CM17 CM16 112 CM06 1 CM17 CM16 102 2 gel CM06 0 CM17 CM16 012 O o CM06 0 CM17 CM16 002 Details of divider Oscillation stop detection reset Oscillation stop re oscillation detection interrupt generating circuit gt Oscillation stop re oscillation detection signal _Variable On chip Oscillator ROCR1 and ROCRO 002 f1 ROC O f2 ROC ROCR1 and Adem O f3 ROC BOCH and ROCRO 112 1 4 1 8 ROCR3 and ROCR2 112 ROCR3 and ROCR2 102 On chip ROCRS and ROCR2 012 oscillator CM21 switch signal PLL frequency synthesizer Programmable counter PLL clock Voltage Phase control comparator oscillator g i VCO Main clock Internal low pass filter Figure 7 1 Clock Generation Circuit 2tENESAS Rev 2 00 Jan 31 2007 page 45 of 385 REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 7 Clock Generation Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset CMO 000616 010010002 Reserved bits Set to 0 Wait Mode peripheral function 0 Do not stop peripheral function clock in wait mod
22. if IC OC base timer Sc Spa IC OC interrupt 0 UART1 reception UAR TO reception Priority of peripheral function interrupts if priority levels are same UART2 reception ACK2 A D conversion DMA1 UART 2 bus collision SI 04 INT5 _N Ty yY BS Timer AO UART1 transmission i UARTO transmission H 3 e e Interrupt request level resolution output to clock generation circuit Figure 7 1 ___ Ss Interrupt Liag request Address match accepted Watchdog timer Oscillation stop and re oscillation detection Low voltage detection DBC NMI Figure 9 10 Interrupts Priority Select Circuit Mt Rev 2 00 Jan 31 2007 page 81 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 9 Interrupts 9 6 INT Interrupt INTi interrupt i 0 to 5 is triggered by the edges of external inputs The edge polarity is selected using the IFSRi bit in the IFSR register The INT5 input has an effective digital debounce function for a noise rejection Refer to 17 6 Digital Debounce function for this detail When using INT5 interrupt to exit stop mode set the P17DDR register to FF16 before entering stop mode To use the INT4 interrupt set the IFSR6 bit in the IFSR register to 1 INT4 To use the INT5 interrupt set the IFSR7 bit in the IFSR register to 1 INT5 After modifiying the IFS
23. low voltage detection interrupt enable set the VC27 bit to 1 low voltage detection circuit enable 5 This register does not change at software reset watchdog timer reset and oscillation stop detection reset 6 The detection circuit does not start operation until td E A elapses after the VC26 bit or VC27 bit are set to 1 Figure 5 5 VCR1 Register and VCR2 Register Rev 2 00 Jan 31 2007 page 36 of 385 2tENESAS REJ09B0047 0200 5 Reset M16C 28 Group M16C 28 M16C 28B Low Voltage Detection Interrupt Register 1 b7 b6 b4 b3 b2 b Symbol D4INT Address 001F16 After Reset 0016 Bit Symbol Bit Name Low voltage detection interrupt enable bit 5 Function 0 Disable 1 Enable STOP mode deactivation control bit 4 0 Disable do not use the low voltage detection interrupt to exit stop mode Enable use the low voltage detection interrupt to exit stop mode Voltage change detection flag 2 Not detected Vdet4 passing detection WDT overflow detect flag Sampling clock select bit Not detected Detected b5b4 00 CPU clock divided by 8 01 CPU clock divided by 16 10 CPU clock divided by 32 11 CPU clock divided by 64 Nothing is assigned When write set to 0 When read its content is 0 Write to this register after setting the PRC3 bit in the PRCR register to 1 write enable Useful
24. 0 TCKO Count operation type S Reload type select bit Free run type Two phase pulse signal processing Operation 0 Normal processing operation select bit 1 1 Multiply by 4 processing operation 1 TCK1 bit is valid for timer A3 mode register No matter how this bit is set timers A2 and A4 always operate in normal processing mode and x4 processing mode respectively 2 If two phase pulse signal processing is desired following register settings are required e Set the TAIP bit in the UDF register to 1 two phase pulse signal processing function enabled e Set the TAITGH and TAiTGL bits in the TRGSR register to 002 TAiIN pin input e Set the port direction bits for TAiIN and TAiouT to 0 input mode Figure 12 9 TA2MR to TA4MR Registers in Event Counter Mode when using two phase pulse signal processing with timer A2 A3 or A4 Rev 2 00 Jan 31 2007 page 107 of 385 ztENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer 12 1 2 1 Counter Initialization by Two Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z phase counter initialization input during two phase pulse signal processing This function can only be used in timer A3 event counter mode during two phase pulse signal process ing free running type x4 processing with Z phase entered from the INT2 pin Counter initialization by Z phase input is enabled by writing 000016 to the
25. 0 m o 0 0 favidedby 0 0 to 0 o 0 aviae o0 o o 1 0 avea o o e 0 o o Towsedms LL Low power dissipation mode TT dvidedbyt 1 0 o 0 On chip avae 1 oe 0 0 0 _ ea a o e o o o e i javidedby 16 1 On chip oscillator low power dissipation mode NOTES 1 When the CM05 bit is set to 1 main clock turned off in low speed mode the mode goes to low power dissipation mode and CMO6 bit is set to 1 divided by 8 mode simultaneously 2 The divide by n value can be selected the same way as in on chip oscillator mode 3 On chip oscillator frequency can be any of those described in the section 7 6 1 6 On chip Oscillator Mode 7 6 2 Wait Mode In wait mode the CPU clock stops running The CPU and the watchdog timer operated by the CPU clock also stop However if the PM22 bit in the PM2 register is 1 on chip oscillator clock for the watchdog timer count source the watchdog timer remains active Because the main clock sub clock and on chip oscillator clock all are on the peripheral functions using these clocks keep operating 7 6 2 1 Peripheral Function Clock Stop Function If the CM02 bit is 1 peripheral function clocks turned off during wait mode the f1 f2 f8 32 Dao f2S10 f8SIO f32S1O and fAD clocks stop running in wait mode with the power consumption reduced that much However fC32 remains on 7 6 2 2 Entering Wait M
26. 15 1 4 Repeat Sweep Mode 0 229 15 1 5 Repeat Sweep Mode EE 231 15 1 6 Simultaneous Sample Sweep Mode 233 15 1 7 Delayed Trigger Mode EE 236 15 1 8 Delayed Trigger Mode 1 242 15 2 Resolution Select Function EE 248 E Sample and e e DEE 248 15 4 Power Consumption Reducing Function ENEE 248 15 5 Output Impedance of Sensor under A D Conversion ccccccccccceceeeeeeeeeteeeeeeeeeeeees 249 16 Multi master PC bus Interface n snnooeeennnnneeeeneeeeetn trne rrsereeerernnnnneeeere nn 250 16 1 l CO Data Shift Register SOO register AEN 259 16 2 l CO Address Register SODO register AEN 259 16 3 I CO Clock Control Register S20 regeiert 260 16 3 1 Bits 0 to 4 SCL Frequency Control Bits CCRA 260 16 3 2 Bit 5 SCL Mode Specification Bit FAST MODE 0 eeeeceeeeeeeeeeeeeneeeeeeeeeeeees 260 T6353 BIE 0 ACK Bit AGI RE 260 16 3 4 Bit 7 ACK Glock Bit ACK CLK ee DEER EEN 260 16 4 FCO Control Register 0 S1DO eececceceesecceeeeeeeeeeeeaeeeeeeneeeeecaeeeeeesaeeeeseeneeeeeennees 262 16 4 1 Bits O to 2 Bit Counter BCO BC2 EES EE 262 16 4 2 Bit 3 IPC Interface Enable Bit ESO 262 16 4 3 Bit 4 Data Format Select Bit ALS s 22ecae aed cee dhe 262 16 4 4 Bit 6 IPC bus Interface Reset Bit HD 262 16 4 5 Bit 7 EC bus Interface Pin Input Level Select Bit TI 263 16 5 FCO Status Register S10 register ccccccceecececeeeeeeeeeeeeeeeeeeeeeeeeesaneeeetesneeeeeeaes 264 16 5 1 Bit 0 Last Recei
27. Appendix 1 Package Dimensions e Dimensions are updated e 85 pin version is added Appendix 2 Functional Comparison e Appendix 2 1 Difference between M16C 28 Group Normal ver and M16C 28 Group T ver V ver Information of three phase motor control timer and CRC calculation in M16C 28 normal ver changed e Appendix 2 2 Difference between M16C 28 Group and M16C 29 Group Normal ver Information of interrupt three phase motor control timer CAN C 12 REVISION HISTORY M16C 28 Group M16C 28 M16C 28B Hardware Manual Summary module and CRC calculation in M16C 28 Normal ver changed e Appendix 2 3 Difference between M16C 28 and M16C 29 Groups T ver V ver Information of CAN module changed Overview 2 3 e Table 1 1 and Table 1 2 Performance Outline of M16C 28 Group Information about option deleted 19 to 21 ue Table 1 10 Pin Description Description partially modified Clock Generation Circuit 43 e Figure 7 1 Clock Generation Circuit Figure partially modified 47 e Figure 7 6 PCLKR Register and PM2 Register NOTE 4 partially modified 54 e 7 6 1 Normal Operation Mode Information partially modified 58 e Figure 7 11 State Transition to Stop Mode and Wait Mode Figure partially modified 59 e Figure 7 12 State Transition in Normal Mode Figure partially modified e Table 7 5 Allowed Transition and Setting Table partially modified M16C 28B added word standardized EC bus mode CPU clock Overview 1 1 Features Description modified e Tab
28. Error found NOTES 1 When the SMD2 to SMDO bits in the UiMR register are set to 000 2 serial I O disabled or the RE bit in the UiC1 register is set to 0 reception disabled all of the SUM PER FER and OER bits are set to 0 no error The SUM bit is set to 0 no error when all of the PER FER and OER bits are set to 0 no error Also the PER and FER bits are set to 0 by reading the lower byte of the UiRB register 2 The ABT bit is set to 0 by setting to 0 by program Writing 1 has no effect Nothing is assigned at the bit 11 in the UORB and U1RB registers When write set to 0 When read its content is 0 UARTIi Baud Rate Generation Register i 0 to 2 1 2 3 b7 bo Symbol Address After Reset U2BRG 037916 Indeterminate Function Setting Range UOBRG 03A1 16 Indeterminate r U1BRG 03A916 Indeterminate Assuming that set value n UIBRG divides the count source 0016 to FFi6 byn 1 NOTES 1 Write to this register while serial UO is neither transmitting nor receiving 2 Use MOV instruction to write to this register The transfer clock is shown below when the setting value in the UiBRG register is set as n 1 When the CKDIR bit in the UiMR register to 0 internal clock Clock synchronous serial I O mode f 2 n 1 Clock asynchronous serial I O UART mode fj 16 n 1 2 When the CKDIR bit in the UiMR register to 1 e
29. M16C 28 Group M16C 28 M16C 28B 1 Overview 1 Flash Memory Version PTLGOO85JB A 85FOG Normal ver M30280FA Type No M30280FAWG Chip version and product code B Chip version The first edition is shown to be blank and continues with A B and C U5 Product code See Table 1 5 Date code seven digits Manufacturing management code 2 Flash Memory Version PLQPO0080KB A 80P6Q A Normal ver M16C M30280FAHP Type No M30280FAHP A U5 Chip version and product code XXXXXXX A Chip version and product code The first edition is shown to be blank and continues with A B and C O U5 Product code Table 1 5 Date code seven digits Manufacturing management code 3 Flash Memory Version PLQP0064KB A 64P6Q A Normal ver 30281FA Type No M30281 FAHP A U5 Chip version and product code A Chip version and product codel XXXXXXX The first edition is shown to be blank and continues with A B and C U5 Product code Table 1 5 Date code seven digits Manufacturing management code 4 Mask ROM Version PLQP0080KB A 80P6Q A Normal ver M16C Type No M30280MAHP M30280MA XXXHP A U5 Chip version and product code XXXXXXX XXX ROM No O A Chip version and product code The first edition is shown to be blank and continues with A B and C U5 Product code Table 1 7 Date code seven digits Manufacturing management code 5 Mask ROM Version PLQP0064 KB A 64P6Q A Normal ver Date cod
30. Selected by TAITGH to TAITGL bits 16 8 bit PWM mode 0 Functions as a 16 bit pulse width modulator select bit 1 Functions as an 8 bit pulse width modulator b7 b6 Count source select bit 00 h or f2 01 ie 1 1 fc32 RW 1 Effective when the TAITGH and TAITGL bits in the ONSF or TRGSR register are 002 TAIIN pin input 2 The port direction bit for the TAiIN pin must be set to 0 input mode Figure 12 12 TAiMR Register in Pulse Width Modulation Mode Rev 2 00 Jan 31 2007 page 112 of 385 RENESAS REJ09B0047 0200 M Input signal to TAIIN pin 16C 28 Group M16C 28 M16C 28B 1 f x 2 1 Count source Input signal to TA pin S i Trigger is not generated by this signal PWM pulse output from TAiouT pin IR bit of TAIIC register fi Frequency of count source f1 f2 f8 f32 fc32 i 0t04 Set to 0 upon accepting an interrupt request or by program NOTES 1 n 000016 to FFFE16 2 This timing diagram is for the case where the TAi register is 000316 the TAITGH and TAITGL bits in the ONSF or TRGSR register is set to 002 TAiIN pin input the MR1 bit in the TAiMR register is set to 1 rising edge and the MR2 bit in the TAiMR register is set to 1 trigger selected by TAITGH and TAITGL bits Figure 12 13 Example of 16 bit Pulse Width Modulator Operation Count source 1 gt i fi X m 1 Underflow signal of 8 bit prescaler 2 PWM pulse outpu
31. The internal counter measures the time out detection time and the TOSEL bit selects between two modes long time and short time When time out is detected set the ESO bit to 0 I2C bus interface disabled and reset the counter 16 7 2 Bit1 Time Out Detection Flag TOF The TOF flag indicates the time out detection If the internal counter which measures the time out period overflows the TOF flag is set to 1 and the 12C bus interface interrupt request is generated at the same time 16 7 3 Bit2 Time Out Detection Period Select Bit TOSEL The TOSEL bit selects time out detection period from long time mode and short time mode When the TOSEL bit is set to 0 long time mode is selected When it is set to 1 short time mode is selected respectively The internal counter increments as a 16 bit counter in long time mode while the counter increments as a 14 bit counter in short time mode based on the 12C system clock VIIC as a counter source Table 16 7 shows examples of time out detection period Table 16 7 Examples of Time out Detection Period Unit ms Viic MHz Long time mode Short time mode 4 16 4 4 1 2 32 8 8 2 1 65 6 16 4 16 7 4 Bits 3 4 5 EC System Clock Select Bits ICK2 4 The ICK4 to 2 bits ICK1 and ICKO bits in the S3D0 register and the PCLKO bit in the PCLKR register select the system clock NIC of the 12C bus interface circuit See Table 16 6 for the setting values 16 7 5 Bit7
32. Timing at which counter reaches 000016 TBiS bit TBiIC register s IR bit Set to 0 upon accepting an interrupt request or by program The MR3 bit in the g TBiMR register The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register i 0to2 NOTES 1 Counter is initialized at completion of measurement 2 Timer has overflowed 3 This timing diagram is for the case where the MR1 to MRO bits in the TBiMR register are 102 measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse Figure 12 22 Operation timing when measuring a pulse width Rev 2 00 Jan 31 2007 page 119 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer 12 2 4 A D Trigger Mode A D trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A D conversion to start A D conversion It is used in timer BO and timer B1 only In this mode the timer starts counting by one trigger until the count value becomes 000016 Figure 12 23 shows the TBiIMR register in A D trigger mode and Figure 12 24 shows the TB2SC register Table 12 9 Specifications in A D Trigger Mode Count Source f1 f2 f8 f32 and fc32 Count Operation e Decrement e When the timer underflows reload register contents are reloaded before stopping counting e When a trigger is generated during the count oper
33. Vcc 3V CLki TxDi RxDi INTi input Figure 19 6 Timing Diagram 2 Vcc 3V agada P tHD STA tHD DTA tHIGH tsu DAT Figure 19 7 Timing Diagram 3 Rev 2 00 Jan 31 2007 page 349 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 20 Precautions 20 Precautions 20 1 SFR 20 1 1 For 80 Pin and 85 Pin Package Set the IFSR20 bit in the IFSR2A register to 1 after reset and set the PACR2 to PACRO bits in the PACR register to 0112 20 1 2 For 64 Pin Package Set the IFSR20bit in the IFSR2A register to 1 after reset and set the PACR2 to PACRO bits in the PACR register to 0102 22 1 3 Register Setting Immediate values should be set in the registers containing write only bits When establishing a new value by modifying a previous value write the previous value into RAM as well as the register Change the contents of the RAM and then transfer the new value to the register 20 1 4 For Flash Memory 128K 4K Version and Mask ROM Version When setting flash memory 128K 4K version and Mask ROM version follow the procedure below to set the LPCCO and LPCC1 registers after reset 1 Set the LPCCO register to 002116 2 Set the PRCO bit in the PRCR register to 1 3 Set the LPCC13 bit in the LPCC1 register to 1 4 Set the PRCO bit to 0 Example MOV B 00100001b LPCCO BSET PRCO Write enabled MOV B 00001000b LPCC1 BCLR PRC
34. When the main clock on chip oscillator clock or PLI clock runs as CPU clock the WDC7 bit in the WDC register determines whether the prescaler divides the clock by 16 or 128 When the sub clock runs as CPU clock the prescaler divides the clock by 2 regardless of the WDC7 bit setting Watchdog timer cycle is calculated as follows Marginal errors due to the prescaler may occur in watchdog timer cycle With main clock source chosen for CPU clock on chip oscillator clock PLL clock Prescaler dividing 16 or 128 X Watchdog timer count 82768 CPU clock Watchdog timer period With sub clock chosen for CPU clock Prescaler dividing 2 X Watchdog timer count 32768 CPU clock Watchdog timer period For example when CPU clock is set to 16 MHz and the divide by N value for the prescale ris set to 16 the watchdog timer period is approx 32 8 ms The watchdog timer is initialized by writing to the WDTS register The prescaler is initialized after reset Note that the watchdog timer and the prescaler both are inactive after reset so that the watchdog timer is activated to start counting by writing to the WDTS register Write the WDTS register with shorter cycle than the watchdog timer cycle Set the WDTS register also in the beginning of the watchdog timer interrupt routine In stop mode and wait mode the watchdog timer and prescaler are stopped Counting is resumed from the held value when the modes or state are released Figure 10 1
35. 16 7 HCH Control Register 2 S4D0 Register The S4D0 register controls the error communication detection If the SCL clock is stopped counting dring data transfer each device is stopped staying online To avoid the situation the 12C bus interface circuit has a function to detect the time out when the SCL clock is stopped in high level H state for a specific period and to generate an 12C bus interface interrupt request See Figure 16 13 Sct clock stop H V ScL 1 clock 2 clock 3 clock 7 F SDA 1 bit 2 bit LA am d BB flag A Internal counter start signal Internal counter stop reset signal The time of timeout detection Internal counter overflow signal I C BUS interface interrupt request signal Figure 16 13 The timing of time out detection Rev 2 00 Jan 31 2007 page 270 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 16 MULTI MASTER GC bus INTERFACE 16 7 1 Bit0 Time Out Detection Function Enable Bit TOE The TOE bit enables the time out detection function When the TOE bit is set to 1 time out is detected and the EC bus interface interrupt request is generated when the following conditions are met 1 the BB flag in the S10 register is set to 1 bus busy 2 the SCL clock stops for time out detection period while high level H signal is maintained see Table 16 7
36. CHO Analog Input Pin Select Bit Invalid in repeat sweep mode 0 A D Operation Mode Select Bit 0 EIS 11 Repeat sweep mode 0 or Repeat sweep mode 1 Trigger Select Bit 0 Software trigger 1 Hardware trigger AD TRG trigger A D Conversion Start Flag 0 A D conversion disabled 1 A D conversion started Frequency Select Bit 0 Refer to Table 15 2 1 If the ADCONO register is rewritten during A D conversion the conversion result will be indeterminate A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol 0 L ADCON1 Address 03D716 After Reset 0016 i i Bit Symbol Bit Name Function SCANO A D Sweep Pin Select Bit 2 When selecting repeat sweep mode 0 bi bo 00 ANo to AN1 2 pins 0 1 ANo to AN3 4 pins 10 ANo to AN5 6 pins 11 ANo to AN7 8 pins A D Operation Mode Select Bit 1 0 Any mode other than repeat sweep mode 1 8 10 Bit Mode Select Bit 0 8 bit mode 1 10 bit mode Frequency Select Bit 1 Refer to Table 15 2 Vref Connect Bit 3 1 Vref connected Nothing is assigned When write set to 0 When read its content is 0 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 ANOo to ANO7 and AN20 to AN27 can be used in the same way as AN 0 to AN7 Use the ADGSEL1 to ADGSETO bits in the ADCO
37. CLKo RTSo CTSo OUTC17 INPC17 OUTC16 INPC16 OUTC15 INPC15 OUTC14 INPC14 OUTC13 INPC13 OUTC12 INPC12 OUTC11 INPC11 OUTC10 INPC10 INPC17 Rev 2 00 Jan 31 2007 REJ09B0047 0200 page 15 of 385 2tENESAS M16C 28 Group M16C 28 M16C 28B 1 Overview P60 CTSo RTSo P61 CLKo 34 4 gt Pe62 RxDo E Z 4 gt P15 INT3 ADTRG IDV ES 46 ES ak PieilNTaDu ak PIZ INTS INPC17 IDU 44 4 p20 0UTC1o INPC10 SDAMM gt P23 0UTC13 INPC13 gt P27 OUTCI7 INPC17 43 lt gt p24 OUTC11 INPC11 SCLuM lt P63 TxDo 42 4 P22 0UTC12 INPC12 41 39 lt gt P25 0UTC15 INPC15 38 ar P2 OUTC16 INPC16 40 4 gt P24 OUTC14 INPC14 48 4 P03 AN03 37 36 ES P02 ANO2 ZF P30 CLK3 PO1 ANO1 dE P31 SIN3 P00o ANOo lt gt P32 SouT3 P107 AN7 KI3 gt P33 P106 ANe Kle gt M16C 28 Group P6a CTS1 RTS1 CTSO CLKS1 P105 ANs Kli lt gt P65 CLK1 P104 AN4 Klo lt gt M1 6C 28 M1 6C 28B P66 RxD1 P103 AN3 gt _56 P67 TxD1 P102 AN2 lt gt P70 TxD2 SDA2 TAQouT RTS1 CTS1 CTSO CLKS1 P101 AN1 4 gt PLQP0064KB A 64P6Q A P71 RxD2 SCL2 TA0N CLK1 AVss gt P72 CLK2 TA10uUT V RxD1 P100 ANo 4 gt 60 P73 CTS2 RTS2 TA1IN V TXD1 VREF gt P74 TA2ouT W AVco gt P75
38. CO OUTC16 INPC16 ee OUTC15 INPC15 CH CH Rev 2 00 Jan 31 2007 page 17 of 385 REJ09B0047 0200 OUTC14 INPC14 2tENESAS M16C 28 Group M16C 28 M16C 28B 1 Overview Table 1 10 Pin Characteristics for 64 Pin Package continued Control Interrupt Multi master Pin Port Pin Timer Pin Timer S Pin UART Pin GC bus Pin Analog Pin P23 OUTC13 INPC13 P22 OUTC12 INPC12 P21 OUTC11 INPC11 SCLum P20 OUTC10 INPC10 SDAMM P17 INTS IDU INPC17 Pie INT4 IDW P15 INT3 IDV ADTRG P03 ANO3 P02 ANO2 P01 ANO1 POo ANOo P107 ks AN7 P106 Kl2 AN6 P105 Ki AN5 P104 Klo AN4 P103 AN3 P102 AN2 P101 AN1 AVss P100 ANo VREF AVcc P93 AN24 P92 TB2IN Rev 2 00 Jan 31 2007 page 18 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 1 Overview 1 5 Pin Description Table 1 11 Pin Description 64 pin 80 pin and 85 pin packages Classification Power Supply Vcc Vss Function Apply 2 7 to 5 5V to the Vcc pin Apply OV to the Vss pin Analog Power Supply AVC AVSS Supplies power to the A D converter Connect the AVCc pin to Vcc and the AVss pin to Vss Reset Input RESET The microcomputer is in a reset state when L is applied to the RESET pin CNVss CNVss Connect the CNVSss pin to Vss Main Clock Input XIN Main Clock Out
39. Determined by PD2e Input to INPC16 is always active P26 or INPC16 Single phase Waveform Output OUTC16 SR Waveform Output OUTC16 Phase delayed Waveform Output OUTC16 P2s INPC15 OUTC1s Determined by PD2s P25 Determined by PD25s Input to INPC1s is always active P25 or INPC 15 Single phase Waveform Output OUTC15 Determined by PD25 SR Waveform Output mode P25 Phase delayed Waveform Output OUTC15 P2a INPC14 OUTC14 Determined by PD24 P24 Determined by PD24 Input to INPC14 is always active P24 or INPC14 Single phase Waveform Output OUTC14 SR Waveform Output OUTC14 Phase delayed Waveform Output OUTC14 P23 INPC13 OUTC13 Determined by PD23 P23 Determined by PD23 Input to INPC13 is always active P23 or INPC13 Single phase Waveform Output OUTC13 Determined by PD23 SR Waveform Output mode P23 Phase delayed Waveform Output OUTC13 P22 INPC1 2 OUTC12 Determined by PD22 P22 Determined by PD22 Input to INPC12 is always active P22 or INPC12 Single phase Waveform Output OUTC12 SR Waveform Output OUTC12 Phase delayed Waveform Output OUTC12 P21 INPC11 OUTC11 Determined by PD21 P21 Determined by PD21 Input to INPC11 is always active P21 or INPC11 Single phase Waveform Output OUTC11 Determined by PD21 SR Waveform Output mode
40. Do not generate a DMA transfer 2 Block 1 and Block 0 are enabled for rewrite by setting FMRO2 bit in the FMRO register to 1 and setting FMR16 bit in the FMR1 register to 1 Block 2 to Block 5 are enabled for rewrite by setting FMR16 bit in the FMR1 register to 1 3 The time until entering erase suspend and reading flash is enabled is maximum a SA ES after satisfying the conditions Rev 2 00 Jan 31 2007 page 304 of 385 7tENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 18 Flash Memory Version 18 4 1 EW Mode 0 The microcomputer enters CPU rewrite mode by setting the FMRO01 bit in the FMRO register to 1 CPU rewrite mode enabled and is ready to accept software commands EW mode 0 is selected by setting the FMR11 bit in the FMR1 register to 0 To set the FMRO1 bit to 1 set to 1 after first writing 0 The software commands control programming and erasing The FMRO register or the status register indicates whether a programming or erasing opera tions is completed When entering the erase suspend during the auto erasing set the FMR40 bit to 1 erase suspend enabled and the FMR41 bit to 1 suspend request After waiting for td SR ES and verifying the FMR46 bit is set to 1 auto erase stop access to the user ROM area When setting the FMR41 bit to 0 erase restart auto erasing is restarted 18 4 2 EW Mode 1 EW mode 1 is selected by setting the FMR11 bit to 1
41. Figure 16 12 The timing of the interrupt generation at the completion of the data receive 16 6 3 Bits 2 3 Port Function Select Bits PED PEC If the ESO bit in the S1D0 register is set to 1 IC bus interface enabled the SDAmm functions as an output port When the PED bit is set to 1 and the SCLmmM functions as an output port when the PEC bit is set to 1 Then the setting values of P2_0 and P2_1 bits in the port P2 register are output to the 12C bus regardless of he internal SCL SDA output signals SCL SDA pins are onnected to EC bus interface circuit The bus data can be read by reading the port pi direction register in input mode regardless of the setting values of the PED and PEC bits Table 16 5 shows the port specification Table 16 5 Port specifications Pin Name ESO Bit PED Bit Pee E Function 0 0 1 Port I O function P20 1 0 SDA I O function 1 1 SDA input function port output function Pin Name ESO Bit PEC Bit gei Ee Function 0 0 1 Port I O function P21 1 Scu I O function 1 SCL input function port output funcion Rev 2 00 Jan 31 2007 page 268 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 16 MULTI MASTER GC bus INTERFACE 16 6 4 Bits 4 5 SDA SCL Logic Output Value Monitor Bits SDAM SCLM The SDAM SCLM bits can monitor the logic value of the SDA and SCL output signals from the 12C bus interface circuit The SDAM bit monitors the SDA output logic value The SCLM bit monitors the
42. H b7 b6 TCKO Count source select bit 00 fiorte TCK1 11 fc32 Figure 12 18 TBiMR Register in Timer Mode Rev 2 00 Jan 31 2007 page 116 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer 12 2 2 Event Counter Mode In event counter mode the timer counts pulses from an external device or overflows and underflows of other timers see Table 12 7 Figure 12 19 shows the TBiMR register in event counter mode Table 12 7 Specifications in Event Counter Mode Item Specification Count source e External signals input to TBiIN pin i 0 to 2 effective edge can be selected in program e Timer Bj overflow or underflow j i 1 except j 2 if i 0 Count operation e Decrement When the timer underflows it reloads the reload register contents and continues counting Divide ratio 1 n 1 n set value of TBi register 000016 to FFFF16 Count start condition Set TBiS bit to 1 start counting Count stop condition Set TBiS bit to 0 stop counting Interrupt request generation timing Timer underflow TBIIN pin function Count source input Read from timer Count value can be read by reading TBi register Write to timer e When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter e When counting after 1st count source input Value written to TBi register is written to only reload register Transferred to
43. M16C 28 Group M16C 28 M16C 28B 16 MULTI MASTER EC bus INTERFACE Sc SDA BB flag Bit reset signal l Ke d Related bits MST 1 5Viic cycle TRX Figure 16 21 The bit reset timing The STOP condition detection BB flag Bit reset signal Related bits BCO BC2 TRX slave mode Figure 16 22 The bit reset timing The START condition detection ScL H i PIN bit H l The bits referring BCO BC2 eons vo reset MST When in arbitration lost Bit reset signal it TRX When in NACK receive in slave lt gt transmit mode k S 2Vic cycle Bit set signal nh EE The bits referring TRX ALS 0 meanwhile the slave gt Ka to set receive R W bit 1 1Vic cycle Figure 16 23 Bit set reset timing at the completion of data transfer Rev 2 00 Jan 31 2007 page 280 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 16 MULTI MASTER GC bus INTERFACE 2 Generation of RESTART condition In order to generate a RESTART condition after 1 byte data transfer write E016 to the S10 register enter START condition standby mode and leave the SDAMM open Generate a START condition trigger by setting the S00 register after inserting a sufficient software wait until the SDAMM outputs a high level H signal Figure 16 24 shows the RESTART condition generation timing clock Insert software wait
44. Rev 2 00 Jan 31 2007 RENESAS REJ09B0047 0200 page 232 of 385 M16C 28 Group M16C 28 M16C 28B 15 A D Converter 15 1 6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode analog voltages applied to the selected pins are converted one by one to a digital code The input voltages of ANO and AN1 are sampled simultaneously using two circuits of sample and hold circuit Table 15 8 shows the simultaneous sample sweep mode specifications Fig ure 15 16 shows the operation example in simultaneous sample sweep mode Figure 15 17 shows ADCONO to ADCONZ registers and Figure 15 18 shows ADTRGCON registers in simultaneous sample sweep mode Table 15 9 shows the trigger select bit setting in simultaneous sample sweep mode In simultaneous sample sweep mode Timer BO underflow can be selected as a trigger by combining soft ware trigger ADTRG trigger Timer B2 underflow Timer B2 interrupt generation frequency setting counter underflow or A D trigger mode of Timer B Table 15 8 Simultaneous Sample Sweep Mode Specifications Item Specification Function The SCAN1 to SCANO bits in the ADCON1 register and ADGSEL1 to ADGSELO bits in the ADCON2 register select pins Analog voltage applied to the selected pins is converted one by one to a digital code At this time the input voltage of ANo and AN1 are sampled simultaneously A D Conversion Start Condition When the TRG bit in the ADCONDO register is 0 software trigger Set the ADST
45. The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to 1 under the conditions below e the VC27 bit in the VCR2 register is set to 1 low voltage detection circuit enabled e the D40 bit in the D4INT register is set to 1 low voltage detection interrupt enabled e the D41 bit in the D4INT register is set to 1 low voltage detection interrupt is used to exit stop mode e the voltage applied to the VCC pin is higher than Vdet4 the VC13 bit in the VCR1 register is 1 If the microcomputer is set to enter stop mode when the voltage applied to the VCC pin drops below Vdet4 and to exit stop mode when the voltage applied rises to Vdet4 or above set the CM10 bit to 1 when VC13 bit is 0 VCC lt Vdet4 5 5 3 Limitations on WAIT Instruction The low voltage detection interrupt is immediately generated and the microcomputer exits wait mode If WAIT instruction is executed under the conditions below e the CM02 bit in the CMO register is set to 1 stop peripheral function clock e the VC27 bit in the VCR2 register is set to 1 low voltage detection circuit enabled e the D40 bit in the D4INT register is set to 1 low voltage detection interrupt enabled e the D41 bit in the D4INT register is set to 1 low voltage detection interrupt is used to exit wait mode e the voltage applied to the VCC pin is higher
46. Two 2 Kbyte internal ROM areas block A and block B are available in the flash memory version The blocks are allocated addresses F00016 to FFFF16 The fixed interrupt vector tables are allocated addresses FFFDC16 to FFFFF 16 It stores the starting ad dress of each interrupt routine See the section on interrupts for details The internal RAM is allocated higher addresses beginning with address 0040016 For example 4 Kbytes internal RAM is allocated addresses 0040016 to 013FF16 Besides storing data it becomes stacks when the subroutine is called or an interrupt is acknowledged SFR consisting of control registers for peripheral functions such as I O port A D converter serial I O timers is allocated addresses 0000016 to 003FF16 All blank spaces within SFR are reserved and cannot be accessed by users The special page vector table is allocated to the addresses FFE0016 to FFFDB16 This vector is used by the JMPS or JSRS instruction For details refer to the M16C 60 and M16C 20 Series Software Manual Internal RAM area Internal ROM area Memory size XXXXX16 Memory size YYYYY16 4K bytes 6K bytes 01AFF16 64K bytes F000016 0009016 8K bytes 023FF16 96K bytes 12K bytes 033FF16 128K bytes E000016 0040016 Internal RAM Area FFE0016 RESERVED OF00016 Special Page Internal ROM Area Vector Table data space OFFFF16 I Undefined Instruction RESERVED Overflow BRK Instruction Single Step Watc
47. Voltage P0o to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 loL 5mA Output Low L Voltage P0o to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 loL 200uUA Output Low L Voltage High Power loL 1mA XoOutT Low Power loL 0 5mA Output Low L Voltage High Power No load applied XCOUT Low Power No load applied Hysteresis TAOmn TA4in TBOIN TB2in INTo INT5 NMI Age CTSo CTS2 SCL SDA CLKo CLK2 TA2out TA4our Klo Kls Rxpo Rxp2 Sinz SIN4 Hysteresis RESET Hysteresis XIN Input High H Current POo to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 Xin RESET CNVss Vi 5V Input Low L Current POo to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 Xin RESET CNVss VON Pull up Resistance P0o to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 Feedback Resistance XIN Feedback Resistance XCIN NOTES RAM Standby Voltage In stop mode 1 Referenced to Vcc 4 2 to 5 5V Vss 0V at Topr 20 to 85 C 40 to 85 C f BCLK 20MHz
48. Y mode CPU clock ROC s ROC 2 ROC 4 ROC 8 f ROC 16 Low speed mode CPU clock on cM Sub clock oscillation Low power dissipation mode CPU clock Von CM07 0 CMO CM15 1 On chip oscillator low power dissipation mode CPU clock ROC gt Arrow shows mode can be changed Do not change mode to another mode when no arrow is shown NOTES 1 Avoid making a transition when the CM20 bit is set to 1 oscillation stop re oscillation detection function enabled Set the CM20 bit to 0 oscillation stop re oscillation detection function disabled before transiting Wait for the main clock oscillation stabilization time before switching over Switch clock after oscillation of sub clock is sufficiently stable Change bits CM17 and CM16 before changing the CMO6 bit The PM20 bit in the PM2 register becomes effective when the PLC07 bit in the PLCO register is set to 1 PLL on Change the PM20 bit when the PLC07 bit is set to 0 PLL off Set the PM20 bit to 0 2 waits when PLL clock gt 16MHz Set the CMO6 bit to 1 division by 8 mode before changing back the operation mode from on chip oscillator mode to high or middle speed mode When the CM21 bit is set to 0 on chip oscillator turned off and the CMOS bit is set to 1 main clock turned off the CMO6 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High Figure 7 12 Sta
49. after the FMR01 bit is set to 1 set to 1 after first writing O The FMRO register indicates whether or not a programming or an erasing operation is completed Read status register cannot be read in EW mode 1 When an erase program command is initiated the CPU halts all program execution until the command operation is completed or erase suspend request is generated When enabling an erase suspend function set the FMR40 bit to 1 erase suspend enabled and ex ecute block erase commands Also the interrupt to transfer to erase suspend must be set enabled pre liminarily When entering erase suspend after td SR ES from an interrupt is requested interrupts can be accepted When an interrupt request is generated the FMR41 bit is automatically set to 1 suspend request and an auto erasing is suspended If an auto erasing has not completed when the FMROO bit is O after an interrupt process is completed set the FMR41 bit to 0 erase restart and execute block erase com mands again Rev 2 00 Jan 31 2007 page 305 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 18 Flash Memory Version 18 5 Register Description Figure 18 7 shows the flash memory control register 0 and flash memory control register 1 Figure 18 8 shows the flash memory control register 4 18 5 1 Flash Memory Control Register 0 FMRO FMR 00 Bit The FMROO bit indicates the operating state of the flash memory I
50. b G1BTRR enabled by setting bit RST4 to 1 and bits RST2 and RST1 to 0 FFFFi6 n 2 Base timer n 2 i i Ten Ten rg gt OUTC1j pin O Ams ee verse e Jp Inverse a e 1 2 n 2 H Ten 000016 i Write 0 by program if setting to 0 G1IRj bit j 1 to 7 e Setting value of the G1POj register n Setting value of either register G1PO0 or GIBTRR G1IRj bit Bits in the G1IR register The above applies under the following conditions e The IVL bit in the G1POCRj register is set to 0 L output as a default value The INV bit is set to 0 not inversed e The UD1 to UDO bits are set to 002 counter increment mode Figure 13 23 Phase delayed Waveform Output Mode Rev 2 00 Jan 31 2007 page 160 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 13 Timer S 13 5 3 Set Reset Waveform Output SR Waveform Output Mode Output signal level of the OUTC1j pin becomes high H when the INV bit in the G1POCRi i 0 to 7 is set to 0 output is not reversed and the base timer value matches the G1POj register value j 0 2 4 6 The H signal switches to a low level L signal when the base timer value matches the G1POk k j 1 register value Table 13 10 lists specifications of SR waveform mode Figure 13 24 shows an example of the SR waveform mode operation Table 13 10 SR Waveform Output Mode Specifications Item Specification Output waveform e Free running operation the RST1
51. e Before transmission can start the following requirements must be met The TE bit in the UiC1 register is set to 1 transmission enabled The TI bit in the UiC1 register is set to 0 data present in UITB register If CTS function is selected input on the CTSi pin is set to L Reception start condition e Before reception can start the following requirements must be met The RE bit in the UiC1 register is set to 1 reception enabled Start bit detection e For transmission one of the following conditions can be selected The UiIRS bit 2 is set to 0 transmit buffer empty when transferring data from the UiTB register to the UARTIi transmit register at start of transmission The UiIRS bit is set to 1 transfer completed when the serial I O finished sending data from the UARTi transmit register e For reception When transferring data from the UARTIi receive register to the UIRB register at completion of reception Error detection e Overrun error 7 This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit in the the next data e Framing error This error occurs when the number of stop bits set is not detected e Parity error This error occurs when if parity is enabled the number of 1 s in parity and character bits does not match the number of 1 s set e Error sum flag This flag is set to 1 when an
52. e Program e Block erase 20 14 5 Writing Command and Data Write the command code and data at even addresses 20 14 6 Program Command Write xx4016 in the first bus cycle and write data to the write address in the second bus cycle and an auto program operation data program and verify will start Make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle 20 14 7 Operation Speed When CPU clock source is main clock before entering CPU rewrite mode EW mode 0 or 1 select 10 MHZ or less for CPU clock using the CMO6 bit in the CMO register and the CM17 to CM16 bits in the CM1 register Also when CPU clock is f3 ROC on chip oscillator clock before entering CPU rewrite mode EW mode 0 or 1 set the ROCR3 to ROCR2 bits in the ROCR register to divied by 4 or divide by 8 On both cases set the PM17 bit in the PM1 register to 1 with wait state 20 14 8 Instructions Inhibited Against Use The following instructions cannot be used in EW mode 0 because the flash memory s internal data is referenced UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction Rev 2 00 Jan 31 2007 page 375 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 20 Precautions 20 14 9 Interrupts EW Mode 0 e Any interrupt which has a vector in the variable vector table can be used providing that its vector is tra
53. e When the timer underflows it reloads the reload register contents and continues counting Divide ratio 1 n 1 n set value of TBi register i O to 2 000016 to FFFF16 Count start condition Set TBiS bitlNote to 1 start counting Count stop condition Set TBiS bit to 0 stop counting Interrupt request generation timing Timer underflow TBIIN pin function I O port Read from timer Count value can be read by reading TBi register Write to timer e When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter e When counting after 1st count source input Value written to TBi register is written to only reload register Transferred to counter when reloaded next NOTE 1 The TBOS to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register Timer Bi Mode Register i 0 to 2 b7 b6 b5 b4 b3 b2 bi b0 olo Symbol Address After Reset TBOMR to TB2MR 039B16 to 039D 16 00XX00002 d R D b1 b0 Operation mode select bit 0 0 Timer mode or A D trigger mode No effect in timer mode MRI O Can be set to 0 or 1 RW MR1 MR2 TBOMR register Set to 0 in timer mode TB1MR TB2MR registers Nothing is assigned When write set to 0 When read its content is indeterminate MR3 When write in timer mode set to 0 When read in timer mode the content is indeterminate
54. eseyd n s nd oys uo 19 S16 1 y ys Ve py Jou Ieper Ly K peojay 19481691 wt Ou 0128S S 4q SPY U YM D 0118S yndjno seyd iy or Ssouppe 49 4s 6ay o4JUOD UO OUN UE E EP UOHISOd JO 0 Ufro z Sug 7g jeu Joiuno ZG LOI lt euBis nd no seyd n 1 aan Je66u saysued ssz 4 u Jeun au peag Ssz o u Jee peojay 10 jsenbe ydnuu yu GLO p u 19181681 La peoj y k 13451531 wi JeuBis j01 u09 peoa py Jeu reubs 186614 yels p Z L Ui Jeu pow Jeu Jeu ANI ed U zg Jeu 0 USM aq 0 jeufiSs wae No19 jee 9U UNIDO Knuet SLO u 19481691 Zg LOI mojp pun zg w Figure 12 25 Three phase Motor Control Timer Functions Block Diagram 2tENESAS Rev 2 00 Jan 31 2007 page 123 of 385 REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer Three phase PWM Control Register 0 1 b7 b6 b5 b4 b3 b2 bi b Symbol Address After Reset INVCO 034816 0016 Bit Symbol Bit Name Function Effective interrupt output ICTB2 counter is incremented by 1 on INVOO polarity select bit the rising edge of timer A1 reload control signal ICTB2 counter is incremented by 1 on the falling edge of timer A1 reload control signal 3 Effective interrupt output ICTB2 counter incremented by 1 at a specification bit timer B2 underflow 3 4 Selected by INVOO bit Mode selec
55. is added e Figure 18 5 ROMCP Address is modified e Table 18 3 EW Mode 0 and EW Mode 1 Note 2 mark is modified e 18 5 2 Flash Memory Control Register 1 FMR1 FMR17 Bit is modified e Figure 18 7 FMR1 Register Reserved bit map is modified note 1 is modified e Figure 18 8 FMR4 Register Note 2 is modified e Figure 18 10 Setting and Resetting of EW Mode 1 Note 1 deleted Note 3 is added e Table 18 8 Pin Descriptions Flash Memory Standard Serial I O Mode P90 to P97 are modified Electrical Characteristics e Table 19 1 Absolute Maximum Ratings Parameter of Topr is partially modified e Table 19 2 Recommended Operating Conditions Vu and VIL are modified e Table 19 5 Flash Memory Version Electrical Characteristics Note 6 and Note 8 are partially modified e Table 19 8 Electrical Characteristics 1 Condition of VoL and VT VT are modified e Table 19 9 Electrical Characteristics 2 Mask memory information is added note 5 is deleted e Table 19 24 Electrical Characteristics 1 Condition of VOL VT VT and IIL are modified e Table 19 25 Electrical Characteristics 2 Mask memory information is added note 5 is deleted Precautions e 20 1 3 For Flash Memory 128K 4K Version and Mask ROM Version is added e Figure 20 1 LPCCO Register and LPCC1 Register is added e 20 3 2 Power Control Program example in 4 is modified e 20 11 2 AL Flag is modified e 20 14 Mask ROM Version is added e 20 16 1 Trace of Print Board 85 pin Version is added
56. n BRGi divides the count source 0016 to FFie wo byn 1 1 Write to this register while serial I O is neither transmitting or receiving 2 Use MOV instruction to write to this regisgter 3 Set the SiBRG register after setting the SMi1 and SMi0 bits in the SiC register SI Oi Transmit receive Register i 3 4 1 2 ee b0 Symbol Address After Reset S3TRR 036016 Indeterminate S4TRR 036416 Indeterminate Transmission reception starts by writing transmit data to this register After RW transmission reception finishes reception data can be read by reading this register 1 Write to this register while serial I O is neither transmitting or receiving 2 To receive data set the corresponding port direction bit for Gw ti O input mode Figure 14 36 S3C and S4C Registers SS3BRG and S4BRG Registers and S3TRR and S4TRR Registers Rev 2 00 Jan 31 2007 page 213 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 14 Serial I O Table 14 20 SI O3 and SI O4 Specifications Item Specification Transfer data format e Transfer data length 8 bits Transfer clock e The MG bit in the SiC i 3 4 register is set to 1 internal clock fj 2 n 1 fj f1SIO fesio fasio f32S10 n Setting value of SIBRG register 0016 to FF 16 e SMi6 bit is set to 0 external clock Input from CLKi pin Transmission reception start condition e Before transmission reception can start the following req
57. registers and the status thereof are the same as in hardware reset 1 The microcomputer cannot exit stop mode by brown out detection reset hardware reset 2 Rev 2 00 Jan 31 2007 page 32 of 385 2tENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 5 Reset Recommended operating i voltage RESET KE Equal to or less Equal to or less than 0 2Vcc than 0 2Vcc lt More than td ROC td P R Figure 5 1 Example Reset Circuit 5 2 Software Reset When the PMO3 bit in the PMO register is set to 1 microcomputer reset the microcomputer has its pins CPU and SFR initialized Then the program is executed starting from the address indicated by the reset vector The device will reset using internal on chip oscillator as the CPU clock At software reset some SFR s are not initialized Refer to 4 Special Function Register SFR 5 3 Watchdog Timer Reset When the PM12 bit in the PM1 register is 1 reset when watchdog timer underflows the microcomputer initializes its pins CPU and SFR if the watchdog timer underflows The device will reset using internal on chip oscillator as the CPU clock Then the program is executed starting from the address indicated by the reset vector At watchdog timer reset some SFP s are not initialized Refer to 4 Special Function Register SFR 5 4 Oscillation Stop Detection Reset When the CM20 bit in the CM2 register is set to 1 oscillation sto
58. wae nee ai eee e Rae LA Satse rahe ere RO A ODPL See MR ROAD AE AOR eR TE 360 20 6 1 TimMer A E 360 206 2 INMGk EE 363 20 6 3 Three phase Motor Control Timer Function ccecceeeeeeeeeeeeeeeeteeeeeeeeeeeentaeeeees 364 PAG BY BUN AY 2 che eer er nee eee nee ETT ORC OE eae tern en EE OORT CE ea PE one rae 365 20 7 1 Rewrite the G1IR Register eet 365 20 7 2 Rewrite the ICOCIIC Hegtster AAA 366 20 7 3 Waveform Generating EU DEE ccssseiceicetiereseiecaieet a eiecietend eed eieres estes 366 20 7 4 IC OC Base Timer lnterupt 366 20 8 Seral e EE 367 20 8 1 Clock Synchronous Serial EE 367 20 82 UART MOOG ug 368 20 89 SOS SO EE 368 SEET EE 369 20 10 Multi master C bus Interface cccccecceeeeeeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeceeeeeeseeeeeseeeeeees 371 20 10 1 Writing to the SOO Register en 371 Ze 2 Pal Ee 371 20 11 Programmable Ee TEE 372 20 12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version 373 20 13 Mask TR 374 20 131 Intemna ROM EE EE EE 374 20 13 2 Reserved EE deed LEE teh 374 20714 Flash Memory e EE 375 20 14 1 Functions to Inhibit Rewriting Flash Memory Rewrite ceeeeeeteeeeeteeeees 375 20 14 2 Stop e 375 2014S Walt EE eidele Ee Eet A RR 375 20 14 4 Low Power Dissipation Mode On Chip Oscillator Low Power Dissipation Mode 375 20 14 5 Writing Command and Data 375 20 14 6 Program Command EE 375 20 14 7 Operation Speed EE 375 20 14 8 Instructions Inhibited
59. 0 1 Trigger Select Bit Refer to Table 15 11 A D Conversion Start Flag 2 Frequency Select Bit 0 0 A D conversion disabled 1 A D conversion started Refer to Table 15 2 1 If the ADCONDO register is rewritten during A D conversion the conversion result will be indeterminate 2 Do not write 1 in delayed trigger mode 0 When write set to 0 A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 0 Symbol ADCON Address 03D716 After Reset 0016 Bit Symbol Bit Name Function SCANO SCAN1 A D Sweep Pin Select Bit 2 When selecting delayed trigger sweep mode 0 b1 bo 0 0 ANo to AN1 2 pins 0 1 ANo to ANs 4 pins 1 0 ANo to ANs 6 pins 1 1 ANo to AN7 8 pins MD2 BITS A D Operation Mode Select Bit 1 8 10 Bit Mode Select Bit 0 Any mode other than repeat sweep mode 1 0 8 bit mode 1 10 bit mode CKS1 Frequency Select Bit 1 Refer to Table 15 2 VCUT Vref Connect Bit 3 1 Vref connected b7 b6 Nothing is assigned When write set to 0 When read its content is 0 1 If the ADCON1 register is rewritten during A D conversion the conversion result will be indeterminate 2 AN00 to ANO7 and AN20 to AN27 can be used in the same way as AN 0 to AN7 Use the ADGSEL1 to ADGSELO bits in the ADCON2 register to select the desired pin 3 If the VCUT bit is reset
60. 0 ADTRGCON 03D216 0016 Bisinba L A D Operation Mode 1 Simultaneous sample sweep mode Select Bit 2 or delayed trigger mode 0 1 DTE A D Operation Mode 0 Any mode other than delayed trigger Select Bit 3 mode 0 1 HpTRGo ANO Trigger Select Bit Refer to Table 15 9 es Ir is assigned When write set to 0 es IS read its content is 0 1 If ADTRGCON register is rewritten during A D conversion the conversion result will be indeterminate Figure 15 18 ADTRGCON Register in Simultaneous Sample Sweep Mode Table 15 9 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode TRG TRG1 HPTRGO TRIGGER 0 R S Software trigger 1 1 Timer BO underflow 1 1 0 0 ADTRG 1 1 0 Timer B2 or Timer B2 interrupt generation frequency setting counter underflow 2 NOTES 1 A count can be started for Timer B2 Timer B2 interrupt generation frequency setting counter underflow or the INT5 pin falling edge as count start conditions of Timer BO 2 Select Timer B2 or Timer B2 interrupt generation frequency setting counter using the TB2SEL bit in the TB2SC register Rev 2 00 Jan 31 2007 page 235 of 385 RENESAS REJ09B0047 0200 15 1 7 Delayed Trigger Mode 0 In delayed trigger mode 0 analog voltages applied to the selected pins are converted one by one to a digital code The delayed trigger mode 0 used in combination with A D trigger mode of Timer B The Timer BO underflow starts a single
61. 03101 WG control register 0 G1POCRO 141 021116 031116 WG control register 1 G1POCR1 141 021216 031216 WG control register 2 G1POCR2 141 021316 031316 WG control register 3 G1POCR3 141 021416 031416 WG control register 4 G1POCR4 141 021516 031516 WG control register 5 G1POCR5 141 021616 031616 WG control register 6 G1POCR6 141 021716 031716 WG control register 7 G1POCR7 141 021816 031816 TM control register 0 G1TMCRO 140 021916 031916 TM control register 1 G1TMCRI1 140 031A1s TM control register 2 G1TMGR2 140 031Bis TM control register 3 G1TMGCR3 140 031C16 TM control register 4 G1TMCR4 140 025016 031D16 TM control register 5 G1TMCR5 140 025116 031E16 TM control register 6 G1TMCR6 140 025216 031F 1s TM control register 7 G1TMCR7 140 025316 032016 025416 e Base timer register G1BT 137 025516 0322 s Base timer control register 0 GiBCRO 137 025616 032316 Base timer control register 1 GiBCR1 138 025716 032416 TM prescale register 6 GiTPR6 140 025816 032516 TM prescale register 7 G1TPR7Z 140 025916 032616_ Function enable register G1FE 143 025A16 032716 Function select register G1FS 143 025B16 032816 k DES F 47 E Base timer reset register G1BTRR 139 025D16 PACR 172 292 032Ai6 Divider register G1DV 138 025E16 Peripheral clock select register PCLKR 49 032Bis 025F 6 ow power Consumption Control 1 LPCC1 351 032C 16 032D16 032E16 032F16 02E01s 2C0 data shift register Soo 253 033016 Interrupt
62. 037816 0016 bob dob oF 4 d Bit a a a a SMDO al UO mode select bit Serial I O disabled Se EE Clock synchronous serial UO mode 3 re re ce ae ee 12C bus mode UART mode transfer data 7 bits long GE UART mode transfer data 8 bits long i UART mode transfer data 9 bits long hort o not set the value other than the above E CKDIR Internal external clock 0 Internal clock horn select bit 1 External clock 1 GE STPS Stop bit length select bit o One stop bit H Two stop bits TE PRY Odo even parity select bit Effective when PRYE 1 moo o Odd parity Even parity SS PRYE Party enable bit Ge Parity disabled j Parity enabled EE IOPOL TxD RxD I O polarity 0 No reverse reverse bit 1 Reverse NOTES 1 Set the corresponding port direction bit for each CLK2 pin to 0 input mode 2 To receive data set the corresponding port direction bit for each RxD2 pin to 0 input mode 3 Set the corresponding port direction bit for SCL 2 and SDA2 pins to 0 input mode Figure 14 5 UOMR to U2MR Registers Rev 2 00 Jan 31 2007 page 170 of 385 RENESAS R J09B0047 0200 M16C 28 M16C 28B 14 Serial I O M16C 28 Group M16C 28 M16C 28B 14 Serial I O UARTIi Transmit receive Control Rregister 0 i 0 to 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset UOCO to U2C0 03A416 03AC16 037C16 000010002 to a a oto to toad Symbol Bit Name
63. 038E16 Timer A3 Timer AO register O TAk overflow ct _UDF register_ o k i 1 however k 0 when i 4 Pulse output Toggle flip flop NOTES 1 Overflow or underflow Figure 12 3 Timer A Block Diagram Timer Ai Mode Register i 0 to 4 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset TAOMR to TA4MR 039616 to 039A16 0016 Bit Symbol TMODO Operation mode select bit 9 0 Timer mode RW 0 1 Event counter mode TMOD1 1 0 One shot timer mode 1 1 Pulse width modulation PWM mode Function varies with each operation mode t TCKO Count source select bit Function varies with each operation mode Figure 12 4 TAOMR to TA4MR Registers Rev 2 00 Jan 31 2007 page 100 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer Timer Ai Register i 0 to 4 1 b8 b0 b7 Address 038716 038616 038916 038816 038B16 038A16 Symbol TAO TAI TA2 TAS TA4 038D16 038C16 038F 16 O38E16 After Reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function Setting Range Event counter mode Divide the count source by n 1 where n set value Divide the count source by FFFF16 n 1 where n set value when counting up or by n 1 when counting down 000016 to FFFF16 000016 to FFFF16 One shot 000016 to FFFF16 Divide the count source by n where n set value and cause the timer to stop Modify t
64. 03BA1s DMA1 request cause select register DM1SL 9 037Bis O3BBis 037Cis UART2 transmit receive control register 0 U2C0 171 03BC16 037D16 UART2 transmit receive control register 1 U2C1 172 O3BDi6 SR UART2 receive buffer register U2RB 169 VE 037Fi6 O3BFi6 NOTE 1 The blank areas are reserved and cannot be accessed by users B 3 Quick Reference by Address Address Register Symbol Page 03C016 RE A D register 0 ADO 221 03C216 Sc A D register 1 AD1 201 03C416 Dee A D register 2 AD2 201 980616 A D register 3 AD3 221 030716 980816 A D register 4 AD4 221 030916 03CA16 y PN A D register 5 AD5 221 Tri A D register 6 AD6 221 03CD16 03CE16 d E A D register 7 AD7 221 O3D016 03D116 03D216 A D trigger control register ADTRGCON 220 03D316 A D convert status register 0 ADSTATO 221 03D416 A D control register 2 ADCON2 219 03D516 03D616 A D control register D ADCONO 219 03D716 A D control register 1 ADCON1 219 03D816 03D916 03DA16 O3DBi6 03DC16 03DD16 03DE16 03DF16 03E016 Port PO register PO 290 03E116 Port P1 register Pi 290 03E2 6 Port PO direction register PDO 289 03E316 Port P1 direction register PD1 289 03E416 Port P2 register P2 290 03E516 Port P3 register P3 290 03E616 Port
65. 1012 EC bus mode and 0 when they are set to 1002 UART mode transfer data 7 bits long or 1102 UART mode transfer data 9 bits long 3 CTS1 RTS can be used when the CLKMD1 bit in the UCON register is set to 0 only CLK1 output and the RCSP bit in the UCON register is set to 0 CTS0 RTSo not separated SDA2 and SCL2 are effective when i 2 When the SMD2 to SMDO bits in UiMR regiser are set to 0002 serial I O disable do not set NCH bit to 1 TxDi SDA2 and SCL2 pins are N channel open drain output Zk When the U1MAP bit in PACR register is 1 P7 3 to P70 CTS RTS pin in UART1 is assigned to P7 0 When the CLK1 and CLKO bit settings are changed set the UiBRG register NO UART Transmit receive Control Register 2 ae See Symbol Address After Reset UCON 03B016 x00000002 Bit Symbol Function RW UARTO transmit interrupt Transmit buffer empty TI 1 RW cause select bit Transmission completed TXEPT 1 sch oO oe 3 UART1 transmit interrupt rr a a r cause select bit O Transmit buffer empty TI 1 RW Transmission completed TXEPT 1 EOR b o foa A UARTO continuous UORRM Continuous receive mode disabled RW receive mode enable bit Continuous receive mode enable sch oOo UART1 continuous Continuous receive mode disabled i RW receive mode enable bit Pobre EEN Continuous receive mode enabled oO ffective when CLKMD1 bit is set to 1
66. 11 DMAC 1 When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock SES CPU use x Source X Destination RD signal WR signal Data Destination 2 When the transfer unit is 16 bits and the source address of transfer is an odd address CPU clock Address bus CPU use Y Sou RD signal WR signal Data P P Du se y P CPU u Source Source 1 Destination cycle CPU use 3 When the source read cycle under condition 1 has one wait state inserted CPU clock ein CPU use Source Destination CPU use RD signal WR signal Data e Dumm bus CPU use x Source A Destination X Sc TU cPUuse 4 When the source read cycle under condition 2 has one wait state inserted ee E E EE E d Address RD signal WR signal Data WS bus CPU use X Source X Source 1 Destination NOTES 1 The same timing changes occur with the respective conditions at the destination as at the source Figure 11 5 Transfer Cycles for Source Read Rev 2 00 Jan 31 2007 page 94 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 11 DMAG 11 2 DMA Transfer Cycles Any combination of even or odd transfer read and write
67. 12 Timer One shot Start Flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset ONSF 038216 0016 JEETS Timer AO one shot start flag The timer starts counting by setting s this bit to 1 while the TMOD1 to Timer A1 one shot start lag TMODO bits of TAIMR register i PW TA20S Ti A2 sh fl 0 to 4 102 one shot timer TA20S _ Timer A2 one shot start flag mode and the MR2 bit of TAIMR RW Timer A3 one shot start flag register 0 TAiOS bit enabled RW When read its content is 0 Timer A4 one shot start flag Z phase input enable bit 2 Phase input disabled TAOTGL Timer AO event trigger Se Ka selber bit e s9 0 0 Input on TAOIN is selected RW 0 1 TB2 overflow is selected 2 TAOTGH 1 0 TA4 overflow is selected 2 11 TA1 overflow is selected 2 1 Make sure the PD7_1 bit in the PD7 register is set to O input mode 2 Overflow or underflow Trigger Select Register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset TRGSR 038316 0016 EA Li TAITGL Input on TA1IN is selected 1 Timer A1 event trigger TB2 is selected 2 select bit TAO is selected 2 TA2 is selected 2 zl TA2n is sel Timer A2 event trigger TB2 is selected e select bit TA1 is selected 2 TAS is selected 2 Input on TAIN is selected 1 TB2 is selected 2 TA2 is selected 2 TA4 is selected 2 Timer A3 event trigger select bit 8 Input on TAdw is sel
68. 14 Serial I O 14 1 2 2 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode follow the procedure below e Resetting the UIRB register i 0 to 2 1 Set the RE bit in the UiC1 register to 0 reception disabled 2 Set the RE bit in the UiC1 register to 1 reception enabled e Resetting the UiTB register i 0 to 2 1 Set the SMD2 to SMDO bits in UM register 0002 Serial I O disabled 2 Set the SMD2 to SMDO bits in UIMR register 0012 1012 1102 3 1 is written to TE bit in the UiC1 register reception enabled regardless of the TE bit 14 1 2 3 LSB First MSB First Select Function As shown in Figure 14 18 use the UFORM bit in the UiCO register to select the transfer format This function is valid when transfer data is 8 bits long 1 When the UFORM bit in the UiCO register is set to 0 LSB first CLKi Ta st Xf DO X D1 X D2 X D3 X D4 X Ds X De X D7 X P Y SP RXDi st K Do X Di X D2 X Ds X Da X D5 X De X D7 X P Y SP 2 When the UFORM bit in the UiCO register is set to 1 MSB first CLKi TxDi ST D7 X De X Ds X Da X D3 X D2 X D1 X DoX P Y SP Dap sT D7 X DeX D5 X D4 X D3 X D2X D1 X DoX P Y sP ST Start bit P Parity bit SP Stop bit i 0to2
69. 2 00 Jan 31 2007 REJ09B0047 0200 page 3 of 385 2tENESAS M16C 28 Group M16C 28 M16C 28B 1 Overview 1 2 Block Diagram Figure 1 1 is a block diagram of the M16C 28 Group 80 pin and 85 pin packages Figure 1 2 is a block diagram of the M16C 28 Group 64 pin package 8 Port PO Port P Port P2 Port P3 9d HOd Timer 16 bits UART clock synchronous SI O System clock generator Output Timer A 5 8 bits x 3 channels XIN XOUT Input Timer B 3 Clock synchronous SI O XCIN XCOUT 8 bits x 2 channels On chip oscillator 3 phase PWM Multi master DC bus PLL frequency synthesizer i 8 Timer S Input capture Output compare Time measurement 8 channels M16C 60 Series CPU Core Memory Waveform generating 8 channels m ROM SB A D converter 10 bits x 24 channels RAM Watchdog timer 15 bits FLG Multiplier DMAC 2 channels Old HOd 6d Od 8d YOd Zd W0d 1 ROM size depends on MCU type 2 RAM size depends on MCU type Figure 1 1 M16C 28 Group Block Diagram 80 Pin Package and 85 Pin Package Rev 2 00 Jan 31 2007 page 4 of 385 ztENESAS REJ09B0047 0200 M Rev 2 00 Jan 31 2007 16C 28 Grou I O Ports M16C 28 M16C 28B Port P1 1 Overview Port P2 Internal Peripheral Functions Timer 16 bits Output Timer A 5 Input Timer B 3 3 phase PWM Timer S Input capture Output Se
70. 2 lists the relocatable vector tables Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses Table 9 2 Relocatable Vector Tables Interrupt source Vector address 1 Software interrupt Address L to address H number BRK instruction 5 0 to 3 0000 16 to 000316 Reserved INT3 IC OC interrupt 0 S 4 IC OC interrupt 1 12C bus interface 6 24 to 27 001816 to 001B16 S IC OC base timer ScL Spa 4 28 to 31 001 C16 to O01F 16 Reference M16C 60 M16C 20 series software manual Timer S Multi Master 12C bus interface Be SUO4 INT5 2 32 to 35 0020 16 to 002316 SI O3 INT4 2 36 to 39 0024 16 to 002716 Be INT interrupt Serial I O Be UART 2 bus collision detection 6 40 to 43 0028 16 to 002B 16 44 to 47 002C 16 to 002F 16 48 to 51 003016 to 003316 Key input interrupt 52 to 55 0034 16 to 003716 S Serial I O Key input interrupt A D 56 to 59 0038 16 to 003B16 A D convertor UART2 transmit NACK2 3 60 to 63 003C 16 to 003F 16 UART2 receive ACK2 3 64 to 67 004016 to 004316 UARTO transmit 68 to 71 0044 16 to 004716 UARTO receive 72 to 75 0048 16 to 004B16 UART1 transmit 76 to 79 004C 16 to 004F 16 UART1 receive 80 to 83 0050 16 to 005316 Serial I O Timer AO 84 to 87 0054 16 to 00
71. 2 to 4 Count operation Increment or down count can be selected by two phase pulse signal e When the timer overflows or underflows it reloads the reload register con tents and continues counting When operating in free running mode the timer continues counting without reloading Divide ratio 1 FFFF16 n 1 for increment 1 n 1 for down count n set value of TAi register 000016 to FFFF16 Count start condition Set TAIS bit in the TABSR register to 1 start counting Count stop condition Set TAIS bit to 0 stop counting Interrupt request generation timing Timer overflow or underflow TAIIN pin function Two phase pulse input TAiOUT pin function Two phase pulse input Read from timer Count value can be read by reading timer A2 A3 or A4 register Write to timer e When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter e When counting after 1st count source input Value written to TAi register is written to reload register Transferred to counter when reloaded next Select function Note e Normal processing operation timer A2 and timer A3 The timer counts up rising edges or counts down falling edges on TAJIN pin when input signals on TAJOUT pin is H vam LT LIL TAJIN Aa Lady In j 2 3 Increment Increment Increment Decrement Decrement Decrement e Multiply by 4 processing operation
72. 25 us 25 3 25 us 13 3 0 us 12 8 1 812 1 XXX00100 5 0 us 5 3 0 us 3 2 0us 2 4 1 202 2 XXX01100 6 5 us 13 3 5us 7 3 0 us 6 XXX01010 5 5 us 11 3 0 us 6 2 5us 5 2 1 242 1 XXX00100 5 0 us 5 3 0us 3 2 0 us 2 NOTES 1 Do not set odd values or 000002 to START STOP condition setting bits SSC4 to SSCO 2 When the PCLKO bit in the PCLKR register is set to 1 Rev 2 00 Jan 31 2007 page 258 of 385 REJ09B0047 0200 RENESAS M16C 28 Group M16C 28 M16C 28B 16 MULTI MASTER GC bus INTERFACE 16 1 I2CO Data Shift Register S00 register The S00 register is an 8 bit data shift register to store a received data and to write a transmit data When a transmit data is written to the S00 register the transmit data is synchronized with a SCL clock and the data is transferred from bit 7 Then every one bit of the data is transmitted the register s content is shifted for one bit to the left When the SCL clock and the data is imported into the S00 register from bit 0 Every one bit of the data is imported the register s content is shifted for one bit to the left Figure 16 9 shows the timing to store the receive data to the S00 register The S00 register can be written when the ESO bit in the S1D0 register is set to 1 I CO bus interface enabled If the S00 register is written when the ESO bit is set to 1 and the MST bit in the S10 register is set to 1 master mode the bit counter is reset and the SC
73. 28 Group M16C 28 M16C 28B 20 Precautions Changing the interrupt source Disable interrupts 2 3 Change the interrupt generate factor including a mode change of peripheral function Use the MOV instruction to clear the IR bit to 0 interrupt not requested 3 Enable interrupts 2 3 End of change IR bit A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES 1 The above settings must be executed individually Do not execute two or more settings simultaneously using one instruction 2 Use the flag for the INTi interrupt i 0 to 5 For the interrupts from peripheral functions other than the INTT interrupt turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor In this case if the maskable interrupts can all be disabled without causing a problem use the flag Otherwise use the corresponding ILVL2 to ILVLO bit for the interrupt whose interrupt generate factor is to be changed Refer to 20 5 6 Rewrite the Interrupt Control Register for details about the instructions to use and the notes to be taken for instruction execution Figure 20 3 Procedure for Changing the Interrupt Generate Factor 20 4 5 INT Interrupt 1 Either an L level of at least tw INL or an H level of at least tw INH width is necessary for the signal input to pins IN
74. 3 4 5 6 and 7 in the ADSTATO register Figure 15 25 Each Flag Operation in ADSTATO Register Associated with the Operation Example in Delayed Trigger Mode 1 1 Rev 2 00 Jan 31 2007 page 244 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 15 A D Converter Example 3 When ADrrc input falling edge is generated more than two times after ANo pin conversion EI A D pin input voltage sampling A D pin conversion ADrrc pin input t 1 l d ADST flag ADERRO flag ADERR1 flag ADTCSF flag ADSTTO flag ADSTT1 flag ADSTRTO flag ADSTRT1 flag ANo AN AN2 AN3 f valid after single sweep conversion invalid Do not set to 1 by program 1 1 IR bit in the ADIC 4 register Set to 0 when interrupt request acknowledgement or a program ADST flag Bit 6 in the ADCONO register ADERRO ADERR1 ADTCSF ADSTTO ADSTT1 ADSTRTO and ADSTRT1 flaa bits 0 1 3 4 5 6 and 7 in the ADSTATO reaister Figure 15 26 Each Flag Operation in ADSTATO Register Associated with the Operation Example in Delayed Trigger Mode 1 2 Rev 2 00 Jan 31 2007 page 245 of 385 REJ09B0047 0200 2tENESAS M16C 28 Group M16C 28 M16C 28B A D Control Register 0 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol 1 E ADCONO Address 03D616 After Reset 00000XXX2 Bit Symbol Bit Name Function CHO Analog Input Pin Select Bit CH1 CH2 b2
75. 3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode the timer measures pulse period or pulse width of an external signal see Table 12 8 Figure 12 20 shows the TBiMR register in pulse period and pulse width measurement mode Figure 12 21 shows the operation timing when measuring a pulse period Figure 12 22 shows the operation timing when measuring a pulse width Table 12 8 Specifications in Pulse Period and Pulse Width Measurement Mode Item Specification Count source f1 f2 f8 f32 fc32 Count operation e Increment e Counter value is transferred to reload register at an effective edge of mea surement pulse The counter value is set to 000016 to continue counting Count start condition Set TBiS i 0 to 2 bit to 1 start counting Count stop condition Set TBiS bit to 0 stop counting Interrupt request generation timing e When an effective edge of measurement pulse is input ll e Timer overflow When an overflow occurs MR bit in the TBiMR register is set to 1 overflowed simultaneously MR3 bit is cleared to 0 no overflow by writ ing to TBiMR register at the next count timing or later after MR3 bit was set to 1 At this time make sure TBiS bit is set to 1 start counting TBIIN pin function Measurement pulse input Read from timer Contents of the reload register measurement result can be read by reading TBi regis
76. 5 to 6 cycles of UIBRG count source 6 to 7 cycles of UIBRG count source RW E ch ch uA C000 7 to 8 cycles of UIBRG count source NOTES 1 The DL2 to DLO bits are used to generate a delay in SDAI output by digital means during 12C bus mode In other than 12C bus mode set these bits to 0002 UART mode transfer data 9 bits long 2 The amount of delay varies with the load on SCL2 and SDA2 pins Also when using an external clock the amount of delay increases by about 100 ns UART2 Special Mode Register 4 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset U2SMR4 037416 0016 SCL2 SDA output 0 Start and stop conditions not output 1 Start and stop conditions output 0 ACK TE eee ee ACK data bit 1 NACK l ACK data output 0 Serial I O data output po onan rararescscsc ss 1 ACK data output RW SCL2 output stop 0 Disabled RW Caan miaii aaa aa pe negen 1 Enabled AN 0 SCL2 L hold disabled edt ena tee SWC9 SCL2 wait bit 3 1 SCL2 L hold enabled NOTE 1 Set to 0 when each condition is generated Figure 14 9 U2SMR3 and U2SMR4 Registers Rev 2 00 Jan 31 2007 page 174 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 14 Serial I O 14 1 1 Clock Synchronous serial UO Mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data Table 14 1 lists the specifications of the clock synchronous serial I O mode Table 14 2 lists th
77. A D trigger mode select bit 1 A D trigger mode Timer B1 operation mode 0 Other than A D trigger mode RW RW f 0 TB2 interrupt TB2SEL Trigger select bit 1 Underflow of TB2 interrupt generation frequency setting counter ICTB2 b6 b5 Reserved bit Set to 0 Nothing is assigned When write set to 0 b7 When read its content is 0 Write to this register after setting the PRC1 bit in the PRCR register to 1 write enabled If the INV11 bit is 0 three phase mode 0 or the INVO6 bit is 1 triangular wave modulation mode set this bit to 0 Timer B2 underflow When setting the IVPCR1 bit to 1 three phase output forcible cutoff by SD pin input enabled set the PD8_5 bit to 0 input mode Associated pins are U P80 U P81 V P72 V P73 W P74 W P7s When a high level H signal is applied to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff pins U U V V W and W are exit from the high impedance state If a low level L signal is applied to the SD pin three phase motor control timer output will be disabled INV03 0 At this time when the IVPCR1 bit is 0 pins U U V V W and W become programmable UO ports When the IVPCR1 bit is set to 1 pins U U V V W and W are placed in a high impedance state regardless of which function of those pins is used When this bit is used in delayed trigger mode 0 set the TBOEN and TB1EN bits to 1 A D trigger
78. Against lee eestessseaesireesgerusdeebseieste eege 375 20 tE gh 21g de Cooper ene ete ete cy ten eee eee ene reer ir eee oer ere emer ee Eee eee nnn ere 376 20 14 10 HOW ee 376 20 14 11 Writing in the User ROM Area ee 376 20 14 12 DMA MANS EE 376 20 14 13 Regarding Programming Erasure Times and Execution Time nnnnnnn101000a 376 20 14 14 Definition of Programming Erasure Times ceeceeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeees 377 20 14 15 Flash Memory Version Electrical Characteristics 10 000 E W cycle products U7 U9 377 20 14 16 ee TEE 377 20 14 17 Standard Serial WO dE 377 ADV UN ISS EE 378 20 15 1 Trace of Print Board 85 pin Package 378 20 16 Instr ction for a Device TUS Cassa eine last es ete eher ee ER 379 Appendix 1 Package Dimensions cc ccseeeseeceeceeeeeeeeeeeeceeeeceeeceeeeeeeeeeeetees 380 Appendix 2 Functional Comparison ceceeeceseeeceeeeeeeceeeeceeeeeeeeeeeeeeeeeeeeeeess 382 Appendix 2 1 Difference between M16C 28 Group Normal ver and M16C 28 Group T ver V ver 382 Appendix 2 2 Difference between M16C 28 Group and M16C 29 Group Normal ver 383 PROC IS ES MOON EE 384 A 9 Quick Reference by Address Address Register Symbol Page Address Regis
79. Bit Reserved Bit b2 bi A D Input Group Select 9 0 Select port P10 group 0 1 Do not set 1 0 Select port PO group 1 1 Select port P1 P9 group Set to 0 TRG1 b7 b6 Trigger Select Bit 1 Frequency Select Bit 2 See Table 15 2 Set to 0 in one shot mode Nothing is assigned When write set to 0 When read its content is 0 1 If the ADCON2 register is rewritten during A D conversion the conversion result will be indeterminate Figure 15 7 ADCONO to ADCON2 Registers in One Shot Mode Rev 2 00 Jan 31 2007 page 224 of 385 REJ09B0047 0200 2tENESAS M16C 28 Group M16C 28 M16C 28B 15 A D Converter 15 1 2 Repeat mode In repeat mode analog voltage applied to a selected pin is repeatedly converted to a digital code Table 15 4 shows the repeat mode specifications Figure 15 8 shows the operation example in repeat mode Figure 15 9 shows the ADCONO to ADCON2Z registers in repeat mode Table 15 4 Repeat Mode Specifications Specification Function The CH2 to CHO bits in the ADCONO register and the ADGSEL1 to ADGSELO bits in the ADCON2 register select pins Analog voltage applied to a selected pin is repeatedly converted to a digital code A D Conversion Start e When the TRG bit in the ADCONO register is 0 software trigger Condition Set the ADST bit in the ADCONDO register to 1 A D conversion started e When the TRG bit in the ADCONO register is
80. Clock output from CLK1 RW Clock output from CLKS1 Output from CLK1 only Transfer clock output from multiple RW pins function selected CTS RTS shared pin CTS RTS separated CTSo supplied RW from the P64 pin 2 toro D E Ge UART1 CLK CLKS r CLKMDO Select bit 0 h pos UART1 CLK CLKS hobo CLKMD1 select bit 1 1 oO LH Separate UARTO tot CTS RTS bit sch Oo Nothing is assigned When write set to 0 When read the content is indeterminate NOTES 1 To use more than one transfer clock output pins set the CKDIR bit in the U1MR register to 0 internal clock 2 When the U1MAP bit in PACR register is set to 1 P73 to P70 CTSo is supplied from the Pio pin Figure 14 6 UOCO to U2CO and UCON Registers Rev 2 00 Jan 31 2007 page 171 of 385 RENESAS REJ09B0047 0200 M16C 28 Grou M16C 28 M16C 28B 1 4 Serial I O UARTIi Transmit receive Control Register 1 i 0 1 KS p5 b4 b3 b2 bi b0 Symbol Address After Reset U0C1 U1C1 03A516 03AD16 000000102 Bit Name Function RW Transmit enable bit 0 Transmission disabled RW 1 Transmission enabled Transmit buffer 0 Data present in UiTB register RO empty flag 1 No data present in UiTB register Receive enable bit 0 Reception disabled RW 1 Reception enabled Receive complete flag 0 No data present in UiRB register RO 1 Data present in UIRB register Nothing is assigned UART2 T
81. D4 X Ds X De X D7 RXDi X Do X Di X D2 X D3 X D4 X Ds X De X D7 NOTES 1 This applies to the case where the UFORM bit in the UiCO register is set to 0 LSB first and the UiLCH bit in the UiC1 register is set to 0 no reverse 2 When not transferring the CLKi pin outputs a high signal 3 When not transferring the CLKi pin outputs a low signal i Oto2 Figure 14 11 Polarity of transfer clock 14 1 1 3 LSB First MSB First Select Function Use the UFORM bit in the UiCO register i 0 to 2 to select the transfer format Figure 14 12 shows the transfer format 1 When the UFORM bit in the UiCO register 0 LSB first CU TXDi X DO X D1 X D2 X D3 X D4 X Ds X De X D7 RXDi X Do X Di X D2 X D3 X D4 X D5 X De X D7 2 When the UFORM bit in the UiCO register is set to 1 MSB first CU TXDi X D7 X De X Ds X D4 X D3 X D2 X D1 X Do RXDi X D7 X De X D5 X D4 X D3 X D2 X D1 X Do NOTES 1 This applies to the case where the CKPOL bit in the UiCO register is set to 0 transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock and the UiLCH bit in the UiC1 register O no reverse i Oto2 Figure 14 12 Transfer format Rev 2 00 Jan 31 2007 page 180 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 2
82. DMA request occurs after writing to the DMAE bit the value written to the TCRi register is the value minus 1 If the read value is a value in the middle of transfer the DMAi is not in an initial state Rev 2 00 Jan 31 2007 page 359 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 20 Precautions 20 6 Timer 20 6 1 Timer A 20 6 1 1 Timer A Timer Mode 1 The timer remains idle after reset Set the mode count source counter value etc using the TAIMR i 0 to 4 register and the TAi register before setting the TAIS bit in the TABSR register to 1 count starts Always make sure the TAiMR register is modified while the TAIS bit remains 0 count stops regardless whether after reset or not 2 While counting is in progress the counter value can be read out at any time by reading the TAi register However if the TAi register is read at the same time the counter is reloaded the read value is always FFFF 16 If the TAI register is read after setting a value in it but before the counter starts counting the read value is the one that has been set in the register 3 If a low level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1 three phase output forcible cutoff by input on SD pin enabled the TA10UT TA2ouT and TA40uT pins go to a high impedance state 20 6 1 2 Timer A Event Counter Mode 1 The timer remains idle after reset Set the mode count
83. EE 133 BE DK e 135 13 1 Base EE 146 13 1 1 Base Timer Reset HegtstertG71BIHR en 150 13 2 Interrupt Operation EE 151 13 3 DMA SU DORE GE 151 13 4 Time Measurement Function sive ccccieiecs eege NES NEES eh tee cad 152 13 5 Waveform Generating Function 3 ee Ee 156 13 5 1 Single Phase Waveform Output Mode 157 13 5 2 Phase Delayed Waveform Output Mode 159 13 5 3 Set Reset Waveform Output SR Waveform Output Mode 161 13 6 Me Port PUNCHON Se EE 163 13 6 1 INPC17 Alternate Input Pin Selection en 164 13 6 2 Digital Debounce Function for Pin P17 INT5 INPC1 7 cceecceeeeeeeeeeeereeeeeeeeeeees 164 E Senal VO EE 165 RE et EE EE 165 14 1 1 Clock Synchronous serial I O Mode ssnsensseesnennnnnensnnennnrnnnnrnnnrnnrennnnnnnerrenennnnee 175 14 1 2 Clock Asynchronous Serial I O UART Mode cccecceeseeeeeeeeeeeeeeneeeeeeeeeennees 183 14 1 3 Special Mode 1 I C bus mode UART2 ENEE 191 14 1 4 Special Mode 2 UART2 000 2 ee eeeeceeeeceeeeeeeeeeeee eee eeeeeeeaeeeeeeeeeeaeeeeeeeeeeeeeeeeeeeeeeeeee 201 14 1 5 Special Mode 3 IEBus mode UA 205 14 1 6 Special Mode 4 SIM Mode UARTZ 207 Vas SIS e RE 212 14 2 1 SI Oi Operation Timing EE 215 14 2 2 CLK Eed 215 14 2 3 Functions for Setting an SOUTi Initial Value cee ee ceeeeee eee eeeeeeetteeeeeeeeeeeeees 216 VS Ree 217 15 1 Operating Koleeg e e er rege rgegegeferubuEbrergeE eEEEA Eed EES EES reet 223 E ER nee 223 EE eher 225 15 1 3 Single Sweep Mode EE 227
84. Flag 1 AN1 conversion completed 1 ADSTATO register is valid only when the DTE bit in the ADTRGCON register is set to 1 A D Register i i 0 to 7 Symbol Address After Reset ADO 03C116 to 03C016 Indeterminate AD1 03C316 to 03C216 Indeterminate AD2 03C516 to 03C416 Indeterminate AD3 03C716 to 03C616 Indeterminate AD4 03C916 to 03C816 Indeterminate AD5 03CB16 to 03CA16 Indeterminate AD6 03CD16 to 03CC16 Indeterminate AD7 03CF16 to 03CE16 Indeterminate b0 Function When the BITS bit in the ADCON1 When the BITS bit in the ADCON1 register is 1 10 bit mode register is 0 8 bit mode 1 Eight low order bits of A D conversion result A D conversion result Two high order bits of When read its content is A D conversion result indeterminate Nothing is assigned When write set to 0 When read its content is 0 Figure 15 4 ADSTATO Register and ADO to AD7 Registers Rev 2 00 Jan 31 2007 page 221 of 385 RENESAS REJ09B0047 0200 Timer B2 Special Mode Register 1 b7 b6 b5 b4 b3 b2 bi b0 oE EE Doo Eoo Timer B2 reload timing 0 Timer B2 underflow si oi ob f switch bit 2 1 Timer A output at odd numbered RW poy gk RW RW 0 Three phase output forcible cutoff Three phase output port Gg input high impedan e IVPCR1 S control bit 1 3 4 7 1 Three phase output forcible cutoff by SD pin input high impedance enabled TBOEN Timer BO operation mode 0 Other than
85. G1IR Register Bits in the G1IR register are not automatically set to 0 no interrupt requested even if a requested inter rupt is acknowledged Set each bit to 0 by program after the interrupt requests are verified The IC OC interrupt is generated when any bit in the G1IR register is set to 1 interrupt requested after all the bits are set to 0 If conditions to generate an interrupt are met when the G1IR register holds the value other than 0016 the IC OC interrupt request will not be generated In order to enable an IC OC interrupt request again clear the G1IR register to 0016 Use the following instructions to set each bit in the G1IR register to 0 Subject instructions AND BCL Figure 20 4 shows an example of IC OC interrupt i processing Interrupt Yes Set the G1IRi bit to 0 Process channel i waveform generating interrupt Set the G1IRj bit to 0 Process channel j time measurement interrupt Interrupt completed NOTES 1 Example for the interrupt operation when using the channel i waveform generating interrupt and channel j time measurement interrupt Figure 20 4 IC OC Interrupt i Flow Chart Rev 2 00 Jan 31 2007 page 365 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 20 Precautions 20 7 2 Rewrite the ICOCiIC Register When the interrupt request to the ICOCIiIC register is generated during the instruction process the IR bit may not be set to 1 interrupt reque
86. HOER ELE EP EE LL EEE eh SKS TOOTE 2 INPC1j pin input or lt trigger signal after passing the digital filter G1IRj bit y Delayed by 1 clock write 0 by program if setting to 0 NOTES 1 Bits in the G1IR register 2 Input pulse applied to the INPC1j pin requires 1 5 f8T1 clock cycles or more b When selecting both edges as a timer measurement trigger The CTS1 to CTSO bits 1 12 fBT1 Base timer n 2 X n 1 n n 1X n 2X n 3X n 4XK n 5XK n 6X n 7X n 8X n 9Xn 10KnN 1 1Kn 1 2X n 13 n 1 4 INPC1j pin input or trigger signal after passing the digital filter G1IRj bit Y Kee L X write 0 by program e e if setting to 0 y y y NOTES 1 Bits in the G1IR register 2 No interrupt is generated if the microcomputer receives a trigger signal when the G1IRj bit is set to 1 However the value of the G1TMj register is updated c Trigger signal when using digital filter The DEI to DFO bits in the G1TMCR register 102 or 112 f1 or f2 or fBT1 UI INPC1j pin Gt ID a 4 a ef Maximum 3 5 f1 or f2 or fBT1 1 Trigger signal after passing the digital filter The trigger signal is delayed by the digital filter NOTES 1 fBT1 when the DEI to DFO bits are set to 102 and f1 or f2 when set to 112 Figure 13 20 Time Measurement Function 2 Rev 2 00 Jan 31 2007 page 154 of 385
87. IDBO and DB1 Transfer the values to the three phase output shift register U phase output signal 1 U phase output signal 1 phase INV14 0 L active U phase INVI4 1 phase UH active gt i Dead time U phase NOTE 1 Internal signals See Figure 12 25 The above applies under the following conditions INVCO 01XX110Xz2 X varies depending on each system and INVC1 010XXX002 Examples of PWM output change are e Default value of registers IDBO and IDB1 DUO 0 DUBO 1 DU1 1 DUB1 1 They are changed to DU0 1 DUBO 0 DU1 1 DUB1 1 when the timer B2 interrupt is generated Figure 12 34 Sawtooth Wave Modulation Operation Rev 2 00 Jan 31 2007 page 132 of 385 2tENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer 12 3 1 Position Data Retain Function This function is used to retain the position data synchronously with the three phase waveform output There are three position data input pins for U V and W phases A trigger to retain the position data hereafter this trigger is referred to as retain trigger can be selected by the PDRT bit in the PDRF register This bit selects the retain trigger to be the falling edge of each positive phase or the rising edge of each positive phase 12 3 1 1 Operation of the Position data retain Function Figure 12 35 shows a usage example of the position data retain function U phase when the retain trigger is selected as the falling edge of t
88. Indeterminate WR 2 NOTES 1 The indeterminate state depends on the instruction queue buffer A read cycle occurs when the instruction queue buffer is ready to accept instructions 2 When the stack is in the internal RAM the WR signal indicates the write timing by changing high level to low level Figure 9 5 Time Required for Executing Interrupt Sequence Rev 2 00 Jan 31 2007 page 76 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 9 Interrupts 9 4 1 Interrupt Response Time Figure 9 6 shows the interrupt response time The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed Specifically it consists of the time from when an interrupt request is generated till when the instruction then executing is completed a in Figure 9 6 and the time during which the inter rupt sequence is executed b in Figure 9 6 Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine Interrupt response time a The time from when an interrupt request is generated till when the instruction then executing is completed The length of this time varies with the instruction being executed The DIVX instruction requires the longest time which is equal to 30 cycles without wait s
89. Internal synchronous clock SH 7 select bit 5 0 0 Selecting f1 or f2 0 1 Selecting fs SMi1 10 Selecting f32 1 Do not set SMi2 Souri output disable bit 4 0 Sourti output 1 Gout output disable high impedance DM S I Oi port select bit 0 Input output port 1 Gout output CLKi function 0 Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 Transmit data is output at rising edge of transfer clock and receive data is input at falling edge SMi5 Transfer direction select bit 0 LSB first 1 MSB first RW CLK polarity selct bit SMi6 Synchronous clock select bit 0 External clock 2 RW 1 Internal clock 3 SMi7 Souti initial value set bit Effective when the GM is set to 0 0 L output 1 H output 1 Set the S4C register by the next instruction after setting the PRC2 bit in the PRCR register to 1 write enable 2 Set the SMi3 bit to 1 and the corresponding port direction bit to O input mode 3 Set the GM bit to 1 SouTi output CLKi function 4 When the SMi2 bit is set to 1 the corresponding pin goes to high impedance regardless of the function in use 5 When the SMi1 and SMi0 bit settings are changed set the SiBRG register SI Oi Bit Rate Generator i 3 4 1 2 3 Symbol Address After Reset S3BRG 036316 Indeterminate S4BRG 036716 Indeterminate Setting Range Assuming that set value
90. NMI Interrupt 6 information added e 20 5 5 INT Interrupt 3 information added e 20 7 1 3 Timer A One shot Timer Mode 6 information added e 20 7 1 4 Timer B Pulse Width Modulation Mode 2 information modified e 20 7 2 2 Timer B Event Counter Mode 2 information modified e 20 8 1 Rewrite G1IR Register modified e Figure 20 3 IC OC Interrupt Flow Chart added e 20 8 2 Rewrite the ICOCiIC Register added e 20 8 3 Waveform Generating Function added e 20 9 1 1 Transmission reception 2 information modified 20 9 2 1 Special Mode ZC bus Mode added 20 11 Multi master I2C bus Interface added e 20 12 Programmable I O Ports 2 and 3 information modified e 20 14 1 Functions to Inhibit Rewriting Flash Memory Rewrite modified e 20 14 2 Stop Mode modified e 20 14 4 Low Power Disspation Mode On chip Oscillator Low Power Dissipation Mode modified e 20 14 7 Operating Speed modified e 20 14 13 Regarding Programming Erasure Times and Execution Time modified e 20 14 14 Definition of Programming Erasure Times added e 20 14 15 Flash Memory version Electrical Characteristics 10 000 E W cycle products U7 U9 added e 20 14 16 Boot Mode added e 20 15 Noise added e 20 16 Instruction fo Devise Use added Appendix 2 Functional Comparison New chapter Flash Memory Version e Table 18 1 Flash Memory Version Specifications Topr value is added for data retention specification Jan 06 All Pages 85 pin plastic molded TFLGA package and ma
91. O Noise filter Event counter m Timer mode One shot timer mode e PWM mode Timer A1 interrupt H Event counter mode Timer mode One shot timer mode e PWM mode Timer A2 interrupt e e Event counter mode Timer mode One shot timer mode PWM mode Timer A3 interrupt H gt Event counter mode Timer mode One shot timer mode PWM mode SCH Timer A4 interrupt D o Timer A4 Be Noise filter Event counter mode Timer B2 overflow or underflow Figure 12 1 Timer A Configuration Rev 2 00 Jan 31 2007 page 98 of 385 RENESAS R J09B0047 0200 M16C 28 Group M16C 28 M16C 28B 12 Timer f2 PCLKO bit 0 Clock prescaler O e Main clock fi or f2 e PLL clock SC XCIN On chip oscillator POLEKO bits T clock Set the CPSR bit in the f32 CPSRF register to 1 prescaler reset f1 or f2 f8 f32 fC32 Timer B2 overflow or underflow to Timer A count source Timer mode e Pulse width measuring mode pulse period measuring mode Timer BO interrupt e Event counter mode Timer mode Pulse width measuring mode pulse period measuring mode Timer B1 interrupt e Event counter mode Timer mode Pulse width measuring mode pulse period measuring mode Timer B2 interrupt Timer B2 e Event counter mode Figure 12 2 Ti
92. P2 direction register PD2 289 03E716 Port P3 direction register PD3 289 O3E816 O3E916 O3EA16 03EB16 03EC16 Port P6 register D 290 03ED 6 Port P7 register P7 290 03EE16 Port P6 direction register PD6 289 03EF16 Port P7 direction register PD7 289 03F016 Port P8 register P8 290 03F116 Port P9 register P9 290 03F2 6 Port P8 direction register PDS 289 03F316 Port P9 direction register PD9 289 03F416 Port P10 register P10 290 O3F516 03616 Port P10 direction register PD10 289 03F716 03F816 03F916 03FA16 03FB16 03FCi6 Pull up control register 0 PURO 291 03FDie Pull up control register 1 PUR1 291 03FE16 Pull up control register 2 PUR2 291 03FF16 Port control register PCR 292 NOTE 1 The blank areas are reserved and cannot be accessed by users B 4 CENESAS M16C 28 Group M16C 28 M16C 28B SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 1 Overview 1 1 Features The M16C 28 Group M16C 28 M16C 28B of single chip control MCUs incorporates the M16C 60 series CPU core employing the high performance silicon gate CMOS technology and sophisticated instructions for a high level of efficiency The M16C 28 Group M16C 28 M16C 28B are housed in 64 pin and 80 pin plastic molded LQFP packages and also in 85 pin plastic molded TFLGA Thin Fine Pitch Land Grid Array package This MCU is capable of executing instructions at high speed In addition the CPU core boasts a multiplier and DMAC for high
93. P22 to P27 P30 P60 P61 P64 P65 P74 to P76 P80 P81 inside dotted line included Data bus inside dotted line not included Input to respective peripheral functions NOTES 1 Mr symbolizes a parasitic diode Pull up selection Direction register a O 17 Programmable UO Ports Port P1 control register lt Direction Lester EE ort latch est s Make sure the input voltage on each port will not exceed Vcc Figure 17 1 UO Ports 1 Rev 2 00 Jan 31 2007 page 284 of 385 REJ09B0047 0200 2RENESAS M16C 28 Group M16C 28 M16C 28B Pull up selection Direction P20 P21 P70 P71 register ee P72 P73 bi lt q r ro 17 Programmable I O Ports Output Data bus Port latch e CMOS and St Switching between 4 Nch Input to respective peripheral functions Pull up selection P82 to P84 Direction register g Data bus Port latch Input to respective peripheral functions Pull up selection Direction register P31 P62 P66 P77 P90 to P92 lt Data bus Port latch Input to respective peripheral functions SE w lle symbolizes a parasitic diode Make sure the input voltage on each port will not ex
94. P30 to P37 P60 to P67 P7o to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 Average Output High H Current POo to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 Peak Output Low L Current POo to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P7o to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 Average Output Low L Current POo to P07 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P7o to P77 P80 to P87 P90 to P93 P95 to P97 P100 to P107 5 0 f XIN Main Clock Input Oscillation Frequency Vec 3 0 to 5 5 V 20 Vec 2 7 to 3 0 V 33 X Voc 80 f Xcn Sub Clock Oscillation Frequency 50 f1 ROC On chip Oscillator Frequency 1 2 f2 ROC On chip Oscillator Frequency 2 3 ROC On chip Oscillator Frequency 3 26 PLL PLL Clock Oscillation Frequency Voc 4 2 to 5 5 V M16C 28B 24 Voc 3 0 to 4 2 V M16C 28B 3 33 X Voc 10 Voc 3 0 to 5 5 V M16C 28 20 Vcc 2 7 to 3 0 V 33 X Vcc 80 CPU Operation Clock Frequency M16C 28 20 M16C 28B 24 NOTES Wait Time to Stabilize PLL Frequency Synthesizer Vec 5 0 V 20 Vec 3 0 V 50 1 Referenced to Vcc 2 7 to 5 5 V at Topr 20 to 85 C 40 to 85 C unless otherwise specified 2 The mean output current is the mean v
95. PRC2 bit in the PRCR register to 1 write enable Bit Symbol Figure 14 7 U0C1 to U2C1 Register and PACR Register Rev 2 00 Jan 31 2007 REJ09B0047 0200 page 172 of 385 7tENESAS M16C 28 Grou M16C 28 M16C 28B 14 Serial I O b7 b6 b5 b4 b3 b2 bi b0 SIS ees ae UART2 Special Mode Register Address 037716 After Reset X00000002 Symbol U2SMR Bit ICH 12C bus mode select bit Other than 0 Qerthan 126 bue mode bus mode 0 Qerthan 126 bue mode bus mode a Po Arbitration lost detecting Ve Update per bit hor flag control bit Update per byte e STOP condition detected START condition detected busy Bus busy flag b7 Reserved bit Set to 0 Auto clear function 0 No auto clear function select bit of transmit 1 Auto clear at occurrence of bus collision enable bit sss Transmit start condition 9 Not synchronized to R xDi select bit 1 Synchronized to R xDi 2 Nothing is assigned When write set O When read its content is indeterminate NOTES b7 b6 b5 b4 b3 b2 bi b0 female te ce te Bit e F IICM2 12C bus mode select bit 2 Refer to Table 14 13 RW CSC Clock synchronous bit 0 Disabled RW R 1 Enabled SWC SCL2 wait output bit 0 Disabled RW 1 Enabled ALS SDA2 output stop bit S Disabled RW Enabled STAC UART initialization bit y Disabled Enabled SWC2 SCL2 wait output bit 2 0 Transf
96. PURO raw 1 The pin for which this bit is 1 pulled up and the direction bit is O input mode is pulled up 0 Not pulled a 1 Pulled up 1 Pull up Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Address 03FD16 After Reset 0016 Symbol PUR1 Bit Symbol Bit Name Function Nothing is assigned When write set to 0 b3 b0 PU14 PU15 When read the content is 0 P60 to P63 pull up P64 to P67 pull up 0 Not pulled high 1 Pulled high PU16 P70 to P73 pull up P74 to P77 pull up 1 The pin for which this bit is 1 pulled up and the direction bit is O input mode is pulled up Pull up Control Register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset PUR2 03FE16 0016 P104 to P107 pull up Nothing is assigned When write set to 0 b7 b6 When read the content is 0 0 Not pulled up 1 Pulled up 1 1 The pin for which this bit is 1 pulled up and the direction bit is O input mode is pulled up Figure 17 8 PURO to PUR2 Registers Rev 2 00 Jan 31 2007 page 291 of 385 RENESAS REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 17 Programmable I O Ports Port Control Register TRC Symbp Address After Reset XXX KX Per 03FF16 0016 Bitsymbo PCRO Port P1 control bit Operation performed when the P1 register is read 0 When the port is set for input the input levels of P10 to P17 pins are r
97. REJ09B0047 0200 M16C 28 Group M16C 28 M16C 28B 19 Electrical Characteristics Table 19 6 Voltage Detection Circuit Electrical Characteristics 1 3 Standard Parameter Measurement Condition Min Typ Max Low Voltage Detection Voltage Reset Level Detection Voltage Low Voltage Reset Hold Voltage Low Voltage Reset Release Voltage Vcc 0 8 to 5 5V NOTES 1 Vdet4 gt Vdet3 2 Vdet3s is the minmum voltage to maintain hardware reset 2 3 The voltage detection circuit is designed to use when Vocis set to 5V 4 If the supply power voltage is greater than the reset level detection voltage when the reset level detection voltage is less than 2 7V the operation at f BCLK lt 10MHz is guranteed However A D conversion serial I O flash memory program and erase are excluded Table 19 7 Power Supply Circuit Timing Characteristics Standard Min Typ Max Parameter Measurement Condition Wait Time to Stabilize Internal Supply Voltage when Power on Wait Time to Stabilize Internal On chip Oscillator when Power on Voeo 2 7 to 5 5V td R S STOP Release Time Low Power Dissipation Mode Wait Mode Release td P R td ROC td W S Time td S R Hardware Reset 2 Release Wait Time Voc Vdet3r to 5 5V td E A Voltage Detection Circuit Operation Start Time Vcc 2 7 to 5 5V NOTES 1 When Voc 5V Rev 2 00 Jan 31 2007 page 332 o
98. RTS2 Output pins for data reception control CLKO to CLK3 Inputs and outputs the transfer clock RxD0 to RxD2 Inputs serial data TxDO to TxD2 Outputs serial data CLKS1 Output pin for transfer clock 12C bus Mode SDA2 SCL2 Inputs and outputs serial data Inputs and outputs the transfer clock Multi master IC bus SDAmMM SCLMM Inputs and outputs serial data Inputs and outputs the transfer clock Reference Voltage Input VREF Applies reference voltage to the A D converter A D Converter Input ANo to AN7 AN0o to ANO3 AN24 Analog input pins for the A D converter O ADTRG Output Rev 2 00 Jan 31 2007 REJ09B0047 0200 Input pin for an external A D trigger I O Input and output page 19 of 385 2tENESAS M16C 28 Group M16C 28 M16C 28B 1 Overview Table 1 11 Pin Description 64 pin 80 pin and 85 pin packages Continued I O Type Classification Symbol INPC10 to INPC17 Function Input pins for the time measur