TEXAS INSTRUMENTS -ADS807 handbook
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1. Input Amplitude dBFS SINAD vs SAMPLING FREQUENCY Differential Input 35 40 45 50 55 60 Sampling Frequency MHz TYPICAL CHARACTERISTICS Cont At T full specified temperature range differential input range 2V to 3V sampling rate 5OMHz and internal reference unless otherwise noted DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR m T a a a 7 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Output Codes Output Codes DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR 2 0 fry 10MHz 1 5 1 0 a 05 j 0 Ww a A 0 5 ery 1 0 1 5 2 0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Output Codes Output Codes DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR Single Ended Input Sampling Frequency 40MHz Sampling Frequency 40MHz 1 000 2 0 fn 10MHz 1 5 0 500 1 0 T 0 5 m 4 A p J a 0 5 0 500 1 0 1 5 1 000 2 0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Output Codes Output Codes AP Texas ADS807 8 INSTRUMENTS SBAS072A www ti com APPLICATION INFORMATION THEORY OF OPERATION The ADS807 is a high speed CMOS A D converter which employs a pipelined converter architecture consisting of 12 internal stages Each stage feeds its data into the digital error2. FIGURE 3 AC Coupled Differential Interface for Single Supply Operation AC Coupled Single Ended to Differential Interface for Single Supply Operation The previously discussed interface circuit can be modified if the system only allows for a single supply operation e g Vs 5V Single supply operation requires the driver ampli fier to be biased as well in order to process a bipolar input signal Typically single supply amplifiers do not achieve distortion performance as well as dual supply op amps The driver amplifiers output swing must exceed the full scale input range of the converter In addition dual op amps such as the current feedback OPA2681 should be considered since they provide the closest open loop gain and phase matching between the two channels Shown in Figure 3 is a single supply interface circuit for an AC coupled input signal With the ADS807 set to the 2Vp p input range the top and bottom references REFT REFB provide an output voltage of 3 0V and 2 0V respectively The CM output of the ADS807 is used to bias the inputs of the driving amplifiers Using the OPA2681 on a single 5V supply its ideal com mon mode point is 2 5V which coincides with the recom mended common mode input level for the ADS807 thus obviating the need for coupling capacitors between the amplifiers and the converter The addition of a small series resistor Rg between the output of the op amps and the input of the ADS807 will be
3. 1dB input f 10MHz 1aB input f 20MHz dB input f 40MHz undersampling f 1MHz to 10MHz fs 40MHz f 1MHz to 10MHz fs 40MHz f 1MHz 1dB input f 10MHz 1aB input Signal to Noise Distortion SINAD f 1MHz 1dBFS input f 10MHz 1dBFS input f 20MHz 1dBFS input f 1MHz to 10MHZz fg 40MHz f 1MHz to 10MHZz fg 40MHz f 1MHz 1dBFS input f 10MHz dBFS Input Output Noise Aperture Delay Time Aperture Jitter Over Voltage Recovery Time fs 40MHz fg 50MHz T 25 C fs 40MHz Full Temp 2Vp p Single Ended Input 2Vp p Single Ended Input 3Vp p 3Vp p 2Vp p Single Ended Input 3Vp p 3Vp p Input Grounded 0 5 0 5 Tested Tested 2 0 83 82 76 76 69 71 68 68 66 67 67 69 69 67 67 67 67 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB LSBs rms ns ps rms DIGITAL INPUTS Logic Family Convert Command High Level Input Current Vin 5V Low Level Input Current Vin OV High Level Input Voltage Low Level Input Voltage Input Capacitance Start Conversion CMOS Rising Edge of Convert Clock 50 10 1 0 i bag TEXAS ADS807 INSTRUMENTS 3 SBAS072A www ti com ELECTRICAL CHARACTERISTICS Cont At T full specified temperature range Vs 5V differential input range 2V to 3V for each input sampling rate 50MHz unless otherwise noted ADS807E PAR
4. any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier
5. beneficial in almost all interface configurations It will decouple the op amp s output from the capacitive load and avoid gain peaking which can result in increased noise For best spurious and distortion performance the resistor value should be kept below 100Q Furthermore the series resistor in combination with the shunt capacitor establishes a passive low pass filter limiting the bandwidth for the wideband noise thus improving the SNR The spurious free dynamic range of this single supply front end is limited by the 2nd harmonic distortion An improvement of several dB may be realized by adding a pull down resistor Rp at the output of each amplifier This pulls a DC bias current out of the output stage of the amplifier It is set to approximately 5mA in Figure 3 but will vary depending on the amplifier used i bee TEXAS ADS807 INSTRUMENTS 11 SBAS072A www ti com Single Ended AC Coupled Dual Supply Interface The circuit provided in Figure 4 shows typical connections for using the ADS807 in a single ended input configuration The bias requirements for AC coupling are provided by a single resistor to the CM output lead The single ended mode of operation should be considered for ease of interface com plexity and applications where the dynamic performance can be compromised The series resistor Rg along with the shunt capacitance provide the means to adjust the bandwidth and optimize the performance towards good signal to nois
6. correction logic ensuring excellent differential linearity and no missing codes at the 12 bit level The output data becomes valid after the rising clock edge see Timing Dia gram The pipeline architecture results in a data latency of 6 clock cycles The analog input of the ADS807 consists of a differential track and hold circuit The differential topology along with tightly matched poly poly capacitors produce a high level of AC performance at high sampling rates and in undersampling applications Both inputs IN IN require external biasing using a com mon mode voltage that is typically at the mid supply level V lt 2 DRIVING THE ANALOG INPUTS The analog inputs of the ADS807 are a very high impedance They should be driven through an R C network designed to pass the highest frequency of interest This prevents high frequency noise in the input from affecting SFDR and SNR The ADS807 can be used in a wide variety of applications and deciding on the best performing analog interface circuit depends on the type of application The circuit definition should include considerations of input frequency spectrum and amplitude single ended or differential drive and avail able power supplies For example communication frequency domain applications process frequency bands not including DC In imaging time domain applications the input DC component must be maintained into the A D converter Features of the ADS807 including full scal
7. or External 3Vp p Single Ended Internal 3Vp p Times 1 Input or External TABLE Reference Voltages for Input Signal Ranges If it is desired to switch between internal and external refer ences disconnect switches must be added between the exter nal references and the ADS807 DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Clock jitter is critical to the SNR performance of high speed high resolution A D converters Clock jitter leads to aperture jitter ta which adds noise to the signal being converted The ADS807 samples the input signal on the rising edge of the CLK input Therefore this edge should have the lowest possible jitter The jitter noise contribution to total SNR is given by the following equation If this value is near your system require ments input clock jitter must be reduced Jitter SNR 20log soe rms signaltorms noise IN A where f is input signal frequency ta is rms clock jitter Particularly in undersampling applications special consider ation should be given to clock jitter The clock input should be treated as an analog input in order to achieve the highest level of performance Any overshoot or undershoot of the clock signal may cause degradation of the performance When digitizing at high sampling rates the clock should have 50 duty cycle t t along with fast rise and fall times of 2ns or less Over Range Indicator OTR If the analog input voltage exceeds the set full s
8. power and ground planes are particularly important for high frequency designs Multilayer PC boards are recom mended for best performance since they offer distinct advan tages such as minimizing ground impedance separation of signal layers by ground layers etc The ADS807 should be treated as an analog component Whenever possible the supply pins should be powered by the analog supply This will ensure the most consistent results since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable ADS807 SBAS072A performance All ground connections on the ADS807 are internally joined together eliminating the need for split ground planes The ground pins 1 20 26 should directly connect to an analog ground plane which covers the PC board area under the converter While designing the layout it is impor tant to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path Because of the its high sampling rate the ADS807 generates high frequency current transients and noise clock feedthrough that are fed back into the supply and reference lines This requires that all supply and reference pins are sufficiently bypassed Figure 8 shows the recommended decoupling scheme for the ADS807 In most cases 0 1uF ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range The
9. soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided Tl bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be availabl
10. the SNR performance but depending on the signal source large resistor values may be detrimental to achieving good harmonic distortion In any case optimizing the R C values for the specific application is encouraged Transformer Coupled Single Ended to Differential Configuration If the application requires a signal conversion from a single ended source to drive the ADS807 differentially an RF transformer might be a good solution The selected trans former must have a center tap in order to apply the common mode DC voltage necessary to bias the converter inputs AC grounding the center tap will generate the differential signal swing across the secondary winding Consider a step up transformer to take advantage of a signal amplification with out the introduction of another noise source Furthermore the reduced signal swing from the source may lead to improved distortion performance The differential input configuration provides a noticeable advantage of achieving good SFDR over a wide range of input frequencies In this mode both inputs of the ADS807 see matched impedances Figure 1 shows the schematic for the suggested transformer coupled interface circuit The component values of the R C low pass may be optimized depending on the desired roll off frequency The resistor across the secondary side Ry should be calculated using the equation R n Rg to match the source impedance Rg for good power transfer and VSWR The circ
11. ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2006 Texas Instruments Incorporated
12. 1dBc D 06 S ne be o o ne ne 5 2 E a ne TP dlakava aih Bale A 2 tll 0 5 10 15 20 25 0 5 10 15 20 25 Frequency MHz Frequency MHz SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE Sampling Frequency 27MHz Single Ended 2Vp p fin 10MHz fin 10MHz SNR 68dBFS SNR 68dBFS SFDR 81dBFS SFDR 62dBFS D n WL Ww m m B 1A o o ne ne E D D ivi wo 0 4 5 9 0 13 5 0 4 5 9 0 13 5 Frequency MHz Frequency MHz AP Texas ADS807 6 INSTRUMENTS www ti com SBAS072A TYPICAL CHARACTERISTICS Cont At T full specified temperature range differential input range 2V to 3V sampling rate 50MHz and internal reference unless otherwise noted SPECTRAL PERFORMANCE Sampling Frequency 53MHz fin 21MHz SNR 68dBFS SFDR 72dBFS D n LL Le m m B Ach o o ne ne E T S F 0 5 3 10 6 15 9 21 2 26 5 Frequency MHz OUTPUT NOISE HISTOGRAM DC INPUT 800k 3V Full Scale 600k 5 fan me o o E 06 2 400k a oa a LL o 200k 0 N 2 N 1 N N 1 N 2 Code DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY Differential Input ao D T es B 2 o Z O a Le on Sampling Frequency MHz BT 48 Texas ADS807 INSTRUMENTS SBAS072A www ti com UNDERSAMPLING Sampling Frequency 27MHz fin 5OMHz SNR 65dBFS SFDR 73dBFS 0 4 5 9 0 13 5 Frequency MHz SWEPT POWER SFDR
13. 7 NOTE 1 Optional FIGURE 6 Recommended Bypassing for the Reference Pins 5V USING EXTERNAL REFERENCES For even more design flexibility the internal reference can be disabled and an external reference voltage used The utilization of an external reference may be considered for applications requiring higher accuracy improved tempera ture performance or a wide adjustment range of the converter s full scale range In multichannel applications the use of a common external reference has the benefit of obtaining better matching and drift of the full scale range between converters Figure 7 gives an example of an exter nal reference circuit using a single supply low power dual op amp OPA2234 The external references can vary as long as the value of the external top reference REFT EXT stays within the range of Vs 1 70V and REFB 0 4V and the external bottom reference REFB EXT stays within 1 70V and REFT 0 4V Note that the function of the range selector pin FSg_ is disabled while the converter operates in external reference mode Setting the ADS807 for external reference mode re quires the INT EXT pin pin 18 to be HIGH The logic level applied to the INT EXT pin of the ADS807 determines if the converter operates with either the built in reference or external reference voltages Because this function pin has an internal 50kQ pull up resistor the default configu ration is external reference mod
14. AMETER CONDITIONS TYP DIGITAL OUTPUTS Logic Family CMOS Logic Coding Straight Offset Bin Low Output Voltage lo 504A VDRV 5V Low Output Voltage Io 1 6mA VDRV 5V High Output Voltage lop 504A VDRV 5V High Output Voltage lop 0 5mA VDRV 5V Low Output Voltage Io 504A VDRV 3V High Output Voltage lop 504A 3 State Enable Time 3 State Disable Time Output Capacitance Zero Error Referred to FS Zero Error Drift Referred to FS Gain Error Gain Error Drift Gain Error Gain Error Drift Power Supply Rejection of Gain REFT Tolerance 2V Full Scale Deviation From Ideal 3 0V 3V Full Scale Deviation From Ideal 3 25V REFB Tolerance 2V Full Scale Deviation From Ideal 2 0V 3V Full Scale Deviation From Ideal 1 75V 100 External REFT Voltage Range REFB 0 4 Vs 1 70 External REFB Voltage Range 1 70 REFT 0 4 Reference Input Resistance POWER SUPPLY REQUIREMENTS Supply Voltage Vs Operating Supply Current lg Operating Power Dissipation VDRV 5V External Reference VDRV 3V External Reference VDRV 5V Internal Reference VDRV 3V Internal Reference Thermal Resistance 0 SSOP 28 NOTES 1 Spurious Free Dynamic Range refers to the magnitude of the largest harmonic 2 dBFS means dB relative to Full Scale 3 2 tone intermodulation distortion is referred to the largest fundamental tone This number will be 6dB higher if it is referred to the magnitude of the 2 ton
15. Burr Brown Products from Texas Instruments ADS807 La Soz SBAS072A JANUARY 1999 REVISED JULY 2002 12 Bit 53MHz Sampling ANALOG TO DIGITAL CONVERTER FEATURES SPURIOUS FREE DYNAMIC RANGE 82dB at 10MHz f n HIGH SNR 67 5dB 2Vp p 69dB 3Vp p LOW POWER 335mW INTERNAL OR EXTERNAL REFERENCE LOW DNL 0 5LSB FLEXIBLE INPUT RANGE 2Vp p to 3Vp p SSOP 28 PACKAGE DESCRIPTION The ADS807 is a high speed high dynamic range 12 bit pipelined Analog to Digital A D converter This con verter includes a high bandwidth track and hold that gives excellent spurious performance up to and beyond the Nyquist rate The differential nature of this track and hold and A D converter circuitry minimizes even order harmonics and gives excellent common mode noise immunity The track and hold can also be operated single ended The ADS807 provides for setting the full scale range of the converter without any external reference circuitry The inter nal reference can be disabled allowing low drive internal references to be used for improved tracking in multichannel systems APPLICATIONS COMMUNICATIONS IF PROCESSING COMMUNICATIONS BASESTATIONS TEST EQUIPMENT MEDICAL IMAGING VIDEO DIGITIZING CCD DIGITIZING The ADS807 provides an over range indicator flag to indicate an input signal that exceeds the full scale input range of the converter This flag can be used to reduce the gain of front
16. Qty ADS807E ACTIVE SSOP DB 28 48 Green RoHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br ADS807E 1K ACTIVE SSOP DB 28 1000 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br ADS807E 1KG4 ACTIVE SSOP DB 28 1000 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br ADS807EG4 ACTIVE SSOP DB 28 48 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free RoHS Exempt or Green ROHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be
17. Ratings installation procedures can cause damage may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods may affect device reliability ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications PACKAGE ORDERING INFORMATION SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA QUANTITY ADS807E SSOP 28 40 C to 85 C ADS807E ADS807E Tube 50 e j ADS807E 1K Tape and Reel 1000 NOTE 1 For the most current specifications and package information refer to our web site at www ti com PIN CONFIGURATION PIN DESCRIPTIONS PiN DESIGNATOR DESCRIPTION SSS d Ground A i Data Bit 1 MSB Bit 2 Data Bit 2 Bit 3 Data Bit 3 Bit 4 Data Bit 4 Bit 5 Data Bit 5 Bit 6 Data Bit 6 Bit 7 Data Bit 7 Bit 8 Data Bit 8 Bit 9 Data Bit 9 Bit 10 Data Bit 10 Bit 11 Data Bit 11 Bit 12 Data Bit 12 LSB CLK Convert Clock Top View GND Bit 1 MSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 ADS807E Vs 5V Supply FSseL HI 3V LO 2V OTR Out of Range Indicator INT EXT Reference Select HIGH or Floating Exter _ nal LOW Internal 50kQ pull up OE Output Enable GND Ground Bit 7 Bit 8 Bit 9 Bit 10 REFB Bottom Reference Bypas
18. S IN 2V IN 3V TABLE III Coding Table for Single Ended Input Configuration with IN Tied to the Common Mode Voltage loading will cause larger dynamic currents as the digital outputs are changing Those high current surges can feed back to the analog portion of the ADS807 and affect the performance If necessary external buffers or latches close to the converter s output pins may be used to minimize the capacitive loading They also provide the added benefit of isolating the ADS807 from high frequency digital noise on the bus coupling back into the converter Digital Output Driver Supply VDRV The ADS807 features a dedicated supply pin for the output logic drivers VDRV which is not internally connected to the other supply pins Setting the voltage at VDRV to 5V or 3V the ADS807 produces corresponding logic levels and can directly interface to the selected logic family The output stages are designed to supply sufficient current to drive a variety of logic families However it is recommended to use the ADS807 with 3V logic supply This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the AC performance of the converter In some applica tions it might be advantageous to decouple the VDRV pin with additional capacitors or a pi filter GROUNDING AND DECOUPLING Proper grounding bypassing short trace lengths and the use of
19. XAS 12 INSTRUMENTS ADS807 www ti com SBAS072A REFERENCE OPERATION The internal reference consists of a bandgap voltage refer ence the drivers for the top and bottom reference and the resistive reference ladder The bandgap reference circuit includes logic functions that allow setting the analog input swing of the ADS807 to a differential full scale range of either 2Vp p or 3Vp p by simply tying the FSse pin to a LOW or HIGH potential respectively While operating the ADS807 in the external reference mode the buffer amplifiers for the REFT and REFB are disabled The ADS807 has an internal 50kQ pull down resistor at the range select pin RSEL Therefore this pin can be either hardwired to ground or left unconnected which will default the converter to a 2Vp p full scale input range FSR While set for the 2Vp p range the top and bottom reference voltages will be REFT 3 0V and REFB 2 0V Switching to the 3Vp p range changes those voltages to REFT 3 25V and REFB 1 75V The reference buffers can be utilized to supply up to 1mA sink and source to external circuitry To ensure proper operation with any reference configuration it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum as shown in Figure 6 Good performance requires using 0 1uF low inductance capaci tors All bypassing capacitors should be located as close to their respective pins as possible ADS80
20. cale range an over range condition exists The OTR pin of the ADS807 can be used to monitor any such out of range condition This OTR output is updated along with the data output corre sponding to the particular sampled analog input voltage Therefore the OTR data is subject to the same pipeline delay as the digital data The OTR output is LOW when the input voltage is within the defined input range It will go to HIGH if the applied signal exceeds the full scale range Data Outputs The output data format of the ADS807 is in positive Straight Offset Binary code as shown in Table II and Table III This format can easily be converted into the Binary Two s Comple ment code by inverting the MSB It is recommended that the capacitive loading on the data lines be as low as possible lt 15pF Higher capacitive kis TEXAS 14 INSTRUMENTS www ti com SINGLE ENDED INPUT IN CM Pin 23 STRAIGHT OFFSET BINARY SOB 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0000 FS 1LSB IN CMV FSR 2 1 2 FS Bipolar Zero IN Vom 1 2 FS FS IN CMV FSR 2 TABLE II Coding Table for Single Ended Input Configuration with IN Tied to the Common Mode Voltage STRAIGHT OFFSET BINARY DIFFERENTIAL INPUT SOB 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0000 FS 1LSB IN 3V IN 2V 1 2 FS Bipolar Zero IN IN Vow 1 2 FS F
21. e Grounding this pin will activate the internal reference option The input track and hold amplifier is differential A positive 1Vp p on the IN and its compliment a negative 1Vp p on the IN see Figure 3 results in 2Vp p on the output of the track and hold Likewise 2Vp p on the IN and OVp p on the IN see Figure 4 results in 2Vp p on the output of the track and hold Therefore the reference volt ages REFT and REFB are the same for both differential and single ended inputs see Table The external references may be changed for different tasks The ADS807 will follow the external references with a latency of 8 to 10 clock cycles If it is desired to use INT EXT and FSseL to change the configuration of a circuit for different tasks a large amount of time must be allowed This time could be hundreds of microseconds Refer to the diagram on the front page Note that there is no disconnect for external references 4 7kQ REF1004 2 5V A O Top Reference O Bottom Reference FIGURE 7 Example for an External Reference Driver Using the Dual Single Supply Op Amp OPA2234 i Wy TEXAS ADS807 INSTRUMENTS 13 SBAS072A www ti com INPUT REFERENCE IN Pin 25 IN Pin 24 REFT REFB 2Vp p Differential Internal 2V to 3V 3V to 2V 1Vp p Times 2 Inputs or External 2Vp p Single Ended Internal 2Vp p Times 1 Input or External 1 5V to 3 5V 3Vp p Differential Internal 1 5Vp p Times 2 Inputs
22. e for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that
23. e fundamental envelope 4 Effective number of bits ENOB is defined by as SINAD 1 76 6 02 5 A 50kQ pull down resistor is inserted internally on OE pin 6 Includes internal reference 7 Excludes internal reference i Wy TEXAS 4 INSTRUMENTS ADS807 www ti com SBAS072A TIMING DIAGRAM Analog In Data Out N 6 N 5 Data Invalid Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time C OpF New Data Delay Time C 15pF max tconv 2 tconv 2 2 NOTE 1 t and t times are valid for VDRV voltages of 2 7V to 5V ADS807 SBAS072A Ais TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS At T full specified temperature range differential input range 2V to 3V sampling rate 50MHz and internal reference unless otherwise noted SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 fin 1MHz 40 fy 10MHz SNR 68dBFS SNR 68dBFS SFDR 83dBFS 20 SFDR 82dBFS D n 30 LL WL g S 40 2 Ss 50 2 E a 5 60 oO wo 70 80 90 i 100 asai i i i 0 5 10 15 20 25 0 5 10 15 20 25 Frequency MHz Frequency MHz SPECTRAL PERFORMANCE 2 TONE INTERMODULATION DISTORTION fin 21MHz f4 12MHz SNR 68dBFS f 13MHz SFDR 77dBFS IMD 3 7
24. e ratio In addition the amplifier configuration can be easily modified for an anti aliasing filter based on a 2nd order Sallen Key or Multiple Feedback topology The interface example shown in Figure 4 operates with the full scale range of the ADS807 set to 2Vp p leaving suffi cient headroom for the output of the OPA642 to drive the converter and maintain low signal distortion DC Coupled Differential Driver with Level Shift Several applications will require that the bandwidth of the signal path include DC in which case the signal has to be DC coupled to the A D converter An op amp based interface circuit can be configured to scale and level shift the input signal to be compatible with the selected input range of the A D converter The circuit shown in Figure 5 employs a dual op amp OPA2681 to drive the input of the ADS807 differ entially The single supply general purpose op amp OPA234 is added to buffer the common mode voltage of 2 5V available at the CM pin and apply it to the input of the driver amplifier This sets the correct DC voltage to bias the inputs of the ADS807 It should be noted that any DC voltage differences between the IN and IN inputs of the ADS807 will result in an offset error Using the OPA2681 this circuit can be operated either with a single or a dual 5V supply ADS807E ADS807E FIGURE 5 DC Coupled Input Driver with Level Shifting i Wy TE
25. e select FSg_ external reference and CM output provide flexibility to ac commodate a wide range of applications The ADS807 should be configured to meet application objectives while observing the headroom requirements of the driving amplifi ers to yield the best overall performance The ADS807 input structure allows it to be driven either single ended or differentially Differential operation of the ADS807 requires an in phase input signal and a 180 out of phase part simultaneously applied to the inputs IN IN The differential operation offers a number of advantages which in most applications will be instrumental in achieving the best dynamic performance of the ADS807 e the signal swing is half of that required for the single ended operation and therefore is less demanding to achieve while maintaining good linearity performance from the signal source e the reduced signal swing allows for more headroom in the interface circuitry and therefore a wider selection of the best suitable driver op amp even order harmonics are minimized e improves the noise immunity based on the converter s common mode input rejection Using the single ended mode the signal is applied to one of the inputs while the other input is biased with a DC voltage to the required common mode level Both inputs are equal in terms of their impedance and performance except that applying the signal to the complementary input IN instead of the IN i
26. end gain control circuitry There is also an output enable pin to allow for multiplexing and testability on a PC board The ADS807 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications CLK ADS807 Timing Circuitry 3V 2 5V Pipelined 3 Stat 2V A D State 3V iN Converter Outputs 2 5V 2V Soscinasissi 5 INT EXT FSg OE l Reference H Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet A PRODUCTION DATA information is current as of publication date a Products conform to specifications per the terms of Texas Instruments 1 Standard warranty Production processing does not necessarily include TEXAS testing of all parameters INSTRUMENTS www ti com Copyright 1999 Texas Instruments Incorporated ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC Analog Input 0 3V to Vg 0 3V DISCHARGE SENSITIVITY Logic Input 0 3V to Vs 0 3V one a Case Temperature This integrated circuit can be damaged by ESD Texas Instru Junction Temperature ments recommends that all integrated circuits be handled with Storage Temperature appropriate precautions Failure to observe proper handling and NOTE 1 Stresses above those listed under Absolute Maximum
27. hould be such that the amplifier s performance will not degrade the A D converter s performance The ADS807 operates on a single power supply which requires a level shift to a ground based bipolar input signals to comply with its input voltage range require ments The input of the ADS807 is of a capacitive nature and the driving source needs to provide the current to charge or discharge the input sampling capacitor while the track and hold is in track mode This effectively results in a dynamic input impedance which depends on the sampling frequency It most applications it is recommended to add a series resistor typically 20Q to 50Q between the drive source and the converter inputs This will isolate the capacitive input from the source which can be crucial to avoid gain peaking when using wideband operational amplifiers Secondly it will create a 1st order low pass filter in conjunction with the specified input capacitance of the ADS807 Its cutoff fre quency can be adjusted even further by adding an external shunt capacitor from each signal input to ground The opti mum values of this R C network depend on a variety of factors which include the ADS807 sampling rate the se lected op amp the interface configuration and the particular application time domain versus frequency domain Gener ally increasing the size of the series resistor and or capacitor i bag TEXAS ADS807 INSTRUMENTS 9 SBAS072A www ti com will improve
28. ir effective ness largely depends on the proximity to the individual supply pin Therefore they should be located as close to the supply pins as possible If system supplies are not a low enough impedance adding a small tantalum capacitor will yield the best results ADS807 3V 5V FIGURE 8 Recommended Bypassing for the Supply Pins i Ais TEXAS ADS807 INSTRUMENTS 15 SBAS072A www ti com PACKAGE DRAWING MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB R PDSO G PLASTIC SMALL OUTLINE 28 PINS SHOWN gt i fi Gage Plane Y 0 AUUUOUE UT J y seating Pan 2 00 MAX 0 05 MIN 4 gt 0 10 PINS 4040065 E 12 01 NOTES A All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 150 gow i bag TEXAS 16 INSTRUMENTS ADS807 www ti com SBAS072A K Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 1 May 2006 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing
29. n performance for input frequencies of up to 15MHz The two amplifiers A1 A2 are configured as an inverting and noninverting gain stage to convert the input signal from single ended to differential The nominal gain for this stage is set to 2V V The outputs of the OPA642s are AC coupled to the converter s differential inputs This will keep the distortion performance at its best since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained Four resistors located between the top REFT and bottom REFB reference shift the input signal to a common mode voltage of approximately 2 5V The interface circuit of Figure 2 can be modified to extend the bandwidth to approximately 25MHz by replacing the OPA642 with its decompensated version the OPA643 The OPA643 provides the necessary slew rate for a low distortion front end to the ADS807 With a minimum gain stability of 3 the gain resistors have to be modified as well as optimizing the series resistor and shunt capacitance at each of the converter inputs ADS807E CM 2 5V FIGURE 1 Converting a Single Ended Input Signal into a Differential Signal Using a RF Transformer i bag TEXAS 10 INSTRUMENTS ADS807 www ti com SBAS072A 4020 16 50 OPA642 WMA i 4020 4020 ADS807E A2 OPA642 ADS807E
30. nput will invert the input signal relative to the output code For example in case the input driver operates in inverting mode using IN as the signal input will restore the phase of the signal to its original orientation Time domain applications may benefit from a single ended interface con figuration and its reduced circuit complexity While maintain ing good SNR driving the ADS807 with a single ended signal will result in a reduction of the distortion performance Employing dual supply amplifiers and AC coupling will usu ally yield the best results while DC coupling and or single supply amplifiers impose additional design constraints due to their headroom requirements especially when selecting the 3Vp p input range However single supply amplifiers have the advantage of inherently limiting their output swing to within the supply rails Alternatively a voltage limiting ampli fier like the OPA688 may be considered to set fixed signal limits and avoid any severe over range condition for the A D converter The full scale input range of the ADS807 is defined by the reference voltages For example setting the range select pin to FSse_ LOW and using the internal references REFT 3 0V and REFTB 2 0V the full scale range is defined to FSR 2 REFT REFB 2Vp p The trade off of the differential input configuration versus the single ended is its higher complexity In either case the selection of the driver amplifier s
31. s REFT Top Reference Bypass CM Common Mode Voltage Output IN Complementary Analog Input IN Analog Input GND Ground Vs 5V Supply VDRV Logic Driver Supply Voltage Bit 11 Bit 12 LSB CLK k TEXAS 2 INSTRUMENTS ADS807 www ti com SBAS072A ELECTRICAL CHARACTERISTICS At T full specified temperature range Vs 5V differential input range 2V to 3V for each input sampling rate 50MHz unless otherwise noted PARAMETER RESOLUTION CONDITIONS ADS807E TYP 12 Tested SPECIFIED TEMPERATURE RANGE Ambient Air ANALOG INPUT 2V Full Scale Input Range Differential 2V Full Scale Input Range Single Ended 3V Full Scale Input Range Differential 3V Full Scale Input Range Single Ended Analog Input Bias Current Analog Input Bandwidth Input Impedance 2Vp p INT or EXT Ref 2Vp p INT or EXT Ref 3Vp p INT or EXT Ref 3Vp p INT or EXT Ref pA MHz MQ pF CONVERSION CHARACTERISTICS Sample Rate Data Latency Samples s Clock Cycles DYNAMIC CHARACTERISTICS Differential Linearity Error largest code error f 1MHz f 10MHz No Missing Codes No Mlssing Codes Integral Nonlinearity Error f 1MHz Spurious Free Dynamic Range f 1MHz 1dB input f 10MHz 1aB input f 20MHz 1aB input f 40MHz undersampling f 1MHz to 10MHz fs 40MHz 2 Tone Intermodulation Distortion f 12MHz and 13MHz 7dB each tone Signal to Noise Ratio SNR f 1MHz
32. uit example of Figure 1 shows the voltage feedback amplifier OPA680 driving the RF transformer which converts the single ended signal into a differential one The OPA680 can be employed for either single or dual supply operation For details on how to optimize its frequency response refer to the OPA680 data sheet SBOS083 available at www ti com With the 49 99 series output resistor the ampli fier emulates a 50Q source Rg Any DC content of the signal can be easily blocked by a capacitor 0 1uF and to also to avoid DC loading of the op amp s output stage AC Coupled Single Ended to Differential Interface with Dual Supply Op Amps Communications applications in particular demand a very high dynamic range and low levels of intermodulation distor tion but usually allow the input signal to be AC coupled into the A D converter Appropriate driver amplifiers need to be selected to maintain the excellent distortion performance of the ADS807 Often these op amps deliver the lowest distor tion with a small ground centered signal swing that requires dual power supplies Because of the AC coupling this re quirement can be easily accomplished and the needed level shifting of the input signal can be implemented without affecting the driver circuit See Figure 2 for an example of such an interface circuit specifically designed to maximize the dynamic performance The voltage feedback amplifier OPA642 maintains an ex cellent distortio
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