MAXIM MAX125/MAX126 Manual
Contents
1. kl d al ET 2x4 Channel Simultaneous Sampling 14 Bit DAS General Description Features The MAX125 MAX126 are high speed multichannel Four Simultaneous Sampling T H Amplifiers with 14 bit data acquisition systems DAS with simultaneous Two Multiplexed Inputs eight single ended inputs track holds T Hs These devices contain a 14 bit 3us total P puts eig 9 successive approximation analog to digital converter ADC 2 5 reference a buffered reference input us Conversion Time per Channel and a bank of four simultaneous sampling T H ampli fiers that preserve the relative phase information of the sampled inputs The MAX125 MAX126 have two multi 100k 3 ch plexed inputs for each T H allowing a total of eight sps 3 channels inputs In addition the converter is overvoltage tolerant 76ksps 4 channels to 17V a fault condition on any channel will not harm Input Range 5V MAX125 Throughput 250ksps 1 channel 142ksps 2 channels the IC Available input ranges are 5V MAX125 and 2 5V MAX126 2 5V MAX126 ST 5 Fault Protected Input Multiplexer 17V An on board sequencer converts one to four channels per CONVST pulse In the default mode one T H output 5V Supplies CH1A is converted An interrupt signal INT is provided Internal 2 5V or External Reference Operation after the last conversion is complete Convert two three or four channels by reprogramming the Programmab2. MIN MAX 0 096 0 104 2 44 0 004 0 011 0 10 0 012 0 017 0 30 SSOP EPS ik TOP VIEW sni e Lr SIE i FRONT VIEW SIDE VIEW NOTES 1 D amp E DO NOT INCLUDE MOLD FLASH 2 MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0 15mm 006 DDALLAS al AS Lake 3 LEADS BE COPLANAR WITHIN 0 10mm 004 PROPRIETARY INFORMATION 4 CONTROLLING DIMENSION MILLIMETERS ERE PACKAGE OUTLINE 36L SSOP 0 80 MM PITCH APPROVAL DOCUMENT CONTROL NO REV 1 P 210040 Revision History Pages changed at Rev 2 1 2 15 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 15 2007 Maxim Integrated Products MAXIM is registered trademark of Maxim Integrated Products Inc 9c LXVMW Sc LXVIW
3. duty cycle must be 30 to 70 26 CS Chip Select Input active low 27 WR Write Input active low 28 RD Read Input active low 29 CONVST Conversion Start Input Rising edge initiates sampling and conversion sequence 30 INT Interrupt Output Falling edge indicates the end of a conversion sequence 31 AVss 5V 5 Analog Supply Voltage 32 33 CH4A CH4B Channel 4 Multiplexed Inputs single ended 34 35 CH3A CH3B Channel 3 Multiplexed Inputs single ended Detailed Description The MAX125 MAX126 use a successive approximation conversion technique and four simultaneous sampling track hold T H amplifiers to convert analog signals into 14 bit digital outputs Each T H has two multiplexed inputs allowing a total of eight inputs Each T H output is converted and stored in memory to be accessed sequentially by the parallel interface with successive read cycles The MAX125 MAX126 internal micro sequencer can be programmed to digitize one two three or four inputs sampled simultaneously from either of the two banks of four inputs see Figure 2 The conversion timing and control sequences are derived from a 16MHz external clock the CONVST TOOUTPUT PIN 120pF i Figure 1 Load Circuit for Access Time and Bus Relinquish Time MAXIM 2x4 Channel Simultaneous Sampling 14 Bit DAS BANDGAP REFERENCE DO AO LSB D1 A1 THR
4. internal The data access time is defined as the time required for an output to cross 0 8V or 2 0V It is measured using the circuit of Figure 1 The measured number is then extrapolated back to determine the value with a 25pF load The bus relinquish time is derived from the measured time taken for the data outputs to change 0 5V when loaded with the circuit of Figure 1 The measured number is then extrapolated back to remove the effects of charging discharging the 120pF capacitor Thus the time given is the part s true bus relinquish time independent of the external bus loading capacitance MAXIM sss 5 9ZTXVW SCTXVIN 125 126 2x4 Channel Simultaneous Sampling 14 Bit DAS Pin Description PIN NAME FUNCTION 12 CH2B CH2A Channel 2 Multiplexed Inputs single ended 3 4 CH1B CH1A Channel 1 Multiplexed Inputs single ended 5 AVDD 5V 5 Analog Supply Voltage 6 REFIN External Reference Input Internal Reference Output Bypass with a O 1uF capacitor to AGND 7 REFOUT Reference Buffer Output Bypass with a 4 7 capacitor to AGND 8 36 AGND Analog Ground Both pins must be tied to ground 9 16 D13 D6 Data Bits D13 MSB 17 DVpp 5V 5 Digital Supply Voltage 18 DGND Digital Ground 19 20 D5 D4 Data Bits 21 24 D3 A3 D0 AO Bidirectional Data Bits Address Bits DO AO LSB 25 CLK Clock Input
5. 16MHz external clock 50 duty cycle TA TMIN to Tmax unless otherwise noted PARAMETER SYMBOL CONDITIONS DC ACCURACY Note 1 Resolution All channels Integral Nonlinearity Note 2 Differential Nonlinearity Bipolar Zero Error Guaranteed monotonic to 13 bits TA 25 TMIN to TMAX Bipolar Zero Error Match Between all channels Zero Code Tempco Error TA 25 C TA TMIN to TMAX Error Match Error Tempco DYNAMIC PERFORMANCE fc_k 16MHz fin Between all channels Signal to Noise Plus Distortion Total Harmonic Distortion SINAD 10 06kHz Notes 1 3 e channel mode MAX125 250ksps Note 4 MAX126 e chan mode channel 1A 250ksps Notes 4 5 5 C nel 1A S Spurious Free Dynamic Range Single chan mode channel 1A 250ksps Channel to Channel Isolation Single chan mode channel 1A 250ksps MAXIM 2x4 Channel Simultaneous Sampling 14 Bit DAS ELECTRICAL CHARACTERISTICS continued AVpp 5V 5 AVss 5V 596 DVpp 5V 596 VREFIN 2 5V AGND DGND OV 4 7uF capacitor from REFOUT to AGND 0 1uF capacitor from REFIN to AGND fci 16MHz external clock 50 duty cycle TA TMiN to Tmax unless otherwise noted P
6. ARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Input Voltage Range VIN V MAX126 2 5 MAX125 Vin 5V Input Current IIN 667 UA MAX126 VIN 2 5V Input Capacitance CIN Note 7 16 pF TRACK HOLD Acquisition Time tACQ 1 us Small Signal Bandwidth 8 MHz Full Power Bandwidth 0 5 MHz Droop Rate 2 mV ms Aperture Delay 5 ns Aperture Jitter 30 pSRMS Aperture Delay Matching 500 ps REFERENCE OUTPUT Note 8 Output Voltage VnEFOUT TA 25 C 2 475 2 500 2 525 V External Load Regulation OMA lt ILOAD lt 1mA 1 REFOUT Tempco Note 9 30 z r a7 REFERENCE INPUT nput Voltage Range 2 50 10 V nput Current REFIN 2 5V 10 UA nput Resistance Note 10 10 kQ nput Capacitance Note 7 10 pF EXTERNAL CLOCK External Clock Frequency 0 1 16 MHz DIGITAL INPUTS CONVST RD WR CS CLK AO A3 Note 1 nput High Voltage VIH 2 4 V nput Low Voltage VIL 0 8 V CONVST RD WR CS CLK 1 nput Current IIN HA A0 A3 10 nput Capacitance CIN Note 7 15 pF 9ZTXVW SCTXVIN 125 126 2x4 Channel Simultaneous Sampling 14 Bit DAS ELECTRICAL CHARACTERISTICS continued AVpp 5V 596 AVss 5V 596 DVpp 5V 596 VREFIN 2 5V AGND DGND OV 4 7uF capacitor from REFOUT to 0 1uF capacitor from REFIN to AGND fci 16MHz external clock 50 duty cycle TA to Tmax unle
7. EE STATE D2 A2 OUTPUT DRIVERS D3 A3 CONTROL LOGIC D18 MSB MAXIM MAX125 BUS INTERFACE MAX126 CONVST INT Figure 2 Functional Diagram 9CIXVW SCTIXVIA 125 126 2x4 Channel Simultaneous Sampling 14 Bit DAS BUFFER CHoLD FROM MICROSEQUENCER HOLD 7pF S3A S1B 2B a P A S3B MAXIM MAX125 MAX126 Figure 3 Equivalent Input Circuit signal and the programmed mode The T H amplifiers hold the input voltages at the CONVST rising edge Additional CONVST pulses are ignored until the last conversion for the sample is complete The ADC con verts each assigned channel in Aus and stores the result in an internal 4x14 bit memory At the end of the last conversion INT goes low and the T H amplifiers begin to track the inputs again The data can be accessed by applying successive pulses to the RD pin Successive reads access data words sequen tially The memory is not random access data from CH1 is always read first After accessing all pro grammed channels the address pointer selects CH1 again Additional read pulses cycle through the data words CS can be held low during successive reads Input Bandwidth The T H s input tracking circuitry has an 8MHz small signal bandwidth so it is possible to digitize high speed transient events and measure periodic signals with bandwidths exceeding the ADC s sampling rate by u
8. M MAX125 MAX126 Figure 6 Internal Reference Reading a Conversion Digitized data from up to four channels are stored in memory to be read out through the parallel interface After receiving an INT signal the user can access up to four conversion results by performing up to four read operations With CS low the conversion result from CH 1 is accessed and INT is reset high on the first RD falling edge On the RD rising edge the internal address pointer is advanced If a single conversion is pro grammed only one RD pulse is required and the 10 address pointer is reset to CH 1 For multichannel con versions up to four RD falling edges sequentially access the data for channels 1 through 4 For n chan nels converted 1 n x 4 the address pointer is reset to CH 1 after n RD pulses Do not perform a read oper ation during conversion as it will corrupt the conver sion s accuracy Applications Information External Clock The MAX125 MAX126 require a TTL compatible clock up to 16MHz for proper operation The clock duty cycle s range is between 30 and 70 Internal and External Reference The MAX125 MAX126 can be used with an internal or external reference voltage An external reference can be connected directly at REFIN An internal buffer with a gain of 1 provides 2 5V at REFOUT Internal Reference The full scale range with the internal reference is 5 for the MAX125 and 2 5V for the MAX126 Bypas
9. MAXIM MAIN DC VELOCITY FEEDBACK connect that point to the system analog ground plane to avoid interference from other digital noise sources If DGND is connected to the system digital ground digi tal noise may get through to the ADC s analog portion The AGND pins must be connected directly to a low impedance ground plane Extra impedance between the pins and the ground plane increases crosstalk and degrades INL Bypass AVpp and AVss with O 1uF ceramic capacitors to AGND Mount them with short leads close to the device Ferrite beads may also be used to further iso late the analog and digital power supplies Bypass DVpp with a 0 1uF ceramic capacitor to DGND 13 9CIXVNW SCTIXVIA 125 126 2x4 Channel Simultaneous Sampling 14 Bit DAS Pin Configuration Typical Operating Circuit TOP VIEW CH1A CH1B CH2A CH2B CH3B CHA MAXIM MAXIM CHAB MAX125 MAX125 MAX126 MAX126 AVpp AGND RD WR AVss cs CLK D0 AO LSB D1 A1 D2 A2 CLK CONVSTINT CS RD WR D3 A3 D4 D5 7 CONTROL INTERFACE Chip Information TRANSISTOR COUNT 4219 SUBSTRATE CONNECTED TO AVss Ao MAXX 2x4 Channel Simultaneous Sampling 14 Bit DAS Package Information The package drawing s in this data sheet may not reflect the most current specifications For the latest package outline information go to www maxim ic com packages INCHES MILLIMETERS
10. dth tRD 30 ns Data Access Time tDA 25pF load Note 13 30 ns Bus Relinquish Time tDH 25pF load Note 14 5 45 ns Mode 1 1 channe 3 C ion Ti Mode 2 2 channe 6 onversion Time S SR Mode 3 3 channe 9 Mode 4 4 channe 12 Mode 1 1 channe 250 Mode 2 2 channe 142 Conversion Rate Channel ksps Mode 3 3 channe 100 Mode 4 4 channe 76 Start Up Time Exiting shutdown 5 us Note 1 AVpp 5V AVss 5V DVpp 5V VREFIN 2 500V external Vin 5V MAX125 or 2 5V MAX126 Note 2 Relative accuracy is the analog value s deviation at any code from its theoretical value after the full scale range has been calibrated Note 3 CLK synchronized with CONVST Note 4 fin 10 06kHz Vin 5V MAX125 or 2 5V MAX126 Note 5 First five harmonics Note 6 All inputs except CH1A driven with 5V MAX125 or x2 5V MAX126 10kHz signal CH1A connected to AGND and digitized Note 7 Guaranteed by design Not production tested Note 8 AVpp 5V AVss DN DVpp 5V VIN OV all channels Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 Temperature drift is defined as the change in output voltage from 25 C to Tmin or Tmax It is calculated as TC AREFOUT REFOUT AT See Figure 2 Defined as the change in positive full scale caused by a 5 variation in the nominal supply voltage Tested with one input at full scale and all others at AGND VngrIN 2 5V internal Tested with Vin AGND on all channels VREFIN 2 5V
11. ed chan nel CS must be low during the four RD pulses The channel is selected with the binary coding of two switches A 16 bit 16373 latch simplifies layout Motor Control Applications Vector motor control requires monitoring of the individ ual phase currents In their most basic application the MAX125 MAX126 simultaneously sample two currents CH1A and CH2A Figure 10 and preserve the neces sary relative phase information Only two of the three phase currents have to be digitized because the third component can be mathematically derived with a coor dinate transformation 11 9ZTXVW SCTXVIN 125 126 2x4 Channel Simultaneous Sampling 14 Bit DAS 1 2 HC74 LATCH xiu CLOCK TO 16373 LATCH Figure 9 Output Demultiplexer Circuit The circuit of Figure 10 shows a typical vector motor control application using all available inputs of the MAX125 MAX126 CH1A and 2 are connected to two isolated Hall effect current sensors and are a part of the current torque feedback loop The MAX125 MAX126 digitize the currents and deliver raw data to the following DSP and controller stages where the vector processing takes place Sensorless vector control uses a computer model for the motor and an algorithm to split each output current into its magnetiz ing stator current and torque producing rotor current components 12 EXTERNAL CLOCK If 2 t
12. grated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 9c LXVMW Sc LXVIW MAX125 MAX126 2x4 Channel Simultaneous Sampling 14 Bit DAS ABSOLUTE MAXIMUM RATINGS Delen Pte esto 0 3V to 6V AVSS TIO ENER Aeddi er ette eee nns 0 3V to 6V AVpp to AGND DVpp to DGND AGND to DGND END eir e ORE etl ed 17V REFIN REFOUT to AGND Digital Inputs Outputs to DGND SSOP derate 11 8mW C above 70 C Operating Temperature Ranges MAX125CCAX MAX126CCAX 0 3V to 6V 0 3V to 0 3V 0 3V to 6V Storage Temperature Range Continuous Power Dissipation TA 70 C 125 126 Lead Temperature soldering 105 s EP 0 C to 70 C E 40 C to 85 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS AVpp 45V 5 AVss 5V 596 DVpp 5V 596 VREFIN 2 5V AGND DGND OV 4 7uF capacitor from REFOUT to AGND O 1uF capacitor from REFIN to AGND
13. ized To input data into the MAX125 MAX126 pull CS low program the bidirectional pins AO A3 Table 1 and pulse WR low Data is latched into the devices on the WR or CS rising edge The ADC is now ready to convert Once programmed the ADCs continue operating in the same mode until they are reprogrammed or until power is removed Figure 5 shows an example of program ming a four channel conversion using Input Mux A Starting a Conversion After programming the MAX125 MAX126 as outlined in the Programming Modes section pulse CONVST low to initiate a conversion sequence The analog inputs are sampled at the CONVST rising edge Do not start a new conversion while the conversion is in progress Monitor the INT output A falling edge indicates the end of a conversion sequence 9ZTXVW SCTXVIN 125 126 2x4 Channel Simultaneous Sampling 14 Bit DAS Table 1 Modes of Operation NVERSION A3 A2 A1 SEAN Deg MODE 0 0 0 0 3 Input Mux A Single Channel Conversion default at power up 0 0 0 1 6 Input Mux A Two Channel Conversion 0 0 1 0 9 Input Mux A Three Channel Conversion 0 0 1 12 Input Mux A Four Channel Conversion 0 1 0 0 3 Input Mux B Single Channel Conversion 0 1 0 6 Input Mux B Two Channel Conversion 0 1 1 0 9 Input Mux B Three Channel Conversion 0 1 1 1 12 Input Mux B Four Channel Conversion 1 X X X Power Down X Don t care MAXI
14. le On Board Sequencer MAX125 MAX126 through the bidirectional parallel High Speed Parallel DSP Interface interface Once programmed the MAX125 MAX126 continue to convert the specified number of channels per CONVST pulse until they are reprogrammed The channels are converted sequentially beginning with CH1 The INT signal always follows the end of the last conversion in a conversion sequence The ADC con Ordering Information verts each assigned channel in 3us and stores the Ss UNE result in an internal 14x4 RAM Upon completion of the conversions data can be Seen Du eer SUC SCH TEMP RANGE PACKAGE LSB CODE cessive pulses to the RD pin Four successive reads MAX125CCAX 0 C to 70 C 36 SSOP 44 A864 access four data words sequentially MAXIPSCEAX 40 C to 485 C 36SSOP 4 The parallel interface s data access and bus release MAX126CCAX 70 36 SSOP 44 A364 timing specifications are compatible with most popular digital signal processors and 16 bit 32 bit microproces sors so the MAX125 MAX126 conversion results can be accessed without resorting to wait states MAX126CEAX 40 C to 85 C 36 SSOP 4 A36 4 Applications Multiphase Motor Control Power Grid Synchronization Power Factor Monitoring 2 Typical Operating Circuit appears at end of data sheet Digital Signal Processing Vibration and Waveform Analysis Pin Configuration appears at end of data sheet MAXIM Maxim Inte
15. o 3 phase conversion is not practical three cur rents can be sampled simultaneously with the addition of a third sensor not shown Optional voltage position feedback can be derived by measuring two phase voltages CH3A CH4A Typically an isolated differential amplifier is used between the motor and the MAX125 MAX126 Again the third phase voltage can be derived from the magnitude phase voltage and its relative phase For optimum speed control and good load regulation close to zero speed additional velocity and position feedback are derived from an encoder or resolver and MAXIM 2x4 Channel Simultaneous Sampling 14 Bit DAS MAIN DC RESOLVER ENCODER EXTERNAL SETPOINTS CONTROLLER MAXIM MAX125 MAX126 14 BIT ADC MICRO SEQUENCER SIMULTANEOUS UH Figure 10 Vector Motor Control brought to the MAX125 MAX126 at CH4B The addi tional channels can be used to evaluate slower analog inputs such as the main DC bus voltage CH2B tem perature sensors CH3B or other analog inputs AUX CH1B Power Supply Bypassing and Ground Management For optimum system performance use printed circuit boards with separate analog and digital ground planes Wire wrapped boards are not recommended Connect the two ground planes together at the low impedance power supply source Connect DGND and AGND together at the IC For the best ground connec tion connect the DGND and AGND pins together and
16. our Channel Conversion Input Mux A Between conversions the buffer input is connected to channel 1 of the selected track hold bank When a channel is not selected switches S1 S2 and S3 are placed in hold mode to improve channel to channel isolation Digital Interface Input data AO A3 and output data 00 013 are multi plexed on a three state bidirectional interface This par allel can easily be interfaced with a microprocessor uP or DSP CS WR and RD control the write and read operations CS is the standard chip select signal which enables the controller to address the MAX125 MAX126 as O port When CS is high it disables the WR and MAXIM RD inputs and forces the interface into a high Z state Figure 4 details the interface timing Programming Modes The MAX125 MAX126 have eight conversion modes plus power down which are programmed through a bidirectional parallel interface At power up the devices default to the mode nput Mux A Single Channel Conversion The user can select between two banks mux inputs A or mux inputs B of four simultaneous sampled input channels as illustrated in Figure 2 An internal microsequencer can be programmed to convert one two three or four channels of the selected bank per sample For a single channel conversion CH1 is digitized and then INT goes low to indicate completion of the conversion For multichannel conversions INT goes low after the last channel has been digit
17. s REFIN with a 0 1uF capacitor to AGND and bypass the REFOUT pin with a 4 7uF min capacitor to AGND Figure 6 The maximum value to compensate the ref erence buffer is 22uF Larger values are acceptable if low ESR capacitors are used External Reference For operation over a wide temperature range an exter nal 2 5V reference with tighter specifications improves accuracy The MAX6325 is an excellent choice to match the MAX125 MAX126 accuracy over the commercial and extended temperature ranges with a MAXIM 2x4 Channel Simultaneous Sampling MAXIM MAX125 MAX126 MAXIMA MAX6325 Figure 7 External Reference 1 max temperature drift Connect an external reference at REFIN as shown in Figure 7 The minimum impedance is 7kQ for DC currents in both normal oper ation and shutdown Bypass REFOUT with a 4 7uF low ESR capacitor Power On Reset When power is first applied the internal power on reset circuitry activates the MAX125 MAX126 with INT high ready to convert The default conversion mode is Input Mux A Single Channel Conversion See the Programming Modes section if other configurations are desired After the power supplies have been stabilized the reset time is bus no conversions should be performed during this phase At power up data in memory is undefined Software Power Down Software power down is activated by setting bit A3 of the control word high Table 1 It is asserted after the WR or CS ri
18. sing edge at which point the ADC immedi ately powers down to a low quiescent current state AVpp drops to less than 1 5mA and AVss is reduced to less than 1mA The ADC blocks and reference buffer are turned off but the digital interface and the refer ence remain active for fast power up recovery Wake up the MAX125 MAX126 by writing a control word Table 1 The bidirectional interface interprets a logic zero at A3 as the start signal and powers up in the mode selected by AO A1 and A2 The reference MAXIM 14 Bit DAS OUTPUT CODE A tisp 16384 INPUT VOLTAGE LSB FS 2 x Vngrour MAX125 FS Vperour MAX126 Figure 8 Bipolar Transfer Function buffer s settling time and the bypass capacitor s value dominate the power up delay With the recommended 4 7yF at REFOUT the power up delay is typically Bus Transfer Function The MAX125 MAX126 have bipolar input ranges Fig ure 8 shows the bipolar output transfer function Code transitions occur at successive integer least significant bit LSB values Output coding is twos complement binary with 1LSB 610uV for the MAX125 and 1LSB 305pV for the MAX126 Output Demultiplexer An output demultiplexer circuit is useful for isolating data from one channel in a four channel conversion sequence Figure 9 s circuit uses the external 16MHz clock and the INT signal to generate four RD pulses and a latch clock to save data from the desir
19. sing undersampling techniques To avoid high frequency signals being aliased into the frequency band of interest anti alias filtering is recommended o lt o TRACK REFOUT 34 Analog Input Range and Input Protection The MAX125 s input range is 5V and the MAX126 s input range is 2 5V The input resistance for both parts is 10kO An input protection structure allows input volt ages to 17V without harming the IC This protection is also active in shutdown mode Track Holds The MAX125 MAX126 feature four simultaneous T Hs Each T H has two multiplexed inputs A T switch input configuration provides excellent hold mode isolation Allow 1us acquisition time for 14 bit accuracy The T H aperture delay is typically 10ns The 500ps aperture delay mismatch between the T Hs allows the relative phase information of up to four different inputs to be preserved Figure 3 shows the equivalent input circuit illustrating the ADC s sampling architecture Only one of four T H stages with its two multiplexed inputs CH_A and CH_B is shown All switches are in track configuration for channel A An internal buffer charges the hold capacitor to minimize the required acquisition time between conversions The analog input appears as a 10kQ resistor in parallel with a 16pF capacitor MAXIM 2x4 Channel Simultaneous Sampling 14 Bit DAS D 14 toy Figure 5 Programming a F
20. ss otherwise PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS 00 013 INT Note 1 Output High Voltage VOH IOUT 1mA 4 V Output Low Voltage VoL louT 1 6mA 0 4 V Three State Leakage Current DO D13 10 pA E No n o oF POWER REQUIREMENTS Positive Supply Voltage AVDD 4 75 5 5 25 V egative Supply Voltage AVss 5 25 5 4 75 V Digital Supply Voltage DVpp 4 75 5 5 25 V Positive Supply Current I AVpp dut 25 mA egative Supply Current AVss 17 13 mA Digital Supply Current I DVpp 3 5 mA Shutdown Positive Current mA Shutdown Negative Current 1 mA Shutdown Digital Current mA Positive Supply Rejection PSRR Note 11 1 2 LSB Negative Supply Rejection PSRR Note 11 2 LSB Power Dissipation Note 12 165 250 mW 4 MAXIM 2x4 Channel Simultaneous Sampling 14 Bit DAS TIMING CHARACTERISTICS Figure 4 AVpp 5V AVss 5V DVpp 5V AGND DGND OV TA Tmin to Tmax unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVST Pulse Width tcw 30 ns CS to WR Setup Time tows 0 5 CS to WR Hold Time tCWH 0 ns WR Low Pulse Width DA 30 ns CS to CONVST Delay tcsD 125 ns Address Setup Time tas 30 ns Address Hold Time tAH 0 ns RD to INT Delay 25pF load 30 ns Delay Time Between Reads tRD 40 ns CS to RD Setup Time iCRS 0 ns CS to RD Hold Time tCRH 0 ns RD Low Pulse Wi
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MAXIM MAX125/MAX126 Manual