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TEXAS INSTRUMENTS Industrial 14kSPS 24-Bit Analog-to-Digital Converter with Low-Drift Reference Manual

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1. 0 15 NOM i f casera a E Seating Plane tL EA 20 MAX 0 15 1j Z 0 0 0 05 PINS DIM A MAX A MIN 4040064 F 01 97 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 Dou 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testi
2. ADS1259 ADS1259B PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT CLOCK SOURCE fc x jatemaloseiiiatot Nominal frequency 7 3728 7 3728 MHz Accuracy 0 2 2 0 2 2 Frequency range 2 7 3728 8 2 7 3728 8 MHz Crystal oscillator Start up time 20 20 ms Frequency range 0 1 7 3728 8 0 1 7 3728 8 MHz External clock Duty cycle 40 60 40 60 96 DIGITAL INPUT OUTPUT DVDD 2 7V to 5 25V Vin 0 8 DVDD DVDD 0 8 DVDD DVDD V Vu DGND 0 2 DVDD DGND 0 2 DVDD V Vos lou 1mA 0 8 DVDD 0 8 DVDD V lou 8mA 0 75 DVDD 0 75 DVDD V Va log 1mA 0 2 DVDD 0 2 DVDD V lo 8mA 0 2 DVDD 0 2 DVDD V Input hysteresis 0 1 0 1 V Input leakage 0 lt VpieitaL input lt DVDD 10 10 uA POWER SUPPLY AVSS 2 6 0 2 6 0 V AVDD AVSS 4 4 75 AVSS 5 25 AVSS 4 75 AVSS 5 25 V DVDD 2 7 5 25 2 7 5 25 V fies op 23 8 ee 38 jen AVDD AVSS current ference enabled in i us l sions denti 1 40 1 40 lAl Power Down mode 1 40 1 40 pA Operating 500 700 500 700 uA DVDD current Sleep mode 160 300 160 300 pA Power Down mode 1 10 1 10 uA Operating 13 22 13 22 mW Power dissipation utres enabled id i ii alere dissi 05 12 05 12 mW Power Down mode 10 240 10 240 uW TEMPERATURE RANGE Specified temperature range 40 4105 40 105 G Operating temperature range 40 4125 40 4125 C Storage temperature range 60 150 60 150 C 11 Crystal operation using 18pF load capacitors 12 Specified with internal oscillator
3. VREFP VREFN Input Current nA VREFP VREFN Input Current nA t Current AVSS 55 35 15 5 25 45 65 85 105 125 0 5 1 0 15 20 25 30 35 40 45 50 Temperature C Veer V Figure 26 Figure 27 DIFFERENTIAL INPUT IMPEDANCE vs TEMPERATURE INTERNAL REFERENCE SETTLING TIME 130 Crerin 1uF X7R 128 Internal Oscillator External Crystal 124 Settling of Final Value 122 Differential Input Impedance kQ 120 55 35 15 5 25 45 65 85 105 125 Temperature C Time s Figure 28 Figure 29 INTERNAL OSCILLATOR vs TEMPERATURE 7 40 7 35 7 30 Internal Oscillator MHz 55 35 15 5 25 45 65 85 105 125 Temperature C Figure 30 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 I TEXAS INSTRUMENTS www ti com OVERVIEW The ADS1259 is a high linearity low drift analog to digital converter ADC designed for the needs of industrial process control precision instrumentation and similar applications The converter provides high resolution 24 bit output data at sample rates ranging from 10SPS to 14 4kSPS Figure 31 shows a block diagram of the ADS1259 The devic
4. 30 40 Frequency kHz Figure 39 Frequency Response for Data Rate 14 4kSPS 30 40 Frequency kHz Figure 40 Frequency Response Data Rate 3600SPS R 4 Frequency Hz Figure 41 Magnitude Response for Data Rate 60SPS Submit Documentation Feedback Product Folder Link s ADS1259 19 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 ALIASING The low pass characteristic of the digital filter repeats at multiples of the modulator rate fmop fci 78 Figure 42 shows the responses plotted out to 7 3728MHz at the data rate of 14 4kSPS Notice how the responses near dc 0 9216MHz 1 8432MHz 2 7698MHz etc are the same as given by f Nfuop fparA Where N 0 1 2 etc The digital filter attenuates high frequency noise on the ADS1259 inputs up to the frequency where the response repeats However noise or frequency components existing in the signal where the response repeats alias into the passband Often a simple RC antialias filter is sufficient to reject these input frequencies T S o o 3 E o s 0 9 1 8 2 8 3 7 4 6 5 5 65 74 Frequency MHz Figure 42 Frequency Response to 7 3728MHz Data Rate 14400SPS 20 Submit Documentation Feedback I TEXAS INSTRUMENTS www ti com CLOCK SOURCE There are three ways to provide the ADS1259 clock the internal oscillat
5. SBAS424C JUNE 2009 REVISED MARCH 2010 MODULATOR OVERLOAD BEHAVIOR The ADS1259 modulator is inherently stable and therefore has predictable recovery behavior resulting from an input overdrive condition The modulator does not exhibit the self resetting behavior of other modulator types which often results in unstable output conversion results when overdriven The ADS1259 modulator outputs a 1s density data stream at 90 duty cycle with the positive full scale input signal applied 10 duty cycle with the negative full scale signal If the input is overdriven past 90 modulation but below 100 modulation 10 and 0 for negative overdrive respectively the modulator remains stable and continues to output the 1s density data stream The digital filter may or may not clip the output codes to FS or FS depending on the duration of the overdrive When the input is returned to the normal range from a long duration overdrive worst case the modulator returns immediately to the normal range but the group delay of the digital filter delays the return of the conversion result to within the linear range one reading for the sinc filter and two readings for completely settled data If the inputs are sufficiently overdriven to drive the modulator to full duty cycle that is all 1s or all Os the modulator enters a stable saturated state The digital output code may clip to FS or FS again depending on the duration A small
6. Table 13 Offset Calibration Word REGISTER BYTE BIT ORDER OFCO LSB B7 B6 B5 B4 B3 B2 B1 BO LSB OFC1 MID B15 B14 B13 B12 B11 B10 B9 B8 OFC2 MSB B23 MSB B22 B21 B20 B19 B18 B17 B16 Table 14 Full Scale Calibration Word REGISTER BYTE BIT ORDER FSCO LSB B7 B6 B5 B4 B3 B2 B1 BO LSB FSC1 MID B15 B14 B13 B12 B11 B10 B9 B8 FSC2 MSB B23 MSB B22 B21 B20 B19 B18 B17 B16 26 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com CALIBRATION The ADS1259 has commands to correct for system offset and gain errors Calibration can be performed at any time the ADS1259 and associated circuitry such as the input amplifier external reference power supplies etc have stabilized Options include calibrating after power up after temperature changes or calibration at regular intervals To calibrate Set the gate control mode PULSE bit 0 Start the ADS1259 conversions Apply the appropriate input to the ADS1259 zero or full scale Allow time for the input to completely settle Send the OFSCAL offset calibration or GANCAL full scale calibration command as appropriate Wait for calibration to complete as given by the time listed in 15 DRDY goes low when calibration is complete The conversion result at this time uses th
7. 2 Shaded cells indicate improved specifications of the ADS1259B 3 Calibration accuracy is on the level of noise signal and ADC reduced by the effect of 16 reading averaging 4 Reference drift specified by design and final production test Drift calculated over the specified temperature range using box method 5 Excludes internal reference error 6 fpata 14 4kSPS Placing a notch of the digital filter at 60Hz setting fpara 10SPS or 60SPS further improves the common mode rejection and power supply rejection of this input frequency 7 Absolute input voltage range for out of range specification AVSS 150mV lt AINP or AINN lt AVDD 150mV 8 Over the range AVSS lt VREFP or VREFN lt AVDD For reference voltage exceeding AVDD or AVSS input current 150nA 10mV 9 Limit the reference output current to 10mA 10 Crerout THF Crer 1HF Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS continued Minimum maximum specifications are at T 40 C to 105 C Typical specifications are at T4 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V fork 7 3728MHZ Veer 2 5V and fpara 60SPS unless otherwise noted I TEXAS INSTRUMENTS www ti com
8. 2 5 2 0 1 5 1 0 0 5 00 05 10 15 20 25 0 05 10 15 20 25 3 0 35 40 45 50 55 Vin V Reference Voltage V Figure 10 Figure 11 LINEARITY DEVIATION vs INPUT LEVEL INTEGRAL NONLINEARITY vs TEMPERATURE 3 0 T 125 C 5 Units T 85 C z T 25 C 29 E amp 2 2 0 e 2 E S S 1 5 gt z 2 1 0 oO 0 5 0 2 5 2 0 1 5 1 0 05 0 05 1 0 15 20 25 Input Signal V Temperature C Figure 12 Figure 13 8 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 l TEXAS INSTRUMENTS www ti com Occurrences a INL ppm ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 TYPICAL CHARACTERISTICS continued At T4 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V Vper 2 5V VREFN AVSS fo 7 3728MHz and foata 60SPS unless otherwise noted OFFSET vs TEMPERATURE 100 5 Units 75 F lt 50 25 0 25 50 75 55 35 15 5 25 45 65 85 105 125 Temperature C Figure 14 OFFSET DRIFT DISTRIBUTION HISTOGRAM 30 60 Units From Two Production Lots 25 20 E o Offset Drift uV C Figure 16 INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 3 0 2 5 15 20 25 3 0 35 40 45 50 55 Reference Voltage V 0 05 10 Figure 18 Copyright 2009 2010 Texas Instruments Incorporated Gain Error ppm 500 40
9. 2009 2010 Texas Instruments Incorporated ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 BASIC CONNECTION The ADS1259 basic connections are shown in Figure 63 The diagram shows the ADS1259 operating with an internal oscillator and with internal reference Dual 2 5V analog power supplies are also shown Pins 6 9 are the SPI port connection The remaining digital I O pins connect to the controller I O Note that the minimum configuration of the digital I O may include only SCLK DIN and DOUT 202 to 502 ADS1259 WM AINP AVDD Signal Input Q AINN AVSS 202 to 502 Controller I O 4 RESET PWDN VREFN 2 5V Reference Output START VREFP Drives the PGA280 SYNCIN Pin AAH sYNcoUT REFOUT 5 DVDD DGND Controller SPI Port BYPASS XTAL2 Controller I O XTAL1 CLKIN 1 It is recommended to buffer the ADS1259 inputs The output isolation resistors may be incorporated within the amplifier feedback loop 2 Low distortion COG or film capacitor recommended Figure 63 ADS1259 Basic Connection Diagram LAYOUT Place the input buffer and input decoupling capacitors close to the ADS1259 inputs The bypass capacitors for power supply and reference decoupling should also be placed close to the device In some cases it may be necessary to use a split ground plane in which digital return currents of external components are routed
10. DIFFERENTIAL INPUT SIGNAL Vin IDEAL OUTPUT AINP AINN CODE gt VREF 7FFFFFh V oe a l 000001h 0 000000h VREF 22 1 FFFFFFh 2 3 lt V REF Ex 800000h 2 _ 4 1 Excludes effects of noise linearity offset and gain errors DATA INTEGRITY Data readback integrity is augmented by a checksum byte and redundant data read capability The checksum byte is the sum of three data conversion bytes offset by 9Bh Additionally the data conversion bytes may be read multiple times by continuing to shift data past the initial read of 24 bits 32 bits if checksum is enabled Copyright 2009 2010 Texas Instruments Incorporated ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 DATA CHECKSUM BYTE AND FLAG BIT An optional checksum byte can be appended to the conversion data bytes The checksum makes the data word length four bytes in length instead of three The checksum byte is enabled by the register bit CHKSUM The checksum itself is the least significant byte sum of the three conversion data bytes offset by 9Bh Note that the checksum byte option only applies to the readback conversion data not to register data The checksum is either seven bits or eight bits depending if the FLAG register bit is enabled If the FLAG bit is enabled the checksum is seven bits with bit 7 replaced by the out of range flag Figure 57 and Table 17 describe the combinations of the FLAG and CHKSUM register bits Checksum
11. because the sinc digital filter provides more filtering than the sinc digital filter sinc provides lower noise conversions Table 1 shows the noise as a function of data rate and filter mode Table 1 expresses typical noise data in several ways RMS noise effective number of bits ENOB and noise free bits ENOB is calculated from Equation 1 in FSR RMS Noise ENOB in 2 Where FSR 2Vper 1 The calculation of noise free bits uses the same formula as Equation 1 except that the peak to peak noise value is used instead of RMS noise ADC The analog to digital converter ADC section of the ADS1259 is composed of two blocks a high accuracy modulator and a programmable digital filter ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 MODULATOR The high performance modulator is an inherently stable fourth order A 2 2 pipelined structure as shown in Figure 32 It shifts the quantization noise to a higher frequency out of the passband where digital filtering can easily remove it Analog Input Vin 2nd Order AX 1st Stage To Digital Filter 2nd Order AX 2nd Stage 4th Order Modulator Figure 32 Fourth Order Modulator The modulator first stage converts the analog input voltage into a pulse code modulated PCM stream When the level of differential analog input AINP AINN is near the level of the reference voltage VREFP VREFN the 1s density of the PCM data strea
12. 3600SPS 111 14400SPS NOTE fork 7 3728MHz Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 Submit Documentation Feedback 37 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com OFCO OFFSET CALIBRATION BYTE 0 LEAST SIGNIFICANT BYTE Address 3h 7 6 5 4 3 2 1 0 OFCO7 OFCO06 OFCO05 OFC04 OFCO03 OFC02 OFCO01 OFCO00 Reset value 00000000b OFC1 OFFSET CALIBRATION BYTE 1 Address 4h 7 6 5 4 3 2 1 0 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFCO09 OFCO08 Reset value 00000000b OFC2 OFFSET CALIBRATION BYTE 2 MOST SIGNIFICANT BYTE Address 5h 7 6 5 4 3 2 1 0 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 Reset value 00000000b FSCO FULL SCALE CALIBRATION BYTE 0 LEAST SIGNIFICANT BYTE Address 6h 7 6 5 4 3 2 1 0 FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSCO01 FSCO00 Reset value 00000000b FSC1 FULL SCALE CALIBRATION BYTE 1 Address 7h 7 6 5 4 3 2 1 0 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 Reset value 00000000b FSC2 FULL SCALE CALIBRATION BYTE 2 MOST SIGNIFICANT BYTE Address 8h 7 6 5 4 3 2 1 0 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 Reset value 01000000b 38 Submit Documentation Feedback Product Folder Link s ADS1259 Copyright
13. 496 50 25 0 25 50 75 100 125 Temperature C Figure 22 OUT OF RANGE THRESHOLD DISTRIBUTION HISTOGRAM 18 Relative to 10596 16 30 Units 14 a 12 o E 10 8 8 6 4 2 0 OO XO st QN yrrir oooco ai Threshold Error Figure 24 10 Submit Documentation Feedback Internal Reference Voltage V Threshold Error Product Folder Link s Power Supply Current mA N o POWER SUPPLY CURRENT vs TEMPERATURE 4 0 3 5 3 0 nternal Reference On Temperature C Figure 21 INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2 504 2 502 2 500 2 498 2 496 2 494 45 65 85 105 125 Temperature C Figure 23 OUT OF RANGE THRESHOLD vs TEMPERATURE 2 0 5 Units B 55 35 15 5 25 45 65 85 105 125 Temperature C Figure 25 Copyright 2009 2010 Texas Instruments Incorporated ADS1259 ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 TYPICAL CHARACTERISTICS continued At T4 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V Vper 2 5V VREFN AVSS fg 7 3728MHz and foata 60SPS unless otherwise noted REFERENCE INPUT CURRENT vs TEMPERATURE REFERENCE INPUT CURRENT vs REFERENCE VOLTAGE 250 200 VREFP Input Current VREFN Input Current VREFP AVDD
14. 6 5 4 3 2 1 0 1 0 ID1 IDO 0 RBIAS 0 SPI Reset value 10XX0101b Bit 7 Reserved read only Always returns 1 Bit 6 Reserved read only Always returns O Bits 5 4 ID 1 0 Factory programmed identification bits read only Note that these bits may change without notification Bit 3 Reserved Always write O Bit 2 RBIAS Internal reference bias 0 Internal reference bias disabled 1 Internal reference bias enabled default Bit 1 Reserved Always write O Bit 0 SPI SCLK timeout of SPI interface 0 SPI timeout disabled 1 SPI timeout enabled default when SCLK is held low for 218 clock cycles Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Link s ADS1259 ADS1259 P I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com CONFIG1 CONFIGURATION REGISTER 1 Address 1h 7 6 5 4 3 2 1 0 FLAG CHKSUM 0 SINC2 EXTREF DELAY2 DELAY1 DELAYO Reset value 00001000b Bit 7 FLAG Out of range flag 0 Disabled default 1 Enabled replaces bit 24 LSB of the conversion data with the out of range bit if the CHKSUM byte is enabled bit 7 of the checksum byte Bit 6 CHKSUM Checksum 0 Disabled default 1 Conversion data checksum byte included in readback Bit 5 Reserved Always write O Bit 4 SINC2 Digital filter mode 0 sinc filter default 1 sinc filter Bit
15. C RELATED PRODUCTS FEATURES PRODUCT 24 bit ADC with integrated PGA ADS1256 Wide range PGA PGA280 High precision PGA G 1 10 100 1000 PGA204 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Copyright 2009 2010 Texas Instruments Incorporated ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com This integrated circuit can be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage Ata ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications ORDERING INFORMATION For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI web site at www ti com ABSOLUTE MAXIMUM RATINGS Over operating free air temperature range unless otherwise noted ADS1259 MIN MAX UNIT AVDD to AVSS 0 3 5 5 V AVSS to DGND 2 8 40 3 V DVDD to DGND 0 3 5 5 V Input curren
16. MSB data byte Mid data byte LSB data byte 9Bh 32 Bit Conversion Data CHKSUM 1 24 Bit Conversion Data CHKSUM 0 Flag 1 Bit 0 of LSB Conversion Data E Bit 7 of Checksum Figure 57 Checksum Byte and Out of Range Flag Table 17 Checksum Byte and Over Range Flag FLAG CHKSUM REGISTER REGISTER BIT BIT DESCRIPTION No checksum byte no out of range flag 8 bit checksum byte no out of range flag 0 0 0 1 No checksum byte out of range flag replaces LSB bit 0 of conversion data 7 bit checksum byte out of range replaces MSB bit 7 of checksum byte Submit Documentation Feedback 29 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 DATA RETRIEVAL New conversion data are available when DRDY goes low Read the data within 20 fci cycles of the next DRDY falling edge or the data are incorrect Do not read data during this interval The conversion data may be read in two ways Data Read in Continuous mode and Data Read in Stop Continuous mode Data Read Operation in Continuous Mode In Read Data Continuous mode the conversion data may be shifted out directly without the need of the data read command When DRDY and DOUT if CS is low assert low the conversion data are ready The data are shifted out on DOUT on the rising edges of SCLK with the most significant bit MSB clocked out first In Gate Convert Mode DRDY retu
17. details GANCAL Gain Calibration Description This command performs a gain calibration Apply a full scale signal and allow the input to stabilize before sending the command see the Calibration section for more details 34 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 REGISTER MAP The operation of the ADS1259 is controlled through a set of registers Collectively the registers contain all the information needed to configure the part such as data rate calibration etc Table 20 shows the register map Table 20 Register Map ADDRESS REGISTER VALUE BIT7 BIT6 BIT5 BIT 4 BIT3 BIT 2 BIT 1 BITO Oh CONFIGO 10XX0101b 1 0 ID1 IDO 0 RBIAS 0 SPI th CONFIG1 00001000b FLAG CHKSUM 0 SINC2 EXTREF DELAY2 DELAY1 DELAYO 2h CONFIG2 XX000000b DRDY EXTCLK SYNCOUT PULSE 0 DR2 DR1 DRO 3h OFCO 00000000b OFCO7 OFCO6 OFCO05 OFC04 OFC03 OFC02 OFCO1 OFCO0 4h OFC1 00000000b OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFCO9 OFC08 5h OFC2 00000000b OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 6h FSCO 00000000b FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSCO01 FSC00 7h FSC1 00000000b FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 8h FSC2 01000000b FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 CONFIGO CONFIGURATION REGISTER 0 Address 0h 7
18. filter cycle begins The programmable delay may be useful to provide time for external circuits such as after an external signal mux change before the reading is started Register bits DELAY 2 0 set the initial delay time as shown in Table 8 Table 8 Initial START Delay DELAY 2 0 tpeLAv terk toevay us 000 0 0 001 64 8 68 010 128 17 4 011 256 34 7 100 512 69 4 101 1024 139 110 2048 278 111 4096 556 1 fei 7 3728MHz After the programmable delay the digital filter is reset and a new conversion is started DRDY goes low when data are ready There is no need to ignore or discard data the data are completely settled The total time to perform the first conversion is the sum of the programmable delay time and the settling of the digital filter That is the value of Table 8 and Table 9 combined Figure 52 shows the timing and Table 9 shows the settling time with programmable delay equal to 0 Table 9 Settling Time Using START DATA RATE SETTLING TIME tset ms SPS sinc sinc 10 100 200 16 6 60 3 120 50 20 3 40 4 60 17 0 33 7 400 2 85 5 42 1200 1 18 2 10 3600 0 632 0 980 14 400 0 424 0 563 1 fei 7 3728MHz DELAY 2 0 000 Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com Settling Time While Continuously Converting If th
19. less for higher data rate The filter consists of two sections a fixed decimation sinc filter followed by a variable decimation filter configurable as sinc or sinc as illustrated in Figure 38 The sinc filter has fixed decimation of 64 and reduces the data rate of the modulator from fci 8 to fc 7512 The second filter stage receives the data from the sinc filter The second filter stage has programmable averaging or decimation and can be configured in either sinc or sinc mode The decimation ratio of this stage sets the final output data rate As detailed in Table 3 the DR 2 0 register bits program the decimation ratio and the final output data rate The output data rates are identical for both sinc and sinc filters Table 3 Decimation Ratio of Final Filter Stage DR 2 0 REGISTER DECIMATION BITS RATIO R DATA RATE SPS 111 1 14400 110 4 3600 101 12 1200 100 36 400 011 240 60 010 288 50 001 864 16 6 000 1440 10 Modulator Rate fc 8 Analog sinc Filter Modulator decimate by 64 DR 2 0 Register Bits Program Decimation 18 Submit Documentation Feedback Le Figure 38 Block Diagram of Digital Filter I TEXAS INSTRUMENTS www ti com The SINC2 register bit selects either the sinc or sinc filter The sinc filter settles in one conversion cycle while the sinc filter settles in two conversion cycles However the sinc filter has th
20. low to control conversions by command STOP Stop Conversions Description This command stops conversions When the STOP command is sent the conversion in progress completes and further conversions are stopped If conversions are already stopped this command has no effect See the Conversion Control section Tie the START pin low to control conversions by command RDATAC Read Data Continuous Description This command enables the Read Data Continuous mode default See the Read Data Continuous Mode section for details Disable this mode with the SDATAC command before sending other commands SDATAC Stop Read Data Continuous Description This command cancels the Read Data Continuous mode 32 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 RDATA Read Data Description Issue this command opcode after DRDY goes low to read the conversion result in Stop Read Data Continuous mode See the Read Data Mode section for more details RREG Read from Registers Description These opcode bytes read register data The Register Read command is a two byte opcode followed by the output of the register data The first byte contains the command opcode and the register address The second byte of the opcode specifies the number of registers to read 1 First opcode byte 0010 rrrr where rrrri
21. operating internal oscillator current 40uA typ 13 External CLKIN SCLK stopped Digital inputs maintained at Vi or Vij voltage levels Submit Documentation Feedback Product Folder Link s ADS1259 Copyright 2009 2010 Texas Instruments Incorporated ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 PIN CONFIGURATION PW PACKAGE TSSOP 20 TOP VIEW AINP AVDD AINN AVSS RESET PWDN VREFN START VREFP SYNCOUT REFOUT 2 ADS1259 CS DVDD SCLK DGND DIN BYPASS DOUT XTAL2 DRDY XTAL1 CLKIN ADS1259 Terminal Functions PIN NAME PIN FUNCTION DESCRIPTION AINP 1 Analog input Positive analog input AINN 2 Analog input Negative analog input RESET PWDN 3 Digital input Reset Power Down reset is active low hold low for power down START 4 Digital input Start conversions active high SYNCOUT 5 Digital output Sync clock output fc 8 cs 6 Digital input SPI chip select active low SCLK 7 Digital input SPI clock input DIN 8 Digital input SPI data input DOUT 9 Digital output SPI data output DRDY 10 Digital output Data ready output active low Internal oscillator DGND XTAL1 CLKIN 11 Digital input External clock clock input Crystal oscillator external crystal1 XTAL2 12 Digital External crystal2 otherwise no connection BYPASS 13 Analog Core voltage bypass DGND 14 Digital Digital ground DVDD 15 Digital D
22. 0 Gain Error ppm Occurrences GAIN vs TEMPERATURE 5 Units 25 45 105 125 Temperature C 65 85 Figure 15 GAIN DRIFT DISTRIBUTION HISTOGRAM 60 Units From Two Production Lots oN TO ODO N o rrr dq d ai t N Gain Drift ppm C Figure 17 GAIN ERROR AND OFFSET vs REFERENCE VOLTAGE 50 10 0 150 100 Q zh 0 g S 50 100 150 05 10 15 20 25 30 35 40 45 50 55 Reference Voltage V Figure 19 Submit Documentation Feedback 9 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 I TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued At T4 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V Vae 2 5V VREFN AVSS foi 7 3728MHz and foata 60SPS unless otherwise noted POWER SUPPLY AND COMMON MODE REJECTION vs FREQUENCY 140 CMR 120 l BVDD DVDD m Md CMR AVDD AVSS T 80 8 AVDD o 60 c AVSS amp 40 20 0 10 100 1k 10k 100k 1M Power Supply and Common Mode Frequency Hz Figure 20 INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2 501 ADS1259B 2 500 2 499 2 498 2 497 Internal Reference Voltage V 2
23. 3 EXTREF Reference select 0 Internal 1 External default Bits 2 0 DELAY 2 0 START conversion delay 000 No delay default 001 64 to 010 128 to 011 256 tox 100 512 tox 101 1024 tor 110 2048 to 111 4096 to 36 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com 7 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 CONFIG2 CONFIGURATION REGISTER 2 Address 2h 6 5 4 3 2 DRDY EXTCLK SYNCOUT PULSE 0 DR2 DR1 DRO Reset value XX000000b DRDY Data ready read only This bit duplicates the state of the DRDY pin Poll this bit to indicate that data are ready When DRDY is low data are ready Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2 0 EXTCLK Clock source read only 0 Device clock source is internal oscillator 1 Device clock source is external clock Note that the ADS1259 selects the clock source automatically SYNCOUT SYNCOUT clock enable 0 SYNCOUT disabled default 1 SYNCOUT enabled Note that if disabled the output is driven low PULSE Conversion Control mode select 0 Gate Control mode default 1 Pulse Control mode Reserved Always write O DR 2 0 Data rate setting 000 10SPS default 001 16 6SPS 010 50SPS 011 60SPS 100 400SPS 101 1200SPS 110
24. 9 25 45 65 Temperature C 85 Figure 6 Copyright 2009 2010 Texas Instruments Incorporated 105 125 Submit Documentation Feedback Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com TYPICAL CHARACTERISTICS continued At T4 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V Vper 2 5V VREFN AVSS fg 7 3728MHz and foata 60SPS unless otherwise noted NOISE vs INPUT VOLTAGE NOISE vs INPUT VOLTAGE 7 7 Data Rate 10SPS Data Rate 60SPS 6 6 5 5 g B 5 4 5 4 Internal Reference Internal Reference Ratiometric Configuration E Crer 1uF Ratiometric Configurati o o 2 3 Crerin 1uF A 3 o o z z 2 2 1 1 0 0 2 5 2 0 1 5 1 0 0 5 0 05 10 15 20 2 5 2 5 2 0 1 5 1 0 0 5 0 05 10 15 20 2 5 Vin V Vin V Figure 8 Figure 9 NOISE vs INPUT VOLTAGE NOISE vs REFERENCE VOLTAGE 10 19 Internal Reference Shorted Input Crerin 1HF 9 8 8 REF5025 a 7 A E 6 E 6 gt gt ometric Configuration S35 o o ta Rate 14 4kSPS o 4 o 4 z z 3 Data Rate 10SPS Data Rate 16 6SPS 2 2 Data Rate 14 4kSPS 1 0 0
25. EM PERFORMANCE Resolution No missing codes 24 24 Bits Data rate foara 10 14400 10 14400 SPS ntegral nonlinearity Best fit method 0 0003 0 001 0 00004 0 0003 FSR Offset error 40 250 40 250 uV Offset error after calibration 1 1 uV Offset drift Ta 40 C to 105 C 0 05 0 25 0 05 0 25 uV C Gain error 0 05 0 5 0 05 0 5 Gain error after calibration 0 0002 0 0002 96 Gain drift Ta 40 C to 105 C 0 5 25 0 5 2 5 ppm C Normal mode rejection See Figure 41 Common mode rejection 60Hz ac 9 100 120 100 120 dB Noise See Table 1 0 7 0 7 uV AVDD AVSS power supply 60Hz ac 85 95 85 95 dB rejection DVDD power supply rejection 60Hz ac 85 110 85 110 dB OUT OF RANGE DETECTION Threshold Level 105 105 FSR Accuracy 0 5 0 5 FSR VOLTAGE REFERENCE INPUTS Reference input range Vper E E 0 5 2 5 Bir co 7 0 5 2 5 digo bad V REM td us wer os AMA wem os v nee B us input VREFN 0 5 AVDD 100mV VREFN 0 5 AVDD 100mV V Average reference input current pup poe Average reference input current drift Internal or external clock 0 2 0 2 nA C INTERNAL VOLTAGE REFERENCE Reference output voltage Kui ae I 2 5 2 5 V Accuracy Ta 25 C 10 4 10 2 donee m Ta 40 C to 105 C 10 40 4 12 ppm C Ta 0 C to 85 C 2 5 ppm C Drive current sink and source 10 10 10 10 mA Load regulation 10 10 uV mA Turn on settling time 0 001 settling 1 1 s 1 SPS samples per second
26. I TEXAS INSTRUMENTS www ti com aD ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 Industrial 14kSPS 24 Bit Analog to Digital Converter with Low Drift Reference Check for Samples ADS1259 FEATURES 24 Bits No Missing Codes Output Data Rates From 10 To 14kSPS High Performance INL 0 4ppm Reference Drift 2ppm C Gain Drift 0 5ppm C Offset Drift 0 05 V C Noise 0 71 Vgys at 608PS Simultaneous 50 60Hz Rejection at 10SPS Single Cycle Settling Internal Oscillator Out of Range Detection Readback Data Integrity by Checksum and Redundant Data Read Capability SPI Compatible Interface Analog Supply 5V or 2 5V Digital Supply 2 7V to 5V Low Power 13mW APPLICATIONS A SPI All other trademarks are the property of their respective owners Industrial Process Control Scientific Instrumentation Test and Measurement AVDD VREFP VREFN REFOUT cma 2 5V Reference Programmable Calibration Digital Filter Engine Control Out of Range Interface Detection AX Modulator O AVSS DGND is a trademark of Motorola PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters DESCRIPTION The ADS1259 is a high linearity low drift 24 bit analog to digital converter ADC designed for the ne
27. TER BIT Internal 1 0 External See 1 used between REFOUT and AVSS Submit Documentation Feedback If the reference output is not required set RBIAS 0 If the reference output is enabled RBIAS 1 an external 1uF capacitor must be Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com Reference Drift The ADS1259 internal reference is designed for minimal drift error which is defined as the change in reference voltage over temperature The drift is calculated using the box method as described by Equation 2 Vaeruax ha VaeruiN Drift Vaeenom X Temp Range x 10 ppm Where Veermax Vrermin and Vrernom are the maximum minimum and nominal reference output voltages respectively over the specified temperature range 2 The ADS1259 internal reference features a maximum drift coefficient of 5ppm C over 0 C to 85 C operating range and 12ppm C over 40 C to 105 C operating range External Reference To select the ADS1259 for external reference operation set the EXTREF register bit 1 default If desired the internal reference can continue to provide a 2 5V reference output via the REFOUT and AVSS pins In this case set the RBIAS register bit 1 to power the internal reference If the internal reference is activated an external 1uF capacitor from REFOUT to AVSS is required Co
28. TOP conversion 0000 101x 0Ah or OBh 2 RDATAC Control Set Read Data Continuous mode 0001 0000 10h SDATAC Control Stop Read Data Continuous mode 0001 0001 11h RDATA Data Read data by opcode 0001 001x 12h or 13h RREG Register Read nnnn register at address rrrr 0010 rrrr 20h 0000 rrrr 0000 nnnn 00h nnnn WREG Register Write nnnn register at address rrrr 0100 rrrr 40h 0000 rrrr 0000 nnnn 00h nnnn OFSCAL Calibration Offset calibration 0001 1000 18h GANCAL Calibration Gain calibration 0001 1001 19h 1 nnnn number of registers to be read written 1 For example to read write 3 registers set nnnn 2 0010 rrrr starting register address for read write opcodes 2 These commands are decoded on the seventh bit of the opcode The eighth bit is a don t care bit All other commands are decoded on the eighth bit WAKEUP Exit SLEEP Mode Description This command exits the low power SLEEP mode see the SLEEP Mode section SLEEP Enter SLEEP Mode Description This command enters the low power SLEEP mode See the SLEEP Mode section RESET Reset Registers to Default Values Description This command resets the digital filter cycle and returns all register settings to the default values START Start Conversions Description This command starts data conversions If PULSE bit 1 then a single conversion is performed If PULSE bit 0 then conversions continue until the STOP command is sent Tie the START pin
29. TSSOP PW 20 2000 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br ADS1259IPW ACTIVE TSSOP PW 20 70 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br ADS1259IPWR ACTIVE TSSOP PW 20 2000 Green RoHS amp CU NIPDAU Level 1 260C UNLIM no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free proc
30. ata 7 8 8 Read Data command 012h 3 tuppate 20 fc Do not issue the Read Data opcode during this time 4 During this interval DOUT does not follow DRDY stop continuous mode 7 DIN data are latched on the falling edge of SCLK Data are output on the rising edges of SCLK Figure 60 Data Read Operation in STOP Continuous Mode Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com COMMAND DEFINITIONS The commands summarized in Table 19 control and configure the operation of the ADS1259 The commands are stand alone except for the register read and register write operations which require a second command byte plus data CS can be taken high or held low between opcode commands but must stay low for the entire command operation Note that the Read Data Continuous mode must be cancelled by the Stop Read Data Continuous mode opcode SDATAC before sending further commands Table 19 Command Definitions COMMAND TYPE DESCRIPTION FIRST OPCODE BYTE SECOND OPCODE BYTE WAKEUP Control Wake up from SLEEP mode 0000 001x 02h or 03h 2 SLEEP Control Begin SLEEP mode 0000 010x 04h or 05h 2 RESET Control Reset to power up values 0000 011x 06h or 07h 2 START Control START conversion 0000 100x 08h or 09h 2 STOP Control S
31. ata A register value of 00000h has no offset correction default value Note that while the offset calibration register value can correct offsets ranging from FS to FS as Table 11 shows to avoid input overload the analog inputs cannot exceed 105 full scale I TEXAS INSTRUMENTS www ti com Table 11 Offset Calibration Values OFC REGISTER FINAL OUTPUT CODE 7FFFFFh 800001h 000001h FFFFFFh 000000h 000000h FFFFFFh 000001h 800001h 7FFFFFh 1 Ideal output code excluding noise and inherent offset error FSC 2 0 Registers The full scale calibration is a 24 bit word composed of three 8 bit registers as shown in Table 14 The full scale calibration value is 24 bit straight binary normalized to 1 0 at code 400000h Table 12 summarizes the scaling of the full scale register A register value of 400000h default value has no gain correction gain 1 Note that while the gain calibration register value corrects gain errors above 1 gain correction lt 1 the full scale range of the analog inputs cannot exceed 105 full scale to avoid input overload Table 12 Full Scale Calibration Register Values FSC REGISTER GAIN FACTOR 800000h 2 0 400000h 1 0 200000h 0 5 000000h 0 AINP y D igital Modulator AINN OFC Register Output Data Clipped to 24 Bits gt Final Output FSC Register 400000h Figure 54 Calibration Block Diagram
32. away from the ADS1259 In this case connect the grounds at the power supply CONFIGURATION GUIDE Configuration of the ADS1259 involves configuring the device hardware power supply I O pins etc and device register settings The registers are configured by commands sent via the device SPI port Power Supplies The ADS1259 analog section operates either with a single 5V or dual 2 5V supplies The digital section operates from 2 7V to 5V The digital and analog power supplies may be tied together 5V only Reference Select either the internal reference or an external reference for the ADS1259 see the Reference section The default is external reference Figure 63 depicts the internal reference connection Clock Choose the desired clock source see the Clock Source section Figure 63 depicts the internal clock operation Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com SYNCOUT Pin Connect the SYNCOUT pin to the SYNCIN pin of the PGA280 using a 4 7kQ series resistor placed close to the ADS1259 The 1MQ pull down resistor is required when the ADS1259 is in power down mode RESET PWDN Pin This pin must be high in normal operation If it is desired to completely power down the device or to have a hardware reset control then connect this pin to a controller If these fu
33. capacitor between REFOUT and AVSS An internal switch connects the internal reference to REFOUT O Reference Output O CRerout o 2 5 I TEXAS INSTRUMENTS www ti com the ADC reference input pins VREFP and VREFN Note that these device pins are not intended to drive external circuits An external 1tuF capacitor connected from VREFP to VREFN is recommended for noise reduction The capacitor can be increased for increased noise filtering but the settling time of the reference may also increase The settling time should be considered upon activating the internal reference See Figure 29 for typical reference settling Crerin 1uF The capacitor dielectric absorption results in increased settling time for RC filter circuits To activate the internal reference set the register bit RBIAS 1 This enables the reference bias Once biased the internal reference can then be selected as the ADC reference by the register bit EXTREF EXTREF 0 closes the internal switches Reference Bias 4 RBIAS Register Bit 1 Bias On V Reference AVSS Reference Input O gt 1uF T Creen Reference Select a EXTREF Register Bit 1 Switch Open for External Reference ADC Reference Input gt VREFN Figure 37 Reference Block Diagram Table 2 Reference Selection for Figure 37 ADS1259 REFERENCE RBIAS REGISTER BIT EXTREF REGIS
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35. ding of external circuits An onboard oscillator is provided as the clock source for the device Optionally an external crystal can be used As a third clock option the device can be driven by an external clock source SYNCOUT is an output that provides a 1 8 rate clock intended to drive the chopping clock input of the PGA280 Gain and offset registers scale the digital filter output to produce the final code value On command calibration corrects for system offset and gain errors An SPl compatible serial interface provides the control and configuration as well as the data interface to the ADS1259 Onboard registers combined with commands are used to control and configure the device The RESET PWDN pin is dual function A momentary low resets the device and if the pin is held low powers down the device The START pin as well as commands controls the conversions BYPASS DVDD SYNCOUT Calibration Control and Serial Interface Out of Range Detection ADS1259 Figure 31 ADS1259 Block Diagram 12 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com NOISE PERFORMANCE The ADS1259 offers excellent noise performance that can be optimized by adjusting the data rate and by selection of the digital filler mode As the averaging is increased by reducing the data rate the noise drops correspondingly Additionally
36. duration overdrive may not always clip the output code When the input returns to the normal range the modulator requires up to 12 modulator clock cycles fyop to exit saturation and return to the linear region The digital filter requires two additional conversions sinc more for sinc for fully settled data In the extreme case of over range either input is overdriven exceeding that either analog supply voltage plus an internal ESD diode drop The internal ESD diodes begin to conduct and the signal on the input is clipped If the differential input signal range is not exceeded the modulator remains in linear operation If the differential input signal range is exceeded the modulator is saturated but stable and outputs all 1s or Os When the input overdrive is removed the diodes recovery quickly and the 14 Submit Documentation Feedback I TEXAS INSTRUMENTS www ti com ADS1259 recovers as normal Note that the linear input range is 100mV beyond the analog supply voltages with input levels greater than this range use care to limit the input current to 100mA peak transient 10mA continuous INPUT OUT OF RANGE DETECTION FLAG The ADS1259 has a fastresponding out of range circuit that triggers when the differential input exceeds 105 or 105 of FSR 1 05 Vref The out of range circuit latches the result of the comparator output and appends the result as either the LSB of conversion data or as bit 7 of the data check
37. e allows unipolar or bipolar analog power supply configuration AVDD AVSS 5V total The analog supplies may be set to single 45V to accept unipolar or offset bipolar signals or the supplies can be set to 2 5V to accept true bipolar signals The operating range of the digital power supply DVDD is 2 7V to 5V An internal low dropout regulator LDO powers the digital core from the DVDD supply while the device l O operates directly from DVDD BYPASS is the LDO output and requires a 0 1uF or larger capacitor to ground The inherently stable fourth order AZ modulator measures the differential input signal Viy AINP AINN against the differential reference Vper VREFP VREFN A fast responding out of range detector flags the output data if the input should over range while converting VREFP VREFN AX Modulator Programmable Digital Filter Engine The digital filter receives the modulator signal and provides the digital output The filter consists of a fifth order sinc filter followed by a programmable averager selectable as either a sinc or sinc In sinc mode the filter settles in a single conversion The programmable averaging yields output data rates from 10SPS to 14 4kSPS The ADS1259 integrates a low drift low noise 2 5V reference The internal reference can drive loads up to 10mA The ADS1259 also operates from an external reference if desired The reference input is buffered to reduce loa
38. e benefit of wider frequency notches which improve line cycle rejection FREQUENCY RESPONSE The low pass digital filter sets the overall frequency response of the ADS1259 The filter response is the product of the fixed and programmable filter sections and is given by Equation 4 He His f x Haine f 5 dl Sin SIE fork fork x eax sn Rx sin SET fek fork where N 1 sinc N 2 sinc R Decimation ratio refer to Table 3 4 The digital filter attenuates noise on the modulator output including noise from within the ADS1259 and external noise present within the ADS1259 input signal Adjusting the filtering by changing the decimation ratio used in the programmable filter changes the filter bandwidth With a higher number of decimation the bandwidth is reduced and more noise is attenuated x Tu sinc Filter Output Data Rate fc R x 512 SINC2 Register Bit 0 sinc Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com The sinc filter produces wide notches at fo 512 and multiples thereof At these frequencies the filter has zero gain Figure 39 shows the response data rate 14 4kSPS With decimation of the second stage the wide notches produced by the sinc filter remain but a number of narrow notches are superimposed in the response Th
39. e first of the notches occur at the data rate The number of superimposed notches is determined by the decimation ratio minus 1 The second stage filter has notches or zeroes at the data rate and multiples thereof Figure 40 shows the response of the second stage filter combined with the sinc stage Decimation of 4 produces three equally spaced notches between each main notch of the sinc filter The frequency response of the other data rates higher decimation ratios produces a similar pattern but with more equally spaced notches between the main sinc notches Table 4 lists the first notch frequency and the 3dB bandwidth Figure 41 illustrates the detail of the magnitude response with data rate 60SPS Note that input frequencies within the 1 60Hz bandwidth are attenuated 40dB by the sinc filter and 80dB by the sinc filter Table 4 First Notch Frequency and 3dB Filter Bandwidth DATA RATE FIRST NOTCH 99B BANDWIDTH Hz SPS Hz sinc sinc 1000 10 4 3 3 1 16 69 16 6 7 3 5 2 50 50 22 16 60 60 27 19 400 400 177 127 1200 1200 525 380 3600 3600 1440 1100 14400 14400 2930 See 4 fork 7 3728MHz Notch at 50Hz and 60Hz Notch at 50Hz Same as sinc Copyright 2009 2010 Texas Instruments Incorporated o 2 o o 3 2 c o oO Magnitude dB Magnitude dB ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010
40. e new offset or full scale calibration words Figure 55 shows the calibration timing calibration do not send commands During Perform offset calibration prior to the gain calibration Copyright 2009 2010 Texas Instruments Incorporated ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 The internal full scale calibration word is bypassed during offset calibration Do not exceed 105 of full scale range for gain calibration Note that the out of range threshold is unaffected by gain calibration Table 15 Calibration Timing DATA RATE tcan CALIBRATION TIME ms SPS sinc sinc 14400 1 89 2 19 3600 5 43 6 15 1200 14 9 16 7 400 43 2 48 4 60 284 318 50 341 380 16 6 1020 1140 10 1700 1900 1 fork 7 3728MHz DOUT with CS 0 Calibration complete and first data ready CAL Command Figure 55 Calibration Timing Submit Documentation Feedback 27 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 SERIAL INTERFACE The SPl compatible serial interface consists of four signals CS SCLK DIN and DOUT or three signals in which case CS may be tied low The interface is used to read conversion data configure registers and control the ADS1259 operation SERIAL COMMUNICATION The ADS1259 communications occur by clocking commands into the device on DIN and reading register and conversion data on DOUT The SCLK i
41. ed SYNCOUT frequency is equal to the ADS1259 clock rate divided by 8 fsyncout fci 8 The output clock is enabled by the register bit SYNCOUT Disabling the output stops the clock but the output remains actively driven low In power down mode the SYNCOUT output becomes an input As with all digital inputs the pin must not be allowed to float An external 1MQ pull down resistor is recommended to ground the input in power down mode The SYNCOUT clock is reset when START is received and whenever registers CONFIG 2 0 are changed Connect SYNCOUT to the PGA280 SYNCIN pin through a 4 7kQ series resistor Place the resistor as close as possible to the ADS1259 SYNCOUT pin SLEEP MODE SLEEP mode is started by sending the SLEEP command In SLEEP mode the device enters a reduced power state and only a minimum of circuitry is kept active The WAKEUP command exits the SLEEP mode and after which 512 fox cycles are counted before the ADS1259 is ready for communication The register settings are unaffected in SLEEP SLEEP does not change the RBIAS register bit For quick conversions after WAKEUP keep the internal reference bias on before entering SLEEP Otherwise after exiting SLEEP mode allow time for the reference to settle Alternatively to minimize power consumption during SLEEP set the internal reference bias off prior to engaging SLEEP Note that in SLEEP mode the SPI timeout function is disabled BYPASS The digital core of
42. eds of industrial process control precision instrumentation and other exacting applications Combined with a signal amplifier such as the PGA280 a high resolution high accuracy measurement system is formed that is capable of digitizing a wide range of signals The converter uses a fourth order inherently stable delta sigma AZ modulator that provides outstanding noise and linearity performance The data rates are programmable up to 14kSPS including 10SPS 50SPS and 60SPS that provide excellent normal mode line cycle rejection The digital filter can be programmed for a fast settling mode where the conversions settle in a single cycle or programmed for a high line cycle rejection mode A fast responding input over range detector flags the conversion data if an input over range should occur The ADS1259 also provides an integrated low noise very low drift 2 5V reference The on chip oscillator an external crystal or an external clock can by used as the ADC clock source Data and control communication are handled over a 4MHz SPl compatible interface capable of operating with a minimum of three wires Data integrity is augmented by data bytes checksum and redundant data read capability Conversions are synchronized either by command or by pin Dissipating only 13mW in operation the ADS1259 can be powered down dissipating less than 25uW The ADS1259 is offered in a TSSOP 20 package and is fully specified from 40 C to 105
43. ere is a step change on the input signal while continuously converting the next data represent a combination of the previous and current input signal and should therefore be discarded see Figure 53 for this step change Table 10 shows the number of conversion cycles for completely settled data while continuously converting Table 10 Settling Time While Continuously Converting DRDY Periods DATA RATE SETTLING TIME tse7 Conversions SPS sinc sinc 10 2 3 16 6 2 3 50 2 3 60 2 3 400 2 3 1200 2 3 3600 3 4 14 400 6 7 1 Settling time is defined as the number of DRDY periods after the input signal has settled following an input step change For best data throughput in multiplexed applications issue a START condition START pin or Start command after the input has settled following a multiplexer change see the Setling Time Using START section Vi AINP AINN Old Vin 4 Old V Data DRDY DOUT SEN PR ES ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 OFFSET AND GAIN The ADS1259 features low offset 40uV typ and low gain errors 0 05 typ The offset and gain errors can be corrected by sending calibration commands to the ADS1259 see the Calibration section The ADS1259 also features very low offset drift 0 05uV C typ and very low gain drift 0 5ppm C typ The offset and gain drift are calculated using the box method as described by Equat
44. esses Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total
45. hes from accidentally shifting the data If SCLK is held low for 2 8 fox periods the serial interface resets After reset the next communication cycle can be started The timeout can be used to recover communication when the serial interface is interrupted The SPI timeout is enabled by register bit SPI When the serial interface is idle hold SCLK low 28 Submit Documentation Feedback I TEXAS INSTRUMENTS www ti com DATA INPUT DIN DIN is the input data pin and is used with SCLK to send data to the ADS1259 opcode commands and register data The device latches input data on the falling edge of SCLK DATA OUTPUT DOUT DOUT is the output data pin and is used with SCLK to read conversion and register data from the ADS1259 In addition to providing data output in RDATAC mode DOUT indicates when data are ready Data are ready when DOUT transitions low In this manner DOUT functions the same as DRDY with CS 0 as shown in Faure 56 When reading data the data are shifted out on the rising edge of SCLK DOUT is in a 3 state condition when CS is high DATA READY DRDY DRDY is an output that indicates when conversion data_are available for reading falling edge active DRDY is asserted on_an output pin and also a register bit To poll the DRDY register bit set the stop read data continuous mode_and then read the CONFIG2 register When the DRDY bit is low data can be read The data read operation must complete withi
46. igital power supply REFOUT 16 Analog output Positive reference output VREFP 17 Analog input Positive reference input VREFN 18 Analog input Negative reference input AVSS 19 Analog Negative analog power supply and negative reference output AVDD 20 Analog Positive analog power supply Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com SPI TIMING CHARACTERISTICS tscuk tspwH SCLK DIN DOUT Figure 1 Serial Interface Timing TIMING REQUIREMENTS SERIAL INTERFACE TIMING At T4 40 C to 105 C and DVDD 2 7V to 5 25V unless otherwise noted SYMBOL DESCRIPTION MIN MAX UNIT tcssc CS low to first SCLK setup time 50 ns tscLk SCLK period 1 8 tork P tspwH SCLK pulse width high 90 ns 3 90 ns tspwe SCLK pulse width low 9 3 2 toLk tpisT Valid DIN to SCLK falling edge setup time 35 ns tbiuD Valid DIN to SCLK falling edge hold time 20 ns tpopp SCLK rising edge to valid new DOUT propagation delay 60 ns tpoHp SCLK rising edge to DOUT invalid hold time 0 ns tcspop CS low to DOUT driven propagation delay 0 40 ns tcspoz CS high to DOUT Hi Z propagation delay 20 ns lcsH CS high pulse 20 toLk 1 CS can be tied low 2 terk 1 feik 3 Holding SCLK low longer than 218 x tci cycles rese
47. ion 5 and Equation 6 Offset Drift Voremax 2 Vorrei Temp Range 5 GainErrory y QainError mn Gain Drift Temp Range where VorrMAx Voremin GainErroryax and GainErroryiny are the maximum and minimum offset and gain error readings recorded over the Temp Range 40 C to 105 C 6 Mix of Old and New Vin Data Fully Settled New Vy Data Settled Data Figure 53 Step Change on Vy while Continuously Converting Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 OFFSET AND FULL SCALE CALIBRATION REGISTERS The conversion data are scaled by offset and gain registers before yielding the final output code As shown in Figure 54 the output of the digital filter is first subtracted by the offset register OFC and then multiplied by the full scale register FSC Equation 7 shows the scaling Final Output Data Input OFC 2 0 x Tauno 400000h 7 The values of the offset and full scale registers are set by writing to them directly or they are set by calibration commands OFC 2 0 Registers The offset calibration is a 24 bit word composed of three 8 bit registers as shown in Table 13 The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h This value is subtracted from the conversion d
48. ly Full dynamic range is achieved when the inputs are differentially driven Vgge As a result of the switched capacitor input structure of the ADS1259 a buffer is recommended to drive the analog inputs An input filter comprised of 200 to 500 resistors and 10nF capacitors should be used between the buffer and the ADS1259 inputs fmon 0 9216MHz AVSS 2 5V 9 Rere A 500kO AINP O 4 Ree e 130k AINN O 4 Reg a 500kQ Equivalent Circuit O AVSS 2 5V MODE Rowe Fiere B 2Rerr a 120kO Room Refr a 500k2 Figure 36 Simplified ADC Input Structure Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 REFERENCE The ADS1259 includes an onboard voltage reference with a low temperature coefficient The reference voltage is 2 5V with the capability of sinking and sourcing 10mA via the REFOUT pin The ADS1259 can also operate from an external reference The external reference is the default selection Refer to Figure 37 for a reference block diagram Internal Reference The reference output is provided between pins REFOUT and AVSS Because the reference output return shares the same pin as AVSS route the reference return trace and the AVSS trace independently as Kelvin connected printed circuit board PCB traces For stability reasons connect a 1uF
49. m is at its highest When the level of the differential analog input is near zero the PCM Os and 1s densities are nearly equal At the two extremes of the analog input levels FS and FS the 1s density of the PCM streams are approximately 90 and 4 109256 respectively The modulator second stage produces a 1s density data stream designed to cancel the quantization noise of the first stage The data streams of the two stages are then combined in the digital filter stage Table 1 Typical Noise Data vs Data Rate and Digital Filter DATA SINC DIGITAL FILTER SINC DIGITAL FILTER RATE SAMPLE NOISE NOISE ENOB NOISE NOISE NOISE ENOB NOISE SPS SIZE uVams uVpp RMS FREEBITS uVams uVpp RMS FREE BITS 10 128 0 5 1 8 23 3 21 4 0 45 1 6 23 4 21 6 16 6 256 0 55 2 4 23 1 21 0 0 5 2 23 3 21 3 50 512 0 65 3 5 22 9 20 4 0 6 3 23 0 20 7 60 512 0 7 4 22 8 20 3 0 65 3 5 22 9 20 4 400 4096 1 4 9 5 21 8 19 0 1 2 8 3 22 0 19 2 1200 8192 2 8 17 21 1 18 2 2 14 21 3 18 4 3600 8192 3 9 32 20 3 17 8 3 4 27 20 5 17 5 14400 8192 6 2 50 19 6 16 6 3 3 3 3 1 Noise data taken with shorted analog inputs and internal 2 5V reference using the circuit of Figure 63 2 Data sample sizes used for analysis 3 Same as sinc mode Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s ADS1259 ADS1259
50. n 20 fci cycles of the next DRDY falling edge After power on or after reset DRDY defaults high When reading data in Gate Control mode DRDY is reset high on the first SCLK rising edge If data are not retrieved DRDY pulses high during the new data update time as shown in F9 56 Do not retrieve data during this time as the data are invalid In Pulse Control mode DRDY remains low until a new conversion is started The previous conversion data may be read 20 tc prior to the DRDY falling edge 20t o Data Updating l x BEDV pi 00 DRDY Pin 4 1 DOUT functions in the same manner as the DRDY pin if CS is low and in the RDATAC mode 2 The DRDY bit functions in the same manner as the DRDY pin SDATAC mode only Figure 56 DRDY and DOUT With No Data Retrieval Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com DATA FORMAT The ADS1259 outputs 24 bits of conversion data in binary twos complement format MSB first The data LSB has a weight of Vggp 2 1 A positive full scale input produces an output code of 7FFFFFh and the negative full scale input produces an output code of 800000h The output clips at these codes for signals that exceed full scale 9le 16 summarizes the ideal output codes for different input signals Table 16 Ideal Output Code versus Input Signal
51. n the conversion is complete DRDY goes low and further conversions are halted To start a new conversion transition the START pin back to high or transmit the START opcode again START Pin f oR oR START STARTY Single Single Halted Conversion Halted Conversion DRDY 1 START opcode command takes effect on the seventh SCLK falling edge Figure 51 Pulse Control Mode CONVERSION SETTLING TIME The ADS1259 features a digital filter architecture in which settling time can be traded for wide filter notches resulting in improved line cycle rejection This trade off is determined by the selection of the sinc or sinc filter The sinc filter settles in a single cycle while the sinc filter provides wide width filter notches The settling time of the ADS1259 is different if START is used to begin conversions or if the ADS1259 is free running the conversions These modes are explained in the Settling Time Using START and Settling Time While Continuously Converting sections Vin AINP AINN m N Settled Viy START Pin 7th Falling SCLK Edge of Opcode x START Command DRDY Settled Data 1 tser initial start delay plus the new conversion cycle time Figure 52 Data Retrieval Time After START 24 Submit Documentation Feedback I TEXAS INSTRUMENTS www ti com Settling Time Using START When START goes high via pin or command a delay may be programmed before the conversion
52. nctions are not needed tie the pin high Note that the device can both be reset and SLEEP mode engaged by commands START Pin If it is desired to control conversions by pin connect this line to the controller Otherwise this line can be tied high to free run conversions The conversions can also be controlled by software commands In this case tie the START pin low DRDY Pin DRDY is an output that indicates when data are ready for readback Note that the DOUT pin and also the DRDY register bit indicates when data are ready as well so DRDY connection to a controller is optional CS Pin If the ADS1259 is a single device connected to the SPI bus then CS can be tied low Otherwise for applications where the ADS1259 shares the bus with another device CS must be connected DOUT Pin When the ADS1259 SPI is deselected CS 1 the DOUT pin is in 3 state mode A pull down resistor may be necessary to prevent floating the controller input pin Miscellaneous Digital I O Avoid ringing on the digital inputs and outputs Resistors in series with the trace driving end helps to reduce ringing by controlling impedances SOFTWARE GUIDE After the power supplies have fully established allow a minimum of 2 9 system clocks before beginning communication to the device The registers can then be configured by commands via the SPI port The following steps detail a suggested procedure to initialize the ADS1259 1 Send the SDATAC comma
53. nd lt 11h gt This command cancels the RDATAC mode RDATAC mode must be cancelled before the register write commands 2 Send the register write command The following example shows the register write as a block of nine bytes starting at register 0 CONFIGO BYTES DATA OPERATION 1 2 01000000 00001000 Write register opcode bytes starting at address 0 9 byte block 3 00000101 CONFIGO register data bias the reference SPI timeout 4 01010000 CONFIG1 checksum enabled sinc filter selection internal reference 5 0000001 1 CONFIG2 Gate Convert mode 60SPS 6 7 8 00000000 00000000 OFC 2 0 3 bytes for offset no offset correction 00000000 9 10 11 00000000 00000000 FSC 2 0 3 bytes for gain no full scale correction 01000000 40 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 3 Optional readback verification of the register data READ register command 20h lt 08 gt The nine bytes of readback data that follow represent the nine register bytes 4 Take the START pin high or send the START command to start conversions 5 Optionally send the RDATAC command 10h This permits reading of conversion data without the need of the read data command Otherwise the read data opcode must be sent to read each conversion result 6 When the DRDY pin or the DRDY bit goes low or
54. ng of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Re
55. nput is used to clock the data into and out of the device CS disables the ADS1259 serial port but otherwise does not affect the ADC operation The communication protocol to the ADS1259_ is half duplex That is data are transmitted to and from the device one direction at a time Communications to and from the ADS1259 occurs on 8 bit boundaries If an unintentional SCLK transition should occur such as from a possible noise spike the ADS1259 serial port may not respond properly The port can be reset by one of the following ways 1 Take CS high and then low to reset the interface 2 Hold SCLK low for 2 fci cycles to reset the interface 3 Take RESET PWDN low and back high to overall reset the device 4 Cycle the power supplies to overall reset the device CHIP SELECT CS The chip select CS selects the ADS1259 for SPI communication To select the device pull CS low CS must remain low for the duration of the serial communication When CS is taken high the serial interface is reset input commands are ignored and DOUT enters a high impedance state If the ADS1259 does not share the serial bus with another device CS may be tied low Note that DRDY remains active when CS is high SERIAL CLOCK SCLK The serial clock SCLK is a Schmitt triggered input used to clock data into and out of the ADS1259 Even though the input is relatively noise immune it is recommended to keep SCLK as clean as possible to prevent glitc
56. ns begin when either the START pin is taken high or when the START command is sent Conversions continue indefinitely until the START pin is taken low or the STOP command is transmitted As seen in Figure 50 DRDY is forced high when the conversion starts and falls low when data are ready When stopped the conversion in process completes and further conversions are halted Figure 49 and Table 7 show the timing of DRDY and START START Pin or l or Halted Converting Halted DRDY 1 START and STOP opcode commands take effect on the seventh SCLK falling edge Figure 50 Gate Control Mode Table 7 START Timing See Figure 49 SYMBOL DESCRIPTION MIN MAX UNIT START pin low or STOP opcode to DRDY setup time to halt further spsu conversions 16 tok t START pin low or STOP opcode hold time to complete current 16 t DSHD conversion gate mode CLK tpwu L START pin pulse width high low 4 tcik STDR START pin rising edge to DRDY rising edge 4 toLk Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 Pulse Control Mode PULSE Bit 1 In the Pulse Control mode the ADS1259 performs a single conversion when either the START pin is taken high or when the START command is sent As seen in Figure 51 DRDY goes high when the conversion is started Whe
57. om Data Read Operation in Stop Continuous Mode In Stop Read Data Continuous mode a read data command RDATA must be sent for each new data read operation New conversion data are ready when DRDY falls low or the DRDY register bit transitions low The data read operation may then occur The read data command must be sent at least 20 fci cycles before the DRDY falling edge or the data are incorrect Do not the read data command during this time Data Ready ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 As shown in Figure 60 after sending the RDATA command the data are shifted out on DOUT on the rising edges of SCLK The MSB is clocked out on the first rising edge of SCLK In Gate Control mode DRDY returns to high on the first falling edge of SCLK In Pulse Control mode DRDY remains low until a new conversion is started The conversion data consist of three or four bytes MSB first depending on whether the checksum byte is included The data may be read multiple times by continuing to shift the data Next Data Ready 3 e tuppare 1 In Gate Control mode DRDY returns to high on the first falling edge of SCLK In Pulse Control mode DRDY remains low until the next conversion is started The DRDY pin or DRDY register bit can also be polled to determine when data are ready 2 CS may be held low 3 4 5 Optional conversion data checksum 6 Optional repeat of previous conversion d
58. ommunication start 216 terk AVDD avss 3 5V nom DVDD 2 1V nom e 2 xta Internal Reset ADS1259 Operational Figure 48 Power On Sequence 22 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com START START is a digital input that controls the ADS1259 conversions Conversions are started when START is taken high and are stopped when START is taken low If START is toggled during a conversion the conversion is restarted DRDY goes high when START is taken high Figure 49 andTable 7 show the START timing Note that reasserting START within 22 tc cycles of the DRDY falling edge causes DRDY to fall soon after This conversion result should be discarded The next DRDY falling edge as given in Table 9 is the valid conversion data 1 START and STOP commands take effect on the seventh SCLK falling edge Figure 49 START to DRDY Timing CONVERSION CONTROL The conversions of the ADS1259 are controlled by either the START pin or by the START command ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 When using commands to control conversions hold the START pin low The ADS1259 features two modes to control conversions Gate Control mode and Pulse Control mode The mode is selected by the PULSE register bit Gate Control Mode PULSE Bit 0 Default Conversio
59. ons www ti com Ilprf Video and Imaging www ti com video Wireless www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2010 Texas Instruments Incorporated
60. or an external clock or an external crystal ceramic resonator The ADS1259 selects the clock source automatically Figure 43 shows the clock select block If either external clock sources are present the internal oscillator is disabled and the external clock source is selected If no external clock is present the internal oscillator is selected The ADS1259 continuously monitors the clock source The clock source can be polled by the EXTCLK bit bit 6 of register CONFIG2 0 internal oscillator 1 external clock The data rate and corresponding filter notches scale by the accuracy of clock frequency Consideration should be given to the clock accuracy and the corresponding effect to the notch frequency locations Clock Detect Internal Oscillator System Clock XTAL1 CLKIN Figure 43 Equivalent Circuitry of the Clock Source Internal Oscillator Figure 44 shows the internal oscillator connection XTAL1 CLKIN is grounded and XTAL2 is not connected floating The internal oscillator draws approximately 40uA from the DVDD supply Note that the internal oscillator has 2 accuracy over temperature The oscillator accuracy has a corresponding effect on line cycle notch frequency locations XTAL1 CLKIN Figure 44 Internal Oscillator Connection Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com External Clock Figure 45
61. purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 20 Jul 2010 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Reel Diameter Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPQ Reel Reel AO BO KO P1 Ww Pint ADS1259BIPWR TSSOP PW 20 2000 330 0 16 4 6 95 7 1 1 6 8 0 16 0 Q1 ADS1259IPWR TSSOP PW 20 2000 330 0 16 4 6 95 7 1 1 6 8 0 16 0 Q1 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 20 Jul 2010 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS1259BIPWR TSSOP PW 20 2000 346 0 346 0 33 0 ADS1259IPWR TSSOP PW 20 2000 346 0 346 0 33 0 Pack Materials Page 2 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PINS SHOWN
62. pyright 2009 2010 Texas Instruments Incorporated ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 For external reference applications place a 1puF minimum capacitor close to the VREFP and VREFN pins Because the ADS1259 measures the signal inputs AINP and AINN against the reference inputs VREFP and VREFN reference noise and drift may degrade overall system performance In ratiometric measurement applications reference noise and drift have a cancelling effect In absolute measurement applications reference noise and drift directly effect the conversion results Voltage Reference Inputs VREFP VREFN ESD diodes protect the reference inputs To keep these diodes from turning on make sure the voltages on the reference pins do not go below AVSS by more than 300mV and likewise do not exceed AVDD by more than 300mV The absolute maximum reference input range is AVSS 300mV lt VREFP or VREFN lt AVDD 300mV 3 Note that the valid operating range of the reference inputs are shown in the Electrical Characteristics table Submit Documentation Feedback 17 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 DIGITAL FILTER The programmable low pass digital filter receives the modulator output and produces a high resolution digital output By adjusting the amount of filtering tradeoffs can be made between resolution and data rate filter more for higher resolution filter
63. rns to high on the first falling edge of SCLK In Pulse Convert mode DRDY remains low until a new conversion starts As shown in Figure 59 the conversion data consist of three or four bytes data MSB first depending on whether the checksum byte is included The data may be read multiple times by continuing to shift the data The data read operation must be completed with 20 fci cycles of next DRDY falling edge Data Ready I TEXAS INSTRUMENTS www ti com The Read Data Continuous mode is cancelled by sending the Stop Read Data Continuous command SDATAC This operation occurs simultaneously with ADC conversion data on DOUT which can be ignored Once the SDATAC command is sent other commands may be sent to the ADS1259 Observe the SCLK and DRDY timing requirements when reading data in this mode as shown in Figure 58 and Table 18 Figure 58 SCLK to DRDY Timing Table 18 SCLK and DRDY Timing Characteristics for Figure 57 SYMBOL DESCRIPTION MIN UNIT tscpr SCLK low before DRDY SCDR low 20 terk torsc DRDY falling edge to SCLK rising edge 20 ns 1 These requirements apply only to reading conversion data in RDATAC mode Next Data Ready 4 luPparE Figure 59 Data Read Operation in Continuous Mode 30 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti c
64. roduct Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com REVISION HISTORY NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Revision B January 2010 to Revision C Page e Changed ADS1259B and ADS1259 Internal Voltage Reference Accuracy parameter in the Electrical CM ANACTOHISUCS ME nwwwwwnw0 3 Changed ADS1259 Internal Voltage Reference Temperature drift parameter in the Electrical Characteristics 3 Added Figure 23 ADS1259 internal reference voltage versus temperature graph seen 10 Added PGA280 Application section sessi ennet rennen rak eisa nonk sA aS EPEa EE en nnn 41 Changes from Revision A December 2009 to Revision B Page Updated description of out of range flag in Input Out Of Range Detection FLAG section sss 14 42 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 ip TEXAS PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 17 Mar 2010 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty ADS1259BIPW ACTIVE TSSOP PW 20 70 Green RoHS amp CUNIPDAU Level 1 260C UNLIM no Sb Br ADS1259BIPWR ACTIVE
65. s the starting register address Second opcode byte 0000 nnnn where nnnn is the number of registers to read The 17th SCLK rising edge of the operation clocks out the MSB of the first register 1 CS may be tied low Figure 61 RREG Command Example Read Two Registers Starting from Register 00h CONFIGO OPCODE 1 0010 0000 OPCODE 2 0000 0001 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS SBAS424C JUNE 2009 REVISED MARCH 2010 www ti com WREG Write to Register Description These two opcode bytes write register data The Register Write command is a two byte opcode followed by the register data The first byte contains the command opcode and the register address The second byte of the opcode specifies the number of registers to write 1 First opcode byte 0100 rrrr where rrrr is the starting register address Second opcode byte 0000 nnnn where nnnn is the number of registers to write After the opcode bytes the register data follows in MSB first format 1 CS may be tied low Figure 62 WREG Command Example Write Two Registers Starting from 00h CONFIGO OPCODE 1 0100 0000 OPCODE 2 0000 0001 OFSCAL Offset Calibration Description This command performs an offset calibration Apply a zero signal and allow the input to stabilize before sending the command see the Calibration section for more
66. sale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers a
67. shows the external clock connection The clock is applied to XTAL1 CLKIN and XTAL2 floats Make sure a clean clock input is applied to the ADS1259 free of overshoot and glitches A series resistor often helps to reduce overshoot and should be placed close to the driving end of the clock source Q XTAL1 CLKIN Figure 45 External Clock Connection Crystal Oscillator Figure 46 shows the crystal oscillator connection The crystal connects to XTAL1 CLKIN and XTAL2 and the capacitors connect to ground The crystal and capacitors should be placed close to the device pins with short direct traces Neither the XTAL1 CLKIN nor the XTAL2 pins can be used to drive any other logic Table 5 lists the recommended crystal for the ADS1259 If using other crystals verify the oscillator start up behavior XTAL1 CLKIN Crystal 7 3728MHz C4 Cy 5pF to 20pF Figure 46 Crystal Connection Table 5 Recommended Crystal MANUFACTURER FREQUENCY PART NUMBER ECS 7 3728MHz ECS 73 18 10 Copyright 2009 2010 Texas Instruments Incorporated ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 SYNCOUT SYNCOUT is a digital output pin intended to synchronize the chopping frequency of the PGA280 to the sampling frequency of the ADS1259 Synchronizing the PGA280 to the ADS1259 places the PGA280 chopped 1 f noise at an exact null in the ADS1259 frequency response where the PGA280 1 f noise is reject
68. sum byte After the conversion data are read or after a new conversion is started the comparator latch is reset Figure 33 and Figure 34 show the detection block diagram and the detection operation respectively See the Data Checksum Byte and FLAG Bit section for more detail fuop 2 O Data Read Reset Figure 33 Input Out Of Range Detect Block Diagram Conversions AINP AINN 96 Vie Figure 34 Input Out Of Range Detect Operation Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 I TEXAS INSTRUMENTS www ti com ANALOG INPUTS AINP AINN The ADS1259 measures the differential input signal Vin AINP AINN against the differential reference Vrer VREFP VREFN using internal capacitors that are continuously charged and discharged Figure 36 shows the simplified schematic of the ADC input circuitry the right side of the figure illustrates the input circuitry with the capacitors and switches replaced by an equivalent circuit Figure 35 demonstrates the ON OFF timings for the switches of Figure 36 In Figure 36 S switches close during the input sampling phase With switch S4 closed Ca charges to AINP Caz charges to AINN and Cg charges to AINP AINN For the discharge phase S opens first and then S closes Ca and C4 discharge to approximately to AVSS 2 5V and Cg discharges to OV This two phase sample discharge cycle repea
69. t momentary 100 100 mA Input current continuous 10 10 mA Analog input voltage to DGND AVSS 0 3 AVDD 0 3 V Digital input voltage to DGND 0 3 DVDD 0 3 V Maximum junction temperature 150 C Operating temperature range 40 125 C Storage temperature range 60 150 C 1 Stresses above these ratings may cause permanent damage Exposure to absolute maximum conditions for extended periods may degrade device reliability These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied 2 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 ADS1259 I TEXAS INSTRUMENTS www ti com SBAS424C JUNE 2009 REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS Minimum maximum specifications are at Ta 40 C to 105 C Typical specifications are at T4 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V fci 7 3728MHZz Vref 2 5V and fpata 60SPS unless otherwise noted ADS1259 ADS1259B PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT ANALOG INPUTS Full scale input voltage range FSR Vin AINP AINN VREF VREF V vA Akh BORE AVSS 0 1 AVDD 0 1 AVSS 0 1 AVDD 0 1 v Differential input impedance 120 120 kQ Common mode input impedance 500 500 kQ SYST
70. the ADS1259 is powered by an internal low dropout regulator LDO The DVDD supply is the LDO input and the BYPASS pin is the LDO output A 1uF capacitor must be connected from the LDO output to DGND No other load current should be drawn from the BYPASS pin Submit Documentation Feedback 21 Product Folder Link s ADS1259 ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 RESET PWDN The RESET PWDN pin has two functions device power down and device reset Momentarily holding the pin low resets the device and holding the pin low for 2 fox cycles activates the Power Down mode POWER DOWN MODE In power down mode internal circuit blocks are disabled including the oscillator reference and SPI and the device enters a micro power state To engage power down mode hold the RESET PWDN pin low for 2 9 fci cycles Note that the register contents are not saved because they are reset when RESET PWDN goes high Keep the digital inputs at defined Vi or Vin logic levels do not 3 state To minimize power supply leakage current disable the external clock Note that the ADS1259 digital outputs remain active in power down The analog signal inputs may float To exit power down take RESET PWDN high Wait 216 fo cycles before communicating to the ADS1259 as shown in Figure 47 RESET PWDN Figure 47 RESET PWDN Timing I TEXAS INSTRUMENTS www ti com RESET There are three methods to reset the ADS1259 c
71. ts with a period of tsaypte 1 fuop fmon is the operating frequency of the modulator where fmon fc 8 The charging of the input sampling capacitors draws a transient current from the source driving the ADS1259 ADC inputs The average value of this current can be used to calculate an effective impedance Rep where Repr Vin laverace These impedances scale inversely with fyop For example if fuop is reduced by a factor of two the impedances double Note that the sampling capacitors can vary 15 over production lots and typically vary 1 with temperature The variations of the sampling capacitors have a corresponding effect on the analog input impedance AVSS 2 5V j A ESD Diodes o S S O ESD Diodes S AVSS 2 5V ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 ESD diodes protect the analog inputs To keep these diodes from turning on make sure the voltages on the input pins do not go below AVSS by more than 300mV and likewise do not exceed AVDD by more than 300mV AVSS 300mV lt AINP or AINN lt AVDD 300mV Note that the valid input range is AVSS 100mV lt AINP or AINN lt AVDD 100mV I tsaupLE 1 fmop E A cu Perr and fyon foix 8 Figure 35 S and S Switch Timing for Figure 36 Although optimized for differential signals the ADS1259 inputs may be driven with a single ended signal by fixing one input to AVSS or mid supp
72. ts the SPI interface enabled by SPI register bit 4 DOUT load 20pF 100kO to DGND 6 Submit Documentation Feedback Copyright 2009 2010 Texas Instruments Incorporated Product Folder Link s ADS1259 l TEXAS INSTRUMENTS www ti com ADS1259 SBAS424C JUNE 2009 REVISED MARCH 2010 TYPICAL CHARACTERISTICS At T 25 C AVDD 2 5V AVSS 2 5V DVDD 3 3V Vae 2 5V VREFN AVSS foy 7 3728MHz and DATA NOISE DISTRIBUTION HISTOGRAM 60SPS unless otherwise noted NOISE DISTRIBUTION HISTOGRAM 200 160 Data Rate 10SPS Data Rate 60SPS 180 F Shorted Input 140 Shorted Input 160 512 Samples 512 Samples 120 140 9 120 100 i 100 80 3 3 8 80 6 60 60 40 40 20 20 0 0 Reading uV Reading uV Figure 2 Figure 3 NOISE DISTRIBUTION HISTOGRAM NOISE DISTRIBUTION HISTOGRAM Data Rate 400SPS Data Rate 14 4kSPS Shorted Input Shorted Input 4096 Samples 4096 Samples 8 8 t g g 5 5 8 8 o o Onounonounounooinoiuonoduotduoo 10 CN Q rPl 10 QN O nr 10 QN CN 10 PI O QI 10 P QO CO 10 n Sd ee SO S A Reading uV Reading uV Figure 4 Figure 5 EFFECTIVE NUMBER OF BITS vs TEMPERATURE EFFECTIVE NUMBER OF BITS HISTOGRAM 25 Data Rate 60SPS Data Rate 10SPS 24 23 g 3 E Data Rate e m 22 2 8 21 o 20 1
73. when DOUT transitions low read the data PGA280 APPLICATION Figure 64 shows the ADS1259 connected to the PGA280 The PGA280 is a programmable gain fully differential instrumentation amplifier that is ideally suited to drive the ADS1259 The amplifier features 5V to 18V supply input section that accepts wide ranging signal levels and features a 5V output section that matches the ADS1259 low voltage inputs The ADS1259 2 5V REFOUT drives the PGA280 VOCM pin to level shift the signal The ADS1259 provides a clock output SYNCOUT that drives the PGA280 GPIO6 chopping clock input An optional extended CS ECS function feature of the PGA280 GPIOO allows use of one CS to alternately select each device for SPI communication Additionally the optional BUFA trigger output of the PGA280 GPIO5 starts the ADS1259 conversions The trigger can be delayed to occur after an input multiplexer change The delay allows settling of the PGA280 before the ADC conversion begins 15V 15V Q O AVDD VREFP VREFN RESET PWDN 8 DIN Controller 1 Refer to the PGA280 product data sheet for power supply bypassing recommendations 2 Locate this resistor as close as possible to pin 5 of the ADS1259 3 COG or film capacitor Figure 64 PGA280 Driving the ADS1259 Copyright 2009 2010 Texas Instruments Incorporated Submit Documentation Feedback 41 P
74. ycle the power supplies take RESET PWDN low or send the RESET opcode command When using the RESET PWDN pin take it low to force a reset Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high The RESET command takes effect on the eighth falling SCLK edge of the opcode command On reset the configuration registers are initialized to the default states and the conversion cycle restarts After reset allow eight fc cycles before communicating to the ADS1259 Note that when using the reset command the SPI interface itself may require reset before accepting the command See the SPI Timing Characteristics section for details POWER ON SEQUENCE The ADS1259 has three power supplies AVDD AVSS and DVDD The supplies can be sequenced in any order but be sure that at any time the analog inputs do not exceed AVDD or AVSS and the digital inputs do not exceed DVDD After the last power supply has crossed the respective power on threshold 2 fox cycles are counted before releasing the internal reset After the internal reset is released the ADS1259 is ready for operation Figure 48 shows the power on sequence of the ADS1259 Table 6 Timing Characteristics for Figure 47 SYMBOL DESCRIPTION MIN UNIT tiow Pulse width low for reset 4 tcik tlow Pulse width low for power down 216 telk tRHSC Reset high to SPI communication start 8 toLk taHsc Exit power down to SPI c

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