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LINEAR TECHNOLOGY LTC2499 handbook

1. 55 30 5 20 45 70 TEMPERATURE C 95 120 2499 F05 Figure 5 Absolute Temperature Error 2499fa 19 LIC2499 APPLICATIONS INFORMATION Initiating a New Conversion When the LTC2499 finishes a conversion it automatically enters the sleep state Once in the sleep state the device is ready for a read operation After the device acknowledges a read request the device exits the sleep state and enters the data output state The data output state concludes and the LTC2499 starts a new conversion once a Stop condition is issued by the master or all 32 bits of data are read out of the device During the data read cycle a Stop command may be issued by the master controller in order to start a new conversion and abort the data transfer This Stop command must be issued during the ninth clock cycle of a byte read when the bus is free the ACK NAK cycle LTC2499 Address The LTC2499 has three address pins CAO CA1 CA2 Each may be tied high low or left floating enabling one of 27 possible addresses see Table 5 In addition to the configurable addresses listed in Table 5 the LTC2499 also contains a global address 1110111 which may be used for synchronizing multiple LTC2499s or other LTC24XX delta sigma 126 devices see Synchronizing Multiple 17024995 with a Global Address Call section Operation Sequence The LTC2499 acts as a transmitter or receiver as shown in Figure 6 The devic
2. RMS NOISE e 04 25 2 15 1 050 05 1 15 2 25 INPUT DIFFERENTIAL VOLTAGE V 2499 610 RMS Noise vs Vec 2 5V Vin OV GND TA 25 Fo GND a o d RMS NOISE uV N e o 2499 613 Offset Error vs Temperature o an Lk OFFSET ERROR ppm of Veer e 745 40 15 0 15 30 45 60 75 90 TEMPERATURE C 2499 G16 RMS NOISE uV RMS NOISE uV OFFSET ERROR ppm of Vere RMS Noise vs Vin cm Vec 5V VREF 5V Vin OV TA 25 C Fo GND e V 2499 611 RMS Noise vs Vper e A e a 4 2499 G14 REF 2 5V REF GND Vin OV GND Ty 25 C Fo GND 39 43 47 54 55 Vcc V 3 27 31 3 5 2499 G17 RMS Noise vs Temperature Ta Vec 5V VREF 5V Vin OV Vin cm GND Fo GND e RMS NOISE uV e o 0 4 45 30 15 0 15 30 45 60 75 90 TEMPER
3. TEMPERATURE C 15 30 45 60 75 90 2499 633 2499fa LI MYR 9 LIC2499 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error vs Vec Offset Error vs VREF PSRR vs Frequency at Vcc 2x Speed Mode 2x Speed Mode 2x Speed Mode 250 240 0 2 5V Voc 5V Voc 4 1V DC Vin OV 230 Vin OV 2201 REF 2 5V 200 Vin cm GND GND REF GND Fo GND 220 Fo GND IN GND TA 25 C TA 25 C 40 IN GND Fo GND 150 60 Ta 25 C REJECTION dB OFFSET ERROR uV OFFSET ERROR uV 2 2 5 3 3 5 4 45 5 5 5 Voc V 2499 G34 PSRR vs Frequency at Vec 2x Speed Mode Vec 4 1V DC 1 4V 2 5V REF GND IN GND IN GND Fo GND TA 25 C RREJECTION dB 140 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT Vcc Hz 2499 G37 10 100 1k 10k FREQUENCY AT Hz 100k 1 2499 G35 2499 G36 PSRR vs Frequency at Vcc 2x Speed Mode Vec 4 1V DC 0 7V 2 5V REF GND IN GND IN GND Fo GND TA 25 C REJECTION dB 140 30600 30650 30700 30750 FREQUENCY AT Vcc Hz 30800 2499 G38 PIN FUNCTIONS GND Pins 1 4 6 31 32 33 34 Ground Multiple ground pins internally connected
4. Crer 0 01uF Crer 1uF 10uF Vec 5V Crer VREF 9V 1 25V 400 y 3 75V Fo GND 25 C 0 200 400 600 800 1000 Rsource 2 FS ERROR ppm 2499 F16 Figure 16 FS Error vs Rsource at Vger Large Crer 2499fa LI We 25 LIC2499 APPLICATIONS INFORMATION Vec 5V 8 Vngr 5V Vin cm 2 5 R 1k 6 T4 25 4 CREF 10uF 2 0 INL ppm OF VREF 0 5 0 3 0 1 0 1 0 3 0 5 Vin REF 2499 F17 Figure 17 INL vs Differential Input Voltage and Reference Source Resistance for Crer gt 1 the reference common mode voltage a linearity error of approximately 0 67ppm per 1000 of reference resistance results see Figure 17 In applications where the input and reference common mode voltages are different the errors increase A 1V difference in between common mode input and common mode reference results in a 6 7ppm INL error for every 100 2 of reference resistance Inadditionto the reference sampling charge the reference ESD protection diodes have atemperature dependent leak age current This leakage current nominally 1nA 10nA max results in a small gain error A 100Q reference resistance will create a 0 5uV full scale error Normal Mode Rejection and Antialiasing One of the advantages delta sigma ADCs offer over conventional ADCs is on chip digital filtering
5. C 2499 2499fa LI MYR 1 LIC2499 ABSOLUTE MAXIMUM RATINGS Notes 1 2 Supply Voltage Ver 0 3V to 6V Analog Input Voltage CHO CH15 COM 0 3V to Vec 0 3V 0 3V to Vec 0 3V ADCINN ADCINP MUXOUTP MUXOUTN 0 3V to Vec 0 3V Digital Input Voltage 0 3V to Vec 0 3V Digital Output Voltage 0 3V to Vec 0 3V Operating Temperature Range 624990 026 to 70 C 024991 40 to 85 C Storage Temperature Range 65 to 150 C PACKAGE ORDER INFORMATION TOP VIEW UHF PACKAGE 38 LEAD 2 x 7mm 2 QFN Tymax 125 C 34 C W EXPOSED PAD Pil 39 IS GND MUST BE SOLDERED TO PCB ORDER PART NUMBER QFN PART MARKING LTC2499CUHF 2499 LTC2499IUHF Order Options Tape and Reel Add TR Lead Free Add ZPBF Lead Free Tape and Reel Add ZTRPBF Lead Free Part Marking http www linear com leadfree Consult LTC Marketing for parts specified with wider operating temperature ranges The temperature grade is defined by a label on the shipping container 2499fa HIN IR LIC2499 ELECTRICAL CHARACTERISTICS NORMAL SPEED the o denotes the s
6. VIHA Low Level Input Voltage for Address Pins CA0 CA1 CA2 0 05 VILA High Level Input Voltage for Address Pins CAO CA1 CA2 0 95Vcc V RiNH 2 from CAO CA1 CA2 to Vcc to Set Chip Address 10 it to RiNL Resistance from CAO CA1 CA2 to GND to Set Chip Address 10 Bit to 0 Resistance from CA1 CA2 to GND or to Set Chip 2 Address Bit to Float lj Digital Input Current 10 10 Vuys Hysteresis of Schmitt Trigger Inputs Note 5 0 05Vcc VoL Low Level Output Voltage SDA 3mA e 0 4 V tor Output Fall Time 10 Vit Bus Load Cg 10pFto 20 0 1Cg 250 ns 400pF Note 14 lin Input Leakage 0 1Vcc lt Vin lt Voc 1 pA Coax External Capacitative Load on Chip Address Pins CAO CA1 10 pF CA2 for Valid Float 2499fa 4 LI LIC2499 POWER REQUIREMENTS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Voc Supply Voltage 2 7 5 5 lec Supply Current Conversion Current Note 11 160 275 Temperature Measurement Note 11 200 300 Sleep Mode Note 11 1 2 DIGITAL INPUTS AND DIGITAL OUTPUTS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at
7. 2 5V 20 iN GND GND 40 Fo GND 25 C REJECTION dB 40 30600 30650 30700 30750 FREQUENCY AT Vcc Hz 30800 2499 G23 Conversion Current vs Output Data Rate 500 VREF Voc 450 LIN GND GND Fo EXT OSC 400 Ta 25 C SUPPLY CURRENT uA S 100 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 G26 PSRR vs Frequency at Vcc Vcc 4 1V DC 2 5V IN GND GND Fo GND 25 C REJECTION dB 120 1 10 100 1k 10k FREQUENCY AT Hz 100k 1M 2499 G21 Conversion Current vs Temperature 200 Fo GND 180 160 140 CONVERSION CURRENT uA 120 00 45 30 15 0 15 30 45 60 75 90 TEMPERATURE C 2499 G24 Integral Nonlinearity 2x Speed Mode Vcc 5V VREF 5V 3 Voc 5V VREF 5V 2 ViN CM 2 5V Fo GND ok 5p ve 45 0 2 2 5 2 1 5 1 0 5 0 05 1 INPUT VOLTAGE V 15 2 25 2499 G27 2499fa LIC2499 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity 2x Speed Mode Vec 2 5V Integral Nonlinearity 2x Speed
8. TECHNOLOGY LTC2499 24 Bit 8 16 Channel AX ADC with Easy Drive Input Current Cancellation and 122 Interface FEATURES Up to Eight Differential or 16 Single Ended Inputs Easy Drive Technology Enables Rail to Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 2 Wire 12 Interface with 27 Addresses Plus One Global Address for Synchronization 600nV RMS Noise Integrated High Accuracy Temperature Sensor GND to Vec Input Reference Common Mode Range Programmable 50Hz 60Hz or Simultaneous 50Hz 60Hz Rejection Mode 2ppm INL No Missing Codes 1ppm Offset and 15ppm Full Scale Error 2x Speed Reduced Power Mode 15Hz Using Internal Oscillator and 80pA at 7 5Hz Output No Latency Digital Filter Settles in a Single Cycle Even After a New Channel Is Selected Single Supply 2 7V to 5 5V Operation 0 8mW Internal Oscillator Tiny 5mm x 7mm QFN Package APPLICATIONS Direct Sensor Digitizer Direct Temperature Measurement Instrumentation Industrial Process Control DESCRIPTION The LTC92499 is a 16 channel eight differential 24 bit No Latency AZX ADC with Easy Drive technology and a 2 wire I2C interface The patented sampling scheme elimi nates dynamic input current errors and the shortcomings of on chip buffering through automatic cancellation of differential input current This allows large external source impedances and rail to rail input signals
9. 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS feosc External Oscillator Frequency Range Note 16 10 4000 kHz tHEO External Oscillator High Period 0 125 100 Us External Oscillator Low Period 0 125 100 Us tconv 1 Conversion Time for 1x Speed Mode 50Hz Mode e 1572 160 3 163 5 ms 60Hz Mode 131 133 6 136 3 ms Simultaneous 50Hz 60Hz Mode e 1441 146 9 149 9 ms External Oscillator Note 10 41036 fgosc in kHz ms tconv 2 Conversion Time for 2x Speed Mode 50Hz Mode 78 7 80 3 81 9 ms 60Hz Mode 656 66 9 68 2 ms Simultaneous 50Hz 60Hz Mode 722 73 6 75 1 ms External Oscillator Note 10 20556 fegsc in kHz ms 2 TIMING CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at 25 C Note 3 15 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency 0 400 kHz tup SDA Hold Time Repeated Start Condition e 0 6 tiow Low Period of the SCL Pin 1 3 tHIGH High Period of the SCL Pin 0 6 ps tsU STA Set Up Time for a Repeated Start Condition e 0 6 Us tHD DAT Data Hold Time 0 0 9 HS 15 Data Set Up Time 100 ns tr Rise Time for SDA Signals Note 14 20 010 300 ns t Fall Time for SDA Signals Note 14 20 0 1Cg 300 ns tsU STO Set Up Time for Stop Condition e 0 6 ps BUF
10. Input Normal Mode Rejection 2x Speed Mode ER and effective resolution as wellas a shift in frequency rejec tion When using the integrated temperature sensor the internal oscillator should be used or an external oscillator feosc 307 2kHz maximum change feosc results in a proportional change in the internal notch position This leads to reduced differential mode rejection of line frequencies The common mode rejection of line frequencies remains unchanged thus fully differential input signals with a high degree of symmetry on both the IN and pins will continue to reject line frequency noise An increase in fggsc also increases the effective dynamic input and reference current External RC networks will continue to have zero differential input current but the time required for complete settling 580ns for fggsc 307 2kHz is reduced proportionally Once the external oscillator frequency is increased above 1MHz a more than 3x increase in output rate the effectiveness of internal auto calibration circuits begins to degrade This results in larger offset errors full scale errors and decreased resolution as seen in Figures 30 37 20 40 60 n PI 1 120 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY fy NPUT NORMAL REJECTION dB 2499 F28 Figure 28 Input Normal Mode Rejection 2x Speed Mode
11. combination of front end switching and digital process ing Since the external amplifier is placed between the multiplexer and the ADC it is inside this correction loop This results in automatic offset correction and offset drift removal of the external amplifier The LTC6078 is an excellent amplifier for this function It operates with supply voltages as low as 2 7V and its noise level is 18nV 4Hz The Easy Drive input technology ofthe LTC2499 enables an RC network to be added directly to the output of the LTC6078 The capacitor reduces the magnitude of the current spikes seen at the input to the ADC and the resistor isolates the capacitor load from the op amp output enabling stable operation The LTC6078 can also be biased at supply rails beyond those used by the LTC2499 This allows the external sensor to swing rail to rail 0 3V to Vec 0 3V without the need of external level shift circuitry Figure 12 External Buffers Provide High Impedance Inputs and Amplifier Offsets are Automatically Cancelled 2499fa 24 LIC2499 APPLICATIONS INFORMATION Reference Current Similar to the analog inputs the LTC2499 samples the differential reference pins REF and REF transferring small amounts of charge to and from these pins thus producing a dynamic reference current If incomplete set tling occurs as a function the reference source resistance and reference bypass capacitance linearity and gain errors are
12. 100 110 120 2 0 fs 26 35 46 5 66 716 85 915 10fs DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz 2499 F19 NPUT NORMAL MODE REJECTION dB Figure 19 Input Normal Mode Rejection Internal Oscillator and 60Hz Rejection Mode 2499fa 20 LI MYR LIC2499 APPLICATIONS INFORMATION The user can expect to achieve this level of performance using the internal oscillator as shown in Figures 22 23 and 24 Measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes Traditional high order delta sigma modulators suffer from potential instabilities at large input signal levels The proprietary architecture used for the LTC2499 third order modulator resolves this problem and guarantees stability with input signals 150 of full scale In many industrial applications it is not uncommon to have microvolt level Signals superimposed over unwanted error sources with several volts if peak to peak noise Figures 25 and 26 show measurement results forthe rejection ofa 7 5V peak to peak noise source 150 of full scale applied to the LTC2499 These curves show that the rejection performance is maintained even in extremely noisy environments N 1605 5120 NPUT NORMAL MODE REJECTION dB 100 110 120 0 2 3 N 4 5fy 8fN INPU
13. 2499fa LI We 29 LIC2499 APPLICATIONS INFORMATION 70 50 EN p ViN CM VREF CM PM P Voc 5V 4 40 f Vin OV 5 NO AVERAGE Fo EXT CLOCK 5 90 s 2 gt 30 Ta 85 C d 100 amp A 20 2 110 2 10 Ed 120 5 430 0 Ta 25 C 140 10 48 50 52 54 56 58 60 62 0 10 20 30 40 50 60 70 80 90 100 DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz OUTPUT DATA RATE READINGS SEC 2499 F29 2499 F30 Figure 29 Input Normal Mode Figure 30 Offset Error vs Output Data Rejection 2x Speed Mode with and Rate and Temperature Without Running Averaging 0 24 500 22 TA 85 C 21000 5 20 5 amp 1500 5 18 gt 2000 d 16 t 2500 14 VIN CM VREF CM T REF 5V M ii 12 Fy EXT CLOCK Fo EXT CLOCK RES LOG 2 Vper NOISERms 3500 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC Figure 32 FS Error vs Output Data Rate and Temperature Vin om VREF CM Vin Ov Fo EXT CLOCK 25 C 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 F33 Figure 33 Resolution 5 lt 1LSB vs Output Data Rate and Temperatur
14. ADCs with Differential Inputs in MSOP 1 45uVpms Noise 4ppm INL Simultaneous 50Hz 60Hz LTC2411 1 Rejection LTC2411 1 LTC2413 24 Bit No Latency AX ADC with Differential Inputs Simultaneous 50Hz 60Hz Rejection 800nVpys Noise LTC2440 24 Bit High Speed Low Noise AX ADC 3 5kHz Output Rate 200nV Noise 24 6 ENOBs LTC2442 24 Bit High Speed 2 4 Channel AX ADC with Integrated 8kHz Output Rate 200nV Noise Simultaneous 50Hz 60Hz Amplifier Rejection LTC2449 24 Bit High Speed 8 16 Channel AX ADC 8kHz Output Rate 200nV Noise Simultaneous 50Hz 60Hz Rejection LTC2480 LTC2482 16 Bit 24 Bit AX ADCs with Easy Drive Inputs 600nV Noise Pin Compatible with 16 Bit and 24 Bit Versions LTC2484 Programmable Gain and Temperature Sensor LTC2481 LTC2483 16 Bit 24 Bit A ADCs with Easy Drive Inputs 600nV Noise Pin Compatible with 16 Bit and 24 Bit Versions LTC2485 12C Interface Programmable Gain and Temperature Sensor LTC2496 16 Bit 8 16 Channel AX ADC with Easy Drive Inputs and Pin Compatible with LTC2498 LTC2449 SPI Interface LTC2497 16 Bit 8 16 Channel AX ADC with Easy Drive Inputs and Pin Compatible with LTC2499 26 Interface LTC2498 24 Bit 8 16 Channel AX ADC with Easy Drive Inputs and Pin Compatible with LTC2496 LTC2449 SPI Interface Temperature Sensor 3 Linear Technology Corporation 1630 McCarthy Blvd Milpitas CA 95035 7417 408 432 1900 FAX 408 434 0507 www linear com 2499fa LT CGRAFX 0407 REV PRINTED IN
15. CM 14 0 REF GND 12 Fo EXT CLOCK Ta 25 C RES LOG 2 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 F37 Figure 37 Resolution INLjay lt 1LSB vs Output Data Rate and Temperature 2499fa 30 AL LIC2499 PACKAGE DESCRIPTION UHF Package 38 Lead Plastic QFN 5mm x 7mm Reference LTC DWG 05 08 1701 e CI 5 50 0 05 E 7 410 0 05 2 SIDES LI co 3 15 0 05 C 2 SIDES 1 o gt PACKAGE 0 25 0 05 gt l 0 50 BSC lt 5 15 0 05 2 SIDES gt 6 10 0 05 2 SIDES E 7 50 0 05 2 SIDES _L__ RECOMMENDED SOLDER PAD LAYOUT PIN 1 NOTCH R 0 30 TYP OR 5 00 0 10 0 75 0 05 v 0 35 x 45 CHAMFER SIDES 41 0 00 0 05 0 40 0 10 PIN 1 TOP MARK SEE NOTE 6 1 i I I I 1 7 00 0 10 T 5 15 0 10 2 SIDES 2 SIDES I I 1 I Y 0 40 0 10 gt lt 0200 REF 0 25 0 05 lt UH QFN 0205 0 200 REF 0 75 0 05 0 00 0 05 BOTTOM VIEW EXPOSED PAD y HHHH dy NOTE tt 1 DRAWING CONFORMS TO JEDEC PACKAGE 4 DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE OUTLINE 0 220 VARIATION WHKD
16. Combined with a large oversample ratio the 1702499 significantly simplifies antialiasing filter requirements Additionally the input current cancellation feature allows external low pass filtering without degrading the DC performance of the device The SINC digital filter provides excellent normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency fs see Figures 18 and 19 The modulator sampling frequency is fs 15 360Hz while operating with its internal oscillator and fs fgosc 20 when operating with an external oscillator of frequency fgosc When using the internal oscillator the LTC2499 is de signed to reject line frequencies As shown in Figure 20 rejection nulls occur at multiples of frequency fy where fy is determined by the input control bits FA and FB fy 50Hz or 60Hz or 55Hz for simultaneous rejec tion Multiples of the modulator sampling rate fs fy 256 only reject noise to 15dB see Figure 21 if noise sources are present at these frequencies antialiasing will reduce their effects 10 20 30 40 50 60 70 80 90 100 110 1 0 fs 2536 446 5fs 6fs 716 815 91 101111215 DIFFERENTIAL INPUT SIGNAL FREQUENCY Hz 2499 F18 NPUT NORMAL MODE REJECTION dB Figure 18 Input Normal Mode Rejection Internal Oscillator and 50Hz Rejection Mode 0 10 20 30 40 50 60 70 80 90
17. LI Ure 23 LIC2499 APPLICATIONS INFORMATION inputimpedances the common mode input current effects are rejected by the large CMRR of the LTC2499 leading to little degradation in accuracy Mismatches in source impedances lead to gain errors proportional to the dif ference between the common mode input and common mode reference 1 mismatches in 1ksource resistances lead to gain errors on the order of 15ppm Based on the Stability of the internal sampling capacitors and the ac curacy of the internal oscillator a one time calibration will remove this error In addition to the input sampling current the input ESD protection diodes have a temperature dependent leakage current This current nominally 1nA 10nA max results in a small offset shift A 1k source resistance will create a 1uV typical and a 10uV maximum offset voltage Automatic Offset Calibration of External Buffers Amplifiers In addition to the Easy Drive input current cancellation the LTC2499 allows an external amplifier to be inserted between the multiplexer output and the ADC input see Figure 12 This is useful in applications where balanced 1102499 ANALOG 17 INPUTS source impedances are not possible One pair of external buffers amplifiers can be shared between all 17 analog inputs The LTC2499 performs an internal offset calibration every conversion cycle in order to remove the offset and drift of the ADC This calibration is performed through a
18. LOW 1000100 FLOAT FLOAT HIGH 1000110 FLOAT FLOAT FLOAT 1000101 may be read using the method described above If the conversion cycle is not concluded and a valid address selects the device the LTC2499 generates a NAK signal indicating the conversion cycle is in progress Continuous Read Write Once the conversion cycle is concluded the LTC2499 can be written to and then read from using the Repeated Start Sr command Figure 8 shows a cycle which begins with a data Write a repeated Start followed by a Read and concluded with a Stop command The following conversion begins after all 2499fa 20 LIC2499 APPLICATIONS INFORMATION 7 BIT ADDRESS DATA DATA TRANSFERRING mn CONVERSION SLEEP gt lt DATA INPUT OUTPUT gt lt CONVERSION 2499 F05 Figure 6 Conversion Sequence 7 BIT ADDRESS JACK 7 BIT ADDRESS R READ ACK READ P CONVERSION gt lt gt lt gt lt SLEEP OUTPUT CONVERSION 2499 07 gt lt gt lt gt lt CONVERSION SLEEP DATAOUTPUT Figure 7 Consecutive Reading with the Same Input Configuration 5 7 BIT ADDRESS W ACK WRITE Sr 7 BIT ADDRESS READ P gt lt gt lt gt lt gt lt gt lt CONVERSION SLEEP DATAINPUT ADDRESS DATAOUTPUT CONVERSION 2499 F08 Figure 8 Write Read Start Conversion 7 BIT ADDRESS 2
19. MOLD FLASH MOLD FLASH IF PRESENT SHALL NOT EXCEED 0 20mm ON ANY SIDE 2 DRAWING NOT TO SCALE 5 EXPOSED PAD SHALL BE SOLDER PLATED 3 ALL DIMENSIONS ARE IN MILLIMETERS 6 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2499fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable y LINTAR However no responsibility is assumed for its use Linear Technology Corporation makes no representa TECHNOLOGY tion that the interconnection of its circuits as described herein will not infringe on existing patent rights 31 LIC2499 TYPICAL APPLICATION External Buffers Provide High Impedance Inputs and Amplifier Offsets are Automatically Cancelled LTC2499 ANALOG 17 INPUTS 1 2 LTC6078 1 1 2 LTC6078 ADC WITH SDA EASY DRIVE SCL INPUTS 2499 TA03 PART NUMBER DESCRIPTION COMMENTS LT1236A 5 Precision Bandgap Reference 5V 0 05 Max Initial Accuracy 5ppm C Drift LT1460 Micropower Series Reference 0 075 Max Initial Accuracy 10ppm C Max Drift LT1790 Micropower SOT 23 Low Dropout Reference Family 0 05 Max Initial Accuracy 10ppm C Max Drift LTC2400 24 Bit No Latency AX ADC in S0 8 0 3ppm Noise 4ppm INL 10ppm Total Unadjusted Error 200A LTC2410 24 Bit No Latency AX ADC with Differential Inputs 0 8uVams Noise 2ppm INL LTC2411 24 Bit No Latency AX
20. Mode Vec 2 71 2 5V 3 3 Vcc 5V Vec 2 7V 2 5V 2 5V 2 Vic 1 25 Fo GND gt gt 5 e a E 3 3 125 0 75 025 025 075 1 25 125 075 0 25 025 075 1 25 INPUT VOLTAGE V INPUT VOLTAGE V 2499 628 2499 G29 RMS Noise vs VREF Offset Error vs Vin cm 2x Speed Mode 2x Speed Mode 1 0 200 RET 5 by VREF BV Vin OV 0 8 196 FEN GND 194 Ta 25 C 06 192 e z 190 Voc 5V 186 Vin OV 02 Vino GND 184 Fo GND 182 Ta 25 C 0 180 0 1 2 3 4 5 i 0 1 2 3 5 6 Veer V V 2499 G31 2499 G32 Noise Histogram 2x Speed Mode READINGS Vec 5V VREF 5V Vin OV Ta 25 C 10 000 CONSECUTIVE RMS 0 85uV AVERAGE 0 184mV NUMBER OF READINGS 0 179 181 4 Offset Error vs Temperature 183 8 OUTPUT READING uV 2x Speed Mode gt Vec 5V VREF 5V Vin OV Fo Vin cm GND GND 186 2 188 6 2499 G30 OFFSET ERROR uV N s 160 45 30 15 0
21. USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 2006
22. bits long sets the input channel selects the temperature sensor rejection mode and speed mode DATA OUTPUT FORMAT The output register contains the last conversion result After each conversion is completed the device automati cally enters the sleep state where the supply current is reduced to 14A When the LTC2499 is addressed for a read operation it acknowledges by pulling SDA low and acts as a transmitter The master receiver can read up to four bytes from the LTC2499 After a complete read operation 4 bytes a new conversion is initiated The device will NAK subsequent read operations while a conversion is being performed The data output stream is 32 bits long and is shifted out are HIGH the differential input voltage is equal to or above FS If both bits are set low the input voltage is below FS The function of these bits is summarized in Table 2 The 24 bits following the MSB bit are the conversion result in binary two s complement format The remaining six bits are sub LSBs below the 24 bit level As long as the voltage on the selected input channels IN and remains between 0 3V and 0 3V absolute maximum operating range a conversion result is gener ated for any differential input voltage Viy from FS 0 5 to FS 0 5 Vngr For differential input voltages greater than FS the conversion result is clamped to the value corresponding to FS For differential input vol
23. device before the initiation of a new conversion Data Transferring After the Start condition the 126 bus is busy and data transfer can begin between the master and the addressed slave Data is transferred over the bus in groups of nine bits one byte followed by one acknowledge ACK bit The master releases the SDA line during the ninth SCL clock cycle The slave device can issue an ACK by pulling SDA low or issue a Not Acknowledge NAK by leaving the SDA line high impedance the external pull up resistor will hold the line high Change of data only occurs while the clock line SCL is low DATA FORMAT After a Start condition the master sends a 7 bit address followed by a read write R W bit The R W bit is 1 fora read request and 0 for a write request If the 7 bit address matches the hard wired LTC2499 s address one of 27 pin selectable addresses the device is selected When the device is addressed during the conversion state it will not acknowledge R W requests and will issue a NAK by leaving the SDA line high If the conversion is complete the LTC2499 issues an ACK by pulling the SDA line low e tub sDA tsysto gt be 2499 F02 Figure 2 Definition of Timing for Fast Standard Mode Devices on the 12C Bus 2499fa 14 LI Ure LIC2499 APPLICATIONS INFORMATION The LTC2499 has two registers The output register 32 bits long contains the last conversion result The input register 16
24. for optimum ground cur rent flow and Vcc decoupling Connect each one of these pins to a common ground plane through a low impedance connection All seven pins must be connected to ground for proper operation SCL Pin 2 Serial Clock Pin of the 12C Interface The LTC2499 can only act as a slave and the SCL pin only ac cepts an external serial clock Data is shifted into the SDA pin onthe rising edges ofthe SCL clockand outputthrough the SDA pin on the falling edges of the SCL clock SDA Pin 3 Bidirectional Serial Data Line of the 12C Inter face Inthe transmitter mode Read the conversion result is output through the SDA pin while in the receiver mode Write the device channel select and configuration bits are input through the SDA pin The pin is high impedance during the data input mode and is an open drain output requires an appropriate pull up device to Vcc during the data output mode 2499fa 10 LI LIC2499 PIN FUNCTIONS NC Pin 5 No Connect This pin can be left floating or tied to GND COM Pin 7 The Common Negative Input for All Single Ended Multiplexer Configurations The voltage on CH0 CH15 and COM pins can have any value between GND 0 3V to Vcc 0 3V Within these limits the two selected inputs IN and provide a bipolar input range Vin from 0 5 Vggr to 0 5 VREF Outside this input range the converter produces unique Over range and und
25. from a Note 15 All values refer to VIH MIN and levels straight line passing through the actual endpoints of the transfer curve Note 16 Refer to Applications Information section for Performance vs The deviation is measured from the center of the quantization band Data Rate graphs 2499fa LI Wee 5 LIC2499 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity Vcc 5V 5V Integral Nonlinearity Vcc 5V 2 5V Integral Nonlinearity Vec 2 7V 2 5V 3 Voc 5V Vec 5V 5V 2 5V 2 VIN CM 25V VIN CM 1 25V Fo G Fo GND 4B 1 45 5 T T E n ho C E 5 I M 5 E 0 p omm 85 C os 2 3 3 3 25 2 15 1 05 0 05 1 15 2 25 125 075 0 25 025 075 1 25 125 075 0 25 025 075 1 25 INPUT VOLTAGE V INPUT VOLTAGE V INPUT VOLTAGE V 2499 601 2499 G02 Total Unadjusted Error Total Unadjusted Error Total Unadjusted Error 5V Vpgr 5V
26. input current is zero the common mode input current ljy liy 2 is proportional to the difference between the common mode input voltage Vin cm and the common mode reference voltage VREF cM In applications where the input common mode voltage is equal to the reference common mode voltage as in the case of a balanced bridge both the differential and com mon mode input current are zero The accuracy of the converter is not compromised by settling errors In applications where the input common mode voltage is constant but different from the reference common mode voltage the differential input current remains zero while the common mode input current is proportional to the difference between and Vrer cm For a reference common mode voltage of 2 5V and aninputcommon mode of 1 5V the common mode input current is approximately 0 74uA in simultaneous 50Hz 60Hz rejection mode This common mode input current does not degrade the accuracy if the source impedances tied to IN and IN are matched Mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full scale reading A 1 mismatch in a 1kQ source resistance leads to a 74u V shift in offset voltage In applications where the common mode input voltage varies as a function of the input signal level single ended type sensors the common mode input current varies proportionally with input voltage For the case of balanced 2499fa
27. 2499 APPLICATIONS INFORMATION Using the 2X speed mode of the LTC2499 alters the rejection characteristics around DC and multiples of fs The device bypasses the offset calibration in order to increase the output rate The resulting rejection plots are shown in Figures 27 and 28 1x type frequency rejection can be achieved using the 2x mode by performing a run ning average of the previoius two conversion results see Figure 29 Output Data Rate When using its internal oscillator the 1702499 produces up to 7 5 samples per second sps with a notch frequency of 60Hz The actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short When operating with an external conversion clock fg connected to an external oscillator the 1702499 output data rate can be increased The duration of the conversion cycle is 41036 fegsc If feosc 307 2kHz the converter behaves as if the internal oscillator is used An increase fegsc over the nominal 307 2kHz will trans late into a proportional increase in the maximum output data rate up to a maximum of 100sps The increase in output rate leads to degradation in offset full scale error 20 NPUT NORMAL REJECTION dB 0 2 4fy 5 8fy INPUT SIGNAL FREQUENCY 2499 F27 Figure 27
28. ATURE 2499 G12 Offset Error vs Viy cwy 0 3 Voc 5V VREF 5V 0 2 Vin 0V E TA 25 C Fo GND 5 01 9 x 0 a 2 02 0 3 1 0 1 2 3 4 5 V 2499 G15 Offset Error vs VREF 0 3 Voc 5V REF GND T 0 2 Vin OV Vin cm GND Ew TA 25 C o 5 0 Fo GND 0 E 0i 2 902 2499 618 2499fa LI We 7 LIC2499 TYPICAL PERFORMANCE CHARACTERISTICS FREQUENCY kHz REJECTION dB On Chip Oscillator Frequency vs Temperature 300 45 30 15 0 15 30 45 60 75 90 TEMPERATURE C 2499 G19 PSRR vs Frequency at Vec Vcc 4 1V DC 1 4V 2 5V IN GND GND Fo GND Ta 25 C 0 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT Vec Hz 2499 G22 Sleep Mode Current vs Temperature Fo GND SLEEP MODE CURRENT uA 1 2 Veg 5V 0 6 Voc 2 7V 0 45 30 15 0 15 30 45 60 75 90 TEMPERATURE C 2499 G25 On Chip Oscillator Frequency vs Vec 310 2 5V Vin OV 308 VIN CM 5 TA 25 C 306 2 304 fe 302 300 25 30 35 40 45 50 55 Voc V 2499 G20 PSRR vs Frequency at Vec 0 Voc 4 1V DC 0 7V Vngr
29. Bus Free Time Between a Second Start Condition 1 3 Note 1 Stresses beyond those listed under Absolute Maximum Ratings Note 7 50Hz mode internal oscillator or 256kHz 2 external oscillator may cause permanent damage to the device Exposure to any Absolute Note 8 60Hz mode internal oscillator 307 2kHz 2 external oscillator Maximum Rating condition for extended periods may affect device reliability and lifetime Note 2 All voltage values are with respect to GND Note 3 Unless otherwise specified Vcc 2 7V to 5 5V VntrcM 2 Fs 0 5VREF Vin IN INT Vince IN 7 2 where and are the selected input channels Note 4 Use internal conversion clock or external conversion clock source with fegsc 307 2kHz unless otherwise specified Note 5 Guaranteed by design not subject to test 280kHz 2 external oscillator oscillator frequency fgosc is expressed in kHz Note 11 The converter uses its internal oscillator Note 12 The output noise includes the contribution of the internal calibration operations Note 13 Guaranteed by design and test correlation Note 9 Simultaneous 50Hz 60Hz mode internal oscillator or fegsc Note 10 The external oscillator is connected to the Fo pin The external Note 14 Cg capacitance of one bus line in pF lt Cg lt 400pF Note 6 Integral nonlinearity is defined as the deviation of a code
30. OWER ON RESET DEFAULT CONFIGURATION IN CH1 50Hz 60Hz REJECTION 1X OUTPUT CONVERSION STOP OR READ 32 BITS 2499 F01 Figure 1 State Transition Table and has no effect on the operation cycle described above The advantage of continuous calibration is extreme stability of offsetand full scale readings with respectto time supply voltage variation input channel and temperature drift Easy Drive Input Current Cancellation The LTC2499 combines a high precision delta sigma ADC with an automatic differential input current cancellation frontend A proprietary front end passive sampling network transparently removes the differential input current This enables external RC networks and high impedance sen sors to directly interface to the LTC2499 without external amplifiers The remaining common mode input current is eliminated by either balancing the differential input im pedances or setting the common mode input equal to the common mode reference see the Automatic Differential Input Current Cancellation section This unique architec ture does not require on chip buffers thereby enabling signals to swing beyond ground and Voc Moreover the 2499fa 12 AL LIC2499 APPLICATIONS INFORMATION cancellation does not interfere with the transparent offset and full scale auto calibration and the absolute accuracy full scale offset linearity drift is maintained even with exter
31. PUT DATA FORMAT The serial input word to the LTC2499 is 13 bits long and is written into the device input register in two 8 bit words The first word SGL ODD A2 A1 A0 is used to select the input channel The second word of data IM FA FB SPD is used to select the frequency rejection speed mode 1x 2x and temperature measurement After power up the device initiates an internal reset cycle which sets the input channel to CHO CH1 IN CHO IN CH1 the frequency rejection to simultaneous 50Hz 60Hz and 1x output rate auto calibration enabled The first conversion automatically begins at power up using this default configuration Once the conversion is complete up to two words may be written into the device The first three bits of the first input word consist of two preamble bits and one enable bit Valid settings for these three bits are 000 100 and 101 Other combinations should be avoided ACK BY LTC2499 START BY MASTER SLEEP gt lt If the first three bits are 000 or 100 the following data is ignored don t care and the previously selected input channel remains valid for the next conversion If the first three bits shifted into the device are 101 then the next five bits select the input channel for the next conversion cycle see Table 3 The first input bit SGL following the 101 sequence de termines if the input selection is differential SGL 0 or single ended SGL 1 For SGL 0 tw
32. T SIGNAL FREQUENCY Hz 2499 F20 Figure 20 Input Normal Mode Rejection at DC 100 NPUT NORMAL MODE REJECTION dB 110 120 250 252fy 254fy 256fy 2581 260fy 262fy INPUT 5 GNAL FREQUENCY Hz 2499 21 Figure 21 Input Normal Mode Rejection at fs 256 fy 2499fa LI We 2 LIC2499 APPLICATIONS INFORMATION 0 D XE Riese 0 Ix MEASURED DATA Vcc 5V o MEASURED DATA VREF 5V 220 CALCULATED DATA Vincu 25V 220 CALCULATED DATA Vin p P 5V H t 25 C AN lA hid 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 0 125 25 375 50 625 75 875 100 112 5 125 137 5 150 162 5 175 187 5 200 NPUT FREQUENCY Hz NPUT FREQUENCY Hz 2498 F23 2498 F24 Figure 22 Input Normal Mode Rejection vs Input Frequency with Figure 23 Input Normal Mode Rejection vs Input Frequency with Vcc 5V VREF 5V 2 5V Vin p p 5V 40 Ty 25 C NORMAL MODE REJECTION dB e indt NORMAL MODE REJECTION dB Input Perturbation of 100 60Hz No
33. Vec 5V Vpggr 2 5V Vee 2 71 2 5V 12 12 12 Vec 5V Voc 5V E Vec 2 7V 5V Vref 2 5V 85 C P 2 5V 8 2 5V 8 ViN cM 1 25V 8 1 25V Fo GND 5 0 n Fo GND Fo GND 0 25 C _ 0 25 gt NA 0 25 eT 4 y A 4 Vb 4 SE gt Bra gt gt a 5 2 4 5 5 45 C 0 45 0 gt 45 C E 0 a a Ter ii ory oe 2 4 gt 2 4 gt 2 4 LA E i 8 8 12 2 12 2 5 2 1 5 1 0 5 0 05 1 15 2 25 125 0 75 0 25 0 25 075 125 4 25 0 75 0 25 025 075 1 25 INPUT VOLTAGE V INPUT VOLTAGE V INPUT VOLTAGE V 2499 G04 2499 G05 2499 G06 Noise Histogram 6 8sps Noise Histogram 7 5sps Long Term ADC Readings 14 14 5 10 000 CONSECUTIVE 10 000 CONSECUTIVE Vec 5V 25 C ben pod ij 21 NS EN 4 Vper 5V NOISE 0 60uV VREF 5V AVERAGE 0 69uV 2 5 Eis 3 c 10 Viy 7 0V 10 Vin 2 Ta 25 C i e N E 5 8 Y 8 oc oc a S 6 5 6 j oc ce E E S 4 A gt 4 2 V 2 z z Adi lh 0 3 24 18 1 2 06 0 0 6 OUTPUT READING uV 2499 G07 0 3 24 18 12 06 0 06 OUTPUT READING uV 2499 G08 0 10 2 30 40 50 60 TIME HOURS 2499 609 2499fa LI LIC2499 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs Input Differential Voltage
34. Voltage GND 0 3V Voc 0 3V V IN Corresponds to the Selected Positive Input Channel Absolute Common Mode IN Voltage GND 0 3V Voc 0 3V V IN Corresponds to the Selected Negative Input Channel VIN Input Differential Voltage Range IN e FS FS FS Full Scale of the Differential Input IN IN 0 5VREF V LSB Least Significant Bit of the Output Code 224 REF Absolute Common Mode REF Voltage e 0 1 Vcc V REF Absolute Common Mode REF Voltage GND REF 0 1V V VREF Reference Voltage Range REF REF e 0 1 Vcc V CS IN IN Sampling Capacitance 11 pF CS IN Sampling Capacitance 11 pF CS Vner Sampling Capacitance 11 pF Ipc IN DC Leakage Current Sleep Mode IN GND e 10 1 10 nA Ipc LEAK IN IN DC Leakage Current Sleep Mode GND e 10 1 10 nA IpC LEAK REF REF DC Leakage Current Sleep Mode REF Vcc e 100 1 100 IDC LEAK REF REF DC Leakage Current Sleep Mode REF GND e 100 1 100 MUX Break Before Make 50 ns QIRR MUX Off Isolation Vin 2Vp p DC to 1 8MHz 120 dB 2 INPUTS AND DIGITAL OUTPUTS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Vin High Level Input Voltage 0 7Vcc VIL Low Level Input Voltage 0
35. WRITE OPTIONAL P gt lt gt lt gt lt CONVERSION gt SLEEP DATA INPUT CONVERSION 2499 F09 Figure 9 Start a New Conversion Without Reading Old Conversion Result 2499fa LI MYR 2 1 LIC2499 APPLICATIONS INFORMATION 32 bits are read out of the device or after a Stop command The following conversion will be performed using the newly programmed data In cases where the same speed 1x 2x mode and rejection frequency 50Hz 60Hz 50Hz and 60Hz is used but the channel is changed a Stop or Repeated Start may be issued after the first byte channel selection data is written into the device Discarding a Conversion Result and Initiating a New Conversion with Optional Write At the conclusion of a conversion cycle a write cycle can be initiated Once the write cycle is acknowledged a Stop command will start a new conversion If a new input channel or conversion configuration is required this data can be written into the device and a Stop command will initiate the next conversion see Figure 9 Synchronizing Multiple LTC2499s with a Global Address Call In applications where several LTC2499s or other 12C delta sigma ADCs from Linear Technology Corporation are used on the same 126 bus all converters can be syn chronized through the use of a global address call Prior to issuing the global address call all converters must have completed a conversion cycle The master then issues a Start followe
36. antialiasing results in incomplete settling The LTC2499 offers two methods of removing these errors The first is an automatic differential input current cancellation Easy Drive and the second is the insertion of an external buffer between the MUXOUT and ADCIN pins thus isolating the input switching from the source resistance Automatic Differential Input Current Cancellation In applications where the sensor output impedance is low up to 10kO with no external bypass capacitor or up to 500Q with 0 001uF bypass complete settling of the input occurs In this case no errors are introduced and direct digitization is possible For many applications the sensor output impedance combined with external input bypass capacitors produces RC time constants much greater than the 580ns required for 1ppm accuracy For example a 10kQ bridge driving a 0 1uF capacitor has atime constant an order of magnitude greater than the required maximum The LTC2499 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors This allows direct digitization of high impedance sensors without the need for buffers The switching algorithm forces the average input current on the positive input Ijy to be equal to the average input current on the negative input 1 Over the complete conversion cycle the average differential input current liy is zero While the differential
37. d by the global address 1110111 and awrite request All converters will be selected and acknowledge the request The master then sends a write byte optional followed by the Stop command This will update the chan nel selection optional converter configuration optional and simultaneously initiate a start of conversion for all delta sigma ADCs on the bus see Figure 10 In order 1 0 1762499 1762499 i LTC2499 s GLOBAL ADDRESS w 2 WRITE OPTIONAL P ALL LTC2499s IN SLEEP gt lt DATA INPUT gt lt CONVERSION OF ALL LTC2499s 2499 F10 Figure 10 Synchronize Multiple LTC2499s with a Global Address Call INTERNAL SWITCH NETWORK EXTERNAL CONNECTION INPUT MULTIPLEXER EXTERNAL CONNECTION SWITCHING FREQUENCY few 123kHz INTERNAL OSCILLATOR fgw 0 4 feosc EXTERNAL OSCILLATOR _ Vic Verom 0 5 Reg AVG 0 5Req Veer Reg where REF REF Cea VREF CM E 12uF Vin IN IN WHERE AND INT ARE THE SELECTED INPUT CHANNELS IN INT Vea INCM 5 Reg 2 71MQ INTERNAL OSCILLATOR 60Hz MODE Reg 2 98 MQ INTERNAL OSCILLATOR 50Hz 60Hz MODE Reg 0 833 10 fosc EXTERNAL OSCILLATOR Figure 11 Equivalent Analog Input Circuit 2499fa 22 LI Ure LIC2499 APPLICATIONS INFORMATION to synchronize multipl
38. e N N N OFFSET ERROR ppm OF 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 F35 Figure 35 Offset Error vs Output Data Rate and Temperature RESOLUTION BITS Vin cm VREF CM Vine Ov Fo EXT CLOCK Ta 25 C RES LOG 2 015 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 F36 Figure 36 Resolution Noisepms lt 1LSB vs Output Data Rate and Temperature 4FS ERROR ppm OF 3500 ViN cM VREF CM 3000 Voc VREF 5V Fo EXT CLOCK 2500 85 C 2000 1500 25 C 1000 500 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 F31 Figure 31 FS Error vs Output Data Rate and Temperature 22 20 85 C TA 25 C e 16 e 8 14 ViN CM VREF CM 12 Voc Vngr 5V Fo EXT CLOCK RES LOG 2 VagE INLyAx 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE READINGS SEC 2499 4 Figure 34 Resolution INLmax lt 1LSB vs Output Data Rate and Temperature 22 20 2 18 m z Voc Vngr 5V S 16 Voc 5V Vngr 2 5V 5 ViN cM VREF
39. e converters without changing the channel or configuration a Stop may be issued after acknowledgement of the global write command Global read commands are not allowed and the converters will NAK a global read request Driving the Input and Reference The input and reference pins of the LTC2499 are connected directly to a switched capacitor network Depending on the relationship between the differential input voltage and the differential reference voltage these capacitors are switched between these four pins Each time a capacitor is switched between two of these pins a small amount of charge is transferred A simplified equivalent circuit is shown in Figure 11 When using the LTC2499 s internal oscillator the input capacitor array is switched at 123kHz The effect of the charge transfer depends on the circuitry driving the in put reference pins If the total external RC time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs Typically the reference inputs are driven from a low impedance source In this case complete settling occurs even with large external bypass capacitors The inputs CH0 CH15 COM on the other hand are typically driven from larger source resistances Source resistances up to 10k may interface directly to the LTC2499 and settle completely however the addition of external capacitors at the input terminals in order to filter unwanted noise
40. e may be programmed to perform several functions These include input channel selection measure the internal temperature selecting the line fre quency rejection 50Hz 60Hz or simultaneous 50Hz and 60Hz and a 2x speed mode Continuous Read Inapplications wherethe input channel configuration does not need to change for each cycle the conversion can be continuously performed and read without a write cycle see Figure 7 The configuration input channel remains unchanged from the last value written into the device If the device has not been written to since power up the configuration is set to the default value At the end of a read operation a new conversion automatically begins At the conclusion of the conversion cycle the next result Table 5 Address Assignment CA2 CA1 CA0 ADDRESS LOW LOW LOW 0010100 LOW LOW HIGH 0010110 LOW LOW FLOAT 0010101 LOW HIGH LOW 0100110 LOW HIGH HIGH 0110100 LOW HIGH FLOAT 0100111 LOW FLOAT LOW 0010111 LOW FLOAT HIGH 0100101 LOW FLOAT FLOAT 0100100 HIGH LOW LOW 1010110 HIGH LOW HIGH 1100100 HIGH LOW FLOAT 1010111 HIGH HIGH LOW 1110100 HIGH HIGH HIGH 1110110 HIGH HIGH FLOAT 1110101 HIGH FLOAT LOW 1100101 HIGH FLOAT HIGH 1100111 HIGH FLOAT FLOAT 1100110 FLOAT LOW LOW 0110101 FLOAT LOW HIGH 0110111 FLOAT LOW FLOAT 0110110 FLOAT HIGH LOW 1000111 FLOAT HIGH HIGH 1010101 FLOAT HIGH FLOAT 1010100 FLOAT FLOAT
41. epending on the function of the device In addition to transmitters and receivers devices canalso be considered as masters or slaves when perform ing data transfers A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer Devices addressed by the master are considered a slave The LTC2499 can only be addressed as a slave Once addressed it can receive configuration bits channel selection rejection mode speed mode or transmit the last conversion result The serial clock line SCL is always an input to the LTC2499 and the serial data line SDA is bidirectional The device supports the standard mode and the fast mode for data transfer speeds up to 400kbits s Figure 2 shows the definition of the I C timing The Start and Stop Conditions AStart S condition is generated by transitioning SDA from high to low while SCL is high The bus is considered to be busy after the Start condition When the data transfer is SDA SCL tsu stay gt finished a Stop P condition is generated by transitioning SDA from low to high while SCL is high The bus is free after a Stop is generated Start and Stop conditions are always generated by the master When the bus is in use it stays busy if a Repeated Start Sr is generated instead of a Stop condition The repeated Start timing is functionally identical to the Start and is used for writing and reading from the
42. er range output codes CHO to CH15 Pin 8 Pin 23 Analog Inputs May be pro grammed for single ended or differential mode MUXOUTP Pin 24 Positive Multiplexer Output Connect to the input of external buffer amplifier or short directly to ADCINP ADCINP Pin 25 Positive ADC Input Connect to the output of a buffer amplifier driven by MUXOUTP or short directly to MUXOUTP ADCINN Pin 26 Negative ADC Input Connect to the output of a buffer amplifier driven by MUXOUTN or short directly to MUXOUTN MUXOUTN Pin 27 Negative Multiplexer Output Con nect to the input of an external buffer amplifier or short directly to ADCINN Vec Pin 28 Positive Supply Voltage Bypass to GND with a 10uF tantalum capacitor in parallel with a 0 1 pF ceramic capacitor as close to the part as possible REF Pin 29 Pin 30 Differential Reference Input The voltage on these pins can have any value between GND and Vcc as long as the reference positive input REF remains more positive than the negative reference input by atleast 0 1V The differential voltage REF sets the full scale range for all input channels Fo Pin 35 Frequency Control Pin Digital input that controls the internal conversion clock rate When Fo is connected to GND the converter uses its internal oscil lator running at 307 2kHz The conversion clock may also be overridden by driving the Fo pin with an external clock in ord
43. er to change the output rate and the digital filter rejection null CA2 Pins 36 37 38 Chip Address Control Pins These pins are configured as a three state LOW HIGH Floating address control bits for the device 120 address Exposed Pad Pin 39 Ground This pin is ground and must be soldered to the PCB ground plane For prototyping purposes this pin may remain floating FUNCTIONAL BLOCK DIAGRAM TEMP SENSOR MUXOUTP ADCINP MUXOUTN ADCINN D DIFFERENTIAL MUX 3RD ORDER e AX MODULATOR 2 WIRE INTERFACE DECIMATING FIR ADDRESS 2499 BD INTERNAL OSCILLATOR AUTOCALIBRATION Fo Q INT EXT AND CONTROL 2 spa 4 SCL 2499fa LI We 11 LIC2499 APPLICATIONS INFORMATION CONVERTER OPERATION Converter Operation Cycle The LTC2499 is a multichannel low power delta sigma analog to digital converter with a 2 wire 12C interface Its operation is made up of four states see Figure 1 The converter operating cycle begins with the conver sion followed by the sleep state and ends with the data input output cycle Initially at power up the LTC2499 performs a conversion Once the conversion is complete the device enters the sleep state While in the sleep state power consumption is reduced by two orders of magnitude The part remains in the sleep state as long it is not addressed for a read write operation The conversion result is held inde
44. finitely in a Static shift register while the part is in the sleep state The device will not acknowledge an external request dur ing the conversion state After a conversion is finished the device is ready to accept a read write request Once the LTC2499 is addressed for a read operation the device begins outputting the conversion result under the control of the serial clock SCL There is no latency in the conver sion result The data output is 32 bits long and contains a 24 bit plus sign conversion result Data is updated on the falling edges of SCL allowing the user to reliably latch data on the rising edge of SCL A new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation The conversion automatically begins at the conclusion of a complete read cycle all 32 bits read out of the device Ease of Use The LTC2499 data output has no latency filter settling delay or redundant data associated with the conversion cycle There is a one to one correspondence between the conversion and the output data Therefore multiplexing multiple analog inputs is straightforward Each conver sion immediately following a newly selected input or mode is valid and accurate to the full specifications of the device The LTC2499 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected This calibration is transparent to the user P
45. gnal Ta 27 C Note 13 27 8 28 0 28 2 mV Internal PTAT Temperature Coefficient 93 5 yV C ELECTRICAL CHARACTERISTICS 2X SPEED The denotes the specifications which apply over the full operating temperature range otherwise specifications are at 25 C Notes 3 4 PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution No Missing Codes 0 1V lt lt Voc FS lt lt FS Note 5 24 Bits Integral Nonlinearity 9V lt Vec lt 5 5V Veer 5 2 5V Note 6 2 10 ppm of VREF 2 7V lt Voc lt 5 51 2 5V ViN CM 1 25V Note 1 ppm of VREF Offset Error 2 5V lt lt Vec GND lt IN INT lt Vece Note 13 e 0 2 2 mV Offset Error Drift 2 5V lt lt Vec GND lt IN 1 lt Vec 100 nV C Positive Full Scale Error 2 5V lt lt Voc 0 75 0 25Vngr e 25 ppm of VREF Positive Full Scale Error Drift 2 5V lt Vgrr lt Voc 0 75Vggr 0 25VREF 0 1 ppm of Negative Full Scale Error 2 5V lt Vgrr lt Voc 0 25Vggr 0 75VREF e 25 ppm of VREF Negative Full Scale Error Drift 2 5V lt Vgrr lt Voc 0 25Vggr 0 75 0 1 ppm of Output Noise 5V lt Vee lt 5 5V Vref 5V GND lt IN IN lt Vee 0 85 VRMS CONVERTER CHARACTERISTICS The denotes the specifications which apply ove
46. he front end circuits and as such its value in nanovolts is nearly constant with reference voltage A decrease in reference voltage will not significantly improve the converter s effec tive resolution On the other hand a decreased reference will improve the converter s overall INL performance Input Voltage Range The analog inputs are truly differential with an absolute common mode range for the CHO CH15 and COM input pins extending from GND 0 3V to Vcc 0 3V Outside these limits the ESD protection devices begin to turn on andthe errors due to inputleakage current increase rapidly Within these limits the 1702499 converts the bipolar dif ferential input signal Viy IN IN where IN and IN are the selected input channels from FS 0 5 VREF to FS 0 5 where Veer REF REF Outside this range the converter indicates the overrange or the underrange condition using distinct output codes see Table 1 Signals applied to the input CHO CH15 COM may extend 300mV below ground and above Vcc In order to limit any fault current resistors of up to 5kQ may be added in series with the input The effect of series resistance on the converter accuracy can be evaluated from the curves presented inthe Input Current Reference Current sections In addition series resistors will introduce a temperature dependent error due to input leakage current A 1nA input leakage current will develop a 1ppm offset erro
47. ie o ow 3 Default at power up 2499fa 17 AL Ure LIC2499 APPLICATIONS INFORMATION The first bit of the second word is the enable bit for the conversion configuration EN2 If this bit is set to 0 then the next conversion is performed using the previously selected converter configuration A new configuration can be loaded into the device by setting EN2 1 see Table 4 The first bit IM is used to select the internal temperature sensor If IM 1 the following conversion will be performed on the internal temperature sensor rather than the selected input channel The next two bits FA and FB are used to set the rejection frequency The final bit SPD is used to select either the 1x output rate if SPD 0 auto calibration is enabled and the offset is continuously calibrated and removed from the final conversion result or the 2x output rate if SPD 1 offset calibration disabled multiplexing output rates Table 4 Converter Configura
48. introduced For relatively small values of external reference capacitance Cngr lt 1nF the voltage on the sampling capacitor settles Voc 5V 80 5V Vin 3 75V 70 1 25V 60 Fo GND TA 25 Crer 0 01 Ogrr 0 001 nF 1 Crer 100 30 Cher OPF T 4FS ERROR ppm gt 10 100 1k 10k 100k Rsounct 2 2499 F13 Figure 13 FS Error vs Rsoync at Small Q T T Crer 1uF 10uF EN Q FS ERROR ppm Cnr 0 01 nF 800 1000 0 200 400 600 Rsource 2499 F15 Figure 15 FS Error vs Rsgurce at Large for reference impedances of many if 100pF up to 10kQ will not degrade the performance see Figures 13 and 14 In cases where large bypass capacitors are required on the reference inputs gt 01 pF full scale and linear ity errors are proportional to the value of the reference resistance Every ohm of reference resistance produces a full scale error of approximately 0 5ppm while operat ing in simultaneous 50Hz 60Hz mode see Figures 15 and 16 If the input common mode voltage is equal to FS ERROR ppm 100 1k 10k 100k RsouRcE 2499 F14 Figure 14 FS Error vs Rsgync at Small
49. nal RC networks Power Up Sequence The 1702499 automatically enters an internal reset state when the power supply voltage Vcc drops below approxi mately 2 0V This feature guarantees the integrity of the conversion result and input channel selection When Vcc rises above this threshold the converter creates an internal power on reset POR signal with a duration of approximately 4ms The POR signal clears all internal registers The conversion immediately following a POR cycle is performed on the input channel IN CHO INT CH1 with simultaneous 50Hz 60Hz rejection and 1x output rate Thefirst conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to 2 7V to 5 5V before the end of the POR interval A new input channel rejection mode speed mode or temperature selection can be programmed into the device during this first data input output cycle Reference Voltage Range This converter accepts atruly differential external reference voltage The absolute common mode voltage range for REF and pins covers the entire operating range of the device GND to Vcc For correct converter operation must be positive REF gt The LTC2499 differential reference input range is 0 1V to Vcc For the simplest operation REF can be shorted to Vcc and can be shorted to GND The converter out put noise is determined by the thermal noise of t
50. o adjacent chan nels can be selected to form a differential input For SGL 1 one of 16 channels is selected as the positive input The negative input is COM for all single ended operations The remaining four bits ODD A2 A1 A0 determine which channel s is are selected and the polarity for a differential input Once the first word is written into the device a second word may be input in orderto selecta configuration mode ACK BY MASTER SUB LSBs gt BY MASTER DATA OUTPUT gt 2499 F03a Figure 3a Timing Diagram for Reading from the LTC2499 ACK BY LTC2499 START BY MASTER ACK OPTIONAL 2ND BYTE ACK LTC2499 LTC2499 DATA INPUT SLEEP gt lt 2499 F03b Figure 3b Timing Diagram for Writing to the LTC2499 2499fa 16 Ln ICD LIC2499 APPLICATIONS INFORMATION Table 3 Channel Selection CHANNEL SELECTION MUX ADDRESS INT INT INT INT INT INT INT INT INT INT INT INT 15 COM 14 IN IN 13 IN IN IN IN IN INT IN IN IN INT IN IN IN goil eoi
51. orm cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors The internal temperature sensor output is 28mV at 27 C 300 K with a slope of 93 5yV C independent of VREF 140000 Vec 5V 5V 120000 SLOPE 314 LSB24 K 100000 80000 DATAOUT24 60000 40000 20000 0 0 100 200 300 400 TEMPERATURE 2499 F04 Figure 4 Internal PTAT Digital Output vs Temperature see Figures 4 and 5 Slope calibration is not required if the reference voltage is known A 5V reference has a slope of 314 LSBso4 C The temperature is calculated from the output code where DATAOUT is the decimal representation ofthe 24 bit result fora 5V reference using the following formula _ DATAOUT 54 814 If a different value of is used the temperature output is DATAOUT VREF ui 1570 Tk inKelvin in Kelvin If the value of is not known the slope is determined by measuring the temperature sensor ata known tempera ture Ty in K and using the following formula DATAOUT N This value of slope can be used to calculate further tem perature readings using DATAOUT24 SLOPE All Kelvin temperature readings can be converted to Tc C using the fundamental equation 1 272 SLOPE ABSOLUTE ERROR
52. pecifications which apply over the full operating temperature range otherwise specifications are at T 25 C Notes 3 4 PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution No Missing Codes 0 1V lt Vrer lt Voc FS lt Vin lt FS Note 5 24 Bits Integral Nonlinearity SV lt Voc lt 5 5V Vngr SV Vin cmy 2 5V Note 6 e 2 10 ppm of VREF 2 7V lt Voc lt 5 5V Vngr 2 5V 1 25V Note 6 e 1 ppm of VREF Offset Error 2 5V lt Vper lt Voc GND lt IN IN lt Note 13 0 5 2 5 uV Offset Error Drift 2 5V lt Vner lt GND lt IN INT lt Voc 10 nV C Positive Full Scale Error 2 5V lt lt Voc 0 75Vggr 0 25Vggr 25 ppm of VREF Positive Full Scale Error Drift 2 5V lt Vggr lt Voc 0 75Vggr 0 25VREF 0 1 ppm of Negative Full Scale Error 2 5V lt Vper lt Voc 0 25 0 75VREF 25 ppm of VREF Negative Full Scale Error Drift 2 5V lt Vref lt Voc 0 25 0 75V per 0 1 ppm of Total Unadjusted Error IV lt Voc lt 5 5V 2 5V Vincom 1 25V 15 ppm of VREF IV lt Voc lt 5 5V SV ViN cM 25V 15 ppm of VREF 2 1N Voc lt 5 5V Veer 2 5V ViN CM 1 25V 15 ppm of VREF Output Noise 2 1N lt lt 5 5V 2 5V lt Vref lt Vec 0 6 VRMS GND lt IN IN lt Vec Note 12 Internal PTAT Si
53. perature 50Hz 60Hz Rejection 1x 1 0 1 X X X X X 1 1 0 1 X Measure Temperature 50Hz Rejection 1x 1 0 1 X X X X X 1 1 1 0 X Measure Temperature 60Hz Rejection 1x 1 0 1 X X X X X 1 X 1 1 X Reserved Do Not Use 2499fa 18 LI Ure LIC2499 APPLICATIONS INFORMATION Speed Mode SPD Every conversion cycle two conversions are combined to remove the offset default mode This result is free from offset and drift In applications where the offset is not critical the auto calibration feature can be disabled with the benefit of twice the output rate While operating in the 2x mode SPD 1 the linearity and full scale errors are unchanged from the 1x mode performance In both the 1x and 2x mode there is no latency This enables input steps or multiplexer changes to settle in a single conversion cycle easing system over head and increasing the effective conversion rate During temperature measurements the 1x mode is always used independent of the value of SPD Temperature Sensor The LTC2499 includes an integrated temperature sen sor The temperature sensor is selected by setting IM 1 During temperature readings MUXOUTN MUXOUTP remains connected to the selected input chan nel The ADC internally connects to the temperature sensor and performs a conversion The digital output is proportional to the absolute tem perature of the device This feature allows the converter to perf
54. r on a 5k resistor if Vpgr 5V This error has a very strong tem perature dependency MUXOUT ADCIN The outputs ofthe multiplexer MUXOUTP MUXOUTN and the inputs to the ADC ADCINP ADCINN can be used to perform input signal conditioning on any of the selected input channels or simply shorted together for direct digitization If an external amplifier is used the 1702499 automatically calibrates both the offset and drift of this circuit and the Easy Drive sampling scheme enables a wide variety of amplifiers to be used In order to achieve optimum performance if an external amplifier is not used short these pins directly together ADCINP to MUXOUTP and ADCINN to MUXOUTN and minimize their capacitance to ground 2499fa LI We 13 LIC2499 APPLICATIONS INFORMATION 26 INTERFACE The LTC2499 communicates through an 12C interface The 26 interface is a 2 wire open drain interface supporting multiple devices and multiple masters on a single bus The connected devices can only pull the data line SDA low and can never drive ithigh SDA is required to be externally connected to the supply through a pull up resistor When the data line is not being driven it is high Data on the 20 bus can be transferred at rates up to 100kbits s in the standard mode and up to 400kbits s in the fast mode Each device on the 126 bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver d
55. r the full operating temperature range otherwise specifications are at T 25 C Note 3 PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC 2 5V lt Vper lt GND lt IN 1 lt Vec Note 5 140 dB Input Common Mode Rejection 50Hz 2 2 5V lt lt Voc GND lt IN 1 lt Vec Notes 5 7 e 140 dB Input Common Mode Rejection 60Hz 2 2 5V lt Vper lt Voc GND lt IN IN lt Vec Notes 5 8 e 140 dB Input Normal Mode Rejection 50Hz 2 2 5V lt lt Voc GND lt IN 1 lt Vec Notes 5 7 e 110 120 dB Input Normal Mode Rejection 60Hz 2 2 5V lt Voc GND lt IN IN lt Notes 5 8 e 110 120 dB Input Normal Mode Rejection 50Hz 60Hz 2 2 5V lt Voc GND lt IN IN lt Notes 5 9 e 87 dB Reference Common Mode Rejection DC 2 5V lt Vper lt Voc GND lt IN IN lt Vec Note 5 120 140 dB Power Supply Rejection DC Veer 2 5V IN GND 120 dB Power Supply Rejection 50Hz 2 60Hz 2 Vngr 2 5V IN GND Notes 7 8 9 120 dB 2499fa LI Ure 3 LTC2499 ANA LOG INPUT AND REFERENCE The denotes the specifications which apply over the full operating temperature range otherwise specifications are at T 25 C Note 3 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN Absolute Common Mode IN
56. tages below FS the conversion result is clamped to the value FS 1LSB Table 2 LTC2499 Status Bits on the falling edges of SCL see Figure The first bit Input Range En NSB is the conversion result sign bit SIG see Tables 1 and Vy gt FS 1 1 2 This bit is high if Vjy gt and low if Viy lt 0 where ov vy FS 1 0 corresponds to the selected input signal IN IN The FS vy lt 0V 0 1 second bit is the most significant bit MSB of the result v lt Fs 0 0 The first two bits SIG and MSB can be used to indicate over and under range conditions see Table 2 If both bits Table 1 Output Data Format Differential Input Voltage Bit31 Bit30 Bit29 Bit28 Bit27 Bit Bits5 0 Vin SIG MSB LSB Sub LSBs Vint 2 FS 1 1 0 0 0 0 00000 FS 1LSB 1 0 1 1 1 1 XXXXX 0 5 FS 1 0 1 0 0 0 XXXXX 0 5 FS 1158 1 0 0 1 1 1 XXXXX 0 1 0 0 0 0 0 XXXXX 1LSB 0 1 1 1 1 1 0 5 FS 0 1 1 0 0 0 0 5 FS 1158 0 1 0 1 1 1 XXXXX FS 0 1 0 0 0 0 XXXXX Vin lt FS 0 0 1 1 1 1 11111 differential input voltage IN IN The full scale voltage FS 0 5 F Sub LSBs are below the 24 bit level They may be included in averaging or discarded without loss of resolution 2499fa AL Ure 15 LIC2499 APPLICATIONS INFORMATION IN
57. tch Input Perturbation of 100 50Hz Notch 0 TT T TTTT Ty 0 T T 1 TFT E 5V E _ Voc 5V MERSU RED DATA Veer 5V Vin p P 5V Veer 5V 20 CALCULATED DATA tt 2 sy 20 7 5V 25V 1 ES 150 OF FULL SCALE n K oe Ta 25 C 2 40 2 2 i 60 60 n S 74 n 3 ix M ly 100 1 f 2 100 f 1 t VN E 120 2 gt Mee 120 E 0 20 40 60 80 100 120 140 160 180 200 220 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY Hz NPUT FREQUENCY Hz 2498 F25 2498 F26 Figure 24 Input Normal Mode Rejection vs Input Frequency with Figure 25 Measure Input Normal Mode Rejection vs Input Input Perturbation of 100 50Hz 60Hz Notch Frequency with Input Perturbation of 150 60Hz Notch 0 Tr Voc 5V g i 150 OF FULL SCALE B cu 5 E 40 i fh 7 P 80 i VLA 2 100 EE Wt NOT 120 b o ad 0 125 25 375 50 625 75 875 100 112 5 125 137 5 150 162 5 175 187 5 200 NPUT FREQUENCY Hz 2498 F27 Figure 26 Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150 50Hz Notch 2499fa 20 AL LIC
58. tion up to 15Hz with no latency When IM 1 temperature measurement SPD will be ignored and the device will operate in 1x mode The configuration remains valid until a new input word with EN 1 thefirstthree bits are 101 forthe first word and EN2 1 for the second write byte is shifted into the device Rejection Mode FA FB The LTC2499 includes a high accuracy on chip oscillator with no required external components Coupled with an integrated fourth order digital low pass filter the 1702499 rejects line frequency noise In the default mode the LTC2499 simultaneously rejects 50Hz and 60Hz by at least 870 If more rejection is required the 1702499 can be configured to reject 50Hz or 60Hz to better than 11008 1 EN SGL ODD 2 M A0 EN2 IM FA FB SPD CONVERTER CONFIGURATION 1 0 0 X X X X X X X X X X Keep Previous 1 0 1 X X X X X 0 X X X X Keep Previous 0 0 1 X X X X X X X X X X Keep Previous 1 0 1 X X X X X 1 0 0 0 0 External Input See Table 3 50Hz 60Hz Rejection 1x 1 0 1 X X X X X 1 0 0 1 0 External Input See Table 3 50Hz Rejection 1x 1 0 1 X X X X X 1 0 1 0 0 External Input See Table 3 60Hz Rejection 1x 1 0 1 X X X X X 1 0 0 0 1 External Input See Table 3 50Hz 60Hz Rejection 2x 1 0 1 X X X X X 1 0 0 1 1 External Input See Table 3 50Hz Rejection 2x 1 0 1 X X X X X 1 0 1 0 1 External Input See Table 3 60Hz Rejection 2x 1 0 1 X X X X X 1 1 0 0 X Measure Tem
59. to be directly digitized while maintaining exceptional DC accuracy The LTC2499 includes a high accuracy temperature sensor and an integrated oscillator This device can be configured to measure an external signal from combi nations of 16 analog input channels operating in single ended or differential modes or its internal temperature sensor The integrated temperature sensor offers 1 30th C resolution and 2 C absolute accuracy The LTC2499 allows a wide common mode input range OV to Vcc independent of the reference voltage Any combination of single ended or differential inputs can be selected and the first conversion after a new channel is selected is valid Access to the multiplexer output en ables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift AX LT LTC and LTM are registered trademarks of Linear Technology Corporation No Latency AX and Easy Drive are trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners TYPICAL APPLICATION Data Acquisition System with Temperature Compensation 2 7V 5 5V io BIT AX ADC 24 WITH EASY DRIVE IE INTERFACE Integrated High Performance Temperature Sensor 5 4 3 2 0 ABSOLUTE ERROR C 5 55 30 5 20 45 70 95 120 TEMPERATURE

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