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ATMEL ATtiny13 Data Sheet

1. Mnemonics Operands Description Operation Flags Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd Rr Add two Registers Rd Rd Rr Z C N V H 1 ADC Rd Rr Add with Carry two Registers Rd Rd Rr C Z C N V H 1 ADIW Rdl K Add Immediate to Word Rdh Rdl Rdh Rdl K Z C N V S 2 SUB Rd Rr Subtract two Registers Rd Rd Rr Z C N V H 1 SUBI Rd K Subtract Constant from Register Rd Rd K Z C N V H 1 SBC Rd Rr Subtract with Carry two Registers Rd Rd Rr C Z C N V H 1 SBCI Rd K Subtract with Carry Constant from Reg Rd Rd K C Z C N V H 1 SBIW Rdl K Subtract Immediate from Word Rdh Rdl lt Rdh Rdl K Z C N V S 2 AND Rd Rr Logical AND Registers Rd lt Rd e Rr ZNV 1 ANDI Rd K Logical AND Register and Constant Rd lt Rd eK Z N V 1 OR Rd Rr Logical OR Registers Rd Rdv Rr Z N V 1 ORI Rd K Logical OR Register and Constant Rd e RdvK Z N V 1 EOR Rd Rr Exclusive OR Registers Rd Rd Rr ZNV 1 COM Rd One s Complement Rd lt OxFF Rd ZC NV 1 NEG Rd Two s Complement Rd 0x00 Rd Z C N V H 1 SBR Rd K Set Bit s in Register Rd RdvK Z N V 1 CBR Rd K Clear Bit s in Register Rd lt Rd e OxFF K Z N V 1 INC Rd Increment Rd Rd 1 ZNV DEC Rd Decrement Rd Rd 1 ZNV 1 TST Rd Test for Zero or Minus Rd Rd Rd Z N V 1 CLR Rd Clear Register Rd Rd amp Rd Z N V 1 SER Rd Set Registe
2. Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 woco FULT ARA r xc fff VIT ADIF ADCL LSB of Result I 3 KE Sample amp Hold d MUX and REFS Conversion MUX and REFS Complete Update Update Figure 45 ADC Timing Diagram Auto Triggered Conversion P One Conversion S Next Conversion Cycle Number i 1 2 3 4 5 6 7 8 9 10 11 12 m i 1 2 soc cock ZZ KIT UFULFLEUIELEFLEFLEUELELI ZZ BUS Lo V ADATE uy iol I I I ADIF i i on I LL gt Sign and MSB of Result Wad Prescaler Reset 2535E AVR 10 04 l Xe Sample amp Hold MUX and REFS Update AMEL I l 4 Prescaler Reset Conversion Complete 83 84 AMEL Figure 46 ADC Timing Diagram Free Running Conversion One Conversion Next Conversion Cycle Number aocciok LI LE LALI YS LIL ADSC l l ADIF l l ADCH x Sign ard MSB of Result ADCL TITT TITT IX LSB of Result l Conversion Complete MUX and REFS Update Table 36 ADC Conversion Time hr Sample amp Hold Sample amp Hold Cycles Conversion Time Condition from Start of Conversion Cycles First conversion 13 5 25 Normal conversions 1 5 13 Auto Triggered conversions 2 13 5 2535E AVR 10 04 Changing Channel or Reference Selection ADC
3. 1 2 85 C 25 C 40 C 0 8 T E o6 38 0 4 0 2 0 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 74 Idle Supply Current vs Vcc Internal RC Oscillator 128 kHz IDLE SUPPLY CURRENT vs Voc INTERNAL WD OSCILLATOR 128 KHZ 0 035 40 C 0 03 25 C 85 C 0 025 z 0 02 3 Q H 0 015 0 01 0 005 0 d T 1 5 2 2 5 3 3 5 4 4 5 5 55 122 ATtinyl3 me 2535E AVR 10 04 Figure 75 Idle Supply Current vs Voc 32 kHz External Clock IDLE SUPPLY CURRENT vs Voc 32kHz EXTERNAL CLOCK 10 9 85 C j 25 C 40 C 6 E 5 8 4 3 2 1 0 d T T 1 1 5 2 2 5 3 9 5 4 4 5 5 55 Voc V Power Down Supply Figure 76 Power Down Supply Current vs Veg Watchdog Timer Disabled Current POWER DOWN SUPPLY CURRENT vs Vcc WATCHDOG TIMER DISABLED 18 ES 85 C 1 4 1 2 d 3 3 08 40 C 0 6 25 C 0 4 0 2 0 T T T T T T 1 5 2 2 5 3 3 5 4 4 5 5 5 5 A MEL 129 2535E AVR 10 04 AMEL Figure 77 Power Down Supply Current vs Voc Watchdog Timer Enabled POWER DOWN SUPPLY CURRENT vs Vcc WATCHDOG TIMER ENABLED 10 40 C 85 C 8 25 C 6 3 6 3 4 3 2 1 0 T T T T T T 1 5 2 2 5 3 3 5 4 45 5 5 5 Vcc V Pin Pull u Figure 78 UO Pin Pull up Resistor Current vs Inp
4. Mnemonics Operands Description Operation Flags Clocks ROR Rd Rotate Right Through Carry Rd 7 lt C Rd n lt Rd n 1 C lt Rd 0 Z C N V 1 ASR Rd Arithmetic Shift Right Rd n Rd n 1 n 0 6 Z C N V 1 SWAP Rd Swap Nibbles Rd 3 0 lt Rd 7 4 Rd 7 4 lt Rd 3 0 None 1 BSET s Flag Set SREG s 1 SREG s 1 BCLR S Flag Clear SREG s lt 0 SREG s 1 BST Rr b Bit Store from Register to T T lt Rr b T 1 BLD Rd b Bit load from T to Register Rd b T None 1 SEC Set Carry Cei C 1 CLC Clear Carry CO C 1 SEN Set Negative Flag Nei N 1 CLN Clear Negative Flag N lt O N 1 SEZ Set Zero Flag Ze Z 1 CLZ Clear Zero Flag Z lt 0 Z 1 SEI Global Interrupt Enable le1 l 1 CLI Global Interrupt Disable 1 0 l 1 SES Set Signed Test Flag EEN S 1 CLS Clear Signed Test Flag Sc 0 S 1 SEV Set Twos Complement Overflow Vel V 1 CLV Clear Twos Complement Overflow Vc 0 V 1 SET Set T in SREG Te1 T 1 CLT Clear T in SREG T lt 0 T 1 SEH Set Half Carry Flag in SREG Ho H d CLH Clear Half Carry Flag in SREG H lt 0O H 1 DATA TRANSFER INSTRUCTIONS MOV Rd Rr Move Between Registers Rd Rr None 1 MOVW Rd Rr Copy Register Word Rd 1 Rd Rr 1 Rr None 1 LDI Rd K Load Immediate Rd K None 1 LD Rd X Load Indirec Rd lt X None 2 LD Rd X Load Indirect and Post Inc Rd X X c X 1 None 2 LD Rd X Load Indirect and Pre Dec X X 1 Rd lt X None 2 LD Rd Y Load Indirect Rd lt Y None 2 LD Rd Y Load Indirect and Post I
5. 8 5 T T T T T T T 60 40 20 0 20 40 60 80 100 Temperature C Figure 116 Calibrated 9 6 MHz RC Oscillator Frequency vs Vcc CALIBRATED 9 6 MHz RC OSCILLATOR FREQUENCY vs Voc 11 10 5 85 C 10 S 25 C 95 g u 40 C 9 8 5 8 1 5 2 2 5 3 8 5 4 4 5 5 5 5 A MEL 149 2535E AVR 10 04 AMEL Figure 117 Calibrated 9 6 MHz RC Oscillator Frequency vs Osccal Value 18 16 14 12 10 Fac MHz CALIBRATED 9 6MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 25 C 72 104 112 120 OSCCAL VALUE Figure 118 Calibrated 4 8 MHz RC Oscillator Frequency vs Temperature 5 1 4 9 4 8 Fnc MHz 4 7 4 6 150 CALIBRATED 4 8 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 20 40 80 100 Temperature C 2535E AVR 10 04 Figure 119 Calibrated 4 8 MHz RC Oscillator Frequency vs Voc CALIBRATED 4 8 MHz RC OSCILLATOR FREQUENCY vs Veg 5 2 85 C 5 T 48 25 C fa 40 C 4 6 4 4 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Voc V Figure 120 Calibrated 4 8 MHz RC Oscillator Frequency vs Osccal Value CALIBRATED 4 8 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 10 9 25 C Frac MHz 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 127 OSCCAL VALUE A MEL 151 2535
6. Instruction Instr 1 5 Instr 2 6 Instr 3 Instr 4 Operation Remarks SDI 0 1000 0000 00 0 0000 0000 00 0_0000_0000_00 Wait after Instr 3 until SDO goes Chip Erase SII 0 0100 1100 00 O0 0110 0100 00 0 0110 1100 00 high for the Chip Erase cycle to SDO X XXXX XXXX XX X NNN XXXX XX X XXXX XXXX XX finish Load Write SDI 0 0001 0000 00 Flash SII 0 0100 1100 00 Enter Flash Programming code Command SDO X_XXXX_XXXX_XX SDI 0 bbbb bbbb 00 0_eeee_eeee_00 0 dddd dddd 00 0 0000 0000 oo Repeat re i SII 0 0000 1100 00 0 0010 1100 O0 0 0011 1100 00 0 0111 1101 oo entire page buffer is filled or until a data within the page is filled See Load Flash SDO X XXXX XXXX XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX Note 1 Page Buffer i SDI 0 0000 0000 00 SII 0 0111 1100 00 Instr 5 SDO X_XXXX_XXXX_XX Wait after Instr 3 until SDO goes Load Flash High SDI 0 0000 000a 00 0 0000 0000 00 0 0000 0000 00 high Repeat Instr 2 3 for each loaded Flash Page until the entire Address and SII 0 0001 1100 00 O 0110 0100 00 0 0110 1100 00 i Program Page spo Flash or all data is programmed X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX Repeat Instr 1 for a new 256 byte page See Note 1 Load Read SDI 0 0000 0010 00 Flash SII 0 0100 1100 00 Enter Flash Read mode Command SDO X_XXXX_XXXX_XX SDI 0 bbbb bbbb 00 0 0000 000a 00 0_0000_0000_00 0 0000 0000 00 Repeat Instr 1 3 6 for each new SII 0 0000 1100 00 0 0001 1100 0
7. Insert nop for synchronization no operation Read port pins i PINB Note 1 For the assembly program two temporary registers are used to minimize the time from pull ups are set on pins 0 1 and 4 until the direction bits are correctly set defin ing bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers As shown in Figure 21 the digital input signal can be clamped to ground at the input of the schmitt trigger The signal denoted SLEEP in the figure is set by the MCU Sleep Controller in Power down mode Power save mode and Standby mode to avoid high power consumption if some input signals are left floating or have an analog signal level close to Voc 2 SLEEP is overridden for port pins enabled as external interrupt pins If the external inter rupt request is not enabled SLEEP is active also for these pins SLEEP is also overridden by various other alternate functions as described in Alternate Port Func tions on page 47 If a logic high level one is present on an asynchronous external interrupt pin config ured as Interrupt on Rising Edge Falling Edge or Any Logic Change on Pin while the external interrupt is not enabled the corresponding External Interrupt Flag will be set 2535E AVR 10 04 Unconnected Pins Alternate Port Functions 2535E AVR 10 04 when resuming from the above mentioned Sleep mode as the clamping in these sleep mode produces the requested logi
8. Turn off global interrupt cli Reset Watchdog Timer wdr Start timed sequence in rl16 WDTCR ori r16 1 WDCE 1 lt lt WDI out WDTCR r16 Got four cycles to set the new values from here Ej Set new prescaler time out value 64K cycles 0 5 s ldi r16 1 lt lt WDE 1 WDP2 1 WDPO out WDTCR r16 Finished setting new values used 2 cycles Turn on global interrupt sei ret C Code Example void WDT Prescaler Change void disable interrupt watchdog reset Start timed sequence WDTCR 1 WDCE 1 WDI Ej ee Set new prescaler time out value 64K cycles 0 5 s WDTCR 1 lt lt WDE 1 WwDP2 1 WDP0 enable interrupt Note 1 The example code assumes that the part specific header file is included Note The Watchdog Timer should be reset before any change of the WDP bits since a change in the WDP bits can result in a time out when switching to a shorter time out period 2535E AVR 10 04 Watchdog Timer Control Register WDTCR BH d 2 2 S 2 2 9 WoT wore wors Woce woe T wore wopr woro worca Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 X 0 0 0 Bit 7 WDTIF Watchdog Timer Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt WDTIF is cleared by hardware when executin
9. PCINT 0 peint in 0 g dl E pin sync cik PCINT 0 in PCMSK x pcint syn pcint setflag PCIF PCINT n pin_lat pin sync pcint in n EL pcint syn Gr pcint setflag g PCIF AMEL 5 External Interrupt registers MCU Control Register MCUCR AMEL The External Interrupt Control Register A contains control bits for interrupt sense control Bit 7 6 5 4 3 2 1 0 Sst Sw T ET cuca Read Write R R W R W R W R W R R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 1 0 ISCO1 ISCOO Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt O is activated by the external pin INTO if the SREG I flag and the corresponding interrupt mask are set The level and edges on the external INTO pin that activate the interrupt are defined in Table 24 The value on the INTO pin is sampled before detecting edges If edge or toggle interrupt is selected pulses that last longer than one clock period will generate an interrupt Shorter pulses are not guaranteed to generate an interrupt If low level interrupt is selected the low level must be held until the completion of the currently executing instruction to generate an interrupt Table 24 Interrupt O Sense Control ISCO1 ISCOO Description 0 0 The low level of INTO generates an interrupt request 0 1 Any logical change on INTO generates an interrupt request 1 0 The falling edge of INTO generates an interrupt req
10. replaces the Output Compare Unit in this case Compare Unit A or Compare Unit B However when using the register or bit defines in a program the precise form must be used i e TCNTO for accessing Timer CounterO counter value and so on The definitions in Table 25 are also used extensively throughout the document Table 25 Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00 MAX The counter reaches its MAXimum when it becomes OxFF decimal 255 TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence The TOP value can be assigned to be the fixed value OxFF MAX or the value stored in the OCROA Register The assignment is dependent on the mode of operation The Timer Counter can be clocked by an internal or an external clock source The clock source is selected by the Clock Select logic which is controlled by the Clock Select CS02 0 bits located in the Timer Counter Control Register TCCROB For details on clock sources and prescaler see Timer Counter Prescaler on page 74 The main part of the 8 bit Timer Counter is the programmable bi directional counter unit Figure 27 shows a block diagram of the counter and its surroundings Figure 27 Counter Unit Block Diagram TOVn DATA BUS Int Req Edge Detector pear Control Logi From Prescaler c bottom top Signal description internal signals count Increment or decrement T
11. 15 lt E T 3 10 5 0 W T T T T 0 0 5 1 15 2 2 5 3 Figure 84 UO Pin Source Current vs Output Voltage Low Power Ports Vec 1 8V UO PIN SOURCE CURRENT vs OUTPUT VOLTAGE LOW POWER PORTS Vcc 1 8V sn 40 C 25 C 6 85 C 5 T4 E r3 23 2 1 0 4 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 A MEL 133 2535E AVR 10 04 AMEL Figure 85 UO Pin Sink Current vs Output Voltage Low Power Ports Voc 5V I O PIN SINK CURRENT vs OUTPUT VOLTAGE LOW POWER PORTS Vcc 5V 40 C 40 25 C 85 85 C _ 30 E E 25 r 20 15 5 0 4 i 0 0 5 1 1 5 2 25 Va V Figure 86 UO Pin Sink Current vs Output Voltage Low Power Ports Vec 2 7V WO PIN SINK CURRENT vs OUTPUT VOLTAGE Low Power Ports Vcc 2 7V i 40 C 16 25 C 14 t 12 E E 10 3 8 6 2 04 T T 1 0 0 5 1 1 5 2 2 5 Va V i4 ATtinyl3 m 2535E AVR 10 04 Figure 87 UO Pin Sink Current vs Output Voltage Low Power Ports Voc 1 8V lo mA Figure 88 UO Pin Source Current vs Output Voltage Voc 5V lon MA I O PIN SINK CURRENT vs OUTPUT VOLTAGE LOW POWER PORTS 1 8V 0 8 1 1 2 1 4 I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Vec 5V 40 C 25 C 85 C 3 4 6 V
12. 60 40 20 0 20 40 60 80 100 Temperature C Figure 110 BOD Thresholds vs Temperature BODLEVEL is 2 7V BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 2 7V 2 9 Rising Vcc 2 8 ke o E o o ZI e 2 7 Falling Voc 2 6 4 i i i 1 60 40 20 0 20 40 60 80 100 Temperature C 1 ATtinyl3 mem 2535E AVR 10 04 Figure 111 BOD Thresholds vs Temperature BODLEVEL is 1 8V BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 1 8V 1 9 Rising Voc 1 85 ke E o 2 Bai ke 1 8 Falling Voc 1 75 60 40 20 0 20 40 60 80 100 Temperature C Figure 112 Bandgap Voltage vs Voc BANDGAP VOLTAGE vs Voc Bandgap Voltage V A MEL 147 2535E AVR 10 04 AMEL Figure 113 Analog Comparator Offset Voltage vs Common Mode Voltage Voc 5V ANALOG COMPARATOR OFFSET vs COMMON MODE VOLTAGE Vcc 5V Comparator Offset Voltage V Common Mode Voltage V Figure 114 Analog Comparator Offset Voltage vs Common Mode Voltage Vcc 2 7V ANALOG COMPARATOR OFFSET vs COMMON MODE VOLTAGE Vec 2 7V 0 003 o o e a 0 0015 Comparator Offset Voltage V 0 0 5 1 15 2 2 5 3 Common Mode Voltage V us ATtinyl3 me Internal Oscillator Speed Figure 115 Calibrated 9 6 MHz RC Oscillator Frequency vs Temperature CALIBRATED 9 6 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 10 3 10 1
13. COMnxO Waveform FOCn Generator OCn OCnx Pin o gt 2 PORT d Q gt DDR Ok The general I O port function is overridden by the Output Compare OCOx from the Waveform Generator if either of the COMOx1 0 bits are set However the OCOx pin direction input or output is still controlled by the Data Direction Register DDR for the port pin The Data Direction Register bit for the OCOx pin DDR OCOx must be set as output before the OCOx value is visible on the pin The port override function is indepen dent of the Waveform Generation mode The design of the Output Compare pin logic allows initialization of the OCOx state before the output is enabled Note that some COMOx1 0 bit settings are reserved for certain modes of operation See 8 bit Timer Counter Register Description on page 68 The Waveform Generator uses the COMOx1 0 bits differently in Normal CTC and PWM modes For all modes setting the COMOx1 0 0 tells the Waveform Generator that no action on the OCOx Register is to be performed on the next Compare Match For com pare output actions in the non PWM modes refer to Table 26 on page 68 For fast PWM mode refer to Table 27 on page 68 and for phase correct PWM refer to Table 28 on page 69 A change of the COMOx1 0 bits state will have effect at the first Compare Match after the bits are written For non PWM modes the action can be forced to have immediate effect by using the FOCOx strobe bits A
14. Default Clock Source AMEL The device has the following clock source options selectable by Flash Fuse bits as shown below The clock from the selected source is input to the AVR clock generator and routed to the appropriate modules Table 2 Device Clocking Options Select Device Clocking Option CKSEL1 0 Calibrated Internal RC Oscillator 01 10 External Clock 00 128 kHz Internal Oscillator 11 Note 1 Forall fuses 1 means unprogrammed while 0 means programmed The various choices for each clocking option is given in the following sections When the CPU wakes up from Power down or Power save the selected clock source is used to time the start up ensuring stable Oscillator operation before instruction execution starts When the CPU starts from reset there is an additional delay allowing the power to reach a stable level before commencing normal operation The Watchdog Oscillator is used for timing this real time part of the start up time The number of WDT Oscillator cycles used for each time out is shown in Table 3 Table 3 Number of Watchdog Oscillator Cycles Typ Time out Number of Cycles 4 ms 512 64 ms 8K 8 192 The device is shipped with CKSEL 10 SUT 10 and CKDIV8 programmed The default clock source setting is therefore the Internal RC Oscillator running at 9 6 MHz with longest start up time and an initial system clock prescaling of 8 This default setting e
15. Vu Input High voltage Except RESET pin 0 6Vc c 9 Voc 0 5 V Vino Input High voltage RESET pin 0 9V50 Vcc 0 5 V V Output Low Voltage lo 20 mA Voc 5V 0 7 V OL PB5 PB1 and PBO lo 10 mA Vee 3V 0 5 V V Output Low Voltage lo 10 mA Voc 5V 0 7 V id PB4 PB3 and PB2 lg 5 mA Voc 3V 0 5 V V Output High voltage lon 20 mA Veg 5V 4 2 V eM PB5 PB1 and PBO lop 10 mA Voc 3V 2 5 V V Output High voltage lop 10 mA Veg 5V 4 2 V d PB4 PB3 and PB2 lop 5 mA Voc 3V 25 V Input Leakage Vcc 5 5V pin low 1 A IL Current UO Pin absolute value H Input Leakage Vcc 5 5V pin high 1 A IH Current I O Pin absolute value H Rest Reset Pull up Resistor 30 80 kQ Rou I O Pin Pull up Resistor 20 50 kQ Active 1MHz Vcc 2V 0 35 mA Active 4MHZ Voc 3V 1 8 mA Active 8MHz Voc 5V 6 mA Power Supply Current i Idle 1MHz Vcc 2V 0 08 0 2 mA ee Idle 4MHz Vog 3V 0 41 1 mA Idle 8MHz Voc DN 1 6 3 mA WDT enabled Voc 3V lt 5 5 HA Power down mode WDT disabled Vcc 3V lt 0 5 2 pA 119 Notes 1 e AMEL All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrol lers manufactured in the same process technology These values are preliminary values representing design targets and will be updated after characterization of actual silicon Max means the highest value where the pin is guaranteed to be read as low Min me
16. 0 0 0 0 0 e Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero e Bit 6 INTFO External Interrupt Flag 0 When an edge or logic change on the INTO pin triggers an interrupt request INTFO becomes set one If the I bit in SREG and the INTO bit in GIMSK are set one the MCU will jump to the corresponding Interrupt Vector The flag is cleared when the inter rupt routine is executed Alternatively the flag can be cleared by writing a logical one to it This flag is always cleared when INTO is configured as a level interrupt Bit 5 PCIF Pin Change Interrupt Flag When a logic change on any PCINT5 0 pin triggers an interrupt request PCIF becomes set one If the I bit in SREG and the PCIE bit in GIMSK are set one the MCU will jump to the corresponding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it ATMEL s 2535E AVR 10 04 AMEL Pin Change Mask Register PCMS K Bit g 6 5 4 3 2 1 0 PCINT1 PCINTO PCMSK Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 6 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bits 5 0 PCINT5 0 Pin Change Enable Mask 5 0 Each PCINT5 0 bit selects whether pin change interrupt is enabled on the correspond ing I O pin If PCINT5 0 is
17. 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved When switching between prescaler settings the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting nor the clock fre quency corresponding to the new setting The ripple counter that implements the prescaler runs at the frequency of the undivided clock which may be faster than the CPU s clock frequency Hence it is not possible to determine the state of the prescaler even if it were readable and the exact time it takes to switch from one clock division to another cannot be exactly predicted From the time the CLKPS values are written it takes between T1 T2 and T1 2 T2 before the new clock frequency is active In this interval 2 active clock edges are pro duced Here T1 is the previous clock period and T2 is the period corresponding to the new prescaler setting 2535E AVR 10 04 Power Management and Sleep Modes MCU Control Register MCUCR 2535E AVR 10 04 The high performance and industry leading code efficiency makes the AVR microcon trollers an ideal choice for low power applications Sleep modes enable the application to shut down unused modules in the MCU thereby saving power The AVR provides various sleep modes allowing the user to tailor the power
18. 1 1 1 0 0 Reserved 1 1 0 1 1 1 1 0 2535E AVR 10 04 Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13 For a general explanation of the AVR interrupt handling refer to Reset and Interrupt Handling on page 10 Interrupt Vectors in ATtiny13 Table 18 Reset and Interrupt Vectors Vector Program No Address Source Interrupt Definition 1 0x0000 RESET External Pin Power on Reset Brown out Reset Watchdog Reset 2 0x0001 INTO External Interrupt Request 0 3 0x0002 PCINTO Pin Change Interrupt Request 0 4 0x0003 TIMO_OVF Timer Counter Overflow 5 0x0004 EE RDY EEPROM Ready 6 0x0005 ANA COMP Analog Comparator 7 0x0006 TIMO COMPA Timer Counter Compare Match A 8 0x0007 TIMO COMPB Timer Counter Compare Match B 9 0x0008 WDT Watchdog Time out 10 0x0009 ADC ADC Conversion Complete If the program never enables an interrupt source the Interrupt Vectors are not used and regular program code can be placed at these locations The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny13 is Address Labels Code Comments 0x0000 rjmp RESET Reset Handler 0x0001 rjmp EXT INTO IRQO Handler 0x0002 rjmp PCINTO PCINTO Handler 0x0003 rjmp TIMO OVF TimerO Overflow Handler 0x0004 rjmp EE RDY EEPROM Ready Handler 0x0005 rjmp ANA COMP Analog Com
19. 10 MHz 2 7 5 5V 0 20 MHz 4 5 5 5V Industrial Temperature Range Low Power Consumption Active Mode 1 MHz 1 8V 240HA Power down Mode 0 1pA at 1 8V AMEL T A 8 bit AVR Microcontroller with 1K Bytes In System Programmable Flash ATtiny13 Preliminary Rev 2535E AVR 10 04 AMEL Pin Configurations Figure 1 Pinout ATtiny13 PDIP SOIC Iw PCINTS RESET ADCO dW PB5 LJ 1 8 O VOC PCINT3 CLKI ADC3 PB3 12 7 O PB2 SCK ADC1 TO PCINT2 PCINT4 ADC2 PB4 O 3 6 LI PB1 MISO AIN1 OCOB INTO PCINT1 GND 14 5 O PBO MOSI AINO OCOA PCINTO PCINTS RESET ADCO dW PB5 VCC PCINT3 CLKI ADC3 PB3 PB2 SCK ADC1 T0 PCINT2 DNC DNC DNC PCINT4 ADC2 PB4 PB1 MISO AIN1 OCOB INTO PCINT1 PBO MOSI AINO OCOA PCINTO NOTE Bottom pad should be soldered to ground DNC Do Not Connect Overview The ATtiny13 is a low power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture By executing powerful instructions in a single clock cycle the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ATtiny13 Block Diagram Figure 2 Block Diagram roc i 8 BIT DATABUS 1 1 i STACK CALIBRATED POINTER INTERNAL i WATCHDOG OSCILLATOR OSCILLATOR 1 vem mE WATCHDOG TIMING AND ub T
20. 11 shortest start up time SUT 1 0 00 Debugwire enabled DWEN 0 or Reset disabled RSTDISBL 0 9 6 MHz internal oscillator CKSEL 1 0 10 shortest start up time SUT 1 0 00 Debugwire enabled DWEN 0 or Reset disabled RSTDISBL 0 4 8 MHz internal oscillator CKSEL 1 0 01 shortest start up time SUT 1 0 00 Debugwire enabled DWEN 0 or Reset disabled RSTDISBL 0 Problem fix Workaround Avoid the above fuse combinations Selecting longer start up time will eliminate the problem 166 ATtiny1 3 El 2535E AVR 10 04 ATtiny13 Rev A 2535E AVR 10 04 4 debugWIRE communication not blocked by lock bits When debugWIRE on chip debug is enabled DWEN 0 the contents of program memory and EEPROM data memory can be read even if the lock bits are set to block further reading of the device Problem fix Workaround Do not ship products with on chip debug of the tiny13 enabled Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs the watchdog will be disabled and the interrupt flag will automatically be cleared This is only applicable in interrupt only mode If the Watchdog is configured to reset the device in the watchdog time out following an interrupt the device works correctly Problem fix Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs This
21. 13 Reset Logic DATA BUS MCU Status Register MCUSR LL x O Q VCC Power on Reset a d T Circuit EXTRF WDRF Brown out BODLEVEL 1 0 4 Pull up Resistor D a a Watchdog ha Timer T u o Watchdog S Oscillator v Clock CK Delay Counters Generator TIMEOUT CKSEL 1 0 SUT 1 0 Table 12 Reset Characteristics Symbol Parameter Condition Min Typ Max Units Power on Reset Threshold Voltage 1 2 V rising Ta 40 85 C Vpor Power on Reset Threshold Voltage 1 1 V falling Ta 40 85 C RESET Pin Threshold Vnsr Voltage Voc 1 8V 5 5V Ort Nee Oe Veg X t Minimum pulse width on 25 RST RESET Pin Voc 1 8V 5 5V H Notes 1 Values are guidelines only Actual values are TBD 2 The Power on Reset will not work unless the supply voltage has been below Vpor falling AMEL s 2535E AVR 10 04 AMEL Power on Reset A Power on Reset POR pulse is generated by an On chip detection circuit The detec tion level is defined in Table 12 The POR is activated whenever Vec is below the detection level The POR circuit can be used to trigger the Start up Reset as well as to detect a failure in supply voltage A Power on Reset POR circuit ensures that the device is reset from Power on Reach ing the Power on Reset threshold voltage invokes the delay counter which determines how lo
22. 31 Shorter pulses are not guaranteed to generate a reset This documentation contains simple code examples that briefly show how to use various parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit defini tions in the header files and interrupt handling in C is compiler dependent Please confirm with the C compiler documentation for more details 2535E AVR 10 04 AVR CPU Core Introduction This section discusses the AVR core architecture in general The main function of the CPU core is to ensure correct program execution The CPU must therefore be able to access memories perform calculations control peripherals and handle interrupts Architectural Overview Figure 3 Block Diagram of the AVR Architecture Data Bus 8 bit Program Status Counter and Control 32x8 Instruction General Register Purpose Interrupt Registrers Unit Instruction a um Decoder a um Y pr Control Lines E N I O Module I O Module 2 I O Module n Oo o o 9 o lt D s 2 o E Direct Addressing EEPROM In order to maximize performance and parallelism the AVR uses a Harvard architecture with separate memories and buses for program and data Instructions in the Program memory are executed with a single level pipelining While one instruction is being exe cuted the next instruction is pre fetched from the P
23. 4 x 0 8 mm Body Lead Pitch 0 50 mm Micro Lead Frame Package MLF A MEL 161 2535E AVR 10 04 AMEL Packaging Information 8P3 Top View eA e End View COMMON DIMENSIONS Unit of Measure inches SYMBOL MIN NOM MAX 0 210 0 115 0 130 0 014 0 018 0 045 0 060 0 030 0 039 0 008 0 010 0 355 0 365 i b2 0 005 0 300 0 310 b 0 240 0 250 Side View Ge 0 300 BSC 0 115 0 130 This drawing is for general information only refer to JEDEC Drawing MS 001 Variation BA for additional information Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS 3 D D1 and E1 dimensions do not include mold Flash or protrusions Mold Flash or protrusions shall not exceed 0 010 inch Eand eA measured with the leads constrained to be perpendicular to datum Pointed or rounded lead tips are preferred to ease insertion b2 and b3 maximum dimensions do not include Dambar protrusions Dambar protrusions shall not exceed 0 010 0 25 mm 01 09 02 TITLE DRAWING NO REV IMEL 2325 Orchard Parkway 8P3 8 lead 0 300 Wide Body Plastic Dual AIMEL San Jose CA 95131 In line Package PDIP SES E 12 ATtinyl3 253
24. 9 volts Wrong values read after Erase Only operation High Voltage Serial Programming Flash EEPROM Fuse and Lock Bits may fail Device may lock for further programming debugWIRE communication not blocked by lock bits Watchdog Timer Interrupt disabled EEPROM can not be written below 1 9 Volt 1 Wrong values read after Erase Only operation At supply voltages below 2 7 V an EEPROM location that is erased by the Erase Only operation may read as programmed 0x00 Problem Fix Workaround If itis necessary to read an EEPROM location after Erase Only use an Atomic Write operation with OxFF as data in order to erase a location In any case the Write Only operation can be used as intended Thus no special considerations are needed as long as the erased location is not read before it is programmed 2 High Voltage Serial Programming Flash EEPROM Fuse and Lock Bits may fail Writing to any of these locations and bits may in some occasions fail Problem Fix Workaround After a writing has been initiated always observe the RDY BSY signal If the writing should fail rewrite until the RDY BSY verifies a correct writing This will be fixed in revision D 3 Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effec tively turning it into an OTP device The following combinations of settings fuse bits will cause this effect 128 kHz internal oscillator CKSEL 1 0
25. ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO ADCSRA Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 ADEN ADC Enable Writing this bit to one enables the ADC By writing it to zero the ADC is turned off Turn ing the ADC off while a conversion is in progress will terminate this conversion Bit 6 ADSC ADC Start Conversion In Single Conversion mode write this bit to one to start each conversion In Free Run ning mode write this bit to one to start the first conversion The first conversion after ADSC has been written after the ADC has been enabled or if ADSC is written at the same time as the ADC is enabled will take 25 ADC clock cycles instead of the normal 13 This first conversion performs initialization of the ADC ADSC will read as one as long as a conversion is in progress When the conversion is complete it returns to zero Writing zero to this bit has no effect e Bit 5 ADATE ADC Auto Trigger Enable ATMEL s AMEL When this bit is written to one Auto Triggering of the ADC is enabled The ADC will start a conversion on a positive edge of the selected trigger signal The trigger source is selected by setting the ADC Trigger Select bits ADTS in ADCSRB e Bit 4 ADIF ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated The ADC Conversion Complete Interrupt is executed if the ADIE bit and the l bit in SREG are se
26. Data Register is not updated until ADCH is read Conse quently if the result is left adjusted and no more than 8 bit precision is required it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH The ADLAR bit in ADMUX and the MUXn bits in ADMUX affect the way the result is read from the registers If ADLAR is set the result is left adjusted If ADLAR is cleared default the result is right adjusted ADC9 0 ADC Conversion Result These bits represent the result from the conversion as detailed in ADC Conversion Result on page 90 Bit 7 6 5 4 3 2 1 0 Jam I I horse Abrst ADS ADCSAB Read Write R R W R R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 5 3 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bits 2 0 ADTS2 0 ADC Auto Trigger Source If ADATE in ADCSRA is written to one the value of these bits selects which source will trigger an ADC conversion If ADATE is cleared the ADTS2 0 settings will have no effect A conversion will be triggered by the rising edge of the selected Interrupt Flag Note that switching from a trigger source that is cleared to a trigger source that is set will generate a positive edge on the trigger signal If ADEN in ADCSRA is set this will start a conversion Switching to Free Running mode ADTS 2 0 0 will not cause a trig ger event even if the ADC Interrupt Flag is set Table 40 ADC Auto
27. None 1 2 BRPL k Branch if Plus if N 0 then PC PC k 1 None 1 2 BRGE k Branch if Greater or Equal Signed if N V 0 then PC PC k 1 None 1 2 BRLT k Branch if Less Than Zero Signed if N V 1 then PC e PC k 1 None 1 2 BRHS k Branch if Half Carry Flag Set if H 1 then PC PC k 1 None 1 2 BRHC k Branch if Half Carry Flag Cleared if H 0 then PC PC k 1 None 1 2 BRTS k Branch if T Flag Set if T 1 then PC PC k 1 None 1 2 BRTC k Branch if T Flag Cleared if T 0 then PC e PC k 1 None 1 2 BRVS k Branch if Overflow Flag is Set if V 1 then PC PC k 1 None 1 2 BRVC k Branch if Overflow Flag is Cleared if V 0 then PC PC k 1 None 1 2 BRIE k Branch if Interrupt Enabled if I2 1 then PC PC k 1 None 1 2 BRID k Branch if Interrupt Disabled if 0 then PC PC k 1 None 1 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register V O P b 1 None 2 CBI P b Clear Bit in I O Register V O P b lt 0 None 2 LSL Rd Logical Shift Left Rd n 1 Rd n Rd 0 lt 0 Z C N V 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 lt 0 Z C N V 1 ROL Rd Rotate Left Through Car Rd 0 lt C Rd n 1 lt Rd n C lt Rd 7 Z C N V 1 AIMEL s 2535E AVR 10 04 AIMEL HE O
28. PUOV 0 0 0 DDOE 0 0 0 DDOV 0 0 0 PVOE 0 OCOB Enable OCOA Enable PVOV 0 OCOB OCOA PTOE 0 0 0 DIEOE PCINT2 PCIE ADC1D PCINT1 PCIE AIN1D PCINTO PCIE AINOD DIEOV ADC1D AIN1D AINOD DI TO INTO PCINT1 Input PCINTO Input PCINT2 Input AIO ADC1 Input Analog Comparator Analog Comparator Negative Input Positive Input 2535E AVR 10 04 AMEL 51 Register Description for l O Ports Port B Data Register PORTB AMEL Bit 7 6 5 4 3 2 1 0 gt Forres Portsa pores PORTS2 PORTSI PORTSO PORTS Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Port B Data Direction Register DDRB Bit 7 6 5 4 3 2 1 0 KENNEL ee DDB2 EEE SE Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Port B Input Pins Address PINB Bit 7 6 5 4 3 2 1 0 Pines Pins Pines PINE PINS PINEO PINE Read Write R R R W R W R W R W R W R W Initial Value 0 0 N A N A N A N A N A N A 52 ATtiny1 3 EES 2535E AVR 10 04 External Interrupts Pin Change Interrupt Timing 2535E AVR 10 04 The External Interrupts are triggered by the INTO pin or any of the PCINT5 0 pins Observe that if enabled the interrupts will trigger even if the INTO or PCINT5 0 pins are configured as outputs This feature provides a way of generating a software interrupt Pin change interrupts PCI will trigger if any enabled PCINT5 0 pin toggles The PCMSK Register control whi
29. RESET Pin High voltage Threshold for Latching Prog enable Voc Vuvner luvnsr 4 5V 12V 100 ns 5 5V 12 100 ns The loaded command and address are retained in the device during programming For efficient programming the following should be considered e The command needs only be loaded once when writing or reading multiple memory locations e Skip writing the data value OxFF that is the contents of the entire EEPROM unless the EESAVE Fuse is programmed and Flash after a Chip Erase e Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM This consideration also applies to Signature bytes reading 12 ATtinyl3 me 2535E AVR 10 04 Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus Lock bits The Lock bits are not reset until the Program memory has been completely erased The Fuse bits are not changed A Chip Erase must be performed before the Flash and or EEPROM are re programmed Note 1 The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed 1 Load command Chip Erase see Table 55 2 Wait after Instr 3 until SDO goes high for the Chip Erase cycle to finish 3 Load Command No Operation A MEL 113 2535E AVR 10 04 AMEL Programming the Flash The Flash is organized in pages see Table 50 on page 109 When programming the Flash the program data is latched into a page buffer This allo
30. Refer to page 41 for details on operation of the Watchdog Timer Figure 18 Watchdog Reset During Operation Vcc RESET gt i 1 CK Cycle WDT TIME OUT 1 i l H t RESET tro na NV TIME OUT i Li INTERNAL RESET The MCU Status Register provides information on which reset source caused an MCU Reset Bit 7 6 5 4 3 2 1 0 C T d womr EE ExT PORF McusR Read Write R R R R R W R W R W R W Initial Value 0 0 0 0 See Bit Description e Bits 7 4 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bit3 WDRF Watchdog Reset Flag This bit is set if a Watchdog Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 2 BORF Brown out Reset Flag This bit is set if a Brown out Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 1 EXTRF External Reset Flag 2535E AVR 10 04 Internal Voltage Reference Voltage Reference Enable Signals and Start up Time 2535E AVR 10 04 This bit is set if an External Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 0 PORF Power on Reset Flag This bit is set if a Power on Reset occurs The bit is reset only by writing a logic zero to the flag To make use of the Reset Flags to identify a reset condition the user should read and then reset the MCUSR as early as possib
31. Speed Grades changed 12MHz to 10MHz 24MHz to 20M Hz Updated Serial Programming Instruction Set on page 109 Updated Maximum Speed vs VCC on page 121 Updated Ordering Information on page 161 C code examples updated to use legal IAR syntax Replaced occurrences of WDIF with WDTIF and WDIE with WDTIE Updated Stack Pointer on page 9 Updated Calibrated Internal RC Oscillator on page 23 Updated Oscillator Calibration Register OSCCAL on page 23 Updated typo in introduction on Watchdog Timer on page 36 Updated ADC Conversion Time on page 84 Updated Serial Downloading on page 106 Updated Electrical Characteristics on page 119 Updated Ordering Information on page 161 Removed rev C from Errata on page 166 Updated Figure 2 on page 3 Updated Table 12 on page 31 Table 17 on page 40 Table 37 on page 91 and Table 57 on page 120 Updated Calibrated Internal RC Oscillator on page 23 Updated the whole Watchdog Timer on page 36 168 ATtinyl3 me 2535E AVR 10 04 2535E AVR 10 04 Updated Figure 54 on page 106 and Figure 57 on page 111 Updated registers MCU Control Register MCUCR on page 50 Timer Counter Control Register B TCCROB on page 71 and Digital Input Disable Register 0 DIDRO on page 78 Updated Absolute Maximum Ratings and DC Characteristics in Electrical Characteristics on page 119 Added Maximum Speed vs VCC on page 121 Updated ADC Characte
32. a c gt o ze H o ot AP MEE aa Ec EAS B ss Sleep Mode D o D u S our o sts Idle X X X X X X X X ADC Noise Reduction X X x X X X Power down x X Note 1 For INTO only level interrupt 28 ATtiny1 3 EE 2535E AVR 10 04 Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown out Detector Internal Voltage Reference Watchdog Timer Port Pins 2535E AVR 10 04 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system In general sleep modes should be used as much as possi ble and the sleep mode should be selected so that as few as possible of the device s functions are operating All functions not needed should be disabled In particular the following modules may need special consideration when trying to achieve the lowest possible power consumption If enabled the ADC will be enabled in all sleep modes To save power the ADC should be disabled before entering any sleep mode When the ADC is turned off and on again the next conversion will be an extended conversion Refer to Analog to Digital Con verter on page 79 for details on ADC operation When entering Idle mode the Analog Comparator should be disabled if not used When entering ADC Noise Reduction mode the Analog Comparator should be disabled In the other sleep modes the Analog Comparator is automatically disabled However if the Analog Comparator is set up to
33. above the nominal frequency Otherwise the EEPROM or Flash ATMEL 2 External Clock AMEL write may fail Note that the Oscillator is intended for calibration to 9 6 MHz or 4 8 MHz Tuning to other values is not guaranteed as indicated in Table 6 Avoid changing the calibration value in large steps when calibrating the calibrated inter nal RC Oscillator to ensure stable operation of the MCU A variation in frequency of more than 2 from one cycle to the next can lead to unpredictable behavior Changes in OSCCAL register should not exceed 0x20 for each calibration Table 6 Internal RC Oscillator Frequency Range Min Frequency in Percentage of Max Frequency in Percentage of OSCCAL Value Nominal Frequency Nominal Frequency 0x00 50 100 Ox3F 7596 150 Ox7F 100 200 To drive the device from an external clock source CLKI should be driven as shown in Figure 12 To run the device on an external clock the CKSEL Fuses must be pro grammed to 00 Figure 12 External Clock Drive Configuration EXTERNAL CLOCK CLKI SIGNAL GND When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 7 Table 7 Start up Times for the External Clock Selection Start up Time from Power Additional Delay from SUT1 0 down and Power save Reset Recommended Usage 00 6 CK 14CK BOD enabled 01 6 CK 14CK 4 ms Fast rising power 10 6 CK 14CK 4 64 ms Slowly ri
34. and Inter rupt Stacks are located This Stack space in the data SRAM is automaticall defined to the last address in SRAM during power on reset The Stack Pointer must be set to point above 0x60 The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt The Stack Pointer is incre mented by one when data is popped from the Stack with the POP instruction and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI The AVR Stack Pointer is implemented as two 8 bit registers in the I O space The num ber of bits actually used is implementation dependent Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed In this case the SPH Register will not be present Bit 15 14 13 12 11 10 9 8 ser Ses Ses smi sm s sm sL 7 6 5 4 3 2 1 0 Read Write R W R W R W DAN R W R W R W R W Initial Value 1 0 0 1 1 1 1 1 o AMEL Instruction Execution Timing Reset and Interrupt Handling AMEL This section describes the general access timing concepts for instruction execution The AVR CPU is driven by the CPU clock clkcp directly generated from the selected clock source for the chip No internal clock division is used Figure 6 shows the parallel instruction fetches an
35. and peripherals are placed in the I O space All I O locations may be accessed by the LD LDS LDD and ST STS STD instructions transferring data between the 32 general purpose working registers and the I O space I O Registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instruc tions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions Refer to the instruction set section for more details When using the I O specific commands IN and OUT the I O addresses 0x00 Ox3F must be used When addressing I O Registers as data space using LD and ST instructions 0x20 must be added to these addresses For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written Some of the Status Flags are cleared by writing a logical one to them Note that unlike most other AVRs the CBI and SBI instructions will only operate on the specified bit and can therefore be used on registers containing such Status Flags The CBI and SBI instructions work with registers 0x00 to Ox1F only The I O and Peripherals Control Registers are explained in later sections 2535E AVR 10 04 System Clock and Clock Options Clock Systems and their Distribution 2535E AVR 10 04 Figure 11 presents the principal clock systems in the AVR and their distribution All of the clocks need not be active at a given ti
36. applied to ADCn is subjected to the pin capacitance and input leakage of that pin regardless of whether that channel is selected as input for the ADC When the chan nel is selected the source must drive the S H capacitor through the series resistance combined resistance in the input path The ADC is optimized for analog signals with an output impedance of approximately 10 kQ or less If such a source is used the sampling time will be negligible If a source with higher impedance is used the sampling time will depend on how long time the source needs to charge the S H capacitor with can vary widely The user is recom mended to only use low impedant sources with slowly varying signals since this minimizes the required charge transfer to the S H capacitor Signal components higher than the Nyquist frequency fapc 2 should not be present to avoid distortion from unpredictable signal convolution The user is advised to remove high frequency components with a low pass filter before applying the signals as inputs to the ADC Figure 47 Analog Input Circuitry ADCn wa 1 1 100 kQ Gau 14 pF li Veg ATMEL e AMEL Analog Noise Canceling Digital circuitry inside and outside the device generates EMI which might affect the Techniques accuracy of analog measurements If conversion accuracy is critical the noise level can be reduced by applying the following techniques 1 Keep analog signal paths as short as possible Make sure analog
37. before the Interrupt Flag used as trigger source is cleared When updating ADMUX in one of these conditions the new settings will affect the next ADC conversion When changing channel selections the user should observe the following guidelines to ensure that the correct channel is selected In Single Conversion mode always select the channel before starting the conversion The channel selection may be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the conversion to complete before changing the channel selection In Free Running mode always select the channel before starting the first conversion The channel selection may be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the first conversion to complete and then change the channel selection Since the next conversion has already started automati cally the next result will reflect the previous channel selection Subsequent conversions will reflect the new channel selection AMEL s AMEL ADC Voltage Reference The reference voltage for the ADC Vggp indicates the conversion range for the ADC Single ended channels that exceed Vper will result in codes close to OXSFF Vref can be selected as either Voc or internal 1 1V reference or external AREF pin The first ADC conversion result after switching reference voltage source may be inaccurate and the user is advised to discard thi
38. by the AVR Break instruction Set ting a Break Point in AVR Studio will insert a BREAK instruction in the Program memory The instruction replaced by the BREAK instruction will be stored When pro gram execution is continued the stored instruction will be executed before continuing from the Program memory A break can be inserted manually by putting the BREAK instruction in the program The Flash must be re programmed each time a Break Point is changed This is auto matically handled by AVR Studio through the debugWIRE interface The use of Break Points will therefore reduce the Flash Data retention Devices used for debugging pur poses should not be shipped to end customers The debugWIRE communication pin dW is physically located on the same pin as External Reset RESET An External Reset source is therefore not supported when the debugWIRE is enabled The debugWIRE system accurately emulates all I O functions when running at full speed i e when the program in the CPU is running When the CPU is stopped care must be taken while accessing some of the I O Registers via the debugger AVR Stu dio See the debugWIRE documentation for detailed description of the limitations A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes This will increase the power consumption while in sleep Thus the DWEN Fuse should be disabled when debugWire is not used The following section describes the registe
39. can be set high to commence normal operation 8 Power off sequence if needed Set RESET to 1 Turn Voc power off A MEL 107 2535E AVR 10 04 AMEL Table 49 Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay lwp FLASH 4 5 ms lwp EEPROM 4 0 ms lwp ERASE 4 0 ms twp FUSE 4 5 ms Figure 55 Serial Programming Waveforms MOSI MISO SAMPLE 0s ATtinyl3 me Table 50 Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash Read Program Memory 0010 H000 0000 000a bbbb bbbb oooo oooo Read H high or low data o from Program memory at word address a b Load Program Memory Page 0100 H000 000x xxxx xxxx bbbb iiii iiii Write H high or low data i to Program memory page at word address b Data low byte must be loaded before Data high byte is applied within the same address Write Program Memory Page 0100 1100 0000 000a bbbb xxxx xxxx xxxx Write Program memory Page at address a b Read EEPROM Memory 1010 0000 000x xxxx xxbb bbbb 0000 oooo Read data o from EEPROM memory at address b Wr
40. for one timer clock cycle The timing diagram for the phase correct PWM mode is shown on Figure 32 The TCNTO value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNTO slopes repre sent Compare Matches between OCROx and TCNTO Figure 32 Phase Correct PWM Mode Timing Diagram TCNTn OCn COMnx1 0 2 OCn COMnx1 0 3 The Timer Counter Overflow Flag TOVO is set each time the counter reaches BOT TOM The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value In phase correct PWM mode the compare unit allows generation of PWM waveforms on the OCOx pins Setting the COMOx1 0 bits to two will produce a non inverted PWM An inverted PWM output can be generated by setting the COMOx1 0 to three Setting the COMOAO bits to one allows the OCOA pin to toggle on Compare Matches if the WGM02 bit is set This option is not available for the OCOB pin See Table 28 on page 69 The actual OCOx value will only be visible on the port pin if the data direction for the port pin is set as output The PWM waveform is generated by clearing or setting the OCOx Register at the Compare Match between OCROx and TCNTO when the counter incre ments and setting or clearing the OCOx Register at Compare Match between OCROx AMEL s 2535E AVR 10 04 Timer Co
41. function of some of the port pins does not affect the use of the other pins in the port as general digital I O The ports are bi directional I O ports with optional internal pull ups Figure 21 shows a functional description of one l O port pin here generically called Pxn Figure 21 General Digital 1 0 DATA BUS SYNCHRONIZER clk yo B WRITE DDRx PULLUP DISABLE RDx PUD A x SLEEP SLEEP CONTROL WRx WRITE PORTx Clk o WO CLOCK RRx READ PORTx REGISTER RPx READ PORTx PIN WPx WRITE PINx REGISTER Note 1 WRx WPx WDx RRx RPx and RDx are common to all pins within the same port Ou SLEEP and PUD are common to all ports Each port pin consists of three register bits DDxn PORTxn and PINxn As shown in Register Description for I O Ports on page 52 the DDxn bits are accessed at the DDRx UO address the PORTxn bits at the PORTx I O address and the PINxn bits at the PINx I O address The DDxn bit in the DDRx Register selects the direction of this pin If DDxn is written logic one Pxn is configured as an output pin If DDxn is written logic zero Pxn is config ured as an input pin If PORTxn is written logic one when the pin is configured as an input pin the pull up resistor is activated To switch the pull up resistor off PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri stated when reset condition becomes active even if no clocks are running
42. it is sufficient to read ADCH Otherwise ADCL must be read first then ADCH to ensure that the content of the data registers belongs to the same conversion Once ADCL is read ADC access to data registers is blocked This means that if ADCL has been read and a conversion completes before ADCH is read neither register is updated and the result from the con 2535E AVR 10 04 version is lost When ADCH is read ADC access to the ADCH and ADCL Registers is re enabled The ADC has its own interrupt which can be triggered when a conversion completes When ADC access to the data registers is prohibited between reading of ADCH and ADCL the interrupt will trigger even if the result is lost Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit ADSC This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed If a different data channel is selected while a conversion is in progress the ADC will finish the current conversion before performing the channel change Alternatively a conversion can be triggered automatically by various sources Auto Trig gering is enabled by setting the ADC Auto Trigger Enable bit ADATE in ADCSRA The trigger source is selected by setting the ADC Trigger Select bits ADTS in ADCSRB see description of the ADTS bits for a list of the trigger sources When a positive edge occurs on the selected trigg
43. lt WDRF out MCUSR r16 Write logical one to WDCE and WDE Keep old prescaler setting to prevent unintentional time out in rl16 WDTCR ori r16 1 WDCE 1 WDi out WDTCR r16 Turn off WDT ldi r16 0 lt lt WDE out WDTCR r16 Ej Turn on global interrupt sei ret C Code Example void WDT off void disable interrupt watchdog reset Clear WDRF in MCUSR MCUSR amp 1 WDRF Write logical one to WDCE and WDE Keep old prescaler setting to prevent unintentional time out R WDTCR 1 WDCE 1 WDE Turn off WDT WDTCR 0x00 enable interrupt Note 1 The example code assumes that the part specific header file is included Note If the Watchdog is accidentally enabled for example by a runaway pointer or brown out condition the device will be reset and the Watchdog Timer will stay enabled If the code is not set up to handle the Watchdog this might lead to an eternal loop of time out resets To avoid this situation the application software should always clear the AMEL s 2535E AVR 10 04 AMEL Watchdog System Reset Flag WDRF and the WDE control bit in the initialisation rou tine even if the Watchdog is not in use The following code example shows one assembly and one C function for changing the time out value of the Watchdog Timer Assembly Code Example WDT Prescaler Change
44. programming the EEPROM the data is latched into a page buffer This allows one page of data to be programmed simultaneously The programming algorithm for the EEPROM Data mem ory is as follows refer to Table 55 1 Load Command Write EEPROM 2 Load EEPROM Page Buffer 3 Program EEPROM Page Wait after Instr 2 until SDO goes high for the Page Programming cycle to finish 4 Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed 5 End Page Programming by Loading Command No Operation The algorithm for reading the Flash memory is as follows refer to Table 55 1 Load Command Read Flash 2 Read Flash Low and High Bytes The contents at the selected address are avail able at serial output SDO The algorithm for reading the EEPROM memory is as follows refer to Table 55 1 Load Command Read EEPROM 2 Read EEPROM Byte The contents at the selected address are available at serial output SDO The algorithms for programming and reading the Fuse Low High bits and Lock bits are shown in Table 55 The algorithms for reading the Signature bytes and Calibration byte are shown in Table 55 Set SCI to 0 Set RESET to 1 Turn Voc power off A MEL 115 AMEL Table 55 High voltage Serial Programming Instruction Set for ATtiny13 Instruction Format
45. sl E sf E The Timer Counter Overflow Flag TOVO is set each time the counter reaches TOP If the interrupt is enabled the interrupt handler routine can be used for updating the com pare value In fast PWM mode the compare unit allows generation of PWM waveforms on the OCOXx pins Setting the COMOx1 0 bits to two will produce a non inverted PWM and an inverted PWM output can be generated by setting the COMOx1 0 to three Setting the COMOA1 0 bits to one allows the ACOA pin to toggle on Compare Matches if the WGM02 bit is set This option is not available for the OCOB pin See Table 27 on page 68 The actual OCOx value will only be visible on the port pin if the data direction for the port pin is set as output The PWM waveform is generated by setting or clearing the OCOx Register at the Compare Match between OCROx and TCNTO and clearing or setting the OCOx Register at the timer clock cycle the counter is cleared changes from TOP to BOTTOM The PWM frequency for the output can be calculated by the following equation _ Io vo focnxPwM zd N 256 The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCROA Register represents special cases when generating a PWM waveform output in the fast PWM mode If the OCROA is set equal to BOTTOM the output will be a narrow spike for each MAX 1 timer clock cycle Setting the OCROA equal to MAX will result in a constantly high or low output depending
46. software assigned pin value a nop instruction must be inserted as indicated in Figure 23 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the synchronizer is one system clock period Figure 23 Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK ru pF F4 rA r16 l OxFF INSTRUCTIONS nop SYNC LATCH SEEN e GE PINxn NEED SS r17 0x00 i OxFF t pd bh mmm ATMEL s Digital Input Enable and Sleep Modes AMEL The following code example shows how to set port B pins 0 and 1 high 2 and 3 low and define the port pins from 4 to 5 as input with a pull up assigned to port pin 4 The result ing pin values are read back again but as previously discussed a nop instruction is included to be able to read back the value recently assigned to some of the pins Assembly Code Example Define pull ups and set outputs high Define directions for port pins ldi rie 1 PB4 1 PB1 1 lt lt PBO ldi r17 1 lt lt DDB3 1 lt lt DDB2 1 DDB1 1 lt lt DDBO out PORTB r16 out DDRB r17 Insert nop for synchronization nop Read port pins in r16 PINB C Code Example unsigned char i Define pull ups and set outputs high Define directions for port pins PORTB 1 PB4 1 PB1 1 PB0 DDRB 1 lt lt DDB3 1 lt lt DDB2 1 lt lt DDB1 1 lt lt DDBO
47. the update of the OCROx Compare Registers to either top or bottom of the counting sequence The synchronization prevents the occurrence of odd length non symmetrical PWM pulses thereby making the output glitch free The OCROx Register access may seem complex but this is not case When the double buffering is enabled the CPU has access to the OCROx Buffer Register and if double buffering is disabled the CPU will access the OCROx directly In non PWM waveform generation modes the match output of the comparator can be forced by writing a one to the Force Output Compare FOCOx bit Forcing Compare Match will not set the OCFOx Flag or reload clear the timer but the OCOx pin will be updated as if a real Compare Match had occurred the COMOx1 0 bits settings define whether the OCOx pin is set cleared or toggled All CPU write operations to the TCNTO Register will block any Compare Match that occur in the next timer clock cycle even when the timer is stopped This feature allows OCROx to be initialized to the same value as TCNTO without triggering an interrupt when the Timer Counter clock is enabled Since writing TCNTO in any mode of operation will block all Compare Matches for one timer clock cycle there are risks involved when changing TCNTO when using the Output Compare Unit independently of whether the Timer Counter is running or not If the value written to TCNTO equals the OCROx value the Compare Match will be missed resulting in inc
48. to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cycles the Program Counter two bytes is popped back from the Stack the Stack Pointer is incremented by two and the I bit in SREG is set 2535E AVR 10 04 AVR ATtiny13 Memories In System Re programmable Flash Program Memory 2535E AVR 10 04 This section describes the different memories in the ATtiny13 The AVR architecture has two main memory spaces the Data memory and the Program memory space In addition the ATtiny13 features an EEPROM Memory for data storage All three memory spaces are linear and regular The ATtiny13 contains 1K byte On chip In System Reprogrammable Flash memory for program storage Since all AVR instructions are 16 or 32 bits wide the Flash is orga nized as 512 x 16 The Flash memory has an endurance of at least 10 000 write erase cycles The ATtiny13 Program Counter PC is nine bits wide thus addressing the 512 Program memory locations Memory Programming on page 102 contains a detailed description on Flash data serial downloading using the SPI pins Constant tables can be allocated within the entire Program memory address space see the LPM Load Program memory instruction description Timing diagrams for instruction fetch and execution are presented in Instruction Execu tion Timing on page 10 Figure 8 Program Memory Map Program Memory
49. unprogrammed EESAVE 6 preserved through the EEPROM not preserved Chip Erase WDTON 5 Watchdog Timer always on 1 unprogrammed CKDIV8 4 Divide clock by 8 0 programmed SUT1 3 Select start up time 1 unprogrammed SUTO 2 Select start up time 0 programmed CKSEL1 1 Select Clock source 1 unprogrammed CKSELO 0 Select Clock source 0 programmed Notes 1 The SPIEN Fuse is not accessible in SPI Programming mode 2 See Watchdog Timer Control Register WDTCR on page 39 for details Program 2535E AVR 10 04 ming this fues will disable the Watchdog Timer Interrupt The default value of SUT1 0 results in maximum start up time for the default clock source See Table 5 on page 23 for details The default setting of CKSEL1 0 results in internal RC Oscillator 9 6 MHz See Table 4 on page 23 for details See System Clock Prescaler on page 25 for details A MEL 103 AMEL The status of the Fuse bits is not affected by Chip Erase Note that the Fuse bits are locked if Lock bit1 LB1 is programmed Program the Fuse bits before programming the Lock bits 14 ATtinyl3 m Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode This does not apply to the EESAVE Fuse which will take effect once it is programmed The fuses are also latched on Power up in Normal mode Signature Bytes All Atmel microcontr
50. 0 0 0110 1000 00 0 0110 1100 OO address Repeat Instr 2 for a new Read Flash Low SDO x_xxxx_xxxx_xx X_XXXX_XXXX_XX X_XXXX_XXXX_XX o qqqq qqqx xx 256 byte page and High Bytes Spi 0_0000_0000_00 o 0000 0000 00 SII 0 0111 1000 00 O 0111 1100 00 Instr 5 6 SDO X XXXX XXXX XX D Pppp pppx xx Load Write SDI 0 0001 0001 00 EEPROM SII 0 0100 1100 00 Edd EEN Command SDO X_XXXX_XXXX_XX i Load EEPROM SP 9 00bb_bbbb_00 0 eeee eeee 00 0 0000 0000 00 0 0000 0000 00 ee SC M em SE 93 SII 0 0000 1100 00 0 0010 1100 O0 0_0110_1101_00 0 0110 1100 oo Page buffer is filled or until all data Page Buffer within the page is filled See Note SDO X XXXX XXXX XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX 2 Wait after Instr 2 until SDO goes Be SDI 0 0000 0000 00 0 0000 0000 00 high Repeat Instr 1 2 for each GC Page SII 0 0110 0100 00 O 0110 1100 00 loaded EEPROM page until the SDO x Xx XXXX xx X_XXXX_XXXX_XX entire EEPROM or all data is programmed SDI 0 00bb bbbb 00 0 eeee eeee 00 0_0000_0000_00 0 0000 0000 00 Repeat Instr 1 5 for each new SII 0 0000 1100 00 O 0010 1100 00 0 0110 1101 00 0 0110 0100 OO address Wait after Instr 5 until Write EEPROM BDO x XXxX XXXX XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_Xxxx_xxxx_xx SDO goes high See Note 3 Byte SDI 0 0000 0000 00 SII 0 0110 1100 00 Instr 5 SDO X_XXXX_XXXX_XX 116 2535E AVR 10 04 Table 55 High voltage Serial Pro
51. 0 04 COMO1 COMOO Description 0 0 Normal port operation OCOB disconnected 0 1 Toggle OCOB on Compare Match 1 0 Clear OCOB on Compare Match 1 1 Set OCOB on Compare Match Table 27 shows the COMOB1 0 bit functionality when the WGM02 0 bits are set to fast PWM mode Table 30 Compare Output Mode Fast PWM Mode COMO1 COMOO Description 0 0 Normal port operation OCOB disconnected 0 1 Reserved 1 0 Clear OCOB on Compare Match set OCOB at TOP 1 1 Set OCOB on Compare Match clear OCOB at TOP Note 1 A special case occurs when OCROB equals TOP and COMOBI is set In this case the Compare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 63 for more details AMEL 69 AMEL Table 28 shows the COMOB1 0 bit functionality when the WGM02 0 bits are set to phase correct PWM mode Table 31 Compare Output Mode Phase Correct PWM Mode COMOA1 COMOAO Description 0 0 Normal port operation OCOB disconnected 0 1 Reserved 1 0 Clear OCOB on Compare Match when up counting Set OCOB on Compare Match when down counting 1 1 Set OCOB on Compare Match when up counting Clear OCOB on Compare Match when down counting Note 1 A special case occurs when OCROB equals TOP and COMOBI is set In this case the Compare Match is ignored but the set or clear is done at TOP See Phase Cor rect PWM Mode on page 65 for more detail
52. 00 Command SDO X XXXX XXX XX Note a address high bits b address low bits d data in high bits e data in low bits p data out high bits q data out low bits x don t care 1 Lock Bit1 2 Lock Bit2 3 CKSELO Fuse 4 CKSEL1 Fuse 5 SUTO Fuse 6 SUT1 Fuse 7 CKDIV8 Fuse 8 WDTON Fuse 9 EESAVE Fuse A SPIEN Fuse B RSTDISBL Fuse C BODLEVELO Fuse D BODLEVEL1 Fuse E MONEN Fuse F SELFPRGEN Fuse Notes 1 For page sizes less than 256 words parts of the address bbbb bbbb will be parts of the page address 2 For page sizes less than 256 bytes parts of the address bbbb bbbb will be parts of the page address 3 The EEPROM is written page wise But only the bytes that are loaded into the page are actually written to the EEPROM Page wise EEPROM access is more efficient when multiple bytes are to be written to the same page Note that auto erase of EEPROM is not available in High voltage Serial Programming only in SPI Programming 2535E AVR 10 04 AMEL 117 High voltage Serial Programming AMEL Figure 60 High voltage Serial Programming Timing Characteristics SDI PBO SII PB1 SCI PB3 SDO PB2 Table 56 High voltage Serial Programming Characteristics Voc 5 0V 10 Unless otherwise noted Symbol Parameter Min Typ Max Units Luet SCI PB3 Pulse Width High 110 ns tsi su SCI PB3 Pulse Width Low 110 ns tysk SDI PBO S
53. 0x0000 OxO1FF ATMEL SRAM Data Memory Data Memory Access Times AMEL Figure 9 shows how the ATtiny13 SRAM Memory is organized The lower 160 Data memory locations address both the Register File the UO memory and the internal data SRAM The first 32 locations address the Register File the next 64 locations the standard I O memory and the last 64 locations address the internal data SRAM The five different addressing modes for the Data memory cover Direct Indirect with Displacement Indirect Indirect with Pre decrement and Indirect with Post increment In the Register File registers R26 to R31 feature the indirect addressing pointer registers The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y or Z register When using register indirect addressing modes with automatic pre decrement and post increment the address registers X Y and Z are decremented or incremented The 32 general purpose working registers 64 I O Registers and the 64 bytes of internal data SRAM in the ATtiny13 are all accessible through all these addressing modes The Register File is described in General Purpose Register File on page 8 Figure 9 Data Memory Map Data Memory 0x0000 0x001F 64 I O Registers 0x0020 0x005F 0x0060 Internal SRAM 64 x 8 Ox009F This section describes the general access timing concepts for in
54. 106 the pin mapping for SPI programming is listed Not all parts use the SPI pins dedicated for the internal SPI interface Figure 54 Serial Programming and Verify 1 8 5 5V OQ RESET SCK MISO MOSI Notes 1 If the device is clocked by the internal Oscillator it is no need to connect a clock source to the CLKI pin Table 48 Pin Mapping Serial Programming Symbol Pins yo Description MOSI PBO l Serial Data in MISO PB1 O Serial Data out SCK PB2 Serial Clock When programming the EEPROM an auto erase cycle is built into the self timed pro gramming operation in the Serial mode ONLY and there is no need to first execute the Chip Erase instruction The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into OxFF Depending on CKSEL Fuses a valid clock must be present The minimum low and high periods for the serial clock SCK input are defined as follows Low gt 2 CPU clock cycles for fx lt 12 MHz 3 CPU clock cycles for fy gt 12 MHz High gt 2 CPU clock cycles for fy lt 12 MHz 3 CPU clock cycles for fy gt 12 MHz o6 ATtinyl3 mem 2535E AVR 10 04 Serial Programming When writing serial data to the ATtiny13 data is clocked on the rising edge of SCK Algorimm When reading data from the ATtiny13 data is clocked on the falling edge of SCK See Figure 55 and Figure 56 for timing details To program and verify
55. 5 ZPCMSB ZPAGEMSB 10 Z REGISTER PAGEMSB PROGRAM COUNTER PCPAGE PCWORD PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD PAGEMSB 0 PAGE INSTRUCTION WORD 00 01 02 PAGEEND Note 1 The different variables used in Figure 53 are listed in Table 46 on page 105 2535E AVR 10 04 Store Program Memory The Store Program Memory Control and Status Register contains the control bits Control and Status Register needed to control the Program memory operations SPMCSR Bit 7 6 5 4 3 2 1 0 I LLL de sus PGWA PGERS SELFPAGEN sewcsn Read Write R R R R W R W RW R W R W Initial Value 0 0 0 0 0 0 0 0 e Bits 7 5 Res Reserved Bits These bits are reserved bits in the ATtiny13 and always read as zero Bit4 CTPB Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer the temporary page buffer will be cleared and the data will be lost Bit 3 RFLB Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the SPMCSR Register will read either the Lock bits or the Fuse bits depending on ZO in the Z pointer into the destination register See EEPROM Write Prevents Writing to SPMCSR on page 100 for details e Bit2 PGWRT Page Write If this bit is written to one at the same time as SELFPRGEN the next SPM instruction within four clock
56. 59 Biometrics Imaging Hi Rel MPU Switzerland Tel 41 26 426 5555 BP 70602 High Speed Converters RF Datacom Fax 41 26 426 5500 44306 Nantes Cedex 3 France Avenue de Rochepleine Tel 33 2 40 18 18 18 BP 123 Asia Fax 33 2 40 18 19 60 38521 Saint Egreve Cedex France Room 1219 Tel 33 4 76 58 30 00 Chinachem Golden Plaza ASICIASSP Smart Cards Fax 33 4 76 58 34 80 77 Mody Road Tsimshatsui Zone Industrielle East Kowloon 13106 Rousset Cedex France Hong Kong Tel 33 4 42 53 60 00 Tel 852 2721 9778 Fax 33 4 42 53 60 01 Fax 852 2722 1369 1150 East Cheyenne Min Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 1759 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Scottish Enterprise Technology Park Tel 81 3 3523 3551 Maxwell Building Fax 81 3 3523 7581 East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 Literature Requests www atmel com literature Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUD
57. 5E AVR 10 04 8S2 Top View Gelz End View SYMBOL A COMMON DIMENSIONS Unit of Measure mm MIN 1 70 NOM MAX 2 16 A1 0 05 0 25 b 0 35 0 48 0 15 0 35 5 13 5 35 D Side View 1 27 BSC This drawing is for general information only refer to EIAJ Drawing EDR 7320 for additional information Mismatch of the upper and lower dies and resin burrs are not included Itis recommended that upper and lower cavities be equal If they are different the larger dimension shall be regarded Determines the true geometric position Values b and C apply to pb Sn solder plated terminal The standard thickness of the solder layer shall be 0 010 0 010 0 005 mm 10 7 03 TITLE 2325 Orchard Parkway 8S2 8 lead 0 209 Body Plastic Small 5 San Jose CA 95131 Outline Package EIAJ AMEL 2535E AVR 10 04 DRAWING NO REV 852 163 AMEL S8S1 O HH Top View COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX D E 5 79 6 20 3 81 3 99 Side View 1 35 1 75 0 1 0 25 4 80 4 98 0 17 0 25 0 31 0 4 End
58. C2D ADC3D ADC1D AIN1D AINOD page 78 page 93 0x13 Reserved 0x12 Reserved 0x11 Reserved 0x10 Reserved OxOF Reserved Ox0E Reserved 0x0D Reserved 0x0C Reserved 0x0B Reserved Ox0A Reserved 0x09 Reserved 0x08 ACSR ACD ACBG ACO ACI ACIE ACIS1 ACISO page 76 0x07 ADMUX REFSO ADLAR MUX1 MUXO page 90 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPSO page 91 0x05 ADCH ADC Data Register High Byte page 92 0x04 ADCL ADC Data Register Low Byte page 92 0x03 ADCSRB ACME ADTS2 ADTS1 ADTSO page 93 0x02 Reserved 0x01 Reserved 0x00 Reserved AIMEL 187 2535E AVR 10 04 T AMEL Note 1 For compatibility with future devices reserved bits should be written to zero if accessed Reserved I O memory addresses should never be written 2 I O Registers within the address range 0x00 Ox1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions 3 Some of the Status Flags are cleared by writing a logical one to them Note that unlike most other AVRs the CBI and SBI instructions will only operation the specified bit and can therefore be used on registers containing such Status Flags The CBI and SBI instructions work with registers 0x00 to Ox1F only ss ATtinyl3 me 2535E AVR 10 04 Instruction Set Summary
59. CNTO by 1 direction Select between increment and decrement clear Clear TCNTO set all bits to zero clk Timer Counter clock referred to as dk in the following top Signalize that TCNTO has reached maximum value bottom Signalize that TCNTO has reached minimum value zero 2535E AVR 10 04 Output Compare Unit 2535E AVR 10 04 Depending of the mode of operation used the counter is cleared incremented or dec remented at each timer clock clk79 clkz can be generated from an external or internal clock source selected by the Clock Select bits CS02 0 When no clock source is selected CS02 0 0 the timer is stopped However the TCNTO value can be accessed by the CPU regardless of whether cik is present or not A CPU write overrides has priority over all counter clear or count operations The counting sequence is determined by the setting of the WGMO1 and WGMOO bits located in the Timer Counter Control Register TCCROA and the WGMO 2 bit located in the Timer Counter Control Register B TCCROB There are close connections between how the counter behaves counts and how waveforms are generated on the Output Compare output OCOA For more details about advanced counting sequences and waveform generation see Modes of Operation on page 62 The Timer Counter Overflow Flag TOVO is set according to the mode of operation selected by the WGM01 0 bits TOVO can be used for generating a CPU interrupt The 8 bit comparat
60. Current vs Output Voltage Vec 1 8V lo mA 0 4 0 2 RESET PIN AS I O SINK CURRENT vs OUTPUT VOLTAGE Vec 1 8V 40 C 25 C 85 C 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 8 2 Var V Figure 100 1 0 Pin Input Threshold Voltage vs Vcc VIH I O Pin Read as 1 Threshold V 2 5 0 5 I O PIN INPUT THRESHOLD VOLTAGE vs Voc VIH IO PIN READ AS 1 85 C 25 C 40 C AMEL 4 5 5 5 141 AMEL Figure 101 I O Pin Input Threshold Voltage vs Voc VIL I O Pin Read as 0 I O PIN INPUT THRESHOLD VOLTAGE vs Vec VIL IO PIN READ AS 0 85 C 25 25 C 40 C 2 ke 215 E E LT 1 0 5 0 T T T T T T 15 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 102 UO Pin Input Hysteresis vs Voc I O PIN INPUT HYSTERESIS vs Voc 0 45 0 4 40 C 0 35 S 03 25 C 9 0 25 9 2 0 2 85 C amp 0 15 0 1 0 05 0 1 5 2 2 5 3 3 5 4 45 5 5 5 Voc V 142 ATtiny1 3 KSS 2535E AVR 10 04 Figure 103 Reset Pin as I O Input Threshold Voltage vs Voc VIH Reset Pin Read as 1 RESET PIN AS I O THRESHOLD VOLTAGE vs Veg VIH IO PIN READ AS 1 2 5 ke 40 C 215 25 C P k 1 85 C 0 5 0 ig T T T T i 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Figure 104 Reset Pin as I O Input Thres
61. DC Control and Status Register A ADCSRA 2535E AVR 10 04 This bit selects the voltage reference for the ADC as shown in Table 37 If this bit is changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSRA is set Table 37 Voltage Reference Selections for ADC REFSO Voltage Reference Selection 0 Vcc used as analog reference 1 Internal Voltage Reference e Bit5 ADLAR ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register Write one to ADLAR to left adjust the result Otherwise the result is right adjusted Changing the ADLAR bit will affect the ADC Data Register immediately regardless of any ongoing conversions For a complete description of this bit see The ADC Data Register ADCL and ADCH on page 92 Bits 4 2 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bits 1 0 MUX1 0 Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC See Table 38 for details If these bits are changed during a conversion the change will not go in effect until this conversion is complete ADIF in ADCSRA is set Table 38 Input Channel Selections MUX1 0 Single Ended Input 00 ADCO PB5 01 ADC1 PB2 10 ADC2 PB4 11 ADC3 PB3 Bit 7 6 5 4 3 2 1 0 ZADEN
62. DOExn Pxn DATA DIRECTION OVERRIDE ENABLE RDx READ DDRx DDOVxn Pxn DATA DIRECTION OVERRIDE VALUE RRx READ PORTx REGISTER PVOExn Pxn PORT VALUE OVERRIDE ENABLE WRx WRITE PORTx PVOVxn Pxn PORT VALUE OVERRIDE VALUE RPx READ PORTx PIN DIEOExn Pxn DIGITAL INPUT ENABLE OVERRIDE ENABLE WPx WRITE PINx DIEOVxn Pxn DIGITAL INPUT ENABLE OVERRIDE VALUE Clk o VO CLOCK SLEEP SLEEP CONTROL Dixn DIGITAL INPUT PIN n ON PORTx PTOExn Pxn PORT TOGGLE OVERRIDE ENABLE AlOxn ANALOG INPUT OUTPUT PIN n ON PORTx Note 1 WRx WPx WDx RRx RPx and RDx are common to all pins within the same port Che SLEEP and PUD are common to all ports All other signals are unique for each pin Table 20 summarizes the function of the overriding signals The pin and port indexes from Figure 24 are not shown in the succeeding tables The overriding signals are gen erated internally in the modules having the alternate function Table 20 Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull up Override If this signal is set the pull up enable is controlled by the Enable PUOV signal If this signal is cleared the pull up is enabled when DDxn PORTxn PUD 0b010 PUOV Pull up Override If PUOE is set the pull up is enabled disabled when Value PUOV is set cleared regardless of the setting of the DDxn PORTxn and PUD Register bits DDOE Data Direction If this signal i
63. Data Registers and ADIF is set In Single Conversion mode ADSC is cleared simultaneously The software may then set ADSC again and a new conversion will be initiated on the first rising ADC clock edge When Auto Triggering is used the prescaler is reset when the trigger event occurs This assures a fixed delay from the trigger event to the start of conversion In this mode the sample and hold takes place two ADC clock cycles after the rising edge on the trigger source signal Three additional CPU clock cycles are used for synchronization logic In Free Running mode a new conversion will be started immediately after the conver sion completes while ADSC remains high For a summary of conversion times see Table 36 2535E AVR 10 04 Figure 43 ADC Timing Diagram First Conversion Single Conversion Mode Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Next First Conversion Conversion 1 2 12 13 ka 15 16 17 18 19 20 21 22 23 24 25 1 2 3 d t d l av 4 Gi TUL A A4 A4 A A A A TX Sign and MSB of Result ZUM Dt EE SE um MUX and REFS Update CH Sample amp Hold Conversion we DS MUX and REFS Complete Update Figure 44 ADC Timing Diagram Single Conversion One Conversion Next Conversion 4
64. E AVR 10 04 AMEL Figure 121 128 kHz Watchdog Oscillator Frequency vs Vec 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs Vcc 120 40 C 115 25 C 110 Frc kHz 105 Voc V Figure 122 128 kHz Watchdog Oscillator Frequency vs Temperature 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs TEMPERATURE 118 116 114 112 N 110 E 1 8V amp 108 H 2 7V 106 4 0V 55V 104 102 100 60 40 20 0 20 40 60 80 100 Temperature C 152 ATtinyl3 me 2535E AVR 10 04 Current Consumption of Peripheral Units 2535E AVR 10 04 Figure 123 Brownout Detector Current vs Voc Icc UA Icc uA 35 30 350 BROWNOUT DETECTOR CURRENT vs Voc 1 5 2 2 5 3 3 5 4 4 5 5 5 Voc V Figure 124 ADC Current vs Vcc ADC CURRENT vs Voc 15 2 25 3 3 5 4 4 5 5 5 Voc V AMEL 5 C 40 C 25 C 85 C 153 AMEL Figure 125 Analog Comparator Current vs Voc ANALOG COMPARATOR CURRENT vs Vcc 140 40 C 120 25 C 100 85 C Icc UA Voc V Figure 126 Programming Current vs Voc PROGRAMMING CURRENT vs Vcc 14 ATtinyl3 m 2535E AVR 10 04 Current Consumption in Reset and Reset Pulse width 2535E AVR 10 04 Figu
65. Features High Performance Low Power AVR 8 Bit Microcontroller Advanced RISC Architecture 120 Powerful Instructions Most Single Clock Cycle Execution 82 x 8 General Purpose Working Registers Fully Static Operation Up to 20 MIPS Througput at 20 MHz Non volatile Program and Data Memories 1K Byte of In System Programmable Program Memory Flash Endurance 10 000 Write Erase Cycles 64 Bytes In System Programmable EEPROM Endurance 100 000 Write Erase Cycles 64 Bytes Internal SRAM Programming Lock for Self Programming Flash Program and EEPROM Data Security Peripheral Features One 8 bit Timer Counter with Prescaler and Two PWM Channels 4 channel 10 bit ADC with Internal Voltage Reference Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog Comparator Special Microcontroller Features debugWIRE On chip Debug System In System Programmable via SPI Port External and Internal Interrupt Sources Low Power Idle ADC Noise Reduction and Power down Modes Enhanced Power on Reset Circuit Programmable Brown out Detection Circuit Internal Calibrated Oscillator HO and Packages 8 pin PDIP SOIC Six Programmable I O Lines 20 pad MLF Six Programmable I O Lines Operating Voltage 1 8 5 5V for ATtiny13V 2 7 5 5V for ATtiny13 Speed Grade ATtiny13V 0 4 MHz 1 8 5 5V 0 10 MHz 2 7 5 5V ATtiny13 0
66. GIFR INTFO PCIF page 55 0x39 TIMSKO OCIEOB OCIEOA TOIEO page 72 0x38 TIFRO OCFOB OCFOA TOVO page 73 0x37 SPMCSR CTPB RFLB PGWRT PGERS SELFPRGEN page 99 0x36 OCROA Timer Counter Output Compare Register A page 72 0x35 MCUCR PUD SE SM1 SMO ISCO1 ISCO0 page 50 0x34 MCUSR WDRF BORF EXTRF PORF page 34 0x33 TCCROB FOCOA FOCOB WGM02 CS02 CS01 CS00 page 68 0x32 TCNTO Timer Counter 8 bit page 72 0x31 OSCCAL Oscillator Calibration Register page 23 0x30 Reserved Ox2F TCCROA COMOA1 COMOAO COMOB1 COMOBO WGMO1 WGM00 page 71 Ox2E DWDR DWDR 7 0 page 96 Ox2D Reserved Ox2C Reserved 0x2B Reserved Ox2A Reserved 0x29 OCROB Timer Counter Output Compare Register B page 72 0x28 GTCCR TSM PSR10 page 75 0x27 Reserved 0x26 CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPSO page 25 0x25 Reserved 0x24 Reserved 0x23 Reserved 0x22 Reserved 0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDPO page 39 0x20 Reserved Ox1F Reserved Ox1E EEARL EEPROM Address Register page 15 0x1D EEDR EEPROM Data Register page 15 Ox1C EECR EEPM1 EEPMO EERIE EEMPE EEPE EERE page 16 Ox1B Reserved Ox1A Reserved 0x19 Reserved 0x18 PORTB PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTBO page 52 0x17 DDRB DDB5 DDB4 DDB3 DDB2 DDB1 DDBO page 52 0x16 PINB PINB5 PINB4 PINB3 PINB2 PINB1 PINBO page 52 0x15 PCMSK PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINTO page 56 0x14 DIDRO ADCOD AD
67. Hz A MEL 125 2535E AVR 10 04 AMEL Figure 69 Active Supply Current vs Vcc 32 kHz External Clock ACTIVE SUPPLY CURRENT vs Vcc 32 kHz EXTERNAL CLOCK 0 04 25 C 0 035 85 C 0 03 0 025 ds E 0 02 us 0 015 0 01 0 005 0 1 5 2 2 5 3 3 5 4 4 5 5 5 5 Vcc V Idle Supply Current Figure 70 Idle Supply Current vs Frequency 0 1 1 0 MHz IDLE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHz 0 9 25 55V 0 7 5 0 V 0 6 4 5V Z o5 4 0 V E 804 3 3 V m 27V 0 2 1 8V 0 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz 126 ATtinyl3 me 2535E AVR 10 04 ATtiny13 Figure 71 Idle Supply Current vs Frequency 1 20 MHz IDLE SUPPLY CURRENT vs FREQUENCY 1 20MHz 5 5V 5 0 V 45 V E MN MN E p lt lt lt LLLONLLL ANE Noj o E es NN Ew p E EE Frequency MHz Figure 72 Idle Supply Current vs Voc Internal RC Oscillator 9 6 MHz IDLE SUPPLY CURRENT vs Voc INTERNAL RC OSCILLATOR 9 6 MHZ 2 5 85 C 25 C 40 C 15 lt x E o 2 1 0 5 0 T 15 2 2 5 3 8 5 4 4 5 5 5 5 A MEL 127 2535E AVR 10 04 AMEL Figure 73 Idle Supply Current vs Voc Internal RC Oscillator 4 8 MHz IDLE SUPPLY CURRENT vs Voc INTERNAL RC OSCILLATOR 4 8 MHZ
68. II PB1 Valid to SCI PB3 High 50 ns Leurs SDI PBO SII PB1 Hold after SCI PB3 High 50 ns tsHov SCI PB3 High to SDO PB2 Valid 16 ns twiwH Pra Wait after Instr 3 for Write Fuse Bits 2 5 ms 118 ATti ny1 3 EES 2535E AVR 10 04 Electrical Characteristics Absolute Maximum Ratings Operating Temperature Storage Temperature Voltage on any Pin except RESET with respect to Ground Maximum Operating Voltage DC Current per I O Pin DC Current Vcc and GND Pins n 55 C to 125 C 65 C to 150 C ges 0 5V to Voc 0 5V Voltage on RESET with respect to Ground 0 5V to 13 0V DC Characteristics NOTICE Ta 40 C to 85 C Voc 1 8V to 5 5V unless otherwise noted Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2535E AVR 10 04 AMEL Symbol Parameter Condition Min Typ Max Units Vu Input Low Voltage 0 5 0 2Vec V
69. IMER CONTROL H i PROGRAM COUNTER END REGISTER PROGRAM FLASH TIMER COUNTERO INSTRUCTION REGISTER PURPOSE INTERRUPT REGISTERS PROGRAMMING INSTRUCTION Greg DECODER LINES Se CONTROL DATA EEPROM STATUS i REGISTER ADC DATA REGISTER DATA DIR ANALOG COMPARATOR PORT B REG PORT B PORT B DRIVERS e NAT PBO PB5 AMEL 3 2535E AVR 10 04 Pin Descriptions VCC GND Port B PB5 PB0 About Code Examples AMEL The AVR core combines a rich instruction set with 32 general purpose working registers All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instruction executed in one clock cycle The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers The ATtiny13 provides the following features 1K byte of In System Programmable Flash 64 bytes EEPROM 64 bytes SRAM 6 general purpose I O lines 32 general pur pose working registers one 8 bit Timer Counter with compare modes Internal and External Interrupts a 4 channel 10 bit ADC a programmable Watchdog Timer with internal Oscillator and three software selectable power saving modes The Idle mode stops the CPU while allowing the SRAM Timer Counter ADC Analog Comparator and Interrupt system to continue functioning The Power down mode saves the reg
70. ING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life Atmel Corporation 2004 All rights reserved Atmel logo and combinations thereof AVR and AVR Studio are registered trademarks and Everywhere You Arel are the trademarks of Atmel Corporation or its subsidiaries Microsoft Windows Windows NT and Windows XP9 are the registered trademarks of Microsoft Corporation Other terms and product names may be trademarks of others Printed on recycled paper 2535E AVR 10 04
71. If PORTxn is written logic one when the pin is configured as an output pin the port pin is driven high one If PORTxn is written logic zero when the pin is configured as an out put pin the port pin is driven low zero AMEL s Toggling the Pin Switching Between Input and Output Reading the Pin Value AMEL Writing a logic one to PINxn toggles the value of PORTxn independent on the value of DDRxn Note that the SBI instruction can be used to toggle one single bit in a port When switching between tri state DDxn PORTxn 0b00 and output high DDxn PORTxn 0b11 an intermediate state with either pull up enabled DDxn PORTxn 0b01 or output low DDxn PORTxn 0610 must occur Normally the pull up enabled state is fully acceptable as a high impedant environment will not notice the dif ference between a strong high driver and a pull up If this is not the case the PUD bit in the MCUCR Register can be set to disable all pull ups in all ports Switching between input with pull up and output low generates the same problem The user must use either the tri state DDxn PORTxn 0b00 or the output high state DDxn PORTxn 0b10 as an intermediate step Table 19 summarizes the control signals for the pin value Table 19 Port Pin Configurations DDxn PORTxn in MCUCH y o Pull up Comment 0 0 X Input No Tri state Hi Z Pxn will source current if ext pulled 0 1 0 Input Yes low 0 1 1 Inpu
72. Input Channels 2535E AVR 10 04 The MUXn and REFS1 0 bits in the ADMUX Register are single buffered through a tem porary register to which the CPU has random access This ensures that the channels and reference selection only takes place at a safe point during the conversion The channel and reference selection is continuously updated until a conversion is started Once the conversion starts the channel and reference selection is locked to ensure a sufficient sampling time for the ADC Continuous updating resumes in the last ADC clock cycle before the conversion completes ADIF in ADCSRA is set Note that the conversion starts on the following rising ADC clock edge after ADSC is written The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written If Auto Triggering is used the exact time of the triggering event can be indeterministic Special care must be taken when updating the ADMUX Register in order to control which conversion will be affected by the new settings If both ADATE and ADEN is written to one an interrupt event can occur at any time If the ADMUX Register is changed in this period the user cannot tell if the next conversion is based on the old or the new settings ADMUX can be safely updated in the following ways 1 When ADATE or ADEN is cleared 2 During conversion minimum one ADC clock cycle after the trigger event 3 After a conversion
73. MEL ATtiny13 has an Enhanced Watchdog Timer WDT The main features are Clocked from separate On chip Oscillator 3 Operating modes Interrupt System Reset Interrupt and System Reset Selectable Time out period from 16ms to 8s Possible Hardware fuse Watchdog always on WDTON for fail safe mode Figure 19 Watchdog Timer WATCHDOG p PRESCALER 128kHz OSCILLATOR OSC 4K OSC 8K OSC 16K OSC 32 OSC 64 050 128 OSC 256K OSC 512K OSC 1024K WDPO WDP1 WDP2 WDP3 WATCHDOG RESET E MCU RESET WDIF WDIE INTERRUPT The Watchdog Timer WDT is a timer counting cycles of a separate on chip 128 kHz oscillator The WDT gives an interrupt or a system reset when the counter reaches a given time out value In normal operation mode it is required that the system uses the WDR Watchdog Timer Reset instruction to restart the counter before the time out value is reached If the system doesn t restart the counter an interrupt or system reset will be issued In Interrupt mode the WDT gives an interrupt when the timer expires This interrupt can be used to wake the device from sleep modes and also as a general system timer One example is to limit the maximum time allowed for certain operations giving an interrupt when the operation has run longer than expected In System Reset mode the WDT gives a reset when the timer expires This is typically used to prevent system hang up in case of runaw
74. MEL s Modes of Operation Normal Mode Clear Timer on Compare Match CTC Mode e ATtiny13 AMEL The mode of operation i e the behavior of the Timer Counter and the Output Compare pins is defined by the combination of the Waveform Generation mode WGMO2 0 and Compare Output mode COMOx1 0 bits The Compare Output mode bits do not affect the counting sequence while the Waveform Generation mode bits do The COMOx1 0 bits control whether the PWM output generated should be inverted or not inverted or non inverted PWM For non PWM modes the COMOx1 0 bits control whether the out put should be set cleared or toggled at a Compare Match See Compare Match Output Unit on page 61 For detailed timing information refer to Figure 33 Figure 34 Figure 35 and Figure 36 in Timer Counter Timing Diagrams on page 66 The simplest mode of operation is the Normal mode WGM02 0 0 In this mode the counting direction is always up incrementing and no counter clear is performed The counter simply overruns when it passes its maximum 8 bit value TOP OxFF and then restarts from the bottom 0x00 In normal operation the Timer Counter Overflow Flag TOVO will be set in the same timer clock cycle as the TCNTO becomes zero The TOVO Flag in this case behaves like a ninth bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOVO Flag the timer resolution can be i
75. MPE bit determines whether writing EEPE to one will have effect or not When EEMPE is set setting EEPE within four clock cycles will program the EEPROM at the selected address If EEMPE is zero setting EEPE will have no effect When EEMPE has been written to one by software hardware clears the bit to zero after four clock cycles Bit 1 EEPE EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM When EEPE is written the EEPROM will be programmed according to the EEPMn bits setting The EEMPE bit must be written to one before a logical one is writ ten to EEPE otherwise no EEPROM write takes place When the write access time has elapsed the EEPE bit is cleared by hardware When EEPE has been set the CPU is halted for two cycles before the next instruction is executed Bit 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM When the correct address is set up in the EEARL Register the EERE bit must be written to 2535E AVR 10 04 Atomic Byte Programming Split Byte Programming Erase Write 2535E AVR 10 04 one to trigger the EEPROM read The EEPROM read access takes one instruction and the requested data is available immediately When the EEPROM is read the CPU is halted for four cycles before the next instruction is executed The user should poll the EEPE bit before starting the read operation If a write opera
76. Trigger Source Selections ADTS2 ADTS1 ADTSO Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer Counter Compare Match A 1 0 0 Timer Counter Overflow 1 0 1 Timer Counter Compare Match B 1 1 0 Pin Change Interrupt Request Bit 7 6 5 4 3 2 1 0 ay ADCOD ADC2D ADCSD ADCID AINID AINOD DIDRO Read Write R R R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 5 2 ADC3D ADCOD ADC3 0 Digital Input Disable AMEL z AMEL When this bit is written logic one the digital input buffer on the corresponding ADC pin is disabled The corresponding PIN register bit will always read as zero when this bit is set When an analog signal is applied to the ADC3 0 pin and the digital input from this pin is not needed this bit should be written logic one to reduce power consumption in the dig ital input buffer 2535E AVR 10 04 debugWIRE On chip Debug System Features Complete Program Flow Control Emulates All On chip Functions Both Digital and Analog except RESET Pin Real time Operation Symbolic Debugging Support Both at C and Assembler Source Level or for Other HLLs Unlimited Number of Program Break Points Using Software Break Points Non intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High Speed Operation Programming of Non volatile Memories Over
77. View 1 27 BSC 0 Notes 1 This drawing is for general information only refer to JEDEC Drawing MS 012 for proper dimensions tolerances datums etc 7 28 03 TITLE DRAWING NO REV IMEL 2325 Orchard Parkway S8S1 8 lead 0 150 Wide Body Plastic Gull Wing Small AIMEL San Jose CA 95131 Outline JEDEC SOIC 14 ATtiny13 2535E AVR 10 04 20M1 P 5 Q Nous 11D TOP VIEW BOTTOM VIEW Note Reference JEDEC Standard MO 220 Fig 1 SAW Singulation WGGD 5 IMEL 2325 Orchard Parkway 20M1 20 pad 4 x 4 x 0 8 mm Body Lead Pitch 0 50 mm AIMEL 2 6 mm Exposed Pad Micro Lead Frame Package MLF San Jose CA 95131 2535E AVR 10 04 TITLE SIDE VIEW COMMON DIMENSIONS Unit of Measure mm NOM 0 75 MAX 0 80 ATtiny13 0 01 0 05 0 20 REF 0 23 0 30 4 00 BSC 2 60 2 75 4 00 BSC 2 60 2 75 0 50 BSC 0 40 AMEL 10 27 04 DRAWING NO REV 165 AMEL Errata The revision letter in this section refers to the revision of the ATtiny13 device ATtiny13 Rev D e 1 ATtiny13 Rev B EEPROM can not be written below 1 9 Volt EEPROM can not be written below 1 9 Volt Writing the EEPROM at Vec below 1 9 volts might fail Problem Fix Workaround Do not write the EEPROM when Vec is below 1
78. age must be stored for example in the temporary page buffer before the erase and then be re written When using alternative 1 the Boot Loader provides an effective Read Modify Write feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alternative 2 is used it is not possible to read the old data while loading since the page is already erased The temporary page buffer can be accessed in a random sequence It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page To execute Page Erase set up the address in the Z pointer write 00000011 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR The data in R1 and RO is ignored The page address must be written to PCPAGE in the Z register Other bits in the Z pointer will be ignored during this operation e The CPU is halted during the Page Erase operation To write an instruction word set up the address in the Z pointer and data in R1 RO write 00000001 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR The content of PCWORD in the Z register is used to address the data in the temporary buffer The temporary buffer will auto erase after a Page Write operation or by writing the CTPB bit in SPMCSR It is also erased after a system reset Note that it is not possible to write more than one time to each address witho
79. ain Error Vrer 4V Vec AV 2 5 LSB ADC clock 200 kHz Single Ended Conversion Offset Error Vrer 4V Voc AV 1 5 LSB ADC clock 200 kHz Conversion Time Free Running Conversion 13 260 US Clock Frequency 50 1000 kHz Vin Input Voltage GND VREF V Input Bandwidth 38 5 kHz Vint Internal Voltage Reference 1 0 1 1 1 2 V Rain Analog Input Resistance 100 MQ Notes 1 Values are preliminary 122 2535E AVR 10 04 ATtiny13 Typical Characteristics Active Supply Current 2535E AVR 10 04 The following charts show typical behavior These figures are not tested during manu facturing All current consumption measurements are performed with all I O pins configured as inputs and with internal pull ups enabled A sine wave generator with rail to rail output is used as clock source The power consumption in Power down mode is independent of clock selection The current consumption is a function of several factors such as operating voltage operating frequency loading of I O pins switching rate of I O pins code executed and ambient temperature The dominating factors are operating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as C Voc f where C load capacitance Ver operating voltage and f average switch ing frequency of I O pin The parts are characterized at frequencies higher than test limits Parts are not guaran teed to function properly at frequencies higher than t
80. al code width the interval between two adjacent transitions from the ideal code width 1 LSB Ideal value 0 LSB AMEL z 2535E AVR 10 04 ADC Conversion Result ADC Multiplexer Selection Register ADMUX AMEL Figure 51 Differential Non linearity DNL Output Code Ox3FF 0 Vor Input Voltage e Quantization Error Due to the quantization of the input voltage into a finite number of codes a range of input voltages 1 LSB wide will code to the same value Always 0 5 LSB e Absolute Accuracy The maximum deviation of an actual unadjusted transition compared to an ideal transition for any code This is the compound effect of offset gain error differential error non linearity and quantization error Ideal value 0 5 LSB After the conversion is complete ADIF is high the conversion result can be found in the ADC Result Registers ADCL ADCH For single ended conversion the result is where Vn is the voltage on the selected input pin and Voer the selected voltage refer ence see Table 37 on page 91 and Table 38 on page 91 0x000 represents analog ground and Ox3FF represents the selected reference voltage minus one LSB Bit 7 6 5 4 3 2 1 0 Less Jam I Moe weus Read Write R R W R W R R R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 Res Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero e Bit 6 REFSO Reference Selection Bit 2535E AVR 10 04 A
81. alibration Byte Poll RDY BSY 1111 0000 0000 0000 XXXX XXXX XXXX XXXO lf o 1 a programming operation is still busy Wait until this bit returns to 0 before applying another command Note a address high bits b address low bits H 0 Low byte 1 High Byte o data out i data in x don t care A MEL 109 2535E AVR 10 04 AMEL Serial Programming Figure 56 Serial Programming Timing Characteristics MOSI p lovsH tsHox Lan SCK Lous MISO Jeun Table 51 Serial Programming Characteristics T 40 C to 85 C Voc 1 8 5 5V Unless Otherwise Noted Symbol Parameter Min Typ Max Units lteic Oscillator Frequency ATtiny13V 0 1 MHz oe Oscillator Period ATtiny13V 1 000 ns Oscillator Frequency ATtiny13L VCC 2 7 lcg 5 5V 0 9 6 MHz terer Oscillator Period ATtiny13L Voc 2 7 5 5V 104 ns Oscillator Frequency ATtiny13 Voc 4 5V lig 5 5V 0 16 MHz oe Oscillator Period ATtiny13 Voc 4 5V 5 5V 67 ns tsus_ SCK Pulse Width High 2 oe ns tas SCK Pulse Width Low 2 tore ns tovsu MOSI Setup to SCK High tote ns tsHox MOSI Hold after SCK High Zoe ns Leiw SCK Low to MISO Valid TBD TBD TBD ns Note 1 2 tere for fyr lt 12 MHz 3 toc for fy gt 12 MHz no ATtinyl3 me High voltage Serial This section describes how to program and verify F
82. ans the lowest value where the pin is guaranteed to be read as high Although each I O port can sink more than the test conditions 20 mA at Vec DN 10 mA at Vec 3V for PB5 PB1 0 10 mA at Voc 5V 5 mA at Vec 3V for PB4 2 under steady state conditions non transient the following must be observed 1 The sum of all IOL for all ports should not exceed 60 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test condition Although each I O port can source more than the test conditions 20 mA at Vcc DN 10 mA at Vec 3V for PB5 PB1 0 10 mA at Voc 5V 5 mA at Voc 3V for PB4 2 under steady state conditions non transient the following must be observed 1 The sum of all IOH for all ports should not exceed 60 mA If IOH exceeds the test condition VOH may exceed the related specification Pins are not guaranteed to source current greater than the listed test condition External Clock Drive Waveforms Figure 61 External Clock Drive Waveforms External Clock Drive Table 57 External Clock Drive Vec 1 8 5 5V Vec 2 2 7 5 5V Voc 2 4 5 5 5V Symbol Parameter Min Max Min Max Min Max Units T tete Clock Frequency 0 4 0 10 0 20 MHz Lac Clock Period 1000 104 62 5 ns tcucx High Time 400 50 25 ns teicx Low Time 400 50 25 ns tei cH Rise Time 2 0 1 6 0 5 us teucL Fall Time 2 0 1 6 0 5 us Atoici Change in
83. ast after the High voltage has been applied to ensure the Prog enable signature has been latched 5 Shortly after latching the Prog enable signature the device will actively output data on the Prog enable 2 SDO pin and the resulting drive contention may increase the power consumption To minimize this drive contention release the Prog enable 2 pin after t jnsz has elapsed 6 Wait at least 50 us before giving any serial instructions on SDI SII Note Ifthe RESET pin is disabled by programming the RSTDISBL Fuse it may not be possible to follow the proposed algorithm above The same may apply when External Crystal or External RC configuration is selected because it is not possible to apply qualified CLKI pulses In such cases the following algorithm should be followed 1 Set Prog enable pins listed in Table 53 to 000 2 Apply 4 5 5 5V between Vcc and GND simultanously as 11 5 12 5V is applied to RESET 3 Wait 100 ns 4 Re program the fuses to ensure that External Clock is selected as clock source CKSEL1 0 0b00 and RESET pin is activated RSTDISBL unprogrammed If Lock bits are programmed a Chip Erase command must be executed before changing the fuses 5 Exit Programming mode by power the device down or by bringing RESET pin to ObO 6 Enter Programming mode with the original algorithm as described above Table 54 High voltage Reset Characteristics Minimum High voltage Period Supply Voltage
84. ation Mode See the description in the Timer Counter Control Register A TCCROA on page 68 Bits 2 0 CS02 0 Clock Select The three Clock Select bits select the clock source to be used by the Timer Counter Table 33 Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source Timer Counter stopped 0 0 1 cIkyo No prescaling 0 1 0 clkyo 8 From prescaler 0 1 1 Clkyo 64 From prescaler 1 0 0 clk 9 256 From prescaler AMEL n Timer Counter Register TCNTO Output Compare Register A OCROA Output Compare Register B OCROB Timer Counter Interrupt Mask Register TIMSKO AMEL Table 33 Clock Select Bit Description Continued CS02 CS01 CSOO Description 1 0 1 CIk o 1024 From prescaler 1 1 0 External clock source on TO pin Clock on falling edge 1 1 1 External clock source on TO pin Clock on rising edge If external pin modes are used for the Timer CounterO transitions on the TO pin will clock the counter even if the pin is configured as an output This feature allows software control of the counting Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Timer Counter Register gives direct access both for read and write operations to the Timer Counter unit 8 bit counter Writing to the TCNTO Register blocks removes the Compare Match on the following timer clock Mod
85. ay code The third mode Interrupt and System Reset mode combines the other two modes by first giving an interrupt and then switch to System Reset mode This mode will for instance allow a safe shutdown by saving critical parameters before a sys tem reset The Watchdog always on WDTON fuse if programmed will force the Watchdog Timer to System Reset mode With the fuse programmed the System Reset mode bit WDE and Interrupt mode bit WDTIE are locked to 1 and 0 respectively To further ensure program security alterations to the Watchdog set up must follow timed sequences The sequence for clearing WDE and changing time out configuration is as follows 1 In the same operation write a logic one to the Watchdog change enable bit WDCE and WDE A logic one must be written to WDE regardless of the previ ous value of the WDE bit 2 Within the next four clock cycles write the WDE and Watchdog prescaler bits WDP as desired but with the WDCE bit cleared This must be done in one operation 2535E AVR 10 04 The following code example shows one assembly and one C function for turning off the Watchdog Timer The example assumes that interrupts are controlled e g by disabling interrupts globally so that no interrupts will occur during the execution of these functions Assembly Code Example WDT off Turn off global interrupt cli Reset Watchdog Timer wdr Clear WDRF in MCUSR in rl16 MCUSR andi r16 Oxff amp 0 lt
86. bits which can be left unprogrammed 1 or can be Memory Lock Bits programmed 0 to obtain the additional security listed in Table 43 The Lock bits can 102 only be erased to 1 with the Chip Erase command Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed even if the Lock Bits are set Thus when Lock Bit security is required should always debugWIRE be disabled by clearing the DWEN fuse Table 42 Lock Bit Byte Lock Bit Byte Bit No Description Default Value 1 unprogrammed 2 1 unprogrammed 1 unprogrammed 1 unprogrammed NIIA AJOIN 1 unprogrammed LB2 1 Lock bit 1 unprogrammed 1 unprogrammed LB1 0 Lock bit 1 unprogrammed Note 1 1 means unprogrammed 0 means programmed Table 43 Lock Bit Protection Modes Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled Further programming of the Flash and EEPROM is disabled in High voltage and Serial Programming mode The Fuse bits are locked in both Serial and High voltage Programming mode debugWire is disabled Further programming and verification of the Flash and EEPROM is disabled in High voltage and Serial 3 0 0 Programming mode The Fuse bits are locked in both Serial and High voltage Programming mode debugWire is disabled No
87. c change If some pins are unused it is recommended to ensure that these pins have a defined level Even though most of the digital inputs are disabled in the deep sleep modes as described above floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled Reset Active mode and Idle mode The simplest method to ensure a defined level of an unused pin is to enable the internal pull up In this case the pull up will be disabled during reset If low power consumption during reset is important it is recommended to use an external pull up or pull down Connecting unused pins directly to Voc or GND is not recommended since this may cause excessive currents if the pin is accidentally configured as an output Most port pins have alternate functions in addition to being general digital l Os Figure 24 shows how the port pin control signals from the simplified Figure 21 can be overrid den by alternate functions The overriding signals may not be present in all port pins but the figure serves as a generic description applicable to all port pins in the AVR micro controller family ATMEL a AIMEL T Figure 24 Alternate Port Functions PUOExn PUOVxn ba ECH PUD DDOExn DDOVxn PVOExn PVOVxn DIEOExn DATA BUS DIEOVxn P Dixn AlOxn PUOExn Pxn PULL UP OVERRIDE ENABLE PUD PULLUP DISABLE PUOVxn Pxn PULL UP OVERRIDE VALUE WDx WRITE DDRx D
88. ch pins contribute to the pin change interrupts Pin change interrupts on PCINT5 0 are detected asynchronously This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode The INTO interrupts can be triggered by a falling or rising edge or a low level This is set up as indicated in the specification for the MCU Control Register MCUCR When the INTO interrupt is enabled and is configured as level triggered the interrupt will trigger as long as the pin is held low Note that recognition of falling or rising edge interrupts on INTO requires the presence of an I O clock described in Clock Systems and their Distri bution on page 21 Low level interrupt on INTO is detected asynchronously This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode The I O clock is halted in all sleep modes except Idle mode Note that if a level triggered interrupt is used for wake up from Power down the required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt If the level disappears before the end of the Start up Time the MCU will still wake up but no interrupt will be generated The start up time is defined by the SUT and CKSEL Fuses as described in System Clock and Clock Options on page 21 An example of timing of a pin change interrupt is shown in Figure 25 Figure 25 Timing of pin change interrupts
89. ck Bits SII 0 0100 1100 00 0 0010 1100 00 0 0110 0100 00 0 0110 1100 OO high Write 2 1 0 to program SDO x xx XXXX xx X XXXX XXXX XX X_XXXX_XXXX_XX X XXXX xxxx xx _ the Lock Bit Read F L SDI 0 0000 0100 00 0 0000 0000 00 0 0000 0000 00 Reading A 3 0 h ead ruse LOW ou 00100 1100 00 0 0110 1000 00 0 0110 1100 00 See er de Bits Fuse bit is programmed SDO X XXXX XXXX XX X XXXX XXXX XX A 9876 543x xx Read F Te SDI 0 0000 0100 00 0 0000 0000 00 0 0000 0000 00 Bega He 4 h ead Fuse U ou 00100 1100 00 0 0111 1010 O0 0 0111 1110 00 RENE BE meansthe Bits Fuse bit is programmed SDO X XXXX XXXX XX X_XXXX_XXXX_XX x_xxFE_DCBx_xx SDI 0_0000_0100_00 0 0000 0000 00 0 0000 0000 00 Reading 2 1 o Read Lock Bits SII 0 0100 1100 00 0 0111 1000 00 00111 1100 00 E e 1 meansitne Ene bit is programmed SDO X_XXXX_XXXX_XX X_XXXX_XXXX_XX X XXXX X21X XX Read Si SDI 0 0000 1000 00 0 0000 OObb 00 0 0000 0000 00 0 0000 0000 00 R i add h ead Signature ci 00100 1100 00 0 0000 1100 00 0 0110 1000 00 0 0110 1100 oo Repeats Instr 2 4 for eac Bytes signature byte address SDO x XXXX XXXX xx X XXXX XXXX XX X XXXX XXXX XX q_qqqq_qqqx_xx Read SDI 0_0000_1000_00 0 0000 0000 00 0 0000 0000 00 0 0000 0000 00 s e SII 0 0100 1100 00 0 0000 1100 00 0 0111 1000 00 0 0111 1100 00 Calibration Byte SDO x XXXX XXXX xx X_XXXX_XXXX_XX X_XXXX_XXXX_XX P_pppp_pppx_xx Load No SDI 0 0000 0000 00 Operation SII 0 0100 1100
90. ck Diagram ACIE ANALOG COMPARATOR IRQ INTERRUPT SELECT ACIS1 ACISO ADC MULTIPLEXER ACO OUTPUT Notes 1 See Table 35 on page 78 2 Refer to Figure 1 on page 2 and Table 23 on page 51 for Analog Comparator pin placement Bit 7 6 5 4 3 2 1 0 ewe TT 52 Tats Abrsu ancsrs Read Write R R W R R R R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit6 ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off ADEN in ADCSRA is zero the ADC multiplexer selects the negative input to the Analog Comparator When this bit is written logic zero AIN1 is applied to the negative input of the Analog Compar ator For a detailed description of this bit see Analog Comparator Multiplexed Input on page 78 Bit 7 6 5 4 3 2 1 0 ACBG CEE Acsr Read Write R W R W R R W R W R R W R W Initial Value 0 0 N A 0 0 0 0 0 e Bit 7 ACD Analog Comparator Disable When this bit is written logic one the power to the Analog Comparator is switched off This bit can be set at any time to turn off the Analog Comparator This will reduce power consumption in Active and Idle mode When changing the ACD bit the Analog Compar ator Interrupt must be disabled by clearing the ACIE bit in ACSR Otherwise an interrupt can occur when the bit is changed Bit 6 ACBG Analog Comparator Bandgap Select 2535E AVR 10 04 2535E AVR 10 04 When this bit is set a fixed bandgap refere
91. completed Writing any other combination than 10001 01001 00101 00011 or 00001 in the lower five bits will have no effect AMEL s 2535E AVR 10 04 EEPROM Write Prevents Writing to SPMCSR Reading the Fuse and Lock Bits from Software AMEL Note that an EEPROM write operation will block all software programming to Flash Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation It is recommended that the user checks the status bit EEPE in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register It is possible to read both the Fuse and Lock bits from software To read the Lock bits load the Z pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR When an LPM instruction is executed within three CPU cycles after the RFLB and SELFPRGEN bits are set in SPMCSR the value of the Lock bits will be loaded in the destination register The RFLB and SELFPRGEN bits will auto clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles When RFLB and SELFPRGEN are cleared LPM will work as described in the Instruction set Manual Bit 7 6 5 4 3 2 1 0 Rd po qp KEKE The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits To read the Fuse Low byte load the Z point
92. consumption to the application s requirements To enter any of the three sleep modes the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed The SM1 0 bits in the MCUCR Regis ter select which sleep mode Idle ADC Noise Reduction or Power down will be activated by the SLEEP instruction See Table 10 for a summary If an enabled interrupt occurs while the MCU is in a sleep mode the MCU wakes up The MCU is then halted for four cycles in addition to the start up time executes the interrupt routine and resumes execution from the instruction following SLEEP The contents of the Register File and SRAM are unaltered when the device wakes up from sleep If a reset occurs during sleep mode the MCU wakes up and executes from the Reset Vector Figure 11 on page 21 presents the different clock systems in the ATtiny13 and their dis tribution The figure is helpful in selecting an appropriate sleep mode The MCU Control Register contains control bits for power management Bit 7 6 5 4 3 2 1 0 mb se sm Sw 150 150 weien Read Write R R W R W R W R W R R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 5 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed To avoid the MCU entering the sleep mode unless it is the programmer s purpose it is recommended to write the Sleep Enable SE bit to one just before the execution of t
93. contribute significantly to the total current consumption Refer to Interrupts on page 41 for details on how to con figure the Watchdog Timer When entering a sleep mode all port pins should be configured to use minimum power The most important thing is then to ensure that no pins drive resistive loads In sleep modes where both the I O clock clkyg and the ADC clock clkapc are stopped the input buffers of the device will be disabled This ensures that no power is consumed by the input logic when not needed In some cases the input logic is needed for detecting wake up conditions and it will then be enabled Refer to the section Digital Input Enable and Sleep Modes on page 46 for details on which pins are enabled If the input buffer is enabled and the input signal is left floating or has an analog signal level close to Vec 2 the input buffer will use excessive power For analog input pins the digital input buffer should be disabled at all times An analog signal level close to Vol on an input pin can cause significant current even in active mode Digital input buffers can be disabled by writing to the Digital Input Disable Regis ter DIDRO Refer to Digital Input Disable Register 0 DIDRO on page 78 for details ATMEL 2 System Control and Reset Resetting the AVR Reset Sources AMEL During reset all I O Registers are set to their initial values and the program starts exe cution from the Reset Vector The ins
94. cycles executes Page Write with the data stored in the temporary buffer The page address is taken from the high part of the Z pointer The data in R1 and RO are ignored The PGWRT bit will auto clear upon completion of a Page Write or if no SPM instruction is executed within four clock cycles The CPU is halted during the entire Page Write operation Bit 1 PGERS Page Erase If this bit is written to one at the same time as SELFPRGEN the next SPM instruction within four clock cycles executes Page Erase The page address is taken from the high part of the Z pointer The data in R1 and RO are ignored The PGERS bit will auto clear upon completion of a Page Erase or if no SPM instruction is executed within four clock cycles The CPU is halted during the entire Page Write operation e Bit0 SELFPRGEN Self Programming Enable This bit enables the SPM instruction for the next four clock cycles If written to one together with either CTPB RFLB PGWRT or PGERS the following SPM instruction will have a special meaning see description above If only SELFPRGEN is written the following SPM instruction will store the value in R1 RO in the temporary page buffer addressed by the Z pointer The LSB of the Z pointer is ignored The SELFPRGEN bit will auto clear upon completion of an SPM instruction or if no SPM instruction is exe cuted within four clock cycles During Page Erase and Page Write the SELFPRGEN bit remains high until the operation is
95. d instruction executions enabled by the Harvard architecture and the fast access Register File concept This is the basic pipelin ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost functions per clocks and functions per power unit Figure 6 The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 dko Wt VN CPU 7 i i i 1st Instruction Fetch y i 1st Instruction Execute i i Se 2nd Instruction Fetch i i 2nd Instruction Execute 1 1 1 3rd Instruction Fetch i l l l l 3rd Instruction Execute I I 1 4th Instruction Fetch i I 1 I EE I I l Figure 7 shows the internal timing concept for the Register File In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register Figure 7 Single Cycle ALU Operation T1 T2 T3 T4 GE x Xx o UKE Ge EE CPU i I D l Total Execution Time K bebe I D l L l L Register Operands Fetch I o L L ALU Operation Execute lt _ gt raaa I Result Write Back nC r I I I The AVR provides several different interrupt sources These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the inter
96. data register out EEDR r16 Write logical one to EEMPE sbi EECH EEMPE Start eeprom write by setting EEPE Sbi EECR EEPE C Code Example void EEPROM write unsigned char ucAddress unsigned char ucData Wait for completion of previous write while EECR amp 1 lt lt EEPE Set Programming mode EECH 0 lt lt EEPM1 0 gt gt EEPMO I Set up address and data registers EEARL ucAddress EEDR ucData Write logical one to EEMPE EECR 1 lt lt EEMPE Start eeprom write by setting EEPE EECR 1 lt lt EEPE j s ATtinyl3 me 2535E AVR 10 04 Preventing EEPROM Corruption 2535E AVR 10 04 The next code examples show assembly and C functions for reading the EEPROM The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions Assembly Code Example EEPROM read Wait for completion of previous write Sbic EECR EEPE rjmp EEPROM read Set up address r17 in address register out EEARL r17 Start eeprom read by writing EERE sbi EECR EERE Read data from data register in r16 EEDR ret C Code Example unsigned char EEPROM read unsigned char ucAddress Wait for completion of previous write wh
97. de reo e eie p Ed ui HO Pi EErN 105 cepe 105 Serial Downloading ertt ie rte tete sa dee Ee ER ERR RAE ERR crea 106 High voltage Serial Programminmg 111 High voltage Serial Programming Algorttbm 112 High voltage Serial Programming Characteristics eseeeeeeeeee eeen 118 Electrical Gharacteristiles E 119 Absolute Maximum Hatnge AAA 119 DC Characteristics enne nennen nennen 119 External Clock Drive WaveformS nennen 120 External Clock Drive nennen nennen nennen nnns 120 Maximum Speed vs Veg enne enne tenente enata trinitatis 121 ADC Characteristics Preliminary Data 122 ATtiny13 Typical Characteristics eee eeoooss 123 Active Supply Cumrent nnne nennen nnns nns 123 Idle Supply ET 126 Power Down Supply Current ssssssesssseeeeneeeene nennen 129 laute M 130 Pim Driver Strength ttr eerte tre aan asnasan iae De eu ges 132 Pin Thresholds and Hysteresis AAA 141 BOD Thresholds and Analog Comparator Offset 146 Internal Oscillator Speed urnnrnnrnnrnnnnnnrvnnnnrnnnnnvrnnnnrnnnnnnrnnenvnenenrrnnennnnssnnrnnsnnnne 149 Current Consumption of Peripheral Units 153 Current Consumption in Reset and Reset Pulse width 155 Register SUMMAarYy ee ADDIT Ere SRU is De esc E RE 157 Instruction Set SUMIMAL V su uunmeasde niesnnnn tene 159 Ordering Information E 161 Packaging Information eege
98. e Timer Counter TCNTO and Output Compare Registers OCROA and OCROB are 8 bit registers Interrupt request abbreviated to Int Req in the figure signals are all vis ible in the Timer Interrupt Flag Register TIFRO All interrupts are individually masked with the Timer Interrupt Mask Register TIMSKO TIFRO and TIMSKO are not shown in the figure The Timer Counter can be clocked internally via the prescaler or by an external clock source on the TO pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is selected The output from the Clock Select logic is referred to as the timer clock clkz The double buffered Output Compare Registers OCROA and OCROB is compared with the Timer Counter value at all times The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output AMEL s 2535E AVR 10 04 Definitions Timer Counter Clock Sources Counter Unit AMEL Compare pins OCOA and OCOB See Output Compare Unit on page 59 for details The Compare Match event will also set the Compare Flag OCFOA or OCFOB which can be used to generate an Output Compare interrupt request Many register and bit references in this section are written in general form A lower case n replaces the Timer Counter number in this case 0 A lower case x
99. e can be used to decrease power consumption when the require ment for processing power is low This can be used with all clock source options and it will affect the clock frequency of the CPU and all synchronous peripherals dk ClKape clkcpy and clkg asy are divided by a factor as shown in Table 9 Bit 7 6 5 4 3 2 1 0 exer T ees ees rees GLKPSO ous Read Write R W R R R R W R W R W R W Initial Value 0 0 0 0 See Bit Description Bit 7 CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written Rewriting the CLKPCE bit within this time out period does neither extend the time out period nor clear the CLKPCE bit e Bits 6 4 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero e Bits 3 0 CLKPS3 0 Clock Prescaler Select Bits 3 0 These bits define the division factor between the selected clock source and the internal system clock These bits can be written run time to vary the clock frequency to suit the application requirements As the divider divides the master clock input to the MCU the speed of all synchronous peripherals is reduced when a division factor is used The divi sion factors are given in Table 9 To avoid unintenti
100. er signal the ADC prescaler is reset and a conversion is started This provides a method of starting conversions at fixed intervals If the trigger signal still is set when the conversion completes a new conversion will not be started If another positive edge occurs on the trigger signal during conversion the edge will be ignored Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared A conversion can thus be triggered without causing an interrupt However the Interrupt Flag must be cleared in order to trig ger a new conversion at the next interrupt event Figure 41 ADC Auto Trigger Logic ADTS 2 0 B ADIF ADATE SOURCE 1 4 CONVERSION LOGIC EDGE SOURCE n DETECTOR ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished The ADC then operates in Free Run ning mode constantly sampling and updating the ADC Data Register The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag ADIF is cleared or not If Auto Triggering is enabled single conversions can be started by writing ADSC in ADCSRA to one ADSC can also be used to determine if a conversion is in progress The ADSC bit will be read as one during a conversion independent
101. er with 0x0000 and set the RFLB and SELFPRGEN bits in SPMCSR When an LPM instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR the value of the Fuse Low byte FLB will be loaded in the destination register as shown below Refer to Table 45 on page 103 for a detailed description and mapping of the Fuse Low byte Bit 6 5 4 3 2 1 0 7 Re Similarly when reading the Fuse High byte load 0x0003 in the Z pointer When an LPM instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR the value of the Fuse High byte FHB will be loaded in the destination register as shown below Refer to Table 44 on page 103 for detailed description and mapping of the Fuse High byte Bit T 6 5 4 3 2 1 0 Re Fuer Fase Hes Hei FASs Fue FBT FHEO Fuse and Lock bits that are programmed will be read as zero Fuse and Lock bits that are unprogrammed will be read as one 10 ATtinyl3 me 2535E AVR 10 04 Preventing Flash Corruption Programming Time for Flash when Using SPM 2535E AVR 10 04 During periods of low Voc the Flash program can be corrupted because the supply volt age is too low for the CPU and the Flash to operate properly These issues are the same as for board level systems using the Flash and the same design solutions should be applied A Flash program corruption can be caused by two situations when the voltage is too low First a re
102. eral form A lower case x represents the numbering letter for the port and a lower case n represents the bit number However when using the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Registers and bit locations are listed in Register Descrip tion for I O Ports on page 52 Three I O memory address locations are allocated for each port one each for the Data Register PORTx Data Direction Register DDRx and the Port Input Pins PINx The Port Input Pins I O location is read only while the Data Register and the Data Direction Register are read write However writing a logic one to a bit in the PINx Register will result in a toggle in the corresponding bit in the Data Register In addition the Pull up Disable PUD bit in MCUCR disables the pull up function for all pins in all ports when set Using the I O port as General Digital I O is described in Ports as General Digital I O on page 43 Most port pins are multiplexed with alternate functions for the peripheral fea tures on the device How each alternate function interferes with the port pin is described in Alternate Port Functions on page 47 Refer to the individual module sections for a full description of the alternate functions Ports as General Digital y o Configuring the Pin 2535E AVR 10 04 Note that enabling the alternate
103. et Mode 1 D X System Reset Mode Reset Bit4 WDCE Watchdog Change Enable This bit is used in timed sequences for changing WDE and prescaler bits To clear the WDE bit and or change the prescaler bits WDCE must be set Once written to one hardware will clear WDCE after four clock cycles Bit3 WDE Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR This means that WDE is always set when WDREF is set To clear WDE WDRF must be cleared first This feature ensures multiple resets during conditions causing failure and a safe start up after the failure Bit 5 2 0 WDP3 0 Watchdog Timer Prescaler 3 2 1 and 0 The WDP3 0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running The different prescaling values and their corresponding time out periods are shown in Table 17 on page 40 ATMEL s 2535E AVR 10 04 40 AMEL Table 17 Watchdog Timer Prescale Select Number of WDT Oscillator Typical Time out at WDP3 WDP2 WDP1 WDPO Cycles Vcc BON 0 0 0 0 2K 2048 cycles 16 ms 0 0 0 1 4K 4096 cycles 32 ms 0 0 1 0 8K 8192 cycles 64 ms 0 0 1 1 16K 16384 cycles 0 125s 0 1 0 0 32K 32768 cycles 0 25s 0 1 0 1 64K 65536 cycles 0 5s 0 1 1 0 128K 131072 cycles 1 0s 0 1 1 1 256K 262144 cycles 2 05 1 0 0 0 512K 524288 cycles 4 0s 1 0 0 1 1024K 1048576 cycles 8 0s 1 0 1 0 1 0 1
104. etails 2535E AVR 10 04 Table 28 shows the COMOA1 0 bit functionality when the WGM02 0 bits are set to phase correct PWM mode Table 28 Compare Output Mode Phase Correct PWM Mode COMOA1 0 COMOAO 0 Description Normal port operation OCOA disconnected 0 1 WGM02 0 Normal Port Operation OCOA Disconnected WGM02 1 Toggle OCOA on Compare Match Clear OCOA on Compare Match when up counting Set OCOA on Compare Match when down counting Set OCOA on Compare Match when up counting Clear OCOA on Compare Match when down counting Note 1 A special case occurs when OCROA equals TOP and COMOA1 is set In this case the Compare Match is ignored but the set or clear is done at TOP See Phase Cor rect PWM Mode on page 65 for more details Bits 5 4 COMOB1 0 Compare Match Output B Mode These bits control the Output Compare pin OCOB behavior If one or both of the COMOB 1 0 bits are set the OCOB output overrides the normal port functionality of the I O pin it is connected to However note that the Data Direction Register DDR bit cor responding to the OCOB pin must be set in order to enable the output driver When OCOB is connected to the pin the function of the COMOB1 0 bits depends on the WGM02 0 bit setting Table 26 shows the COMOA1 0 bit functionality when the WGM02 0 bits are set to a normal or CTC mode non PWM Table 29 Compare Output Mode non PWM Mode 2535E AVR 1
105. g BODLEVEL 1 0 Fuses Min Vgor Typ Vgor Max Vgor Units 11 BOD Disabled 10 1 8 01 2 7 V 00 4 3 Note 1 Vgor may be below nominal minimum operating voltage for some devices For devices where this is the case the device is tested down to Vcc Vgor during the production test This guarantees that a Brown out Reset will occur before Voc drops to a voltage where correct operation of the microcontroller is no longer guaranteed Table 14 Brown out Characteristics Symbol Parameter Min Typ Max Units Vuyst Brown out Detector Hysteresis 50 mV tBop Min Pulse Width on Brown out Reset 2 us When the BOD is enabled and Vcc decreases to a value below the trigger level Vgor in Figure 17 the Brown out Reset is immediately activated When Vec increases above the trigger level Vgor in Figure 17 the delay counter starts the MCU after the Time out period Lou has expired The BOD circuit will only detect a drop in Vec if the voltage stays below the trigger level for longer than tgop given in Table 14 AMEL 3 Watchdog Reset MCU Status Register MCUSR AMEL Figure 17 Brown out Reset During Operation RESET l l l I i I TIME OUT trout 7 l l l I I I INTERNAL RESET When the Watchdog times out it will generate a short reset pulse of one CK cycle dura tion On the falling edge of this pulse the delay timer starts counting the Time out period trout
106. g the correspond ing interrupt handling vector Alternatively WDTIF is cleared by writing a logic one to the flag When the I bit in SREG and WDTIE are set the Watchdog Time out Interrupt is executed Bit6 WDTIE Watchdog Timer Interrupt Enable When this bit is written to one and the I bit in the Status Register is set the Watchdog Interrupt is enabled If WDE is cleared in combination with this setting the Watchdog Timer is in Interrupt Mode and the corresponding interrupt is executed if time out in the Watchdog Timer occurs If WDE is set the Watchdog Timer is in Interrupt and System Reset Mode The first time out in the Watchdog Timer will set WDTIF Executing the corresponding interrupt vector will clear WDTIE and WDTIF automatically by hardware the Watchdog goes to System Reset Mode This is useful for keeping the Watchdog Timer security while using the interrupt To stay in Interrupt and System Reset Mode WDTIE must be set after each interrupt This should however not be done within the interrupt service routine itself as this might compromise the safety function of the Watchdog System Reset mode If the interrupt is not executed before the next time out a System Reset will be applied Table 16 Watchdog Timer Configuration WDTON WDE WDTIE Mode Action on Time out 0 0 0 Stopped None 0 0 1 Interrupt Mode Interrupt 0 1 0 System Reset Mode Reset 0 1 1 Interrupt and System Interrupt then go to Reset Mode System Res
107. gister Description rrrrnrnnnnnrvnnnnvrnnnnvrnnnnnrnnenvrnnnrnrnnrnnn 68 TimerCounter Prescalar iuieeieea orae nh sa aa aes p ae 4kRy yr ERE n ERE FR RR aM ER ER PARRA 74 Analog e 76 Analog Comparator Multiplexed Input 78 Analog to Digital Converter rrrrrrrrrrrrrnnnnnnnnnnnnnnnnnnnvennnnnnnnnnnnnnnnenenenen 79 Featules ae 79 euim E 80 Starting a Conversion ient ri ERR Ha EORR RU Ru ERE EIE ETE RR ORE caries 81 Prescaling and Conversion Timing 82 Changing Channel or Reference Selection sse 85 ADC Noise Canceler AAA 86 ADC Conversion ReSUlt acit roe top rn tere e sa trux ERA eR 90 debugWIRE On chip Debug System eese 95 SIT 95 eI Geen A ae eee 95 Physical Interface AAA 95 Software Break Points cn erm arre ee dE ie RR kids 96 Limitations of debug WIRE sunnere certet terea ene c een 96 debugWIRE Related Register in UO Memory arrrnnannvrnnnnvvnnnnrrnnnnvrnnrnnrnnnrnrnnennn 96 Self Programming the Flash ecce e eril elle e eene e nennen enun 97 Addressing the Flash During Self Programming rrrnrnnnnnrnnnnnvrnnnnnrnnennrnnrnnrnnenn 98 2535E AVR 10 04 2535E AVR 10 04 Memory PrOOGFaImiilig EEE 102 Program And Data Memory Lock Bits A 102 EE ia aiioa i E EENS VEEE AANEEN aas 103 Signature Bytes eene nnne ennt nnne nnns ennt 105 Calibration Byte ee e
108. gramming Instruction Set for ATtiny13 Continued Instruction Format Instruction Instr 1 5 Instr 2 6 Instr 3 Instr 4 Operation Remarks Load Read SDI 0_0000_0011_00 EEPROM SII 0 0100 1100 00 Enter EEPROM Read mode Command SDO X XXXX XXXX XX Read EEPROM SDI O bbbb bbbb 00 0 aaaa aaaa 00 0 0000 0000 00 0 0000 0000 00 Repeat Instr 1 3 4 for each new Eds SII 0 0000 1100 00 0 0001 1100 00 0 0110 1000 00 0 0110 1100 OO address Repeat Instr 2 for a new SDO x ox XXXX xx X XXXX XXXX XX X_XXXX_XXXX_XX q_qqqq_qqq0_00 256 byte page Write Fuse Low SP 0 0100 0000 00 0 A987 6543 O0 0 0000 0000 00 0 0000 000000 wait after Instr 4 until SDO goes Wee use LOW en 00100 1100 O0 0 0010 1100 00 0 0110 0100 00 0 0110 1100 OO high Write A 3 0 to program SDO X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX x xxxx xxxx XX the Fuse bit Write Fuse High SP 0 0100 0000 00 0 000F EDCB 00 0 0000 0000 00 0 0000 0000 00 wait after Instr 4 until SDO goes Bits 9 SII 0 0100 1100 00 0 0010 1100 00 0 0111 0100 00 0 0111 1100 OO high Write F B 0 to program SDO X_XXXX_XXXX_XX X_XXXX_XXXX_XX X_XXXX_XXXX_XX X XXXX XXXX XX the Fuse bit SDI 0 0010 0000 00 0 0000 0021 00 0_0000_0000_00 0_0000_0000_00 ait after Instr 4 until SDO goes Write Lo
109. gt b Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2 5 to 3 5 system clock cycles from an edge has been applied to the TO pin to the counter is updated Enabling and disabling of the clock input must be done when TO has been stable for at least one system clock cycle otherwise it is a risk that a false Timer Counter clock pulse is generated Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling The external clock must be guaranteed to have less than half the system clock frequency feci lt f 1 0 2 given a 50 50 duty cycle Since the edge detector uses sampling the maximum frequency of an external clock it can detect is half the sampling frequency Nyquist sampling theorem However due to vari ation of the system clock frequency and duty cycle caused by Oscillator source crystal resonator and capacitors tolerances it is recommended that maximum frequency of an external clock source is less than f 10 2 5 An external clock source can not be prescaled 2535E AVR 10 04 General Timer Counter Control Register GTCCR 2535E AVR 10 04 Figure 38 Prescaler for Timer CounterO gt 10 BIT T C PRESCALER Clear PSR10 TO TIMER COUNTERO CLOCK SOURCE elk Note 1 The synchronization logic on the input pins TO is sh
110. gular write sequence to the Flash requires a minimum voltage to operate cor rectly Secondly the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low Flash corruption can easily be avoided by following these design recommendations one is sufficient 1 Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD if the operating voltage matches the detection level If not an external low Voc reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient 2 Keep the AVR core in Power down sleep mode during periods of low Voc This will prevent the CPU from attempting to decode and execute instructions effec tively protecting the SPMCSR Register and thus the Flash from unintentional writes The calibrated RC Oscillator is used to time Flash accesses Table 41 shows the typical programming time for Flash accesses from the CPU Table 41 SPM Programming Time Symbol Min Programming Time Max Programming Time Flash write Page Erase Page Write and write Lock bits by SPM 3 7 ms 4 5 ms A MEL 101 AMEL Memory This section describes the different methods for Programming the ATtiny13 memories Programming Program And Data The ATtiny13 provides two Lock
111. hdog to continue operating if enabled This sleep mode halts cke clkcpy and Oko as while allowing the other clocks to run This improves the noise environment for the ADC enabling higher resolution measure ments If the ADC is enabled a conversion starts automatically when this mode is entered Apart form the ADC Conversion Complete interrupt only an External Reset a Watchdog Reset a Brown out Reset an SPM EEPROM ready interrupt an external level interrupt on INTO or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode When the SM1 0 bits are written to 10 the SLEEP instruction makes the MCU enter Power down mode In this mode the Oscillator is stopped while the external interrupts and the Watchdog continue operating if enabled Only an External Reset a Watchdog Reset a Brown out Reset an external level interrupt on INTO or a pin change interrupt can wake up the MCU This sleep mode halts all generated clocks allowing operation of asynchronous modules only Note that if a level triggered interrupt is used for wake up from Power down mode the changed level must be held for some time to wake up the MCU Refer to External Inter rupts on page 53 for details Table 11 Active Clock Domains and Wake up Sources in the Different Sleep Modes Active Clock Domains Oscillators Wake up Sources Do 2 3 x Oo S o o ow TE z Oo og 2 E o o 8 S E O 2 T S A
112. he SLEEP instruction and to clear it immediately after wak ing up Bits 4 3 SM1 0 Sleep Mode Select Bits 2 0 These bits select between the three available sleep modes as shown in Table 10 Table 10 Sleep Mode Select SM1 SMO Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power down 1 1 Reserved Bit 2 Res Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero AMEL 2 Idle Mode ADC Noise Reduction Mode Power down Mode AMEL When the SM1 0 bits are written to 00 the SLEEP instruction makes the MCU enter Idle mode stopping the CPU but allowing Analog Comparator ADC Timer Counter Watchdog and the interrupt system to continue operating This sleep mode basically halts clkce and ck Aen while allowing the other clocks to run Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow If wake up from the Analog Comparator interrupt is not required the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register ACSR This will reduce power consumption in Idle mode If the ADC is enabled a conversion starts automatically when this mode is entered When the SM1 0 bits are written to 01 the SLEEP instruction makes the MCU enter ADC Noise Reduction mode stopping the CPU but allowing the ADC the external inter rupts and the Watc
113. he ordering code indicates The difference between current consumption in Power down mode with Watchdog Timer enabled and Power down mode with Watchdog Timer disabled represents the dif ferential current drawn by the Watchdog Timer Figure 64 Active Supply Current vs Frequency 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs LOW FREQUENCY 0 1 1 0 MHZ 1 2 Tr Jd 55V 50V 0 8 45V T 4 0 V E o6 Oo 2 3 3V 0 4 27V 1 8V 0 2 0 bh emeng E e DE GE T T T 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz A MEL 123 AMEL Figure 65 Active Supply Current vs Frequency 1 20 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20MHZ 14 4 5 5V 12 5 0 V 10 45V T 8 E o 2 6 4 2 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz Figure 66 Active Supply Current vs Vcc Internal RC Oscillator 9 6 MHz ACTIVE SUPPLY CURRENT vs Voc INTERNAL RC OSCILLATOR 9 6 MHZ Icc mA R Vcc V 124 ATtinyl3 m 2535E AVR 10 04 Figure 67 Active Supply Current vs Vcc Internal RC Oscillator 4 8 MHz ACTIVE SUPPLY CURRENT vs Voc INTERNAL RC OSCILLATOR 4 8 MHZ 45 25 C 4 40 C 85 C 3 5 3 T 25 g 15 0 5 0 1 JJ 1 1 15 2 25 3 3 5 4 4 5 5 5 5 Voc V Figure 68 Active Supply Current vs Vcc Internal WDT Oscillator 128 kHz ACTIVE SUPPLY CURRENT vs Voc INTERNAL WD OSCILLATOR 128 K
114. hold Voltage vs Vcc VIL Reset Pin Read as 0 RESET PIN AS I O THRESHOLD VOLTAGE vs Veg VIL IO PIN READ AS 0 Threshold V A MEL 143 2535E AVR 10 04 AMEL Figure 105 Reset Pin as I O Pin Hysteresis vs Voc RESET PIN AS IO PIN HYSTERESIS vs Voc 0 7 40 C 25 C 85 C Input Hysteresis V Figure 106 Reset Input Threshold Voltage vs Voc VIH Reset Pin Read as 1 RESET INPUT THRESHOLD VOLTAGE vs Vcc VIH IO PIN READ AS 11 25 2 S 15 Lang 9 E 85 C 25 C 0 5 0 15 2 2 5 3 3 5 4 45 5 55 Voc V 144 ATti ny1 3 Ell 2535E AVR 10 04 Figure 107 Reset Input Threshold Voltage vs Voc VIL Reset Pin Read as 0 RESET INPUT THRESHOLD VOLTAGE vs Voc VIL IO PIN READ AS 0 Threshold V 4 5 5 5 5 Figure 108 Reset Input Pin Hysteresis vs Voc RESET INPUT THRESHOLD VOLTAGE vs Vcc VIL IO PIN READ AS 0 0 5 40 C 0 4 0 3 85 C Threshold V 0 2 25 C 0 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 AIMEL 145 2535E AVR 10 04 HE AMEL BOD Thresholds and Figure 109 BOD Thresholds vs Temperature BODLEVEL is 4 3V Analog Comparator Offset BOD THRESHOLDS vs TEMPERATURE BODLEVEL IS 4 3V 45 Rising Vcc 44 E Ke E S 43 Falling Vec 4 2 d f T i T 1
115. ifying the counter TCNTO while the counter is running introduces a risk of missing a Compare Match between TCNTO and the OCROx Registers Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8 bit value that is continuously compared with the counter value TCNTO A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OCOA pin Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8 bit value that is continuously compared with the counter value TCNTO A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OCOB pin Bit 7 6 5 4 3 2 1 0 On TIMSKo Read Write R R R R R W R W R W R Initial Value 0 0 0 0 0 0 0 0 Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bit 3 OCIEOB Timer Counter Output Compare Match B Interrupt Enable When the OCIEOB bit is written to one and the I bit in the Status Register is set the Timer Counter Compare Match B interrupt is enabled The corresponding interrupt is 2535E AVR 10 04 Timer Counter 0 Interrupt Flag Register TIFRO 2535E AVR 10 04 executed if a Compare Match in Timer Counter occurs i e when the OCFOB bit is set in the Timer Counter Interrupt Flag Registe
116. igital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS 2 0 8 BIT DATA BUS ADC MULTIPLEXER SELECT ADMUX ADC CTRL amp STATUS REGISTER ADCSRA REFS1 ADLAR TRIGGER SELECT MUX DECODER CHANNEL SELECTION INTERNAL 1 1V REFERENCE SAMPLE amp HOLD COMPARATOR 10 BIT DAC ADC3 ADC2 We ADC MULTIPLEXER OUTPUT ADC1 ADCO The ADC converts an analog input voltage to a 10 bit digital value through successive approximation The minimum value represents GND and the maximum value represents the voltage on Vec or an internal 1 1V reference voltage The analog input channel is selected by writing to the MUX bits in ADMUX Any of the ADC input pins can be selected as single ended inputs to the ADC The ADC is enabled by setting the ADC Enable bit ADEN in ADCSRA Voltage refer ence and input channel selections will not go into effect until ADEN is set The ADC does not consume power when ADEN is cleared so it is recommended to switch off the ADC before entering power saving sleep modes The ADC generates a 10 bit result which is presented in the ADC Data Registers ADCH and ADCL By default the result is presented right adjusted but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX If the result is left adjusted and no more than 8 bit precision is required
117. igned a Data memory address mapping them directly into the first 32 locations of the user Data Space Although not being phys ically implemented as SRAM locations this memory organization provides great flexibility in access of the registers as the X Y and Z pointer registers can be set to index any register in the file The X register Y register and The registers R26 R31 have some added functions to their general purpose usage Z register Stack Pointer 2535E AVR 10 04 These registers are 16 bit address pointers for indirect addressing of the data space The three indirect address registers X Y and Z are defined as described in Figure 5 Figure 5 The X Y and Z registers 15 XH XL 0 R27 0x1B R26 0x14 15 YH YL 0 R29 0x1D R28 0x1C 15 ZH ZL 0 R31 Ox1F R30 0x1E In the different addressing modes these address registers have functions as fixed dis placement automatic increment and automatic decrement see the instruction set reference for details The Stack is mainly used for storing temporary data for storing local variables and for storing return addresses after interrupts and subroutine calls The Stack Pointer Regis ter always points to the top of the Stack Note that the Stack is implemented as growing from higher memory locations to lower memory locations This implies that a Stack PUSH command decreases the Stack Pointer The Stack Pointer points to the data SRAM Stack area where the Subroutine
118. ile EECR amp 1 EEPE Set up address register EEARL ucAddress Start eeprom read by writing EERE EECR 1 EERE Return data from data register return EEDR During periods of low Vgc the EEPROM data can be corrupted because the supply volt age is too low for the CPU and the EEPROM to operate properly These issues are the same as for board level systems using EEPROM and the same design solutions should be applied An EEPROM data corruption can be caused by two situations when the voltage is too low First a regular write sequence to the EEPROM requires a minimum voltage to operate correctly Secondly the CPU itself can execute instructions incorrectly if the supply voltage is too low EEPROM data corruption can easily be avoided by following this design recommendation Keep the AVR RESET active low during periods of insufficient power supply voltage This can be done by enabling the internal Brown out Detector BOD If the detection level of the internal BOD does not match the needed detection level an external low Voc reset protection circuit can be used If a reset occurs while a write operation is in progress the write operation will be completed provided that the power supply voltage is sufficient AMEL e UO Memory AMEL The I O space definition of the ATtiny13 is shown in Register Summary on page 157 All ATtiny13 I Os
119. ility with future devices this bit must be set to zero when TCCROB is written when operating in PWM mode When writing a logical one to the FOCOA bit an immediate Compare Match is forced on the Waveform Generation unit The OCOA output is changed according to its COMOA1 0 bits setting Note that the FOCOA bit is implemented as a strobe Therefore it is the value present in the COMOA1 0 bits that determines the effect of the forced compare A FOCOA strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCROA as TOP The FOCOA bit is always read as zero e Bit 6 FOCOB Force Output Compare B The FOCOB bit is only active when the WGM bits specify a non PWM mode However for ensuring compatibility with future devices this bit must be set to zero when TCCROB is written when operating in PWM mode When writing a logical one to the FOCOB bit an immediate Compare Match is forced on the Waveform Generation unit The OCOB output is changed according to its COMOB1 0 bits setting Note that the FOCOB bit is implemented as a strobe Therefore it is the value present in the COMOB 1 0 bits that determines the effect of the forced compare A FOCOB strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCROB as TOP The FOCOB bit is always read as zero e Bits 5 4 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bit 3 WGM02 Waveform Gener
120. ions In order to prevent unintentional EEPROM writes a specific write procedure must be fol lowed Refer to Atomic Byte Programming on page 17 and Split Byte Programming on page 17 for details on this When the EEPROM is read the CPU is halted for four clock cycles before the next instruction is executed When the EEPROM is written the CPU is halted for two clock cycles before the next instruction is executed Bit 7 6 5 4 3 2 1 0 RES RRE RR EEARL Read Write R R RW RW RW RW R W RW Initial Value 0 0 X x x x x x e Bits 7 6 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bits 5 0 EEAR5 0 EEPROM Address The EEPROM Address Register EEARL specifies the EEPROM address in the 64 bytes EEPROM space The EEPROM data bytes are addressed linearly between 0 and 63 The initial value of EEARL is undefined A proper value must be written before the EEPROM may be accessed Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value X x x X X X X x Bits 7 0 EEDR7 0 EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEARL Register For the EEPROM read oper ation the EEDR contains the data read out from the EEPROM at the address given by EEARL AMEL EEPROM Control Register EECR AMEL Bit 7 6 5 4 3 2 1 0 Read Write R R R W R W R W R W R W R W Initial Va
121. is cleared none of the interrupts are enabled independent of the individual interrupt enable settings The I bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts The l bit can also be set and cleared by the application with the SEI and CLI instructions as described in the instruction set reference e Bit 6 T Bit Copy Storage The Bit Copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source or destination for the operated bit A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction e Bit 5 H Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations Half Carry is useful in BCD arithmetic See the Instruction Set Description for detailed information Bit4 S Sign Bit S NOV The S bit is always an exclusive or between the Negative Flag N and the Two s Comple ment Overflow Flag V See the Instruction Set Description for detailed information Bit 3 V Two s Complement Overflow Flag The Two s Complement Overflow Flag V supports two s complement arithmetics See the Instruction Set Description for detailed information e Bit 2 N Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation See the Instruction Set Description f
122. is done by selecting a long enough time out period EEPROM can not be written below 1 9 Volt Writing the EEPROM at Vec below 1 9 volts might fail Problem Fix Workaround Do not write the EEPROM when Vec is below 1 9 volts Revision A has not been sampled A MEL 167 Datasheet Revision History Changes from Rev 2535D 04 04 to Rev 2535E 10 04 Changes from Rev 2535C 02 04 to Rev 2535D 04 04 Changes from Rev 2535B 01 04 to Rev 2535C 02 04 Changes from Rev 2535A 06 03 to Rev 2535B 01 04 e of EE eS PS AMEL Please note that the referring page numbers in this section are referring to this docu ment The referring revision in this section are referring to the document revision Bits EEMWE EEWE changed to EEMPE EEPE in document Updated Pinout ATtiny13 on page 2 Updated Write Fuse Low Bits in Table 55 on page 116 Table 57 on page 120 Added Pin Change Interrupt Timing on page 53 Updated General Interrupt Mask Register GIMSK on page 55 Updated Pin Change Mask Register PCMSK on page 56 Updated item 4 in Serial Programming Algorithm on page 107 Updated Enter High voltage Serial Programming Mode on page 112 Updated DC Characteristics on page 119 Updated ATtiny13 Typical Characteristics on page 123 Updated Ordering Information on page 161 Updated Packaging Information on page 162 Updated Errata on page 166 Maximum
123. is executed Bit 2 OCFOA Output Compare Flag 0 A The OCFOA bit is set when a Compare Match occurs between the Timer CounterO and the data in OCROA Output Compare Register0 OCFOA is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCFOA is cleared by writing a logic one to the flag When the I bit in SREG OCIEOA Timer CounterO Compare Match Interrupt Enable and OCFOA are set the Timer CounterO Compare Match Interrupt is executed Bit 1 TOVO Timer Counter0 Overflow Flag The bit TOVO is set when an overflow occurs in Timer CounterO TOVO is cleared by hardware when executing the corresponding interrupt handling vector Alternatively TOVO is cleared by writing a logic one to the flag When the SREG I bit TOIEO Timer CounterO Overflow Interrupt Enable and TOVO are set the Timer CounterO Overflow interrupt is executed The setting of this flag is dependent of the WGM02 0 bit setting Refer to Table 32 Waveform Generation Mode Bit Description on page 70 AMEL n Timer Counter Prescaler Prescaler Reset External Clock Source AMEL The Timer Counter can be clocked directly by the system clock by setting the CSn2 0 1 This provides the fastest operation with a maximum Timer Counter clock frequency equal to system clock frequency fc vo Alternatively one of four taps from the prescaler can be used as a clock source The prescaled clock has a frequency
124. ister con tents disabling all chip functions until the next Interrupt or Hardware Reset The ADC Noise Reduction mode stops the CPU and all I O modules except ADC to minimize switching noise during ADC conversions The device is manufactured using Atmel s high density non volatile memory technology The On chip ISP Flash allows the Program memory to be re programmed In System through an SPI serial interface by a conventional non volatile memory programmer or by an On chip boot code running on the AVR core The ATtiny13 AVR is supported with a full suite of program and system development tools including C Compilers Macro Assemblers Program Debugger Simulators In Cir cuit Emulators and Evaluation kits Digital supply voltage Ground Port B is a 6 bit bi directional I O port with internal pull up resistors selected for each bit The Port B output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port B pins that are externally pulled low will source current if the pull up resistors are activated The Port B pins are tri stated when a reset condition becomes active even if the clock is not running Port B also serves the functions of various special features of the ATtiny13 as listed on page 50 Reset input A low level on this pin for longer than the minimum pulse length will gener ate a reset even if the clock is not running The minimum pulse length is given in Table 12 on page
125. ite EEPROM Memory 1100 0000 000x xxxx xxbb bbbb iiii iiii Write data i to EEPROM memory at address b Load EEPROM Memory 1100 0001 0000 0000 0000 OObb iiii iiii Load data i to EEPROM memory page Page page access buffer After data is loaded program EEPROM page Write EEPROM Memory 1100 0010 OOXX xxxx xxbb bbOO XXXX XXXX Page page access Write EEPROM page at address b Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits 0 programmed 1 unprogrammed See Table 42 on page 102 for details Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits Set bits 0 to program Lock bits See Table 42 on page 102 for details Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits 0 to program 1 to unprogram Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits 0 to program 1 to unprogram See Table 36 on page 84 for details Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits 0 programmed 1 unprogrammed Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx 0000 oooo Read Fuse High bits 0 pro grammed 1 unprogrammed See Table 36 on page 84 for details Read Calibration Byte 0011 1000 000x xxxx 0000 0000 oooo oooo Read C
126. lash Program memory EEPROM Programming Data memory Lock bits and Fuse bits in the ATtiny13 Figure 57 High voltage Serial Programming 11 5 12 5V 1 8 5 5V O O PB5 RESET SERIAL CLOCK INPUT PB3 CLKI SCK MISO MOSI Table 52 Pin Name Mapping Signal Name in High voltage Serial Programming Mode Pin Name I O Function SDI PBO l Serial Data Input SII PB1 Serial Instruction Input SDO PB2 O Serial Data Output SCI PB3 l Serial Clock Input min 220ns period The minimum period for the Serial Clock Input SCI during High voltage Serial Pro gramming is 220 ns Table 53 Pin Values Used to Enter Programming Mode Pin Symbol Value SDI Prog enable 0 0 SII Prog enable 1 0 SDO Prog enable 2 0 A MEL 111 2535E AVR 10 04 High voltage Serial Programming Algorithm Enter High voltage Serial Programming Mode Considerations for Efficient Programming AMEL To program and verify the ATtiny13 in the High voltage Serial Programming mode the following sequence is recommended See instruction formats in Table 55 The following algorithm puts the device in High voltage Serial Programming mode 1 Apply 4 5 5 5V between Vcc and GND 2 Set RESET pin to 0 and toggle SCI at least six times 3 Setthe Prog enable pins listed in Table 53 to 000 and wait at least 100 ns 4 Apply Vuyrst 12 5V to RESET Keep the Prog enable pins unchanged for at least tyyr
127. le in the program If the register is cleared before another reset occurs the source of the reset can be found by examining the Reset Flags ATtiny13 features an internal bandgap reference This reference is used for Brown out Detection and it can be used as an input to the Analog Comparator or the ADC The voltage reference has a start up time that may influence the way it should be used The start up time is given in Table 15 To save power the reference is not always turned on The reference is on during the following situations 1 When the BOD is enabled by programming the BODLEVEL 1 0 Fuse 2 When the bandgap reference is connected to the Analog Comparator by setting the ACBG bit in ACSR 3 When the ADC is enabled Thus when the BOD is not enabled after setting the ACBG bit or enabling the ADC the user must always allow the reference to start up before the output from the Analog Com parator or ADC is used To reduce power consumption in Power down mode the user can avoid the three conditions above to ensure that the reference is turned off before entering Power down mode Table 15 Internal Voltage Reference Characteristics Symbol Parameter Min Typ Max Units VBG Bandgap reference voltage 1 0 1 1 1 2 V taa Bandgap reference start up time 40 70 US Bandgap reference current B consumption Note 1 Values are guidelines only Actual values are TBD ATMEL 5 Watchdog Timer A
128. lobal Interrupt Enable bit is cleared the cor responding Interrupt Flag s will be set and remembered until the Global Interrupt Enable bit is set and will then be executed by order of priority The second type of interrupts will trigger as long as the interrupt condition is present These interrupts do not necessarily have Interrupt Flags If the interrupt condition disap pears before the interrupt is enabled the interrupt will not be triggered When the AVR exits from an interrupt it will always return to the main program and exe cute one more instruction before any pending interrupt is served Note that the Status Register is not automatically stored when entering an interrupt rou tine nor restored when returning from an interrupt routine This must be handled by software When using the CLI instruction to disable interrupts the interrupts will be immediately disabled No interrupt will be executed after the CLI instruction even if it occurs simulta neously with the CLI instruction The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence Assembly Code Example in r16 SREG store SREG value cli disable interrupts during timed sequence SbiEECR EEMPE start EEPROM write sbi EECR EEPE out SREG r16 restore SREG value I bit C Code Example char cSREG CSREG SREG store SREG value disable interrupts duri
129. lock SOUCES E 22 Default Clock Gource eene nnne nnne entren 22 Calibrated Internal RC Oscillator ssseseeeenneenennn 23 External Clock c M A 24 128 kHz Internal Oecllaior nennen 25 System Clock Prescaler sse eene 25 Power Management and Sleep Modes 27 Idle Modo una ee teo IDEE EUR D e RE Rent 28 ADC Noise Reduction Mode 28 Power down Mode A 28 Minimizing Power Consumption nennen 29 System Control and Reset mrrrnnavvnnnnnnnnnnnnnvvnnnnnnnnnnvnnnnnnnnnnnnnnennnnnnnnnn 30 Internal Voltage Reference uk 35 Watchdog WR 36 drug cM OI an 41 2535E AVR 10 04 AMEL Interrupt Vectors in ATtiny13 seen 41 DC POFIS oppido NE NN 42 I g 4 00 01 GUO MN ER 42 Ports as General Digital UO 43 Alternate Port FUNGUONS sesser beeseeu eei Eed ER ie edge en LX ee Eu eua 47 Register Description for UO Porte 52 External InterrUptS T c m 53 Pin Change Interrupt Timing 53 External Interrupt registers enn 54 8 bit Timer CounterO with PW M e eeeeee seen enne nnn 57 o ETE 57 Timer Counter Clock Gources sse nennen 58 Co nter UNI E 58 Output Compare Uhit aic cecinerunt needs ci tat aeuo a de Dax e da E ace 59 Compare Match Output Unnt neret 61 Modes of Operation iir E tte bed Ee i Geh ede e Pee SEN 62 Timer Counter Timing Diagorams enne 66 8 bit Timer Counter Re
130. lue 0 0 X X 0 0 X 0 Bit 7 Res Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny13 For compatibility with future AVR devices always write this bit to zero After reading mask out this bit Bit 6 Res Reserved Bit This bit is reserved in the ATtiny13 and will always read as zero Bits 5 4 EEPM1 and EEPMO EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE It is possible to program data in one atomic opera tion erase the old value and program the new value or to split the Erase and Write operations in two different operations The Programming times for the different modes are shown in Table 1 While EEPE is set any write to EEPMn will be ignored During reset the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming Table 1 EEPROM Mode Bits Programming EEPM1 EEPMO Time Operation 0 0 3 4 ms Erase and Write in one operation Atomic Operation 0 1 1 8 ms Erase Only 1 0 1 8 ms Write Only 1 1 Reserved for future use Bit 3 EERIE EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set Writing EERIE to zero disables the interrupt The EEPROM Ready Interrupt generates a constant interrupt when Non volatile memory is ready for programming Bit2 EEMPE EEPROM Master Program Enable The EE
131. ly of how the conver sion was started AMEL s 2535E AVR 10 04 Prescaling and Conversion Timing AMEL Figure 42 ADC Prescaler Reset 7 BIT ADC PRESCALER ADPSO ADPS1 ADPS2 ADC CLOCK SOURCE By default the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution If a lower resolution than 10 bits is needed the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate The ADC module contains a prescaler which generates an acceptable ADC clock fre quency from any CPU frequency above 100 kHz The prescaling is set by the ADPS bits in ADCSRA The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA The prescaler keeps running for as long as the ADEN bit is set and is continuously reset when ADEN is low When initiating a single ended conversion by setting the ADSC bit in ADCSRA the con version starts at the following rising edge of the ADC clock cycle A normal conversion takes 13 ADC clock cycles The first conversion after the ADC is switched on ADEN in ADCSRA is set takes 25 ADC clock cycles in order to initialize the analog circuitry The actual sample and hold takes place 1 5 ADC clock cycles after the start of a normal conversion and 14 5 ADC clock cycles after the start of an first conversion When a con version is complete the result is written to the ADC
132. me In order to reduce power consumption the clocks to modules not being used can be halted by using different sleep modes as described in Power Management and Sleep Modes on page 27 The clock systems are detailed below Figure 11 Clock Distribution General UO Flash and ad uii EEPROM AVR Clock Control Unit Reset Logic Watchdog Timer Source clock Watchdog clock Watchdog Oscillator Clock Multiplexer Calibrated RC Oscillator External Clock The CPU clock is routed to parts of the system concerned with operation of the AVR core Examples of such modules are the General Purpose Register File the Status Reg ister and the Data memory holding the Stack Pointer Halting the CPU clock inhibits the core from performing general operations and calculations The I O clock is used by the majority of the I O modules like Timer Counter The I O clock is also used by the External Interrupt module but note that some external inter rupts are detected by asynchronous logic allowing such interrupts to be detected even if the I O clock is halted The Flash clock controls operation of the Flash interface The Flash clock is usually active simultaneously with the CPU clock The ADC is provided with a dedicated clock domain This allows halting the CPU and I O clocks in order to reduce noise generated by digital circuitry This gives more accu rate ADC conversion results AMEL Clock Sources
133. minal Frequency 100 9 6 MHz 01 4 8 MHz Note 1 The device is shipped with this option selected When this Oscillator is selected start up times are determined by the SUT Fuses as shown in Table 5 Table 5 Start up Times for the Internal Calibrated RC Oscillator Clock Selection Start up Time Additional Delay from SUT1 0 from Power down Reset Vcc 5 0V Recommended Usage 00 6 CK 14CK BOD enabled 01 6 CK 14CK 4 ms Fast rising power 100 6 CK 14CK 64 ms Slowly rising power 11 Reserved Note 1 The device is shipped with this option selected Bit 7 6 5 4 3 2 1 0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CALO OSCCAL Read Write R R W R W R W R W R W R W R W Initial Value 0 Device Specific Calibration Value Bit 7 Res Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero e Bits 6 0 CAL6 0 Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove pro cess variations from the Oscillator frequency This is done automatically during Chip Reset When OSCCAL is zero the lowest available frequency is chosen Writing non zero values to this register will increase the frequency of the internal Oscillator Writing Ox7F to the register gives the highest available frequency The calibrated Oscillator is used to time EEPROM and Flash access If EEPROM or Flash is written do not cali brate to more than 1096
134. n 162 SPS E A dd hee 162 852 bedi 163 SI ERa 164 Zu 165 zip MT o 166 AT ny Ig Rev Di MEE 166 ANIIS Bev B o Here a e PEE De a eret ded aS 166 A MEL iii iv AMEL ATUNY TS Rev Ais E A A E AAE E 167 Datasheet Revision History rrrnrrnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnn 168 Changes from Rev 2535D 04 04 to Rev 2535E 10 04 aeee 168 Changes from Rev 2535C 02 04 to Rev 2535D 04 04 sess 168 Changes from Rev 2535B 01 04 to Rev 2535C 02 04 seese 168 Changes from Rev 2535A 06 03 to Rev 2535B 01 04 secese 168 Ee i 2535E AVR 10 04 AIMEL EE S Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Atmel Operations Memory 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 Microcontrollers 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 436 4314 La Chantrerie RF Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany Tel 49 71 31 67 0 Fax 49 71 31 67 2340 1150 East Cheyenne Mtn Blvd Colorado Springs CO 80906 USA Tel 1 719 576 3300 Fax 1 719 540 17
135. nc Rd Y Y Y 1 None 2 LD Rd Y Load Indirect and Pre Dec Ye Y 1 Rd Y None 2 LDD Rd Y4q Load Indirect with Displacement Rd Y q None 2 LD Rd Z Load Indirec Rd Z None 2 LD Rd Z Load Indirect and Post Inc Rd Z Z Z4 None 2 LD Rd Z Load Indirect and Pre Dec Z Z 1 Rd Z None 2 LDD Rd Z q Load Indirect with Displacement Rd Z q None 2 LDS Rd k Load Direct from SRAM Rd lt k None 2 ST X Rr Store Indirect X Rr None 2 ST X Rr Store Indirect and Post Inc X Rr X lt X 1 None 2 ST X Rr Store Indirect and Pre Dec X lt X 1 X lt Rr None 2 ST Y Rr Store Indirec Y lt Rr None 2 ST Y Rr Store Indirect and Post Inc Y lt Rr Y Y 1 None 2 ST Y Rr Store Indirect and Pre Dec Y lt Y 1 Y lt Rr None 2 STD Y q Rr Store Indirect with Displacement Y q lt Rr None 2 ST Z Rr Store Indirect Z lt Rr None 2 ST Z Rr Store Indirect and Post Inc Ge Rr ZeZ 1 None 2 ST Z Rr Store Indirect and Pre Dec Z lt Z 1 Z lt Rr None 2 STD Z q Rr Store Indirect with Displacement Z q Rr None 2 STS k Rr Store Direct to SRAM k Rr None 2 LPM Load Program Memory RO lt Z None 3 LPM Rd Z Load Program Memory Rd lt Z None 3 LPM Rd Z Load Program Memory and Post Inc Rd lt Z Z Z 1 None 3 SPM Store Program Memory z R1 RO None IN Rd P In Port Rd lt P None 1 OUT P Rr Out Port P lt Rr None 1 PUSH Rr Push Register on Stack STACK lt Rr None 2 POP Rd P
136. nce voltage replaces the positive input to the Analog Comparator When this bit is cleared AINO is applied to the positive input of the Analog Comparator Bit 5 ACO Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO The synchronization introduces a delay of 1 2 clock cycles e Bit4 ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACISO The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I bit in SREG is set ACI is cleared by hardware when execut ing the corresponding interrupt handling vector Alternatively ACI is cleared by writing a logic one to the flag Bit 3 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I bit in the Status Register is set the Ana log Comparator interrupt is activated When written logic zero the interrupt is disabled e Bit 2 Res Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero Bits 1 0 ACIS1 ACISO Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator inter rupt The different settings are shown in Table 34 Table 34 ACIS1 ACISO Settings ACIS1 ACISO Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Compa
137. ncreased by software There are no special cases to consider in the Normal mode a new counter value can be written anytime The Output Compare Unit can be used to generate interrupts at some given time Using the Output Compare to generate waveforms in Normal mode is not recommended since this will occupy too much of the CPU time In Clear Timer on Compare or CTC mode WGM02 0 2 the OCROA Register is used to manipulate the counter resolution In CTC mode the counter is cleared to zero when the counter value TCNTO matches the OCROA The OCROA defines the top value for the counter hence also its resolution This mode allows greater control of the Compare Match output frequency It also simplifies the operation of counting external events The timing diagram for the CTC mode is shown in Figure 30 The counter value TCNTO increases until a Compare Match occurs between TCNTO and OCROA and then counter TCNTO is cleared Figure 30 CTC Mode Timing Diagram ge H i i i i i 4 i i i i i i i i i i i i i i 1 i i 4 i i 4 i i i i i i i i i A i i i i i i i i i i i i i i i T OCnx Interrupt Flag Set Y P fl TCNTn OCn Toggle An interrupt can be generated each time the counter value reaches the TOP value by using the OCFOA Flag If the interrupt is enabled the interrupt handler routine can be used for updating the TOP value However changi
138. ng TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature If the new value written COMnx1 0 1 2535E AVR 10 04 Fast PWM Mode 2535E AVR 10 04 to OCROA is lower than the current value of TCNTO the counter will miss the Compare Match The counter will then have to count to its maximum value OxFF and wrap around starting at 0x00 before the Compare Match can occur For generating a waveform output in CTC mode the OCOA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode COMOA1 0 1 The OCOA value will not be visible on the port pin unless the data direction for the pin is set to output The waveform generated will have a maxi mum frequency of foco fo vol when OCROA is set to zero 0x00 The waveform frequency is defined by the following equation c falk vo Ha 2 N 14OCRnx The N variable represents the prescale factor 1 8 64 256 or 1024 As for the Normal mode of operation the TOVO Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00 The fast Pulse Width Modulation or fast PWM mode WGM02 0 3 or 7 provides a high frequency PWM waveform generation option The fast PWM differs from the other PWM option by its single slope operation The counter counts from BOTTOM to TOP then restarts f
139. ng the device is kept in RESET after Voc rise The RESET signal is activated again without any delay when Vcc decreases below the detection level Figure 14 MCU Start up RESET Tied to Voc z Ad uM Voc POT RESET SC en TIME OUT ef INTERNAL RESET Figure 15 MCU Start up RESET Extended Externally sg V V 1 POT cc td Li D I f L _ K V RESET HM i i D I nf F TIME OUT trout INTERNAL I RESET i External Reset Brown out Detection 2535E AVR 10 04 An External Reset is generated by a low level on the RESET pin if enabled Reset pulses longer than the minimum pulse width see Table 12 will generate a reset even if the clock is not running Shorter pulses are not guaranteed to generate a reset When the applied signal reaches the Reset Threshold Voltage Vagr on its positive edge the delay counter starts the MCU after the Time out period Lou has expired Figure 16 External Reset During Operation Vcc RESET I i lt tour TIME OUT INTERNAL RESET ATtiny13 has an On chip Brown out Detection BOD circuit for monitoring the Vcc level during operation by comparing it to a fixed trigger level The trigger level for the BOD can be selected by the BODLEVEL Fuses The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be inter preted as Vgor Vgor Vuyst 2 and Vgor Vgor Viysr 2 Table 13 BODLEVEL Fuse Codin
140. ng timed sequence disable interrupt EECR 1 lt lt EEMPE start EEPROM write EECR 1 lt lt EEPE SREG cSREG restore SREG value I bit AMEL Interrupt Response Time AMEL When using the SEI instruction to enable interrupts the instruction following SEI will be executed before any pending interrupts as shown in this example Assembly Code Example sei set Global Interrupt Enable sleep enter sleep waiting for interrupt note will enter sleep before any pending interrupt s C Code Example enable interrupt set Global Interrupt Enable Sleep enter sleep waiting for interrupt note will enter sleep before any pending interrupt s The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum After four clock cycles the Program Vector address for the actual interrupt handling routine is executed During this four clock cycle period the Program Counter is pushed onto the Stack The vector is normally a jump to the interrupt routine and this jump takes three clock cycles If an interrupt occurs during execution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles This increase comes in addition
141. nge Interrupt 2 ADC Input channel or Pin Change Interrupt 3 ADC Input channel Clock Input or Pin Change Interrupt 4 Serial Clock Input Timer Counter Clock Input ADC Input Channel 0 or Pin Change Interrupt 5 Serial Data Input Analog Comparator Negative Input Output Compare and PWM Output B for Timer Counter External Interrupt O or Pin Change Interrupt 6 Serial Data Output Analog Comparator Positive Input Output Compare and PWM Output A for Timer Counter or Pin Change Interrupt Table 22 and Table 23 on page 51 relate the alternate functions of Port B to the overrid ing signals shown in Figure 24 on page 48 Table 22 Overriding Signals for Alternate Functions in PB5 PB3 Signal PB5 RESET Name ADCO PCINT5 PB4 ADC2 PCINT4 PB3 ADC3 CLKI PCINT3 PUOE RSTDISBL e DWEN 0 0 PUOV 1 0 0 DDOE RSTDISBL DWEN 0 0 DDOV debugWire Transmit 0 0 PVOE 0 0 0 PVOV 0 0 0 PTOE 0 0 0 DIEOE RSTDISBL PCINT5 PCINT4 PCIE ADC2D PCINT3 PCIE ADC3D PCIE ADCOD DIEOV ADCOD ADC2D ADC3D DI PCINTS5 Input PCINT4 Input PCINTS Input AlO RESET Input ADCO Input ADC2 Input ADC3 Input Note 1 1 when the Fuse is 0 Programmed Table 23 Overriding Signals for Alternate Functions in PB2 PBO Signal PB2 SCK ADC1 PB1 MISO AIN1 PBO MOSI AINO AREF Name TO PCINT2 OCOB INTO PCINT1 OCOA PCINTO PUOE 0 0 0
142. nput buffer on the AIN1 0 pin is disabled The corresponding PIN Register bit will always read as zero when this bit is set When an analog signal is applied to the AIN1 O pin and the digital input from this pin is not needed this bit should be written logic one to reduce power consumption in the digital input buffer 0 2535E AVR 10 04 Analog to Digital Converter Features 2535E AVR 10 04 10 bit Resolution 0 5 LSB Integral Non linearity 2 LSB Absolute Accuracy 13 260 ps Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 Vcc ADC Input Voltage Range Selectable 1 1V ADC Reference Voltage Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler The ATtiny13 features a 10 bit successive approximation ADC The ADC is connected to a 4 channel Analog Multiplexer which allows four single ended voltage inputs con structed from the pins of Port B The single ended voltage inputs refer to OV GND The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion A block diagram of the ADC is shown in Figure 40 Internal reference voltages of nominally 1 1V or Voc are provided On chip ATMEL 79 Operation AMEL Figure 40 Analog to D
143. nsures that all users can make their desired clock source setting using an In System or High voltage Programmer 2535E AVR 10 04 Calibrated Internal RC Oscillator Oscillator Calibration Register OSCCAL 2535E AVR 10 04 The calibrated internal RC Oscillator provides an 9 6 MHz or 4 8 MHz clock The fre quency is the nominal value at 3V and 25 C If the frequency exceeds the specification of the device depends on Voc the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start up See System Clock Prescaler on page 25 for more details This clock may be selected as the system clock by program ming the CKSEL Fuses as shown in Table 4 If selected it will operate with no external components During reset hardware loads the calibration byte into the OSCCAL Regis ter and thereby automatically calibrates the RC Oscillator At 3V and 25 C this calibration gives a frequency within 10 of the nominal frequency Using calibration methods as described in application notes available at www atmel com avr it is possible to achieve 3 accuracy at any given Vcc and Temperature When this Oscillator is used as the chip clock the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time out For more information on the pre programmed calibration value see the section Calibration Byte on page 105 Table 4 Internal Calibrated RC Oscillator Operating Modes CKSEL1 0 No
144. of either fork vol fork 10 64 foi 105 256 or fork 9 1024 The prescaler is free running i e operates independently of the Clock Select logic of the Timer Counter Since the prescaler is not affected by the Timer Counter s clock select the state of the prescaler will have implications for situations where a prescaled clock is used One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler 6 CSn2 0 1 The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N 1 system clock cycles where N equals the prescaler divisor 8 64 256 or 1024 It is possible to use the Prescaler Reset for synchronizing the Timer Counter to program execution An external clock source applied to the TO pin can be used as Timer Counter clock clkz5 The TO pin is sampled once every system clock cycle by the pin synchronization logic The synchronized sampled signal is then passed through the edge detector Fig ure 37 shows a functional equivalent block diagram of the TO synchronization and edge detector logic The registers are clocked at the positive edge of the internal system clock clkyo The latch is transparent in the high period of the internal system clock The edge detector generates one clk pulse for each positive CSn2 0 7 or negative CSn2 0 6 edge it detects Figure 37 TO Pin Sampling Tn sync D Q gt W ty To Clock Select Logic LE
145. ollers have a three byte signature code which identifies the device This code can be read in both serial and High voltage Programming mode also when the device is locked The three bytes reside in a separate address space For the ATtiny13 the signature bytes are 1 0x000 Ox1E indicates manufactured by Atmel 2 0x001 0x90 indicates 1 KB Flash memory 3 0x002 0x07 indicates ATtiny13 device when 0x001 is 0x90 Calibration Byte Signature area of the ATtiny13 has one byte of calibration data for the internal RC Oscil lator This byte resides in the high byte of address 0x000 During reset this byte is automatically written into the OSCCAL Register to ensure correct frequency of the cali brated RC Oscillator Page Size Table 46 No of Words in a Page and No of Pages in the Flash FlashSize Page Size PCWORD No of Pages PCPAGE PCMSB Sa we Ko mn ez Table 47 No of Words in a Page and No of Pages in the EEPROM EEPROM Size PCWORD No of Pages PCPAGE EEAMSB 64 bytes 4 bytes EEA 1 0 16 EEA 5 2 5 A MEL 105 2535E AVR 10 04 Serial Downloading AMEL Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND The serial interface consists of pins SCK MOSI input and MISO output After RESET is set low the Programming Enable instruction needs to be executed first before program erase operations can be executed NOTE in Table 48 on page
146. on the polarity of the output set by the COMOA1 0 bits A frequency with 50 duty cycle waveform output in fast PWM mode can be achieved by setting OCOx to toggle its logical level on each Compare Match COMOx1 0 1 The waveform generated will have a maximum frequency of foco Lo 1 0 2 when OCROA is set to zero This feature is similar to the OCOA toggle in CTC mode except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode Phase Correct PWM Mode The phase correct PWM mode WGM02 0 1 or 5 provides a high resolution phase correct PWM waveform generation option The phase correct PWM mode is based on a dual slope operation The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM TOP is defined as OxFF when WGM2 0 1 and OCROA when WGM2 0 5 In non inverting Compare Output mode the Output Compare OCOx is cleared on the Compare Match between TCNTO and OCROx while upcounting and set on the Compare Match while down counting In inverting Output Compare mode the operation is inverted The dual slope operation has lower maximum operation frequency than single slope operation However due to the symmetric feature of the dual slope PWM modes these modes are preferred for motor control applications In phase correct PWM mode the counter is incremented until the counter value matches TOP When the counter reaches TOP it changes the count direction The TCNTO value will be equal to TOP
147. onal changes of clock frequency a special write procedure must be followed to change the CLKPS bits 1 Write the Clock Prescaler Change Enable CLKPCE bit to one and all other bits in CLKPR to zero 2 Within four cycles write the desired value to CLKPS while writing a zero to CLKPCE Interrupts must be disabled when changing prescaler setting to make sure the write pro cedure is not interrupted AMEL 2 Switching Time AMEL The CKDIV8 Fuse determines the initial value of the CLKPS bits If CKDIV8 is unpro grammed the CLKPS bits will be reset to 0000 If CKDIV8 is programmed CLKPS bits are reset to 0011 giving a division factor of eight at start up This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating condi tions The device is shipped with the CKDIV8 Fuse programmed Table 9 Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPSO Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1
148. op Register from Stack Rd lt STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep see specific descr for Sleep function None d WDR Watchdog Reset see specific descr for WDR Timer None 1 BREAK Break For On chip Debug Only None N A D 160 ATti ny1 3 EE 2535E AVR 10 04 Ordering Information Speed MHz Power Supply Ordering Code Package Operation Range ATtiny13V 10PI 8P3 ATtiny13V 10PU 8P3 ATtiny13V 10SI 8S2 10 18 55 ATtiny13V 10SU 852 Industrial oe ATtiny13V 10SSl S881 40 C to 85 C ATtiny13V 10SSU S881 ATtiny13V 10MI 20M1 ATtiny13V 10MU 20M1 ATtiny13 20PI 8P3 ATtiny13 20PU 8P3 ATtiny13 20Sl 8S2 20 27 55 ATtiny13 20SU 8S2 Industrial ae ATtiny13 20SSI S8S1 40 C to 85 C ATtiny13 20SSU S881 ATtiny13 20MI 20M1 ATtiny13 20MU 20M1 Notes 1 This device can also be supplied in wafer form Please contact your local Atmel sales office for detailed ordering information and minimum quantities 2 Pb free packaging alternative complies to the European Directive for Restriction of Hazardous Substances RoHS direc tive Also Halide free and fully Green 3 For Speed vs Voc see Maximum Speed vs VCC on page 121 Package Type 8P3 8 lead 0 300 Wide Plastic Dual Inline Package PDIP 8S2 8 lead 0 209 Wide Plastic Small Outline Package EIAJ SOIC S881 8 lead 0 150 Wide Plastic Gull Wing Small Outline JEDEC SOIC 20M1 20 pad 4 x
149. or continuously compares TCNTO with the Output Compare Regis ters OCROA and OCROB Whenever TCNTO equals OCROA or OCROB the comparator signals a match A match will set the Output Compare Flag OCFOA or OCFOB at the next timer clock cycle If the corresponding interrupt is enabled the Out put Compare Flag generates an Output Compare interrupt The Output Compare Flag is automatically cleared when the interrupt is executed Alternatively the flag can be cleared by software by writing a logical one to its I O bit location The Waveform Gener ator uses the match signal to generate an output according to operating mode set by the WGM02 0 bits and Compare Output mode COMOx1 0 bits The max and bottom sig nals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation See Modes of Operation on page 62 Figure 28 shows a block diagram of the Output Compare unit Figure 28 Output Compare Unit Block Diagram DATA BUS 8 bit Comparator OCFnx Int Req top bottom Waveform Generator FOCn WGMn1 0 COMnX1 0 AMEL 5 Force Output Compare Compare Match Blocking by TCNTO Write Using the Output Compare Unit AMEL The OCROx Registers are double buffered when using any of the Pulse Width Modula tion PWM modes For the normal and Clear Timer on Compare CTC modes of operation the double buffering is disabled The double buffering synchronizes
150. or detailed information Bit 1 Z Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation See the Instruction Set Description for detailed information Bit 0 C Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation See the Instruc tion Set Description for detailed information ATMEL AMEL General Purpose The Register File is optimized for the AVR Enhanced RISC instruction set In order to Register File achieve the required performance and flexibility the following input output schemes are 8 supported by the Register File e One 8 bit output operand and one 8 bit result input e Two 8 bit output operands and one 8 bit result input e Two 8 bit output operands and one 16 bit result input e One 16 bit output operand and one 16 bit result input Figure 4 shows the structure of the 32 general purpose working registers in the CPU Figure 4 AVR CPU General Purpose Working Registers 7 0 Addr 0x00 0x01 0x02 OxOD General Ox0E Purpose OxOF Working 0x10 Registers 0x11 Ox1A X register Low Byte Ox1B X register High Byte Ox1C Y register Low Byte Ox1D Y register High Byte Ox1E Z register Low Byte Ox1F Z register High Byte Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 4 each register is also ass
151. orrect waveform generation Similarly do not write the TCNTO value equal to BOTTOM when the counter is down counting The setup of the OCOx should be performed before setting the Data Direction Register for the port pin to output The easiest way of setting the OCOx value is to use the Force Output Compare FOCOx strobe bits in Normal mode The OCOx Registers keep their values even when changing between Waveform Generation modes Be aware that the COMOx1 0 bits are not double buffered together with the compare value Changing the COMOx1 0 bits will take effect immediately 2535E AVR 10 04 Compare Match Output Unit Compare Output Mode and Waveform Generation 2535E AVR 10 04 The Compare Output mode COMOx1 0 bits have two functions The Waveform Gener ator uses the COMOx1 0 bits for defining the Output Compare OCOXx state at the next Compare Match Also the COMOx1 0 bits control the OCOx pin output source Figure 29 shows a simplified schematic of the logic affected by the COMOx1 0 bit setting The I O Registers I O bits and I O pins in the figure are shown in bold Only the parts of the general I O Port Control Registers DDR and PORT that are affected by the COMOx1 0 bits are shown When referring to the OCOx state the reference is for the internal OCOx Register not the OCOx pin If a system reset occur the OCOx Register is reset to 0 Figure 29 Compare Match Output Unit Schematic m COMnx1
152. ou V AMEL 135 AMEL Figure 89 I O Pin Source Current vs Output Voltage Voc 2 7V I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Voc 2 7V 35 30 40 C 25 C 25 gt 85 C T 20 E I 9 15 5 0 0 0 5 1 1 5 2 2 5 3 Vou V Figure 90 I O Pin Source Current vs Output Voltage Vec 1 8V I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Voc 1 8V 10 40 C 25 C 85 C 7 _ 6 z E 5 k s 5 4 3 2 1 o 4 i 1 i i i l 0 0 2 0 4 0 6 0 8 1 12 14 1 6 1 8 2 Von V 1 ATtinyl3 mem 2535E AVR 10 04 Figure 91 UO Pin Sink Current vs Output Voltage Vec 5V I O PIN SINK CURRENT vs OUTPUT VOLTAGE Voc 5V 100 90 40 C 80 70 25 C _ 60 85 C lt E 50 3 40 30 20 10 0 4 i 0 0 5 1 15 2 2 5 Vor V Figure 92 I O Pin Sink Current vs Output Voltage Voc 2 7V I O PIN SINK CURRENT vs OUTPUT VOLTAGE Voc d 40 35 40 C 30 25 C 25 z 85 C E 2 3 15 10 5 0 d 0 0 5 1 1 5 2 2 5 Vor V A MEL 137 2535E AVR 10 04 138 AMEL Figure 93 UO Pin Sink Current vs Output Voltage Voc 1 8V I O PIN SINK CURRENT vs OUTPUT VOLTAGE Vcc 1 8V 40 C 25 C 85 C 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 Vor V Figure 94 Reset Pin as I O S
153. ource Current vs Output Voltage Vcc 5V lou MA RESET PIN AS I O SOURCE CURRENT vs OUTPUT VOLTAGE Voc 5V 40 C 25 C 85 C 3 Vou V 2535E AVR 10 04 Figure 95 Reset Pin as I O Source Current vs Output Voltage Vec 2 7V RESET PIN AS I O SOURCE CURRENT vs OUTPUT VOLTAGE Vec 2 7V 2 5 40 C 2 25 C 45 85 C lt x E I 9 1 0 5 0 0 0 5 1 1 5 2 2 5 3 Vou V Figure 96 Reset Pin as I O Source Current vs Output Voltage Voc 1 8V RESET PIN AS I O SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 1 8V 2 5 40 C 2 25 C 15 lt x E 5 85 C 1 0 5 0 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 Vou V A MEL 139 2535E AVR 10 04 AMEL Figure 97 Reset Pin as I O Sink Current vs Output Voltage Vec DN RESET PIN AS I O SINK CURRENT vs OUTPUT VOLTAGE Voc 5V 14 40 C 12 25 C 10 85 C e 8 E Ze A 2 0 0 0 5 1 15 2 5 Vo V Figure 98 Reset Pin as I O Sink Current vs Output Voltage Vcc 2 7V RESET PIN AS I O SINK CURRENT vs OUTPUT VOLTAGE Vec 2 7V 45 40 C 4 3 5 25 C 3 S 85 C T 25 E o 2 1 5 0 5 0 T T 0 0 5 1 1 5 2 5 Var V 14 ATtinyl3 me 2535E AVR 10 04 Pin Thresholds and Hysteresis 2535E AVR 10 04 Figure 99 Reset Pin as I O Sink
154. own in Figure 37 Bit 7 6 5 4 3 2 1 0 SM PSR j GTCCR Read Write RW R R R R R R RW Initial Value 0 0 0 0 0 0 0 0 e Bit 7 TSM Timer Counter Synchronization Mode Writing the TSM bit to one activates the Timer Counter Synchronization mode In this mode the value that is written to the PSR10 bit is kept hence keeping the Prescaler Reset signal asserted This ensures that the Timer Counter is halted and can be config ured without the risk of advancing during configuration When the TSM bit is written to zero the PSR10 bit is cleared by hardware and the Timer Counter start counting e Bit 0 PSR10 Prescaler Reset Timer CounterO When this bit is one the Timer CounterO prescaler will be Reset This bit is normally cleared immediately by hardware except if the TSM bit is set AIMEL S Analog Comparator ADC Control and Status Register B ADCSRB Analog Comparator Control and Status Register ACSR AMEL The Analog Comparator compares the input values on the positive pin AINO and nega tive pin AIN1 When the voltage on the positive pin AINO is higher than the voltage on the negative pin AIN1 the Analog Comparator output ACO is set The comparator can trigger a separate interrupt exclusive to the Analog Comparator The user can select Interrupt triggering on comparator output rise fall or toggle A block diagram of the com parator and its surrounding logic is shown in Figure 39 Figure 39 Analog Comparator Blo
155. parator Handler 0x0006 rjmp TIMO COMPA Timer0 CompareA Handler 0x0007 rjmp TIMO COMPB Timer0 CompareB Handler 0x0008 rjmp WATCHDOG Watchdog Interrupt Handler 0x0009 rjmp ADC ADC Conversion Handler 0x000A RESET ldi r16 low RAMEND Main program start 0x000B out SPL r16 Set Stack Pointer to top of RAM 0x000C sei Enable interrupts 0x000D lt instr gt xxx AIMEL n 2535E AVR 10 04 AMEL UO Ports Introduction All AVR ports have true Read Modify Write functionality when used as general digital I O ports This means that the direction of one port pin can be changed without uninten tionally changing the direction of any other pin with the SBI and CBI instructions The same applies when changing drive value if configured as output or enabling disabling of pull up resistors if configured as input Each output buffer has symmetrical drive characteristics with both high sink and source capability The pin driver is strong enough to drive LED displays directly All port pins have individually selectable pull up resistors with a supply voltage invariant resistance All UO pins have protection diodes to both Voc and Ground as indicated in Figure 20 Refer to Electrical Characteristics on page 119 for a complete list of parameters Figure 20 I O Pin Equivalent Schematic Logic See Figure General Digital I O for Details pin All registers and bit references in this section are written in gen
156. peration completes While the device is busy programming it is not possible to do any other EEPROM operations To write a location the user must write the address into EEARL and the data into EEDR If the EEPMn bits are 0b10 writing the EEPE within four cycles after EEMPE is written will trigger the write operation only programming time is given in Table 1 The EEPE bit remains set until the write operation completes If the location to be written has not been erased before write the data that is stored must be considered as lost While the device is busy with programming it is not possible to do any other EEPROM operations The calibrated Oscillator is used to time the EEPROM accesses Make sure the Oscilla tor frequency is within the requirements described in Oscillator Calibration Register OSCCAL on page 23 AMEL AMEL The following code examples show one assembly and one C function for erase write or atomic write of the EEPROM The examples assume that interrupts are controlled e g by disabling interrupts globally so that no interrupts will occur during execution of these functions Assembly Code Example EEPROM write Wait for completion of previous write sbic EECR EEPE rjmp EEPROM write Set Programming mode ldi r16 0 lt lt EEPM1 0 lt lt EEPMO out EECH r16 Set up address r17 in address register out EEARL r17 Write data r16 to
157. period from one clock cycle to the next 2 2 2 120 Maximum Speed vs Veg Maximum frequency is dependent on Vcc As shown in Figure 62 and Figure 63 the Maximum Frequency vs Vcc curve is linear between 1 8V lt Voc lt 2 7V and between 27V Noe lt 4 5V Figure 62 Maximum Frequency vs Vcc ATtiny13V 10 MHz Safe Operating Area 4 MHz 1 8V 2 7N 5 5V Figure 63 Maximum Frequency vs Vgc ATtiny13 20 MHz RE Safe Operating Area 2 7V 4 5V 5 5V A MEL 121 2535E AVR 10 04 AMEL ADC Characteristics Preliminary Data Table 58 ADC Characteristics Single Ended Channels 40 C 85 C Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Single Ended Conversion Vrer 4V Voc AV 2 LSB ADC clock 200 kHz Single Ended Conversion Vrer 4V Voc AV 3 LSB ADC clock 1 MHz Absolute accuracy Including INL DNL quantization error Nus peng ain and offset error REF UM voc Ns z ADC clock 200 kHz Io LSB Noise Reduction Mode Single Ended Conversion VREF 4V Vec 4V ADC clock 1 MHz 2s LSB Noise Reduction Mode Single Ended Conversion Integral Non linearity INL Vrer 4V Voc AV 1 LSB ADC clock 200 kHz Single Ended Conversion Differential Non linearity DNL Vgge 4V Voc AV 0 5 LSB ADC clock 200 kHz Single Ended Conversion G
158. purpose registers or between a register and an immediate are executed The ALU operations are divided into three main categories arithmetic logical and bit func tions Some implementations of the architecture also provide a powerful multiplier supporting both signed unsigned multiplication and fractional format See the Instruc tion Set section for a detailed description 2535E AVR 10 04 Status Register 2535E AVR 10 04 The Status Register contains information about the result of the most recently executed arithmetic instruction This information can be used for altering program flow in order to perform conditional operations Note that the Status Register is updated after all ALU operations as specified in the Instruction Set Reference This will in many cases remove the need for using the dedicated compare instructions resulting in faster and more compact code The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt This must be handled by software The AVR Status Register SREG is defined as Bit 7 6 5 4 3 2 1 0 COLLE sms Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 I Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled The individ ual interrupt enable control is then performed in separate control registers If the Global Interrupt Enable Register
159. r TIFRO Bit 2 OCIEOA Timer Counter0 Output Compare Match A Interrupt Enable When the OCIEOA bit is written to one and the I bit in the Status Register is set the Timer CounterO Compare Match A interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer CounterO occurs i e when the OCFOA bit is set in the Timer Counter 0 Interrupt Flag Register TIFRO Bit 1 TOIEO Timer CounterO Overflow Interrupt Enable When the TOIEO bit is written to one and the I bit in the Status Register is set the Timer CounterO Overflow interrupt is enabled The corresponding interrupt is executed if an overflow in Timer CounterO occurs i e when the TOVO bit is set in the Timer Counter 0 Interrupt Flag Register TIFRO Bit 7 6 5 4 3 2 1 0 Lees Tecra vow re Read Write R R R R R W R W R W R Initial Value 0 0 0 0 0 0 0 0 Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bit 3 OCFOB Output Compare Flag 0 B The OCFOB bit is set when a Compare Match occurs between the Timer Counter and the data in OCROB Output Compare RegisterO B OCFOB is cleared by hardware when executing the corresponding interrupt handling vector Alternatively OCFOB is cleared by writing a logic one to the flag When the I bit in SREG OCIEOB Timer Counter Compare B Match Interrupt Enable and OCFOB are set the Timer Counter Compare Match Interrupt
160. r Rd lt OxFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC lt PC k 1 None 2 IJMP Indirect Jump to Z PC Z None 2 RCALL k Relative Subroutine Call PC lt PC k 1 None 3 ICALL Indirect Call to Z PCc Z None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK l 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 20r3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 20r3 None 1 2 3 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC lt PC 20r3 None 1 2 3 SBIS P b Skip if Bit in UO Register is Set if P b 1 PC PC 20r 3 None 1 2 3 BRBS S k Branch if Status Flag Set if SREG s 1 then PC lt PC k 1 None 1 2 BRBC s k Branch if Status Flag Cleared if SREG s 0 then PC lt PC k 1 None 1 2 BREQ k Branch if Equal if Z 1 then PC PC k 1 None 1 2 BRNE k Branch if Not Equal if Z 0 then PC PC k 1 None 1 2 BRCS k Branch if Carry Set if C 1 then PC PC k 1 None 1 2 BRCC k Branch if Carry Cleared if C 0 then PC PC k 1 None 1 2 BRSH k Branch if Same or Higher if C 0 then PC PC k 1 None 1 2 BRLO k Branch if Lower if C 1 then PC PC k 1 None 1 2 BRMI k Branch if Minus if N 1 then PC PC k 1
161. rator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge When changing the ACIS1 ACISO bits the Analog Comparator Interrupt must be dis abled by clearing its Interrupt Enable bit in the ACSR Register Otherwise an interrupt can occur when the bits are changed AMEL 7 Analog Comparator Multiplexed Input AMEL It is possible to select any of the ADC3 0 pins to replace the negative input to the Ana log Comparator The ADC multiplexer is used to select this input and consequently the ADC must be switched off to utilize this feature If the Analog Comparator Multiplexer Enable bit ACME in ADCSRB is set and the ADC is switched off ADEN in ADCSRA is zero MUX1 0 in ADMUX select the input pin to replace the negative input to the Ana log Comparator as shown in Table 35 If ACME is cleared or ADEN is set AIN1 is applied to the negative input to the Analog Comparator Table 35 Analog Comparator Multiplexed Input ACME ADEN MUX1 0 Analog Comparator Negative Input 0 X XX AIN1 1 1 XX AIN1 1 0 00 ADCO 1 0 01 ADC1 1 0 10 ADC2 1 0 11 ADC3 Digital Input Disable Register 0 DIDRO Bit 2 1 0 EES Ces Ancsb ADT Aib ANGD ven R W R W R W R W R W 78 Read Write R Initial Value 0 0 6 5 ADCOD R R W 0 4 3 0 0 0 0 Bits 1 0 AIN1D AINOD AIN1 AINO Digital Input Disable When this bit is written logic one the digital i
162. re 127 Reset Supply Current vs Voc 0 1 1 0 MHz Excluding Current through the Reset Pull up lcc mA 0 14 RESET SUPPLY CURRENT vs Voc 0 1 1 0 MHz EXCLUDING CURRENT THROUGH THE RESET PULL UP 5 5V 5 0V 4 5V 4 0V 3 3V EA 1 8V 0 1 0 2 0 3 0 4 0 5 0 6 Frequency MHz Figure 128 Reset Supply Current vs Voc 1 24 MHz Excluding Current through the Reset Pull up 3 5 RESET SUPPLY CURRENT vs Vcc 1 24 MHz EXCLUDING CURRENT THROUGH THE RESET PULL UP 5 5V 4 5V 4 0V AMEL Frequency MHz 24 155 AMEL Figure 129 Reset Pulse Width vs Voc RESET PULSE WIDTH vs M o 2500 2000 1500 S E 3 amp 1000 500 85 C 25 C 40 C 04 15 ATtinyl3 me 2535E AVR 10 04 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Ox3F SREG l T H S V N Z G page 7 0x3E Reserved Ox3D SPL SP 7 0 page 9 Ox3C Reserved Ox3B GIMSK INTO PCIE page 55 Ox3A
163. ress contains a 16 or 32 bit instruction During interrupts and subroutine calls the return address Program Counter PC is stored on the Stack The Stack is effectively allocated in the general data SRAM and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM All user programs must initialize the SP in the Reset routine before subroutines or interrupts are executed The Stack Pointer SP is read write accessible in the I O space The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture The memory spaces in the AVR architecture are all linear and regular memory maps A flexible interrupt module has its control registers in the I O space with an additional Global Interrupt Enable bit in the Status Register All interrupts have a separate Interrupt Vector in the Interrupt Vector table The interrupts have priority in accordance with their Interrupt Vector position The lower the Interrupt Vector address the higher the priority The I O memory space contains 64 addresses for CPU peripheral functions as Control Registers SPI and other I O functions The I O memory can be accessed directly or as the Data Space locations following those of the Register File Ox20 Ox5F The high performance AVR ALU operates in direct connection with all the 32 general purpose working registers Within a single clock cycle arithmetic operations between general
164. ristics Preliminary Data on page 122 Updated ATtiny13 Typical Characteristics on page 123 Updated Ordering Information on page 161 Updated Packaging Information on page 162 Updated Errata on page 166 Changed instances of EEAR to EEARL A MEL 169 AIMEL vo ATtinyl3 me Table of Contents CC T 1 Pin CONTIG ON ATI OTIS e 2 Qu mL T 2 Block Diagram zt Eo retten tt e Di De re ER EE eh b o Reps 3 PINIDESGHPUONS a H H 4 About Code EN ANOS M 4 AVR ee 5 Ta 1 do 0 1010 0 o CE H 5 Architectural Overvlew 5 ALU Arithmetic Logic Unit eite teet tu tec test ien 6 Status Register AAA 7 General Purpose Register File 8 Stack POUMC ae m 9 Instruction Execution TIMING eses enm 10 Reset and Interrupt Handling 10 AVR ATtiny13 Memories aske 3 esnSan qae ba ns FERNER EU EPAU ERE SESTU dE 13 In System Re programmable Flash Program Memory sees 13 SRAM Data Memory visum nouerit eo lag der Ee Cua e DER Ra SEL E FERE Pe URN Ea eO ad 14 EEPROM Data MOmoty edere ertet ee rk dt eR ERE RE ewes ako Yn ced death nakne 15 Hen ceisas 20 System Clock and Clock Options eese 21 Clock Systems and their Distribution sessseeseeeneeeenee 21 C
165. rogram memory This concept enables instructions to be executed in every clock cycle The Program memory is In System Reprogrammable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with a single clock cycle access time This allows single cycle Arithmetic Logic Unit ALU operation In a typical ALU operation two operands are output from the Register File AMEL s 2535E AVR 10 04 ALU Arithmetic Logic Unit AMEL the operation is executed and the result is stored back in the Register File in one clock cycle Six of the 32 registers can be used as three 16 bit indirect address register pointers for Data Space addressing enabling efficient address calculations One of the these address pointers can also be used as an address pointer for look up tables in Flash Pro gram memory These added function registers are the 16 bit X Y and Z register described later in this section The ALU supports arithmetic and logic operations between registers or between a con stant and a register Single register operations can also be executed in the ALU After an arithmetic operation the Status Register is updated to reflect information about the result of the operation Program flow is provided by conditional and unconditional jump and call instructions able to directly address the whole address space Most AVR instructions have a single 16 bit word format Every Program memory add
166. rom BOTTOM TOP is defined as OxFF when WGM2 0 3 and OCROA when WGM2 0 7 In non inverting Compare Output mode the Output Compare OCOx is cleared on the Compare Match between TCNTO and OCROx and set at BOTTOM In inverting Compare Output mode the output is set on Compare Match and cleared at BOTTOM Due to the single slope operation the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual slope opera tion This high frequency makes the fast PWM mode well suited for power regulation rectification and DAC applications High frequency allows physically small sized exter nal components coils capacitors and therefore reduces total system cost In fast PWM mode the counter is incremented until the counter value matches the TOP value The counter is then cleared at the following timer clock cycle The timing diagram for the fast PWM mode is shown in Figure 31 The TCNTO value is in the timing diagram shown as a histogram for illustrating the single slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNTO slopes represent Compare Matches between OCROx and TCNTO ATMEL AMEL Figure 31 Fast PWM Mode Timing Diagram OCRnx Interrupt Flag Set TUE RUM E pn oT ER TS rr OCRNX Update and i j i i TOVn Interrupt Flag Set i i i i i i i i i i i i TCNTn OCn COMnx1 0 2 Cn COMnx1 0 3 Period L
167. rs used with the debugWire Bit 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 The DWDR Register provides a communication channel from the running program in the MCU to the debugger This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations 2535E AVR 10 04 Self Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer Page Loading Performing a Page Write 2535E AVR 10 04 The device provides a Self Programming mechanism for downloading and uploading program code by the MCU itself The Self Programming can use any available data interface and associated protocol to read code and write program that code into the Program memory The Program memory is updated in a page by page fashion Before programming a page with the data stored in the temporary page buffer the page must be erased The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation Alternative 1 fill the buffer before a Page Erase e Fill temporary page buffer e Perform a Page Erase e Perform a Page Write Alternative 2 fill the buffer after Page Erase e Perform a Page Erase Fill temporary page buffer e Perform a Page Write If only a part of the page needs to be changed the rest of the p
168. rupt The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors The complete list of vectors is shown in Interrupts on page 41 The list also determines the priority levels of the different interrupts The lower the address the higher is the priority level RESET has the highest priority and next is INTO the External Interrupt Request O When an interrupt occurs the Global Interrupt Enable I bit is cleared and all interrupts are disabled The user software can write logic one to the I bit to enable nested inter rupts All enabled interrupts can then interrupt the current interrupt routine The I bit is automatically set when a Return from Interrupt instruction RETI is executed 2535E AVR 10 04 2535E AVR 10 04 There are basically two types of interrupts The first type is triggered by an event that sets the Interrupt Flag For these interrupts the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine and hardware clears the corresponding Interrupt Flag Interrupt Flags can also be cleared by writing a logic one to the flag bit position s to be cleared If an interrupt condition occurs while the corresponding interrupt enable bit is cleared the Interrupt Flag will be set and remem bered until the interrupt is enabled or the flag is cleared by software Similarly if one or more interrupt conditions occur while the G
169. s Bits 3 2 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bits 1 0 WGM01 0 Waveform Generation Mode Combined with the WGMO 2 bit found in the TCCROB Register these bits control the counting sequence of the counter the source for maximum TOP counter value and what type of waveform generation to be used see Table 32 Modes of operation sup ported by the Timer Counter unit are Normal mode counter Clear Timer on Compare Match CTC mode and two types of Pulse Width Modulation PWM modes see Modes of Operation on page 62 Table 32 Waveform Generation Mode Bit Description Timer Counter Mode of Update of TOV Fla Mode WGM2 WGM1 WGMO Operation TOP OCRxat Seton 0 0 0 0 Normal OxFF Immediate MAX 1 0 0 1 PWM Phase OxFF TOP BOTTOM Correct 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM OxFF TOP MAX 4 1 0 0 Reserved 5 1 0 1 PWM Phase OCRA TOP BOTTOM Correct 6 1 1 0 Reserved 7 1 1 1 Fast PWM OCRA TOP TOP Notes 1 MAX OxFF 2 BOTTOM 0x00 70 ATtiny1 3 D 2535E AVR 10 04 Timer Counter Control Register B TCCROB 2535E AVR 10 04 Bit 1 0 7 6 5 4 3 2 Ww R R R W Read Write W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 FOCOA Force Output Compare A The FOCOA bit is only active when the WGM bits specify a non PWM mode However for ensuring compatib
170. s 7 6 COM01A 0 Compare Match Output A Mode These bits control the Output Compare pin OCOA behavior If one or both of the COMOA1 0 bits are set the OCOA output overrides the normal port functionality of the I O pin it is connected to However note that the Data Direction Register DDR bit cor responding to the OCOA pin must be set in order to enable the output driver When OCOA is connected to the pin the function of the COMOA1 0 bits depends on the WGM02 0 bit setting Table 26 shows the COMOA1 0 bit functionality when the WGM02 0 bits are set to a normal or CTC mode non PWM Table 26 Compare Output Mode non PWM Mode COMO1 COMOO Description 0 0 Normal port operation OCOA disconnected 0 1 Toggle OCOA on Compare Match 1 0 Clear OCOA on Compare Match 1 1 Set OCOA on Compare Match Table 27 shows the COMOA1 0 bit functionality when the WGMO 1 O0 bits are set to fast PWM mode Table 27 Compare Output Mode Fast PWM Mode COMO1 COMOO Description 0 0 Normal port operation OCOA disconnected 0 1 WGM02 0 Normal Port Operation OCOA Disconnected WGM02 1 Toggle OCOA on Compare Match 1 0 Clear OCOA on Compare Match set OCOA at TOP 1 1 Set OCOA on Compare Match clear OCOA at TOP Note 1 A special case occurs when OCROA equals TOP and COMOA1 is set In this case the Compare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 63 for more d
171. s result ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to 86 reduce noise induced from the CPU core and other I O peripherals The noise canceler can be used with ADC Noise Reduction and Idle mode To make use of this feature the following procedure should be used 1 Make sure that the ADC is enabled and is not busy converting Single Con version mode must be selected and the ADC conversion complete interrupt must be enabled 2 Enter ADC Noise Reduction mode or Idle mode The ADC will start a con version once the CPU has been halted 3 If no other interrupts occur before the ADC conversion completes the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine If another interrupt wakes up the CPU before the ADC con version is complete that interrupt will be executed and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes The CPU will remain in active mode until a new sleep command is executed Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption 2535E AVR 10 04 Analog Input Circuitry 2535E AVR 10 04 The analog input circuitry for single ended channels is illustrated in Figure 47 An analog source
172. s set the Output Driver Enable is controlled Override Enable by the DDOV signal If this signal is cleared the Output driver is enabled by the DDxn Register bit DDOV Data Direction If DDOE is set the Output Driver is enabled disabled Override Value when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value If this signal is set and the Output Driver is enabled the Override Enable port value is controlled by the PVOV signal If PVOE is cleared and the Output Driver is enabled the port Value is controlled by the PORTxn Register bit PVOV Port Value If PVOE is set the port value is set to PVOV regardless Override Value of the setting of the PORTxn Register bit PTOE Port Toggle If PTOE is set the PORTxn Register bit is inverted Override Enable DIEOE Digital Input If this bit is set the Digital Input Enable is controlled by Enable Override the DIEOV signal If this signal is cleared the Digital Input Enable Enable is determined by MCU state Normal mode sleep mode DIEOV Digital Input If DIEOE is set the Digital Input is enabled disabled when Enable Override DIEOV is set cleared regardless of the MCU state Value Normal mode sleep mode DI Digital Input This is the Digital Input to alternate functions In the figure the signal is connected to the output of the schmitt trigger but before the synchronizer Unless the Digital Input is used as a clock source the module with the alternate f
173. set and the PCIE bit in GIMSK is set pin change interrupt is enabled on the corresponding I O pin If PCINT5 0 is cleared pin change interrupt on the corresponding I O pin is disabled 8 bit Timer CounterO Timer Countero is a general purpose 8 bit Timer Counter module with two independent with PWM Output Compare Units and with PWM support It allows accurate program execution timing event management and wave generation The main features are Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match Auto Reload Glitch Free Phase Correct Pulse Width Modulator PWM Variable PWM Period Frequency Generator Three Independent Interrupt Sources TOVO OCFOA and OCFOB Overview A simplified block diagram of the 8 bit Timer Counter is shown in Figure 26 For the actual placement of I O pins refer to Pinout ATtiny13 on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the 8 bit Timer Counter Register Description on page 68 Figure 26 8 bit Timer Counter Block Diagram TOVn Int Req Control Logic SO e Clock Select Edge TOP BOTTOM From Prescaler Timer Counter OCnA gt Waveform OCnA Generation OCnB Int Req Waveform OCnB Generation DATA BUS OCRnB TCCRnA TCCRnB Registers Th
174. sing power 11 Reserved When applying an external clock it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU A variation in frequency of more than 2 from one clock cycle to the next can lead to unpredictable behavior It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency Note that the System Clock Prescaler can be used to implement run time changes of the internal clock frequency while still ensuring stable operation Refer to System Clock Prescaler on page 25 for details 2535E AVR 10 04 128 kHz Internal Oscillator System Clock Prescaler Clock Prescale Register CLKPR 2535E AVR 10 04 The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz The frequency is nominal at 3V and 25 C This clock may be select as the system clock by programming the CKSEL Fuses to 11 When this clock source is selected start up times are determined by the SUT Fuses as shown in Table 8 Table 8 Start up Times for the 128 kHz Internal Oscillator Start up Time from Power Additional Delay from SUT1 0 down and Power save Reset Recommended Usage 00 6 CK 14CK BOD enabled 01 6 CK 14CK 4 ms Fast rising power 10 6 CK 14CK 64 ms Slowly rising power 11 Reserved The ATtiny13 system clock can be divided by setting the Clock Prescale Register CLKPR This featur
175. t ADIF is cleared by hardware when executing the corresponding interrupt handling vector Alternatively ADIF is cleared by writing a logical one to the flag Beware that if doing a Read Modify Write on ADCSRA a pending interrupt can be dis abled This also applies if the SBI and CBI instructions are used Bit 3 ADIE ADC Interrupt Enable When this bit is written to one and the I bit in SREG is set the ADC Conversion Com plete Interrupt is activated Bits 2 0 ADPS2 0 ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC Table 39 ADC Prescaler Selections ADPS2 ADPS1 ADPSO Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 The ADC Data Register ADCL and ADCH ADLAR 0 Bit 15 14 13 12 11 10 9 8 Aw apen aper 7 6 5 4 3 2 1 0 Read Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR 1 Bit 15 14 13 12 11 10 9 8 ADCS ADCH ADT Apo dL 7 6 5 4 3 2 1 0 Read Write R R R R R R R R R R R R R R R R 92 ATti ny1 3 SSS eee 2535E AVR 10 04 ADC Control and Status Register B ADCSRB Digital Input Disable Register 0 DIDRO 2535E AVR 10 04 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete the result is found in these two registers When ADCL is read the ADC
176. t No Tri state Hi Z 1 0 X Output No Output Low Sink 1 1 X Output No Output High Source Independent of the setting of Data Direction bit DDxn the port pin can be read through the PINxn Register bit As shown in Figure 21 the PINxn Register bit and the preceding latch constitute a synchronizer This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock but it also introduces a delay Figure 22 shows a timing diagram of the synchronization when reading an externally applied pin value The maximum and minimum propagation delays are denoted tog max and tog min respectively Figure 22 Synchronization when Reading an Externally Applied Pin value SYSTEM CLK Tdi ri Fi rA INSTRUCTIONS xx xx lt name gt SYNC LATCH i myr o So PINxn d 0 S r17 0x00 OxFF 2535E AVR 10 04 2535E AVR 10 04 Consider the clock period starting shortly after the first falling edge of the system clock The latch is closed when the clock is low and goes transparent when the clock is high as indicated by the shaded region of the SYNC LATCH signal The signal value is latched when the system clock goes low It is clocked into the PINxn Register at the suc ceeding positive clock edge As indicated by the two arrows tpd max and tpd min a single signal transition on the pin will be delayed between VG and 1 system clock period depending upon the time of assertion When reading back a
177. ternal memory access The internal data SRAM access is performed in two clkcpy cycles as described in Figure 10 Figure 10 On chip Data SRAM Access Cycles Ti T2 T3 Memory Access Instruction Next Instruction 2535E AVR 10 04 EEPROM Data Memory EEPROM Read Write Access EEPROM Address Register EEARL EEPROM Data Register EEDR 2535E AVR 10 04 The ATtiny13 contains 64 bytes of data EEPROM memory It is organized as a separate data space in which single bytes can be read and written The EEPROM has an endur ance of at least 100 000 write erase cycles The access between the EEPROM and the CPU is described in the following specifying the EEPROM Address Registers the EEPROM Data Register and the EEPROM Control Register For a detailed description of Serial data downloading to the EEPROM see page 106 The EEPROM Access Registers are accessible in the I O space The write access times for the EEPROM are given in Table 1 A self timing function however lets the user software detect when the next byte can be written If the user code contains instructions that write the EEPROM some precautions must be taken In heavily filtered power supplies Vcc is likely to rise or fall slowly on Power up down This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used See Preventing EEPROM Corruption on page 19 for details on how to avoid problems in these situat
178. tes 1 Program the Fuse bits before programming the LB1 and LB2 2 1 means unprogrammed 0 means programmed 2535E AVR 10 04 Fuse Bytes The ATtiny13 has two Fuse bytes Table 44 and Table 45 describe briefly the functional ity of all the fuses and how they are mapped into the Fuse bytes Note that the fuses are read as logical zero 0 if they are programmed Table 44 Fuse High Byte Fuse High Byte Bit No Description Default Value E 7 1 unprogrammed 6 1 unprogrammed 5 1 unprogrammed SELFPRGEN 4 Self Programming Enable 1 unprogrammed DWEN 3 debugWire Enable 1 unprogrammed BODLEVEL10 2 Brown out Detector trigger level 1 unprogrammed BODLEVELO 1 Brown out Detector trigger level 1 unprogrammed RSTDISBL 0 External Reset disable 1 unprogrammed Notes 1 See Table 13 on page 33 for BODLEVEL Fuse decoding 2 See Alternate Functions of Port B on page 50 for description of RSTDISBL and DWEN Fuses 3 DWEN must be unprogrammed when Lock Bit security is required See Program And Data Memory Lock Bits on page 102 4 When programming the RSTDISBL Fuse High voltage Serial programming has to be used to change fuses to perform further programming Table 45 Fuse Low Byte Fuse Low Byte Bit No Description Default Value SPIEN 7 Enable Serial Program 0 programmed SPI prog and Data Downloading enabled EEPROM memory is 1
179. the ATtiny13 in the Serial Programming mode the following sequence is recommended see four byte instruction formats in Table 50 1 Power up sequence Apply power between Vcc and GND while RESET and SCK are set to 0 In some systems the programmer can not guarantee that SCK is held low during power up In this case RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to 0 2 Wait for at least 20 ms and enable serial programming by sending the Program ming Enable serial instruction to pin MOSI 3 The serial programming instructions will not work if the communication is out of synchronization When in sync the second byte 0x53 will echo back when issuing the third byte of the Programming Enable instruction Whether the echo is correct or not all four bytes of the instruction must be transmitted If the 0x53 did not echo back give RESET a positive pulse and issue a new Programming Enable command 4 The Flash is programmed one page at a time The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program memory Page instruction To ensure correct loading of the page the data low byte must be loaded before data high byte is applied for a given address The Program memory Page is stored by loading the Write Program memory Page instruction with the 5 MSB of the address If polling RDY BSY is not used the user m
180. the following figures The figures include information on when Interrupt Flags are set Figure 33 contains timing data for basic Timer Counter operation The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode Figure 33 Timer Counter Timing Diagram no Prescaling Oe clkr i clko i TONTn BOTTOM BOTTOM 1 TOVn Figure 34 shows the same timing data but with the prescaler enabled 2535E AVR 10 04 2535E AVR 10 04 Figure 34 Timer Counter Timing Diagram with Prescaler f i 1 0 8 MUI BOTTOM BOTTOM 1 Figure 35 shows the setting of OCFOB in all modes and OCFOA in all modes except CTC mode and PWM mode where OCROA is TOP Figure 35 Timer Counter Timing Diagram Setting of OCFOx with Prescaler fok 0 8 UT GN IL fL fL fL TCNTn OCRnx 1 OCRnx OCRnx 1 OCRnx 2 OCRnx OCRnx Value f OCFnx i i i i i i i Figure 36 shows the setting of OCFOA and the clearing of TCNTO in CTC mode and fast PWM mode where OCROA is TOP Figure 36 Timer Counter Timing Diagram Clear Timer on Compare Match mode with Prescaler f i 0 8 so MINIM AMEL e 8 bit Timer Counter Register Description Timer Counter Control AMEL Register A TCCROA Bit E 5 3 2 1 0 E EA A Read Write RW RW RW RW R R RW RW Initial Value 0 0 0 0 0 0 0 e Bit
181. tion is in progress it is nei ther possible to read the EEPROM nor to change the EEARL Register Using Atomic Byte Programming is the simplest mode When writing a byte to the EEPROM the user must write the address into the EEARL Register and data into EEDR Register If the EEPMn bits are zero writing EEPE within four cycles after EEMPE is written will trigger the erase write operation Both the erase and write cycle are done in one operation and the total programming time is given in Table 1 The EEPE bit remains set until the erase and write operations are completed While the device is busy with programming it is not possible to do any other EEPROM operations It is possible to split the erase and write cycle in two different operations This may be useful if the system requires short access time for some limited period of time typically if the power supply voltage falls In order to take advantage of this method it is required that the locations to be written have been erased before the write operation But since the erase and write operations are split it is possible to do the erase operations when the system allows doing time critical operations typically after Power up To erase a byte the address must be written to EEARL If the EEPMn bits are 0b01 writing the EEPE within four cycles after EEMPE is written will trigger the erase opera tion only programming time is given in Table 1 The EEPE bit remains set until the erase o
182. tracks run over the analog ground plane and keep them well away from high speed switching digital tracks 2 Use the ADC noise canceler function to reduce induced noise from the CPU 3 If any port pins are used as digital outputs it is essential that these do not switch while a conversion is in progress ADC Accuracy Definitions An n bit single ended ADC converts a voltage linearly between GND and Voer in 2 steps LSBs The lowest code is read as 0 and the highest code is read as 2 1 Several parameters describe the deviation from the ideal behavior e Offset The deviation of the first transition 0x000 to 0x001 compared to the ideal transition at 0 5 LSB Ideal value 0 LSB Figure 48 Offset Error Output Code Ideal ADC Actual ADC ffset Erro Voer Input Voltage e Gain Error After adjusting for offset the Gain Error is found as the deviation of the last transition 0x3FE to Ox3FF compared to the ideal transition at 1 5 LSB below maximum Ideal value 0 LSB Figure 49 Gain Error Ideal ADC Actual ADC Voer Input Voltage e Integral Non linearity INL After adjusting for offset and gain error the INL is the maximum deviation of an actual transition compared to an ideal transition for any code Ideal value 0 LSB Figure 50 Integral Non linearity INL Output Code Ideal ADC Actual ADC Veer dnput Voltage e Differential Non linearity DNL The maximum deviation of the actu
183. truction placed at the Reset Vector must be a RJMP Relative Jump instruction to the reset handling routine If the program never enables an interrupt source the Interrupt Vectors are not used and regular program code can be placed at these locations The circuit diagram in Figure 13 shows the reset logic Table 12 defines the electrical parameters of the reset circuitry The I O ports of the AVR are immediately reset to their initial state when a reset source goes active This does not require any clock source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out period of the delay counter is defined by the user through the SUT and CKSEL Fuses The different selections for the delay period are presented in Clock Sources on page 22 The ATtiny13 has four sources of reset e Power on Reset The MCU is reset when the supply voltage is below the Power on Reset threshold Vpor e External Reset The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length e Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled e Brown out Reset The MCU is reset when the supply voltage Vo is below the Brown out Reset threshold Vgor and the Brown out Detector is enabled 2535E AVR 10 04 ATtiny13 Figure
184. uest 1 1 The rising edge of INTO generates an interrupt request 2535E AVR 10 04 General Interrupt Mask Register GIMSK BH i 2 2 4 B 2 9 move T LL ev Read Write R R W R W R R R R R Initial Value 0 0 0 0 0 0 0 e Bits 7 4 0 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bit 6 INTO External Interrupt Request 0 Enable When the INTO bit is set one and the I bit in the Status Register SREG is set one the external pin interrupt is enabled The Interrupt Sense ControlO bits 1 0 ISCO1 and ISC00 in the MCU Control Register MCUCR define whether the external interrupt is activated on rising and or falling edge of the INTO pin or level sensed Activity on the pin will cause an interrupt request even if INTO is configured as an output The correspond ing interrupt of External Interrupt Request 0 is executed from the INTO Interrupt Vector e Bit 5 PCIE Pin Change Interrupt Enable When the PCIE bit is set one and the I bit in the Status Register SREG is set one pin change interrupt is enabled Any change on any enabled PCINT5 0 pin will cause an interrupt The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector PCINT5 0 pins are enabled individually by the PCMSKO Register General Interrupt Flag Register GIFR n 2 S i 2 2 9 Wm ror NNN am Read Write R R W R W R R R R R Initial Value 0 0
185. unction will use its own synchronizer AIO Analog This is the Analog Input Output to from alternate Input Output functions The signal is connected directly to the pad and can be used bi directionally The following subsections shortly describe the alternate functions for each port and relate the overriding signals to the alternate function Refer to the alternate function description for further details 2535E AVR 10 04 AMEL 49 AMEL MCU Control Register MCUCR Bit 7 6 5 4 3 2 1 0 SE smi smo ISCO1 Iscoo MCUCR Read Write R R W R W R W R W R R W R W Initial Value 0 0 0 0 0 0 0 0 Bits 7 2 Res Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero Bit 6 PUD Pull up Disable When this bit is written to one the pull ups in the I O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull ups DDxn PORTxn 0b01 See Configuring the Pin on page 43 for more details about this feature Alternate Functions of Port B The Port B pins with alternate function are shown in Table 21 50 Table 21 Port B Pins Alternate Functions Port Pin Alternate Function PB5 RESET dW ADCO PCINT5 PB4 ADC2 PCINT4 PB3 ADC3 CLKI PCINT3 PB2 SCK ADC1 TO PCINT2 PB1 MISO AIN1 OCOB INTO PCINT1 RXD PBO MOSI AINO OCOA PCINTO TXD 9 Notes 1 Reset pin debugWire I O ADC Input channel or Pin Cha
186. unter Timing Diagrams AMEL and TCNTO when the counter decrements The PWM frequency for the output when using phase correct PWM can be calculated by the following equation focnxPCPWM N 510 The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCROA Register represent special cases when generating a PWM waveform output in the phase correct PWM mode If the OCROA is set equal to BOTTOM the output will be continuously low and if set equal to MAX the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values At the very start of period 2 in Figure 32 OCn has a transition from high to low even though there is no Compare Match The point of this transition is to guarantee symmetry around BOTTOM There are two cases that give a transition without Compare Match e OCROA changes its value from MAX like in Figure 32 When the OCROA value is MAX the OCn pin value is the same as the result of a down counting Compare Match To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up counting Compare Match e The timer starts counting from a value higher than the one in OCROA and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up The Timer Counter is a synchronous design and the timer clock clky9 is therefore shown as a clock enable signal in
187. use the Internal Voltage Reference as input the Analog Comparator should be disabled in all sleep modes Otherwise the Internal Voltage Ref erence will be enabled independent of sleep mode Refer to Analog Comparator on page 76 for details on how to configure the Analog Comparator If the Brown out Detector is not needed in the application this module should be turned off If the Brown out Detector is enabled by the BODLEVEL Fuses it will be enabled in all sleep modes and hence always consume power In the deeper sleep modes this will contribute significantly to the total current consumption Refer to Brown out Detec tion on page 33 for details on how to configure the Brown out Detector The Internal Voltage Reference will be enabled when needed by the Brown out Detec tion the Analog Comparator or the ADC If these modules are disabled as described in the sections above the internal voltage reference will be disabled and it will not be con suming power When turned on again the user must allow the reference to start up before the output is used If the reference is kept on in sleep mode the output can be used immediately Refer to Internal Voltage Reference on page 35 for details on the start up time If the Watchdog Timer is not needed in the application this module should be turned off If the Watchdog Timer is enabled it will be enabled in all sleep modes and hence always consume power In the deeper sleep modes this will
188. ust wait at least twp o as before issuing the next page See Table 49 Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming 5 A The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction An EEPROM memory location is first automatically erased before new data is written If polling RDY BSY is not used the user must wait at least twp eeprom before issuing the next byte See Table 49 In a chip erased device no OxFFs in the data file s need to be programmed B The EEPROM array is programmed one page at a time The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction The EEPROM Mem ory Page is stored by loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address When using EEPROM page access only byte loca tions loaded with the Load EEPROM Memory Page instruction is altered The remaining locations remain unchanged If polling RDY BSY is not used the used must wait at least tip cepRom before issuing the next page See Table 47 In a chip erased device no OxFF in the data file s need to be programmed 6 Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO 7 Atthe end of the programming session RESET
189. ut Voltage Vec 5V g cc I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 5V 160 140 85 C 25 C 120 40 C 100 T 80 Es 60 40 20 0 0 1 2 3 4 5 6 Vor V 130 2535E AVR 10 04 Figure 79 I O Pin Pull up Resistor Current vs Input Voltage Voc 2 7V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Voc 2 7 lop uA Figure 80 Reset Pull up Resistor Current vs Reset Pin Voltage Vcc 5V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 5V 120 40 CL_ 25 C 100 85 C 80 T 3 t 60 Ra 40 20 04 0 1 2 8 4 5 VRESET v TEL x T 2535E AVR 10 04 Pin Driver Strength 132 AMEL Figure 81 Reset Pull up Resistor Current vs Reset Pin Voltage Voc 2 7V 30 Ingser uA 20 70 60 lon mA RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Voc 2 7V 0 5 1 I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE LOW POWER PORTS Vcc 5V 1 5 VnesET V Figure 82 UO Pin Source Current vs Output Voltage Low Power Ports Voc 5V 40 C 25 C 85 C Von V 2535E AVR 10 04 Figure 83 UO Pin Source Current vs Output Voltage Low Power Ports Voc 2 7V UO PIN SOURCE CURRENT vs OUTPUT VOLTAGE LOW POWER PORTS Vcc 2 7V 25 40 C 20 25 C 85 C
190. ut erasing the temporary buffer If the EEPROM is written in the middle of an SPM Page Load operation all data loaded will be lost To execute Page Write set up the address in the Z pointer write 00000101 to SPMCSR and execute SPM within four clock cycles after writing SPMCSR The data in R1 and RO is ignored The page address must be written to PCPAGE Other bits in the Z pointer must be written to zero during this operation e The CPU is halted during the Page Write operation ATMEL s AMEL Addressing the Flash The Z pointer is used to address the SPM commands During Self Bi 15 14 13 12 11 10 9 8 Programming ze zie ma m ER TESTES my gt ze a sa sj 2 am 7 6 5 4 3 2 1 0 98 Since the Flash is organized in pages see Table 46 on page 105 the Program Counter can be treated as having two different sections One section consisting of the least sig nificant bits is addressing the words within a page while the most significant bits are addressing the pages This is shown in Figure 53 Note that the Page Erase and Page Write operations are addressed independently Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation The LPM instruction uses the Z pointer to store the address Since this instruction addresses the Flash byte by byte also the LSB bit ZO of the Z pointer is used Figure 53 Addressing the Flash During SPM BIT 1
191. view The debugWIRE On chip debug system uses a One wire bi directional interface to con trol the program flow execute AVR instructions in the CPU and to program the different non volatile memories Physical Interface When the debugWIRE Enable DWEN Fuse is programmed and Lock bits are unpro grammed the debugWIRE system within the target device is activated The RESET port pin is configured as a wire AND open drain bi directional I O pin with pull up enabled and becomes the communication gateway between target and emulator Figure 52 The debugWIRE Setup 1 8 5 5V Q dw Figure 52 shows the schematic of a target MCU with debugWIRE enabled and the emulator connector The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses When designing a system where debugWIRE will be used the following observations must be made for correct operation e Pull Up resistor on the dW RESET line must be in the range of 10k to 20 kQ However the pull up resistor is optional e Connecting the RESET pin directly to Veg will not work ATMEL 2535E AVR 10 04 Software Break Points Limitations of debugWIRE debugWIRE Related Register in UO Memory debugWire Data Register DWDR AMEL e Capacitors inserted on the RESET pin must be disconnected when using debugWire e All external reset sources must be disconnected debugWIRE supports Program memory Break Points
192. ws one page of program data to be programmed simultaneously The following procedure describes how to pro gram the entire Flash memory 1 Load Command Write Flash see Table 55 2 Load Flash Page Buffer 3 Load Flash High Address and Program Page Wait after Instr 3 until SDO goes high for the Page Programming cycle to finish 4 Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed 5 End Page Programming by Loading Command No Operation When writing or reading serial data to the ATtiny13 data is clocked on the rising edge of the serial clock see Figure 59 Figure 60 and Table 56 for details Figure 58 Addressing the Flash which is Organized in Pages PCMSB PAGEMSB Er PCPAGE PCWORD PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD PAGEMSB 0 RAGE _ jo INSTRUCTION WORD 00 E 01 S 02 A P gt i Y 1 y L Po q eg Li RE 1 R PAGEEND Figure 59 High voltage Serial Programming Waveforms E MBX X X XX LE pus MBX XM XX XX X LBN SCI PB3 114 ATti ny1 3 El 2535E AVR 10 04 Programming the EEPROM Reading the Flash Reading the EEPROM Programming and Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Power off sequence 2535E AVR 10 04 The EEPROM is organized in pages see Table 51 on page 110 When

ATMEL ATtiny13 Data Sheet

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