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MAXIM 71M6541D/F/G 71M6542F/G Energy Meter ICs Manual

1. Pi Pi Lua F 6 dom a cf Name Type Circuit Function E LCD Common Outputs These four pins provide the select dd icto EUMD as S S signals for the LCD display 31 45 SEGDIOOMWPULSE 30 44 SEGDIO1 VPULSE 29 43 SEGDIO2 SDCK 28 42 SEGDIO3 SDATA 27 41 SEGDIO4 26 39 SEGDIOS Multiple Use Pins Configurable as either LCD segment 25 38 SEGDIOG XPULSE driver or DIO Alternative functions with proper selection of associated I O RAM registers are 24 37 SEGDIO7 YPULSE SEGDIOO WPULSE SEGDIO1 VPULSE 23 36 PEQDIDNIDI SEGDIO2 SDCK 22 17 35 30 SEGDIO 9 14 UO 3 4 5 SEGDIO3 SDATA SEGDIO6 XPULSE e 25 SEGDIO 18 SEGDIO8 DI 16 10 24 18 SEGDIO 19 25 Unused pins must be configured as outputs or T 114 SEGDIO 28 35 terminated to V3P3 GNDD 63 62 95 94 SEGDIO 44 45 99 96 SEGDIO 40 43 52 SEGDIO52 51 SEGDIO53 47 SEGDIO54 9 17 SEGDIO26 COM5 Multiple Use Pins Configurable as either LCD segment V O 3 4 5 driver or DIO with alternative function LCD common 8 16 SEGDIO27 COM4 drivers 3 SPI_CSZ SEGDIO36 2 SPI DO SEGDIO37 o 3 4 5 Multiple Use Pins Configurable as either LCD segment 1 SPI DI SEGDIO38 driver or DIO with alternative function SPI interface 64 100 SPI CKI SEGDIO39 33 53 OPT TX SEGDIO51 o 3 4 5 Multiple Use Pins configurable as either LCD segment 32 46 OPT RX SEGDIO55 driver or DIO with alternative function optical port UART1 38 58 E_RX
2. UO RAM I O RAM 71M6541D F G cc dn Mnemonic Location hex Eg 0 ori Eg 2 FIR LEN 1 0 210C 2 1 1 1 2 ADC_DIV 2200 5 1 1 0 PLL FAST 2200 4 1 1 1 MUX_DIV 3 0 2100 7 4 3 3 4 MUX0_SEL 3 0 2105 3 0 0 0 0 MUX1_SEL 3 0 2105 7 4 A A A MUX2_SEL 3 0 2104 3 0 2 2 2 MUX3 SEL 3 0 2104 7 4 1 1 9 RMT E 2709 3 0 0 0 DIFFA E 210C 4 1 1 1 DIFFB_E 210C 5 1 1 1 EQU 2 0 2106 7 5 Oor1 Oor1 2 CE Code CE41A01 CE41A01 CE41A04 Equations Oor1 Oor1 2 cd 1 Shunt and 1 CT 1 Shunt and 1 CT 1 Shunt and 1 CT Current Sensor Types or or or 2 CTs 2 CTs 2 CTs Applicable Figure Figure 2 Figure 4 Figure 4 Notes Teridian updates the CE code periodically Please contact your local Teridian representative to obtain the latest CE code and the associated settings The configuration presented in this table is set by the MPU demonstration code during initialization Rev 2 15 71M6541D F G and 71M6542F G Data Sheet Table 2 Required CE Code and Settings for 71M6x01 isolated Sensor I O RAM IJO RAM 71M6541D F G 71M6542F G Mnemonic Location hex hex FIR LEN 1 0 210C 2 1 1 1 ADC_DIV 2200 5 1 1 PLL_FAST 2200 4 1 1 MUX DIV 3 0 2100 7 4 3 3 MUXO SEL 3 0 2105 3 0 0 0 MUX1_SEL 3 0 2105 7 4 A A MUX2_SEL 3 0 2104 3 0 1 9 MUX3_SEL 3 0 2104 7 4 1 1 RMT E 2709 3 1 1 DIFFA E 210C 4 1 1 DIFFB_E 2
3. Rev 2 69 71M6541D F G and 71M6542F G Data Sheet LCD Drivers 71M6542F G With a maximum of 56 LCD driver pins available the 71M6542D F is capable of driving up to 6 x 56 336 pixels of an LCD display when using the 6 x multiplex mode At eight pixels per digit this corresponds to 42 digits LCD segment data is written to the LCD SEGn 5 0 I O RAM registers as described in 2 5 8 3 Digital UO for the SEGA6 through SEG50 cannot be configured as DIO pins Display data for these pins are written to I O RAM fields LCD SEG46 5 0 I O RAM 0x243E 5 0 through LCD SEG50 5 0 I O RAM 0x2442 5 0 see Table 59 The associated pins function as ICE interface pins and the ICE functionality overrides the LCD function whenever ICE E is pulled high Table 59 71M6542F G LCD Data Registers for SEG46 to SEG50 SEG 46 47 48 49 50 Pin 93 92 58 57 56 Always LCD pins except Configuration when used for ICE interface or TMUXOUT TMUX2OUT Go GIGS se a N eo D Q St E E Yt uU E LE LEES SEG Data Register T T S 5 B m E m m m A WW Si A A 8 3 38 8 8 2 5 9 EEPROM Interface The 71M6541D F G provides hardware support for either a two pin or a three wire p wire type of EEPROM interface The interfaces use the SFR EECTRL SFR 0x9F and EEDATA SFR Ox9E registers for communication 2 5 9 1 Two pin EEPROM Interface The dedicated 2 pin
4. Direction Register 0 SEGDIO 19 20 21 22 23 24 25 26 27 Pin 4 36 1 14 13 12 31 10 9 8 Configuration Si 3 4 5 6 7 0 1 2 3 0 DIO 1 LCD LCD MAP 23 19 I O RAM 0x2409 LCD MAP 27 24 I O RAM 0x2408 T19 20 IER CAE NEKTAR E PER ESSE SEG Data Register LCD_SEGDIO19 5 0 to LCD SEGDIO27 5 0 VO RAM 0x2423 5 0 to 0x242C 5 0 T19 20 21 22 es oa esq EE EE DIO Data Register LCD_SEGDIO19 0 to LCD SEGDIO27 0 VO RAM 0x2423 0 to Ox242C 0 T19 20 21 x x 24 2528 27 1 9 ec input 1 output LCD_SEGDIO19 1 to LCD SEGDIO27 1 VO RAM 0x2423 1 to 0x242C 1 Table 50 Data Direction Registers for SEGDIO36 39 to SEGDIO44 45 71M6541D F G SEGDIO E 36 37 38 39 44 45 Pin 3 2 64 63 62 x 4 5 7 4 5 Configuration 0 DIO 1 LcCD LCD MAP 39 36 LCD MAP 45 44 VO RAM 0x2407 OO RAM 0x2406 36 37 38 39 44 45 SEG Data Register LCD_SEGDIO36 5 0 to LCD_SEGDIO45 5 0 VO RAM 0x2434 2437 5 0 to 0x243C 243D 5 0 36 37 38 39 44 45 DIO Data Register LCD_SEGDIO32 0 to LCD_SEGDIO45 0 VO RAM 0x2434 2437 0 to 0x243C 243D 0
5. CE ae Address Name Default Description 0x25 QUANT VA 0 0x26 QUANT IA 0 Compensation factors for truncation and noise in voltage current 0x27 QUANT_A 0 real energy and reactive energy for phase A 0x28 QUANT VARA 0 0x29 QUANT VB 0 e i e OX2A QUANT IB 0 ompensation factors for truncation and noise in voltage current WANT E real energy and reactive energy for phase B vee QUANT 9 t 71M6542 only 0x2C QUANT_VARB 0 0x38 0x43453431 f T 0x39 0x6130316B CE file name identifier in ASCII format CE41a01f These values are overwritten as soon as the CE starts Ox3A 0x00000000 LSB weights for use with Local Sensors QUANT Ix LSB 5 08656 10 IMAX Amps QUANT _Wx LSB 1 04173 10 VMAX IMAX Watts QUANT _VARx _ LSB 1 04173 10 VMAX IMAX Vars LSB weights for use with the 71M6x01 isolated sensors QUANT _ Ix_ LSB 1 38392 10 17 IMAX Amps QUANT Wa LSB 1 71829 10 VMAX IMAX Watts QUANT VARx _ LSB 1 71829 10 VMAX IMAX Vars 134 Rev 2 71M6541D F G and 71M6542F G Data Sheet 5 3 11 CE Calibration Parameters Table 92 lists the parameters that are typically entered to effect calibration of meter accuracy Table 92 CE Calibration Parameters CE c Address Name Default Description 0x10 CAL_IA 16384 These constants control the gain of their respective channels The e B 14 _ M Ox11 CAL VA 16384 nominal value for
6. tus changed byte received DE detected zero XPULSE crossing YPULSE CE detected sa 2 WPULSE Wh pulse VPULSE VARh pulse DIO status 1 DIO changed 3 CE BUSY 4 VSTAT Supply s EEPROM BUSY fell s command SPI received accumulation ARER IESUS ycle complete RTC 1S every second 6 RTC T alarm clock byte transmitted RTC 1M every minute Flag 1 means that an interrupt has occurred and has not been cleared EX0 EX6 are cleared automaticallywhen the hardware vectors to the interrupt handler Priority Assignment Polling Sequence Internal Source refers to interrupt sources originating within the 80515 MPU core External Source refers to interrupt sources outside the 80515 MPU core originating from other parts of the 71M654x SoC Figure 16 Interrupt Structure Interrupt Vector 3 19 2010 Rev 2 47 71M6541D F G and 71M6542F G Data Sheet 2 5 On Chip Resources 2 5 1 Physical Memory 2 5 1 1 Flash Memory The device includes 128KB 71M6541G 71M6542G 64KB 71M6542F 71M6541F or 32KB 71M6541D of on chip flash memory The flash memory primarily contains MPU and CE program code It also contains images of the CE RAM and I O RAM On power up before enabling the CE the MPU copies these images to their respective locations Flash space allocate
7. SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin 4 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29 Configuration 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 1 7 0 DIO 1 LCD LCD MAPY 7 0 O RAM 0x240B LCD MAP 15 8 I O RAM 0x240A 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 LCD_SEGO 5 0 to LCD_SEG15 5 0 I O RAM 0x2410 5 0 to 0x241F 5 0 0 12 3 0 1 2 3 0 1 2 3 0 1 24 3 SEG Data Register DIO Data Register PO SFR 0x80 P1 SFR 0x90 P2 SFR 0xA0 P3 SFR 0xBO Direction Register 4 5 67 4 5 6 7 4 5 6 7 4 5 6 7 0 input 1 output PO SFR 0x80 P1 SFR 0x0 P2 SFR 0xA0 P3 SFR 0xBO Internal Resources Configurable Y Y Y YvY vY Y vY vYv see Table 47 Rev 2 63 71M6541D F G and 71M6542F G Data Sheet Table 53 Data Direction Registers for SEGDIO16 to SEGDIO31 71M6542F G SEGDIO 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pin 28 27 25 24 23 22 21 20 19 18 17 16 11 10 9 Configuration 0 1 2 33 4 5 6 7 0 1 2 3 4 567 0 DIO 1 LCD LCD_MAP 23 16
8. 71M6541D F G and 71M6542F G Data Sheet Table 89 Other Transfer Variables CE Su Address Name Description Fundamental frequency LSB A 0 509 10 Hz for Local 0x82 FREQ X nen LSB DL 0 58710 Hz for Remote 2 The number of edge crossings of the selected voltage in the previous 0x83 MAINEDGE X accumulation interval Edge crossings are either direction and are de bounced 5 3 9 Pulse Generation Table 90 describes the CE pulse generation parameters The combination of the CECONFIG PULSE_SLOW and PULSE FAST bits CE RAM 0x20 0 1 controls the speed of the pulse rate The default values of O and O maintain the original pulse rate given by the Kh equation WRATE CE RAM 0x21 controls the number of pulses that are generated per measured Wh and VARh quantities The lower WRATE is the slower the pulse rate for the measured energy quantity The metering constant Kh is derived from WRATE as the amount of energy measured for each pulse That is if Kh 1Wh pulse a power applied to the meter of 120 V and 30 A results in one pulse per second If the load is 240 V at 150 A ten pulses per second are generated Control is transferred to the MPU for pulse generation if EXT PULSE 1 CE RAM 0x20 5 In this case the pulse rate is determined by APULSEW and APULSER CE RAM 0x45 and 0x49 The MPU has to load the source for pulse generation in APULSEW and APULSER to generate pulses Irrespective of the
9. OPT_TXMOD 1 OPT_TXMOD 0 OPT_FDC 2 25 a D C RN m cua cR dE 1 38kHz Figure 18 Optical Interface Bit Banged Optical UART Third UART As shown in Figure 19 the 71M654x can also be configured to drive the optical UART with a DIO signal in a bit banged configuration When control bit OPT_BB I O RAM 0x2022 0 is set the optical port is driven by DIO5 and the SEGDIOS5 pin is driven by UART1 TX This configuration is typically used when the two dedicated UARTs must be connected to high speed clients and a slower optical UART is permissible 58 Rev 2 71M6541D F G and 71M6542F G Data Sheet Internal DIQ55 SEG55 d i o o SEGDIO55 UART1 RX lt oer RX OPT RXDIS SEG51 LCD MAP 55 vapa VARPULSE 3 1 SEGDIO51 y WPULSE 2 ES OPT TX A Uapr TX 4 O T wei o 7 A FAW yna B e LCD MAP 51 BET a len am OPT TXMOD OPT TXE 1 0 OPT FDC z 1 SEGS OPT TXINV 2 N i 2 A SEGDIOS TX2 m LCD MAP 5 OPT BB OPT_TXMOD 1 OPT_TXMOD 0 OPT_FDC 2 25 AT B 1 38kHz Figure 19 Optical Interface UART1 2 5 8 Digital I O and LCD Segment Drivers 2 5 8 1 General Information The 71M6541D F G and 71M6542F G combine most DIO pins with LCD segment drivers Each SEG DIO pin can be configured as a DIO pin or as a segment SEG driver pin On reset or power up all
10. Table 6 shows the allowable combinations of values in RCMD 4 2 and TMUXRn 2 0 and the corresponding data type and format sent back by the 71M6x01 isolated sensor and how the data is stored in RMT RD 15 8 and RMT RD 7 0 The MPU selects which of the three phases is read by asserting the proper code in the RCMD 1 0 field as shown in Table 5 Table 6 Remote Interface Read Commands RCMD 4 2 TMUXRn 2 0 Read Operation RMT_RD 15 8 RMT RD 7 0 001 00X TRIMT 7 0 TRIMT 7 RMT RD 8 TRIMT 6 0 RMT RD 7 1 trim fuse for all 71M6x01 010 00X STEMP 10 0 STEMP 10 8 RMT RD 10 8 STEMP 7 0 sensed 71M6x01 temperature RMT RD 15 11 are sign extended 010 01X VSENSE 7 0 All zeros VSENSE 7 0 sensed 71M6x01 supply voltage 010 10X VERSION 7 0 VERSION 7 0 All zeros chip version Notes 1 TRIMT 7 0 is the VREF trim value for all 71M6x01 devices Note that the TRIMT 7 0 8 bit value is formed by RMT RD 8 and RMT RD 7 1 See the 71M6xxx Data sheet for more information on TRIMT 7 0 2 See the 71M6xxx Data Sheet for the equation to calculate temperature from the STEMP 7 0 value read from the 71M6x01 3 See the 71M6xxx Data Sheet for the equation to calculate temperature from the VSENSE 7 0 value read from the 71M6x01 With hardware and trim related information on each connected 71M6x01 Isolated Sensor available to the 71M6541D F G the MPU can implement temperature compensation of the
11. Rev 2 155 71M6541D F G and 71M6542F G Data Sheet 6 8 Pinout Diagrams 6 8 1 71M6541D F G LQFP 64 Package Pinout SPI DI SEGDIO38 SPI DO SEGDIO37 SPI CSZ SEGDIO36 COM3 SEGDIO27 COM4 SEGDIO26 COM5 SEGDIO25 SEGDIO24 SEGDIO23 SEGDIO22 SEGDIO21 SEGDIO20 SEGDIO19 1 2 3 4 5 6 7 8 9 SPI_CKI SEGDIO39 SEGDIO44 TMUX2O0UT SEG46 SEGDIO45 TMUXOUT SEG47 XOUT XIN VBAT_RTC VBAT V3P3SYS IBP IBN GNDD V3P3D VDD ICE_E E RXTX SEG48 E TCLK SEG49 E RST SEG50 RX TX OPT TX SEGDIO51 Teridian 71M6541D 71M6541F SEGDIO9 SEGDIO8 DI SEGDIO7 YPULSE SEGDIO5 SEGDIO4 SEGDIO3 SDATA SEGDIO2 SDCK SEGDIO1 VPULSE SEGDIOO WPULSE OPT_RX SEGDIO55 SEGDIO6 XPULSE Figure 50 Pinout for the 71M6541D FIG LQFP 64 Package 156 Rev 2 71M6541D F G and 71M6542F G Data Sheet 6 8 2 71M6542F G LQFP 100 Package Pinout O LO dt Q UI ta S qu QOo o00351 05r SZXXAY3413952 oQooooOgoL lt 585885338 ep 8 Eu a az ougsullggRRSESEOSOSIUSZ222Q0 nnum a SPI DI SEGDIO38 m 1 O 75mm XIN SPI DO SEGDIO37 Wii 74mm NC SPI CSZ SEGDIO36 mm 3 73 NC SEGDIO35 mm 4 72 Em GNDA SEGDIO34 ear 710m VBAT_RTC SEGDIO33 am 6 70mm VBAT SEGDIO32 um 7 69mm V3P3SYS SEGDIO31 am 8 68 IBP SEGDIO30 am 9 67 NB IBN SEGDIO29 mi 10 66 NC SEGDIO28 gum 11 H H 65 NC COMO m 12 Terid ian 64 um NC COM1 mm 13 63 NC COM2mm 14 62 mg GNDD COMS3 mm 15 71M6542F 61mm V3P3D SEGDIO27 COM4 mm 16 comm V
12. 41 61 V3P3D 13 Auxiliary voltage output of the chip In mission mode this pin is connected to V3P3SYS by the internal selection switch In BRN mode it is internally connected to VBAT V3P3D is floating in LCD and sleep mode A 0 1 uF bypass capacitor to ground must be connected to this pin 40 60 VDD The output of the 2 5V regulator This pin is powered in MSN and BRN modes A 0 1 pF bypass capacitor to ground should be connected to this pin 57 89 VLCD The output of the LCD DAC A 0 1 UF bypass capacitor to ground should be connected to this pin 46 70 VBAT 12 Battery backup pin to support the battery modes BRN LCD A battery or super capacitor is to be connected between VBAT and GNDD If no battery is used connect VBAT to V3P3SYS 47 71 VBAT RTC 12 RTC and oscillator power supply A battery or super capacitor is to be connected between VBAT and GNDD If no battery is used connect VBAT RTC to V3P3SYS 158 Rev 2 71M6541D F G and 71M6542F G Data Sheet 6 9 2 Analog Pins Table 120 Analog Pins Pin Pin Name Type Circuit Description 64 pin 100 pin Differential or single ended Line Current Sense Inputs These pins are voltage inputs to the internal A D 55 87 IAP converter Typically they are connected to the outputs of current sensors Unused pins must be tied to 54 86 IAN i 6 V3P3A l nt l
13. 1 Timer O interrupt External interrupt 2 2 External interrupt 1 External interrupt 3 3 Timer 1 interrupt External interrupt 4 4 Serial channel O interrupt External interrupt 5 5 External interrupt 6 Each group of interrupt sources can be programmed individually to one of four priority levels as shown in Table 35 by setting or clearing one bit in the SFR interrupt priority register IPO SFR 0xA9 and one in IP1 SFR 0xB9 Table 36 If requests of the same priority level are received simultaneously an internal polling sequence as shown in Table 37 determines which request is serviced first d Table 35 Interrupt Priority Levels IP1 x IPO x Priority Level 0 Level 0 lowest 0 Level 1 1 Level 2 1 Level 3 highest Table 36 Interrupt Priority Registers IPO and IP1 Changing interrupt priorities while interrupts are enabled can easily cause software defects It is best to set the interrupt priority registers only once during initialization before interrupts are enabled Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB LSB IPO SFR 0xA9 IPO 5 IPO 4 IPO 3 IPO 2 IPO 1 IPO O IP1 SFR OxB9 IP1 5 IP1 4 IP1 3 IP1 2 IP1 1 IP1 0 Rev 2 45 71M6541D F G and 71M6542F G Data Sheet Table 37 Interrupt Polling Sequence External interrupt O Serial
14. OSC COMP 0 0 R W STEMP 10 3 2881 7 0 STEMP 2 0 2882 7 5 LKPAUTOI 2887 O 0 RW Rev 2 53 71M6541D F G and 71M6542F G Data Sheet Referring to Figure 17 the table lookup method uses the 10 bits plus sign bit value in STEMP 10 0 right shifted by two bits to obtain an 8 bit plus sign value i e NV RAM Address STEMP 4 A limiter ensures that the resulting look up address is in the 6 bit plus sign range of 64 to 63 decimal The 8 bit NV RAM content pointed to by the address is added as a 2 s complement value to 0x40000 the nominal value of 4 RTC P RTC Q Refer to 2 5 4 3 RTC Rate Control for information on the rate adjustments performed by registers RTC_P 16 0 I O RAM 0x289B 2 0 0x289C 0x289D 7 2 and RTC_Q 1 0 I O RAM 0x2891 1 0 The 8 bit values loaded in to NV RAM must be scaled correctly to produce rate adjustments that are consistent with the equations given in 2 5 4 3 RTC Rate Control for RTC P and RTC Q Note that the sum of the 8 bit 2 s complement value looked up and 0x40000 form a 19 bit value which is equal to 4 RTC_P RTC_Q as shown in Figure 17 The output of the Temperature Compensation is automatically loaded into the RTC P 16 0 and RTC Q 1 0 locations after each look up and summation operation LIMIT Look Up RAM STEME 222 ea gt ADDR 10 S 8 256 64 63 255 6 S d 4 RTC_P RTC lh d 75s 19 Q 19
15. Table 71 lists the events that clear the WF flags In addition to push buttons and timers the part can also reboot due to the RESET pin the RESET bit I O RAM 0x2200 3 the WDT the cold start detector and E RST As seen in Table 69 each of these mechanisms has a flag bit to alert the MPU to the source of the wakeup If the wake up is caused by return of system power there is no active WF flag and the VSTAT 2 0 field SFR OxF9 2 0 indicate that system power is stable Table 69 Wake Enables and Flag Bits Wake Enable Wake Flag e De bounce Description Name Location Name Location WAKE ARM 28B2 5 WF TMR 28B1 5 No Wake on Timer EW_PB 28B3 3 WF PB 28B1 3 Yes Wake on PB EW RX 28B3 4 WF RX 28B1 4 2 us Wake on either edge of RX EW_DIO4 28B3 2 WF DIO4 28B1 2 2 us Wake on SEGDIOA EW DIO52 28B3 1 WF DIO52 28B1 1 Yes Wake on SEGDIOB52 OPT RXDIS 1 Wake on DIO55 EW DIO55 28B3 0 WE DIO55 28B1 0 Yes with 64 ms de bounce OPT_RXDIS 0 Wake on either Rev 2 87 71M6541D F G and 71M6542F G Data Sheet Wake Enable Wake Flag n De bounce Description Name Location Name Location edge of OPT_RX with 2 us de bounce OPT_RXDIS I O RAM 0x2457 2 Always Enabled WF RST 28BO 6 2 us Wake after RESET Always Enabled WF_RSTBIT 28BO 5 No Wake after RESET bit Wake after E_ RST Always Enabled WF_ERST 28BO
16. 0x84 WSUM_X for EQU 2 0 0 O RAM 0x2106 7 5 and EQU 2 0 1 0x85 WOSUM X The sum of Wh samples from each wattmeter 0x86 WISUM X element LSB 1 55124 10 VMAX IMAX Wh Figure 36 page 94 Figure 38 page 96 Ox88 VARSUM X The signed sum VAROSUM X VAR1SUM X Not used for EQU 2 0 0 and EQU 2 0 1 0x89 VAROSUM X The sum of VARh samples from each wattmeter Ox8A VARISUM X element LSB 1 55124 10 VMAX IMAX VARh Note 71M6542 only WSUM X CE RAM 0x84 and VARSUM X CE RAM 0x88 are the signed sum of Phase A and Phase B Wh or VARh values according to the metering equation specified in the I O RAM control field EQU 2 0 I O RAM 0x2106 7 5 WxSUM X x 0 or 1 CE RAM 0x85 and 0x86 is the Wh value accumulated for phase x in the last accumulation interval and can be computed based on the specified LSB value 130 Rev 2 71M6541D F G and 71M6542F G Data Sheet 5 3 8 2 Instantaneous Energy Measurement Variables IxSQSUM_X and VxSQSUM see Table 87 are the sum of the squared current and voltage samples acquired during the last accumulation interval Table 87 CE Energy Measurement Variables with Local Sensors Ge ipti Configuration Address Name Description Ox8C IOSQSUM_X_ The sum of squared current samples from each element LSB 9 4045 10 IMAX AH Ox8D I15SQSUM X When EQU 1 IOSQSUM X is based on IA and IB Figure 35 page 93
17. 0x90 VOSQSUM x The sum of squared voltage samples from each Film page Es element _ 13 24 2 0x911 VISQSUM_X LSBy 9 4045 10 VMAX V h 71M6542 only Table 88 CE Energy Measurement Variables with Remote Sensor CE KE Address Name Description Configuration Ox8C IOSQSUM_X The sum of squared current samples from each element LSB 2 55872 10 IMAX AH When EQU 1 IOSQSUM X is based on IA and A IB Figure 36 page 94 0x8D I1SQSUM X Ox90 VOSQSUM X The sum of squared voltage samples from each Figure 38 page 96 element i OKAL P LSBy 9 40448 10 VMAX V h 71M6542 only The RMS values can be computed by the MPU from the squared current and voltage samples as follows N N acc ACC IxSQSUM LSB 3600 F VxSQSUM LSB 3600 F IXpus VXeus Note Nacc SUM_SAMPS 12 0 CE RAM 0x23 Other Transfer variables include those available for frequency and phase measurement and those reflecting the count of the zero crossings of the mains voltage and the battery voltage These transfer variables are listed in Table 89 MAINEDGE_X CE RAM 0x83 reflects the number of half cycles accounted for in the last accumulated interval for the AC signal of the phase specified in the FREQSEL 1 0 field in CECONFIG CE RAM 0x20 7 6 MAINEDGE X is useful for implementing a real time clock based on the input AC signal Rev 2 131
18. 251 UART and Optical Interface i ee eed ieee de es adobe di eae 58 2 5 8 Digital UO and LCD Segment Drivers 59 2 5 9 EEPRONMVInterface ene dedadedadutadutadudtadudtuda terrere 70 2 5 10 SPE Slave De TEE 73 2 5 11 Hardware Watchdog mer 78 2 5 12 Test Ports TMUXOUT and TMUX2OUT Pins mnn 78 3 Functional DescrtiptiOli eee ecu ee AARAA NANANA NA exo KAAR KAAR KARAKA ANKARANA ees irira 80 3 1 Theory of Operaton sinri sinri nennen nennen eian 80 3 2 Batten Modes iin DDR DRRnaGnenno iiM 81 3 2 1 BRN Modes a S48 nA EEN Baan di hin ain Geen E 83 3 2 2 ECD Mode itive un 83 3 2 3 SEP ee coon dao dia oii ada aes 84 71M6541D F G and 71M6542F G Data Sheet 3 3 Fault and Reset Behavior entree eene nennen nennen nennen nnne nnns 85 3 3 1 Events at POWer DDOWn eee eere nnne tnter enhn enhn Dannan E gagne d naay 85 3 3 2 IC Behavior at Low Battery Voltage emn 86 3 39 95 Reset SEQUENCE d dece e p e ae ettet 86 3 3 4 Watchdog Timer RESE EE 86 3 4 Wake Up BehaVvIOF 1 ee o t o ee ee eee ee dd 87 3 4 1 Wake on Hardware Events ccc t t ete te ete ete e Dee LET ER RR 87 SL WAKE Ob IW a S RERO 90 3 5 Data Flow and MPU CE Communication eee 91 4 Application InformatiOh esee ce eere euer eure Feo era Ce a ora a ra Fara EES ra orar ora ara Ee Co Erro EEN 92 Al Connecting 5 V Devices enne nennen nennen nennen nnns ness A sensn sss nennen nnns 92 4 2 Direct Connection o
19. A single 2 order delta sigma A D converter digitizes the voltage and current inputs to the device The resolution of the ADC including the sign bit is 21 bits FIR LEN 1 0 1 I O RAM 0x210C 2 1 or 22 bits FIR_LEN 1 0 2 The ADC is clocked by CKADC Initiation of each ADC conversion is controlled by MUX_CTRL internal circuit as described above At the end of each ADC conversion the FIR filter output data is stored into the CE RAM location determined by the multiplexer selection FIR data is stored LSB justified but shifted left 9 bits 2 2 6 FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer The purpose of the FIR filter is to decimate the ADC output to the desired resolution At the end of each ADC conversion the output data is stored into the fixed CE RAM location determined by the multiplexer selection as shown in Table 1 and Table 2 2 2 7 Voltage References A bandgap circuit provides the reference voltage to the ADC The amplifier within the reference is chopper stabilized i e the chopper circuit can be enabled or disabled by the MPU using the I O RAM control field CHOP E 1 0 I O RAM 0x2106 3 2 The two bits in the CHOP_E 1 0 field enable the MPU to operate the chopper circuit in regular or inverted operation or in toggling modes recommended When the chopper circuit is toggled in between multiplexer cycles dc offsets on VREF are automati
20. LCD RST 240C 2 R W Clear all bits of LCD data These bits affect SEGDIO pins that are configured as LCD drivers LCD DAC 4 0 240D 4 0 RAW This register controls the LCD contrast DAC which adjusts the VLCD voltage and has an output range of 2 5 VDC to 5 VDC The VLCD voltage is VLCD 2 5 2 5 LCD DAC 4 0 31 Thus the LSB of the DAC is 80 6 mV The maximum DAC output voltage is limited by V3P3SYS VBAT and whether LCD BSTE is set LCD CLK 1 0 2400 1 0 RAW Sets the LCD clock frequency 1 T See definition of T in Figure 21 Note fw 32768 Hz 00 fw 2 9 01 fw 2 8 10 fw 2 7 11 fw 2 6 LCD MODE 2 0 2400 6 4 RAW The LCD bias and multiplex mode LCD MODE Output 4 states 1 3 bias 000 3 states 1 3 bias Static display 5 states 1 3 bias 6 states 1 3 bias LCD VMODET1 0 2401 7 6 00 00 R W This register specifies how VLCD is generated LCD_VMODE 11 10 01 00 Description External VLCD LCD boost and LCD DAC enabled LCD DAC enabled No boost and no DAC VLCD VBAT or V3P3SYS The LCD can be driven in static AG bias and 1 3 bias modes Figure 21 defines the COM waveforms Note that COM pins that are not required in a specific mode maintain a segment off state rather than GND VCC or high impedance The segment drivers SEGDIO22 and SEGDIO23 can be configured to blink at eit
21. System Power 143 6 4 9 2 5 V Voltage Regulator Battery Power 144 6 4 10 Crystal Oscillatot rrr rrr rrr ed 144 6 4 11 Phase Locked Loop DL 144 Ra RI PA M GIDIP CICER 145 6 4 13 VLCD Generator 146 MP Il trates 148 GiANIS SADC ero IPTE 149 6 4 16 Pre Amplifier for IAPDIAN cece cece cece reenter reer reese aan e terse n nnn nnnnn nnne rrr nnne nnn 150 6 5 Tifmirig SpecifICatlons 2 9 eee Ieri ceca 151 6 5 1 Fash Memory EE 151 E ASR SIave t faded tcc o oaa oa OC a UR RET S 151 6 5 3 EEPROM MEA CE iiie PR rE aT EE EE IE EFERO EE DER ee eA doc doeet 151 6 54 RESET PIU iiti tr EE HORDE tee e ere ev co vo eee 152 pep drugs Wu 152 Ep Package Outline DraWwIngs orb rer rre E re E RETE EES 153 6 6 1 64 Pin LQFP Outline Package Drawing eeeeseeeeeeeeeeseseeeeeeessrresssssnnrnsnesnnnnnnnnnnenn nn 153 6 6 2 100 Pin LQFP Package Outline Drawing eeeee nn 154 6 7 Package Marklh gs inet tecto Saban toe RO EE ERR DER eee 155 6 8 Pinout Dlagrams noc hopOpPI DB IR ceu Det Ie aos ERREUR DUREE A 156 6 8 1 71M6541D F G LQFP 64 Package Pinot 156 6 8 2 71M6542F G LQFP 100 Package Pmmout nn 157 6 9 Pin Descriptions nennen nenne nnne nnne enne nennen enne nennen nnns 158 6 9 1 Power and Ground Pm 158 6 9 2 sANAlOG Plrisai d on tt o De redet Pe d EP Eee dove deett 159 6 9 3 Digtal GEET 160 6 9 4 O Equivalent CIrCUI
22. or they can be used to directly operate optical components for example an infrared diode and phototransistor implementing a FLAG interface Figure 41 shows the basic connections for UART1 The OPT TX pin becomes active when the I O RAM control field OPT_TXE I O RAM 0x2456 3 2 is set to 00 The polarity of the OPT TX and OPT RN pins can be inverted with the configuration bits OPT TXINV I O RAM 0x2456 0 and OPT_RXINV I O RAM 0x2457 1 respectively The OPT TX output may be modulated at 38 kHz when system power is present Modulation is not available in BRN mode The OPT_TXMOD bit I O RAM 0x2456 1 enables modulation The duty cycle is controlled by OPT_FDC 1 0 I O RAM 0x2457 5 4 which can select 50 25 12 5 and 6 25 duty cycle A 6 2596 duty cycle means OPT TX is low for 6 25 of the period The OPT RX pin uses digital signal thresholds It may need an analog filter when receiving modulated optical signals With modulation an optical emitter can be operated at higher current than nominal enabling it to increase the distance along the optical path Rev 2 101 71M6541D F G and 71M6542F G Data Sheet If operation in BRN mode is desired the external components should be connected to V3P3D However it is recommended to limit the current to a few mA V3P3SYS I 71M654x R4 I I 10 kQ OPT RX C IB DE i Phototransistor E 4 AN I V3P3SYS NN OPT TX Figure 41 Connection for Optical Component
23. 2200 2 0 olol RW The maximum value for MPU DIV 2 0 is 4 Based on the default values of the PLL FAST bit and MPU DIV 2 0 the power up MPU rate is 6 29 MHz 4 1 5725 MHz The minimum MPU clock rate is 38 4 kHz when PLL FAS T 1 MUXO SEL 3 0 2105 3 0 O O RW Selects which ADC input is to be converted during time slot O MUX1_SEL 3 0 2105 7 4 O O RW Selects which ADC input is to be converted during time slot 1 MUX2_SEL 3 0 2104 3 0 O O RW Selects which ADC input is to be converted during time slot 2 MUXS SEL 3 0 2104 7 4 0 O RW Selects which ADC input is to be converted during time slot 3 MUXA SEL 3 0 2103 3 0 O O RW Selects which ADC input is to be converted during time slot 4 MUXS5 SEL 3 0 2103 7 4 0 O RW Selects which ADC input is to be converted during time slot 5 MUX6 SEL 3 0 2102 3 0 O O RW Selects which ADC input is to be converted during time slot 6 MUX7_SEL 3 0 2102 7 4 O O RW Selects which ADC input is to be converted during time slot 7 MUX8 SEL 3 0 2101 3 0 0 O RW Selects which ADC input is to be converted during time slot 8 MUX9_SEL 3 0 2101 7 4 0 O RW Selects which ADC input is to be converted during time slot 9 MUX10 SEL 3 0 2100 3 0 O O RW Selects which ADC input is to be converted during time slot 10 118 Rev 2 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir
24. 44 68 IBP Pins IBP IBN may be configured for communication with 43 67 IBN the remote sensor interface 71M6x01 When RMT _E 1 I O RAM 0x2709 3 the IBP IBN pins become balanced differential pair If unused RMT E must be zero and IBP IBN must tied to V3P3A Line Voltage Sense Inputs These pins are voltage 52 82 VA 6 inputs to the internal A D converter Typically they are 83 vB connected to the outputs of resistor dividers Unused pins must be tied to V3P3A Voltage Reference for the ADC This pin should be left m iu WSEF 2 S unconnected floating Crystal Inputs A 32 kHz crystal should be connected across these pins Typically a 15 pF capacitor is also connected from XIN to GNDA and a 10 pF capacitor is connected from XOUT to GNDA It A9 19 AN 8 is important to minimize the capacitance between these 49 76 XOUT O pins See the crystal manufacturer datasheet for details If an external clock is used a 150 mV p p clock signal should be applied to XIN and XOUT should be left unconnected Pin VB only available on 71M6542F G Rev 2 159 71M6541D F G and 71M6542F G Data Sheet 6 9 3 Digital Pins Table 121 lists the digital pins Pin types P Power O Output Input I O Input Output N C no connect The circuit number denotes the equivalent circuit as specified in 6 9 4 I O Equivalent Circuits Table 121 Digital Pins
25. 5 VARPULSE _ gt o 2 E a D 8 E x z z PB EEPROM 4 INTERFACE Q VBAT_RTC MPU Non Volatile Rx 80515 CONFIGURATION RAM TXL IGURATION RAM OPT RX lee DATA D RAM ue INIEBRAGE 0x0000 0xFFFF SEGDIO5S i ol 0x2000 0x20FF OPT_TX 3 TEMP 0x0000 SENSOR SEGDIO51 MEMORY OxFFFF FLASH PROGRAM SHARE i 32 64 128 kp WPULSE 0x0000 0xFFFF Hm VARPULSE 7 n CON FIGURATION EMULATOR PARAMETERS weu Rszz CKMPU 2x gt PORT POWER FAULT DETECTION WAKE TEST MUX TEST MUX 2 FAULTZ VSTAT 10 11 2011 71M6542F G only RESET E RXTX ISEGAB ICE E E TCLK SEG49 41 E_RST SEG50 Figure 1 IC Functional Block Diagram Rev 2 9 71M6541D F G and 71M6542F G Data Sheet 1 Introduction This data sheet covers the 71M6541D 32KB 71M6541F 64KB 71M6541G 128KB 71M6542F 64KB and 71M6542G 128KB fourth generation Teridian energy measurement SoCs The term 71M654x is used when discussing a device feature or behavior that is applicable to all four part numbers The appropriate part number is indicated when a device feature or behavior is being discussed that applies only to a specific part number This data sheet also covers basic details about the companion 71M6x01 isolated current sensor device For more complete information on the 71M6x01 sensors refer to the 71M6xxx Data Sheet This document covers the use of the 71M654x with locally connected sensors as well when it is use
26. 6 located at I O RAM 0x270A 2 0 0x270A 6 4 and 0x2709 2 0 respectively Next the MPU writes RCMD 4 0 SFR OxFC 4 0 with the desired command and phase selection When the RCMD 4 2 bits have cleared to zero the transaction has been completed and the requested data is available in RMT_RD 15 0 I O RAM 0x2602 7 0 is the MSB and 0x2603 7 0 is the LSB The read parity error bit PERR RD SFR OxFC 6 is also updated during the transaction If the MPU writes to RCMD 4 0 before a previously initiated read transaction is completed the command is ignored Therefore the MPU must wait for RCMD 4 2 0 before proceeding to issue the next remote sensor read command The RCMDJ 4 0 field is divided into two sub fields COMMAND RCMD 4 2 and PHASE RCMD 1 0 as shown in Table 5 Table 5 RCMD 4 0 Bits Command Phase Selector Associated TMUXRn RCMDJ 4 2 RCMD 1 0 Control Field 000 Invalid 00 Invalid 001 Command 1 01 IBP IBN TMUXRB 2 0 100 Reserved 101 Invalid 110 Reserved 22 Rev 2 71M6541D F G and 71M6542F G Data Sheet 111 Reserved 1 Only two codes of RCMD 4 2 SFR OxFC 4 2 are relevant for normal operation These are RCMD 4 2 001 and 010 Codes 000 and 101 are invalid and will be ignored if used The remaining codes are reserved and must not be used 2 For the RCMD 1 0 control field codes 01 10 and 11 are valid and 00 is invalid and must not be used
27. CE RAM IN v INP SP IBP Remote Digital Shunt 71M6x01 Isolation gt SN IBN Interface a INN 71M6541D F 11 5 2010 IN Optional Neutral Current Figure 3 71M6541D F G AFE Block Diagram with 71M6x01 Figure 4 shows the 71M6542F G AFE with locally connected sensors The analog input signals IAP IAN VA IBP IBN and VB are multiplexed to the ADC input and sampled by the ADC The ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and processed by the CE See Figure 7 for the multiplexer timing sequence corresponding to Figure 4 See Figure 37 for the meter configuration corresponding to Figure 4 VREF n IA Y IAP praene epe Ea L MUX AX ADC CONVERTER cr amp or Local VREF Shunt IAN VREF ET ee gt FIR CE RAM VADC gt ES VADC10 VA VADC9 VB IB Y IBP GT IBN gt 71M6542F 11 5 2010 Figure 4 71M6542F G AFE Block Diagram Local Sensors Rev 2 13 71M6541D F G and 71M6542F G Data Sheet Figure 5 shows the 71M6542F G multiplexer interface with one local and one remote resistive shunt sensor As seen in Figure 5 when a remote isolated shunt sensor is connected via the 71M6x01 the samples associated with this current channel are not routed to the multiplexer and are instead transferred digitally to the 71M
28. CROSS Signal with CHOP E 00 sssssssssssssenneeeee eene nenne nennen nnne nnn nnns 21 RIM TINNO DEET TEE stint a DARE I ARTS 26 Timing relationship between ADC MUX CE and RTM Serial Transier 26 Pulse Generator FIFO TIMING E 28 Accumulation Interval eese yeyIyIH seen 29 Samples from Multiplexer Cycle MUX DIV 3 0 3 30 Samples from Multiplexer Cycle MUX DIV 3 0 AN 30 Interr pt StrUct re p ee 47 Automatic Temperature Compensation 00 c cece cece cece cece eee e eee eter tees esa aaeeeeeeeeeeeeaaaaaeeeeeeeeeeeaaa 54 Optical Interface ET 58 Optical Intertace ARTA 2 citt sete aaa i aa aA pepe ced bate a 2s epe decent tieeees 59 Connecting an External Load to DIO Pins ssssssssesseenm meer 60 LCD Wael S iet ee tee t ee t e tete t t a n c e e e een 68 3 wire Interface Write Command H 72 3 wire Interface Write Command HZH 72 3 wire Interface Read Commande 72 3 Wire Interface Write Command when CNT ZO ssssssssseee emere nnn 73 3 wire Interface Write Command when HiZ 1 and WERT e 73 SPI Slave Port Typical Multi Byte Read and Write operatons 75 Voltage Current Momentary and Accumulated Energy 80 Operation Modes State Diagramm 81 MPU CE Da ta El0Wisiiiuiiingtsdtie a I PRU CERE der a 91 Resistive Voltage Divider Voltage Gensimng een 92 CT with Single Ende
29. Description MUX_DIV 3 0 is the number of ADC time slots in each MUX frame The maximum number of time slots is 11 Configures the input of the optical port to be a DIO pin to allow it to be bit banged In this case DIO5 becomes a third high speed UART Refer to OPT_BB 2457 0 0 RW 2 5 7 UART and Optical Interface under the Bit Banged Optical UART Third UART sub heading on page 58 MUX DIV 3 0 2100 7 4 o lol RW Selects OPT TX modulation duty cycle OPT FDC Function 0 OPT_FDC 1 0 2457 5 4 0 RW Ee 01 2596 Low 10 12 596 Low 11 6 25 Low OPT_RX can be configured as an input to the optical UART or as SEGDIO55 OPT RXDIS 0 and LCD MAP 55 0 OPT RX OPT_RXDIS 2457 2 O RW OPT RXDIS 1 and LCD MAP 55 0 DIO55 OPT_RXDIS 0 and LCD MAP 55 1 SEG55 OPT_RXDIS 1 and LCD MAP 55 1 SEG55 Inverts result from OPT_RX comparator when 1 Affects only the UART input E Een 9 gs Has no effect when OPT RX is used as a DIO input Configures the OPT_TX output pin If LCD MAP 51 0 OPT TXE 1 0 2456 3 2 00 R W 00 DIO51 01 OPT TX 10 WPULSE 11 VARPULSE If LCD MAP 51 1 Xx SEG51 OPT_TXINV 2456 0 0 RW Invert OPT TX when 1 This inversion occurs before modulation Enables modulation of OPT_TX When OPT_TXMOD is set OPT_TX is OPT_TXMOD 2456 1 O RAW modulated when it would otherw
30. RW Selects the LCD bias and multiplex mode LCD_MODE Output LCD_MODE Output LCD MODE 2 0 2400 6 4 ol RW 000 4 states 1 3 bias 100 Static display 001 3 states 1 3 bias 101 5 states 1 3 bias 010 2 states LG bias 110 6 states 1 3 bias 011 3 states bias LCD_ON 240C 0 0 RW Turns on or off all LCD segments without changing LCD data If both bits are LCD_BLANK 240C 1 0 RW set the LCD display is turned on Puts the IC to sleep but with LCD display still active Ignored if system power LCD ONLY 28B2 6 0 0 W is present It awakens when Wake Timer times out when certain DIO pins are raised or when system power returns See 3 2 Battery Modes Clear all bits of LCD data These bits affect SEGDIO pins that are configured pee CTE Of e as LCD drivers This bit does not auto clear LCD SEGO 5 0 MEE x e GE 2410 5 0 to ol 1 RW SEG Data for SEGO through SEG15 DIO data for these pins is in SFR LCD SEGI15 5 0 241F 5 0 space LCD_SEGDIO16 5 0 2420 5 0 to SEG and DIO data for SEGDIO16 through SEGDIO45 If configured as DIO to 243DI5 0 O R W bit 1 is direction 1 is output O is input bit O is data and the other bits are LCD SEGDIO45 5 0 5 0 ignored LCD SEG406 5 0 to 243E b 0 to 2442 5 0 o RW emi data for SEG46 through SEG50 These pins cannot be configured as LCD SEG50 5 0 l SEG and DIO data for SEGDIO51 through SEGDIO55 If configured as DIO LCD_SEGDIO51 5 0 E Hone ieee EE 3 to 2443
31. VOS 36 37 38 39 44 45 Direction Register 0 input 1 output LCD_SEGDIO32 1 to LCD_SEGDIO45 1 VO RAM 0x2434 2437 1 to 0x243C 243D 1 Table 51 Data Direction Registers for SEGDIO51 and SEGDIO55 71M6541D F G DIO Data Register SEGDIO Bi aes res sem e EEN Pin 4 39 1 ee ile ed eser es Configuration Eae e esi Saee tan e 0 DIO 1 LCD LCD MAP 55 LDC_MAP 51 VO RAM 0x2405 54 55 SEG Data Register LCD SEGDIO51 5 0 LCD_SEGDIO55 5 0 VO RAM 0x2443 5 0 and 0x2447 5 0 B Men ces ul tens Is eg le A LCD SEGDIO51 0 to LCD SEGDIOS55 0 VO RAM 0x2443 0 and 0x2447 0 Direction Register 0 input 1 output 51 55 LCD SEGDIO51 1 to LCD SEGDIO55 1 VO RAM 0x2443 1 and 0x2447 1 62 Rev 2 71M6541D F G and 71M6542F G Data Sheet 2 5 8 3 Digital UO for the 71M6542F G A total of 55 combined SEG DIO pins are available for the 71M6542D F These pins can be categorized as follows 35 combined DIO LCD segment pins o SEGDIO4 SEGDIO5 2 pins o SEGDIOS9 SEGDIO25 17 pins o SEGDIO28 SEGDIO35 8 pins o SEGDIO40 SEGDIO45 6 pins o SEGDIO52 SEGDIO53 2 pins 15 combined DIO LCD segment pins shared with other functions o SEGDIOO WPULSE SEGDIO1 VPULSE 2 pins o SEGDIO2 SDCK SEGDIO3 SDATA 2 pins o SEGDIO6 XPULSE SEGDIO7
32. by a memory share circuit Each CE instruction word is two bytes long Allocated flash space for the CE program cannot exceed 4096 16 bit words 8 KB The CE program counter begins a pass through the CE code each time multiplexer state O begins The code pass ends when a HALT instruction is executed For proper operation the code pass must be completed before the multiplexer cycle ends The CE program must begin on a 1 KB boundary of the flash address The I O RAM control field CE LCTN 5 0 I O RAM 0x2109 5 0 defines which 1 KB boundary contains the CE code Thus the first CE instruction is located at 1024 CE LCTN 5 0 2 3 2 CE Data Memory The CE and MPU share data memory RAM Common access to XRAM by the CE and MPU is controlled by a memory share circuit The CE can access up to 3 KB of the 3 KB data RAM XRAM i e from RAM address 0x0000 to OxOCOO The XRAM can be accessed by the FIR filter block the RTM circuit the CE and the MPU Assigned time slots are reserved for FIR and MPU respectively to prevent bus contention for XRAM data access by the CE The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data communication between the two processors Table 3 shows the CE addresses in XRAM allocated to analog inputs from the AFE The CE is aided by support hardware to facilitate implementation of equations pulse counters and accumulators This hardware is controlled through the I O RAM contr
33. the MPU program but not to make other changes to the chip s state 3 3 4 Watchdog Timer Reset The watchdog timer WDT is described in 2 5 11 Hardware Watchdog Timer A status bit WF OVF I O RAM 0x28B0 4 is set when a WDT overflow occurs Similar to the other wake flags this bit is powered by the non volatile supply and can be read by the MPU to determine if the part is initializing after a WD overflow event or after a power up The WF OVF bit is cleared by the RESET pin 86 Rev 2 71M6541D F G and 71M6542F G Data Sheet There is no internal digital state that could deactivate the WDT For debug purposes however the WDT can be disabled by raising the ICE E pin to 3 3 VDC In normal operation the WDT is reset by periodically writing a one to the WD RST control bit O RAM 0x28B4 7 The watchdog timer is also reset when the 71M654x wakes from LCD or SLP mode and when ICE E 1 3 4 Wake Up Behavior As described above the part always wakes up in MSN mode when system power is restored As described in 3 2 Battery Modes transitions from both LCD and SLP mode to BRN mode can be initiated by a wake up timer timeout when the pushbutton PB input is high a high level on SEGDIOA SEGDIO52 or SEGDIOS55 or by activity on the RX or OPT RX pins 3 4 1 Wake on Hardware Events The following pin signal events wake the 71M654x from SLP or LCD mode a high level on the PB pin either edge on the RX pin a rising edge on the SE
34. 0 RW 00 fue 64 Hz 10 fue 256 Hz fw fw _ 01 s 7 128 Hz 11 W 512 Hz 2 2 The LCD contrast DAC This DAC controls the VLCD voltage and has an output range of 2 5 V to 5 V The VLCD voltage is LCD DAC 4 0 240D 4 0 0 RW VLCD 2 5 2 5 LCD DAC 4 0 31 Thus the LSB of the DAC is 80 6 mV The maximum DAC output voltage is limited by V3P3SYS VBAT and whether LCD_BSTE 1 Enables the LCD display When disabled VLC2 VLC1 and VLCO are ground as are the COM and SEG outputs if their LCD MAP bit is 1 LCD E 2400 7 o BW 116 Rev 2 71M6541D F G and 71M6542F G Data Sheet LCD SEGDIO55 5 0 Name Location Rst Wk Dir Description LCD_MAP 55 48 2405 7 0 0 RW Enables LCD segment driver mode of combined SEGDIO pins Pins that LCD MAP 47 40 2406 7 0 0 RW cannot be configured as outputs SEG48 through SEG50 become inputs with LCD MAP 39 32 2407 7 0 0 RW jinternal pull ups when their LCD MAP bit is zero Also note that SEG48 LCD MAP 31 24 2408 7 0 0 RW through SEGB5O are multiplexed with the in circuit emulator signals When the LCD MAP 23 16 2409 7 0 0 RW ICE E pin is high the ICE interface is enabled and SEG48 through SEG50 LCD MAP 15 8 240A 7 0 o RW become E RXTX E TCLK and E RST respectively LCD MAP 7 0 240B 7 0 o
35. 0 1 572864 MHz 4 9152 MHz ADC_DIV 1 0 786432 MHz 2 4576 MHz BCURR 2704 3 0 O RW Connects a 100 pA load to the battery selected by TEMP_BSEL BSENSE 7 0 2885 7 0 R The result of the battery measurement See 2 5 6 71M654x Battery Monitor CE E 2106 0 O O RW CE enable CE program location The starting address for the CE program is CE LCTN 5 0 2109 5 0 31 31 R W iT e g prog m EC E These bytes contain the chip identification Chop enable for the reference bandgap circuit The value of CHOP changes CHOP E 1 0 2106 3 2 o lol pa on the rising edge of MUXSYNC according to the value in CHOP E 00 toggle 01 positive 10 reversed 11 toggle except at the mux sync edge at the end of an accumulation interval Rev 2 111 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir Description The CHOP settings for the remote sensor 00 Auto chop Change every MUX frame CHOPR 1 0 2709 7 6 00 00 R W 01 Positive 10 Negative 11 Auto chop Same as 00 DIFFA_E 210C 4 O O RW Enables differential configuration for the IA current input IAP IAN DIFFB E 210C 5 O 0 RW Enables differential configuration for the IB current input IBP IBN DIO R2 2 0 2455 2 0 0 Connects PB and dedicated I O pins DIO2 through DIO11 to internal resources DIO R3 2 0 2455 6 4 0 If more than one
36. 1 Positive EEPROM CMDJ3 0 Operation 0000 No op command 0010 Receive a byte from the EEPROM and send ACK 3 0 CMD 3 0 W 0000 Positive 0011 Transmit a byte to the EEPROM 0101 Issue a STOP sequence 0110 Receive the last byte from the EEPROM and do not send ACK 1001 Issue a START sequence Others No operation set the ERROR bit The EEPROM interface can also be operated by controlling the DIO2 and DIOS pins directly The vd direction of the DIO line can be changed from input to output and an output value can be written with a single write operation thus avoiding collisions see Table 15 Port Registers SEGDIOO 15 Therefore no resistor is required in series SDATA to protect against collisions 2 5 9 2 Three wire p Wire EEPROM Interface with Single Data Pin A 500 kHz three wire interface using SDATA SDCK and a DIO pin for CS is available The interface is selected by setting DIO EEX 1 0 10 The EECTRL bits when the three wire interface is selected are shown in Table 61 When EECTRL is written up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM depending on the values of the EECTRL bits 2 5 9 3 Three wire py Wire SPI EEPROM Interface with Separate Di DO Pins If DIO EEX 1 0 11 the three wire interface is the same as above except DI and DO are separate pins In this case SEGDIO3 becomes DO and SEGDIO8 becomes DI The timing diagram
37. 103 71M6541D F G and 71M6542F G Data Sheet 4 14 Flash Programming 4 14 1 Flash Programming via the ICE Port Operational or test code can be programmed into the flash memory using either an in circuit emulator or the Flash Programmer Module TFP 2 available from Teridian The flash programming procedure uses the E RST E RXTX and E TCLK pins 4 14 2 Flash Programming via the SPI Port It is possible to erase read and program the flash memory of the via the SPI port See 2 5 10 SPI Slave Port for a detailed description 4 15 MPU Firmware Library All application specific MPU functions mentioned in 4 Application Information are featured in the demonstration C source code supplied by Teridian The code is available as part of the Demonstration Kit for the 71M6541D F G and 71M6542F G The Demonstration Kits come with the preprogrammed with demo firmware and mounted on a functional sample meter Demo Board The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in circuit emulator ICE 4 16 Crystal Oscillator The oscillator of the 71M6541D F G and 71M6542F G drives a standard 32 768 kHz watch crystal The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_
38. 5 0 to 2447 5 0 0 Rw bit 1 is direction 1 is output O is input bit O is data and the other bits are ignored SEGDIO52 through SEDIO54 are available only on the 71M6542F G Rev 2 117 71M6541D F G and 71M6542F G Data Sheet Name Location RstWk Dir Description Specifies how VLCD is generated See 2 5 8 4 for the definition of V3P3L LCD_VMODE Description 11 External VLCD LCD VMODE 1 0 2401 7 6 00 00 RAW Hu ay 7 6 10 LCD boost and LCD DAC enabled 01 LCD DAC enabled 00 No boost and no DAC VLCD V3P3L LCD Blink Frequency ignored if blink is disabled LCD Y 2400 2 0 RWW L 1H 0 0 5 HZ LKPADDR 6 0 2887 6 0 O O RW The address for reading and writing the RTC lookup RAM Auto increment flag When set LKPADDR auto increments every time LKPAUTOI 2887 7 O O RW LKP RD or LKP_WR is pulsed The incremented address can be read at LKPADDR 6 0 LKPDAT 7 0 2888 7 0 O O RW The data for reading and writing the RTC lookup RAM Strobe bits for the RTC lookup RAM read and write When set the LKPADDR 6 0 field and LKPDAT register is used in a read or write LKP RD 2889 1 0 0 RW operation When a strobe is set it stays set until the operation completes at LKP WR 2889 0 0 0 R W which time the strobe is cleared and LKPADDR 6 0 is incremented if the LKPAUTOI bit is set MPU clock rate is MPU Rate MCK Rate 20 MPU PM20 MPU DIV 2 0
39. 6 2 Recommended External Components Table 94 Recommended External Components Name From To Function Value Unit C1 V3P3A GNDA Bypass capacitor for 3 3 V supply 20 1 20 uF C2 V3P3D GNDD Bypass capacitor for 3 3 V output 0 1 20 uF CSYS V3P3SYS GNDD Bypass capacitor for V3P3SYS 21 0 30 uF CVDD VDD GNDD Bypass capacitor for VDD 0 1 20 uF Bypass capacitor for VLCD pin when CVLCD VLCD GNDD charge pump is used 20 1 20 uF 32 768 kHz crystal electrically similar to ECS 327 12 5 17X Vishay XT26T or AUS SH XOUT Suntsu SCP6 32 768kHz TR load SEWER AME capacitance 12 5 pF Load capacitor values for crystal depend on CXS XIN GNDA crystal specifications and board parasitics 15 10 pF Nominal values are based on 4 pF board CXL XOUT GNDA capacitance and include an allowance for 10 10 pF chip capacitance 7 6 3 Recommended Operating Conditions Unless otherwise specified all parameters listed in 6 4 Performance Specifications and 6 5 Timing Specifications are valid over the Recommended Operating Conditions provided in Table 95 below Table 95 Recommended Operating Conditions Parameter Condition Min Typ Max Unit precision metering operation MSN mode VBAT OV to 38 V Voltages at VBAT and VBAT_RTC need Seel ae ae SR M not be present VBAT Voltage BRN mode V3P3SYS is V3P3SYS lt 2 8 V below the 2 8 V comparator threshold and
40. 71M654x monitors the V3P3A pin voltage only Indicates that the V3P3A pin voltage is 2 2 8 V The V3P3A and E V3OK bit V3P3SYS pins are expected to be tied together at the PCB level The 71M654x monitors the V3P3A pin voltage only 1B MUX SYNC Ls multiplexer frame SYNC signal See Figure 6 and Figure 1C CE BUSY interrupt ee p See 2 3 3 on page 25 and Figure 16 on page 47 1D CE_XFER interrupt 1F RTM output from CE See 2 3 5 on page 25 Note All TMUX 5 0 values which are not shown are reserved Table 66 TMUX2 4 0 Selections TMUX2 4 0 Signal Name Description 0 WD OVF Indicates when the watchdog timer has expired overflowed One second pulse with 2596 Duty Cycle This signal can be used 1 PULSE 1S to measure the deviation of the RTC from an ideal 1 second interval Multiple cycles should be averaged together to filter out jitter Four second pulse with 25 Duty Cycle This signal can be used to measure the deviation of the RTC from an ideal 4 second 2 PULSE_4S interval Multiple cycles should be averaged together to filter out jitter The 4 second pulse provides a more precise measurement than the 1 second pulse 3 RTCLK 32 768 kHz clock waveform 8 SPARE 1 bit I O RAM Copies the value of the bit stored in 0x2704 1 For general 0x2704 1 purpose use 9 SPARE 2 bit LO RAM Copies the value of the bit stored in 0x2704 2 For general 0x2704 2 purpose use
41. 71M6x01 Included on the 71M6x01 companion isolator chip are Digital isolation communications interface An analog front end AFE A precision voltage reference VREF A temperature sensor for digital temperature compensation A fully differential shunt resistor sensor input A pre amplifier to optimize shunt current sensor performance Isolated power circuitry obtains dc power from pulses sent by the 71M654x In a typical application the 32 bit compute engine CE of the 71M654x sequentially processes the samples from the voltage inputs on analog input pins and from the external 71M6x01 isolated sensors and performs calculations to measure active energy Wh and reactive energy VARh as well as Ah and V h for four quadrant metering These measurements are then accessed by the MPU processed further and output using the peripheral devices available to the MPU In addition to advanced measurement functions the clock function allows the 71M6541D F G and 71M6542F G to record time of use TOU metering information for multi rate applications and to time stamp tamper or other events Measurements can be displayed on 3 3 V LCDs commonly used in low tem perature environments An on chip charge pump is available to drive 5 V LCDs Flexible mapping of LCD display segments facilitate integration of existing custom LCDs Design trade off between the number of LCD segments and DIO pins can be implemented in software to accommodate various requiremen
42. 74 73 72 77 70 69 68 71M6542G GT 110124TK ss 62 is 445AP so VTOaaane o 71M6541D IGT 428AB 104224TH 1 2 3 4 5 6 7 8 20 56 21 55 22 54 23 53 24 52 25 51 ortcoooQgudoaosxuooroooguozoortooo UTERE UUUUUUUDUUUUUUUDUUUUUUUUU Figure 49 Package Markings Examples Figure 49 provides an example of the package markings for the 64 pin and 100 pin packages Package markings comprise three lines of text and are as described in Table 117 and Table 118 below Table 117 71M6541 Package Markings Line No Markings Description 1 71M6541D Part number IGT wraps to the next line Refer to Table 122 The five characters to the right of the dot TARGAR i e 428AB are the lot code The first four digits to the left are the year and week of manufacture as YYWW In this example the date code is 1042 which 3 104224TH represents year 2010 week 42 The last four characters i e 24TH are reserved for Maxim internal use only Table 118 71M6542 Package Markings Line No Markings Description 1 71M6542G IGT Part number Refer to Table 122 The first four digits to the left are the year and week of manufacture as YYWW In this example the date code is 1101 which 2 110124TK represents year 2011 week 1 The last four characters i e 24TK are reserved for Maxim internal use only 3 445AP A five character lot code
43. 8 bit Timer Counters Mode 1 Mode 2 Mode 3 In Mode 3 TLO is affected by TRO and gate control bits and sets the TFO flag on overflow while THO is affected by the RI bit and the TF1 flag is set on overflow Table 23 specifies the combinations of operation modes allowed for Timer O and Timer 1 Table 23 Allowed Timer Counter Mode Combinations Timer 1 Mode 0 Mode 1 Mode 2 Timer 0 mode 0 Yes Yes Yes Timer 0 mode 1 Yes Yes Yes Timer 0 mode 2 Not allowed Not allowed Yes Rev 2 71M6541D F G and 71M6542F G Data Sheet Table 24 TMOD Register Bit Description SFR 0x89 Bit Symbol Function Timer Counter 1 TMOD 7 Gate If TMOD 7 is set external input signal control is enabled for Counter 1 The TRI bit in the TCON register SFR 0x88 must also be set in order for Counter 1 to increment With these settings Counter 1 increments on every falling edge of the logic signal applied to one or more of the SEGDIO2 11 pins as specified by the contents of the DIO R2 through DIO R11 registers See 2 5 8 Digital I O and LCD Segment Drivers and Table 47 TMOD 6 C T Selects timer or counter operation When set to 1 a counter operation is performed When cleared to 0 the corresponding register functions as a timer TMOD 5 4 MI MO Selects the mode for Timer Counter 1 as shown in Table 22 Timer Counter 0 TMOD 3 Gate If TMOD 3 is set external i
44. A WAKE Indicates when a WAKE event has occurred B MUX SYNC a multiplexer frame SYNC signal See Figure 6 and Figure C MCK See 2 5 3 on page 50 E GNDD Digital GND Use this signal to make the TMUX2OUT pin static 12 INTO DIG I O 13 INT1 DIG I O 14 INT2 CE PULSE 15 INT3 CE BUSY Interrupt O See 2 4 8 on page 40 Also see Figure 16 on page 47 16 INT4 VSTAT 17 INT5 EEPROM SPI 18 INT6 XFER RTC 1F HIM CK flash See 2 3 5 on page 25 Note All TMUX2 4 0 values which are not shown are reserved Rev 2 79 71M6541D F G and 71M6542F G Data Sheet 3 Functional Description 3 1 Theory of Operation The energy delivered by a power source into a load can be expressed as t E f V O1 Odt 0 Assuming phase angles are constant the following formulae apply P Real Energy Wh V A cos ot Q Reactive Energy VARh V A sing t S Apparent Energy VAh JP Q For a practical meter not only voltage and current amplitudes but also phase angles and harmonic content may change constantly Thus simple RMS measurements are inherently inaccurate A modern solid state electricity meter IC such as the Teridian 71M654x functions by emulating the integral operation above i e it processes current and voltage samples through an ADC at a constant frequency As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest the current and voltage samples mult
45. DIO pins are DIO inputs except for SEGDIOO 15 see caution note below until they are configured as desired under MPU control The pin function can be configured by the I O RAM registers LCD MAPn 0x2405 0x240B Setting the bit corresponding to the pin in LCD MAPn to 1 configures the pin for LCD setting LCD MAPn to 0 configures it for DIO disabled by PORT E 0 I O RAM 0x270C 5 to avoid unwanted pulses during reset After configuring pins SEGDIOO through SEGDIO15 the MPU must enable these pins by setting PORT E Once a pin is configured as DIO it can be configured independently as an input or output For SEGDIOO to SEGDIO15 this is done with the SFR registers PO SFR 0x80 P1 SFR 0x90 P2 SFR 0xA0 and P3 SFR 0xB0 as shown in Table 48 71M6541D F G and Table 52 71M6542F G The PB pin is a dedicated digital input and is not part of the SEGDIO system e After reset or power up pins SEGDIOO through SEGDIO15 are initially DIO outputs but are The CE features pulse counting registers and each pulse counter interrupt output is internally routed to the pulse interrupt logic Thus no routing of pulse signals to external pins is required in order to generate pulse interrupts See interrupt source No 2 in Figure 16 A 3 bit configuration word UO RAM register DIO Rn I O RAM 0x2009 2 0 through 0x200E 6 4 can be used for pins SEGDIO2 through SEGDIO11 when configured as DIO and PB to individually assign an internal resource suc
46. DIV 3 0 The duration of a multiplexer frame in CK FIR cycles is MUX frame duration CK FIR cycles 3 2 PLL FAST Time Slot Duration MUX DIV 48 PLL_FAST 102 The ADC conversion sequence is programmable through the MUXx SEL control fields I O RAM 0x2100 to 0x2105 As stated above there are three ADC time slots in the 71M6541D F G and four ADC time slots in the 71M6542F G as set by MUX_DIV 3 0 I O RAM 0x2100 7 4 In the expression MUXx SEL 3 0 n x refers to the multiplexer frame time slot number and n refers to the desired ADC input number or ADC handle e ADCO to ADC10 or simply O to 10 decimal Thus there are a total of 11 valid ADC handles in the 71M654x devices For example if MUXO SEL 3 0 0 then ADCO corresponding to the sample from the IAP IAN input configured as a differential input is positioned in the multiplexer frame during time slot 0 See Table 1 and Table 2 for the appropriate MUXx SEL 3 0 settings and other settings applicable to a particular CE code Note that when the remote sensor interface is enabled and even though the samples corresponding to the remote sensor current IBP IBN do not pass through the multiplexer the MUX2 SEL 3 0 and MUXS3 SEL 3 0 control fields must be written with a valid ADC handle that is not being used Typically ADC1 is used for this purpose see Table 2 In this manner the ADC1 handle which is not used in the 71M6541D F G or 71M6542F G is used as a place hol
47. E 1 O DIFFA E 1 RAM 0x210C 4 The ADC results are stored in CE RAM location ADCO CE RAM 0x0 and ADC1 CE RAM 0x1 is not disturbed For locally connected sensors Figure 2 and Figure 4 the IBP ADC2 differential input must be enabled by setting DIFFB E I O RAM 0x210C 5 DIFFB E 1 For the remote connected sensor Figure 3 and Figure 5 Or with a remote shunt sensor RMT E I O RAM 0x2709 3 IBN ADC3 RMT E 1 must be set In both cases the ADC results are stored in RAM location ADC2 CE RAM 0x2 and ADC3 CE RAM 0x3 is not disturbed Single ended mode only The ADC result is stored in RAM location ADC10 CE RAM 0xA Single ended mode only 71M6542F only The ADC result is stored in RAM location ADC9 CE RAM 0x9 Pin Comment IAN ADC1 VA ADC10 VB ADC9 Rev 2 17 71M6541D F G and 71M6542F G Data Sheet Multiplexer advance FIR initiation and chopping of the ADC reference voltage using the internal CROSS signal see 2 2 7 Voltage References are controlled by the internal MUX CTRL circuit Additionally MUX CTRL launches each pass of the CE through its code Conceptually MUX CTRL is clocked by CK32 the 32768 Hz clock from the PLL block The behavior of the MUX CTRL circuit is governed by e CHOP E 1 0 I O RAM 0x2106 3 2 e MUX_DIV 3 0 O RAM 0x2100 7 4 e FIR LEN 1 0 I O RAM 0x210C 2 1 e ADC DIV I O RAM 0x2200 5 The du
48. IBP IBN input must be configured as an analog differential input disabling the remote sensor interface i e RMT E 0 I O RAM 0x2709 3 See Figure 4 for the AFE configuration corresponding to Note This system is referenced to PHASE A LL Lee H emm CH kung NEUTRAL POWER SUPPLY A PHASE A I o gt S MUX and ADC V3P3A V3P3SYS GNDA GNDD g IAP PWR MODE IAN CONTROL TERIDIAN WAKE UP n 71M6542F REGULATOR BATTERY S D VBAT IL R VBAT_RTC ps TEMPERATURE BATTERY BATTERY SENSOR MONITOR l VREF RAM SERIAL PORTS ron LEDDISPLAY COMPUTE Se 8888 8888 TX ENGINE SEG DIO AMR RX LCD DRIVER BEEN FLASH SS gees PULSES MODUL RX MEMORY E DIO e IR ATOR d TX i I 5 POWER FAULT MPU es IC or pWire COMPARATOR RTC EEPROM TIMERS HOST SPI INTERFACE S 32 kHz ICE 11 5 2010 Figure 37 71M6542F G with Local Sensors Rev 2 95 71M6541D F G and 71M6542F G Data Sheet 4 6 71M6542F G Using 71M6x01 and Current Shunts Figure 38 shows a typical two phase connection for the 71M6542F G using one isolated and one non isolated sensor For best performance the IAP IAN current sensor input is configured for differential mode i e DIFFA E 1 I O RAM 0x210C 4 The 71M6x01 Isolated Sensor Interface is used to isolate phase B The outputs of the 71M6x01 Isolated Sensor Interf
49. In this configuration IAP IAN IBP IBN and VA are sampled the extra conversion time slot i e slot 2 is the optional Neutral current and the physical current sensor for the Neutral current measurement may be omitted if not required For a standard single phase application with tamper sensor in the neutral path two current inputs can be configured for differential mode using the pin pairs IAP IAN and IBP IBN This means that the multiplexer applies a total of three inputs to the ADC In this application the system design may use two locally connected current sensors via IAP IAN and IBP IBN as shown in Figure 2 and configured as differential inputs Alternately the IAP IAN pin pair is configured as a differential input and connected to a local current shunt and IBP IBN is configured to connect to an isolated 71M6x01 isolated sensor i e RMT E 1 as shown in Figure 3 The VA pin is typically connected to the phase voltage via resistor dividers For this configuration the multiplexer frame is also as shown in Figure 6 and time slot 2 is unused and ignored by the CE as the samples corresponding to the remote sensor IBP IBN do not pass through the multiplexer and are stored directly in CE RAM The remote current sensor channel is sampled during the second half of the multiplexer frame and its timing relationship to the VA voltage is precisely known so that delay compensation can be properly applied The 71M6542F adds the ability to sample a
50. LOO E Ee OS From Host SPI_CSZ 0 15 16 39 40 From Host SPI CK From Host SPI DI a15 Y A14 a1 Y ao c7 Vee f es f 7 Y coy v From 654x SPI DO me sr ste sts f i emile f be Y D1 po f pel H D1 foo f d d SERIAL WRITE 16 bit Address 8 bit CMD Status Byte DATA ADDR DATA ADDR 1 Zeta Ee e EH AN 8 From Host SPI CSZ N i Extended Write 0 15 39 40 From Host SPI CK From Hos SPI DI x VAis A14 5 Y aa Y Ao D7 D6 f 01 Do fo fpe J 5 o1 oo Y x From 654x SPI DO WE ST7 Y ST6 X ST5 x n Y STO Figure 27 SPI Slave Port Typical Multi Byte Read and Write operations Table 63 SPI Command Sequences Command Sequence Description ADDR 1xxx xxxx STATUS Read data starting at ADDR ADDR auto increments until SPI CSZ is ByteO ByteN raised Upon completion SPI CMD SFR OxFD is updated to 1xxx xxxx and an SPI interrupt is generated The exception is if the command byte is 1000 0000 In this case no MPU interrupt is generated and SPI CMD is not updated Oxxx xxxx ADDR ByteO Write data starting at ADDR ADDR auto increments until SPI CSZ is ByteN raised Upon completion
51. O RAM 0x2409 LCD MAP 31 24 VO RAM 0x2408 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SEG Data Register LCD_SEGDIO16 5 0 to LCD_SEGDIO31 5 0 I O RAM 0x2420 5 0 to 0x242F 5 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DIO Data Register LCD_SEGDIO16 0 to LCD_SEGDIO31 0 VO RAM 0x2420 0 to 0x242F 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MU LCD SEGDIO16 1 to LCD SEGDIOSI1 1 SEH QO RAM 0x2420 1 to Ox242FT1 Table 54 Data Direction Registers for SEGDIO32 to SEGDIO45 71M6542F G SEGDIO 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin 7 3 2 100 99 98 97 96 95 94 0 1 2 3 4 5 7 0 1 2 3 4 5 Configuration 0 DIO 1 LCD LCD MAP 39 32 LCD MAP 45 40 i I O RAM 0x2407 VO RAM 0x2406 5 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SEG Data Register LCD_SEGDIO32 5 0 to LCD_SEGDIO45 5 0 VO RAM 0x2430 5 0 to 0x243D 5 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 DIO Data Register LCD_SEGDIO32 0 to LCD_SEGDIO45 0 VO RAM 0x2430 0 to 0x243D 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 PAs ict pee eae LCD_SEGDIO32 1 to LCD_SEGDIO45 1 Gel O RAM 0x2430 1 to 0x243D 1 Table 55 Data Direction Registers for SEGDIO51 to SEGDIO55 71M6542F G SEGDIO 51 52 53 54 55 Pin 53 52 5
52. R this byte wil be locked out while it is one Write duration could be as long as 6ms Sets the period between temperature measurements Automatic measurements can be enabled in any mode MSN BRN LCD or SLP TEMP_PER 0 disables automatic temperature updates in which case TEMP_START may be used by the MPU to initiate a one shot temperature measurement 0 No temperature updates 16 2 TEMP PER 7 Continuous updates Selects the power source for the temp sensor TEMP_PWR 28A0 6 0 RW 1 V3P3D 0 VBAT RTC This bit is ignored in SLP and LCD modes where the temp sensor is always powered by VBAT_RTC When TEMP_PER 0 automatic temperature measurements are disabled and TEMP_START may be set by the MPU to initiate a one shot temperature SHEN START 28B4I6 0 0 RW measurement TEMP START is ignored in SLP and LCD modes Hardware clears TEMP START when the temperature measurement is complete TMUX 5 0 2502 5 0 RW Selects one of 32 signals for TMUXOUT See 2 5 12 for details TMUX2 4 0 2503 4 0 RW Selects one of 32 signals for TMUX2OUT See 2 5 12 for details TMUXRA 2 0 210A 2 0 000000 R W The TMUX setting for the remote isolated sensor 71M6x01 The silicon version index This word may be read by firmware to determine the silicon version VERSION 7 0 2706 7 0 R VERSION 7 0 Silicon Version 0001 0011 B01 0010 0010 B02 Brings the ADC reference voltage out to the VREF pin This feature is disabled VRE
53. RAM 0x24 would be 80 Vrms SQRT 2 SAG THR ss where SAG THR ss is the LSB value in the description of SAG_THR see Table 84 Rev 2 125 71M6541D F G and 71M6542F G Data Sheet The parameters EQU 2 0 I O RAM 0x2106 7 5 CE E I O RAM 0x2106 0 and SUM SAMPS 12 0 are essential to the function of the CE are stored in I O RAM see 5 2 I O RAM Map Alphabetical Order for details 5 3 4 Environment Before starting the CE using the CE E bit I O RAM 0x2106 0 the MPU has to establish the proper environment for the CE by implementing the following steps e Locate the CE code in Flash memory using CE LCTN 5 0 I O RAM 0x2109 5 0 e Load the CE data into RAM e Establish the equation to be applied in EQU 2 0 I O RAM 0x2106 7 5 e Establish the number of samples per accumulation period in SUM SAMPS 12 0 I O RAM 0x2107 4 0 0x2108 7 0 e Establish the number of cycles per ADC multiplexer frame MUX DIV 3 0 I O RAM 0x2100 7 4 e Apply proper values to MUXn SEL as well as proper selections for DIFFn E I O RAM 0x210C 5 4 and RMT E I O RAM 0x2709 3 in order to configure the analog inputs e initialize any MPU interrupts such as CE BUSY XFER BUSY or the power failure detection interrupt e VMAX 600 V IMAX 707 A and kH 1 Wh pulse are assumed as default settings When different CE codes are used a different set of environment parameters need to be established The exact values for these parameters a
54. RTMO 7 0 210E 7 0 olo Four RTM probes Before each CE code pass the values of these registers are serially output on the RTM pin The RTM registers are ignored when RTM1 7 0 210F 7 0 0 0 RW d i SUP RTMDOI7 0 2110 70 olo RTM E 0 Note that RTMO is 10 bits wide The others assume the upper 7 0 7 0 two bits are 00 RTM3 7 0 2111 7 0 0 0 Inhibits erasure of page 0 and flash addresses above the beginning of CE code SECURE SFR B2 6 0 0 RW Jas defined by CE LCTN 5 0 Also inhibits the read of flash via the SPI and ICE port Puts the part to SLP mode Ignored if system power is present The part SLEEP 28B2 7 0 0 W wakes when the Wake timer times out when push button is pushed or when system power returns SPI CMD 7 0 SFR FD 7 0 R SPI command register for the 8 bit command from the bus master SPI port enable Enables SPI interface on pins SEGDIO36 SEGDIO39 SPIE 270C 4 1 1 RW Requires that LCD_MAP 36 39 0 SPI SAFE 270C 3 o lol Rw Limits SPI writes to SPI CMD and a 16 byte region in DRAM No other writes are permitted SPI STAT contains the status results from the previous SPI transaction Bit 7 Ready error The 71M654x was not ready to read or write as directed by the previous command Bit 6 Read data parity This bit is the parity of all bytes read from the 71M654x in the previous command Does not include the SPI STAT byte Bit 5 Write data parity This bit is the overall parity of the bytes written to
55. YPULSE 2 pins o SEGDIO8 DI 1 pin o SEGDIO26 COM5 SEGDIO27 COM4 2 pins o SEGDIO36 SPI_CSZ SEGDIO39 SPI_CKI 4 pins o SEGDIO51 OPT_TX SEGDIO55 OPT_RX 2 pins 5 dedicated SEG segment pins are available o ICE Inteface pins SEG48 E_RXTX SEG49 E_TCLK SEG50 E_RST 3 pins o Test Port pins SEG46 TMUX2OUT SEG47 TMUXOUT 2 pins There are four dedicated common segment outputs COMO COM3 plus the two additional shared common segment outputs that are listed under combined SEG DIO shared pins SEGDIO26 COMB SEGDIO27 COMA Thus in a configuration where none of these pins are used as DIOs there can be up to 55 LCD segment pins with 4 commons or 53 LCD segment pins with 6 commons And in a configuration where LCD segment pins are not used there can be up to 50 DIO pins Example SEGDIO12 see pin 32 in Table 52 is configured as a DIO output pin with a value of 1 high by writing O to bit 4 of LCD MAP 15 8 and writing 1 to both P3 4 and P3 0 The same pin is configured as an LCD driver by writing 1 to bit 4 of LCD MAP 15 8 The display information is written to bits O to 5 of LCD SEGI12 The configuration for pins SEGDIO16 to SEGDIO31 is shown in Table 53 the configuration for pins SEGDIO32 to SEGDIO45 is shown in Table 54 SEG46 through SEG50 cannot be configured as DIO pins The configuration for pins SEGDIO51 to SEGDIO55 is shown in Table 55 Table 52 Data Direction Registers for SEGDIOO to SEGDIO15 71M6542F G
56. address as shown in Table 38 Once the interrupt service has begun it can be interrupted only by a higher priority interrupt The interrupt service is terminated by a return from interrupt instruction RETI When a RETI instruction is performed the processor returns to the instruction that would have been next when the interrupt occurred When the interrupt condition occurs the processor also indicates this by setting a flag bit This bit is set regardless of whether the interrupt is enabled or disabled Each interrupt flag is sampled once per machine cycle and then samples are polled by the hardware If the sample indicates a pending interrupt when the interrupt is enabled then the interrupt request flag is set On the next instruction cycle the interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address if the following conditions are met e No interrupt of equal or higher priority is already in progress e Aninstruction is currently being executed and is not completed e The instruction in progress is not RETI or any write access to the registers IENO IEN1 IEN2 IPO or IP1 Special Function Registers for Interrupts The following SFR registers control the interrupt functions e The interrupt enable registers IENO IEN1 and IEN2 see Table 26 Table 27 and Table 28 e The Timer Counter control registers TCON and T2CON see e Table 29 and Table 30 e The interrupt request register IRCON see Table 31
57. awakened at a regular rate set by TEMP PER 2 0 I O RAM 0x28A0 2 0 The result of the temperature measurement can be read from the two I O RAM locations STEMP 10 3 I O RAM 0x2881 and STEMP 2 0 I O RAM 0x2882 7 5 Note that both of these I O RAM locations must be read and properly combined to form the STEMP 10 0 11 bit value see STEMP in Table 46 The resulting 11 bit value is in 2s complement form and ranges from 1024 to 1023 decimal The equations below are used to calculate the sensed temperature from the 11 bit STEMP 10 0 reading The equations below are used to calculate the sensed temperature The first equation applies when the 71M654x is in MSN mode and TEMP PWR 1 The second equation applies when the 71M654x is in BRN mode and in this case the TEMP PWR and TEMP BSEL bits must both be set to the same value so that the battery that supplies the temperature sensor is also the battery that is measured and reported in BSENSE Thus the second equation requires reading STEMP and BSENSE In the second equation BSENSE the sensed battery voltage is used to obtain a more accurate temperature reading when the IC is in BRN mode For the 71M654x in MSN Mode with TEMP PWR 1 Temp C 0 325 STEMP 22 For the 71M654x in BRN Mode with TEMP_PWR TEMP_BSEL Temp C 0 325 STEMP 0 00218 BSENSE 0 609 BSENSE 64 4 Table 46 shows the I O RAM registers used for temperature and battery measurement If TEMP_PWR sele
58. compiler directive MODC2 dual data pointers are enabled in certain library routines 32 Rev 2 71M6541D F G and 71M6542F G Data Sheet An alternative data pointer is available in the form of the PDATA register SFR OxBF sometimes referred to as USR2 It defines the high byte of a 16 bit address when reading or writing XDATA with the instruction MOVX A Ri or MOVX Ri A Internal Data Memory Map and Access The Internal data memory provides 256 bytes 0x00 to OxFF of data memory The internal data memory address is always 1 byte wide Table 11 shows the internal data memory map The Special Function Registers SFR occupy the upper 128 bytes The SFR area of internal data memory is available only by direct addressing Indirect addressing of this area accesses the upper 128 bytes of Internal RAM The lower 128 bytes contain working registers and bit addressable memory The lower 32 bytes form four banks of eight registers RO R7 Two bits on the program memory status word PSW SFR OxDO select which bank is in use The next 16 bytes form a block of bit addressable memory space at addresses 0x00 0x7F All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing Table 11 Internal Data Memory Map Address Range Direct Addressing Indirect Addressing 0x80 OxFF Special Function Registers SFRs RAM 0x30 Ox7F Byte addressable area 0x20 Ox2F Bit addressable area 0x00 Ox1F Re
59. document For instance EQU 2 0 can be accessed at I O RAM 0x2000 7 5 or at I O RAM 0x2106 7 5 Table 74 I O RAM Map Functional Order Basic Configuration Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CE6 2000 EQU 2 0 U CHOP_E 1 0 RTM E CE E CE5 2001 U SUM SAMPS 12 8 CEA 2002 SUM SAMPS 7 0 CE3 2003 U U CE_LCTN 5 0 CE2 2004 PLS MAXWIDTH 7 0 CE1 2005 PLS INTERVAL 7 0 CEO 2006 R R DIFFB E DIFFA E RFLY DIS FIR LEN 1 0 PLS INV RCEO 2007 CHOPR 1 0 R R RMT E R R R RTMUX 2008 U TMUXRB 2 0 U TMUXRA 2 0 Reserved 2009 U U R U U U U U MUX5 200A MUX DIV 3 0 MUXI10 SEL MUX4 200B MUX9_SEL MUX8_SEL MUX3 200C MUX7_SEL MUX6_SEL MUX2 200D MUX5_SEL MUXA SEL MUX1 200E MUXS3 SEL MUX2 SEL MUXO 200F MUXI1 SEL MUXO SEL TEMP 2010 TEMP BSEL TEMP PWR OSC COMP TEMP BAT TBYTE BUSY TEMP PER 2 0 LCDO 2011 LCD E LCD MODE 2 0 LCD ALLCOM LCD Y LCD CLK 1 0 LCD1 2012 LCD VMODE 1 0 LCD BLNKMAP23 5 0 LCD2 2013 LCD BAT R LCD BLNKMAP22 5 0 LCD MAP6 2014 LCD MAP 55 48 Rev 2 105 71M6541D F G and 71M6542F G Data Sheet SFMM and SFMS are accessible only through the SPI slave port See Invoking SFM page 77 for details t 71M6542F G only Nam
60. e The interrupt priority registers IPO and IP1 see Table 36 Table 26 The IENO Bit Functions SFR 0xA8 Bit Symbol Function IENO 7 EAL EAL 0 disables all interrupts IENO 6 WDT Not used for interrupt control IENO 5 Not Used IENO 4 ESO ESO 0 disables serial channel 0 interrupt IENO 3 ET ET1 0 disables timer 1 overflow interrupt IENO 2 EX1 EX1 0 disables external interrupt 1 DIO status change IENO 1 ETO ETO 0 disables timer O overflow interrupt IENO O EX0 EXO0 0 disables external interrupt 0 DIO status change Table 27 The IEN1 Bit Functions SFR 0xB8 Bit Symbol Function IEN1 7 Not used IEN1 6 Not used IEN1 5 EX6 EX6 0 disables external interrupt 6 XFER BUSY RTC 1S RTC 1M or RTC T IEN1 4 EX5 EX5 0 disables external interrupt 5 EEPROM or SPI IEN1 3 EX4 EX4 0 disables external interrupt 4 VSTAT Rev 2 41 71M6541D F G and 71M6542F G Data Sheet IEN1 2 EX3 EX3 0 disables external interrupt 3 CE_BUSY IEN1 1 EX2 EX2 0 disables external interrupt 2 XPULSE YPULSE WPULSE or VPULSE IEN1 0 Not Used Table 28 The IEN2 Bit Functions SFR 0x9A Bit Symbol Function IEN2 0 ES1 ES1 0 disables the serial channel 1 interrupt Table 29 TCON Bit Functions SFR 0x88 Bit
61. essi routinier sirenenet a aaa Iu a edad 152 ETC lee te 152 71M6541 Package Markings AEN 155 K ee EE LA Lu Le EE 155 Power and Gro nd PIPDS 22 2 22 2 22 ret ER tetany Ur EC OO E PO eeii ely 158 ing SAIT 159 Digital PINS isi one Ee Eee EDO EHE Era EE EE EN RE RR ERE FERE ERR FERE ERE CEN e nada 160 Ordering Information eoo eerte cer ent Re ct Ere e E P Pec e Eo aee a e ete ta 163 Rev 2 71M6541D F G and 71M6542F G Data Sheet VREF V3P3A GNDA GNDD VLCD V3P3SYS IAP AX IAN AD CONVERTER IBP IBN VLCD Voltage Boost vaP3D VA VB VBAT UX MUX CTRL Voltage Regulator I CK32 xiN Oscillator RTCLK 32KHz XouT 32 KHz VDD v 2 5V to logic CLOCK GEN CK 4X LCD GEN CKMPU_2x MPU RAM MEMORY SHARE MUX_SYNC WIBE 3l5 KB CKCE VARPULSE n JP 4 9MHz RTM LCD DRIVER 32 bit Compute TEST Engine CE CONTROL Ge 32 m 82 0x00 ox2FF COMo 5 0x0000 0x13FF n A SEG Pins PROG 0x000 0x3FF S A SEGDIO Pins DIGITAL UO 16 WPULSE gt gt
62. lt n o 1 57MHz from PLL 1 57MHz from PLL e Yes e e e e Yes Y Yes Yes Yes 38 4kHz 38 9kHz Y e e Y e Yes Yes Yes Yes Yes Yes es Yes n o bd o lt n o Y Y Y Y n o lt n o lt o n o lt o lt bd 7 Kg lt 2 lt bd 7 lt bd 2 o o o o o lt n o o lt n o 38 9kHz n lt gt Kg i Kg 2 lt gt n 7 lt bd 7 lt 7 lt 2 lt lt o o o o bd c bd bd o o o0 o Ii o lt n o i bd o n n d lt n 7 lt bd 7 lt bd 7 lt bd 2 The CE is active in BRN mode but ADC data is inaccurate The MPU should halt the CE to conserve power CE E 0 I O RAM 0x2106 0 indicates that the corresponding circuit is not active Boost implies that the LCD boost circuit is active i e LCD VMODET 1 0 10 I O RAM 0x2401 7 6 The LCD boost circuit requires a clock from the PLL to function Thus the PLL is automatically kept active if LCD boost is active while in LCD mode otherwise the PLL is de activated 82 Rev 2 71M6541D F G and 71M6542F G Data Sheet 3 2 1 BRN Mode In BRN mode most non metering digital functions are active as shown in Table 67 including ICE UART EEPROM LCD and RTC In BRN mode the PLL continues to function at the same frequency as MSN mode It is up to the MPU to scale down t
63. make use of auto increment and may access single bytes The command byte must always be of the form 1xxx xxxx in SFM read transactions SPI commands in SFM Interrupts are not generated in SFM since the MPU is halted The format of the commands is described in the SPI Transactions description on Page 73 2 5 11 Hardware Watchdog Timer An independent robust fixed duration watchdog timer WDT is included in the 71M6541D F G and 71M6542F G It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1 5 seconds When not refreshed on time the WDT overflows and the part is reset as if the RESET pin were pulled high except that the I O RAM bits are in the same state as after a wake up from SLP or LCD modes see the I O RAM description in 5 2 I O RAM Map Alphabetical Order for a list of I O RAM bit states after RESET and wake up After 4100 CK32 cycles or 125 ms following the WDT overflow the MPU is launched from program address 0x0000 The watchdog timer is also reset when the internal signal WAKE 0 see 3 4 Wake Up Behavior For details see 3 3 4 Watchdog Timer Reset 2 5 12 Test Ports TMHUXOUT and TMUX2OUT Pins Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT and TMUX2OUT pins These pins are multiplexed with the SEG47 and SEG46 function In order to function as test pins LCD MAP 46 I O RAM 0x2406 6 and LCD MAP 47 I O
64. memory However the 71M6541D F G and 71M6542F G contain a Special Flash Mode SFM that facilitates initial production programming of the flash memory When the 71M654x is in SFM mode the SPI interface can erase read and write the flash Other memory elements such as XRAM and I O RAM are not accessible to the SPI in this mode In order to protect the flash contents several operations are required before the SFM mode is successfully invoked Details on the SFM are in 2 5 10 SPI Slave Port Rev 2 49 71M6541D F G and 71M6542F G Data Sheet 2 5 1 2 MPU CE RAM The 71M6541D includes 3 KB of static RAM memory on chip XRAM plus 256 bytes of internal RAM in the MPU core The 71M6541D F G and the 71M6542F G include 5 KB of static RAM memory on chip XRAM plus 256 bytes of internal RAM in the MPU core The static RAM is used for data storage for both MPU and CE operations 2 5 1 3 I O RAM Configuration RAM The I O RAM can be seen as a series of hardware registers that control basic hardware functions UO RAM address space starts at 0x2000 The registers of the I O RAM are listed in Table 74 The 71M6541D F G and 71M6542F G include 128 bytes non volatile RAM memory on chip in the I O RAM address space addresses 0x2800 to 0x287F This memory section is supported by the voltage applied at VBAT_RTC and the data in it are preserved in BRN LCD and SLP modes as long as the voltage at VBAT_RTC is within specification 2 5 2 Oscillat
65. modes where the temperature sensor is always powered by VBAT RTC Selects which battery is monitored by the temperature sensor 1 VBAT 0 VBAT RTC Test bits for the temperature monitor VCO TEMP TEST must be 00 in regular operation Any other value causes the VCO to run continuously with the control voltage described below TEMP BAT 28A0 4 o RW TEMP_START 28B4 6 0 RW TEMP_PWR 28406 O RW TEMP_BSEL 28A0 7 0 RW TEMP_TEST 1 0 2500 1 0 0 RW TEMP_TEST Function 00 Normal operation 01 Reserved for factory test 1X Reserved for factory test STEMP 10 3 2881 7 0 R The result of the temperature measurement STEMP 2 0 2882 7 5 R To correctly form STEMP 10 0 the MPU must read 0x2881 7 0 shift it left by three bit positions padding LSBs with zeros then read 0x2882 7 5 shift it right by 5 bits padding the 5 MSBs with zeros and then logically OR the two quantities together BSENSE 7 0 2885 7 0 R The result of the battery measurement Connects a 100 pA load to the battery selected by BCURR 2704 3 0 D RAW TEMP BSEL Refer to the 71M6xxx Data Sheet for information on reading the temperature sensor in the 71M6x01 devices 2 5 6 71M654x Battery Monitor The 71M654x temperature measurement circuit can also monitor the batteries at the VBAT and VBAT RTC pins The battery to be tested e VBA
66. processor at up to 38 400 bits s with MPU clock 1 2288 MHz The operation of the RX and TX UARTO pins is as follows 36 Rev 2 71M6541D F G and 71M6542F G Data Sheet e UARTO RX Serial input data are applied at this pin Conforming to RS 232 standard the bytes are input LSB first e UARTO TX This pin is used to output the serial data The bytes are output LSB first Several UART related registers are available for the control and buffering of serial data A single SFR register serves as both the transmit buffer and receive buffer SOBUF SFR 0x99 for UARTO and S1BUF SFR 0x9C for UART1 When written by the MPU SxBUF acts as the transmit buffer and when read by the MPU it acts as the receive buffer Writing data to the transmit buffer starts the transmission by the associated UART Received data are available by reading from the receive buffer Both UARTs can simultaneously transmit and receive data WDCON 7 SFR 0xD8 selects whether timer 1 or the internal baud rate generator is used All UART transfers are programmable for parity enable parity 2 stop bits 1 stop bit and XON XOFF options for variable communication baud rates from 300 to 38400 bps Table 17 shows how the baud rates are calculated Table 18 shows the selectable UART operation modes Table 17 Baud Rate Generation Using Timer 1 Using Internal Baud Rate Generator WDCON 7 0 WDCON 7 1 UARTO 254 foxmpul 384 256 TH1 257
67. security feature limits the ICE to global flash erase operations only All other ICE operations are blocked This guarantees the security of the user s MPU and CE program code Security is enabled by MPU code that is executed in a 64 CKMPU cycle pre boot interval before the primary boot sequence begins Once security is enabled the only way to disable it is to perform a global erase of the flash followed by a chip reset The first 64 cycles of the MPU boot code are called the pre boot phase because during this phase the ICE is inhibited A read only status bit PREBOOT SFR 0xB2 7 identifies these cycles to the MPU Upon completion of pre boot the ICE can be enabled and is permitted to take control of the MPU The security enable bit SECURE SFR 0xB2 6 is reset whenever the chip is reset Hardware associated with the bit permits only ones to be written to it Thus pre boot code may set SECURE to enable the security feature but may not reset it Once SECURE is set the pre boot code is protected and no external read of program code is possible Specifically when the SECURE bit is set the following applies e The ICE is limited to bulk flash erase only e Page zero of flash memory the preferred location for the user s pre boot code may not be page erased by either MPU or ICE Page zero may only be erased with global flash erase e Write operations to page zero whether by MPU or ICE are inhibited The 71M6541D F G and 71M6542F G al
68. serial interface communicates with external EEPROM devices and is intended for use with I C devices The interface is multiplexed onto the SEGDIO2 SDCK and SEGDIO3 SDATA pins and is selected by setting DIO EEX 1 0 01 I O RAM 0x2456 7 6 The MPU communicates with the interface through the SFR registers EEDATA and EECTRL If the MPU wishes to write a byte of data to the EEPROM it places the data in EEDATA and then writes the Transmit code to EECTRL This initiates the transmit operation which is finished when the BUSY bit falls INT5 is also asserted when BUSY falls The MPU can then check the RX ACK bit to see if the EEPROM acknowledged the trans mission A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall Upon completion the received data is in EEDATA The serial transmit and receive clock is 78 kHz during each transmission and then holds in a high state until the next transmission The EECTRL bits when the two pin interface is selected are shown in Table 60 70 Rev 2 71M6541D F G and 71M6542F G Data Sheet Table 60 EECTRL Bits for 2 pin Interface Status Read Reset m Bit Name Write State Polarity Description 7 ERROR R 0 Positive 1 when an illegal command is received 6 BUSY R 0 Positive 1 when serial data bus is busy 5 RX ACK R 1 Positive 1 indicates that the EEPROM sent an ACK bit Ge 1 indicates that an ACK bit has been sent to the 4 TX ACK R
69. the LCD mode when LCD BSTE 1 Current dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated directly from VBAT The LCD DAC uses a low power reference and within the constraints of VBAT and the voltage doubler generates a VLCD voltage of 2 5 VDC 2 5 LCD DACT 4 0 31 The LCD BAT bit I O RAM 0x2402 7 causes the LCD system to use the battery voltage in all power modes This may be useful when an external supply is available for the LCD system The advantage of connecting the external supply to VBAT rather than VLCD is that the LCD DAC is still active If LCD EXT 1 the VLCD pin must be driven from an external source In this case the LCD DAC has no effect Rev 2 65 71M6541D F G and 71M6542F G Data Sheet The LCD system has the ability to drive up to six segments per SEG driver If the display is configured with Six back planes the 6 way multiplexing compresses the number of SEG pins required to drive a display and therefore enhance the number of DIO pins available to the application Refer to the LCD MODE 2 0 field I O RAM 0x2400 6 4 settings Table 57 for the different LCD multiplexing choices If 5 state multiplexing is selected SEGDIO27 is converted to COMA If 6 state multiplexing is selected SEGDIO26 is converted to COM5 These conversions override the SEG DIO mapping of SEGDIO26 and SEGDIO27 Additionally independent of LCD MODE 2 0 if LCD ALLCOM 1 then SE
70. the MOVX A Ri instruction Internal and External Memory Map Table 10 shows the address type use and size of the various memory components Table 10 Memory Map Address Memory Memory Name Typical Usage Memory Size hex Technology Type yp H bytes Program memory TOLL Modus Geier 0000 7FFF Flash Memory Non volatile for MPU and CE CE program on 1 3 KB max KB boundary External RAM Shared by CE and 0000 0BFF Static RAM Volatile XRAM MPU 5 3 KB t Configuration 2000 27FF Static RAM Volatile RAM I O RAM Hardware control 2KB Non volatile Configuration Battery buffered 2800 287F Static RAM battery RAM I O RAM memory 128 0000 00FF Static RAM Volatile Internal RAM Part of 80515 Core 256 t Memory size depends on IC See 2 5 1 Physical Memory for details MOVX Addressing There are two types of instructions differing in whether they provide an 8 bit or 16 bit indirect address to the external data RAM In the first type MOVX A Ri the contents of RO or R1 in the current register bank provide the eight lower ordered bits of address The eight high ordered bits of the address are specified with the PDATA SFR This method allows the user paged access 256 pages of 256 bytes each to all ranges of the external data RAM In the second type of MOVX instruction MOVX A DPTR the data pointer generates a 16 bit address This form is faster and more efficient when accessing v
71. the SFMS I O RAM 0x2081 register This action invokes SFM provided that the previous write operation to SFMM met the requirements Writing any other pattern to this register does not invoke SFM Additionally any write operations to this register automatically reset the previously written SFMM register values to zero Rev 2 77 71M6541D F G and 71M6542F G Data Sheet SFM details The following occurs upon entering SFM e The CE is disabled e The MPU is halted Once the MPU is halted it can only be restarted with a reset This reset can be accomplished with the RESET pin a watchdog reset or by cycling power without battery at the VBAT pin e The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase cycle e Mass erase is invoked if specified in the SFMM register I O RAM 0x2080 see Invoking SFM above The SECURE bit SFR 0xB2 6 is cleared at the end of this and all Mass Erase cycles e All SPI read and write operations now refer to Flash instead of XRAM space The SPI host can access the current state of the pending multi cycle Flash access by performing a 4 byte SPI write of any address and checking the status field All SPI write operations in SFM mode must be 6 byte write transaction that writes two bytes to an even address The write transactions must contain a command byte of the form Oxxx xxxx Auto incrementing is disabled for write operations SPI read transactions can
72. the VA voltage sensor is available in both the 71M6541D F G and 71M6542F G and is directly connected to the 71M654x The VB voltage sensor is available only in the 71M6542F G and is also directly connected to it Thus the precision of these directly connected voltage sensors is affected by VREF in the 71M654x The 71M654x also has one shunt current sensor IA which is connected directly to it and therefore is also affected by the VREF in the 71M654x The external current sensor and its corresponding signal conditioning circuit also has a temperature dependency which also may require compensation depending on the required accuracy class Finally the second current sensor IB is isolated by the 71M6x01 and depends on the VREF of the 71M6x01 plus the variation of the corresponding shunt resistance with temperature The MPU has the responsibility of computing the necessary compensation values required for each sensor channel based on the sensed temperature Teridian provides demonstration code that implements the GAIN ADJn compensation equation shown below The resulting GAIN ADJn values are stored by the MPU in three CE RAM locations GAIN ADJO GAIN ADJ2 CE RAM 0x40 0x42 The demonstration code thus provides a suitable implementation of temperature compensation but other methods are possible in MPU firmware by utilizing the on chip temperature sensors and the CE RAM GAIN ADJn storage locations The demonstration code maintains three separate sets o
73. the voltage samples through the all pass filter thus delaying the voltage samples by 360 6 resulting in the residual phase error between the current and its corresponding voltage of 0 d The residual phase error is negligible and is typically less than 1 5 milli degrees at 100Hz thus it does not contribute to errors in the energy measurements When using remote sensors the CE performs the same delay compensation described above to align each voltage sample with its corresponding current sample Even though the remote current samples do not pass through the 71M654x multiplexer their timing relationship to their corresponding voltages is fixed and precisely known provided that the MUXn SEL 3 0 slot assignment fields are programmed as shown in Table 1 and Table 2 2 2 4 ADC Pre Amplifier The ADC pre amplifier is a low noise differential amplifier with a fixed gain of 8 available only on the IAP IAN sensor input pins A gain of 8 is enabled by setting PRE_E 1 I O RAM 0x2704 5 When disabled the supply current of the pre amplifier is 10 nA and the gain is unity With proper settings of the PRE E and DIFFA E I O RAM 0x210C 4 bits the pre amplifier can be used whether differential mode is selected or not For best performance the differential mode is recommended In order to save power the bias current of the pre amplifier and ADC is adjusted according to the ADC_DIV control bit I O RAM 0x2200 5 2 2 5 A D Converter ADC
74. to Four Pulse Outputs with Pulse Count e Four Quadrant Metering e Digital Temperature Compensation Metrology Compensation Accurate RTC for TOU Functions with Automatic Temperature Compensation for Crystal in All Power Modes e Independent 32 Bit Compute Engine e 46 64Hz Line Frequency Range with the Same Calibration e Phase Compensation 10 e Three Battery Backup Modes Brownout Mode BRN LCD Mode LCD Sleep Mode SLP e Wake Up on Pin Events and Wake On Timer e 1pA in Sleep Mode e Flash Security e In System Program Update e 8 Bit MPU 80515 Up to 5 MIPS e Full Speed MPU Clock in Brownout Mode e LCD Driver Up to 6 Commons Up to 56 Pins e 5V LCD Driver with DAC e Up to 51 Multifunction DIO Pins e Hardware Watchdog Timer WDT e l C IMICROWIREG EEPROM Interface e SPI Interface with Flash Program Capability e Two UARTS for IR and AMR e IR LED Driver with Modulation e Industrial Temperature Range e 64 Pin 71M6541D F G and 100 pin 71M6542F G Lead Pb Free LQFP Package Rev 2 71M6541D F G and 71M6542F G Data Sheet Table of Contents 1 Introduction EE 10 2 Hardware Description eeeeceeeeeeereee eee nun nn nra n anna nnnnnnnn nn nna enar mnnn n nnmnnn ennnen 11 2 1 Elo Ee EE 11 2 2 gt Analog FrontEnd ABE E E E 12 E Bett Nino r DI EE 14 2 2 2 JEE MultipleXer eee eee ee ee Ti 15 2 2 3 Delay eelere e BEE 19 2 2 4 ADE Gul E ER 20 2 2 5 AJD Gonv
75. writing a 1 into the LKP RD bit I O RAM 0x2889 1 The process of reading from and writing to the NV RAM is accelerated by setting the LKPAUTOI bit I O RAM 0x2887 7 When LKPAUTOI is set LKPADDR 6 0 auto incremented every time LKP RD or LKP WR is pulsed It is also possible to perform random access of the NV RAM by writing a O to the LKPAUTOI bit and loading the desired address into LKPADDR 6 0 If the oscillator temperature compensation feature is not being used it is possible to use the NV RAM storage area as ordinary NV storage space using the procedure described above to read and write NV RAM data In this case keep the OSC_COMP bit I O RAM 0x28A0 5 reset to disable the automatic oscillator temperature compensation feature 2 5 4 5 RTC Interrupts The RTC generates interrupts each second and each minute These interrupts are called RTC_1SEC and RTC 1MIN In addition the RTC functions as an alarm clock by generating an interrupt when the minutes and hours registers both equal their respective target counts as defined in Table 45 The alarm clock interrupt is called RTC T All three interrupts appear in the MPU s external interrupt 6 See Table 33 in the interrupt section for the enable bits and flags for these interrupts The target registers for minutes and hours are listed in Table 45 Table 45 I O RAM Registers for RTC Interrupts Name Location Rst Wk Dir Description RTC TMIN 5 0 289E b 0 O O RW The target minu
76. 0 I O RAM 0x210B 7 0 controls the delay to the first pulse update and the interval between subsequent updates The LSB of the PLS INTERVAL 7 0 register is equivalent to 4 CK FIR cycles CK FIR is typically 4 9152MHz if PLL FAST 1 and ADC_DIV 0 but other CK FIR frequencies are possible see the ADC DIV definition in Table 76 If PLS INTERVAL 7 0 0 the FIFO is deactivated and the pulse outputs are updated immediately The MUX frame duration in units of CK FIR clock cycles is given by If PLL_FAST 1 MUX frame duration in CK FIR cycles 1 FIR LEN 1 ADC_DIV 1 MUX DIV 150 ADC_DIV 1 If PLL_FAST 0 MUX frame duration in CK FIR cycles 3 3 FIR_LEN 1 ADC_DIV 1 MUX_DIV 48 ADC_DIV 1 PLS_INTERVAL 7 0 in units of CK_FIR clock cycles is calculated by PLS INTERVAL 7 0 floor Mux frame duration in CK FIR cycles CE pulse updates per Mux frame 4 Since the FIFO resets at the beginning of each multiplexer frame the user must specify PLS_INTERVAL 7 0 so that all of the possible pulse updates occurring in one CE execution are output before the multiplexer frame completes For instance the 71M654x CE code outputs six updates per multiplexer interval and if the multiplexer interval is 1950 CK_FIR clock cycles long the ideal value for the interval is 1950 6 4 81 25 However if PLS_INTERVAL 7 0 82 the sixth output occurs too late and would be lost In this case the proper value for PLS INTERVAL 7
77. 0 is 81 i e round down the result Since one LSB of PLS INTERVAL 7 0 is equal to 4 CK FIR clock cycles the pulse time interval T in units of CK FIR clock cycles is T 4 PLS INTERVAL 7 0 Rev 2 27 71M6541D F G and 71M6542F G Data Sheet If the FIFO is enabled e PLS INTERVAL 7 0 0 hardware also provides a maximum pulse width feature in control register PLS_MAXWIDTH 7 0 I O RAM 0x210A By default WPULSE and VPULSE are negative pulses e low level pulses designed to sink current through an LED DLS MAXWIDTH 7 0 determines the maximum negative pulse width Tmax in units of CK FIR clock cycles based on the pulse interval T according to the formula Tmax 2 PLS MAXWIDTH 7 0 1 T If PLS MAXWIDTH 255 or PLS INTERVAL O no pulse width checking is performed and the pulses default to 5096 duty cycle Tmax is typically programmed to 10 ms which works well with most calibration systems The polarity of the pulses may be inverted with the control bit PLS_INV I O RAM 0x210C 0 When PLS INV is set the pulses are active high The default value for PLS INV is zero which selects active low pulses The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIOO WPULSE and SEGDIO1 VPULSE respectively pins 45 and 44 The pulses can also be output on OPT TX pin 53 see OPT TXE 1 0 I O RAM 0x2456 3 2 for details ADC MUX Frame MUX_DIV Conversions MUX DIV 4 is shown ple Se
78. 01 When set the power pulse is driven high and low When cleared it is driven high followed by an open circuit fly back interval 120 Rev 2 71M6541D F G and 71M6542F G Data Sheet Name Location RstWk Dir Description Enables the remote digital isolation interface which transforms the IBP IBN RMT_E 2709 3 0 0 RW pins into a digital balanced differential pair Thus enabling these pins to interface to the 71M6x01 isolated sensor RMT_RD 15 8 2602 7 0 RMT RD 7 0 2603 7 0 0 0 R Response from remote read request Indicates that a count error has occurred in the RTC and that the time is not esu RDUM Si eos trustworthy This bit can be cleared by writing a O RTC_P 16 14 289B 2 0 4 4 RTC adjust See 2 5 4 Real Time Clock RTC RTC P 13 6 289C 7 0 O O R W OxOFFBF x RTC P x Ox10040 RTC P 5 0 289D 7 2 0 0 Note RTC_P 16 0 and RTC Q 1 0 form a single 19 bit RTC adjustment value RTC adjust See 2 5 4 Real Time Clock RTC Bre Ono er SE E Note RTC P 16 0 and RTC Q 1 0 form a single 19 bit RTC adjustment value Freezes the RTC shadow register so it is suitable for MPU reads When RTC RD 2890 6 O O RW RTC_RD is read it returns the status of the shadow register O up to date 1 frozen RTC SBSC 7 0 2892 7 0 R Time remaining until the next 1 second boundary LSB 1 256 second RTC TMIN 5 0 289E 5 0 O R W The target minutes register See
79. 0x40000 Figure 17 Automatic Temperature Compensation The 128 NV RAM locations are organized in 2 s complement format as shown in Table 44 As mentioned above the STEMP 10 0 digital temperature values are scaled such that the corresponding NV RAM addresses are equal to STEMP 10 0 4 limited in the range of 64 to 63 See 2 5 5 71M654x Temperature Sensor on page 56 for the equations to calculate temperature in degrees C from the STEMP 10 0 reading The temperature equation is used to calculate the two temperature columns in Table 44 the second column and the rightmost column The second column uses the full 11 bit values of STEMP 10 0 while the values in the rightmost column are calculated using the post limiter 6 S values multiplied by 4 Since each look up table address step corresponds to a 4 x 0 325 C temperature step two is added to the post limiter 6 S value after multiplying by 4 to calculate the temperature values in the rightmost column This method ensures that the compensation data is loaded into the look up table in a manner that minimizes quantization error Table 44 shows the numerical values corresponding to each node in Figure 17 The values of STEMP 10 0 outside the 256 to 255 range are not shown in this table The limiter output is confined to the range of 64 to 63 which is directly the desired address of the 128 byte look up table The rightmost column gives the nominal temperature corresponding to each address cel
80. 1 47 46 Configuration ey ee ca ek of O RAM 0x2405 7 3 51 52 53 54 55 SEG Data Register LCD_SEGDIO51 5 0 to LCD_SEGDIO55 5 0 VO RAM 0x2443 5 0 to 0x2447 5 0 51 52 53 54 55 DIO Data Register LCD SEGDIO51 0 to LCD SEGDIOS55 0 VO RAM 0x2443 0 to 0x2447 0 51 52 53 54 55 E LCD SEGDIO51 1 to LCD SEGDIOS55 1 MID UG aaah el VO RAM 0x2443 1 to 0x2447 1 64 Rev 2 71M6541D F G and 71M6542F G Data Sheet 2 5 8 4 LCD Drivers The LCD drivers are grouped into up to six commons COMO COM5 and up to 56 segment drivers The LCD interface is flexible and can drive 7 segment digits 14 segments digits or enunciator symbols A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS depending on the V3P3SYS voltage The voltage doubler while capable of driving into a 500 kO load is able to generate a maximum LCD voltage that is within 1 V of twice the supply voltage The doubler and DAC operate from a trimmed low power reference The configuration of the VLCD generation is controlled by the I O RAM field LCD VMODET 1 0 I O RAM 0x2401 7 6 It is decoded into the LCD EXT LDAC E and LCD BSTE internal signals Table 56 details the LCD VMODET 1 0 configurations Table 56 LCD VMODE 1 0 Configurations LCD VMODE 1 0 LCD EXT LDAC E LCD BSTE Description 11 1 0 0 External VLCD connected to the VLCD pin See note 2 below for the definitio
81. 10C 5 0 0 EQU 2 0 2106 7 5 Oor1 0 10r2 CE41B016201 CE Coe i CE41B016601 Equations 0 1 0 1 and 2 1 Local Shunt 1 Local Shunt Current Sensor Type and and 1 Remote Shunt 1 Remote Shunt Applicable Figure Figure 3 Figure 5 Notes 1 Although not used set to 1 the sample data is ignored by the CE 2 7T1M654x with 71M6201 remote sensor 200 Amps 3 71M654x with 71M6601 remote sensor 60 Amps Teridian updates the CE code periodically Please contact your local Teridian representative to obtain the latest CE code and the associated settings The configuration presented in this table is set by the MPU demonstration code during initialization those required by the corresponding CE code being used results in undesirable side effects and must not be selected by the MPU Consult your local Teridian representative to obtain Using settings for the UO RAM Mnemonics listed in Table 1 and Table 2 that do not match the correct CE code and AFE MUX settings corresponding to the application For a basic single phase application the IAP IAN current input is configured for differential mode whereas the VA pin is single ended and is typically connected to the phase voltage via a resistor divider The IBP IBN differential input may be optionally used to sense the Neutral current This configuration implies that the multiplexer applies a total of three inputs to the ADC For this configuration the multiplexer sequence is as shown in Figure 6
82. 150 MUX_SYNC lt gt MUX STATE S X 0 X 1 X 2 X 3 A S X ADC EXECUTION 7 UP E LK SF J ADCO ADC1 ADC2 ADC3 CE TIMING e 0 450 OO 350 wv1800 CE EXECUTION Az LESS f F e e CK COUNT CE CYCLES 1CK for each ADC transfer MAX CK COUNT cE BUSY _ XFER BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL RTM TIMING rere RTM 7 7 NOTES 1 ALL DIMENSIONS ARE 5MHZ CK COUNTS 2 THE PRECISE FREQUENCY OF CK IS 150 CRYSTAL FREQUENCY 4 9152MHz 3 XFER BUSY OCCURS ONCE EVERY SUM SAMPS CODE PASSES Figure 11 Timing relationship between ADC MUX CE and RTM Serial Transfer 26 Rev 2 71M6541D F G and 71M6542F G Data Sheet 2 3 6 Pulse Generators The 71M6541D F G and 71M6542F G provide four pulse generators VPULSE WPULSE XPULSE and YPULSE as well as hardware support for the VPULSE and WPULSE pulse generators The pulse generators can be used to output CE status indicators SAG for example to DIO pins All pulses can be configured to generate interrupts to the MPU The polarity of the pulses may be inverted with control bit PLS_INV I O RAM 0x210C 0 When this bit is set the pulses are active high rather than the more usual active low PLS INV inverts all four pulse outputs The function of each pulse generator is determined by the CE code and the MPU code mu
83. 1M6542F G Data Sheet this document e 71M6xxx Data Sheet e 71M6541 Demo Board User s Manual e 71M654x Software User s Guide 9 Contact Information For more information about Maxim products or to check the availability of the 71M6541D F G and 71M6542F G contact technical support at www maxim ic com support Rev 2 163 71M6541D F G and 71M6542F G Data Sheet Appendix A Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital O DSP Digital Signal Processor FIR Finite Impulse Response ES Inter IC Bus ICE In Circuit Emulator IEC International Electrotechnical Commission MPU Microprocessor Unit CPU PLL Phase locked loop RMS Root Mean Square SFR Special Function Register SOC System on Chip SPI Serial Peripheral Interface TOU Time of Use UART Universal Asynchronous Receiver Transmitter 164 Rev 2 71M6541D F G and 71M6542F G Data Sheet Appendix B Revision History REVISION REVISION PAGES NUMBER DATE PERCRIENON CHANGED 1 0 3 11 Initial release Removed the information about 18mW typ consumption at 3 3V 1 11 4 11 in sleep mode from the Features section l Updated the Temperature Measurement Equation and 141 Temperature Error parameters in Table 99 Promoted 71M6542G to production level Table 122 Added references to 71M6541G 2G throughout the document as appropriate 1 9 10 2
84. 25 38 V Either V3P3SYS or VBAT RTC must be Max VBAT_RTC high enough to power the RTC module V3P3SYS 2 0 V VBAT RTC Voltage VBAT RTC is not needed to support the RTC and non V3P3SYS 2 0 V 2 0 3 8 V volatile memory unless V3P3SYS 2 0 V Operating Temperature 40 85 C Notes 1 GNDA and GNDD must be connected together 2 V3P3SYS and V3P3A must be connected together Rev 2 139 71M6541D F G and 71M6542F G Data Sheet 6 4 Performance Specifications 6 4 1 Input Logic Levels Table 96 Input Logic Levels Parameter Condition Min Typ Digital high level input voltage Vi Digital low level input voltage Vi Input pullup current lit E RXTX E RST E TCLK OPT RX OPT TX SPI CSZ SEGDIO36 Other digital inputs Input pull down current IIH ICE E RESET TEST Other digital inputs VIN 0 V ICE E 3 3V VIN V3P3D Note 1 In battery powered modes digital inputs should be below 0 1 V or above VBAT 0 1 V to minimize battery current 6 4 2 Output Logic Levels Table 97 Output Logic Levels Parameter Condition Min Typ Max Unit Digital high level output voltage lLoan TRA bam X cede E loa 15 mA V3P3D 0 6 V OH see notes 1 2 Digital low level output volt lLoan 1 m 2 igital low level output voltage kon 16 m i O8 7 VoL see note 1 Note 1 Guaranteed by design not production tested 2 Caution Th
85. 3 2 us ICE must be enabled Always Enabled WF OVF 28BO 4 No Wake after WD reset Always Enabled WF CSTART 28BO 7 No Wake after cold start the first application of power Always Enabled WF BADVDD 28BO 2 No dod dd WEE t 71M6542F G only pin is high level sensitive This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level This 88 Rev 2 71M6541D F G and 71M6542F G Data Sheet Table 70 Wake Bits Name Location RST WK Dir Description Connects SEGDIO4 to the WAKE logic and permits EW_DIO4 28B3 2 0 RW SEGDIO4 rising to wake the part This bit has no effect unless SEGDIO4 is configured as a digital input Connects DIO52 to the WAKE logic and permits DIO52 high level to wake the part 71M6542F G only This bit EE 28B3 1 0 aii has no effect unless dud configured as iat input Connects DIO55 to the WAKE logic and permits DIO55 EW_DIOS5 28B3 0 0 R W high level to wake the part This bit has no effect unless DIO55 is configured as a digital input Arms the WAKE timer and loads it with the value in the WAKE TMR register I O RAM 0x2880 When SLP WASPCARM 28B2 5 S S PUN mode or LCD See IE asserted by Es MPU the WAKE timer becomes active Connects the PB pin to the WAKE logic and permits PB EW PB 28B3 3 0 R W high level to wake the part PB is always configured as an input Connects the
86. 3 0 MUX8_SEL 3 0 MUX3 2102 MUX7_SEL 3 0 MUX6_SEL 3 0 MUX2 2103 MUX5 SEL 3 0 MUX4_SEL 3 0 MUX1 2104 MUX3_SEL 3 0 MUX2_SEL 3 0 MUXO 2105 MUX1_SEL 3 0 MUXO SEL 3 0 CE6 2106 EQU 2 0 U CHOP_E 1 0 RTM E CE E CE5 2107 U U U SUM_SAMPS 12 8 CE4 2108 SUM SAMPS 7 0 CE3 2109 U U CE_LCTN 5 0 CE2 210A PLS MAXWIDTH 7 0 CE1 210B PLS INTERVAL 7 0 CEO 210C R R DIFFB E DIFFA E RFLY DIS FIR LEN 1 0 PLS INV RTMO 210D U U U U U U RTMO 9 8 RTMO 210E RTMO 7 0 RTM1 210F RTM1 7 0 RTM2 2110 RTM2 7 0 RTM3 2111 RTM3 7 0 CLOCK GENERATION CKGN 2200 U U ADC_DIV PLL_FAST RESET MPU DIV 2 0 LCD DIO VREF TRIM FUSES TRIMT 2309 TRIMT 7 0 LCD DIO LCDO 2400 LCD E LCD MODE 2 0 LCD ALLCOM LCD Y LCD CLK 1 0 LCD1 2401 LCD VMODE 1 0 LCD BLNKMAP23 5 0 LCD2 2402 LCD BAT R LCD BLNKMAP22 5 0 LCD MAP6 2405 LCD MAP 55 48 LCD MAP5 2406 LCD MAP 47 40 Rev 2 107 71M6541D F G and 71M6542F G Data Sheet Name Addr LCD MAPA 2407 LCD MAP3 2408 LCD MAP2 2409 LCD MAP1 240A LCD MAPO 240B LCD4 240C U U LCD DAC 240D U U SEGDIOO 2410 U U X E U U SEGDIO15 241F U U SEGDIO16 2420 U U 7 R U U SEGDIO45 243D U U SEGDIO46 243E U U 2 U U SEGDIO50 2442 U U SEGDIO51 2443 U U M EK U U SEGDIO55 2447 U U DIO R5 2450 U U DIO R4 2451 U DIO R3 2452 U DIO R2 2453 U DIO R1 2454 U DIO RO 2455
87. 3 uA These specifications apply to all COM and SEG pins VLCD 2 5 V to 5 V LCD VMODE 3 LCD ON 1 LCD BLANK 0 LCD MODE 6 LCD CLK 2 Output load is 74 pF per SEG and COM pin Rev 2 145 71M6541D F G and 71M6542F G Data Sheet 6 4 13 VLCD Generator Table 108 LCD Driver Performance Specifications V3P3 3 3 V RVLCD removed LCD BAT O0 LCD VMODE 1 0 0 AILCD 10 pA V3P3 0 V VBAT 2 5 V RVLCD removed LCD BAT 1 LCD VMODE 1 0 0 AILCD 10 pA LCD VMODE 1 0 2 RVLCD removed LCD Boost Frequency CVLCD removed PLL_FAST 1 PLL_FAST 0 LCD VMODE 1 0 2 LCD_CLK 1 0 2 RVLCD removed V3P3 3 3V LCD_DAC 4 0 1F From LCDADJO and LCDADJ12 fuses VSYS to VLCD switch impedance VBAT to VLCD switch impedance VLCD IOH current VLCD 0 VLCD IOH lt 0 25 LCDADJ12 LCDADJO LCDADJ LCD DAC 5mV LCDADJO a ODDA LCD_DAC VLCDyom LCD_DAC 2 65 2 65 LCDADJ LCD DAC The above equations describe the nominal value of VLCD for a specific LCD DAC value The specifications below list the maximum deviation between actual VLCD and VLCDnom Note that when VCC and boost are insufficient the LCD DAC will not reach its target value and a large negative error Will occur LCD DAC Error VLCD VLCDnom LCD VMODEL 1 0 2 see note 2 LCD DAC 4 0 1F Full Scale with Boost LCD CLK 1 0 2 V3P3 3 6 V LCD MODE 2 0 6 V3P3 3 0 V VBAT 4 0 V V3P3 0 BRN Mode VBAT 2 5 V V3P3 0 BRN Mo
88. 36 PDATA OxBF 0x00 High address byte for MOVX Ri also called USR2 32 IRCON OxCO 0x00 Interrupt Request Control Register 42 T2CON 0xC8 0x00 Polarity for INT2 and INT3 42 PSW OxDO 0x00 Program Status Word 35 WDCON OxD8 0x00 Baud Rate Control Register only WDCON 7 bit used 36 A OxEO 0x00 Accumulator do B OxFO 0x00 B Register 35 34 Rev 2 71M6541D F G and 71M6542F G Data Sheet Accumulator ACC A SFR 0x E0 ACC is the accumulator register Most instructions use the accumulator to hold the operand The mnemonics for accumulator specific instructions refer to accumulator as A not ACC B Register SFR OxF0 The B register is used during multiply and divide instructions It can also be used as a scratch pad register to hold temporary data Program Status Word PSW SFR 0xDO0 This register contains various flags and control bits for the selection of the register banks see Table 14 Table 14 PSW Bit Functions SFR 0xD0 PSW Bit Symbol Function 7 CV Carry flag 6 AC Auxiliary Carry flag for BCD operations 5 F0 General purpose Flag 0 available for user V FO is not to be confused with the FO flag in the CESTATUS register 4 RS1 Register bank select control bits The contents of RS1 and RSO select the working register bank RS1 RSO Bank selected Location 3 RSO 00 Bank 0 0x00 0x07 01 Bank 1 0x08 OxOF 10 Bank 2 0x10 0x17 11 Bank 3 0x18 Ox1F 2 OV Over
89. 5 C 10 Smeg fe mass erase operations WieTmepeBye l Jales Page Erase 1024 bytes 2 m Wastme o 1 1 1 2 1 w 6 5 2 SPI Slave Table 113 SPI Slave Timing Specifications Parameter Condition Uwe Typ Max Unit SPI Setup Time SPI DItoSPI CKrse 10 J m SPI Hold Time SPLCKrisetoSPLDI 10 J nm SPI Output Delay Sp CKfaltoSPI DO J 4 ns SPI Recovery Time SPI _CSZfallto SPI CK 10 J ms SPI Removal Time SPL CK to SPI CSZrise 15 J ms SPI Clock Dep 1 ts LSPIOHKEoW o Sof J mm SPI Clock Freq SPlIFregMPUFeg 20 MHZMHz SPI Transaction Space SPI_CSZ rise to SPI CSZfall 45 MPU Cycles 6 5 3 EEPROM Interface Table 114 EEPROM Interface Timing Parameter Condition Min Typ Max Unit Using interrupts Write Clock frequency CH CKMPU 4 9 MHZ bit banging DIO2 3 100 kHz PLL_FAST 0 Write Clock frequency 3 wire CKMPU 4 9 MHz PLL FAST 0 160 kHz PLL FAST 1 500 Rev 2 151 71M6541D F G and 71M6542F G Data Sheet 6 5 4 RESET Pin Table 115 RESET Pin Timing Parameter Condition Min Typ Max Unit Reset pulse width 5 us Reset pulse fall time see note 1 1 us Notes 1 Guaranteed by design not product
90. 6542F G via the digital isolation interface and are directly stored in CE RAM See Figure 6 for the multiplexer timing sequence corresponding to Figure 5 See Figure 38 for the meter configurations corresponding to Figure 5 VREF EE MUX T AX ADC CONVERTER Local VREF 1 Shunt IAN VREF FIR VADC10 VA VADE gt is VADC9 VB CE RAM INP SP IBP Remote Digital Shunt 71M6x01 Isolation SN IBN Interface ae INN 71M6542F 11 5 2010 Figure 5 71M6542F G AFE Block Diagram with 71M6x01 2 2 1 Signal Input Pins The 71M6541D F G features five ADC inputs The 71M6542F G features six ADC inputs IAP IAN and IBP IBN are intended for use as current sensor inputs These four current sensor inputs can be configured as four single ended inputs or can be paired to form two differential inputs For best performance it is recommended to configure the current sensor inputs as differential inputs i e IAP IAN and IBP IBN The first differential input IAP IAN features a pre amplifier with a selectable gain of 1 or 8 and is intended for direct connection to a shunt resistor sensor and can also be used with a Current Transformer CT The remaining differential pair i e IBP IBN may be used with CTs or may be enabled to int
91. 654x function as a smart front end with preprocessing capability Since the addresses are in 16 bit format any type of XRAM data can be accessed CE MPU I O RAM but not SFRs or the 80515 internal register bank 2 Acommunication link can be established via the SPI interface By writing into MPU memory locations the external host can initiate and control processes in the 71M654x MPU Writing to a CE or MPU location normally generates an interrupt a function that can be used to signal to the MPU that the byte that had just been written by the external host must be read and processed Data can also be inserted by the external host without generating an interrupt 3 An external DSP can access front end data generated by the ADC This mode of operation uses the 71M654x as an analog front end AFE 4 Flash programming by the external host SPI Flash Mode SPI Transactions A typical SPI transaction is as follows While SPI CSZ is high the port is held in an initialized reset state During this state SPI DO is held in Hi Z state and all transitions on SPI CLK and SPI DI are ignored When SPI CSZ falls the port begins the transaction on the first rising edge of SPI CLK As shown in Table 62 a transaction consists of an optional 16 bit address an 8 bit command an 8 bit status byte followed by one or more bytes of data The transaction ends when SPI CSZ is raised Some transactions may consist of a command only Rev 2 73 71M6541D F G
92. 7 2 11 11 Added missing data sheet title header to odd and even pages 49 54 56 Corrected errata detected since the previous v1 1 see 62 97 120 indicated pages changed Added section 6 7 on page 155 Rev 2 165 71M6541D F G and 71M6542F G Data Sheet Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 O 2011 Maxim Integrated Products MAXIM is a registered trademark of Maxim Integrated Products
93. 709 3 See Figure 3 for the AFE configuration corresponding to Figure 36 Note This system is referenced to LINE He e LH e NEUTRAL gt POWER SUPPLY D LINE z TERIDIAN a 71M6xx1 5 MUX and ADC V3P3A V3P3SYS GNDA GNDD D 9 IAP PWR MODE fc IAN CONTROL 00000 mmm Pulse TERIDIAN WAKE UP WT Zz rans 71M6541D F REGULATOR BATTERY a former VBAT 6 VBAT RTC eo TEMPERATURE BATTERY BATTERY MONITOR SENSOR RAM ee LCD DISPLAY COMPUTE SEG ENGINE SEG DIO 8888 8888 LCD DRIVER FLASH DIO PULSES BEES MODUL MEMORY DIO BID ATOR E pU POWER FAULT MPU ilis IC or uWire COMPARATOR RTC EEPROM TIMERS 2 32 kHz ICE 11 5 2010 Figure 36 71M6541D F G with 71M6x01 isolated Sensor 94 Rev 2 71M6541D F G and 71M6542F G Data Sheet 4 5 71M6542F G Using Local Sensors Figure 38 shows a 71M6542F G configuration using locally connected current sensors The IAP IAN current channel may be directly connected to either a shunt resistor or a CT while the IBP IBN channel is connected to a CT and is therefore isolated This configuration implements a dual phase measurement utilizing Equation 2 For best performance both the IAP IAN and IBP IBN current sensor inputs are configured for differential mode i e DIFFA E 1 and DIFFB E 1 I O RAM 0x210C 4 and 0x210C 5 The
94. 71M6542F G Data Sheet See 4 7 3 and 4 7 4 below for further temperature compensation details 4 7 8 Temperature Compensation for VREF with Local Sensors This section discusses metrology temperature compensation for the meter designs where local sensors are used as shown in Figure 35 and Figure 37 In these configurations where all sensors are directly connected to the 71M654x each sensor channel s accuracy is affected by the voltage variation in the 71M654x VREF due to temperature The VREF in the 71M654x can be compensated digitally using a second order polynomial function of temperature The 71M654x features an on chip temperature sensor for the purpose of temperature compensating its VREF There are also error sources external to the 71M654x The voltage sensor resistor dividers and the shunt current sensor and or CT and their corresponding signal conditioning circuits also have a temperature dependency which also may require compensation depending on the required accuracy class The compensation for these external error sources may be optionally lumped with the compensation for VREF by incorporating their compensation into the PPMC and PPMC2 coefficients for each corresponding channel The MPU has the responsibility of computing the necessary compensation values required for each sensor channel based on the sensed temperature Teridian provides demonstration code that implements the GAIN ADJn compensation equation shown below The resultin
95. 82 Local Sensors 0x21 WRATE 547 K 109 1587 Remote Sensor Nacc SUM_SAMPS 12 0 CE RAM 0x23 See Table 83 for the definition of X The default value yields 1 0 Wh pulse for VMAX 600 V and IMAX 208 A The maximum value for WRATE is 32 768 2 0x22 KVAR 6444 Scale factor for VAR measurement 0x23 SUM_SAMPS 2520 SUM SAMPS Nacc Wh pulse WPULSE generator input to be updated by the MPU when using external pulse generation The output pulse rate is APULSEW Fs 2 WRATE X 2 0x45 APULSEW 0 aha i ee This input is buffered and can be updated by the MPU during a conversion interval The change takes effect at the beginning of the next interval 0x46 WPULSE CTR 0 WPULSE counter Unsigned numerator containing a fraction of a pulse The value nd WEULSE TRAG g in this register always counts up towards the next pulse 0x48 WSUM_ACCUM 0 Roll over accumulator for WPULSE 0x49 APULSER 0 VARh VPULSE pulse generator input Ox4A VPULSE CTR 0 VPULSE counter Ox4B VPULSE FRAC 0 Unsigned numerator containing a fraction of a pulse The value in this register always counts up towards the next pulse Ox4C VSUM ACCUM 0 Roll over accumulator for VPULSE Rev 2 133 71M6541D F G and 71M6542F G Data Sheet 5 3 10 Other CE Parameters Table 91 shows the CE parameters used for suppression of noise due to scaling and truncation effects Table 91 CE Parameters for Noise Suppression and Code Version
96. BSENSE 7 0 LKPADDR 2887 LKPAUTOI LKPADDR 6 0 LKPDATA 2888 LKPDAT 7 0 LKPCTRL 2889 U U U U U U LKP RD LKP WR RTCO 2890 RTC WR RTC RD U RTC FAIL U U U U Rev 2 109 71M6541D F G and 71M6542F G Data Sheet Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTC2 2892 BIC SBSC 7 0 RTC3 2893 U U BIC SEC 5 0 RTC4 2894 U U BIC MIN 5 0 RTC5 2895 U U U RTC_HR 4 0 RTC6 2896 U U U U U BIC DAY 2 0 RTC7 2897 U U U RTC DATE 4 0 RTC8 2898 U U U U RTC_MO 3 0 RTC9 2899 RTC YR 7 0 RTC10 289B U U U U U RTC_P 16 14 RTC11 289C RTC_P 13 6 RTC12 289D RTC_P 5 0 RTC_Q 1 0 RTC13 289E U U RTC_TMIN 5 0 RTC14 289F U U U RTC_THR 4 0 TEMP 28A0 TEMP_BSEL TEMP_PWR OSC_COMP TEMP_BAT TBYTE_BUSY TEMP PER 2 0 WF1 28B0 WF CSTART WF RST WF RSTBIT WF_OVF WF ERST WF BADVDD WF2 28B1 U U WF TMR WF RX WF PB WF DIO4 WF DIO52 WF DIO55 MISC 28B2 SLEEP LCD ONLY WAKE ARM WAKE E 28B3 U U U EW_RX EW_PB EW DIO4 EW DIO52 EW_DIO55 WDRST 28B4 WD RST TEMP START U U U U U U MPU PORTS P3 SFR BO DIO DIR 15 12 DIO 15 12 P2 SFR A0 DIO DIR 11 8 DIO 11 8 P1 SFR 90 DIO DIR 7 4 DIO 7 4 PO SFR 80 DIO DIR 3 0 DIO 3 0 FLASH ERASE SFR94 FLSH_ERASE 7 0 FLSHCTL SFRB2 PREBOOT SECURE U U FLSH PEND FLSH_PSTWR FLSH MEEN FLSH_PWE PGADR SFRB7 FL
97. Battery Power Unless otherwise specified V3P3SYS V3P3A 0 PB GND BRN Table 104 Low Power Voltage Regulator Performance Specifications VBAT 3 0V 3 8V V3P3 0 V ILOAD 0 mA VBAT 3 3 V V3P3 0 V V2P5 load regulation ILOaD 0 MA to 1 mA ILOAD Oma VBAT 2 0 V Voltage Overhead 2V VBAT VDD V3P3 0 V 6 4 10 Crystal Oscillator Measurement conditions Crystal disconnected test load of 200 pF 100 kO between XOUT and GNDD Table 105 Crystal Oscillator Performance Specifications XIN to XOUT Capacitance Foon dd see note 1 RTC_ADJ 7F to O Capacitance change on XOUT Bias voltage unbiased Vpp 0 1 V Notes 1 Guaranteed by design not production tested 6 4 11 Phase Locked Loop PLL Table 106 PLL Performance Specifications PLL FAST 0 V3P3 0 V to 3 3 V step measured from first edge of MCK PLL_FAST settling time V3P3 0 V VBAT 3 8 V to 20V PLL_FAST rise see note 1 PLL Power up Settling Time see note 1 PLL_FAST fall See note 1 PLL SLP to MSN Settling Time PLL_FAST 0 see note 2 PLL power up overshoot PLL_FAST 0 see note 1 Notes 1 Guaranteed by design not production tested 144 Rev 2 71M6541D F G and 71M6542F G Data Sheet 6 4 12 LCD Drivers Table 107 LCD Driver Performance Specifications PARAMETER CONDITION MIN TYP MAX UNIT VLCD Current VLCD 3 3 all LCD map bits 0 2 UA see Notes 1 to 4 VLCD 5 0 all LCD map bits 0
98. CK 38 40 kHz 38 6 kHz UART Modulation CK32 MCK 32 768 kHz 32 kHz clock 2 5 4 Real Time Clock RTC 2 5 4 1 RTC General Description The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the VBAT_RTC pin depending on the V3OK internal bit The RTC consists of a counter chain and output registers The counter chain consists of registers for seconds minutes hours day of week day of month month and year The chain registers are supported by a shadow register that facilitates read and write operations Table 42 shows the I O RAM registers for accessing the RTC 2 5 4 2 Accessing the RTC Two bits RTC RD I O RAM 0x2890 6 and RTC WR I O RAM 0x2890 7 control the behavior of the shadow register When RTC RD is low the shadow register is updated by the RTC after each two milliseconds When RTC RD is high this update is halted and the shadow register contents become stationary and are suitable to be read by the MPU Thus when the MPU wishes to read the RTC it freezes the shadow register by setting the RTC RD bit reads the shadow register and then lowers the RTC_RD bit to let updates to the shadow register resume Since the RTC clock is only 500Hz there may be a delay of approximately 2 ms from when the RTC RD bit is lowered until the shadow register receives its first update Reads to RTC RD continue to return a one until the first shadow update occurs When RTC
99. DD SEGDIO26 COM5 mm 17 59 ICE E SEGDIO25 mm 18 58 E RXTX SEG48 SEGDIO24 mm 19 57 E TCLK SEG49 SEGDIO23 mm 20 56 E RST SEG5O SEGDIO22 gum 21 55 RX SEGDIO21 mma 22 54 mm TX SEGDIO20 mm 23 538mm OPT TX SEGDIO51 SEGDIO19 mm 24 52 mg SEGDIO52 SEGDIO18 mm 25 51m SEGDIO53 ANNAN RHDOHHRHOHOHDOHOTESTETSSESSB PITT OF O 10 3 00 QI 1 O O9 m Lu LL LO 5 SF zU LL 10 SF OOO SEEREEEEEEEEEPEFEREEERPEE aaananaano92go0 OFOFFOO ooooooooO0iuno csi US ol SS OO uuuuuulugoc eo ovozu 00000000 UNS OJS noo a T COR aa omgaat EI UU oo W W o unt nn nn o Figure 51 Pinout for the 71M6542F G LQFP 100 Package Rev 2 157 71M6541D F G and 71M6542F G Data Sheet 6 9 Pin Descriptions 6 9 1 Power and Ground Pins Pin types P Power O Output I Input I O Input Output The circuit number denotes the equivalent circuit as specified under 6 9 4 I O Equivalent Circuits Table 119 Power and Ground Pins Pin 64 pin Pin 100 pin Name Type Circuit Description 50 72 80 GNDA P Analog ground This pin should be connected directly to the ground plane 42 62 GNDD P Digital ground This pin should be connected directly to the ground plane 53 85 V3P3A Analog power supply A 3 3 V power supply should be connected to this pin V3P3A must be the same voltage as V3P3SYS 45 69 V3P3SYS System 3 3 V supply This pin should be connected to a 3 3 V power supply
100. DIO4 wake flag bit If DIO4 is configured to wake the part this bit is set WF DIO4 28B1 2 O R whenever the de bounced version of DIO4 rises It is held in reset if DIO4 is not configured for wakeup DIO52 wake flag bit If DIO52 is configured to wake the part this bit is set WF DIO52 28B1 1 O R whenever the de bounced version of DIO52 rises It is held in reset if DIO52 is not configured for wakeup DIO55 wake flag bit If DIO55 is configured to wake the part this bit is set WF DIO55 28B1 0 Di R Whenever the de bounced version of DIO55 rises It is held in reset if DIO55 is not configured for wakeup WF TMR 28B1 5 0 R Indicates that the wake timer caused the part to wake up WF PB 28B1 3 0 R Indicates that the PB caused the part to wake WF RX 28B1 4 0 R Indicates that RX caused the part to wake WF_CSTART 28BO 7 0 WE RST 28BO 6 1 WF RSTBIT 28BO 5 0 R Indicates that the Reset pin Reset bit ERST pin Watchdog timer the cold WF OVF 28BO 4 Orge start detector or bad VBAT caused the part to reset WE ERST 28BO 3 0 WE BADVDD 28BO 2 0 124 Rev 2 71M6541D F G and 71M6542F G Data Sheet 5 3 CE Interface Description 5 3 1 CE Program The CE performs the precision computations necessary to accurately measure energy These computations include offset cancellation phase compensation product smoothing product summation frequency detection VAR ca
101. Data Access Locetons nennen nemen nnn nnne nnns 127 Table 80 CESTATUS Register 127 Table 81 CESTATUS CE RAM 0x80 Bit Definitions esssssssseeee mem nnns 128 Table 82 CECONFIG Register AAAAAN EEN 128 Table 83 CECONFIG CE RAM 0x20 Bit Definitions sessssseeee enne 128 Table 84 Sag Threshold and Gain Adjust Control 129 Table 85 CE Transfer Variables with Local Gensors enne 130 Table 86 CE Transfer Variables with Remote Sensor sssseseee enne 130 Table 87 CE Energy Measurement Variables with Local Sensors sssssssseessesrrrrseesssrrrrrrreerenrrrrns 131 Table 88 CE Energy Measurement Variables with Remote Sensor sssssrrrrrrrtrrtrrttrrrrrrrrrrrrrrrrna 131 Table 89 Other Transfer Varlables nc HEERRECEEE EEUU EECRE LEE CP Fe e edes 132 Table 90 CE Pulse Generation Parameters AAA 133 Table 91 CE Parameters for Noise Suppression and Code Version 134 Table 92 CE Calibration Parameters AAA 135 Table 93 Absolute Maximum Range 138 Table 95 Recommended Operating Condttons nennen nnns 139 Table 96 Input Eogic Levels oise nenieca ea erre Eee b Eee bvb Er ea exea rea vea rea samen RER eg 140 Table 97 O utput b glc Levels coeno ite teet rete Ph e te eet e t t Deed ne ren eee ad HR 140 Table 98 Battery Monitor Performance Specifications TEMP BAT 1 141 Table 99 Temperature Montor cece cece cece cece eect e teeter ee ee me emen nennen nnn nr nnns n
102. Definitions SE FIG Name Default Description 23 Reserved 0 When this bit is set control of temperature compensation is enabled for the 71M6x01 Isolated Sensor Interface When 1 the MPU controls temperature compensation via the 22 EXT TEMP 0 GAIN ADJn registers CE RAM 0x40 0x42 when 0 the CE is in control When 1 XPULSE produces a pulse for each zero crossing of 21 EDGE INT 1 the mains phase selected by FREQSEL 1 0 which can be used to interrupt the MPU 20 SAG INT 1 When 1 activates YPULSE output when a sag condition is detected 252 The number of consecutive voltage samples below SAG_THR 19 8 SAG CNT CE RAM 0x24 before a sag alarm is declared The default value OxFC is equivalent to 100 ms FREQSEL 1 0 selects the phase to be used for the frequency monitor sag detection and for the zero crossing counter MAINEDGE X CE RAM 0x83 FREQ SEL 1 0 Phase Selected 7 6 FREQSEL 1 0 0 0 0 A 0 1 B 1 X Not allowed 71M6542F G only 128 Rev 2 71M6541D F G and 71M6542F G Data Sheet When zero causes the pulse generators to respond to internal data WPULSE WSUM_X CE RAM 0x84 VPULSE VARSUM X CE RAM 0x88 Otherwise the generators respond to values the MPU places in APULSEW and APULSER CE RAM 0x45 and 0x49 4 2 Reserved 0 Reserved When PULSE FAST 1 the pulse generator input is increased 16x When PULSE SLOW 1 the pulse generator input is 1 PULSE FAST 0 reduced by a factor of 64 These two pa
103. E 1 0 00 At the end of the first interval CROSS is high at the end of the second interval CROSS is low Operation with CHOP E 1 0 00 does not require control of the chopping mechanism by the MPU In the second toggle state CHOP_E 1 0 11 CROSS does not toggle at the end of the last multiplexer cycle in an accumulation interval A second low power voltage reference is used in the LCD system and for the comparators that support transitions to and from the battery modes Rev 2 21 71M6541D F G and 71M6542F G Data Sheet 2 2 8 71M6x01 Isolated Sensor Interface Remote Sensor Interface 2 2 8 1 General Description Non isolating sensors such as shunt resistors can be connected to the inputs of the 71M654x via a combination of a pulse transformer and a 71M6x01 IC a top level block diagram of this sensor interface is shown in Figure 36 The 71M6x01 receives power directly from the 71M654x via a pulse transformer and does not require a dedicated power supply circuit The 71M6x01 establishes 2 way communication with the 71M654x supplying current samples and auxiliary information such as sensor temperature via a serial data stream One 71M6x01 Isolated Sensor can be supported by the 71M6541D F G and 71M6542F G When remote interface IBP IBN is enabled the two analog current inputs pins IBP and IBN become a digital balanced differential interface to the remote sensor See Table 3 for details Each 71M6x01 Isolated Sensor cons
104. ES een ccc rtt o ee t p E Pt ete t ttu Ene RE uda 162 To Ordering Information ceci tete te ete ceo Saks ete e eco be ein ce xe e ce co bach ia Deer E re DI De anaie ankein aun 163 7 1 71M6541D F G and 71M6542F G nenne nnne nnn nnne n nennen nne n nnns 163 8 Related Information een EE Ee 163 9 Contact Information ueeeeeeeeeeeeeeeeeennnnnnnnnnnnnnnnnnnnnnnnn nnn n niin ununi uuu u snnt 163 ee Ee de TEE 164 Appendix B Revision HISEOTy 0 2 2ccc2ce saca ci ca ace ceca aca neca rara ENEE 165 Rev 2 71M6541D F G and 71M6542F G Data Sheet Figures Figure 2 71M6541D F G AFE Block Diagram Local Gensorst eee 12 Figure 3 71M6541D F G AFE Block Diagram with ZIMGxT eem 13 Figure 4 71M6542F G AFE Block Diagram Local Sensors ssssssseee eee 13 Figure 5 71M6542F G AFE Block Diagram with 71M6X01 1 0 0 criti ees 14 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 39 States in a Multiplexer Frame MUX DIV 3 0 3 eene 17 States in a Multiplexer Frame MUX DIV 3 0 Ai 17 General Topology of a Chopped Ampltter ttrt rrtt rr rAEEEEEEEEEEEEEEEEEEEEEEEE EEEE 21
105. EXT PULSE status the output pulse rate controlled by APULSEW and APULSER is implemented by the CE only By setting EXT PULSE 1 the MPU is providing the source for pulse generation If EXT PULSE is 0 WOSUM X CE RAM 0x85 and VAROSUM X CE RAM 0x89 are the default pulse generation sources In this case creep cannot be controlled since it is an MPU function The maximum pulse rate is 3 Fs 7 56 kHz See 2 3 6 2 VPULSE and WPULSE for details on how to adjust the timing of the output pulses The maximum time jitter is 1 6 of the multiplexer cycle period nominally 67 us and is independent of the number of pulses measured Thus if the pulse generator is monitored for one second the peak jitter is 67 ppm After 10 seconds the peak jitter is 6 7 ppm The average jitter is always zero If itis attempted to drive either pulse generator faster than its maximum rate it simply outputs at its maximum rate without exhibiting any rollover characteristics The actual pulse rate using WSUM as an example is WRATE WSUM F X z Ke where Fs sampling frequency 2520 6 Hz X Pulse speed factor derived from the CE variables PULSE_SLOW CE RAM Ox20 0 and PULSE FAST CE RAM 0x20 1 RATE 132 Rev 2 71M6541D F G and 71M6542F G Data Sheet Table 90 CE Pulse Generation Parameters m Name Default Description Address H Kh eS Wh pulse WRATE N Acc X where K 66 17
106. F G LCD Data Registers for SEG46 to GEGbO 70 Table 60 EECTRL Bits for 2 pin Interface 71 Table 61 EECTRL Bits for the 3 wire Interface 71 Table 62 SPI Transaction Te EE 74 Table 63 SPI Command Sequences eese nene hh nennen nnn hh nnn nne s nnne nnne nennen nena 75 Table 64 SP Re lISIers Ii eee re E Era Et ERE aU Ere eL ee eu dave a e wu a eee 76 Table Ga TMUX I5 0 Selectlons o i te ed dee ete etre oed ce e etu e t rer e a E ad 79 T able 66 TMUX2 4 0 Selections c eee entere D a D nnnc ee eee 79 Table 67 Available Circuit Funchons nennen nnne nn nemrnnnn nnn nnn nennen nnne 82 Table 68 VSTAT 2 0 TE RE 85 Table 69 Wake Enables and Flag Bits seesesseesessseseseeeeeeeneeennnennnnnnn nennen nnne nnne 87 Table 70 Wake Bits B nane enter ete EE E RM B avid ERE epe Eee e Ere avid 89 Table 71 Clear Events for WAKE Tags 90 Table 72 GAIN ADJn Compensation Channels enne nnns 98 Table 73 GAIN ADJn Compensation Channels 0 ccccccccceeeeeeeeeeeeeeeaeeeeeeeeeeeeeaaaaeeeeeeeeeeesaaaaeeeneeees 100 Table 74 I O RAM Map Functional Order Basic Configuration sseeee rttr rrrrrrrnE na 105 Table 75 O RAM Map Functional Order 107 Table 76 I O RAM Map Functional Order 111 Table 77 Standard GE CodeS as ee eege Ee Ee ma m s n RR ER eg 125 Table 78 CE EQU Equations and Element Input Mapping ssssssttrrrtrttttrtttttt ttrt rttr rtr EEEEEEEEEEEEEE EEEE EEE 126 Table 79 CE Raw
107. FLASH mode This bit is zero when the TEST pin is zero Bit 0 SPI FLASH mode ready Used in SPI FLASH mode Indicates that the flash is ready to receive another write instruction 76 Rev 2 71M6541D F G and 71M6542F G Data Sheet SPI Flash Mode SFM In normal operation the SPI slave interface cannot read or write the flash memory However the 71M6541D F G and 71M6542F G support an SPI Flash Mode SFM which facilitates initial programming of the flash memory When in SFM mode the SPI can erase read and write the flash memory Other memory elements such as XRAM and I O RAM are not accessible in this mode In order to protect the flash contents several operations are required before the SFM mode is successfully invoked In SFM mode n byte reads and dual byte writes to flash memory are supported See the SPI Transactions description on Page 73 for the format of read and write commands Since the flash write operation is always based on a two byte word the initial address must always be even Data is written to the 16 bit flash memory bus after the odd word is written In SFM mode the MPU is completely halted For this reason the interrupt feature described in the SPI Transaction section above is not available in SFM mode The 71M6541D F G and 71M6542F G must be reset by the WD timer or by the RESET pin in order to exit SFM mode Invoking SFM The following conditions must be met prior to invoking SFM e PinICE E 1
108. F_CAL 2704 7 0 0 RW when VREF DIS1 VREF DIS 2704 6 O 1 RW Disables the internal ADC voltage reference Rev 2 123 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir Description This word describes the source of power and the status of the VDD VSTAT Description 000 System Power OK V3P3A gt 3 0v Analog modules are functional and accurate V3AOK V3OK 11 001 System Power Low 2 8v V3P3A 3 0v Analog modules not accurate Switch over to battery power is imminent V3AOK V3OK 01 VSTAT 2 0 SFR F9 2 0 R 010 Batter power and VDD OK VDD gt 2 25v Full digital functionality V3AOK V30K 00 VDDOK VDDgt2 11 011 Battery power and VDD gt 2 0 Flash writes are inhibited If the TRIMVDD 5 fuse is blown PLL FAST I O RAM 0x2200 4 is cleared V3AOK V30K 00 VDDOK VDDgt2 01 101 Battery power and VDD lt 2 0 When VSTAT 101 processor is nearly out of voltage Processor failure is imminent V3AOK V30K 00 VDDOK VDDgt2 00 Arms the WAKE timer and loads it with WAKE TMR 7 0 When SLEEP or eS 28B2 5 0 RW LCD_ONLY is asserted by the MPU the WAKE timer becomes active WAKE TMR 7 0 2880 7 0 O RW Timer duration is WAKE TMR 1 seconds WD Per 28BA 7 olol w Reset the WD timer The WD is reset when a 1 is written to this bit Writing a one clears and restarts the watch dog timer
109. GDIO26 and SEGDIO27 become COM4 and COMB if their LCD MAP bits are set The LCD ON I O RAM 0x240C 0 and LCD BLANK I O RAM 0x240C 1 bits are an easy way to either blank the LCD display or turn it fully on Neither bit affects the contents of the LCD data stored in the LCDSEG DIO registers In comparison LCD RST I O RAM 0x240C 2 clears all LCD data to zero LCD RST affects only pins that are configured as LCD A small amount of power can be saved by programming the LCD frequency to the lowest value that provides satisfactory LCD visibility over the required temperature range 66 Rev 2 71M6541D F G and 71M6542F G Data Sheet Table 57 shows all I O RAM registers that control the operation of the LCD interface Table 57 LCD Configurations Name Location Rst Wk Dir Description LCD ALLCOM 2400 3 R W Configures all 6 SEG COM pins as COM Has no effect on pins whose LCD_MAP bit is zero LCD_BAT 2402 7 R W Connects the LCD power supply to VBAT in all modes LCD_E 2400 7 R W Enables the LCD display When disabled VLC2 VLC1 and VLCO are ground as are the COM and SEG outputs if their LCD_MAP bitis 1 LCD_ON LCD_BLANK 240C 0 240C 1 R W R W LCD ON 1 turns on all LCD segments without affecting the LCD data Similarly LCD BLANK 1 turns off all LCD segments without affecting the LCD data If both bits are set all LCD segments are turned on
110. GDIO4 pin a high level on the SEGDIO52 pin 71M6542F G only or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin See Table 69 for de bounce details on each pin and for further details on the OPT_RX SEGDIO55 pin The SEGDIO4 SEGDIO52 71M6542F G only and SEGDIO55 pins must be configured as DIO inputs and their wake enable EW x bits must be set In SLP and LCD modes the MPU is held in reset and cannot poll pins or react to interrupts When one of the hardware wake events occurs the internal WAKE signal rises and within three CK32 cycles the MPU begins to execute The MPU can determine which one of the pins awakened it by checking the WF PB WF RX WF SEGDIO4 WF DIO52 71M6542F G only or WF DIOS55 flags see Table 69 If the part is in SLP or LCD mode it can be awakened by a high level on the PB pin This pin is normally pulled to GND and can be connected externally so it may be pulled high by a push button depression Some pins are de bounced to reject EMI noise Detection hardware ignores all transitions after the initial transition Table 69 shows which pins are equipped with de bounce circuitry Pins that do not have de bounce circuits must still be high for at least 2 us to be recognized The wake enable and flag bits are also shown in Table 69 The wake flag bits are set by hardware when the MPU wakes from a wake event Note that the PB flag is set whenever the PB is pushed even if the part is already awake
111. IAN or IBP IBN Finput impedance no preamp Jeer 49 99 99 ADC Gain Error vs Power Supply Variation Vin 200 mV pk 65 Hz 10 ANout px 357nV V y V3P3A 3 0 V 3 6 V 100AV3P3A 3 3 Input Offset IADCO IADC1 V3P3A DIFFO_E 1 PRE_E 0 IADCO V3P3A DIFFO_E 0 PRE_E 0 THD 250mVpk Vin 65Hz 250mVpk Name FIR LEN ADC DIV PLL FAST 64kpts FFT Blackman Harris 0 0 3 x Window ajro nim olojo gt aj I onm Oo OQ a gt THD 20mVpk Vin 65Hz 20mVpk Name RAEN Ape piv Pu rast 64kpts FFT Blackman Harris Window a T onim olojo S njwjaojln BY EE ry l PLL FAST MUX DIV 0 Vin 65Hz 20mVpk 64kpts FFT Blackman Harris window w Ie o m 5 B G ry oo ce rio jmim jog ojm A 91125 B 778688 C 1103823 D 884736 E 2097152 F G H J Name FIR_LEN iz PLL FAST 91125 103823 884736 2097152 aj I onim ojoj S njoj D PP Sien Ina Rev 2 149 71M6541D F G and 71M6542F G Data Sheet Guaranteed by design not production tested Unless stated otherwise the following test conditions apply to all the parameters provided in this table FIR LEN 1 0 1 VREF_DIS 0 P
112. J 6 0 to 7F maximizes the load capacitance minimizing the oscillator frequency The adjustable capacitance is approximately RTCA_ ADJ 16 5 pF 128 The precise amount of adjustment depends on the crystal properties the PCB layout and the value of the external crystal capacitors The adjustment may occur at any time and the resulting clock frequency should be measured over a one second interval ADJ The second rate adjustment is digital and can be used to adjust the clock rate up to 988ppm with a resolution of 3 8 ppm 1 9 ppm Note that 3 8 ppm corresponds to 1 LSB of the 19 bit quantity formed by 4 RTCP RTCQ and 1 9 ppm corresponds to 2 LSB The rate adjustment is implemented starting at the next second boundary following the adjustment Since the LSB results in an adjustment every four seconds the frequency should be measured over an interval that is a multiple of four seconds The clock rate is adjusted by writing the appropriate values to RTC P 16 0 I O RAM 0x289B 2 0 0x289C 0x289D 7 2 and RTC Q 1 0 I O RAM 0x289D 1 0 Updates to RTC rate adjust registers RTC P and RTC_Q are done through the shadow register described above The new values are loaded into the counters when RTC WR I O RAM 0x2890 7 is lowered The default frequency is 32 768 RTCLK cycles per second To shift the clock frequency by A ppm RTC P and RTC Q are calculated using the following equation 52 Rev 2 71M6541D F G and 71M6542F G Data She
113. LL FAST 1 ADC_DIV 0 MUX_DIV 6 LSB values do not include the 9 bit left shift at CE input 6 4 16 Pre Amplifier for IAP IAN Table 111 Pre Amplifier Performance Specifications PARAMETER CONDIION MIN TYP MAX UNIT Differential Gain Vin 30mvV differential Vin 15mv differential see note 1 Ta 25 C V3P3 3 3 V PRE_E 1 FIR_LEN 2 DIFFO_E 1 2520Hz sample rate 7 8 7 92 8 0 VN 7 8 7 92 8 0 VN Gain Variation vs V3P3 V3P3 0 Vin 30mV differential see note 1 2 97 V 3 63 V LE Vin 30mv differential see note 1 Phase Shift Vin 30mv differential see note 1 Preamp input current IADCO IADC1 Preamp ADC THD Vin 30mvV differential Vin 15mvV differential Preamp Offset IADCO IADC1 V3P3 30mV IADCO IADC1 V3P3 15mV IADCO IADC1 V3P3 IADCO IADC1 V3P3 15mV IADCO IADC1 V3P3 30mV Ta 40 C 85 C Ta 25 C V3P3 3 3 V PRE_E 1 FIR_LEN 2 DIFFO_E 1 2520Hz sample rate IADCO IADC1 V3P3 Ta 25 C V3P3 3 3 V PRE_E 1 FIR_LEN 2 DIFFO_E 1 2520Hz sample rate Ta 25 C V3P3 3 3 V PRE_E 1 FIR_LEN 2 DIFFO_E 1 2520Hz sample rate Notes 1 Guaranteed by design not production tested 150 Rev 2 71M6541D F G and 71M6542F G Data Sheet 6 5 Timing Specifications 6 5 1 Flash Memory Table 112 Flash Memory Timing Specifications mge Gomd on min Typ wax Unit_ 40 Cw 85 C 20000 Loge Flash data retention 25 C 100 vaars 8
114. MA AAILM Teridian Smart Grid Solutions 19 5376 Rev 2 11 11 71M6541D F G and 71M6542F G Energy Meter ICs 2 Ee GENERAL DESCRIPTION The 71M6541D 71M6541F 71M6541G 71M6542F 71M6542G are Teridian 4th generation single phase metering SoCs with a 5MHz 8051 compatible MPU core low power RTC with digital temperature compensation flash memory and LCD driver Our Single Converter Technology with a 22 bit delta sigma ADC three or four analog inputs digital temperature compensation precision voltage reference and a 32 bit computation engine CE supports a wide range of metering applications with very few external components The 71M6541 2 devices support optional interfaces to the Teridian 71M6x01 series of isolated sensors which offer BOM cost reduction immunity to magnetic tamper and enhanced reliability Other features include an SPI interface advanced power management ultra low power operation in active and battery modes 3 5KB shared RAM and 32 64 128KB of flash memory that can be programmed in the field with code and or data during meter operation and the ability to drive up to six LCD segments per SEG driver pin High processing and sampling rates combined with differential inputs offer a powerful metering platform for residential meters A complete array of code development tools demonstration code and reference designs enable rapid development and certification of meters that meet all ANSI and IEC electricity mete
115. MUX6_SEL 3 0 2102 3 0 Selects the ADC input converted during time slot 6 MUX7 SEL 3 0 2102 7 0 Selects the ADC input converted during time slot 7 MUX8_SEL 3 0 2101 3 0 Selects the ADC input converted during time slot 8 MUX9_SEL 3 0 2101 7 0 Selects the ADC input converted during time slot 9 MUX10 SEL 3 0 2100 3 0 Selects the ADC input converted during time slot 10 ADC_DIV 2200 5 Controls the rate of the ADC and FIR clocks MUX DIV 3 0 2100 7 4 The number of ADC time slots in each multiplexer frame maximum 11 PLL_FAST 2200 4 Controls the speed of the PLL and MCK FIR LEN 1 0 210C 1 Determines the number of ADC cycles in the ADC decimation FIR filter DIFFA E 210C 4 Enables the differential configuration for analog input pins IAP IAN DIFFB E 210C 5 Enables the differential configuration for analog input pins IBP IBN Enables the remote sensor interface transforming pins IBP IBN into a RMT E 2709 3 digital balanced differential pair for communications with the 71M6x01 sensor PRE E 2704 5 Enables the 8x pre amplifier Refer to Table 76 starting on page 111 for more complete details about these I O RAM locations 2 2 8 Delay Compensation When measuring the energy of a phase i e Wh and VARh in a service the voltage and current for that phase must be sampled at the same instant Otherwise the phase differe
116. O52 SEGDIO52 high level 71M6542F G only WAKE falls If OPT RXDIS 1 I O RAM 0x2457 2 wake on SEGDIO55 high WF DIO55 I OPT_RXDIS 0 WAKE falls wake on either edge of OPT_RX WE RST RESET pin driven high WAKE falls WF CSTART WF_RSTBIT im WF_OVF WF_BADVDD WE_RSTBIT RESET bit is set I O RAM 0x2200 3 WAKE falls WF CSTART WF OVF WF BADVDD WF RST E RST pin driven high and the ICE WF ERST interface must be enabled by driving the WERE MS MEC TASSE do WF OVF WF RSTBIT ICE E pin high WF OVF Watchdog WD reset WAKE falls WF CSTART WF RSTBIT E WF_BADVDD WF_RST Coldstart i e after the application of first WAKE falls WF_RSTBIT WF_OVF i id power WF BADVDD WF RST Note WAKE falls implies that the internal WAKE signal has been reset which happens automatically upon entry into LCD mode or SLEEP mode i e when the MPU sets the LCD ONLY bit O RAM 0x28B2 6 or the SLEEP I O RAM 0x28B2 7 bit When the internal WAKE signal resets all wake flags are reset Since the various wake flags are automatically reset when WAKE falls it is not necessary for the MPU to reset these flags before entering LCD mode or SLEEP mode Also other wake events can cause the wake flag to reset as indicated above e g the WF RST flag can also be reset by any of the following flags setting WF CSTART WS RSTBIT WE OVF WE BADVDD 3 4 2 Wake on Timer If the part is in SLP or LCD
117. PB is always configured as an input Connects RX to the WAKE logic and permits RX rising to wake the part See Eves ZEEE 9 E the WAKE description on page 87 for de bounce issues Determines the number of ADC cycles in the ADC decimation FIR filter PLL_FAST 1 FIR LEN 1 0 ADC Cycles 00 141 01 288 10 384 FIR LEN 1 0 210C 2 1 o o RW PLL FAST 0 FIR LEN 1 0 ADC Cycles 00 135 01 276 10 Not Allowed The ADC LSB size and full scale values depend on the FIR LEN 1 0 setting Refer to 6 4 15 ADC Converter on page 149 114 Rev 2 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir Description Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle default 0x00 0x55 Initiate Flash Page Erase cycle Must be proceeded by a write to FLSH PGADR 5 0 SFR 0xB7 7 2 OxAA Initiate Flash Mass Erase cycle Must be proceeded by a write to FLSH MEEN and the ICE port must be enabled Any other pattern written to FLSH_ERASE has no effect Mass Erase Enable 0 Mass Erase disabled default 1 Mass Erase enabled Must be re written for each new Mass Erase cycle Indicates that a timed flash write is pending If another flash write is attempted it is ignored Flash Page Erase Address FLSH PGADR 5 0 Flash Page Address p
118. R OB 41 Table 28 The ENZ Bit Functions SFR Ox94A ssssssssessssseeseeeen nennen nennen nnn nnn nnn nnn nnn nnn nnn 42 Table 29 TCON Bit Functions SFR ON 42 Table 30 The T2CON Bit Functions SER ONCH nennen ener nr nnne nnn 42 Table 31 The IRCON Bit Functions SFR OXCO sssssssssssssseneee mm eene n ehh nnne nnn nnn n nnne nnn 42 Table 32 External MPU Interrupts uuueseeseseeseseeeeeeeeeeennnnnnnnnnnnnnnnnnnnnnnnn nnne nnn nnn nnn nnn rrr nnn 44 Table 33 Interrupt Enable and Flag Bits ccccccccsssssccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaaaaaaaaaa 44 Table 34 Interrupt Priority Level Groups 45 Table 35 Interrupt Priority Levels AE 45 Table 36 Interrupt Priority Registers IPO and IP1 ccccccscscscsscecceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaas 45 Table 37 Interrupt Polling Sequence nennen nennen nnn nnn rrr 46 Table 38 Interrupt Vectors n nr rr re ret oe Ere rari ce es 46 Table 39 Flash Memory ACCESS eee e eee eee eee deen ee EEE EE nnn nnns nnns a 48 Table 40 Flash S CUrity ece r e i 49 Table 41 Clock System Summary seessssesesesesseseeeeee enne nennen nnn eee ee eee nnn nnn eee nnn nnn rrr 51 Table 42 RTC Control Registers artt REEF wae d einen 52 Table 43 I O RAM Registers for RTC Temperature Compensatton rttr ttrt rttr rrr EErEE EEEE 53 Table 44 NV RAM Temperature Table Structure ss
119. R SUPPLY NEUTRAL D LINE E 2 5 MUX and ADC V3P3A V3P3SYS GNDA GNDD 8 IAP PWR MODE w IAN CONTROL ul TERIDIAN WAKE UP s 71M6541D F REGULATOR VBAT VBAT RTC TEMPERATURE BATTERY SENSOR MONITOR VREF RAM SERIAL PORTS oe LCD DISPLAY O mee 8888 8888 TX ENGINE SEG DIO AMR RX LCD DRIVER DIO PULSES D eg PULSES MODUL RX DIO Ta IR ATOR us H 2 POWER FAULT MPU TC or uWire COMPARATOR RTC EEPROM TIMERS HOST SPI INTERFACE ICE 11 5 2010 Figure 35 71M6541D F G with Local Sensors Rev 2 93 71M6541D F G and 71M6542F G Data Sheet 4 4 71M6541D F G Using 71M6x01and Current Shunts Figure 36 shows a typical connection for one isolated and one non isolated shunt sensor using the 71M6x01 Isolated Sensor Interface This configuration implements a single phase measurement with tamper detection using the second current sensor This configuration can also be used to create a split phase meter e g ANSI Form 2S For best performance the IAP IAN current sensor input is configured for differential mode i e DIFFA E 1 I O RAM 0x210C 4 The outputs of the 71M6x01 Isolated Sensor Interface are routed through a pulse transformer which is connected to the pins IBP IBN The IBP IBN pins must be configured for remote sensor communication i e RMT E 1 I O RAM 0x2
120. RAM 0x2406 7 must be O One of the digital or analog signals listed in Table 65 can be selected to be output on the TMUXOUT pin The function of the multiplexer is controlled with the I O RAM register TMUX 5 0 I O RAM 0x2502 5 0 as shown in Table 65 One of the digital or analog signals listed in Table 66 can be selected to be output on the TMUX2OUT pin The function of the multiplexer is controlled with the I O RAM register TMUX2 4 0 I O RAM 0x2503 4 0 as shown in Table 66 The TMUX 5 0 and TMUX2 4 0 I O RAM locations are non volatile and their contents are preserved by battery power and across resets 78 Rev 2 71M6541D F G and 71M6542F G Data Sheet The TMUXOUT and TMUX2OUT pins may be used for diagnostics purposes during the product development cycle or in the production test The RTC 1 second output may be used to calibrate the crystal oscillator The RTC 4 second output provides higher precision for RTC calibration RTCLK may also be used to calibrate the RTC Table 65 TMUX 5 0 Selections TMUX 5 0 Signal Name Description 1 RTCLK 32 768 kHz clock waveform Indicates when the MPU has reset the watchdog timer Can be 9 WD RST dan S monitored to determine spare time in the watchdog timer A CKMPU MPU clock see Table 9 Indicates that the V3P3A pin voltage is 2 3 0 V The V3P3A and D V3AOK bit V3P3SYS pins are expected to be tied together at the PCB level The
121. RTC THR below RTC THR 4 0 289F 4 0 0 Rw The target hours register The RTC T interrupt occurs when RTC MIN becomes equal to RTC TMIN and RTC HR becomes equal to RTC THR Freezes the RTC shadow register so it is suitable for MPU writes When RTC WR is cleared the contents of the shadow register are written to the RTC WR 2890 7 O O RW RTC counter on the next RTC clock 500 Hz When RTC WR is read it returns 1 as long as RTC WR is set It continues to return one until the RTC counter actually updates The RTC interface registers These are the year month day hour minute and second parameters for the RTC The RTC is set by writing to these registers Year 00 and all others divisible by 4 are defined as a leap year RTC SEC 5 0 2893 5 0 Ex es RTC MIN 5 0 2894 5 0 ae G Si RE eo CIE HR 00to23 00 Midnight RTC DAY 2 0 2896 2 0 RW DAY 01to07 01 Sunday RTC DATE 4 0 2897 4 0 DATE 01 to 31 RTC_MO 3 0 2898 3 0 MO 01 to 12 RTC YR 7 0 2899 7 0 YR 00 to 99 Each write operation to one of these registers must be preceded by a write to Ox20A0 RTCA_ADJ 6 0 2504 7 0 40 R W Analog RTC frequency adjust register Rev 2 121 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir Description RTM E 2106 1 O O RW Real Time Monitor enable When O the RTM output is low RTMO 9 8 210D 1 0 0 0
122. RTC pin Board layouts with minimum capacitance from XIN to XOUT require less battery current Good layouts have XIN and XOUT shielded from each other and from LCD and digital signals S Since the oscillator is self biasing an external resistor must not be connected across the crystal 4 17 Meter Calibration Once the Teridian 71M654x energy meter device has been installed in a meter system it must be calibrated A complete calibration includes the following e Establishment of the reference temperature e g typically 22 C e Calibration of the metrology section i e calibration for tolerances of the current sensors voltage dividers and signal conditioning components as well as of the internal reference voltage VREF at the reference temperature e g typically 22 C e Calibration of the oscillator frequency using the RTCA ADJ 7 0 UO RAM register I O RAM 0x2504 The metrology section can be calibrated using the gain and phase adjustment factors accessible to the CE The gain adjustment is used to compensate for tolerances of components used for signal conditioning especially the resistive components Phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies Due to the flexibility of the MPU firmware any calibration method such as calibration based on energy or current and voltage can be implemented It is also possible to implement segment
123. RW 00 Disable EEPROM interface 01 2 Wire EEPROM interface 10 3 Wire EEPROM interface 11 3 Wire EEPROM interface with separate DO DIO3 and DI DIO8 pins 112 Rev 2 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir Description DIO_PV 2457 6 0 RW Causes VARPULSE to be output on pin SEGDIO1 if LCD MAP 1 0 DIO PW 2457 7 0 RW Causes WPULSE to be output on pin SEGDIOO if LCD MAP 0 O DIO PX 2458 7 0 RW Causes XPULSE to be output on pin SEGDIO6 if LCD MAP 6 O DIO PY 2458 6 O R W Causes YPULSE to be output on pin SEGDIO7 if LCD MAP 7 0 EEDATA 7 0 SFR 9E 0 0 RW Serial EEPROM interface data Serial EEPROM interface control Status Read Reset Bit Name Write State Polarity Description a 1 when an illegal command EECTRL 7 0 SFR 9F olo Rw 7 ERROR R 0 Positive is received 6 BUSY R 0 Positive 1 when serial data bus is busy S 1 indicates that the Ds Ree R 1 Positive EEPROM sent an ACK bit Specifies the power equation Inputs Used for Energy Current EQU Watt amp VAR Formula Calculation WSUM VARSUM WOSUM W1SUM I0SQ I1SQ VAROSUM VARISUM SUM SUM 0 Mss POR VA IA VA IB IA IB EQU 2 0 2106 7 5 O 0 RW VA IA ES E 1 1 element 3W 16 VA IA IB 2 IA IB IB VA IA VB IB P amp
124. RX pin to the WAKE logic and permits RX EW RX 28B9 p S bii rising to wake eene See 3 4 1 ee issues SEGDIOA flag bit If SEGDIOA is configured to wake WF DIO4 28B1 2 0 R the part this bit is set whenever SEGDIOA rises It is held in reset if SEGDIO4 is not configured for wakeup SEGDIOB flag bit If SEGDIO52 is configured to wake the part this bit is set whenever SEGDIOB52 is a high e 28B1 1 0 R a It is held in reset if SEGDIO52 is not configured for wakeup 71M6542F G only SEGDIO55 flag bit If SEGDIO55 is configured to wake the part this bit is set whenever SEGDIO55 is a high WELD IOse 28B1 0 i E S de It is held in reset if SEGDIO55 is not cannae for wakeup WF_TMR 28B1 5 0 R Indicates that the Wake timer caused the part to wake up WF_PB 28B1 3 0 R Indicates that the PB pin caused the part to wake WF RX 28B1 4 0 R Indicates that RX pin caused the part to wake oe oed Indicates that the RST pin E RST pin RESET bit I O WF ERST 28BO 3 8 R RAM 0x2200 3 the cold start detector or low voltage on the VBAT pin caused the part to reset WE E See Table 71 for details WF BADVDD 28BO 2 Rev 2 89 71M6541D F G and 71M6542F G Data Sheet Table 71 Clear Events for WAKE flags Flag Wake on Clear Events WF TMR Timer expiration WAKE falls WF PB PB pin high level WAKE falls WF RX Either edge RX pin WAKE falls WF DIO4 SEGDIOA rising edge WAKE falls WF DI
125. S 2 element 3W 36 Delta YOUR YER I B Note 1 Optionally IB may be used to measure neutral current t 71M6542F G only Rev 2 113 71M6541D F G and 71M6542F G Data Sheet Name Location RstWk Dir Description EX_XFER 27000 EX RTCIS 2700 1 EX RTCiIM 2700 2 EX RTCT 2700 3 Interrupt enable bits These bits enable the XFER_BUSY the RTC_1SEC EX SPI 27017 etc The bits are set by hardware and cannot be set by writing a 1 The bits EX EEX 2700 7 O O RW jare reset by writing O Note that if one of these interrupts is to enabled its SS corresponding 8051 EX enable bit must also be set See 2 4 8 Interrupts for EX XPULSE 2700 6 details EX YPULSE 2700 5 EX WPULSE 2701 6 EX VPULSE 2701 5 Connects SEGDIO4 to the WAKE logic and permits SEGDIO4 rising to wake EW DIOR ZE 9 SS the part This bit has no effect unless DIO4 is configured as a digital input Connects SEGDIOB2 to the WAKE logic and permits SEGDIOB2 rising to EW_DIO52 28B3 1 ol Rw geg the part This bit has no effect unless SEGDIO52 is configured as a igital input The SEGDIO52 pin is only available in the 71M6542F G Connects SEGDIO55 to the WAKE logic and permits SEGDIO55 rising to EW_DIO55 28B3 0 O RW wake the part This bit has no effect unless SEGDIO55 is configured as a digital input EW PB 28B3 3 0 RW Connects PB to the WAKE logic and permits PB rising to wake the part
126. SH PEND bit SFR 0xB2 3 is high and the MPU continues to execute commands When the CE code pass ends CE BUSY falls the FLSH_PEND bit falls and the write operation occurs The MPU can query the FLSH PEND bit to determine when the write operation has been completed While FLSH PEND 1 further flash write requests are ignored Updating Individual Bytes in Flash Memory The original state of a flash byte is OxFF all bits are 1 Once a value other than OxFF is written to a flash memory cell overwriting with a different value usually requires that the cell be erased first Since cells cannot be erased individually the page has to be copied to RAM followed by a page erase After this the page can be updated in RAM and then written back to the flash memory Flash Erase Procedures Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence These special pattern sequence requirements prevent inadvertent erasure of the flash memory The mass erase sequence is e Write 1tothe FLSH MEEN bit SFR OxB2 1 e Write the pattern OxAA to the FLSH_ERASE register SFR 0x94 V The mass erase cycle can only be initiated when the ICE port is enabled 48 Rev 2 71M6541D F G and 71M6542F G Data Sheet The page erase sequence is e Write the page address to FLSH PGADR 5 0 SFR 0xB7 7 2 e Write the pattern 0x55 to the FLSH_ERASE register SFR 0x94 Program Security When enabled the
127. SH PGADR 5 0 U U rc EEDATA SFR 9E EEDATA 7 0 EECTRL SFR Op EECTRL 7 0 71M6542F G only 110 Rev 2 71M6541D F G and 71M6542F G Data Sheet 5 2 I O RAM Map Alphabetical Order Table 76 lists I O RAM bits and registers in alphabetical order Bits with a write direction W in column Dir are written by the MPU into configuration RAM Typically they are initially stored in flash memory and copied to the configuration RAM by the MPU Some of the more frequently programmed bits are mapped to the MPU SFR memory space The remaining bits are mapped to the address space Ox2XXX Bits with R read direction can be read by the MPU Columns labeled Rst and Wk describe the bit values upon reset and wake respectively No entry in one of these columns means the bit is either read only or is powered by the NV supply and is not initialized Write only bits return zero when they are read Locations that are shaded in grey are non volatile i e battery backed Table 76 I O RAM Map Functional Order Name Location RstWk Dir Description ADC_E 2704 4 0 O RW Enables ADC and VREF When disabled reduces bias current ADC_DIV controls the rate of the ADC and FIR clocks The ADC_DIV setting determines whether MCK is divided by 4 or 8 0 MCK 4 1 MCK 8 ADC_DIV 2200 5 o o RW The resulting ADC and FIR clock is as shown below PLL FAST 0 PLL FAST 1 MCK 6 291456 MHz 19 660800 MHz ADC_DIV
128. SPI CMD is updated to Oxxx xxxx and an SPI interrupt is generated The exception is if the command byte is 0000 0000 In this case no MPU interrupt is generated and SPI_CMD is not updated Rev 2 75 71M6541D F G and 71M6542F G Data Sheet Table 64 SPI Registers Name Location Rst Wk Dir Description EX SPI 2701 7 SPI interrupt enable bit SPI CMD SFR FD 7 0 SPI command The 8 bit command from the bus master SPI E 270C 4 SPI port enable bit It enables the SPI interface on pins SEGDIO36 SEGDIO39 IE SPI SFR F8 7 SPI interrupt flag Set by hardware cleared by writing a O SPI SAFE 270C 3 Limits SPI writes to SPI CMD and a 16 byte region in DRAM when set No other write operations are permitted SPI STAT 2708 7 0 SPI STAT contains the status results from the previous SPI transaction Bit 7 Ready error The 71M654x was not ready to read or write as directed by the previous command Bit 6 Read data parity This bit is the parity of all bytes read from the 71M654x in the previous command Does not include the SPI STAT byte Bit 5 Write data parity This bit is the overall parity of the bytes written to the 71M654x in the previous command It includes CMD and ADDR bytes Bit 4 2 Bottom 3 bits of the byte count Does not include ADDR and CMD bytes One two and three byte instructions return 111 Bit 1 SPI
129. Symbol Function TCON 7 TF1 Timer 1 overflow flag TCON 6 TRI Not used for interrupt control TCON 5 TFO Timer O overflow flag TCON 4 TRO Not used for interrupt control TCON 3 IE1 External interrupt 1 flag DIO status changed TCON 2 IT1 External interrupt 1 type control bit 0 interrupt on low level 1 interrupt on falling edge TCON 1 IEO External interrupt O flag DIO status changed TCON O0 ITO External interrupt O type control bit 0 interrupt on low level 1 interrupt on falling edge Table 30 The T2CON Bit Functions SFR 0xC8 Bit Symbol Function T2CON 7 Not used T2CON 6 I3FR Polarity control for external interrupt 3 CE_BUSY 0 falling edge 1 rising edge T2CON 5 I2FR Polarity control for external interrupt 2 XPULSE YPULSE WPULSE and VPULSE 0 falling edge 1 rising edge T2CON 4 0 Not used Table 31 The IRCON Bit Functions SFR 0xCO Bit Symbol Function IRCON 7 Not used IRCON 6 Not used IRCON 5 IEX6 1 External interrupt 6 occurred and has not been cleared XFER BUSY RTC 1S RTC 1M or RTC T IRCON 4 IEX5 1 External interrupt 5 occurred and has not been cleared EEPROM or SPI IRCON 3 IEX4 1 External interrupt 4 occurred and has not been cleared VSTAT IRCON 2 IEX3 1 External interrupt 3 occurred and has not been cleared CE BUSY 42 Rev 2 71M6541D F G and 71M6542F G Data Sheet IRCON 1 IEX2 1 External interrupt 2 occurred and has
130. T or VBAT RTC pin is selected by TEMP BSEL I O RAM 0x28A0 7 When TEMP BAT I O RAM 0x28A0 4 is set a battery measurement is performed as part of each temperature measurement The value of the battery reading is stored in register BSENSE 7 0 I O RAM 0x2885 The following equation is used to calculate the voltage measured on the VBAT pin or VBAT RTC pin from the BSENSE 7 0 and STEMP 10 0 values The result of the equation below is in volts VBAT orVBAT _ RTC 3 293V BSENSE 7 0 142 0 0246V STEMP 10 0 0 000276V In MSN mode a 100 pA de passivation load can be applied to the selected battery e selected by the TEMP BSEL bit by setting the BCURR I O RAM 0x2704 3 bit Battery impedance can be measured by taking a battery measurement with and without BCURR Regardless of the BCURR bit setting the battery load is never applied in BRN LCD and SLP modes Rev 2 57 71M6541D F G and 71M6542F G Data Sheet Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices 2 5 7 UART and Optical Interface The 71M6541D F G and 71M6542F G provide two asynchronous interfaces UARTO and UART1 Both can be used to connect to AMR modules user interfaces etc and also support a mechanism for programming the on chip flash memory Referring to Figure 19 UART1 includes an interface to implement an IR optical port The pin OPT TX is designed to directly drive an external LED for transm
131. TERVAL 7 0 is calculated as follows PLS INTERVAL 7 0 Floor Mux frame duration in CK FIR cycles CE pulse updates per Mux frame 4 For example since the 71M654x CE code is written to generate 6 pulses in one integration interval when the FIFO is enabled i e PLS INTERVAL 7 0 0 and that the frame duration is 1950 CK FIR clock cycles PLS INTERVAL 7 0 should be written with Floor 1950 6 4 81 so that the five pulses are evenly spaced in time over the integration interval and the last pulse is issued just prior to the end of the interval See 2 3 6 2 VPULSE and WPULSE PLS INV 210C 0 RAW Inverts the polarity of WPULSE VARPULSE XPULSE and YPULSE Normally these pulses are active low When inverted they become active high PORT E 270C 5 Enables outputs from the pins SEGDIOO SEGDIO15 PORT E 0 after reset and power up blocks the momentary output pulse that would occur on SEGDIOO to SEGDIO15 PRE E 2704 5 Enables the 8x pre amplifier PREBOOT SFRB2 7 Indicates that pre boot sequence is active RCMD 4 0 SFR FC 4 0 When the MPU writes a non zero value to RCMD 4 0 the IC issues a command to the appropriate remote sensor When the command is complete the IC clears RCMD 4 0 RESET 2200 3 When set writes a one to WF_RSTBIT and then causes a reset RFLY_DIS 210C 3 R W Controls how the IC drives the power pulse for the 71M6x
132. TX SEG48 o 1 4 5 Multiuse Pins Configurable as either emulator port pins 36 56 E RST SEG50 when ICE E pulled high or LCD segment drivers when 37 57 E TCLK SEG49 O 4 5 ICE_E tied to GND 160 Rev 2 71M6541D F G and 71M6542F G Data Sheet Pin Pin Name Type Circuit Function 64 pin 100 pin YP ICE Enable When zero E RST E TCLK and E RXTX 39 59 ICE E 2 become SEG50 SEG49 and SEG48 respectively For ES production units this pin should be pulled to GND to disable the emulator port 60 92 TMUXOUT SEG47 6 4 5 Multiple Use Pins Configurable as either multiplexer clock 61 93 TMUX20UT SEG46 output or LCD segment driver using the I O RAM registers Chip Reset This input pin is used to reset the chip into a known state For normal operation this pin is pulled low To 59 91 RESET 2 reset the chip this pin should be pulled high This pin has an internal 30 pA nominal current source pulldown No external reset circuitry is necessary UARTO Input If this pin is unused it must be terminated Pe 2e FAS to V3P3D or GNDD 34 54 TX O 4 UARTO Output Enables Production Test This pin must be grounded in et oy TEST f normal operation Pushbutton Input This pin must be at GNDD when not active 58 90 PB 3 or unused A rising edge sets the WF PB flag It also causes the part to wake up if it is in SLP or LCD mode PB does not have an internal pullup or pul
133. This disables the watchdog and adds another layer of protection against inadvertent Flash corruption e The external power source V3P3SYS V3P3A is at the proper level gt 3 0 VDC e PREBOOT 0 SFR OxB2 7 This validates the state of the SECURE bit SFR OxB2 6 e SECURE 0 This I O RAM register indicates that SPI secure mode is not enabled Operations are limited to SFM Mass Erase mode if the SECURE bit 1 Flash read back is not allowed in Secure mode e FLSH UNLOCKT 3 0 I O RAM 0x2702 7 4 0010 The I O RAM registers SFMM I O RAM 0x2080 and SFMS I O RAM 0x2081 are used to invoke SFM Only the SPI interface has access to these two registers This eliminates an indirect path from the MPU for disabling the watchdog SFMM and SFMS need to be written to in sequence in order to invoke SFM This sequential write process prevents inadvertent entering of SFM The sequence for invoking SFM is e First write to the SFMM I O RAM 0x2080 register The value written to this register defines the SFM mode o OxD1 Mass Erase mode A Flash Mass erase cycle is invoked upon entering SFM o Ox2E Flash Read back mode SFM is entered for Flash read back purposes Flash writes are not be blocked and it is up to the user to guarantee that only previously unwritten locations are written This mode is not accessible when SPI secure mode is set o SFM is not invoked if any other pattern is written to the SFMM register e Next write 0x96 to
134. U DIOO 2456 DIO1 2457 DIO2 2458 NV BITS RESERVED 2500 RESERVED 2501 TMUX 2502 108 Rev 2 71M6541D F G and 71M6542F G Data Sheet Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMUX2 2503 U U U RTC1 2504 U RTCA ADJ 6 0 71M6x01 Interface REMOTE2 2602 RMT RD 15 8 REMOTE1 2603 RMT_RD 7 0 RBITS INT1 E 2700 EX EEX EX XPULSE EX YPULSE EX RTCT U EX RTCIM EX RTCIS EX XFER INT2 E 2701 EX SPI EX WPULSE EX VPULSE U U U U U SECURE 2702 FLSH_UNLOCK 3 0 R FLSH_RDE FLSH_WRE R AnalogO 2704 VREF_CAL VREF_DIS PRE_E ADC_E BCURR SPARE 2 0 VERSION 2706 VERSION 7 0 INTBITS 2707 U INT6 INT5 INT4 INT3 INT2 INT1 INTO FLAGO SFR E8 IE EEX IE XPULSE IE YPULSE IE RTCT U IE RTCIM IE RTC1S IE XFER FLAG1 SFR F8 IE SPI IE WPULSE IE VPULSE U U U U PB STATE STAT SFR F9 U U U PLL OK U VSTAT 2 0 REMOTEO SFR FC PERR RD PERR WR RCMD 4 0 SPI1 SFR FD SPI CMD 7 0 SPIO 2708 SPI STAT 7 0 RCEO 2709 CHOPR 1 0 R R RMT E R R R RTMUX 270A U R R R U TMUXRA 2 0 INFO PG 270B U U U U U U U INFO_PG DIO3 270C U U PORT_E SPI E SPI SAFE U U U NV RAM and RTC NVRAMxx SE NVRAM 0 NVRAM 7F Direct Access WAKE 2880 WAKE TMR 7 0 STEMP1 2881 STEMP 10 3 STEMPO 2882 STEMP 2 0 U U U U U BSENSE 2885
135. WR is high the update of the shadow register is also inhibited During this time the MPU may overwrite the contents of the shadow register When RTC WR is lowered the shadow register is written into the RTC counter on the next 500Hz RTC clock A change bit is included for each word in the shadow register to ensure that only programmed words are updated when the MPU writes a zero to RTC WR Reads of RTC WR returns one until the counter has actually been updated by the register The sub second register of the RTC RTC SBSC I O RAM 0x2892 can be read by the MPU after the one second interrupt and before reaching the next one second boundary The RTC SBSC register is expressed as a count of 1 128 second periods remaining until the next one second boundary Writing 0x00 to RTC SBSC resets the counter re starting the count from 0 to 127 Reading and resetting the sub second counter can be used as part of an algorithm to accurately set the RTC The RTC is capable of processing leap years Each counter has its own output register The RTC chain registers are not affected by the reset pin watchdog timer resets or by transitions between the battery modes and mission mode Rev 2 51 71M6541D F G and 71M6542F G Data Sheet Table 42 RTC Control Registers Name Location Rst Wk Dir Description RTC ADJ 6 0 2504 6 0 00 R W Register for analog RTC frequency adjustment REC Pe SORIA pi dbi Registers for digital RTC adjustm
136. ace are routed through a pulse transformer which is connected to the pins IBP IBN The IBP IBN pins must be configured for remote sensor communication e RMT E 1 I O RAM 0x2709 3 See Figure 5 for the AFE configuration corresponding to Figure 38 i NEUTRAL i i Shunt Note This system is referenced to PHASE A PHASE B LLL KH e LH M NEJTRAL POWER SUPPLY PHASE A o E TERIDIAN gt 71M6XX1 MUX and ADC V3P3A V3P3SYS GNDA GNDD IAP PWR MODE ra iiio Pulse IAN CONTROL TW Lans TERIDIAN WAKE UP lt gt 0WU9 former ul 71M6542F REGULATOR WY Z f VBAT a VBAT_RTC e TEMPERATURE BATTERY gt gt SENSOR MONITOR ue VREF RAM SERIAL PORTS pcs LCD DISPLAY COMPUTE SS 8888 8888 TX ENGINE SEG DIO AMR RX I LCD DRIVER e DIO PULSES EN FLASH nl PULSES MODUL Rx MEMORY F DO gt ATOR d 2 n POWER FAULT MPU TC or uWire COMPARATOR RTC EEPROM TIMERS HOST SPI INTERFACE EH 32 kHz ICE Figure 38 71M6542F G with 71M6x01 Isolated Sensor 96 Rev 2 71M6541D F G and 71M6542F G Data Sheet 4 7 Metrology Temperature Compensation 4 7 1 Voltage Reference Precision Since the VREF band gap amplifier is chopper stabilized as set by the CHOP E 1 0 O RAM 0x2106 3 2 control field the dc offset voltage which is the most significant long term drif
137. age 0 thru 63 that is erased during the Page Erase cycle default 0x00 Must be re written for each new Page Erase cycle Enables timed flash writes When 1 and if CE E 1 flash write requests are stored in a one element deep FIFO and are executed when CE BUSY falls FLSH PEND can be read to determine the status of the FIFO If FLSH_PSTWR 0 or if CE E O flash writes are immediate Program Write Enable 0 MOVX commands refer to External RAM Space normal operation default FLSH PWE SFR B2 0 O O RW 1 MOVX DPTR A moves A to External Program Space Flash DPTR This bit is automatically reset after each byte written to flash Writes to this bit are inhibited when interrupts are enabled Indicates that the flash may be read by ICE or SPI slave FLSH RDE FLSH ERASE 7 0 SFR 94 7 0 olol W FLSH MEEN SFR B2 1 ojoj W FLSH_PEND SFR B2 3 olol R FLSH PGADR S5 0 SFR B7 7 2 olol w FLSH_PSTWR SFR B2 2 0 0 RW FLSH_RDE 2702 2 R SECURE FLSH_UNLOCK 3 0 2702 7 4 o lol Rw Must De a 2 to enable any flash modification See the description of Flash security for more details FLSH WRE 2702 1 R Indicates that the flash may be written through ICE or SPI slave ports Rev 2 115 71M6541D F G and 71M6542F G Data Sheet Name Location Rst Wk Dir Description IE_XFER SFR E8 0 IE_RTC1S SFR E8 1 Interrupt flags for external interrup
138. ample the voltage error and current error combine resulting in approximately 0 5 maximum energy measurement error However this theoretical 0 5 error considers only the voltage reference VREF as an error source In practice other error sources exist in the system The principal remaining error sources are the current sensors shunts or CTs and their corresponding signal conditioning circuits and the resistor voltage divider used to measure the voltage The 71M654x 0 596 grade devices should be used in Class 196 designs allowing sufficient margin for the other error sources in the system 4 7 2 Temperature Coefficients for the 71M654x The equations provided below for calculating TC1 and TC2 apply to the 71M654x 0 5 energy accuracy In order to obtain TC1 and TC2 the MPU reads TRIMT 7 0 I O RAM 0x2309 and uses the TC1 and TC2 equations provided PPMC and PPMC2 are then calculated from TC1 and TC2 as shown The resulting tracking of the reference voltage VREF is within 40 ppm C corresponding to a 0 5 energy measurement accuracy See 4 7 1 Voltage Reference Precision TC1 275 4 95 TRIMT 7 0 TC2 0 557 2 8 10 TRIMT 7 0 21 PPMC TC1 22 4632 TC1 5 1 195 29 PPMC2 S TC2 1150 116 TC2 5 1 195 The coefficients multiplying TC1 and TC2 to obtain PPMC and PPMC2 are derived from the 1 195V ADC voltage reference and scaling performed in the CE as shown above Rev 2 97 71M6541D F G and
139. and 71M6542F G Data Sheet 122 07 us 122 07 us 122 07 us We un Multiplexer Frame 13 x 30 518 us 396 7 us gt 2520 6 Hz MUX DIV 3 0 3 Conversions Settle CK32 32768 Hz MUXSTATE S 0 X 1 X 2 X S Figure 14 Samples from Multiplexer Cycle MUX_DIV 3 0 3 EE VB Ee EE 91 5 91 5 91 5 305 us bus i us i 5 us i 91 5 us rs ae x z Multiplexer Frame 13 x 30 518 us 396 us gt 2520Hz MUX_DIV 3 0 4 Conversions Settle SE 32768 Hz MUXSTATE S 0 1 2 3 S Figure 15 Samples from Multiplexer Cycle MUX DIV 3 0 4 30 Rev 2 71M6541D F G and 71M6542F G Data Sheet 2 4 80515 MPU Core The 71M6541D F G and 71M6542F G include an 80515 MPU 8 bit 8051 compatible that processes most instructions in one clock cycle Using a 4 9 MHz clock results in a processing throughput of 4 9 MIPS The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases Normally a machine cycle is aligned with a memory fetch therefore most of the 1 byte instructions are performed in a single machine cycle MPU clock cycle This leads to an 8x average performance improvement in terms of MIPS over the Intel 8051 device running at the same clock frequency Table 9 sh
140. and 71M6542F G Data Sheet When SPI CSZ rises SPI command bytes that are not of the form x000 0000 update the SPI CMD SFR OxFD register and then cause an interrupt to be issued to the MPU The exception is if the transaction was a single byte In this case the SPI CMD byte is always updated and the interrupt issued SPI CMD is not cleared when SPI CSZ is high The SPI port supports data transfers up to 10 Mb s A serial read or write operation requires at least 8 clocks per byte guaranteeing SPI access to the RAM is no faster than 1 25 MHz thus ensuring that SPI access to DRAM is always possible Table 62 SPI Transaction Fields inl Required Deeg Description Address Yes except for 2 16 bit address The address field is not required if the single byte transaction is a simple SPI command transaction Command Yes 1 8 bit command This byte can be used as a command to the MPU In multi byte transactions the MSB is the R W bit Unless the transaction is multi byte and SPI CMD is exactly 0x80 or 0x00 the SPI CMD register is updated and an SPI interrupt is issued Otherwise the SPI CMD register is unchanged and the interrupt is not issued Status Yes if transaction 1 8 bit status field indicating the status of the previous includes DATA transaction This byte is also available in the MPU memory map as SPI STAT I O RAM 0x2708 register See Table 64 for the contents Data Yes if transaction 1or Theread or write data Add
141. and PPMC2 coefficients for this channel Table 73 GAIN ADJn Compensation Channels Gain Adjustment Output CE RAM Address 71M6541D F G 71M6542F G GAIN ADJO 0x40 VA VA VB GAIN_ADJ1 0x41 IA IA GAIN_ADJ2 0x42 IB IB In the demonstration code temperature compensation behavior is determined by the values stored in the PPMC and PPMC2 coefficients which are setup by the MPU demo code at initialization time from values that are previously stored in EEPROM To disable temperature compensation in the demonstration code PPMC and PPMC2 are both set to zero for each of the three GAIN ADJn channels To enable temperature compensation the PPMC and PPMC2 coefficients are set with values that match the expected temperature variation of the corresponding channel For VREF compensation both the linear coefficient PPMC and the quadratic coefficient PPMC2 are determined for the 71M654x as described in 4 7 2 Temperature Coefficients for the 71M654x For information on determining the PPMC and PPMC2 coefficients for the 7 1M6x01 VREF refer to the 71M6xxx Data Sheet The compensation for the external error sources is accomplished by summing the PPMC value associated with VREF with the PPMC value associated with the external error source to obtain the final PPMC value for the sensor channel Similarly the PPMC2 value associated with VREF is summed with the PPMC2 value associated with the external error source To determine th
142. are designed for sensors with low source impedance RC filters with resistance values higher than those implemented in the Teridian Demo Boards must not be used Please refer to the Demo Board schematics for complete sensor input circuits and corresponding component values Rin Rour V3P3A Figure 31 Resistive Voltage Divider Voltage Sensing lour Rousen lin Figure 34 Differential Resistive Shunt Connections Current Sensing 92 Rev 2 71M6541D F G and 71M6542F G Data Sheet 4 33 71M6541D F G Using Local Sensors Figure 35 shows a 71M6541D F G configuration using locally connected current sensors The IAP IAN current channel may be directly connected to either a shunt resistor or a CT while the IBP IBN channel is connected to a CT and is therefore isolated This configuration implements a single phase measurement with tamper detection using one current sensor to measure the neutral current This configuration can also be used to create a split phase meter e g ANSI Form 2S For best performance both the IAP IAN and IBP IBN current sensor inputs are configured for differential mode i e DIFFA E 1 and DIFFB E 1 YO RAM 0x210C 4 and 0x210C 5 The IBP IBN input must be configured as an analog differential input disabling the remote sensor interface i e RMT E 0 I O RAM 0x2709 3 See Figure 2 for the AFE configuration corresponding to Figure 35 Note This system is referenced to LINE POWE
143. ary data storage CESTATUS represents the Rev 2 127 71M6541D F G and 71M6542F G Data Sheet status flags for the preceding CE code pass CE BUSY interrupt The significance of the bits in CESTATUS is shown in Table 81 Table 81 CESTATUS CE RAM 0x80 Bit Definitions ui E Name Description 31 4 Not Used These unused bits are always zero 3 F0 F0 is a square wave at the exact fundamental input frequency 2 Not Used This unused bit is always zero Normally zero Becomes one when VB remains below SAG THR for 1 SAG B SAG CNT samples Does not return to zero until VB rises above SAG THR Normally zero Becomes one when VA remains below SAG_THR for 0 SAG A SAG CNT samples Does not return to zero until VA rises above SAG THR The CE is initialized by the MPU using CECONFIG Table 82 This register contains in packed form SAG CNT FREQSEL 1 0 EXT PULSE PULSE SLOW and PULSE FAST The CECONFIG bit definitions are given in Table 83 Table 82 CECONFIG Register CE v Address Name Data Description Ox0030DB00 See description of the CECONFIG bits in mee CECONFIG 9x00B0DB007 Table 83 1 Default for CE41A01 71M6541D F G or CE41A04 71M6542F G CE code for use with local sensors 2 Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote sensors Table 83 CECONFIG CE RAM 0x20 Bit
144. bit Selects either the falling edge or low level on input pin to cause an interrupt TCON 1 IEO Interrupt O edge flag is set by hardware when the falling edge on external pin intO is observed Cleared when an interrupt is processed TCON O ITO Interrupt O type control bit Selects either the falling edge or low level on input pin to cause interrupt 2 4 7 WD Timer Software Watchdog Timer There is no internal software watchdog timer Use the standard hardware watchdog timer instead see 2 5 11 Hardware Watchdog Timer 2 4 8 Interrupts The 80515 provides 11 interrupt sources with four priority levels Each source has its own interrupt request flag s located in a special function register TCON IRCON and SCON Each interrupt requested by 40 Rev 2 71M6541D F G and 71M6542F G Data Sheet the corresponding interrupt flag can be individually enabled or disabled by the interrupt enable bits in the IENO SFR OxA8 IEN1 SFR 0xB8 and IEN2 SFR 0x9A Figure 16 shows the device interrupt structure Referring to Figure 16 interrupt sources can originate from within the 80515 MPU core referred to as Internal Sources or can originate from other parts of the 71M654x SoC referred to as External Sources There are seven external interrupt sources as seen in the leftmost part of Figure 16 and in Table 26 and Table 27 i e EXO EX6 Interrupt Overview When an interrupt occurs the MPU vectors to the predetermined
145. cally be averaged out therefore the chopper circuit should always be configured for one of the toggling modes Since the VREF band gap amplifier is chopper stabilized the dc offset voltage which is the most significant long term drift mechanism in the voltage references VREF is automatically removed by the chopper circuit Both the 71M654x and the 71M6x01 feature chopper circuits for their respective VREF voltage reference The general topology of a chopped amplifier is shown in Figure 8 The CROSS signal is an internal on chip signal and is not accessible on any pin or register 20 Rev 2 71M6541D F G and 71M6542F G Data Sheet Figure 8 General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input With all switches as controlled by CROSS an internal signal in the A position the output voltage is Voutp Voutn G Vinp Voff Vinn G Vinp Vinn G Voff With all switches set to the B position by applying the inverted CROSS signal the output voltage is Voutn