Home

FREESCALE SEMICONDUCTOR MMC2107 handbook

1. Bit Number Bit 31 30 29 28 27 26 25 Bit 24 NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 24 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 Bit 16 NIP23 NIP22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 NIP15 14 NIP13 NIP12 11 10 9 NIP8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 NIP7 NIP6 NIP5 NIP4 NIP3 NIP2 NIPO 0 0 0 0 0 0 0 0 Bit 31 30 29 28 27 26 25 Bit 24 FIES1 FIE30 FIE29 FIE28 FIE27 FIE26 FIE25 FIE24 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 Bit 16 FIE23 FIE22 FIE21 FIE20 FIE19 FIE18 FIE17 FIE16 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 FIE15 FIE14 FIE13 FIE12 FIE11 FIE10 FIE9 FIE8 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 FIE7 FIE6 FIE5 FIE4 FIE2 FIE1 FIEO 0 0 0 0 0 0 0 0 Writes have no effect and the access terminates without a transfer error exception 2107 Rev 2 0 68 System Memory For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc System Memory Map Register Map Address Register Name Bit Number Bit 31 30 29 28 27 26 25 B
2. Address Register Name Bit Number Bit 15 14 13 12 11 10 9 Bit 8 0x00c2_0006 Chip Select Control Read 0x00c2_0007 Register 3 CSCR3 2 50 RO PS WWS WE WS2 WS1 50 Write See page 527 Reset 0 0 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 TAEN CSEN Write Reset 0 0 0 0 0 0 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0x00c2_0008 4 Unimplemented Access results in a bus monitor timeout generating an access termination transfer error 0 00 2 Clocks CLOCK Bit 15 14 13 12 11 10 9 Bit 8 0 00 3 0000 Synthesizer Control Read 0x00c3 0001 Register SYNCR LOLRE MFD2 MFD1 MFDO LOCRE RFD2 RFD1 RFDO Write See page 227 Reset 0 0 1 0 0 0 0 1 Bit 7 6 5 4 3 2 1 Bit 0 Read LOCEN DISCLK FWKUP RSVD4 STMPD1 STMPDO RSVD1 RSVDO rite Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 00 3 0002 Synthesizer Status Read PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS 0 0 Register SYNSR Write See page 230 ne Reset Note 1 Note 1 Note 1 Note 2 Note 2 0 0 0 Notes 1 Reset state determined during reset configuration 2 See the LOCKS and LOCK bit descriptions P Current pin state U Unaffected Writes have no effect and the access terminates without a transfer error exception Figure 2 2 Register Summary Sheet 10 of 34 MMC2107 Rev 2 0 Technical Data MOTOROLA System Memory Map 63 For
3. sPPR e 4 SPR 2 0 25110 Baud Rate sPPR e 4 SPRI2 0 10 Baud Rate 000 000 2 16 5 MHz 100 000 10 3 3 MHz 000 001 4 8 25 MHz 100 001 20 1 65 MHz 000 010 8 4 125 MHz 100 010 40 825 MHz 000 011 16 2 06 MHz 100 011 80 412 5 kHz 000 100 32 1 03 MHz 100 100 160 206 25 kHz 000 101 64 515 62 kHz 100 101 320 103 13 kHz 000 110 128 257 81 kHz 100 110 640 51 56 kHz 000 111 256 128 9 kHz 100 111 1280 25 78 kHz 001 000 4 8 25 MHz 101 000 12 2 75 MHz 001 001 8 4 12 MHz 101 001 24 1 375 MHz 001 010 16 2 06 MHz 101 010 48 687 5 kHz 001 011 32 1 03 MHz 101 011 96 343 75 kHz 001 100 64 515 62 kHz 101 100 192 171 88 kHz 001 101 128 257 81 kHz 101 101 384 85 94 kHz 001 110 256 128 9 kHz 101 110 768 42 97 kHz 001 111 512 64 45 kHz 101 111 1536 21 48 kHz 010 000 6 5 5 MHz 110 000 14 2 36 MHz 010 001 12 2 75 MHz 110 001 28 1 18 MHz 010 010 24 1 375 MHz 110 010 56 589 29 kHz 010 011 48 687 5 kHz 110 011 112 296 64 kHz 010 100 96 343 75 kHz 110 100 224 147 32 kHz 010 101 192 171 88 kHz 110 101 448 73 66 kHz 010 110 384 85 94 kHz 110 110 896 36 83 kHz 010 111 768 42 97 kHz 110 111 1792 18 42 kHz 011 000 8 4 13 MHz 111 000 16 2 06 MHz 011 001 16 2 06 MHz 111 001 32 1 03 MHz 011 010 32 1 03 MHz 111 010 64 515 63 kHz 011 011 64 515 63 kHz 111 011 128 257 81 2 011 100 128 257 81 2 111 100 256 128 91
4. Address Register Name Bit Number Bit 7 6 B 4 3 2 1 Bit 0 Port B Clear Output in a E 1 0 0 d 0x00c0_0025 Data Register CLRB Write CLRB7 CLRB6 CLRBS CLRB4 CLRB3 CLRB2 CLRBi CLRBO SOME noc D 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Port C Clear Output Read 0 0 0 i 0 0 00 0 0026 Data Register CLRC Write CLRC7 CLRC6 5 CLRC4 CLRC3 CLRC2 CLRCi CLRCO MS Lut O 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Port D Clear Output Read 0 2 0 0 00 0 0027 Data Register CLRD Write CLRD7 CLRD6 CLRDS CLRD4 CLRD3 CLRD2 CLRDi CLRDO VPE 0 0 0 0 0 0 0 7 6 5 4 3 2 1 Bit 0 Port E Clear Output Read 1 0 d 0 0 i 0 00 0 0028 Data Register CLRE Write CLRE6 CLRES CLRE4 CLRE3 CLRE CLREO HMM O 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Port F Clear Output 0 0 0 0 o 0 0 0 00 0 0029 Register Write CLRF7 CLRF6 CLRF5 CLRF4 CLRF3 CLRF2 CLRF1 CLRFO SE deus 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Port G Clear Output Read 1 0 0 00 0 0004 Data Register CLRG Write CLRG7 CLRG6 CLRG5 CLRG4 CLRG3 CLRG2 CLRGO Qoi D 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Port H Clear Output Read 0 2 0 9 1 0 00 0 002b Data Register CLRH W
5. Address Register Name Bit Number Edge Port EPORT Bit 15 14 13 12 11 10 9 Bit 8 0x00c6_0000 Pin Assignment Read 0x00c6_0001 Register EPPAR EPPA6 5 4 Write See page 264 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read EPPA3 EPPA2 EPPA1 EPPAO Write Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 TES Read EPORT Data Direction EPDD7 EPDD6 EPDD5 EPDD4 EPDD3 EPDD2 EPDD1 EPDDO 0x00c6 0002 Register EPDDR Write g 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read EPORT Port Interrupt EPIE7 EPIE6 EPIE5 EPIE4 EPIE2 EPIE1 EPIEO 0 00 6 0003 Enable Register EPIER Write 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read EPORT Port Data EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 EPDO 0x00c6 0004 Register EPDR Write Sea ei 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 Bit 0 EPORT Port Pin Data Read EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 EPPDO 0x00c6_0005 Register EPPDR Write Reset Bit 7 6 5 4 3 2 1 Bit 0 Read EPORT Port Flag Regiser EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPFO 0x00c6 0006 EPFR Write 269 SERENA a st D 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0006 0007 Reserved Writes have no effect reads return Os and the access terminates without a transfer error exception P Current pin state U Unaffected
6. Source Module Flag Source Description Flag Clearing Mechanism 16 COF Timer channel 0 Write COF 1 or access IC OC if TFFCA 1 17 Timer channel 1 Write 1 to C1F or access IC OC if TFFCA 1 18 C2F Timer channel 2 Write 1 to C2F or access IC OC if TFFCA 1 19 TIM1 C3F Timer channel 3 Write 1 to C3F or access IC OC if TFFCA 1 20 TOF Timer overflow Write TOF 1 or access TIMCNTH L if TFFCA 1 21 PAIF Pulse accumulator input Write PAIF 1 or access PAC if TFFCA 1 22 Pulse accumulator overflow Write PAOVF 1 or access PAC if TFFCA 1 23 COF Timer channel 0 Write COF 1 or access IC OC if TFFCA 1 24 Timer channel 1 Write C1F 1 or access IC OC if TFFCA 1 25 C2F Timer channel 2 Write C2F 1 or access IC OC if TFFCA 1 26 TIM2 C3F Timer channel 3 Write C3F 1 or access IC OC if TFFCA 1 27 TOF Timer overflow Write TOF 1 or access TIMCNTH L if TFFCA 1 28 PAIF Pulse accumulator input Write PAIF 1 or access PAC if TFFCA 1 29 Pulse accumulator overflow Write PAOVF 1 or access PAC if TFFCA 1 30 PIT1 PIF PIT interrupt flag Write PIF 1 or write PMR 31 PIT2 PIF PIT interrupt flag Write PIF 1 or write PMR 32 EPFO Edge port flag 0 Write EPFO 1 33 EPF1 Edge port flag 1 Write EPF1 1 34 EPF2 Edge port flag 2 Write EPF2 1 35 EPF3 Edge port flag 3 Write 1 36 iiid EPF4 Edge p
7. Ti Ti Qt C1 EI em RESUME 0 y r Y PF1 CF1 a ei od 1 c2 c4 Y CF2 Q1 IDLE ACTIVE PAUSE ACTIVE IDLE Q2 IDLE ACTIVE SUSPEND ACTIVE IDLE as 0000 1000 0100 0110 1010 0010 0000 Figure 18 28 CCW Priority Situation 6 Ti Ti Y Y Q C1 C2 C4 Y T2 Y PFI y CF1 c c3 c2 c4 CF2 Qt IDLE ACTIVE QC active IDLE Q2 IDLE ACTIVE SUSPEND ACTIVE IDLE QS 0000 1000 0100 0110 1010 0010 0000 Figure 18 29 CCW Priority Situation 7 MMC2107 Rev 2 0 Technical Data MOTOROLA Queued Analog to Digital Converter QADC 459 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter QADC Situations S8 and S9 Figure 18 30 and Figure 18 31 repeat the same two situations with the RESUME bit set to a 1 When the RES bit is set following suspension queue 2 resumes execution with the aborted CCW not the first CCW in the queue Y Y at C2 c4 Y PF CF1 02 ct c2 2 c3 C4 RESUME 1 CF2 Qt IDLE ACTIVE PAUSE ACTIVE IDLE Q2 IDLE ACTIVE SUSPEND ACTIVE IDLE Qs 0000 1000 0100 0110 1010 0010 0000 Figure 18 30 CCW Priority Situation 8 Ti Ti Y Y at C1
8. Parameter Symbol Min Typ Max Unit Number of erase pulses EPulse 8 8 20 Erase pulse time See Table 9 11 Required Erase Algorithm on page 219 Erase recovery time lE off 4 0 4 8 6 0 us Number of program pulses 500 Note 1 Program pulse time See Table 9 9 Required Programming Algorithm on page 213 Program recovery time 4 0 4 8 6 0 us 1 Maximum pulses vary with Vpp Table 22 10 FLASH EEPROM Module Life Characteristics Vppr 2 7 to 3 6 V Vpp 4 75 to 5 25 V TA T to Ty Parameter Symbol Value Unit Maximum number of guaranteed program erase cycles P E 100 2 Cycles Data retention at average operating temperature of 85 C Retention 10 Years 1 A program erase cycle is defined as switching the bits from 1 0 1 2 Reprogramming of a FLASH array block prior to erase is not required Technical Data MMC2107 Rev 2 0 594 Electrical Specifications For More Information On This Product Go to www freescale com MOTOROLA 2107 Rev 2 0 PULSES Freescale Semiconductor Inc TIME SECONDS Notes 700 600 500 400 300 200 Electrical Specifications FLASH Memory Characteristics 4 85 4 95 5 05 Vpp V 1 Data taken with Vpp 3 6 V at 25 C 2 One page at a time programming of full 128 K array 5 15 5 25 5 35 3 Total
9. Ti 1 Y Y ct T2 T2 PFI Y 1 ct C2 c4 TORI L at IDLE ACTIVE PAUSE ACTIVE IDLE Q2 IDLE TRIG V7 ACTIVE PAUSE TRIG 7 ACTIVE IDLE as 0000 1000 1011 010 0101 1001 1011 0010 0000 Figure 18 27 CCW Priority Situation 5 The remaining situations S6 through S11 show the impact of a queue 1 trigger event occurring during queue 2 execution Queue 1 is higher in priority the conversion taking place in queue 2 is aborted so that there is not a variable latency time in responding to queue 1 trigger events Technical Data MMC2107 Rev 2 0 458 Queued Analog to Digital Converter QADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Queued Analog to Digital Converter QADC Digital Control In situation 6 Figure 18 28 the conversion initiated by the second CCW in queue 2 is aborted just before the conversion is complete so that queue 1 execution can begin Queue 2 is considered suspended After queue 1 is finished queue 2 starts over with the first CCW when the RES resume control bit is set to 0 Situation S7 Figure 18 29 shows that when pause operation is not in use with queue 2 queue 2 suspension works the same way
10. Bit 31 30 29 28 27 26 25 Bit 24 Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 Bit 16 Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Read 0 0 0 0 0 0 RSVD9 RSVD8 Write Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read RSVD7 RSVD6 RSVD5 RSVD4 RSVD3 RSVD2 RSVD1 RSVDO Write Reset 0 0 0 0 0 0 0 0 Writes have no effect and the access terminates without a transfer error exception Figure 10 5 Synthesizer Test Register 2 SYNTR2 Bits 31 10 Bits 31 10 are read only Writing to bits 31 10 has no effect RSVD9 RSVDO Reserved The RSVD bits can be read at any time Writes to these bits update the register values but have no effect on functionality Technical Data MMC2107 Rev 2 0 234 Clock Module MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Module Functional Description 10 8 Functional Description This subsection provides a functional description of the clock module 10 8 1 System Clock Modes The system clock source is determined during reset The value of Vppsvw 1 latched during reset and is expected to remain at that state after reset is negated If Vppsyn is changed during a reset other than power on reset the internal clocks may glitch as the clock source is changed between external clock mode and PLL clock mode Whenev
11. Pin Number 144 Pin Package 100 Pin Package 86 cso 87 59 Vpp 88 60 6 89 61 INT7 90 62 MOSI 91 63 MISO 92 64 VsrBY 93 65 SCK 94 66 SS 95 OE 96 EB3 97 67 SHS PE7 98 EB2 99 68 6 100 EB1 101 EBO 102 69 TEA 103 70 VppH 104 71 PQB3 105 72 PQB2 106 73 1 107 74 PQBO 108 75 PQA4 109 76 PQA3 110 77 PQA1 111 78 112 79 113 80 VRH 114 81 Vssa 115 82 VDDA Technical Data MOTOROLA For More Information On This Product Signal Description Go to www freescale com 113 Freescale Semiconductor Inc Signal Description Table 4 1 Package Pinouts Sheet 5 of 5 Technical Data Pin Number 144 Pin Package 100 Pin Package 116 A22 117 A21 118 83 RESET 119 A20 120 84 RSTOUT 121 A19 122 A18 123 85 VDDSYN 124 86 XTAL 125 87 EXTAL 126 88 VsssvN 127 89 Vss 128 90 CLKOUT 129 91 Vpp 130 92 TCLK 131 A17 132 A16 133 93 TDI 134 A15 135 94 TDO 136 A14 137 A13 138 95 TMS 139 A12 140 96 Vsg 141 97 Vpp 142 98 TRST 143 99 DE 144 100 D31 PA7 MMC2107 Rev 2 0 114 For More Information On This Product Signal Description Go to www freescale com MOTOROLA Freescale Semiconductor Inc Signal Description
12. QS 9 6 Queue 1 Queue 2 States 0000 Queue 1 idle queue 2 idle 0001 Queue 1 idle queue 2 paused 0010 Queue 1 idle queue 2 active 0011 Queue 1 idle queue 2 trigger pending 0100 Queue 1 paused queue 2 idle 0101 Queue 1 paused queue 2 paused 0110 Queue 1 paused queue 2 active 0111 Queue 1 paused queue 2 trigger pending 1000 Queue 1 active queue 2 idle 1001 Queue 1 active queue 2 paused 1010 Queue 1 active queue 2 suspended 1011 Queue 1 active queue 2 trigger pending 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved A queue is in the active state when a valid queue operating mode is selected when the selected trigger event has occurred or when the QADC is performing a conversion specified by a CCW from that queue Technical Data MOTOROLA Queued Analog to Digital Converter QADC 433 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Analog to Digital Converter QADC Only one queue can be active at a time Either or both queues can be in the paused state A queue is paused when the previous CCW executed from that queue had the pause bit set The QADC does not execute any CCWs from the paused queue until a trigger event occurs Consequently the QADC can service queue 2 while queue 1 is paused Only queue 2 can be in the suspended state When a trigger event occurs on queue 1 while queue 2 is execu
13. 154 To BOCK Dagia db p 155 7 6 5 155 7 7 Memory Registers 155 Zl Mamon MaD sd dtp wo TE OPH EC TELA TETTE EF 156 7 7 2 Registers 157 taal Interrupt Control 157 LIAE Interrupt Status 159 7 7 49 Interrupt Force 160 7 7 2 4 Interrupt Pending 162 7 7 2 5 Normal Interrupt Enable Register 163 7 7 2 6 Normal Interrupt Pending Register 164 Fast Interrupt Enable 165 7 7 2 8 Fast Interrupt Pending Register 166 7 7 89 Priority Level Select 167 7 8 Functional Description 167 7 8 1 Interrupt Sources and Prioritization 168 7 8 2 Fast and Normal Interrupt Requests 168 7 8 3 Autovectored Vectored Interrupt Requests 169 Technical Data MOTOROLA Table of Contents 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Technical Data 7 8 4 Interrupt
14. 262 12 31 Wait and Doze Modes 262 12 3 2 Stop ModE Cua ik shee CE E eae d in 263 12 4 Interrupt General Purpose I O Pin Descriptions 263 12 5 Memory and Registers 263 1251 263 12 5 2 JUMP a eh do DRE OE en Re DONC Re eed 264 12 521 EPORT Pin Assignment Register 264 12 5 2 2 Data Direction Register 266 12 5 2 3 Edge Port Interrupt Enable Register 267 125 24 Edge Port Data 268 12 5 2 5 Edge Port Pin Data Register 268 12 5 2 6 Edge Port Flag Register Rr 269 The edge port module EPORT has eight external interrupt pins Each pin can be configured individually as a low level sensitive interrupt pin an edge detecting interrupt pin rising edge falling edge or both ora general purpose input output I O pin See Figure 12 1 Technical Data MOTOROLA Edge Port Module EPORT 261 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Edge Port Module EPORT EPPAR 2n 2n 1 EPFR n TO INTERRUPT CONTROLLER EPPDR n SYNCHRONIZER RISING EDGE OF CLOCK EPIER n EPDRIn EPDDRin e INTx PIN Figure 12 1 EPORT Block Diagram 12 3 Low Power Mod
15. Ti Ti TE Ti Y Y C1 C2 C3 C4 12 72 T2 Y Y y TORI PFI y TORI CF1 Q2 C2 C3 C4 yY y TOR2 PF2 TOR2 CF2 IDLE ACTIVE PAUSE ACTIVE IDLE IDLE ACTIVE PAUSE K V 7 ACTIVE IDLE 0000 1000 0100 0110 0101 1001 0001 0010 0000 Figure 18 25 CCW Priority Situation 3 The next two situations consider trigger events that occur for the lower priority queue 2 while queue 1 is actively being serviced Situation S4 Figure 18 26 shows that a queue 2 trigger event that is recognized while queue 1 is active is saved and as soon as queue 1 is finished queue 2 servicing begins T1 Qt C1 C2 C3 C4 Y T2 CF1 y ci c2 C4 Q2 y CF2 IDLE ACTIVE IDLE IDLE TRIGGERED ACTIVE IDLE 0000 1000 1011 0010 0000 Figure 18 26 CCW Priority Situation 4 Technical Data MOTOROLA Queued Analog to Digital Converter QADC For More Information On This Product Go to www freescale com 457 Freescale Semiconductor Inc Analog to Digital Converter QADC Situation S5 Figure 18 27 shows that when multiple queue 2 trigger events are detected while queue 1 is busy the trigger overrun error bit is set but queue 1 execution is not disturbed Situation S5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in use in either queue
16. 370 07D 370 MMC2107 Rev 2 0 Technical Data MOTOROLA Table of Contents 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Technical Data Section 17 Serial Peripheral Interface Module SPI TOT COMENGE Rk RAE C bob eee dt 371 168 TENOGOUONEL cuu arie ded 372 priret tE a ded da d dd eee EE SE 17 4 Modes of Operation 373 17 5 Block Diagram 373 17 6 Signal lt 374 17 6 1 MISO Master In Slave 374 17 6 2 Master Out Slave 374 17 6 3 Lua cede RR desde 375 FEM Sme 375 17 7 Memory and 375 17 7 1 2222222222222222 376 17 7 2 SPI Control 2 378 17 7 3 SPI Baud Rate 5 379 17 74 SP AOS Rogister 2 2222522222 2 485 56 381 17 7 5 SPI Data 382 17 7 6 SPI Pullup and Reduced Drive Register 383 177 77 SPI Pot Data Register 2 4 44 384 17 7 8 SPI Port Data Dire
17. 397 Section 18 Queued Analog to Digital Converter QADC 18 1 399 401 183 R eh 402 18 4 Block Diagrami 225225 403 18 5 Modes of Operation 404 18 51 404 18 5 2 Stop Mode cian wr 405 Te Roe ROC Ros Je E MR DE 405 18 6 1 Pon OA Pin FUMCHONS au uda d CRGO eR Ge Eoo a cR 406 18 6 1 1 Pod Analog Input lt 5 406 18 6 1 2 QA Digital Input Output Pins 407 186 2 POU Pill 2444 daa dd k En 407 18 6 2 1 Pod Analog Input lt 5 407 185 22 Port QB Digital Input Ping 407 18 6 3 External Trigger Input 5 408 18 6 4 Multiplexed Address Output 408 18 6 5 Multiplexed Analog Input Pins 409 18 6 6 Voltage Reference 409 18 6 7 Dedicated Analog Supply 409 18 7 Memory NND s dpa oO di OR CIERRE 409 18 8 Register 5 411 18 8 1 QADC Module Configuration Register 411 18 8 2 QADC Test Register
18. Instruction IR3 IRO Instruction Summary Selects the boundary scan register while EXTEST 0000 applying fixed values to output pins and asserting functional reset IDCODE 0001 Selects IDCODE register for shift Selects the boundary scan register for SAMPLE PRELOAD 0010 shifting sampling and preloading without disturbing functional operation ENABLE MCU ONCE 0011 Instruction to enable the controller Selects the bypass register while HIGHZ 1001 three stating all output pins and asserting functional reset CLAMP 1100 Selects bypass while applying fixed values to output pins and asserting functional reset BYPASS 1111 Selects the bypass register for data operations amp 0100 Instruction for chip manufacturing purposes 0110 only Reserved 0101 for chip manufacturing purposes only 0111 1000 Reserved 1101 1110 Decoded to select bypass register 1010 1011 1 To exit this instruction the TRST pin must be asserted or power on reset 2 Motorola reserves the right to change the decoding of the unused opcodes in the future 21 5 2 IDCODE Instruction Technical Data The IDCODE instruction selects the 32 bit IDCODE register for connection as a shift path between the TDI pin and the TDO pin This instruction allows interrogation of the MMC2107 to determine its version number and other part identification data The IDCODE register has been implemented in accordance with the IEEE
19. 231 Clock Out and Clock In Relationships 235 Loss f Clock SUMMATY 239 Stop Mode DOMI cs dob ee C4 RR RC EO REOR E OR RICCA EROR A 240 Charge Pump Current and MFD in Normal Mode Operation 245 I O Port Module Memory 250 PEPAR Reset 256 Ports Supported Pin Functions 258 Edge Port Module Memory 263 265 Watchdog Timer Module Memory Map 274 MMC2107 Rev 2 0 38 List of Tables MOTOROLA For More Information On This Product Go to www freescale com 2107 Rev 2 0 Freescale Semiconductor Inc List of Tables Title Page Programmable Interrupt Timer Modules Memory Map 284 Prescaler Select 286 PIT Interrupt 292 coc Rai o Tm 298 Timer Modules Memory 299 Output Compare Action Selection 307 Input Capture Edge 308 Prescaler 5 311 SS DB de al d a eae ae 316 TIMPORT PO 325 Timer Interrupt Requests 326 Sign
20. Bl Control Bits for Each Pin Control Bits for Each Pin 154 015 logical state 177 8 direction control 155 D15 direction control 178 AQ logical state 156 logical state 179 9 direction control 157 A5 direction control 180 023 logical state 158 016 logical state 181 023 direction control 159 16 direction control 182 A10 logical state 160 A6 logical state 183 A10 direction control 161 direction control 184 024 logical state 162 logical state 185 D24 direction control 163 7 direction control 186 D25 logical state 164 D17 logical state 187 D25 direction control 165 D17 direction control 188 A11 logical state 166 018 logical state 189 A11 direction control 167 018 direction control 190 026 logical state 168 D19 logical state 191 D16 direction control 169 019 direction control 192 D27 logical state 170 D20 logical state 193 D27 direction control 171 D20 direction control 194 D28 logical state 172 D21 logical state 195 D28 direction control 173 021 direction control 196 D29 logical state 174 D22 logical state 197 D29 direction control 175 022 direction control 198 D30 logical state 176 A8 logical state 199 D30 direction control MMC2107 Rev 2 0 552 JTAG Test Access Port and OnCE For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc JTAG Test Access Port and On
21. 500 18 122 Inter pt SOUICES ic wens eee seeds Rad 501 Section 19 External Bus Interface Module C 0 cT 503 oaa deed oe CAREER Gp D e ACE SEE RE eRe 504 19 3 Signal DassnbllallB uiicses dade degens hee md dcs d 505 1931 csi ete denen Ue Ea EORR Ao 506 19 3 2 Show Cycle Strobe SHS diiss 506 19 3 3 Transfer Acknowledge 506 19 34 Transfer Error Acknowledge 506 Technical Data MOTOROLA Table of Contents 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 19 3 5 Emulation Mode Chip Selects CSE 1 0 506 19 3 6 Transfer Code MOEA 506 19 3 7 TRO 507 19 3 8 Address Bus 22 0 507 19 3 9 Enable Byte 3 zi der RR e 507 19 3 10 Chip Selects CS 3 0 iia en nee eme e o ce 507 19 3 11 Output Enable ad aces ie Rc a CR 507 19 3 12 Transfer Size 51 1 0 507 19 3 13 Processor Status 5 3 0 507 19 4 Memory and Registers 508 19 5 508 185 Enable Byte Pins 3 0 510 19 7 2 5552 552524 2
22. Bit 7 6 5 4 3 2 1 Bit 0 Read EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPFO Write Reset 0 0 0 0 0 0 0 0 Figure 12 7 EPORT Port Flag Register EPFR EPF 7 0 Edge Port Flag Bits When an EPORT pin is configured for edge triggering its corresponding read write bit in EPFR indicates that the selected edge has been detected Reset clears EPF 7 0 1 Selected edge for INTx pin has been detected 0 Selected edge for INTx pin has not been detected Bits in this register are set when the selected edge is detected on the corresponding pin A bit remains set until cleared by writing a 1 to it Writing 0 has no effect If a pin is configured as level sensitive EPPARx 00 pin transitions do not affect this register MMC2107 Rev 2 0 Technical Data MOTOROLA Edge Port Module EPORT 269 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Edge Port Module EPORT Technical Data MMC2107 Rev 2 0 270 Edge Port Module EPORT MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Technical Data MMC2107 13 1 Contents 13 2 Introduction 2107 Rev 2 0 Section 13 Watchdog Timer Module 132 poo PTT 271 13 3 Modes of Operation 272 13 3 1 272 13 3 2 272 dO ORO
23. 171 7 8 4 1 M CORE Processor 171 7 8 4 2 Interrupt Controller 171 7 8 4 3 Interrupt Source 172 7 8 5 172 Section 8 Static Random Access Memory SRAM 178 EX 175 8 3 Modes of Operation 175 BAY Low Power lt 176 85 Standby Power Supply Pin 176 86 sorrxenaiirdees etcrteredeasd ds 176 8 7 Reset ath a ura ACA ERE dede ers 177 Lus wa RACE ERE d da EO CREER ERE 177 Section 9 Non Volatile Memory FLASH CMFR SOMOS ssis eem muaa aka p as a a a a a ARA 179 co td cere dee aa D dd id 180 E DE oe ee oe owe ee 181 9 4 Modes of Operation 182 9 4 1 Slop ModE OC op do dd Ped dorm ad E GO EE E 182 9 4 2 Disabled 182 95 dede ER oe ERR 183 Se Gloss y of mcr 185 9 7 Registers and Memory 186 9 7 1 Control Registers eeu ci ci 187 9 7 1 1 CMFR Module Configuration Register 188 9 7 1 2 CMFR Module Test Register 193 9 7 1 3 High Voltage Control Register 196 9 7 2 Array A
24. 547 21 12 Low Level TAP OnCE Module 553 21 13 Signal Descriptions uu qux exp rns 52515405004 955 21 13 1 Debug Serial Input TDI 555 21 13 2 Debug Serial Clock 1 555 21 13 3 Debug Serial 555 Technical Data MOTOROLA JTAG Test Access Port and OnCE 533 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc JTAG Test Access Port and OnCE Technical Data 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 2 21 21 13 4 Debug Mode Select 5 556 Soe TES Reset IHSI cauaa ded inda ca eau n acd sede 556 13 6 Debug Event 556 14 Functional Description 556 557 14 2 Controller and Serial Interface 558 14 3 OncElntorace 5 559 14 3 1 Internal Debug Request Input IDR 559 14 3 2 Debug Request 560 14 3 3 CPU Debug Acknowledge 560 14 3 4 Breakpoint Request BRKRQ 560 14 3 5 Address Attributes ADDR ATTR 560 hee PSIA esc 560 14 37
25. 94 4 7221 Chip Configuration 94 3 7 3 2 Reset Configuration Register 97 3 7 3 3 Chip Identification Register 88 3 7 3 4 Chip Test 100 3 8 Functional Description 100 3 8 1 Reset 101 3 8 2 Chip Mode Selection 103 3 8 3 Boot Device Selection 103 3 8 4 Output Pad Strength Configuration 105 3 8 5 Clock Mode 5 105 3 8 6 Internal FLASH Configuration 106 RO pnl exa dod e de dep CR ORO OBERE EE 106 I CEREREM 106 MMC2107 Rev 2 0 Technical Data MOTOROLA Chip Configuration Module CCM 89 For More Information On This Product Go to www freescale com 3 2 Introduction 3 3 Features 3 4 Modes of Operation Technical Data Freescale Semiconductor Inc Chip Configuration Module CCM The chip configuration module CCM controls the chip configuration and mode of operation The CCM performs these operations Selects the chip operating mode Master mode Single chip mode Emulation mode Factory access slave test FAST mode for factory test only Selects external clock or phase lock loop PLL mode with int
26. 507 19 3 10 Chip Selects 5 3 0 507 19 3 11 Output Enable 507 19 3 12 Transfer FOE 507 19 3 13 Processor Status 3 0 507 19 4 Memory and 508 19 5 TSF caua acad eee ee eRe eos M nO 508 19 6 Enable Byte Pins 3 0 510 19 7 Bus Master da oh we ede ee riat trini 510 19 71 Read 511 18 7 1 1 RE RR A 512 19 7 1 2 Optional Wait States 2 512 State X2 sad eh dra snc he 512 pM 016 ct sk ARE eS 513 19 7 2 1 Sel odd sd ee 63 OP ese 4 1E RE 514 19 7 2 2 Optional Wait States 2 514 15758 2 2 eua dish dn Kad od x 514 Technical Data MOTOROLA External Bus Interface Module EBI 503 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Bus Interface Module EBI 19 2 Introduction Technical Data 19 8 Bus Exception Operation 516 19 8 1 Transfer Error 516 19 8 2 Transfer Abort Termination 516 Emulation SUPPOR 516 19 9
27. 93151934 H3TIOHLNOO NOILONYLSNI dvi dVL 1591 SWL 101 3d 2107 Rev 2 0 Technical Data MOTOROLA JTAG Test Access Port and OnCE For More Information On This Product 536 Go to www freescale com Freescale Semiconductor Inc JTAG Test Access Port and OnCE Top Level Test Access Port TAP 21 3 Top Level Test Access Port TAP CAUTION 2107 Rev 2 0 MOTOROLA MMC2107 provides a dedicated user accessible test access port TAP that is fully compatible with the EEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group JTAG The MMC2107 implementation supports circuit board test strategies based on this standard The top level TAP consists of five dedicated signal pins a 16 state TAP controller an instruction register and three data registers a boundary scan register for monitoring and controlling the device s external pins a device identification register and a 1 bit bypass do nothing register The top level TAP provides the ability to 1 Perform boundary scan external pin drive and monitor operations to test circuitry external to the MMC2107 2 Disable the MMC2107 s out
28. 238 10 8 3 2 PLL Loss of LOOK iai doo e edo oad eee 238 10 8 4 Loss of Clock 238 10 8 4 1 Alternate Clock 239 108 42 Loss of Olock 1 242 10 8 5 Clock Operation During 243 1086 uoa ue wd 243 10 8 6 1 Phase and Frequency Detector PFD 245 1086 2 Charge 245 10 8 6 3 Voltage Control Output 246 10 8 6 4 Multiplication Factor Divider MFD 246 Me 22222555 246 19 10 WU nae a ee be CROP e p oa he dae 246 The clock module contains Crystal oscillator OSC e Phase locked loop PLL Reduced frequency divider RFD e Status and control registers Control logic To improve noise immunity the PLL and OSC have their own power supply pins Vppsyw and Vsssyn All other circuits are powered by the normal internal supply pins and Vgs Features of the clock module include e 2 to 10 MHz reference crystal e Support for low power modes Separate clock out signal 2107 Rev 2 0 222 Clock Module MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Module Modes of Operation 10 4 Modes of Op
29. 314 15 7 15 Pulse Accumulator Control Register 315 15 7 16 Pulse Accumulator Flag 317 15 7 17 Pulse Accumulator Counter Registers 318 15 7 18 Timer Port Data 319 15 7 19 Timer Port Data Direction Register 320 15 7 20 Timer Test Register acaso eee ema 321 Technical Data MOTOROLA Table of Contents 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Technical Data 15 8 Functional Description 321 1281 Posciel Oh dux ER cde dee bad e acd di 321 1562 WI CEDE eh ee eO Y aco eoa do 321 15 8 3 Output Compa aca doen arde CR e Eee de de dc ea c 322 15 84 Pulse 323 15 8 4 1 Event Counter Mode 323 15 8 4 2 Gated Time Accumulation Mode 324 15 85 General Purpose I O 325 Wie 326 1 prre 326 15 10 1 Timer Channel Interrupts 326 15 10 2 Pulse Accumulator Overflow 327 15 10 38 Pulse Accumulator Input 927 15 10 4 Timer Overflow TOF 327 Section 16 Serial Communications Interface Modules
30. Analog to Digital Converter QADC 18 8 5 3 QADC Control Register 2 Control register 2 QACR2 is the mode control register for the operation of queue 2 Software specifies the queue operating mode of queue 2 and may enable a completion and or a pause interrupt Most of the bits are typically written once when the software initializes the QADC and not changed afterward Stop mode resets the register 007f Address 0x00ca_000e and 0x00ca_000f Bit 15 14 13 12 11 10 9 Bit 8 Read 0 CIE2 PIE2 MQ212 MQ211 MQ210 MQ29 MQ28 Write SSE2 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20 Write Reset 0 1 1 1 1 1 1 1 Figure 18 10 QADC Control Register 2 QACR2 Read Anytime Write Anytime except stop mode CIE2 Queue 2 Completion Software Interrupt Enable Bit CIE2 enables an interrupt upon completion of queue 2 The interrupt request is initiated when the conversion is complete for the CCW in queue 2 1 Enable an interrupt after an end of conversion for queue 2 0 Disable the queue completion interrupt associated with queue 2 Technical Data MMC2107 Rev 2 0 422 Queued Analog to Digital Converter QADC MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Queued Analog to Digital Converter QADC Register Descriptions PIE
31. 412 18 8 3 P r Data Registers dwcue 412 18 8 4 Port QA Data Direction Register 414 MMC2107 Rev 2 0 Technical Data MOTOROLA Table of Contents 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Technical Data 18 8 5 Control 416 18 8 5 1 Control Register O 416 18 8 5 2 Control Register T ais s osdon ded donde deeded Ea be 419 18 8 53 OADC Control 2 422 18 8 5 Status 5 427 18 8 6 1 QADC Status Register 0 427 18 8 6 2 Status Register 1 436 18 8 7 Conversion Command Word Table 437 18 8 8 224 555554 5 4 441 18 8 8 1 Right Justified Unsigned Result Register 441 18 8 8 2 Left Justified Signed Result Register 442 18 8 8 3 Left Justified Unsigned Result Register 442 18 9 Functional Description cau cose xe grasso Re tes 443 18 9 1 QADC Bus Accessing 443 18 9 2 External MUIpIeXMI sisse aco doo o EROR ae 443 18 9 21 External Multiplexing 443 18 9 2 2 Module Version 444 18 9 2 3 External Multipl
32. Address Register Name Bit Number Bit 15 14 13 12 11 10 9 Bit 8 Ox00ca_000c Control Register 1 Read 0 0 00 000d QACR1 CIE1 PIE1 MQ112 MQ111 MQ110 MQ19 MQ18 D Write SSE1 See page 419 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Ox00ca_000e QADC Control Register 2 Read 0 0 00 0001 QACR2 CIE2 PIE2 MQ212 MQ211 MQ210 MQ29 MQ28 Write SSE2 See page 422 Reset 0 0 0 0 0 0 0 0 Bit7 6 5 4 3 2 1 Bit 0 Read RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20 Write Reset 0 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 Bit 8 0x00ca_0010 QADC Status RegisterO Read 059 058 0 00 _0011 QASRO 1 1 2 2 TOR1 TOR2 See page 427 Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Read 057 056 CWP5 CWP4 CWP3 CWP2 CWP1 CWPO Write Reset 0 0 0 0 0 0 0 0 P Current pin state U Unaffected Writes have no effect and the access terminates without a transfer error exception Figure 2 2 Register Summary Sheet 22 of 34 2107 Rev 2 0 Technical Data MOTOROLA System Memory Map 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Memory Map Address Register Name Bit Number Bit 15 14 13 12 11 10 9 Bit 8 0 00 0012 Sta
33. 0 00 0000 Serial communications interface 1 SCI1 0 00 0000 Serial communications interface 2 SCI2 0 00 0000 Timer 1 TIM1 OxOOcf 0000 Timer 2 TIM2 0x00dO 0000 FLASH registers CMFR 1 See module sections for details of how much of each block is being decoded Accesses to addresses outside the module memory maps and also the reserved area 0 00 1 0000 0xT7fff will not be responded to and will result in a bus monitor transfer error exception 2 The port register space is mirrored repeated in the 64 Kbyte block This allows the full 64 Kbyte block to be decoded and used to execute an external access to a port replacement unit in emulation mode 2107 Rev 2 0 Technical Data MOTOROLA System Memory Map 53 For More Information On This Product Go to www freescale com Address Ports PORTS 0x00c0_0000 0x00c0_0001 0x00c0_0002 0x00c0_0003 0x00c0_0004 0x00c0_0005 0x00c0_0006 P Current pin state Technical Data Freescale Semiconductor Inc System Memory Map 2 4 Register Map Register Name Port A Output Data iz Register PORTA Write 1 See page 25 Reset Port B Output Data Rene Register PORTB Write 1 See page 25 Reset Port C Output Data Register PORTC Write 1 25 Reset Port D Output Data nen Register PORTD Write 251 Reset Port E Output Data neat Registe
34. Analog to Digital Converter QADC Table 18 2 QADC Memory Map Address MSB LSB Access 0x00ca_0000 QADC module configuration register QADCMCR 5 0x00ca 0002 QADC test register QADCTEST 5 0 00 0004 Reserved 0x00ca_0006 Port QA data register PORTQA Port QB data register PORTQB S U 0x00ca 0008 Port QA data direction register DDRQA S U 0x00ca 000a QADC control register 0 QACRO S U 0x00ca 000c QADC control register 1 QACR1 S U 0x00ca 000e QADC control register 2 QACR2 S U 0x00ca 0010 QADC status register 0 QASRO S U 0x00ca 0012 QADC status register 1 QASR1 S U 0 00 0014 3 0x00ca_01fe Reserved 0x00ca 0200 0x00ca_027e Conversion command word table CCW S U 0x00ca 0280 00 02fe Right justified unsigned result register RJURR S U 0x00ca 0300 e 00 037 Left justified signed result register LUSRR S U 0x00ca 0380 41725 0x00ca_03fe Left justified unsigned result register _LJURR S U 1 S CPU supervisor mode access only S U CPU supervisor or user mode access User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error 2 Access results in the module generating an access termination transfer error if not in test mode 3 Read writes have no effect and the access terminates with a transfer error exception Technica
35. 0x00c5_0040 PLSRO PLSR1 PLSR2 PLSR3 S 0 00 5 0044 PLSR4 PLSR5 PLSR6 PLSR7 5 0 00 5 0048 PLSR8 PLSR9 PLSR10 PLSR11 S 0 00 5 004 PLSR12 PLSR13 PLSR14 PLSR15 S 0 00 5 0050 PLSR16 PLSR17 PLSR18 PLSR19 S 0 00 5 0054 PLSR20 PLSR21 PLSR22 PLSR23 5 0 00 5 0058 PLSR24 PLSR25 PLSR26 PLSR27 5 0 00 5 005 PLSR28 PLSR29 PLSR30 PLSR31 S 0 00 5 0060 PLSR32 PLSR33 PLSR34 PLSR35 5 0 00 5 0064 PLSR36 PLSR37 PLSR38 PLSR39 5 0 00 5 0068 through Unimplemented 0 00 5 007 1 S CPU supervisor mode access only S U CPU supervisor or user mode access User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error 2 Accesses to unimplemented address loca