MAXIM MAX1473 handbook
Contents
1. ATION K EN ALU AVLAZCL AMI 315MHz 433MHz ASK Superheterodyne Receiver with Extended Dynamic Range General Description The MAX1473 fully integrated low power CMOS super heterodyne receiver is ideal for receiving amplitude shift keyed ASK data in the 300MHz to 450MHz frequency range Its signal range is from 114dBm to OdBm With few external components and a low current power down mode it is ideal for cost and power sensi tive applications typical in the automotive and consumer markets The chip consists of a low noise amplifier LNA a fully differential image rejection mixer an on chip phase locked loop PLL with integrated voltage controlled oscillator VCO a 10 7MHz IF limiting amplifier stage with received signal strength indicator RSSI and analog baseband data recovery circuitry The MAX1473 also has a discrete one step automatic gain control AGC that drops the LNA gain by 35dB when the RF input signal is greater than 57dBm The MAX1473 is available in 28 TSSOP and 32 thin QFN packages Both versions are specified for the extended 40 C to 85 C temperature range Applications Security Systems Home Automation Local Telemetry Systems Automotive Remote Keyless Entry Garage Door Openers Remote Controls Wireless Sensors Features Optimized for 315MHz or 433MHz ISM Band Operates from Single 3 3V or 5 0V Supplies High Dynamic Range with On Chip AGC Sel2. 0 3V to Vpps 0 3V All Other Pins to AGND 0 3V to Vpp 0 3V Continuous Power Dissipation Ta 70 C 28 Pin TSSOP derate 12 8mW C above 70 C 1025 6mW 32 Pin Thin QFN derate 21 3mW C above 709 2 1702 1mW Operating Temperature Ranges MAXIAYGE 2 40 to 85 Storage Temperature Range 60 C to 150 C Lead Temperature soldering 105 300 C Soldering Temperature 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability DC ELECTRICAL CHARACTERISTICS 3 3V OPERATION Typical Application Circuit 3 0V to 3 6V no RF signal applied Ta 40 C to 85 C unless otherwise noted Typical values are at Vpp 3 3V and Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS Supply Voltage VDD 3 3V nominal supply Supply Current IDD VPWRDN VDD 315MHz 433 2 VPWRDN Shutdown Supply Current VXTALSEL OV IPWRDN nput Voltage
3. the circuit shown in Figure 4 can be used Layout Considerations A properly designed PCB is an essential part of any RF microwave circuit On high frequency inputs and outputs use controlled impedance lines and keep them as short as possible to minimize losses and radia tion At high frequencies trace lengths that are on the order of 4 10 or longer act as antennas Keeping the traces short also reduces parasitic induc tance Generally 1in of a PCB trace adds about 20nH of parasitic inductance The parasitic inductance can have a dramatic effect on the effective inductance of a passive component For example a 0 trace con necting a 100nH inductor adds an extra 10nH of induc tance or 10 To reduce the parasitic inductance use wider traces and a solid ground or power plane below the signal traces Also use low inductance connections to ground on all GND pins and place decoupling capacitors close to all power supply pins 12 MAXIM MAX1473 DATA B SLICER 25 20 26 DATAOUT DSN PDOUT E Figure 4 Using PDOUT for Faster Startup Control Interface Considerations When operating the MAX1473 with a 4 5V to 5 5V supply voltage the PWRDN and AGCDIS pins may be driven by a microcontroller with either 3V or 5V inter face logic levels When operating the MAX1473 with a 3 0V to 3 6V supply the microcontroller must pro duce logic levels which conform to the and VIL specifications in the DC Electri
4. Hz IR mode It can be left open when the 375MHz image rejection setting is desired A 1nF capacitor is recommended in noisy environments Note 3 BER 2 x 10 3 Manchester encoded data rate 4kbps IF bandwidth 280kHz Note 4 Input impedance is measured at the LNAIN pin Note that the impedance includes the 15nH inductive degeneration con nected from the LNA source to ground The equivalent input circuit is 500 in series with 2 2pF Note 5 Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is fnr 10 7MHz 64 for XTALSEL and fnr 10 7MHz 32 for XTALSEL Vpp 5 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Typical Operating Characteristics Typical Application Circuit Vpp 3 3V far 315MHz TA 25 C unless otherwise noted SUPPLY CURRENT SUPPLY CURRENT BIT ERROR RATE vs SUPPLY VOLTAGE vs RF FREQUENCY vs AVERAGE RF INPUT POWER 56 5 70 s 100 55 fer 433MHz z T 6 5 2 25 10 54 Lr L
5. LE 2 Chip Information PROCESS CMOS 14 MAXUM 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Functional Diagram LNASRC AGCDIS LNAOUT MIXIN1 MIXIN2 IRSEL MIXOUT IFINT IFIN2 4 15 6 8 9 m lt 2 x r3 FEN IF LIMITING Q AMPS GAIN CONTROL EJECTION MAXIM 90 A MAX1473 RSSI DIVIDE DATA BY 64 vco FILTER RDF2 Rpr1 100kQ 100kQ PHASE L LOOP DETECTOR FILTER 1 CRYSTAL DRIVER 16 1 XTALSEL XTAL1 XTAL2 PWRDN DATAOUT DSN DSP DF PDOUT OPP Ba 3 2V REG Package Information For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that a or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing per tains to the package regardless of RoHS status LAND PACKAGE TYPE PACKAGE CODE OUTLINE NO PATTERN NO 28 TSSOP U28 1 21 0066 90 0171 32 Thin QFN EP 1325543 214444 90 0001 15 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED Added lead free parts and exposed pad in Ordering Information and Pin Description tables 1 8 Updated Absolute Maximum Ratings AC Electrical Characteristics Pin Des
6. Low nput Voltage High 315MHz 433 2 nput Logic Current High mage Reject Select Note 2 433MHz VinsEL VDD fnr 375MHz ViRsEL Vpp 2 far 315MHz OV DATAOUT Voltage Output Low DATAOUT Voltage Output High RL 5kQ AVLAXL VI 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range DC ELECTRICAL CHARACTERISTICS 5 0V OPERATION Typical Application Circuit 4 5V to 5 5V no RF signal applied TA 40 C to 85 C unless otherwise noted Typical values are at Vpp 5 0V and TA 25 C Note 1 PARAMETER SYMBOL CONDITIONS Supply Voltage VDD 5 0V nominal supply 315MHz 433 2 VPWRDN OV 315MHz VXTALSEL OV fRF 433MHz Supply Current VPWRDN Shutdown Supply Current Input Voltage Low Input Voltage High Input Logic Current High far 433 2 VinsEL VDD Image Reject Select Note 2 far 375 2 VinsEL 2 315MHz VirRsEL OV DATAOUT Voltage Output Low V 9 p OL 5kQ DATAOUT Voltage Output High VoH AC ELECTRICAL CHARACTERISTICS Typical Application Circuit Vpp 3 0V to 3 6V all RF inputs are referenced to 500 far 315 2 TA 40 C to 85 C unless otherwise noted Typical values are at Vpp 3 3V and Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS GENERAL CHARACTERISTIC
7. S Time for valid signal detection after Startup Time j VPWRDN VOH Receiver Input Frequency Maximum Receiver Input Level PRFIN_MAX Modulation depth gt 18dB Sensitivity Note 3 PRFIN MIN Peak power level AGC Hysteresis LNA gain from low to high LNA IN HIGH GAIN MODE Power Gain fnr 433M fnr 375M 315M Normalized to 500 Input Impedance Note 4 ZIN LNA 1dB Compression Point P1dBLNA Input Referred 3rd Order 3 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range AC ELECTRICAL CHARACTERISTICS continued Typical Application Circuit Vpp 3 0V to 3 6V all RF inputs are referenced to 500 f otherwise noted Typical values are at Vpp 3 3V and Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS RF 315MHz TA 40 C to 85 C unless LO Signal Feedthrough to Antenna Noise Figure LNA IN LOW GAIN MODE Input Impedance Note 4 ZIN_LNA 1dB Compression Point P1dBLNA Input Referred 3rd Order Intercept 433 2 Normalized to 375MHz 315 2 LO Signal Feedthrough to Antenna Noise Figure Power Gain Voltage Gain Reduction MIXER AGC enabled depends on tank Q Input Referred 3rd Order IIP3 Intercept Output Impedance ZOUT MIX Noise Figure NFMIX Image R
8. ailed Description The MAX1473 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data Depending on signal power and component selection data rates as high as 100kbps can be achieved The MAX1473 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range ASK modulation uses a difference in amplitude of the carrier to represent logic O and logic 1 data Voltage Regulator For operation with a single 3 0V to 3 6V supply volt age connect AVDD DVDD and Vpps to the supply voltage For operation with a single 4 5V to 5 5V supply voltage connect Vpps to the supply voltage An on chip voltage regulator drives one of the AVDD pins to approximately 3 2V For proper operation DVDD and both the AVDD pins must be connected together Bypass Vpps DVDD and the pin 7 AVDD pin to AGND with O 01uF capacitors and the pin 2 AVDD pin to AGND with a 0 1uF capacitor all placed as close as possible to the pins Low Noise Amplifier The LNA is an NMOS cascode amplifier with off chip inductive degeneration that achieves approximately 16aB of power gain with a 2 0dB noise figure and an IIP3 of 12dBm The gain and noise figure are depen dent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs The off chip inductive degeneration is achieved by connecting an inductor f
9. cal Characteristics Table for the MAX1473 MAXIM 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Table 2 Component Values for Typical Application Circuit COMPONENT VALUE FOR fnr 433MHz VALUE FOR fnr 315MHz DESCRIPTION C1 100pF 100pF 596 C2 2 7pF 4 7pF 0 1pF 20 Depends on XTAL Depends on XTAL 20 20 5 or better 5 or better 5 or better 5 1kQ 5 1kQ Open Open Shor Shor 6 6128MHz 4 7547MHz Crystek or Hong Kong X tal 13 2256MHz 9 5094MHz Crystek or Hong Kong X tal 10 7 2 ceramic filter 10 7 2 ceramic filter Murata Crystal frequencies shown are for 64 VxrTALSEL OV and 32 VxTALSEL VDD Wirewound recommended 13 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Typical Application Circuit IF Vpp IS THEN IS 3 0V TO 3 6V CONNECTED TO Vpp 45V TO 5 5V CREATED BY LDO AVAILABLE AT AVDD PIN 2 SEE TABLE RF INPUT H1 XTAL2 TO FROM pP F PWRDN lt POWER DOWN C DATA OUT POUT gt 473 Vpps XTALSEL AGCD i C5 E SEE MIXER SECTION SEE PHASE LOCKED LOOP SECTION COMPONENT VALUES IN TAB
10. cription Layout Considerations Typical Application Circuit Functional 2 3 4 8 9 12 Diagram and Package Information added Voltage Regulator section to the 13 14 Detailed Description section Updated DC Electrical and AC Electrical Characteristics tables replaced TOC 4 updated Tables 1 and 2 and Figure 1 updated Phase Locked Loop Data Filter 3 5 6 10 13 Data Slicer and Layout Considerations sections Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance 16 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
11. dyne Receiver with Extended Dynamic Range TSSOP Pin Description FUNCTION 1st Crystal Input See the Phase Locked Loop section Positive Analog Supply Voltage For 5V operation pin 2 is the output of an on chip 3 2V low dropout regulator and should be bypassed to AGND with a 0 1uF capacitor as close as possible to the pin Pin 7 must be externally connected to the supply from pin 2 and bypassed to AGND with a 0 01uF capacitor as close as possible to the pin see the Voltage Regulator section and the Typical Application Circuit Low Noise Amplifier Input See the Low Noise Amplifier section Low Noise Amplifier Source for External Inductive Degeneration Connect inductor to ground to set LNA input impedance See the Low Noise Amplifier section Analog Ground Low Noise Amplifier Output Connect to mixer through an LC tank filter See the Low Noise Amplifier section 1st Differential Mixer Input Connect through a 100pF capacitor to Vppa side of the LC tank MIXOUT 2nd Differential Mixer Input Connect through a 100pF capacitor to LC tank filter from LNAOUT Image Rejection Select Pin Set ViRSEL OV to center image rejection at 315MHz Leave IRSEL unconnected to center image rejection at 375MHz Set ViRSEL Vpp to center image rejection at 433MHz 3300 Mixer Output Connect to the input of the 10 7MHz bandpass filter DGND Digital Ground DVDD Positive Digi
12. e AGC switches on the LNA gain reduction resistor The resistor reduces the LNA gain by 35dB thereby reducing the RSSI out put by about 500mV The LNA resumes high gain mode when the RSSI level drops back below 1 45V approxi mately 65dBm at RF input for 150ms The AGC has a hysteresis of 8dB With the AGC function the MAX1473 can reliably produce an ASK output for RF input levels up to OdBm with modulation depth of 18dB Applications Information Crystal Oscillator The XTAL oscillator in the 1473 is designed to pre sent a capacitance of approximately 3pF between the XTAL1 and XTAL2 If a crystal designed to oscillate with a different load capacitance is used the crystal is pulled away from its stated operating frequency intro ducing an error in the reference frequency Crystals designed to operate with higher differential load capac itance always pull the reference frequency higher For example a 4 7547MHz crystal designed to operate with 10pF load capacitance oscillates at 4 7563 2 with the 1473 causing the receiver to be tuned to 315 1MHz rather than 315 0MHz an error of about 1OOKHZ or 320ppm 10 In actuality the oscillator pulls every crystal The crys tal s natural frequency is really below its specified fre quency but when loaded with the specified load capacitance the crystal is pulled and oscillates at its specified frequency This pulling is already accounted for in the specification of t
13. ectable Image Rejection Center Frequency Selectable x64 or x32 fL o fxrAL Ratio Low 5 2mA Operating Supply Current lt 2 5 Low Current Power Down Mode for Efficient Power Cycling 250ys Startup Time Built In 50dB RF Image Rejection Receive Sensitivity of 114dBm 9 9 9 9 9 9 Ordering Information PART MAX1473EUI TEMP RANGE PIN PACKAGE 40 C to 85 C 28 TSSOP MAX1473ETJ 40 C to 85 C 32 Thin QFN EP Denotes a lead Pb free RoHS compliant package EP Exposed pad Functional Diagram and Typical Application Circuit appear at end of data sheet Pin Configurations TOP VIEW XTAL2 PWRDN PDOUT DATAOUT MAXIM MAX1473 005 SP FFB V D D 0 DSN D ALSEL AGCDIS MAXIM MAXIM MAX1473 DS 5 2 ca zs gt a THIN QFN Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim s website at www maxim ic com 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range ABSOLUTE MAXIMUM RATINGS VDD5 TOA GND i ciini apos 0 3V to 6 0V AVDD T AGND roesit ia 0 3V to 4 0V DVDD itoDGN s ioni rtr ana 0 3V to 4 0V AGND tO BOND se orsi 0 1V to 0 1V IRSEL DATAOUT XTALSEL AGCDIS PWRDN to AGND
14. eft unconnected there by eliminating the need for an external Vpp 2 voltage 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Phase Locked Loop The PLL block contains a phase detector charge pump integrated loop filter VCO asynchronous 64x clock divider and crystal oscillator driver Besides the crystal this PLL does not require any external compo nents The VCO generates a low side local oscillator LO The relationship between the RF IF and crystal reference frequencies is given by fxTAL fnr fip 32 x M where M 1 VXTALSEL VDD or 2 VXTALSEL OV To allow the smallest possible IF bandwidth for best sen sitivity the tolerance of the reference must be minimized Intermediate Frequency RSSI The IF section presents a differential 3300 load to pro vide matching for the off chip ceramic filter The six internal AC coupled limiting amplifiers produce an overall gain of approximately 65aB with a bandpass fil ter type response centered near the 10 7MHz IF fre quency with a 3dB bandwidth of approximately 11 5MHz The RSSI circuit demodulates the IF by pro ducing a DC output proportional to the log of the IF sig nal level with a slope of approximately 14 2mV dB see the Typical Operating Characteristics The AGC circuit monitors the RSSI output When the RSSI output reaches 2 05V which corresponds to an RF input level of approximately 57dBm th
15. ejection not Including LNA Tank 433 2 VIRSEL VDD fnr 375MHz ViRSEL 2 far 315MHz ViRsEL OV Conversion Gain 3300 IF filter load INTERMEDIATE FREQUENCY IF Input Impedance Operating Frequency Bandpass response 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level RSSI Gain PREIN lt 120dBm PRFIN gt OdBm AGC enabled AGC Threshold LNA gain from low to high LNA gain from high to low MAXUM 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range AC ELECTRICAL CHARACTERISTICS continued Typical Application Circuit Vpp 3 0V to 3 6V all RF inputs are referenced to 500 far 315 2 TA 40 C to 85 C unless otherwise noted Typical values are at Vpp 3 3V and Ta 25 C Note 1 PARAMETER SYMBOL CONDITIONS DATA FILTER Maximum Bandwidth DATA SLICER Comparator Bandwidth Output Low Voltage CRYSTAL OSCILLATOR VXTALSEL OV VXTALSEL VDD 13 2256 VXTALSEL OV 4 7547 VXTALSEL VDD 9 5094 433 2 Crystal Frequency Note 5 XTAL 315MHz Crystal Tolerance Input Capacitance From each pin to ground Recommended Crystal Load Capacitance Maximum Crystal Load Capacitance Note 1 100 tested at TA 25 C Guaranteed by design and characterization over temperature Note 2 IRSEL is internally set to 375M
16. he load capacitance Additional pulling can be calculated if the electrical parameters of the crystal are known The frequency pulling is given by fp 2Cm 1 2 t Cioad Coase Cspec where fp is the amount the crystal frequency pulled in ppm Cm is the motional capacitance of the crystal Ccase is the case capacitance Cspec is the specified load capacitance Cload is the actual load capacitance When the crystal is loaded as specified i e Cload Cspec the frequency pulling equals zero Data Filter The data filter is implemented as a 2nd order lowpass Sallen Key filter The pole locations are set by the com bination of two on chip resistors and two external capacitors Adjusting the value of the external capaci tors changes the corner frequency to optimize for dif ferent data rates The corner frequency should be set to approximately 1 5 times the fastest expected data rate from the transmitter Keeping the corner frequency near the data rate rejects any noise at higher frequen cies resulting in an increase in receiver sensitivity The configuration shown in Figure 1 can create a Butterworth or Bessel response The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB decade for the two pole filter The Bessel filter has a linear phase response which works well for filtering digital data To calculate the value of C7 and C6 use the following equations alo
17. ng with the coefficients in Table 1 Table 1 Coefficents to Calculate C7 and C6 FILTER TYPE a Butterworth Q 0 707 1 414 1 3617 Bessel Q 0 577 MAKII 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range b C f a m 4 100k r fg where fc is the desired 3dB corner frequency For example choose a Butterworth filter response with a corner frequency of 5kHz 1 000 7 450pF 1 414 100kQ 3 14 5kHz Choosing standard capacitor values changes C7 to 470pF and C6 to 220pF as shown in the Typical Application Circuit MAXIM MAX1473 Rpr2 RDFA 100kQ2 100 Figure 1 Sallen Key Lowpass Data Filter MAXIM MAX1473 DATA Figure 2 Generating Data Slicer Threshold Data Slicer The purpose of the data slicer is to take the analog out put of the data filter and convert it to a digital signal This is achieved by using a comparator and comparing the analog input to a threshold voltage One input is supplied by the data filter output Both comparator inputs are accessible off chip to allow for different methods of generating the slicing threshold which is applied to the second comparator input The suggested data slicer configuration uses a resistor R1 connected between DSN and DSP with a capaci tor C8 from DSN to DGND Figure 2 This configura tion averages the analog output of the filter and sets the thre
18. ntinued Typical Application Circuit Vpp 3 3V far 315MHz TA 25 C unless otherwise noted NORMALIZED IF GAIN vs IF FREQUENCY S11 MAGNITUDE LOG PLOT OF RFIN 11 SMITH PLOT OF RFIN 5 30 MAX1473 toc12 z 5 i ij 1 3 600MHz z Pd x 0 x Na 0 T e 8 5 ur 10 S a 20 RS z 10 30 40 815MHz z 34dB 15 50 60 MN 20 70 1 10 100 10 109 208 307 406 505 604 703 802 901 1000 IF FREQUENCY MHz RF FREQUENCY MHz REGULATOR VOLTAGE PHASE NOISE PHASE NOISE vs REGULATOR CURRENT vs OFFSET FREQUENCY vs OFFSET FREQUENCY AM z 0 i 0 g t 2 3 20 3 0 E 3 40 4 LLI TU T C 60 5 60 gt Lu c 28 22 22 122 5 d 27 E a a 100 a 10 28 120 12 25 140 14 5 15 25 35 45 1 E 05 1 E 04 1 E 03 1 E 02 1 E 01 1 E 00 1 E 01 1 E 05 1 E 04 1 E 03 1 E 02 1 E 01 1 E 00 1 E 01 REGULATOR CURRENT mA OFFSET FREQUENCY MHz OFFSET FREQUENCY MHz 7 2 MAX1473 315MH2 433MHz ASK Superhetero
19. r md G 53 60 cc 3 1 ac z 5 2 21 55 5 fpr 315MHz a a n 2 04 5 0 50 49 45 001 30 31 32 33 34 35 36 250 300 350 400 500 421 120 119 118 117 116 115 114 SUPPLY VOLTAGE V RF FREQUENCY MHz AVERAGE INPUT POWER dBm RSSI AND DELTA SENSITIVITY vs TEMPERATURE RSSI vs RF INPUT POWER vs IF INPUT POWER 2 00 24 iy 24 MAX1473 toc06 PEAK RF INPUT POWER IF BANDWIDTH 280kHz P 102 0 2 BER 22 22 404 IF BANDWIDTH 280kHz E VaGCDIS T 20 20 106 gt 108 fRF 433MHz 18 18 e 2 B 110 6 Vacpis OV 16 DELTA B 112 4 A 114 315MHz RSSI 2 2 116 118 0 0 40 20 20 40 60 80 100 120 140 120 100 40 60 40 20 0 90 70 50 30 10 10 TEMPERATURE C RF INPUT POWER dBm IF INPUT POWER dBm IMAGE REJECTION IMAGE REJECTION SYSTEM GAIN vs FREQUENCY vs RF FREQUENCY vs TEMPERATURE 30 5 55 8 45 2 UPPE 45 315MHz 2 20 SIDEBAND 2 1 50 ME ca 2 5 z 4 50dB IMAGE vivis 45 2 5 q REJECTION BE fnr 375MHz 43 D 40 e 40 E 42 far 375MH fpr 433MHz is MO fa 35 fnr 315MHz 42 RF 315MHz 433MHz 30 30 4 0 5 10 15 20 25 30 280 330 380 430 480 40 45 1 35 60 85 IF FREQUENCY MHz RF FREQUENCY MHz TEMPERATURE C 6 MAKILA 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Typical Operating Characteristics co
20. rom LNASRC to AGND This inductor sets the real part of the input impedance at LNAIN allowing for a more flexible input impedance match such as a typical PCB trace antenna A nominal value for this inductor with a 500 input impedance is 15nH but is affected by PCB trace See the Typical Operating Characteristics for the relationship between the inductance and the LNA input impedance The AGC circuit monitors the RSSI output When the RSSI output reaches 2 05V which corresponds to an RF input level of approximately 57dBm the AGC switches on the LNA gain reduction resistor The resis tor reduces the LNA gain by 35dB thereby reducing the RSSI output by about 500mV The LNA resumes high gain mode when the RSSI level drops back below 1 45V approximately 65dBm at RF input for 150ms The AGC has a hysteresis of 8dB With the AGC func MAKIM tion the MAX1473 can reliably produce an ASK output for RF input levels up to OdBm with a modulation depth of 18dB The LC tank filter connected to LNAOUT comprises L3 and C2 see the Typical Application Circuit Select L3 and C2 to resonate at the desired RF input frequency The resonant frequency is given by TE ED 2 LTOTAL x CTOTAL where LTOTAL L3 LPARASITICS CTOTAL C2 CPARASITICS LPARASITICS and CpaRASITics include inductance and capacitance of the PCB traces package pins mixer input impedance LNA output impedance etc These parasitics at high frequencies canno
21. shold to approximately 5096 of that amplitude With this configuration the threshold automatically adjusts as the analog signal varies minimizing the possibility for errors in the digital data The sizes of R1 and C8 affect how fast the threshold tracks to the analog ampli tude Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate Note that a long string of zeros or 1 s can cause the threshold to drift This configuration works best if a cod ing scheme such as Manchester coding which has an equal number of zeros and 1 s is used To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise hysteresis can be added to the data slicer as shown in Figure 3 For further information on Data Slicer options please refer to Maxim Application Note 3671 Data Slicing Techniques for UHF ASK Receivers MAXIM MAX1473 DATA SLICER 25 DATAOUT DSP Figure 3 Generating Data Slicer Hysteresis 11 2 MAX1473 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Peak Detector The peak detector output PDOUT in conjunction with an external RC filter creates a DC output voltage equal to the peak value of the data signal The resistor pro vides a path for the capacitor to discharge allowing the peak detector to dynamically follow peak changes of the data filter output voltage For faster receiver startup
22. t be ignored and can have a dramatic effect on the tank filter center fre quency Lab experimentation should be done to opti mize the center frequency of the tank Mixer A unique feature of the 1473 is the integrated image rejection of the mixer This device eliminates the need for a costly front end SAW filter for most applica tions Advantages of not using a SAW filter are increased sensitivity simplified antenna matching less board space and lower cost The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10 7MHz IF from a low side injected LO i e fi o fnr fic The image rejection circuit then combines these signals to achieve a minimum 45dB of image rejection over the full temperature range Low side injection is required due to the on chip image rejection architec ture The IF output is driven by a source follower biased to create a driving impedance of 3300 this provides a good match to the off chip 3300 ceramic IF filter The voltage conversion gain is approximately 13dB when the mixer is driving a 3300 load The IRSEL pin is a logic input that selects one of the three possible image rejection frequencies When VIRSEL OV the image rejection is tuned to 315MHz VIRSEL Vpp 2 tunes the image rejection to 375 2 and when VIRSEL VDD the image rejection is tuned to 433MHz The IRSEL pin is internally set to Vpp 2 image rejection at 375MHz when it is l
23. tal Supply Voltage Connect to both of the AVDD pins Bypass to DGND with a 0 01uF capacitor as close as possible to the pin see the Typical Application Circuit AGCDIS AGC Control Pin Pull high to disable AGC Crystal Divider Ratio Select Pin Drive XTALSEL low to select divider ratio of 64 or drive XTALSE high to select divider ratio of 32 1st Differential Intermediate Frequency Limiter Amplifier Input Decouple to AGND with a 1500pF capacitor 2nd Differential Intermediate Frequency Limiter Amplifier Input Connect to the output of a 10 7MHz bandpass filter Data Filter Output Negative Data Slicer Input Noninverting Op Amp Input for the Sallen Key Data Filter Data Filter Feedback Node Input for the feedback of the Sallen Key data filter Positive Data Slicer Input VDD5 5V Supply Voltage Bypass to AGND with a 0 01uF capacitor as close as possible to the pin For 5V operation Vpps is the input to an on chip voltage regulator whose 3 2V output appears at the pin 2 AVDD pin See the Voltage Regulator section and the Typical Application Circuit DATAOUT Digital Baseband Data Output Peak Detector Output Power Down Select Input Drive this pin with a logic high to power on the IC 2nd Crystal Input o Connection Exposed Pad TQFN Only Connect EP to GND MAXIM 315MHz A33MHz ASK Superheterodyne Receiver with Extended Dynamic Range Det
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MAXIM MAX1473 handbook