Home

ATMEL AT91SAM7S512 AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 AT91SAM7S32 handbook

1. Table 3 1 Signal Description List Continued Active Signal Name Function Type Level Comments USB Device Port DDM USB Device Port Data Analog not present on AT91SAM7S32 DDP USB Device Port Data Analog not present on AT91SAM7S32 USART SCKO SCK1 Serial Clock 1 0 SCK1 not present on AT91SAM7S32 TXDO TXD1 Transmit Data 1 0 TXD1 not present on AT91SAM7S32 RXDO RXD1 Receive Data Input RXD1 not present on AT91SAM7S32 RTSO RTS1 Request To Send Output RTS1 not present on AT91SAM7S32 CTSO CTS1 Clear To Send Input CTS1 not present on AT91SAM7S32 DCD1 Data Carrier Detect Input not present on AT91SAM7S32 DTR1 Data Terminal Ready Output not present on AT91SAM7S32 DSR1 Data Set Ready Input not present on AT91SAM7S32 RI Ring Indicator Input not present on AT91SAM7S32 Synchronous Serial Controller TD Transmit Data Output RD Receive Data Input TK Transmit Clock 1 0 RK Receive Clock 1 0 TF Transmit Frame Sync 1 0 RF Receive Frame Sync 1 0 Timer Counter TCLKO TCLK2 External Clock Inputs Input ege REESEN TIOAO TIOA2 I O Line A 1 0 TIOA2 not present on AT91SAM7S32 TIOBO TIOB2 1 O Line B 1 0 TIOB2 not present on AT91SAM7S32 PWM Controller PWMO PWM3 PWM Channels Output SPI MISO Master In Slave Out 1 0 MOSI Master Out Slave In 1 0 SPCK SPI Serial Clock 1 0 NPCSO SPI Peripheral Chip Select O 1 0 Low NPCS1 NPCS3 SPI Peripheral Chip Select 1 to 3
2. Active Signal Name Function Type Level Comments Power VDDIN Voltage and ADC Regulator Power Supply Input Power 3 0 to 3 6V VDDOUT Voltage Regulator Output Power 1 85V nominal VDDFLASH Flash Power Supply Power 3 0V to 3 6V VDDIO I O Lines Power Supply Power 3 0V to 3 6V or 1 65V to 1 95V VDDCORE Core Power Supply Power 1 65V to 1 95V VDDPLL PLL Power 1 65V to 1 95V GND Ground Ground Clocks Oscillators and PLLs XIN Main Oscillator Input Input XOUT Main Oscillator Output Output PLLRC PLL Filter Input PCKO PCK2 Programmable Clock Output Output ICE and JTAG TCK Test Clock Input No pull up resistor TDI Test Data In Input No pull up resistor TDO Test Data Out Output TMS Test Mode Select Input No pull up resistor JTAGSEL JTAG Selection Input Pull down resistor Flash Memory ERASE oe Nun Configuration Bits Erase Input High Pull down resistor Reset Test NRST Microcontroller Reset 1 0 Low Open drain with pull Up resistor TST Test Mode Select Input High Pull down resistor Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output AIC IRQO IRQ1 External Interrupt Inputs Input IRQ1 not present on AT91SAM7S32 FIQ Fast Interrupt Input Input PIO Pulled up input at reset PAO PA31 Parallel IO Controller A O dee a Ge d 6 AT91SAM 7S Series Preliminary mmm 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary
3. SRAMSIZ Size 0 0 0 0 Reserved 0 0 0 1 1K bytes 0 0 1 0 2K bytes 0 0 1 1 Reserved 0 1 0 0 112K bytes 0 1 0 1 4K bytes 0 1 1 0 80K bytes 0 1 1 1 160K bytes 1 0 0 0 8K bytes 1 0 0 1 16K bytes 1 0 1 0 32K bytes 1 0 1 1 64K bytes 1 1 0 0 128K bytes 1 1 0 1 256K bytes 1 1 1 0 96K bytes 1 1 1 1 512K bytes 28 AT91SAM7S Series Preliminary EEE 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary e ARCH Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x39 0011 1001 CAP9 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0101 0000 AT91SAM7Axx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 0111 0001 AT91SAM7XCxx Series 0x72 0111 0010 AT91SAM7SExx Series 0x73 0111 0011 AT91SAM7Lxx Series 0x75 0111 0101 AT91SAM7Xxx Series 0x92 1001 0010 AT91x92 Series OxFO 1111 0001 AT75Cxx Series e NVPTYP Nonvolatile Program Memory Type NVPTYP Memory 0 0 0 ROM 0 0 1 ROMless or on chip Flash 1 0 0 SRAM emulating ROM 0 1 0 Embedded Flash Memory ROM and Embedded Flash Memory 0 1 1 NVPSIZ is ROM size NVPSIZ2 is Flash size e EXT Extension Flag 0 Chip ID has a single register definition without extension 1 An extend
4. USART1 Timer Counter ATT 3l 23 dl TWI Transceiver VDDIN GND VDDOUT VDDCORE VDDIO VDDFLASH ERASE PGMRDY PGMNVALID PGMNOE PGMCK PGMMO PGMM3 PGMDO PGMD15 PGMNCMD PGMENO PGMEN2 DDM DDP PWMO PWM1 PWM2 PWM3 MADOA 1 DDDIAA CLKO TCLK1 TCLK2 TIOAO TIOBO TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK 4 AT91SAM7S Series Preliminary EEE 6175G ATARM 22 Nov 06 Figure 2 2 TDI TDO TMS TCK JTAGSEL TST FIQ IRQO PCKO PCK2 PLLRC XIN XOUT VDDCORE VDDCORE NRST DRXD DTXD RXDO TXDO SCKO RTSO CTSO NPCSO NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADVREF 6175G ATARM 22 Nov 06 AT91SAM7S32 Block Diagram ARM7TDMI Processor 1 8V Voltage Regulator Memory Controller SRAM Embedded Address 8 Kbytes Flash Decoder Controller Abort Misalignment Status Detection Flash 32 Kbytes Peripheral Bridge Peripheral DMA Controller Controller 9 Channels Fast Flash Programming Interface AAA AAA RA 2222221222 ADC Y YYYY AIMEL AT91SAM7S Series Preliminary VDDIN GND VDDOUT VDDCORE VDDIO VDDFLASH ERASE PGMRDY PGMNVALID PGMNOE PGMCK PGMM0 PGMM3 PGMDO PGMD7 PGMNCMD PGMENO PGMEN2 TWCK AMEL 3 Signal Description Table 3 1 Signal Description List
5. Left Aligned CALG PWM_CMRx 0 l 1 Period AMEL 429 AMEL 33 5 3 PWM Controller Operations 33 5 3 1 Initialization Before enabling the output channel this channel must have been configured by the software application e Configuration of the clock generator if DIVA and DIVB are required e Selection of the clock for each channel CPRE field in the PWM_CMRx register e Configuration of the waveform alignment for each channel CALG field in the PWM_CMRx register e Configuration of the period for each channel CPRD in the PWM_CPRDx register Writing in PWM_CPRDx Register is possible while the channel is disabled After validation of the channel the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below e Configuration of the duty cycle for each channel CDTY in the PWM_CDTYx register Writing in PWM_CDTYx Register is possible while the channel is disabled After validation of the channel the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below e Configuration of the output waveform polarity for each channel CPOL in the PWM_CMRx register e Enable Interrupts Writing CHIDx in the PWM_IER register e Enable the PWM channel Writing CHIDx in the PWM_ENA register It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneou
6. Maximum IRQ Latency 3 5 Cycles Peripheral Interrupt Becomes Active A MEL 189 6175G ATARM 22 Nov 06 24 7 3 24 7 3 1 24 7 3 2 24 7 3 3 190 AMEL Normal Interrupt Priority Controller An 8 level priority controller drives the nIRQ line of the processor depending on the interrupt conditions occurring on the interrupt sources 1 to 31 except for those programmed in Fast Forcing Each interrupt source has a programmable priority level of 7 to 0 which is user definable by writ ing the PRIOR field of the corresponding AIC_SMR Source Mode Register Level 7 is the highest priority and level O the lowest As soon as an interrupt condition occurs as defined by the SRCTYPE field of the AIC_SMR Source Mode Register the nIRQ line is asserted As a new interrupt condition might have hap pened on other interrupt sources since the nIRQ has been asserted the priority controller determines the current interrupt at the time the AIC_IVR Interrupt Vector Register is read The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software The current priority level is defined as the priority level of the current interrupt If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read the interrupt with the lowest interrupt source number is serviced first The nIRQ line can be assert
7. Step Programmer Action Device Action Data I O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latches MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Releases MODE and DATA signals Executes command and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input 21 2 4 2 Read Handshaking For details on the read handshaking sequence refer to Figure 21 5 Figure 21 6and Table 21 5 Figure 21 5 AT91SAM7S512 256 128 64 32 Parallel Programming Timing Read Sequence NCMD DN ey RDY O Q NOE O OY NVALID 7 O o paraiso res XX bats UT KX XIN O MODE 3 9 A ADDR XOX XXX 150 AT91SAM7S Series Preliminary E UUO 6175G ATARM 22 Nov 06 m AT91SAM7S Series Preliminary Figure 21 6 AT91SAM 7S32 Parallel Programming Timing Read Sequence NCMD ON D RDY Q NOE O O Y NVALID C O O Y DATA 7 0 Adress IN Data OUT Xx XIN Wopen XARXA EE Table 21 5 Read Handshake Step Programmer Action Device Action DATA I O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal Tristate 6 Waits for NVALID low ee add NS E 7 Clears NVALID signal Output 8 Reads value on DATA Bus Waits for NOE high Output
8. 16 bit Counter Sampling Divider Baud Rate Clock Sampling USCLKS 3 Clock 30 6 1 1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode the selected clock is first divided by CD which is field programmed in the Baud Rate Generator Register US_BRGR The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8 depending on the programming of the OVER bit in US_MR If OVER is set to 1 the receiver sampling is 8 times higher than the baud rate clock If OVER is cleared the sampling is performed at 16 times the baud rate clock The following formula performs the calculation of the Baud Rate SelectedClock 8 2 Over CD Baudrate This gives a maximum baud rate of MCK divided by 8 assuming that MCK is the highest possi ble clock and that OVER is programmed at 1 30 6 1 2 Baud Rate Calculation Example Table 30 2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies This table also shows the actual resulting baud rate and the error Table 30 2 Baud Rate Example OVER 0 Expected Baud Source Clock Rate Calculation Result CD Actual Baud Rate Error MHz Bit s Bit s 3 686 400 38 400 6 00 6 38 400 00 0 00 4915 200 38 400 8 00 8 38 400 00 0 00 5 000 000 38 400 8 14 8 39 062 50 1 70 7 372 800 38 400 12 00 12 38 400 00 0 00 A MEL 309 6175G AT
9. One Modulo n counter providing eleven clocks Two independent linear dividers working on modulo n counter outputs e Independent channel programming Independent enable disable commands Independent clock selection Independent period and duty cycle with double buffering Programmable selection of the output waveform polarity Programmable center or left aligned output waveform 10 11 USB Device Port Does not pertain to AT91SAM7S32 e USB V2 0 full speed compliant 12 Mbits per second e Embedded USB V2 0 full speed transceiver e Embedded 328 byte dual port RAM for endpoints e Four endpoints Endpoint 0 8 bytes Endpoint 1 and 2 64 bytes ping pong Endpoint 3 64 bytes Ping pong Mode two memory banks for isochronous and bulk endpoints e Suspend resume logic 10 12 Analog to digital Converter e 8 channel ADC 10 bit 384 Ksamples sec Successive Approximation Register ADC e 3 3 LSB Integral Non Linearity 2 2 LSB Differential Non Linearity e Integrated 8 to 1 multiplexer offering eight independent 3 3V analog inputs e External voltage reference for better accuracy on low voltage inputs e Individual enable and disable of each channel e Multiple trigger source Hardware or software trigger External trigger pin Timer Counter 0 to 2 outputs TIOAO to TIOA2 trigger e Sleep Mode and conversion sequencer Automatic wakeup on trigger and back to sleep mode after conversions of all e
10. 256 MBytes 14 x 256 MBytes 3 584 MBytes 0x0000 0000 Ox000F FFF 0x0010 0000 0x001F FFF 0x0020 0000 0x002F FFF 0x0030 0000 OxOFFF FFFF OxF000 0000 OXFFF9 FFFF OXFFFA 0000 OxFFFA 3FFF OxFFFA 4000 OxFFFA FFFF OxFFFB 0000 OxFFFB 3FFF OxFFFB 4000 OxFFFB 7FFF OxFFFB 8000 256M Bytes OxFFFB BFFF OxFFFB C000 OxFFFB FFFF OxFFFC 0000 OxFFFC 3FFF OxFFFC 4000 OxFFFC 7FFF OxFFFC 8000 OxFFFC BFFF OxFFFC C000 OxFFFC FFFF OxFFFD 0000 OxFFFD 3FFF OxFFFD 4000 OxFFFD 7FFF OxFFFD 8000 OxFFFD BFFF OxFFFD C000 OxFFFD FFFF OxFFFE 0000 OxFFFE 3FFF OxFFFE 4000 OxFFFF EFFF OxFFFF F000 OxFFFF FFFF AT91SAM7S Series Preliminary Peripheral Mapping AIMEL RE AT91SAM7S512 256 128 64 321 32 Memory Mapping Internal Memory Mapping 1 Flash before Remap SRAM after Remap 1 MBytes Internal Flash Internal SRAM 1 MBytes Reserved 1 MBytes 253 MBytes TCO TC1 TC2 16 Kbytes 16 Kbytes Reserved on AT91SAM7S32 16 Kbytes 16 Kbytes 16 Kbytes Reserved on AT91SAM7S32 16 Kbytes Note 1 Can be Flash or SRAM depending on REMAP System Controller Mapping OxFFFF F000 OxFFFF F1FF OxFFFF F200 OxFFFF F3FF OxFFFF F400 OxFFFF FSFF OxFFFF F600 OxFFFF FBFF OxFFFF FCOO OxFFFF FCFF OxFFFF FDOO OxFFFF FDOF OxFFFF FD20 OxFFFF FC2F OxFFFF FD30 OxFFFF FC3F OxFFFF FD40 OxFFFF FD4F OxFFFF FD60 OxFFFF FC6F
11. AMEL 31 8 3 SSC Receive Clock Mode Register Name SSC_RCMR Access Type Read Write 31 30 29 28 27 26 25 24 PERIOD 23 22 21 20 19 18 17 16 STDDLY 15 14 13 12 11 10 9 8 AAA EA STOP START 7 6 5 4 3 2 1 0 CKG CKI CKO CKS e CKS Receive Clock Selection CKS Selected Receive Clock 0x0 Divided Clock 0x1 TK Clock signal 0x2 RK pin 0x3 Reserved e CKO Receive Clock Output Mode Selection CKO Receive Clock Output Mode RK pin 0x0 None Input only 0x1 Continuous Receive Clock Output 0x2 Receive Clock only during data transfers Output 0x3 0x7 Reserved e CKI Receive Clock Inversion 0 The data inputs Data and Frame Sync signals are sampled on Receive Clock falling edge The Frame Sync signal out put is shifted out on Receive Clock rising edge 1 The data inputs Data and Frame Sync signals are sampled on Receive Clock rising edge The Frame Sync signal out put is shifted out on Receive Clock falling edge CKI affects only the Receive Clock and not the output clock signal e CKG Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved 30 AT91SAM7S Series Preliminary memm 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary e START Receive Start Selection START Receive Start
12. 39 8 4 4 SPI SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode Problem Fix Workaround In Master Mode MSTR bit must be set in SPI_MR register before configuring SPI_CSRx registers 39 8 4 5 SPI Chip Select and Fixed Mode In fixed Mode if a transfer is performed through a PDC on a Chip select different from the Chip select 0 the output spi_size sampled by the PDC will depend on the field BITS Bits per Trans fer of SPI_CSRO register whatever the selected Chip select is For example if SPI_CSRO is configured for a 10 bit transfer whereas SPI_CSR1 is configured for an 8 bit transfer when a transfer is performed in Fixed mode through the PDC on Chip select 1 the transfer will be con sidered as a HalfWord transfer Problem Fix Workaround 574 AT91SAM7S Series Preliminary E UUO 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary If a PDC transfer has to be performed in 8 bits on a Chip select y y as different from 0 the BITS field of the SPI_CSRO must be configured in 8 bits in the same way as the BITS field of the CSRy Register 39 8 4 6 SPI Baudrate Set to 1 When Baudrate is set at 1 i e when serial clock frequency equals the system clock frequency and when the BITS field of the SPI_CSR register number of bits to be transmitted equals an ODD value in this case 9 11 13 or 15 an additional pulse will be generated on output SPCK Everything is OK if the BITS fie
13. 9 1 1 Brownout Detector and Power on Reset 6175G ATARM 22 Nov 06 The AT91SAM7S Series embeds a brownout detection circuit and a power on reset cell Both are supplied with and monitor VDDCORE Both signals are provided to the Flash to prevent any code corruption during power up or power down sequences or if brownouts occur on the VDDCORE power supply The power on reset cell has a limited accuracy threshold at around 1 5V lts output remains low during power up until VDDCORE goes over this voltage level This signal goes to the reset controller and allows a full re initialization of the device The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE Only VDDCORE is monitored as a voltage drop on VDDFLASH or any other power supply of the device cannot affect the Flash When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level Vbot defined as Vbot hyst 2 the brownout output is immediately activated When VDDCORE increases above the trigger level Vbot defined as Vbot hyst 2 the reset is released The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1us The threshold voltage has a hysteresis of about 50 mV to ensure spike free brownout d
14. A maximum of three reflow passes is allowed per component A MEL 523 6175G ATARM 22 Nov 06 AIMEL 38 AT91SAM7S Ordering Information Table 38 1 LQFP QFN Ordering Information Temperature Ordering Code Package Package Type Operating Range AT91SAM7S512 AU 001 LQFP 64 Seen Industrial AT91SAM7S512 MU QFN 64 40 C to 85 C AT91SAM7S256 AU 001 LQFP 64 esi Industrial AT91SAM7S256 MU QFN 64 40 C to 85 C AT91SAM7S128 AU 001 LQFP 64 ete Industrial AT91SAM7S128 MU QFN 64 40 C to 85 C AT91SAM7S64 AU 001 LQFP 64 ee Industrial AT91SAM7S64 MU QFN 64 40 C to 85 C AT91SAM7S321 AU LQFP 64 Green Industrial AT91SAM7S321 MU QFN 64 40 C to 85 C AT91SAM7S32 AU 001 LQFP 48 Pane Industrial AT91SAM7S32 MU QFN 48 40 C to 85 C sau AT91SAM7S Series Preliminary EEE 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary 39 Errata 39 1 Marking All devices are marked with the Atmel logo and the ordering code Additional marking may be in one of the following formats YYWW v XXXXXXXXX ARM where e YY manufactory year e WW manufactory week e V revision e XXXXXXXXX lot number ZZZZZZ YYWW XXXXXXXXX ARM where e ZZZZZZ manufacturing number e YY manufactory year e WW manufactory week e XXXXXXXXX lot number A MEL 525 6175G ATARM 22 Nov 06 AMEL 39 2 AT91SAM7S512 Errata Revisio
15. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit Receive Data Register Full in the Status Register SPI_SR When the received data is read the RDRF bit is cleared If the SPI_RDR Receive Data Register has not been read before new data is received the Overrun Error bit OVRES in SPI_SR is set As long as this flag is set data is loaded in SPI_RDR The user has to read the status register to clear the OVRES bit Figure 28 5 on page 267 shows a block diagram of the SPI when operating in Master Mode Fig ure 28 6 on page 268 shows a flow chart describing how transfers are handled AT91SAM7S Series Preliminary sa 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary 28 6 3 1 Master Mode Block Diagram Figure 28 5 Master Mode Block Diagram MCK Baud Rate Generator SPI Clock SPCK SPI_RDR PCS NPCS3 Ki Current NPCS2 Peripheral NPCS1 NPCSO SR woen gt A MEL 267 6175G ATARM 22 Nov 06 AMEL 28 6 3 2 Master Mode Flow Diagram Figure 28 6 Master Mode Flow Diagram S SPI Enable NPCS defines the current Chip Select CSAAT DLYBS DLYBCT refer to the fields of the al Chip Select Register corresponding to the Current Chip Select 0 0 When NPCS is OxF CSAAT is 0 Fixed 0 peripheral Variable 1 peripheral NPCS SPI_TDR PCS NPCS SPI_MR PCS NPCS OxF y Fixed p
16. a _ D wo mb IW mb o oO 00 O al A wo IW o TXDATA es TXDATA Master or Slave Transmit Holding Data 302 AT91SAM7S Series Preliminary EEE 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary 30 Universal Synchronous Asynchronous Receiver Transceiver USART 30 1 Overview 6175G ATARM 22 Nov 06 The Universal Synchronous Asynchronous Receiver Transceiver USART provides one full duplex universal synchronous asynchronous serial link Data frame format is widely programma ble data length parity number of stop bits to support a maximum of standards The receiver implements parity error framing error and overrun error detection The receiver time out enables handling variable length frames and the transmitter timeguard facilitates communications with slow remote devices Multidrop communications are also supported through address bit han dling in reception and transmission The USART features three test modes remote loopback local loopback and automatic echo The USART supports specific operating modes providing interfaces on RS485 buses with 1SO7816 T 0 or T 1 smart card slots infrared transceivers and connection to modem ports The hardware handshaking feature enables an out of band flow control by automatic manage ment of the pins RTS and CTS The USART supports the connection to the Peripheral DMA Controller which enables data transfers to the transmitter and from th
17. 39 2 4 3 SPI SPCK Behavior in Master Mode SPCK pin can toggle out before the first transfer in Master Mode Problem Fix Workaround In Master Mode MSTR bit must be set in SPI_MR register before configuring SPI_CSRx registers 39 2 4 4 SPI Chip Select and Fixed Mode In fixed Mode if a transfer is performed through a PDC on a Chip select different from the Chip select 0 the output spi_size sampled by the PDC will depend on the field BITS Bits per Trans fer of SPI_CSRO register whatever the selected Chip select is For example if SPI_CSRO is configured for a 10 bit transfer whereas SPI_CSR1 is configured for an 8 bit transfer when a transfer is performed in Fixed mode through the PDC on Chip select 1 the transfer will be con sidered as a HalfWord transfer Problem Fix Workaround If a PDC transfer has to be performed in 8 bits on a Chip select y y as different from 0 the BITS field of the SPI_CSRO must be configured in 8 bits in the same way as the BITS field of the CSRy Register 39 2 4 SPI Baudrate Set to 1 When Baudrate is set at 1 i e when serial clock frequency equals the system clock frequency and when the BITS field of the SPI_CSR register number of bits to be transmitted equals an ODD value in this case 9 11 13 or 15 an additional pulse will be generated on output SPCK Everything is OK if the BITS field equals 8 10 12 14 or 16 and Baudrate 1 Problem Fix Workaround None 39 2 4 6 SPI Disable In Slav
18. 39 3 AT91SAM7S256 Errata Manufacturing Number 58818C 39 3 1 39 3 1 1 39 3 2 39 3 2 1 39 3 3 39 3 3 1 532 Chip ID Refer to Section 39 1 Marking on page 525 Important Section 39 3 13 1 WDT The Watchdog Timer May Lock the Device in a Reset State Wrong Chip ID Value The Chip ID is 0x270D0940 instead of 0x270B0940 Problem Fix Workaround None Master Clock MCK MCK Limited Master Clock Frequency Ranges If the Flash is operating without wait states the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 19 MHz If the Flash is operating with one wait state the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 19 MHz If the Flash is operating with two wait states the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 25 MHz If the Flash is operating with three wait states the frequency of the Master Clock MCK must be lower than 3 MHz or higher than 38 MHz If these constraints are not respected the correct operation of the system cannot be guaranteed and either data or prefetch abort might occur The maximum operating frequencies at 30 MHz 0 Wait States and 55 MHz 1 Wait State as stated in Table 36 24 Embedded Flash Wait States on page 512 are still applicable Note Itis not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency with only 1 wait state Problem Fix
19. 4 The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoints UDP_ CSRx register 5 The microcontroller carries out data received from the endpoint s memory to its mem ory Data received is available by reading the endpoints UDP_ FDRx register 6 The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BKO in the endpoint s UDP_ CSRx register 7 A new Data OUT packet can be accepted by the USB device Figure 34 9 Data OUT Transfer for Non Ping pong Endpoints Microcontroller Transfers Data Host Sends Data Payload Host Sends the Next Data Payload Host Resends the Next Data Payload gt lt gt q Leg RX_DATA_BKO UDP_CSRx La Interrupt Pending t i han Cleared by Firmware tb BD 2 did adas Data Payload Written in FIFO Content Daaouri A Daaouri ooo Dmaour Content Data OUT 1 Data OUT 1 Data OUT 2 Written by USB Device Microcontroller Read Written by USB Device An interrupt is pending while the flag RX_DATA_BKO is set Memory transfer between the USB device the FIFO and microcontroller memory can not be done after RX_DATA_BKO has been cleared Otherwise the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO a54 AT91SAM7S Series Preliminary E UUO 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary 34 5 2 7 Using Endpoints With Ping po
20. Lines Considerations sisi is 14 611 JTAG PON PINS EE 14 02 TSU PIM daa iia 14 E HE 14 6 4 ERASE GIE 14 6 5 PIO Controller A LINCS sssri aiiiar neiaie aaan EEA 14 6 6 VO Line Drive Levels vecioisicaria att 15 7 Processor and Architecture sssssennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 16 7 1 ARM7TDMI Processor coooocccccccnococcnncononnncnnnnnnnnnnnnnnnnncnnnnnnnncrn rra nn nr nn nan rn rrrnannnncin 16 7 2 Debug and Test Features AANEREN 16 73 Memory Controller icon rr ca 16 7 4 Peripheral DMA Controller A 17 DT MEMOS A A a a 18 8 1 AT91SAM7S8512 conooocccccononnnnnnnonononnnnonnnnnnnnnonnnonnnnonnnnrnrnnonnnnrnnnnnnnnrrnnrinnnnrrrnrinnnnnnnos 18 BZ ATITSAM7S256 e eskesgeEANASERERRENEEEEEREN NANREN ii RASAT REN 18 B ATOTSAM7S 128 inicia aueren ENEE ENEE EE TEAs EPE EE 18 A MEL 593 6175G ATARM 22 Nov 06 AMEL 8 4 ATITSAMISGA E 19 8 5 AT918SAM78321 32 A 19 8 6 Memory Mapping vv TE eE 21 8 7 Embedded Flash ciionoinioconmiiconit a aire 22 8 8 Fast Flash Programming Interface AAA 25 8 9 SAM BA Boot Assistant c ococcnncconnccccnnncccnnnccnnnnncononn cnn rca carr rnn rca rra rra 25 9 Syst m Controller ss 0 iaa iii 26 9 1 Reset Controller econ dc 29 9 2 Glock Generator siii ida oi 30 9 3 Power Management Controller o ooocnnccnnnicinnncccnnoconnoncccnancnnonrnc nn nar cc nn nn narrar 30 9 4 Advanced Interrupt Controller oonncnnnncnnniconnncccnncccnnnnccnnoncnnnrnn narrar rana 31 9
21. O The I O line is at level O 1 The l O line is at level 1 15 6 14 PIO Controller Interrupt Enable Register Name PIO_IER Access Type Write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 lps P ms Pze Pm Po P Pae 7 6 5 4 3 2 1 0 Ps rs ma IS mn Po PO P31 Input Change Interrupt Enable 0 No effect 1 Enables the Input Change Interrupt on the I O line 96 AT91SAM7S Series Preliminary EEE 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary 15 6 15 PIO Controller Interrupt Disable Register Name PIO_IDR Access Type Write only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P20 15 14 13 12 11 10 9 8 pa og e Lem 7 6 5 4 3 2 1 0 PO P31 Input Change Interrupt Disable 0 No effect 1 Disables the Input Change Interrupt on the I O line 15 6 16 PIO Controller Interrupt Mask Register Name PIO_IMR Access Type Read only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 EL Pig Se PB 7 6 5 4 3 2 1 0 Pr Ps Ps Pa Pa Paz In Po PO P31 Input Change Interrupt Mask 0 Input Change Interrupt is disabled on the I O line 1 Input Change Interrupt is enabled on the I O line N AMEL 6175G ATARM 22 Nov 06 AMEL 15 6 17 PIO Controller Interrupt Status Register Name PIO_ISR Access Type Read only 31 30 29 28 27 26 25 24 23 22 21 20 19
22. SPCK SPlo SPI MISO 0 SL gt MOSI Figure 36 4 SPI Master mode with CPOL 0 and NCPHA 1 or CPOL 1 and NCPHA 0 SPCK Sp SPI gt MISO SPl5 gt MOSI Figure 36 5 SPI Slave mode with CPOL 0 and NCPHA 1 or CPOL 1 and NCPHA 0 SPCK Sp MISO Sy SPI SPl gt lt gt MOSI sn AT91SAM 7S Series Preliminary E UUO 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary Figure 36 6 SPI Slave mode with CPOL NCPHA 0 or CPOL NCPHA 1 SPCK SPly MISO x SPlio SEI gt lt gt MOSI Table 36 23 SPI Timings Symbol Parameter Conditions Min Max Units 3 3V domain 28 5 Dell ns SPlo MISO Setup time before SPCK rises master 1 8V domain 38 topycx 2 ns 3 3V domain 0 ns SPI MISO Hold time after SPCK rises master 1 8V domain 0 ns 3 3V domain 2 ns SPI SPCK rising to MOSI Delay master 1 8V domain 7 ns 3 3V domain 26 5 Dell ns SPI MISO Setup time before SPCK falls master 1 8V domain 44 topmcx 2 ns 3 3V domain 0 ns SPI MISO Hold time after SPCK falls master 1 8V domain 0 ns 3 3V domain 2 ns SPI SPCK falling to MOSI Delay master 1 8V domain 2 5 ns 3 3V domain 28 ns SPl SPCK falling to MISO Delay slave 1 8V domain 44 ns 3 3V domain 2 ns SPI MOSI Setup time before SPCK rises slave 1 8V domain
23. 0x0 Continuous as soon as the receiver is enabled and immediately after the end of transfer of the previous data 0x1 Transmit start 0x2 Detection of a low level on RF signal 0x3 Detection of a high level on RF signal 0x4 Detection of a falling edge on RF signal 0x5 Detection of a rising edge on RF signal 0x6 Detection of any level change on RF signal 0x7 Detection of any edge on RF signal 0x8 Compare 0 0x9 0xF Reserved e STOP Receive Stop Selection O After completion of a data transfer when starting with a Compare 0 the receiver stops the data transfer and waits for a new compare 0 1 After starting a receive with a Compare O the receiver operates in a continuous mode until a Compare 1 is detected e STTDLY Receive Start Delay If STTDLY is not 0 a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception When the Receiver is programmed to start synchronously with the Transmitter the delay is also applied Note It is very important that STTDLY be set carefully If STTDLY must be set it should be done in relation to TAG Receive Sync Data reception PERIOD Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal If 0 no PERIOD signal is generated If not 0 a PERIOD signal is generated each 2 x PERIOD 1 Receive Clock A MEL 371 6175G ATARM 22 Nov 06 AMEL 31 8
24. 0x0014 Output Disable Register PIO_ODR Write only 0x0018 Output Status Register PIO_OSR Read only 0x0000 0000 0x001C Reserved 0x0020 Glitch Input Filter Enable Register PIO_IFER Write only 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write only 0x0028 Glitch Input Filter Status Register PIO_IFSR Read only 0x0000 0000 0x002C Reserved 0x0030 Set Output Data Register PIO_SODR Write only 0x0034 Clear Output Data Register PIO_CODR Write only 0x0038 Output Data Status Register PIO_ODSR Read only 0x0000 0000 0x003C Pin Data Status Register PIO_PDSR Read only 0x0040 Interrupt Enable Register PIO_IER Write only 0x0044 Interrupt Disable Register PIO_IDR Write only 0x0048 Interrupt Mask Register PIO_IMR Read only 0x00000000 0x004C Interrupt Status Register PIO_ISR Read only 0x00000000 0x0050 Multi driver Enable Register PIO_MDER Write only 0x0054 Multi driver Disable Register PIO_MDDR Write only 0x0058 Multi driver Status Register PIO_MDSR Read only 0x00000000 0x005C Reserved 0x0060 Pull up Disable Register PIO_PUDR Write only 0x0064 Pull up Enable Register PIO_PUER Write only 0x0068 Pad Pull up Status Register PIO_PUSR Read only 0x00000000 0x006C Reserved 88 AT91SAM7S Series Preliminary sa 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary Table 15 2 Register Mapping Continued Offset Register Name Access Reset Value 0x0070 Perip
25. 40 09 9q ebp3 pazo SOOT YAWIL FOOT YAWIL MDO19 Y3NIL 249019 YAWIL 1490719 YAWIL IMINary m AT91SAM7S Series Preli 396 ss AT91SAM7S Series Preliminary 32 5 3 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR Channel Mode Register In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same fre quency and independently programmable duty cycles or generates different types of one shot or repetitive pulses In this mode TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event EEVT parameter in TC_CMR Figure 32 6 shows the configuration of the TC channel when programmed in Waveform Operat ing Mode 32 5 3 1 Waveform Selection 6175G ATARM 22 Nov 06 Depending on the WAVSEL parameter in TC_CMR Channel Mode Register the behavior of TC_CV varies With any selection RA RB and RC can all be used as compare registers RA Compare is used to control the TIOA output RB Compare is used to control the TIOB output if correctly configured and RC Compare is used to control TIOA and or TIOB outputs A MEL 397 AIMEL RE E Waveform Mode Figure 32 6 gol SOLL VOIL 1 101 U09 Nd NO ANI TC1_IMR Ke uueyo Jajunoo Jaw L golL Jomes ETRGS TC1_SR 9 19 siba
26. 48 33 49 32 1 16 ATMEL 6175G ATARM 22 Nov 06 AMEL 4 2 64 lead LQFP and 64 pad QFN Pinout Table 4 1 AT91SAM7S512 256 128 64 321 Pinout 1 ADVREF 17 GND 33 TDI 49 TDO 2 GND 18 VDDIO 34 PA6 PGMNOE 50 JTAGSEL 3 AD4 19 PA16 PGMD4 35 PA5 PGMRDY 51 TMS 4 AD5 20 PA15 PGMD3 36 PA4 PGMNCMD 52 PA31 5 AD6 21 PA14 PGMD2 37 PA27 PGMD15 53 TCK 6 AD7 22 PA13 PGMD1 38 PA28 54 VDDCORE 7 VDDIN 23 PA24 PGMD12 39 NRST 55 ERASE 8 VDDOUT 24 VDDCORE 40 TST 56 DDM 9 PA17 PGMD5 ADO 25 PA25 PGMD13 41 PA29 57 DDP 10 PA18 PGMD6 AD1 26 PA26 PGMD14 42 PA30 58 VDDIO 11 PA21 PGMD9 27 PA12 PGMDO 43 PAS 59 VDDFLASH 12 VDDCORE 28 PA11 PGMM3 44 PA2 PGMEN2 60 GND 13 PA19 PGMD7 AD2 29 PA10 PGMM2 45 VDDIO 61 XOUT 14 PA22 PGMD10 30 PA9 PGMM1 46 GND 62 XIN PGMCK 15 PA23 PGMD11 31 PA8 PGMMO 47 PA1 PGMEN1 63 PLLRC 16 PA20 PGMD8 AD3 32 PA7 PGMNVALID 48 PAO PGMENO 64 VDDPLL Note 1 The bottom pad of the QFN package must be connected to ground 10 AT91SAM 7S Series Preliminary mmm 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary 4 3 48 lead LQFP and 48 pad QFN Package Outlines Figure 4 3 and Figure 4 4 show the orientation of the 48 lead LQFP and the 48 pad QFN package A detailed mechanical description is given in the section Mechanical Charact
27. Se 0x100 0x124 Reserved for Peripheral Data Controller PDC 6175G ATARM 22 Nov 06 ATMEL 367 AMEL 31 8 1 SSC Control Register Name SSC_CR Access Type Write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 swAsT SE 7 6 5 4 3 2 1 0 EA ERA AAA A AS A RXEN Receive Enable No effect Enables Receive if RXDIS is not set RXDIS Receive Disable No effect Disables Receive If a character is currently being received disables at end of current character reception TXEN Transmit Enable No effect Enables Transmit if TXDIS is not set TXDIS Transmit Disable No effect Disables Transmit If a character is currently being transmitted disables at end of current character transmission SWRST Software Reset No effect Performs a software reset Has priority on any other bit in SSC_CR CH 0 t 20 O e 38 AT91SAM7S Series Preliminary memm 6175G ATARM 22 Nov 06 ss AT91SAM7S Series Preliminary 31 8 2 SSC Clock Mode Register Name SSC_CMR Access Type Read Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 AAA AE ETE AA DIV 7 6 5 4 3 2 1 0 DIV e DIV Clock Divider 0 The Clock Divider is not active Any Other Value The Divided Clock equals the Master Clock divided by 2 times DIV The maximum bit rate is MCK 2 The minimum bit rate is MCK 2 x 4095 MCK 8190 A MEL 369 6175G ATARM 22 Nov 06
28. Table 12 2 AT91SAM7S Series Debug Unit Chip ID Chip Name Chip ID AT91SAM7S32 0x27080340 AT91SAM7S321 0x27080342 AT91SAM7S64 0x27090540 AT91SAM7S128 0x270A0740 AT91SAM7S256 0x270B0940 AT91SAM7S512 0x270B0A40 AMEL 5 12 5 4 12 5 4 1 52 AMEL For further details on the Debug Unit see the Debug Unit section IEEE 1149 1 JTAG Boundary Scan IEEE 1149 1 JTAG Boundary Scan allows pin level access independent of the device packaging technology IEEE 1149 1 JTAG Boundary Scan is enabled when JTAGSEL is high The SAMPLE EXTEST and BYPASS functions are implemented In ICE debug mode the ARM processor responds with a non JTAG chip ID that identifies the processor to the ICE system This is not IEEE 1149 1 JTAG compliant It is not possible to switch directly between JTAG and ICE operations A chip reset must be per formed after JTAGSEL is changed A Boundary scan Descriptor Language BSDL file is provided to set up testing JTAG Boundary scan Register The Boundary scan Register BSR contains 96 bits that correspond to active pins and associ ated control signals Each AT91SAM7Sxx input output pin corresponds to a 3 bit register in the BSR The OUTPUT bit contains data that can be forced on the pad The INPUT bit facilitates the observability of data applied to the pad The CONTROL bit selects the direction of the pad AT91SAM7S Series Preliminary memm 6175G ATARM 22 Nov 06 ss A
29. e PB 7 6 5 4 3 2 1 0 Pr Ps Ps Pa Pa Paz Pi Po e PO P31 Peripheral A Select O No effect 1 Assigns the I O line to the Peripheral A function A MEL 101 6175G ATARM 22 Nov 06 AMEL 15 6 25 PIO Peripheral B Select Register Name PIO_BSR Access Type Write only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P20 15 14 13 12 11 10 9 8 PS pm pas Pe Pm Po mo P 7 6 5 4 3 2 1 0 e PO P31 Peripheral B Select O No effect 1 Assigns the UO line to the peripheral B function 15 6 26 PIO Peripheral A B Status Register Name PIO_ABSR Access Type Read only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P23 P22 pai P20 15 14 13 12 11 10 9 8 EL Po e PB 7 6 5 4 3 2 1 0 Pr Ps Ps Pa Pa Paz Pi Po e PO P31 Peripheral A B Status 0 The I O line is assigned to the Peripheral A 1 The I O line is assigned to the Peripheral B 102 AT91SAM7S Series Preliminary EEE 6175G ATARM 22 Nov 06 ss A T91SAM7S Series Preliminary 15 6 27 PIO Output Write Enable Register Name PIO_OWER Access Type Write only 31 30 29 28 27 26 25 24 P24 23 22 21 20 19 18 17 16 P20 15 14 13 12 11 10 9 8 PS pm pas Pe Pm Po mo P 7 6 5 4 3 2 1 0 e PO P31 Output Write Enable O No effect 1 Enables writing PIO_ODSR for the I O line 15 6 28 PIO Output Write Disable Register Name PIO_OWDR Access Type Write only 3
30. ss AT91SAM7S Series Preliminary 24 8 18 AIC Fast Forcing Enable Register Register Name AIC_FFER Access Type Write only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 Pip PID8 7 6 5 4 3 2 1 0 pioz Pie Pips PID4 PID3 ebo ss e SYS PID2 PID31 Fast Forcing Enable 0 No effect 1 Enables the fast forcing feature on the corresponding interrupt 24 8 19 AIC Fast Forcing Disable Register Register Name AIC_FFDR Access Type Write only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID8 7 6 5 4 3 2 1 0 pioz Pie Ps PIDA PID3 pip2 ss e SYS PID2 PID31 Fast Forcing Disable 0 No effect 1 Disables the Fast Forcing feature on the corresponding interrupt N AMEL 2 6175G ATARM 22 Nov 06 AMEL 24 8 20 AIC Fast Forcing Status Register Register Name AIC_FFSR Access Type Read only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 Pip PID8 7 6 5 4 3 2 1 0 pioz Pie Pps PID4 PID3 ebo ss e SYS PID2
31. 26 1 Description The Power Management Controller PMC optimizes power consumption by controlling all sys tem and user peripheral clocks The PMC enables disables the clock inputs to many of the peripherals and the ARM Processor The Power Management Controller provides the following clocks e MCK the Master Clock programmable from a few hundred Hz to the maximum operating frequency of the device It is available to the modules running permanently such as the AIC and the Memory Controller e Processor Clock PCK switched off when entering processor in idle mode e Peripheral Clocks typically MCK provided to the embedded peripherals USART SSC SPI TWI TC MCI etc and independently controllable In order to reduce the number of clock names in a product the Peripheral Clocks are named MCK in the product datasheet e UDP Clock UDPCk required by USB Device Port operations Does not pertain to AT91SAM7S32 e Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins 26 2 Master Clock Controller The Master Clock Controller provides selection and division of the Master

ATMEL AT91SAM7S512 AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 AT91SAM7S32 handbook

Contents