ON SEMICONDUCTOR Octal 3-State Noninverting Transparent Latch
Contents
1. INCHES MILLIMETERS MIN MAX MIN MAX A 1010 1 070 2566 2717 B 0 240 0260 6 10 6 60 Y C 0150 0 180 381 457 j D 0015 0022 039 0 5 T E 0050 5 1 27 BSC SEATING TNI l F 0050 0 070 127 177 PLANE G 0 100 BSC 2 54 BSC N _ J 0008 0 015 0 21 0 38 0110 0140 280 3 55 G F L 0 300 BSC 7 62 BSC gt lt J 20PL M 09 159 0 159 D 20PL 0 25 0 010 0 TB 0 N 0 020 0 040 0 51 1 01 0 25 0 010 GD T W SOIC 20 DW SUFFIX CASE 7510 05 ISSUE G NOTES 0 1 DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES H PER ASME Y14 5M 1994 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION 4 MAXIMUM MOLD PROTRUSION 0 15 PER SIDE 5 DIMENSION DOES NOT INCLUDE DAMBAR r PROTRUSION ALLOWABLE PROTRUSION x x SHALL BE 0 13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION MILLIMETERS A I DIM MIN MAX ____ Li x A 235 265 B Ai 010 025 20x B B 035 049 023 032 0 25 T A B D 1265 1295 E 740 760 e 1 27 BSC 1005 10 55 h 025 075 I A L 0 50 0 90 oof 7 l SEATING At PLANE EM ME http onsemi com 7 MC74HC573A PACKAGE DIMENSIONS TSSOP 20 DT SUFFIX CASE 948E 02 ISSUE B 20X K REF N2. Wafer Lot YY Year WW Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on this data sheet Publication Order Number MC74HC573A D MC74HC573A po 2 19 pi 2 a 4 D2 02 pata 2 NONINVERTING INPUTS p4 6 OUTPUTS ps 05 pe 06 2 Q7 LATCH ENABLE PIN 20 Vcc OUTPUT ENABLE PIN 10 GND Figure 1 LOGIC DIAGRAM a s ey Latch Enable Enable L H X Don t Z High Impedance H L X No chang X Design Criteria Internal Gate Count Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product Equivalent to a two input NAND gate http onsemi com 2 OUTPUT ENABLE 4 1 Voc po 2 Q0 pi 3 at p2 4 02 ps 5 D4 6 Q4 D5 7 Q5 De 8 Q6 D7 9 Q7 GND LATCH ENABLE Figure 2 PIN ASSIGNMENT MC74HC573A MAXIMUM RATINGS Parameter Unit This device contains protection DC Supply Voltage Referenced to GND circuitry to guard against damage due to high static voltages or electric DC Input Voltage Referenced to GND EXEC fields However precautions must Im DC Output Voltage Referenced to GND vi en n enirn oy DC Input Current per Pin voltages to this high impedance cir z DC Output Current per Pin cuit For proper operation Vin and Vout should be constrained to the DC Supply
3. 0 Minimum Pulse Width Latch Enable Maximum Input Rise and Fall Times http onsemi com 5 MC74HC573A SWITCHING WAVEFORMS INPUT D GND Figure 3 OUTPUT ENABLE 3 0 V GND HIGH Q IMPEDANCE 10 VoL 90 Q HIGH IMPEDANCE Figure 5 TEST POINT OUTPUT DEVICE UNDER E TEST e Includes all probe and jig capacitance Figure 7 Test Circuit TEST POINT CONNECT TO Vcc WHEN OUTPUT TESTING tpi z AND DEVICE CONNECT TO GND WHEN UNDER TESTING tpuz AND tp TEST Includes all probe and jig capacitance Figure 8 Test Circuit LATCH ENABLE Q VALID Vcc INPUT D GND tsu th LATCH 20 ENABLE GND Figure 6 gt 19 Qo Di 01 02 02 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 LATCH ENABLE OUTPUT ENABLE Figure 9 EXPANDED LOGIC DIAGRAM http onsemi com 6 MC74HC573A PACKAGE DIMENSIONS PDIP 20 N SUFFIX PLASTIC DIP PACKAGE CASE 738 03 ISSUE E A NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSION B DOES NOT INCLUDE MOLD FLASH
4. 38 Units Rail MC74HC573ADWG SOIC WIDE 38 Units Rail Pb Free MC74HC573ADWR2 SOIC WIDE 1000 Units Reel MC74HC573ADWR2G SOIC WIDE 1000 Units Reel Pb Free MC74HC573ADT TSSOP 20 75 Units Rail MC74HC573ADTR2 TSSOP 20 2500 Units Reel TFor information on tape and reel specifications including part orientation and tape sizes please refer to our Tape and Reel Packaging Specifications Brochure BRD8011 D This package is inherently Pb Free http onsemi com 3 MC74HC573A DC ELECTRICAL CHARACTERISTICS Voltages Referenced to GND Parameter Test Conditions Guaranteed Limit Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Input Leakage Current Vout 0 1 V or Voc 0 1 V loul 20 nA 0 1 V or Vcc 0 1 V 20 uA Vin Vin or Vit lout 20 uA Vin Vin or Vit lout 2 4mA 6 0 mA 7 8 mA Vout 0 1 Voc 0 1V 20 uA Vin Vin or Vi 2 4mA 6 0 mA 7 8 mA Vin Voc or GND Unit V Maximum Three State Leakage Current Maximum Quiescent Supply Current per Package Output in High Impedance State Vin Vit or Vin Vout Voc or GND Vin Voc or GND 0 uA NOTE Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data
5. 0 8 0 8 ON Semiconductor and m are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and dist
6. Book DL129 D AC ELECTRICAL CHARACTERISTICS C 50 pF Input t 6 0 ns Vcc Guaranteed Limit Symbol Parameter V 55 to 25 lt 85 x 125 C Unit tpi H Maximum Propagation Delay Input D to Q 2 0 150 190 225 ns tPuL Figures 1 and 5 3 0 100 140 180 Maximum Propagation Delay Latch Enable to Q Figures 2 and 5 Maximum Propagation Delay Output Enable to Q Figures 3 and 6 Maximum Propagation Delay Output Enable to Q 190 Figures 3 and 6 38 33 Maximum Output Transition Time Any Output 75 Figures 1 and 5 32 15 6 0 15 Cin Maximum Input Capacitance 15 Cout Maximum Three State Output Capacitance Output in High Impedance EN NOTE For propagation delays with loads other than 50 pF and information on typical parametric values see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book DL129 D State Typical 25 C Vcc 5 0 V Power Dissipation Capacitance Per Enabled Output pF Used to determine the no load dynamic power consumption Pp Cpp Vcc f Icc Vcc For load considerations see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book DL129 D http onsemi com 4 MC74HC573A TIMING REQUIREMENTS 50 pF Input t 6 0 ns Guaranteed Limit 55 to 25 C Parameter ig Min Max Minimum Setup Time Input D to Latch Enable 50 40 10 9 0 Minimum Hold Time Latch Enable to Input D 5 0 5 0 5 0 5
7. Current Vcc and GND Pins range GND x Vin or Vout Voc m A A Power Dissipation in Still Air Plastic DIP Unused inputs must always be tied to an appropriate logic voltage SOIC Packaget TSSOP Packaget level e g either GND or Vcc Unused outputs must be left open Tstg Storage Temperature 6510 150 to 150 Lead Temperature 1 mm from Case for 10 Seconds Plastic DIP TSSOP or SOIC Package Maximum ratings are those values beyond which device damage can occur Maximum ratings applied to the device are individual stress limit values not normal operating conditions and are not valid simultaneously If these limits are exceeded device functional operation is not implied damage may occur and reliability may be affected TDerating Plastic DIP 10 mW C from 65 to 125 C SOIC Package 7 mW C from 65 to 125 C TSSOP Package 6 1 mW C from 65 to 125 C For high frequency or heavy load considerations see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book DL129 D RECOMMENDED OPERATING CONDITIONS Parameter i Max Unit DC Supply Voltage Referenced to GND 6 0 V DC Input Voltage Output Voltage Referenced to GND NUNILZILIIIILITI MANN ERUIT tr t Input Rise and Fall Time Voc 2 0 V 1000 ns Figure 1 Vcc 4 5 V 500 ORDERING INFORMATION MC74HC573AN PDIP 20 1440 Units Box MC74HC573ANG PDIP 20 1440 Units Box Pb Free MC74HC573ADW SOIC WIDE
8. MC74HC573A Octal 3 State Noninverting Transparent Latch High Performance Silicon Gate CMOS The MC74HC573A is identical in pinout to LS573 The devices are compatible with standard CMOS outputs with pullup resistors they are compatible with LSTTL outputs These latches appear transparent to data i e the outputs change asynchronously when Latch Enable is high When Latch Enable goes low data meeting the setup and hold time becomes latched The HC573A is identical in function to the HC373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout Features Pb Free Packages are Available Output Drive Capability 15 LSTTL Loads Outputs Directly Interface to CMOS NMOS and TTL Operating Voltage Range 2 0 to 6 0 V Low Input Current 1 0 uA In Compliance with the Standard No 7 0 A Requirements Chip Complexity 218 FETS or 54 5 Equivalent Gates additional information on our Pb Free strategy and soldering details please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual SOLDERRM D Semiconductor Components Industries LLC 2004 1 December 2004 Rev 10 ON Semiconductor http onsemi com MARKING DIAGRAMS 20 A 74 57 AWLYYWW 5 CASE 738 SOIC WIDE 20 DW SUFFIX CASE 751D 240 TSSOP 20 DT SUFFIX CASE 948E Assembly Location WL
9. OTES ovo PERRO 0 15 0 006 T U 0 10 0 004 T U 2 CONTROLLING DIMENSION A MILLIMETER 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE 2x L 2 BURRS MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0 15 0 006 PER SIDE B 4 DIMENSION B DOES NOT INCLUDE L U INTERLEAD FLASH OR PROTRUSION PIN 1 U INTERLEAD FLASH OR PROTRUSION IDENT SECTION N N SUNL NOT EXCEED 0 25 0 010 PER IDE 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE 0 25 0 010 DAMBAR PROTRUSION SHALL BE 0 08 0 003 TOTAL IN EXCESS OF THE K 1 1 EB LL LIL Nat 0 15 0 006 U DIMENSION AT MAXIMUM MATERIAL 15 0 006 CONDITION M 6 TERMINAL NUMBERS ARE SHOWN A FOR REFERENCE ONLY DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W N F MILLIMETERS INCHES F MAX MIN I DIM A 640 660 0 252 0 260 DETAIL E B 430 450 0 169 0 177 120 0 047 A 5N D 005 05 0 002 0 006 w F 050 075 0 020 0 030 Y 0 65 BSC 0 026 BSC a 027 037 0011 0015 a J 009 0 20 0 004 0 008 Ji 009 016 0 004 0 006 DETAIL E 019 030 0 007 0 012 C 0 100 0 004 019 025 0 007 0 010 T TsEATING L 6 40 BSC _ 0 252 BSC_ PLANE M
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ON SEMICONDUCTOR Octal 3 State Noninverting Transparent Latch