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CIRRUS LOGIC -CS5521/22/23/24/28 handbook

1. gier A2 A i G v L b a m d L END VIEW O SEATING Xi SIDE VIEW PLANE Y 123 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0 084 2 13 A1 0 002 0 006 0 010 0 05 0 13 0 25 A2 0 064 0 068 0 074 1 62 1 73 1 88 b 0 009 0 015 0 22 0 38 2 3 D 0 272 0 2834 0 295 6 90 7 20 7 50 1 E 0 291 0 307 0 323 7 40 7 80 8 20 E1 0 197 0 209 0 220 5 00 5 30 5 60 1 e 0 022 0 026 0 030 0 55 0 65 0 75 L 0 025 0 03 0 041 0 63 0 75 1 03 oc 0 4 8 0 4 8 JEDEC H MO 150 Controling Dimension is Millimeters Notes 1 D and E1 are reference datums and do not included mold flash or protrusions but do include mold mismatch and are measured at the parting line mold flash or protrusions shall not exceed 0 20 mm per side 2 Dimension b does not include dambar protrusion intrusion Allowable dambar protrusion shall be 0 13 mm total in excess of b dimension at maximum material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm from lead tips DS317F4 55 CS5521 22 23 24 28 24L SSOP PACKAGE DRAWING z AA n
2. Notes 13 For bipolar mode the number of bits of Noise Free Resolution is LOG 2XInput Range 6 6xRMS Noise LOG 2 rounded to the nearest bit For unipolar mode the number of bits of Noise Free Resolution is LOG Input Range 6 6xRMS Noise LOG 2 rounded to the nearest bit Also the CS5521 23 s output conversions are 16 bits Noise free Resolution numbers are based upon VREF 2 5 V and XIN 32 768 kHz The values will be affected directly by changes in VREF but the effects due to changes in the XIN frequency will be minor DS317F4 7 TYPICAL RMS NOISE CS5522 24 28 Notes 14 and 15 IDDI IC I RRUS UI Van Vant I am WM f LOGIN CS5521 22 23 24 28 Output Rate l 3 dB Filter Input Range Bipolar Unipolar Mode Sps Frequencv 25 mV 55 mV 100 mV 1V 2 5V 5V 1 88 1 64 90 nV 95 nV 140 nV 1 5 uV 3 uV 6 uV 3 76 3 27 110 nV 130 nV 190 nV 2 uV 4 uV 8 uV 7 51 6 55 170 nV 200 nV 275 nV 2 5 uV 6 uV 11 5 uV 15 0 12 7 250 nV 330 nV 580 nV 4 5 uV 10 uV 20 uV 30 0 25 4 500 nV 1 uV 1 5 uV 16 uV 45 uV 85 uV 61 6 Note 16 50 4 2 uV 4 uV 8 uV 72 uV 195 uV 350 uV 84 5 Note 16 70 7 10 uV 20 uV 35 uV 340 uV 900 uV 2 mV 101 1 Note 16 84 6 30 uV 60 uV 105 uV 1 1 mV 3 mV 5 3 mV Notes 14 Wideband noise aliased into the baseband Referred to the input Typical values shown for 25 C 15 To estimate Peak to Peak Noise multiply RMS noise by 6 6 f
3. CS5521 22 23 24 28 CIDDI IC Ten f CIRRUS LOGIC TYPICAL RMS NOISE CS5521 23 Notes 10 and 11 Output Rate l 3 dB Filter Input Range Bipolar Unipolar Mode Sps Frequencv 25 mV 55 mV 100 mV 1V 2 5V 5V 1 88 1 64 90 nV 148 nV 220 nV 1 8 uV 3 9 uV 7 8 uV 3 76 3 27 122 nV 182 nV 310 nV 2 6 uV 5 7 uV 11 3 uV 7 51 6 55 180 nV 267 nV 435 nV 3 7 uV 8 5 uV 18 1 uV 15 0 12 7 280 nV 440 nV 810 nV 5 7 uV 14 uV 28 uV 30 0 25 4 580 nV 1 1 uV 2 1 uV 18 2 uV 48 uV 96 uV 61 6 Note 12 50 4 2 6 uV 4 9 uV 8 5 uV 92 uV 238 uV 390 uV 84 5 Note 12 70 7 11 uV 27 uV 43 uV 458 uV 1 1 mV 2 4 mV 101 1 Note 12 84 6 41 uV 72 uV 130 uV 1 2 mV 3 4 mV 6 7 mV Notes 10 Wideband noise aliased into the baseband Referred to the input Typical values shown for 25 C 11 To estimate Peak to Peak Noise multiply RMS noise by 6 6 for all ranges and output rates 12 For input ranges lt 100 mV and output rates 260Sps 16 384 kHz chopping frequency is used TYPICAL NOISE FREE RESOLUTION BITS CS5521 23 Note 13 Output Rate l 3 dB Filter Input Range Bipolar Mode Sps Frequencv 25 mV 55 mV 100 mV 1V 2 5V 5V 1 88 1 64 16 16 16 16 16 16 3 76 3 27 16 16 16 16 16 16 7 51 6 55 15 16 16 16 16 16 15 0 12 7 15 15 15 16 16 16 30 0 25 4 14 14 14 14 14 14 61 6 Note 12 50 4 12 12 12 12 12 12 84 5 Note 12 70 7 9 9 9 9 9 9 101 1 Note 12 84 6 8 8 8 8 8 8
4. IDRI IS I OCIC CS5521 22 23 24 28 CIRRUS LOGIC en LIST OF FIGURES Figure 1 Continuous Running SCLK Timing Not to Scale Lena 12 Figure 2 SDI Write Timing Not to Scale ss nanna 12 Figure 3 SDO Read Timing Not to Scale nn nanna 12 Figure 4 Multiplexer Confiourations nanna nanna nanna nenne 13 Figure 5 Input Models for AIN and AIN pins 100 mV Input Ranges seen 14 Figure 6 Input Models for AIN and AIN pins 2100 mV input ranges sses 14 Figure 7 Input Ranges Greater than BN 16 Figure 8 Input Model for VREF and VREF P ims sem neennennznennnn enza na mnn nnnnnn mnn nn 16 Figure 9 C55523 24 Register Diagram nanna nanna nanna 17 Figure 10 Command and Data Word Timing 25 Figure 11 Self Calibration of Offset Low Ranges nanna 32 Figure 12 Self Calibration of Offset High Ranges nanna 32 Figure 13 Self Calibration of Gain All Ranges L nanna 32 Figure 14 System Calibration of Offset Low Ranges sse 32 Figure 15 System Calibration of Offset High Ranges nanna 33 Figure 16 System Calibration of Gain Low Ranges nanna nt 33 Figure 17 System Calibration of Gain High Ranges ann nara 33 Figure 18 Filter Response Normalized to Output Word Rate 1 LL 42 Figure 19 Typical Linearity Error for CS5521 23 0 nara 42 Figure 20 Typical Linearity Error for CS5522 24 28 nanna 42 Figure 21 CS5522 Configured to use on chip charge pump to supply NBV Lena 43 Figure 22 CS5522
5. i HH C 5521 22 23 24 28 16 bit or 24 bit 2 4 8 channel ADCs with PGIA Features e Low Input Current 100 pA Chopper stabilized Instrumentation Amplifier e Scalable Input Span Bipolar Unipolar 2 5V VREF 25 mV 55 mV 100 mV 1 V 2 5V 5V External 10 V 100 V e Wide Vper Input Range 1 to 5 V e Fourth Order Delta Sigma A D Converter e Easy to Use Three wire Serial Interface Port Programmable Auto Channel Sequencer with Conversion Data FIFO Accessible Calibration Registers per Channel Compatible with SPITM and Microwire e System and Self Calibration e Eight Selectable Word Rates Up to 617 Sps XIN 200 kHz Single Conversion Settling 50 60 Hz 3 Hz Simultaneous Rejection e Single 45 V Power Supply Operation Charge Pump Drive for Negative Supply 3 to 5 V Digital Supply Operation e Low Power Consumption 6 0 mW VA AGND VREF VREF General Description The CS5521 22 23 24 28 are highly integrated AX ana log to digital converters ADCs which use charge balance techniques to achieve 16 bit CS5521 23 and 24 bit CS5522 24 28 performance The ADCs come as either two channel CS5521 22 four channel CS5523 24 or eight channel CS5528 devices and include a low input current chopper stabilized instru mentation amplifier To permit selectable input spans of 25 mV 55 mV 100 mV 1 V 2 5 V and 5 V the ADCs include a PGA progra
6. Offset Register 2 All devices Offset Register 3 CS5523 24 28 only Offset Register 4 CS5523 24 28 only Offset Register 6 CS5528 only Offset Register 7 CS5528 only Offset Register 5 CS5528 only Offset Register 8 CS5528 only gt DD NS RM READ WRITE INDIVIDUAL GAIN REGISTER D7 MSB D6 D5 D4 D3 D2 D1 DO 0 CS2 CS1 cso RW 0 1 0 Function These commands are used to access each gain register separately CS1 CSO decode the reg isters accessed R W Read Write 0 Write to selected register 1 Read from selected register CS 2 0 Channel Select Bits 000 001 010 011 100 101 110 111 20 Gain Register 1 All devices Gain Register 2 All devices Gain Register 3 Gain Register 4 Gain Register 5 CS5528 only Gain Register 6 CS5528 only CS5528 only CS5528 only Gain Register 7 pp Gain Register 8 CS5523 24 28 only CS5523 24 28 only DS317F4 CIRRUS LOGIC CS5521 22 23 24 28 m I READ WRITE CONFIGURATION REGISTER D7 MSB D6 D5 D4 D3 D2 D1 DO 0 0 0 0 RAW 0 1 1 Function These commands are used to read from or write to the configuration register R W Read Write 0 Write to selected register 1 Read from selected register
7. Optional XIN Clock AIN1 Source CS5522 C849 AIN1 ScLK LIS Serial AGND 8 Data AIN2 SDI Interface l 12 SCH sDo AO NBV CPD DGND 5 7 13 V Vv Figure 23 CS5522 Configured for Single Supply Bridge Measurement DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 2 8 1 Charge Pump Drive Circuits The CPD Charge Pump Drive pin of the converter can be used with external components shown in Figure 21 to develop an appropriate negative bias voltage for the NBV pin When CPD is used to gen erate the NBV the NBV voltage is regulated with an internal regulator loop referenced to VA Therefore any change on VA results in a propor tional change on NBV With VA 5 V NBV s regulation is set proportional to VA at approxi mately 2 1 V Figure 24 illustrates a charge pump circuit when the converters are powered from a 43 0 V digital supply Alternatively the negative bias supply can be generated from a negative supply voltage or a resistive divider as illustrated in Figure 25 For ground based signals with the instrumentation amplifier engaged when in the 25 mV 55 mV or 100 mV ranges the voltage on the NBV pin should at no time be less negative than 1 8 V or more negative than 2 5 V To prevent excessive voltage stress to the chip when the instrumentation amplifier isn t engaged when in the 1 V 2 5 V or 5 V ranges the NBV voltage should not be more negative than 2 5 V The
8. V Low level Input Voltage All Pins Except XIN and SCLK Vu 0 8 V XIN 1 5 V SCLK 0 6 V High level Output Voltage Vou All Pins Except CPD and SDO Note 19 VA 1 0 V CPD lout 4 0 mA VD 1 0 V SDO lout 5 0 mA VD 1 0 V Low level Output Voltage VoL All Pins Except CPD and SDO lout 1 6 mA 6 0 4 V CPD lout 2 mA 0 4 V SDO lout 5 0 mA 0 4 V Input Leakage Current lin 1 10 uA 3 state Leakage Current loz 10 UA Digital Output Pin Capacitance Cout 9 pF Notes 18 All measurements performed under static conditions 19 lout 100 pA unless stated otherwise Voy 2 4 V 9 lout 40 pA 3 V DIGITAL CHARACTERISTICS T 25 C VA 5 V 15 VD 3 0 V 10 GND 0 See Notes 2 and 18 DS317F4 Parameter Svmbol Min Tvp Max Unit High level Input Voltage All Pins Except XIN and SCLK Vin 0 6 VD V XIN VD 0 5 V SCLK VD 0 45 V Low level Input Voltage All Pins Except XIN and SCLK Vu 0 16 VD V XIN 0 3 V SCLK 0 6 V High level Output Voltage Vou All Pins Except CPD and SDO lout 400 pA VA 0 3 V CPD lout 4 0 mA VD 1 0 V SDO lout 5 0 mA VD 1 0 V Low level Output Voltage VoL All Pins Except CPD and SDO lout 400 pA 0 3 V CPD lout 2 mA 0 4 V SDO lout 5 0 mA 0 4 V Input Leakage Current lin 1 10 uA 3 state Leakage Current loz 10 UA
9. gt Connections b k AN Full Scale Figure 17 System Calibration of Gain High Ranges 1 Full scale input must not saturate the 20X in strumentation amplifier if the calibration is on an input range where the instrumentation am plifier is involved DS317F4 2 The 1 s density of the modulator must not be greater than 80 percent the input to the AX modulator must not exceed the maximum input which Table 1 specifies 3 The input must not be so small relative to the range chosen that the resulting gain register s content decoded in decimal exceeds 3 9999998 see the discussion of operating lim its on input span under the Analog Input and Limitations in Calibration Range sections This requires the full scale input voltage to the modulator to be at least 25 percent of the nom inal value The converter s input ranges were chosen to guar antee gain calibration accuracy to 1 LSB1g or 16 LSB when system gain calibration is performed This is useful when a user wants to manually scale the full scale range of the converter and maintain accuracy For example if a gain calibration is per formed with a 2 5 V full scale voltage and a 1 25 V input range is desired the user can read the con tents of the gain register shift the register contents left by 1 bit and then write the result back to the gain register This multiples the gain by 2 Assuming a system can provide two known
10. the ADC will repeatedly perform conversions referencing multiple Setups The CSRP bits in the command word are ignored in this mode Instead the Depth Pointer DP3 DPO bits in the Configuration Register are accessed to determine the number of Setups to reference when collecting the data The number of Setups refer enced will be equal to DP3 DPO 1 and will be accessed in order beginning with Setup1 Note that in this mode every conversion data set must be read The part will wait for the current conversion data set to be read before performing the next set of conversions To perform repeated multiple Setup conversions with wait the MC bit must be set to 1 the LP bit must be set to 1 and the RC bit must be set to 1 in the Configuration Register Then the 8 bit com mand word to start a conversion must be sent to the converter Because the CSRP bits of the command word are ignored in this mode a start convert command referencing any of the available Setups will begin the conversions The ADC will then per form conversions using the appropriate number of Setups as dictated by the DP bits in the Configura tion Register beginning with Setup The SDO line will fall after the final conversion to indicate that the data is ready Eight SCLKs plus 24 37 l CIRRUS LOGIC CS5521 22 23 24 28 SCLKs for each Setup referenced are required to read the conversion words from the data FIFO The first 8 SCLKs are
11. 7 Setup 8 K Chop Frequency Multiple Conversions Depth Pointer Loop Read Convert Powerdown Modes Flags Etc Latch Outputs Channel Select Output Word Rate PGA Selection Unipolar Bipolar Figure 9 CS5523 24 Register Diagram DS317F4 17 l CIRRUS LOGIC CS5521 22 23 24 28 2 2 1 System Initialization When power to the CS5521 22 23 24 28 is applied the chips are held in a reset condition until the 32 768 kHz oscillator has started and a counter timer elapses Due to the high Q of the 32 768 kHz crystal the oscillator takes 400 600 ms to start The counter timer counts 2006 oscillator clock cycles to make sure the oscillator is fully stable During this time out period the serial port logic is reset and the RV Reset Valid bit in the configuration register is set to indicate that a valid reset occurred After a reset the on chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid com mand configuration register 000040 H offset registers 000000 H gain registers 400000 H channel setup registers 000000 H 18 Note A system reset can be initiated at any time by writing a logic 1 to the RS Reset System bit in the configura tion register After a reset the RV bit is set until the configuration register is read The user must then write a logic 0 to the RS bit to take the part out of the reset mo
12. Channel Set up Registers register is 48 bits long for CS5521 22 register is 96 bits long for CS5523 24 register is 192 bits long for CS5528 110 Reserved 111 Reserved D7 MSB D6 D5 D4 D3 D2 D1 DO CB CSRP3 CSRP2 CSRP1 CSRPO CC2 CC1 CCO BIT NAME VALUE FUNCTION D7 Command Bit CB 0 See table above 1 Must be logic 1 for these commands D6 D3 Channel Pointer Bits 0000 These bits are used as pointers to the Setups CSRP3 CSRPO Note The MC bit must be logic 0 for these bits to take effect When MC 1 these bits are ignored The LP MC and RC A bits in the configuration register are ignored during calibra 1111 tion D2 DO Conversion Calibration 000 Normal Conversion Bits CC2 CCO 001 Self Offset Calibration 010 Self Gain Calibration 011 Reserved 100 Reserved 101 System Offset Calibration 110 System Gain Calibration 111 Reserved DS317F4 Table 2 Command Register Quick Reference 19 till EE gn CIRRUS LOGIC CS5521 22 23 24 28 2 2 4 Command Register Descriptions READ WRITE INDIVIDUAL OFFSET CALIBRATION REGISTER D7 MSB D6 D5 D4 D3 D2 D1 DO 0 CS2 CS1 cso RW 0 0 1 Function These commands are used to access each offset register separately CS1 CSO decode the registers accessed R W Read Write 0 Write to selected register 1 Read from selected register CS 2 0 Channel Select Bits 000 001 Offset Register 1 All devices
13. Configured for ground referenced Unipolar Signals 44 Figure 23 CS5522 Configured for Single Supply Bridge Meaeurement 44 Figure 24 Charge Pump Drive Circuit for VD AN 45 Figure 25 Alternate NBV Circuits nanna ata snnt anna 45 LIST OF TABLES Table 1 Relationship between Full Scale Input Gain Factors and Internal Analog Signal Bolt 15 Table 2 Command Register Quick Heierence ena 19 Table 3 Channel Setup Registers sse nnns 27 Table 4 Configuration Register nanna 30 Table 5 Offset and Gain Registers ran nnns 31 Table 6 Output Coding for 16 bit CS5521 23 and 24 bit CS5522 24 28 sss 40 REVISION HISTORY Revision Date Changes F3 May 2003 F4 August 2005 Added lead free device ordering information Updated legal notice 4 DS317F4 IS I OGIC CS5521 22 23 24 28 1 CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS T 25 C VA VD 5 V 15 VREF 2 5 V VREF AGND NBV 2 1 V XIN 32 768 kHz CFS1 CFS0 00 OWR Output Word Rate 15 Sps Bipolar Mode Input Range 100 mV See Notes 1 and 2 CS5521 23 CS5522 24 28 Parameter Min Typ Max Min Typ Max Unit Accuracy Resolution 16 24 Bits Linearity Error 0 0015 0 003 0 0007 0 0015 FS Bipolar Offset Note 3 1 2 16 32 LSByN Unipolar Offset Note 3 2 4 32 64 LSBy Off
14. D5 D4 D3 D2 D1 DO 1 1 1 1 1 1 1 1 Function Part of the serial port re initialization sequence SYNCO D7 MSB D6 D5 D4 D3 D2 D1 DO 1 1 1 1 1 1 1 0 Function End of the serial port re initialization sequence NULL D7 MSB D6 D5 D4 D3 D2 D1 DO 0 0 0 0 0 0 0 0 Function This command is used to clear a port flag and keep the converter in the continuous conversion 24 mode DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 2 2 5 Serial Port Interface The CS5521 22 23 24 28 s serial interface consists of four control lines CS SCLK SDI SDO Figure 10 illustrates the serial sequence necessary to write to or read from the serial port s registers CS Chip Select is the control line which enables access to the serial port If the CS pin is tied low the port can function as a three wire interface SDI Serial Data In is the data signal used to trans fer data to the converters SDO Serial Data Out is the data signal used to transfer output data from the converters The SDO output will be held at high impedance any time CS is at logic 1 SCLK Serial Clock is the serial bit clock which controls the shifting of data to or from the ADC s serial port The CS pin must be held low logic 0 before SCLK transitions can be recognized by the port logic To accommodate opto isolators SCLK is designed with a Schmitt trigger input to allow an opto isolator with slower rise and fall times to di rectly drive the pin Additi
15. Digital Output Pin Capacitance Cout 9 pF IDDI IC OW I 7 CIRRUS LOGIC DYNAMIC CHARACTERISTICS CS5521 22 23 24 28 Parameter Svmbol Ratio Unit Modulator Sampling Frequency fs XIN 4 Hz Filter Settling Time to 1 2 LSB Full scale Step ts 1 fout S RECOMMENDED OPERATING CONDITIONS AGND DGND 0 V See Note 20 Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital VD 2 7 5 0 5 25 V Positive Analog VA 4 75 5 0 5 25 V Analog Reference Voltage VREF VREF VRefqif 1 0 2 5 VA V Negative Bias Voltage NBV 1 8 2 1 2 5 V Notes 20 All voltages with respect to ground ABSOLUTE MAXIMUM RATINGS AGND DGND 0 V See Note 20 Parameter Symbol Min Typ Max Unit DC Power Supplies Note 21 Positive Digital VD 0 3 6 0 V Positive Analog VA 0 3 6 0 V Negative Bias Voltage Negative Potential NBV 40 3 2 1 3 0 V Input Current Anv Pin Except Supplies Note 22 and 23 lin 10 mA Output Current louT gt 25 mA Power Dissipation Note 24 PDN 500 mW Analog Input Voltage VREF pins VINR NBV 0 3 VA 0 3 V AIN Pins VINA NBV 0 3 VA 0 3 V Digital Input Voltage VIND 0 3 VD 0 3 V Ambient Operating Temperature Ta 40 85 C Storage Temperature Tstg 65 150 C Notes 21 22 23 supply pin is 50 mA 24 WARNING No pin should go more negative than
16. NBV 0 3 V Applies to all pins including continuous overvoltage conditions at the analog input AIN pins Transient current of up to 100 mA will not cause SCR latch up Maximum input current for a power Normal operation is not guaranteed at these extremes 10 Total power dissipation including all input currents and output currents Operation at or beyond these limits may result in permanent damage to the device DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 SWITCHING CHARACTERISTICS T 25 C VA 5 V 15 VD 3 0 V 10 or 5 V 5 Levels Logic 0 0 V Logic 1 VD C 50 pF Parameter Symbol Min Typ Max Unit Master Clock Frequency Note 25 XIN External Clock or Internal Oscillator CS5522 24 28 30 32 768 200 kHz CS5521 23 30 32 768 130 kHz Master Clock Duty Cycle 40 60 96 Rise Times Note 26 tise Any Digital Input Except SCLK 1 0 US SCLK 00 us Any Digital Output 50 ns Fall Times Note 26 trall Any Digital Input Except SCLK 5 1 0 us SCLK 00 US Any Digital Output 50 ns Start up Oscillator Start up Time XTAL 32 768 kHz Note 27 tost 500 S ms Power on Reset Period toor 2006 XIN cycles Serial Port Timing Serial Clock Frequency SCLK 0 2 MHz SCLK Falling to CS Falling for continuous running SCLK to 100 ns Note 28 Serial Clock Pulse Width High t 250 ns Pulse Width Low to
17. Registers DS317F4 31 l CIRRUS LOGIC CS5521 22 23 24 28 offset to occur in the 25 mV 55 mV and 100 mV ranges the AIN pin must be at the proper com mon mode voltage as specified in Common Mode Signal AIN specification in the Analog Input section if AIN 0 V NBV must be between 1 8 V to 2 5 V For self calibration of offset in the 1 0 V 2 5 V and 5 V ranges the inputs of the mod ulator are connected together and then routed to the VREF pin as shown in Figure 12 For self calibration of gain the differential inputs of the modulator are connected to VREF and VREF as shown in Figure 13 For any input range other than the 2 5 V range the converter s gain er ror can not be completely calibrated out when using self calibration This is due to the lack of an accu rate full scale voltage internal to the chips The 2 5 V range is an exception because the external reference voltage is 2 5 V nominal and is used as OPEN 4 AIN ee 2 x2 CLOSED 0 AIN x20 gt AIN EE OPEN VREF Ue MN 4 Reference me ur Cum CLOSED Figure 13 Self Calibration of Gain All Ranges 32 the full scale voltage In addition when self cali bration of gain is performed in the 25 mV 55 mV and 100 mV input ranges the instrumentation am plifier s gain is not calibrated These two factors can leave the converters with a gain error of up t
18. components in Figure 21 are the preferred components for the CPD filter However smaller capacitors can be used with acceptable results The CPD C 470nF C42 470 nF 1N4148 1NA148 1N4148 NBV C 10 uF BAT85 n 1N4148 Cy 2 uF XIN 32 768 kHz Figure 24 Charge Pump Drive Circuit for VD 3 V DS317F4 10 uF ensures verv low ripple on NBV Intrinsic safetv requirements prohibit the use of electrolvtic capacitors In this case four 0 47 uF ceramic ca pacitors in parallel can be used Note The charge pump is designed to nominallv provide 400 uA of current for the instrumentation amplifier when a 0 033 uF pumping capacitor is used XIN 32 768 kHz When a larger pumping capaci tor is used the charge pump can source more current to power external loads Refer to Applications Note 152 Using the CS5521 23 CS5522 24 28 and CS5525 26 Charge Pump Drive for External Loads for more details on using the charge pump with exter nal loads 2 9 Digital Gain Scaling The CS5521 22 23 24 and CS5528 all feature a gain register capable of being scaled from 0 6 to 4 2 22 in decimal The specified ranges of the con verter are defined with a voltage reference of 2 5 V and the gain register set at approximately 1 0 The gain register can be manipulated to scale the input for ranges other than those specified For example when using a 2 5 V voltage reference and the 25 mV inpu
19. conversion words deep Further note that the tvpe of conversion s performed and the wav to access the resulting data from the FIFO is determined bv the MC multiple conversion the LP loop the RC read convert and the DP depth pointer bits in the configuration register 2 4 1 Conversion Protocol The CS552x offer six different conversion modes which can be categorized into two main types of conversions one Setup conversions which refer ence only one Setup and multiple Setup conver sions which reference any number of Setups The converter can be instructed to perform single con versions or repeated conversions with or without wait in either of these modes using the MC LP and RC bits in the Configuration Register The MC bit controls whether the part will do one Setup or multiple Setup conversions The LP bit controls whether the part will perform a single or repeated conversion set When doing repeated conversion sets the RC bit controls whether or not the convert er will wait for the data from the current conversion set to be read before beginning the next conversion set The sections that follow further detail the vari ous conversion modes 2 4 1 1 Single One Setup Conversion LP 0MC 0RC X In this conversion mode the ADC will perform a single conversion referencing only one Setup and return to command mode after the data word has been fully read The 8 bit command word contains the CSRP bits which instruc
20. defining the min imum Full Scale Calibration Range FSCR under ANALOG CHARACTERISTICS margin is retained to accommodate the intrinsic gain error Alterna tively the input full scale signal can be increased to a point in which the modulator reaches its 1 s den sity limit of 80 percent which under nominal con dition occurs when the full scale input signal is 1 5 times the nominal full scale With the chip s intrin sic gain error this full scale input signal may be higher or lower In defining the maximum FSCR margin is again incorporated to accommodate the intrinsic gain error In addition for full scale inputs greater than the nominal full scale value of the range selected there is some voltage at which var ious internal circuits may saturate due to limited amplifier headroom This is most likely to occur in the 100 mV range 2 4 Performing Conversions and Reading the Data Conversion FIFO The CS5521 22 23 24 28 offers various modes of performing conversions The sections that follow detail the differences between the conversion modes The sections also provide examples illus trating how to use the conversion modes with the channel setup registers and to acquire conversions for further processing While reading note that the CS5521 22 have a FIFO which is four words deep The CS5523 24 have a FIFO which is eight words deep and the CS5528 has a FIFO which is sixteen DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28
21. only Setup 10 CS5528 only Setup 11 CS5528 only Setup 12 CS5528 only Setup 13 CS5528 only Setup 14 CS5528 only Setup 15 CS5528 only Setup 16 CS5528 only Lee vg ee Re Ae DS317F4 ii EE emm SSS III e LOGIC CS5521 22 23 24 28 PERFORM CALIBRATION D7 MSB D6 D5 D4 D3 D2 D1 DO 1 CSRP3 CSRP2 CSRP1 CSRPO CC2 CC1 CCO Function These commands instruct the ADC to perform a calibration on the physical input channel refer enced which is chosen by the command byte pointer bits CSRP3 CRSPO CSRP 3 0 Channel Setup Register Pointer Bits 0000 Setup 1 All devices 0001 Setup 2 All devices 0010 Setup 3 All devices 0011 Setup 4 All devices 0100 Setup 5 CS5523 24 28 only 0101 Setup 6 CS5523 24 28 only 0110 Setup 7 CS5523 24 28 only 0111 Setup 8 CS5523 24 28 only 1000 Setup 9 CS5528 only 1001 Setup 10 CS5528 only 1010 Setup 11 CS5528 only 1011 Setup 12 CS5528 only 1100 Setup 13 CS5528 only 1101 Setup 14 CS5528 only 1110 Setup 15 CS5528 only 1111 Setup 16 CS5528 only CC 2 0 Calibration Control Bits 000 Reserved 001 Self Offset Calibration 010 Self Gain Calibration 011 Reserved 100 Reserved 101 System Offset Calibration 110 System Gain Calibration 111 Reserved DS317F4 23 CS5521 22 23 24 28 CIRRUS LOGIC D7 MSB D6
22. other 2 Dimension eA to center of leads when formed parallel 3 Dimension E does not include mold flash DS317F4 53 ll EEE ERR rr m EE en E e IC CIRRUS LOC CS5521 22 23 24 28 24 PIN SKINNY PLASTIC PDIP 300 MIL PACKAGE DRAWING eB 54 JEDEC MS 001 Controling Dimension is Inches gh p HM D gt E1 l gre 1 ry faz fa SEATING NW TOP VIEW PLANE i AL L id L bet GE c bl lt b BOTTOM VIEW SIDE VIEW INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A 0 000 0 210 0 00 5 33 A1 0 015 0 020 0 025 0 38 0 51 0 64 A2 0 115 0 130 0 195 2 92 3 30 4 95 b 0 014 0 018 0 022 0 36 0 46 0 56 b1 0 045 0 058 0 070 1 14 1 46 1 78 c 0 008 0 010 0 014 0 20 0 25 0 36 D 1 230 1 255 1 280 31 24 31 88 32 51 E 0 300 0 310 0 325 7 62 7 87 8 26 E1 0 240 0 252 0 280 6 10 6 40 7 11 e 0 090 0 100 0 110 2 29 2 54 2 79 eA 0 280 0 30 0 320 7 11 7 62 8 13 eB 0 300 0 37 0 430 7 62 9 40 10 92 eC 0 000 0 060 0 00 1 52 L 0 115 0 130 0 150 2 92 3 30 3 81 oc 0 8 15 0 8 15 DS317F4 CS5521 22 23 24 28 20L SSOP PACKAGE DRAWING 4 D zZ TXI
23. ranged The OD flag will be cleared to logic 0 when the modulator becomes stable 29 CS5521 22 23 24 28 D23 MSB D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 NU NU CFS1 CFSO NU MC LP RC DP3 DP2 DP1 DPO D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO PSS PD PS R LPM RS RV OD OF NU NU NU NU BIT NAME VALUE FUNCTION D23 D22 Not Used NU 00 R Must always be logic 0 D21 D20 Chop Frequency Select 00 R 256 Hz Amplifier chop frequency XIN 32 768 kHz CFS1 CFSO 01 4 096 Hz Amplifier chop frequency 10 16 384 Hz Amplifier chop frequency 11 1 024 Hz Amplifier chop frequency D19 Not Used NU 0 R Must always be logic O D18 Multiple Conversion MC 0 R Perform single Setup conversions MC bit is ignored during calibrations 1 Perform multiple Setup conversions on Setups in the channel setup reg ister by issuing only one command with MSB 1 D17 Loop LP 0 R The conversions on the single Setup MC 0 or multiple Setups MC 1 are performed only once 1 The conversions on the single Setup MC 0 or multiple Setups MC 1 are continuously performed D16 Read Convert RC 0 R Don t wait for user to finish reading data before starting new conversions 1 The RC bit is used in conjunction with the LP bit when the LP bit is set to logic 1 If LP 0 the RC bit is ignored If LP 1 the ADC waits for user to read data conversion s before converting a
24. read the 6 conversion results 8 SCLKs are re quired to clear the SDO flag Then 144 additional SCLKs are required to read the conversion data from the FIFO Again the order in which the data is provided is the same as the order in which the channels are converted After the last 3 bytes of the conversion data corresponding to physical channel 3 is read the serial port automatically returns to the command mode where it will remain until the next valid command byte is received Example 4 The configuration register has the following bits as shown DP3 DP0 1001 MC 1 LP 1 RC 0 The command byte issued is 1XXX X000 These settings instruct the convert er to repeatedly perform multiple setup conver sions using ten Setups The order in which the channels are converted is 6 1 6 2 6 3 6 4 6 5 SDO falls after physical channel 5 is converted To read the 10 conversion results 8 SCLKs with SDI 0 are required to clear the SDO flag Then 240 more SCLKs are required to read the conver sion data from the FIFO The order in which the data is provided is the same as the order in which the channels are converted The first 3 bytes of data correspond to the first Setup which in this example is physical channel 6 the next 3 bytes of data cor respond to the second Setup which in this example is physical channel 1 and the last 3 bytes of data DS317F4 corresponds to 10th Setup which here is phvsical channel 5 Since the Set
25. register Note that while the RS bit is set to 1 all other register bits in the ADC will be reset to their default state and the RS bit must be set to 0 for normal operation of the converters Once the RS bit has been set to 0 the ADC is placed in the command state were it waits for a val id command to execute The next step is to load the configuration register and then the channel setup registers with conditions that vou have decided If vou need to do a factorv calibration perform offset and gain calibrations for each channel that is to be used Then off load the offset and gain register contents into EEPROM These registers can then be initialized to these conditions when the instru ment is used in normal operation Once calibration is readv input the command to start conversions in DS317F4 CS5521 22 23 24 28 the mode vou have selected via the configuration register bits Monitor the SDO pin for a flag that the data is readv and read conversion data 2 11 PCB Lavout The CS5521 22 23 24 28 should be placed entirely over an analog ground plane with both the AGND and DGND pins of the device connected to the an alog plane Place the analog digital plane split im mediately adjacent to the digital portion of the chip If separate digital VD and analog VA sup plies are used it is recommended that a diode be placed between them the cathode of the diode should point to VA If the digital supply comes
26. to as the power save modes They power down most of the analog portion of the chip and stop filter convolutions The power save modes are entered whenever the PS R bit of the configuration register is set to logic 1 The particular power save mode entered depends on state of bit D11 PSS the Power Save Select bit in the configuration register If PSS is logic 0 the converters enters the standby mode reducing the power consumption to 1 2 mW The standby mode leaves the oscillator and the on chip bias generator running This allows the converter to quickly return to the normal or low power mode once the PS R bit is set back to a logic 0 If PSS and PS R in the con figuration register are set to logic 1 the sleep mode is entered reducing the consumed power to around 500 uW Since the sleep mode disables the oscilla tor approximately a 500ms oscillator start up de lay period is required before returning to the normal or low power mode 2 2 8 4 Charge Pump Disable The pump disable PD bit permits the user to turn off the charge pump drive thus enabling the user to reduce the radiation of digital interference from the CPD pin when the charge pump is not being used 2 2 8 5 Reset System Control Bits The reset system RS bit permits the user to per form a system reset A system reset can be initiated at any time by writing a logic 1 to the RS bit in the DS317F4 configuration register After a svstem reset cvcle is complete the r
27. up before the analog supply the ADC may not start up properly 47 CIRRUS LOGIC 3 PINDESCRIPTIONS ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL IN ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL IN ANALOG GROUND POSITIVE ANALOG POWER SINGLE ENDED ANALOG INPUT SINGLE ENDED ANALOG INPUT SINGLE ENDED ANALOG INPUT SINGLE ENDED ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL IN ie 20 2 CS5521 49 CS5522 3 18 K te 7 24 CS5523 3 3 CS5524 4 4 21 5 20 6 19 1e 24 2 23 CS5528 3 22 4 21 5 20 CS5521 22 23 24 28 VOLTAGE REFERENCE INPUT VOLTAGE REFERENC
28. used to clear the SDO flag Ev ery 24 bits thereafter consist of the data words of each Setup that was referenced until all of the data has been read from the part If during the first 8 SCLKs 0000 0000 is provided on SDI the con verter will remain in this conversion mode and be gin performing the next set of conversions To exit this conversion mode 1111 1111 must be pro vided on SDI during the first 8 SCLKs If the user decides to exit 24 more SCLKs for each referenced Setup are required to read the final conversion data set from the FIFO and return to command mode 2 4 2 Calibration Protocol To perform a calibration the user must send a com mand byte with its MSB 1 its pointer bits CSRP3 CSRPO set to address the desired Setup to be calibrated and the appropriate calibration bits CC2 CC0 set to choose the type of calibration to be performed Proper calibration assumes that the CSRs have been previously initialized because the information concerning the physical channel its filter rate gain range and polarity comes from the channel setup register being addressed by the pointer bits in the command byte Once the CSRs are initialized all future calibra tions can be performed with one command byte Once a calibration cycle is complete SDO falls and the results are stored in either the gain or offset reg ister for the physical channel being calibrated Note that if additional calibrations are performed on the sa
29. 1 Mspl by2 bj2 by2 bygg KE i 0 D b d where the binary numbers have a value of either zero or one b corresponds to bit MSB 1 N 22 Refer to Table 5 for details The offset and gain calibration steps each take one conversion cycle to complete At the end of the cal ibration step SDO falls to indicate that the calibra tion has finished 2 3 1 Self Calibration The CS5521 22 23 24 28 offer both self offset and self gain calibrations For self calibration of offset in the 25 mV 55 mV and 100 mv ranges the con verters internally tie the inputs of the instrumenta tion amplifier together and route them to the AIN pin as shown in Figure 11 in the CS5528 they are routed to AGND For proper self calibration of Offset Register MSB LSB Register Sign 22 23 24 95 26 l 919 920 921 922 923 924 Reset R 0 0 0 0 0 0 0 0 0 0 0 0 One LSB represents 224 2 times unipolar span proportion of the input span when gain register is set to 1 0 decimal bipolar span is Offset and data word bits align bv MSB bit MSB 4 of offset register changes bit MSB 4 of data Gain Register MSB LSB Register 21 20 a1 92 93 24 l l 217 918 219 gt 20 5 21 5 22 Reset R 0 1 0 0 0 0 0 0 0 0 0 0 The gain register span is from 0 to 4 2 After Reset the MSB 1 bit is 1 all other bits are 0 Table 5 Offset and Gain
30. 15 D13 Gain Bits G2 GO 000 R 100 mV assumes VREF Differential 2 5 V D3 D1 001 55 mV 010 25 mV 011 1 0V 100 5 0 V 101 2 5 V 110 Not used 111 Not used D12 D0 Unipolar Bipolar U B 0 R Bipolar measurement mode 1 Unipolar measurement mode R indicates the bit value after the part is reset Table 3 Channel Setup Registers DS317F4 27 2 2 7 1 Latch Outputs The A1 A0 pins mimic the latch output D23 D11 D22 D10 bits of the channel setup registers Al AO can be used to control external multiplexers and oth er logic functions outside the converter The outputs can sink or source at least 1 mA but it is recom mended to limit drive currents to less than 20 LA to reduce self heating of the chip These outputs are powered from VA hence their output voltage for alogic 1 will be limited to the VA supply voltage 2 2 7 2 Channel Select Bits The channel select CS1 CSO bits are used to de termine which physical input channel will be used when a conversion is performed with a particular Setup 2 2 7 3 Output Word Rate Selection The word rate WR2 WRO bits of the channel set up registers set the output conversion word rate of the converter when a conversion is performed with a particular Setup The word rates indicated in Table 3 assume a master clock of 32 768 kHz and scale linearlv when using other master clock fre quencies Upon reset the converter is set to operate with an output wo
31. 250 ns SDI Write Timing CS Enable to Valid Latch Clock t3 50 ns Data Set up Time prior to SCLK rising ta 50 ns Data Hold Time After SCLK Rising ts 100 2 S ns SCLK Falling Prior to CS Disable tg 100 ns SDO Read Timing CS to Data Valid tz 150 ns SCLK Falling to New Data Bit tg S 150 ns CS Rising to SDO Hi Z tg 150 ns Notes 25 Device parameters are specified with a 32 768 kHz clock however clocks up to 200 kHz CS5522 24 28 or 130 kHz CS5521 23 can be used for increased throughput 26 Specified using 10 and 90 points on waveform of interest Output loaded with 50 pF 27 Oscillator start up time varies with crystal parameters This specification does not apply when using an external clock source 28 Applicable when SCLK is continuously running Specifications are subject to change without notice DS317F4 11 CS5521 22 23 24 28 CIRRUS LOGIC CS to 7 t D ty 4 SCLK MNT l EL te Figure 1 Continuous Running SCLK Timing Not to Scale cs k SDI MSB LSB te SCLK Figure 2 SDI Write Timing Not to Scale CS Lt bo SDO V V poe MSB MSB 1 i LSB te SCLK TEN Figure 3 SDO Read Timing Not to Scale DS317F4 12 l CIRRUS LOGIC CS5521 22 23 24 28 2 GENERAL DESCRIPTION The CS5521 22 23 24 28 are highly integrated AX Analog to Digital Conv
32. 45 section about manipulating the gain register to achieve optimum gain scaling 5V 10 Q Analog ETA M jui Supply ay JE 2 14 VA VD 11 2 5V 20 VREF XOUT 7771 32 768 100 kHz 19 si JE VREF 10 Optional Up to x 100 mV Input XIN Clock 22 10k2 gav199 ee CS55 Source VN t T 1 d uF 68 LI TJMAT geue D Serial 10 KQ AGND ru Data ZN 48 SDI Interface Cold Junction AIN2 SDO 12 5V ae AIN2 N V SUA A1 LM334 49 A0 Absolute IR NBV CPD DGND Logic Outputs C i S 5 7 jk AO A1 Switch from urren 499 Q VA to AGND Reference nz A 3010 1n4145 7 0033 F 1 eg Charge pump network i ERTER f uF 1N4148 for VD 5V only and 7 XIN 32 768 kHz Figure 21 CS5522 Configured to use on chip charge pump to supply NBV DS317F4 43 l CS5521 22 23 24 28 UN 45V Se SES Tee ZE 2 14 eL NA VA VD 11 N B gg KOL 32 768 100 kHz 19 VREF of Optional XIN Clock 7v CS5522 iy P AIN1 9 0 to 5V Input CS AIN1 15 i A ND C Rud l 8 ata SCH SDI mu c Interface CM 0 to VA AN e GI Hey CPD DGND b 7 his kal Figure 22 CS5522 Configured for ground referenced Unipolar Signals 5V d Analog oi F nl 0 1 uF Supply SUME T SC 2 14 8 VA VD 11 BEES XOUT FI 32 768 100kHz VREF Lok
33. 60 80 100 120 140 160 180 200 XIN kHz Figure 20 Typical Linearity Error for CS5522 24 28 DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 2 8 Power Supplv Arrangements The CS5521 22 23 24 28 A D converters are de signed to operate from a single 45 V analog supplv and a single 45 V or 43 V digital supply A 2 1 V supplv is usuallv generated from the charge pump drive to provide power to the instrumentation am plifiers NBV negative bias voltage pin Figure 21 illustrates the CS5522 connected with a 45 V analog supply and with the external compo nents required for the charge pump drive This en ables the CS5522 to measure ground referenced signals with magnitudes down to 100 mV Figure 22 illustrates the CS5522 connected to mea sure ground referenced unipolar signals of a posi tive polarity using the 1 V 2 5 V and 5 V ranges on the converter For the 25 mV 55 mV and 100 mV ranges the signals being digitized must have a common mode between 41 85 to 42 65 V NBV 0 V Although CS5521 22 23 24 28 are optimized for the measurement of thermocouple outputs they are also well suited for the measurement of ratiometric bridge transducer outputs Figure 23 illustrates the CS5522 connected to measure the output of a rati ometric differential bridge transducer while operat ing from a single 45 V supply Bridge outputs may range from 5 mV to 400 mV See Digital Gain Scaling on page
34. CIRRUS LOGIC CS5521 22 23 24 28 CSR Channel Setup Register CSR CSR 1 Setup 1 Setup 2 1 Setup 1 Setup 2 1 Setup 1 Setup 2 Bits lt 47 36 gt Bits lt 35 24 gt Bits lt 95 84 gt Bits lt 83 72 gt Bits lt 191 180 gt Bits lt 179 168 gt 2 Setup 3 Setup 4 Bits lt 23 12 gt Bits 11 0 L L 6 c HA Setup 7 Setup 8 8 Setup 15 Setup 16 Bits lt 23 12 gt Bits lt 11 0 gt Bits lt 23 12 gt Bits lt 11 0 gt CS5521 22 CS5523 24 CS5528 D23 MSB D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 A1 AO CS2 CS1 CSO WR2 WI WRO G2 G1 GO U B D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO A AO CS2 CS1 CSO WR2 WR1 WRO G2 G1 GO U B BIT NAME VALUE FUNCTION D23 D22 Latch Outputs A1 A0 00 R Latch Output Pins A1 A0 mimic D23 D11 D22 D10 register bits D11 D10 D21 D19 Channel Select CS2 000 R Select physical channel 1 All devices D9 D7 CSO 001 Select physical channel 2 All devices 010 Select physical channel 3 CS5523 24 28 only 011 Select physical channel 4 CS5523 24 28 only 100 Select physical channel 5 CS5528 only 101 Select physical channel 6 CS5528 only 110 Select physical channel 7 CS5528 only 111 Select physical channel 8 CS5528 only D18 D16 Word Rate WR2 WRO 000 R 15 0 Sps 2180 XIN cycles D6 D4 001 30 0 Sps 1092 XIN cycles 010 61 6 Sps 532 XIN cycles 011 84 5 Sps 388 XIN cycles 100 101 1 Sps 324 XIN cycles 101 1 88 Sps 17444 XIN cycles 110 3 76 Sps 8724 XIN cycles 111 7 51 Sps 4364 XIN cycles D
35. CMOS clock source with no start up delay is being used to drive the ADC then this delay is not necessary The converters include an on chip power on reset circuit to automatically reset the ADCs shortly af ter power up When power to the CS5521 22 23 24 28 is applied the chips are held in a reset condition until the 32 768 kHz oscillator has started and a counter timer elapses The counter timer counts 2006 oscillator clock cycles to make sure the oscillator is fully stable During this time out period the serial port logic is reset and the RV Reset Valid bit in the configuration regis ter is set to indicate that a valid reset occurred In normal start up conditions this power on reset cir cuit should reset the chip when power is applied If your application may experience abnormal power start up conditions the following sequence of in structions should be performed to guarantee the converter begins proper operation 1 After power is applied initialize the serial port using the serial port synchronization sequence 2 Write a 1 to the reset bit RS of the configu ration register to reset the converter 3 Read the configuration register to determine if the reset valid bit RV is set to 1 If the RV bit is not set the configuration register should be read again 4 When the RV bit has been set to 1 reset the RS bit back to 0 by writing to 0x000000 to the DS317F4 CIRRUS LOGIC configuration
36. E INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA OUT CRYSTAL OUT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA OUT CRYSTAL OUT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT SINGLE ENDED ANALOG INPUT SINGLE ENDED ANALOG INPUT SINGLE ENDED ANALOG INPUT SINGLE ENDED ANALOG INPUT LOGIC OUTPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA OUT CRYSTAL OUT DS317F4 till EE gn CIRRUS LOGIC CS5521 22 23 24 28 3 1 Clock Generator XIN XOUT Crystal In Crystal Out A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device Alternatively an external CMOS compatible clock can be supplied into the XIN pin to provide the master clock for the device 3 2 Control Pins and Serial Data I O CS Chip Select When active low the port will recognize SCLK When high the SDO pin will output a high impedance state CS should be changed when SCLK 0 SDI Serial Data Input SDI is the input pin of the serial input port Data will be input at a rate determined by SCLK SDO Serial Data Output SDO is the seri
37. ION BITS CS5521 23 ena 7 TYPICAL RMS NOISE CS5522 24 28 nanna rna 8 TYPICAL NOISE FREE RESOLUTION BITS CS5522 24 28 L sss 8 5 V DIGITAL GHARAGCTERISTICS nanna arm tana n nnne nanna anna tna 9 3 V DIGITAL CHARACTERISTICS nanna nanna na nnnnr att mnannnnnn ta 9 DYNAMIC CHARACTERISTICS nanna nanna ainada 10 RECOMMENDED OPERATING CONDITIONS Lena nn rna anna nanna 10 ABSOLUTE MAXIMUM RATINGS Lanka nat nnr entrent enr sinn nn en nes 10 SWITCHING CHARACTERISTICS nn nn a nn nanna nnns aE 11 2 GENERAL DESCRIPTION li is e 13 P Analog Input EL 13 2 1 1 Instrumentation Amplifier AAA 14 2 1 2 Coarse Fine Charge Buffers c nn 14 2 1 3 Analog Input Span Considerations ners ann 15 2 1 4 Measuring Voltages Higher than 5V essssssssrrrsssssrnensrennnesrnnnnnnennnnnnsnennnnsnnnnnns 15 2 1 5 Voltage Reference uen ab cnet cere erster eed cena dese dps 16 2 2 Overview of ADC Register Structure and Operating Modes nn 16 2 2 1 System Initialization L nanna ener enne 18 2 2 2 Serial Port Initialization Sequence nn 18 2 2 3 Command Register Quick Reference Lara 19 2 2 4 Command Register Descriptions c nanna 20 2 2 5 Serial Port Interface nn 25 2 2 6 Reading Writing the Offset Gain and Configuration Registers 26 2 2 7 Reading Writing the Channel Setup Registers sena 26 2 2 7 1 Latch Outputs we
38. READ WRITE CHANNEL SETUP REGISTER S D7 MSB D6 D5 D4 D3 D2 D1 DO 0 0 0 0 R W 1 0 1 Function These commands are used to access the channel setup registers CSRs The number of CSRs accessed is determined by the device being used and the number of CSRs that are being accessed i e the depth bits in the configuration register determine the number of levels ac cessed This register is 48 bits long 4 Setups for the CS5521 22 96 bits long 8 Setups for the CS5523 24 and 192 bits 16 Setups long for the CS5528 R W Read Write 0 Write to selected register 1 DS317F4 Read from selected register 21 ii EE emm CIRRUS LOGIC PERFORM CONVERSION CS5521 22 23 24 28 D7 MSB D6 D5 D4 D3 D2 D1 DO 1 CSRP3 CSRP2 CSRP1 CSRPO 0 0 0 Function These commands instruct the ADC to perform conversions on the physical input channel point CSRP 3 0 Channel Setup Register Pointer Bits 22 ed to by the pointer bits CSRP2 CSRPO in the channel setup registers The particular type of conversion performed is determined by the states of the conversion control bits the multiple conversion bit the loop bit read convert bit and the depth pointer bits in the configuration reg ister Setup 1 All devices Setup 2 All devices Setup 3 All devices Setup 4 All devices Setup 5 CS5523 24 28 Setup 6 CS5523 24 28 Setup 7 CS5523 24 28 Setup 8 CS5523 24 28 Setup 9 CS5528
39. SE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks c service marks of their respective owners SPI is a trademark of Motorola Inc 2 DS317F4 l CIRRUS LOGIC CS5521 22123 24128 m 2 2 7 5 Unipolar Bipolar Bit siti eic e nce rettet tee 28 2 2 8 Configuration Register L ran 28 2 2 8 1 Chop Frequency Select L anna 28 2 2 8 2 Conversion Calibration Control Bits L 28 2 2 8 3 Power Consumption Control Bits 28 2 2 8 4 Charge Pump Disable sse 29 2 2 8 5 Reset System Control Bits L nn 29 2 2 8 6 Data Conversion Error Flags Lena 29 SMEs 31 2 9 1 Self Calibration or erede f Ee a tuae e pa 31 2 9 2 System Calibratori tratana endan aiiai ti e Eva e ev xe reme edet ies 32 2 9 3 Calibration TIPS 2 neret aa an a per a 34 2 3 4 Limitations in Calibration Range nanna 34 2 4 Performing Conversions and Reading the Data Conversion FIFO sses 34 2 4 1 Conversion Protool EE 35 2 4 1 1 Single One Setup Conversion sss 35 2 4 1 2 Repeated One Setup Conversions without Wait L 35 2 4 1 3 Repeated One Setup Conversions with Wait L 36 2 4 1 4 Single Multiple Setup Conversions s
40. Tear le elt Si L END VIEW O SEATING Xi SIDE VIEW PLANE UU 1 23 TOP VIEW INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0 084 2 13 A 0 002 0 006 0 010 0 05 0 13 0 25 A2 0 064 0 068 0 074 1 62 1 73 1 88 b 0 009 0 015 0 22 0 38 2 3 D 0 311 0 323 0 335 7 90 8 20 8 50 1 E 0 291 0 307 0 323 7 40 7 80 8 20 E1 0 197 0 209 0 220 5 00 5 30 5 60 1 e 0 022 0 026 0 030 0 55 0 65 0 75 L 0 025 0 03 0 041 0 63 0 75 1 03 oc 0 4 8 0 4 8 JEDEC MO 150 Controling Dimension is Millimeters 1 D and E1 are reference datums and do not included mold flash or protrusions but do include mold mismatch and are measured at the parting line mold flash or protrusions shall not exceed 0 20 mm per side 2 Dimension b does not include dambar protrusion intrusion Allowable dambar protrusion shall be 0 13 mm total in excess of b dimension at maximum material condition Dambar intrusion shall not reduce dimension b by more than 0 07 mm at least material condition 3 These dimensions apply to the flat section of the lead between 0 10 and 0 25 mm from lead tips DS317F4
41. V VA V NBV AGND Range 25 mV 55 mV or 100 mV Note 7 1 85 2 65 V Range 1V 2 5V or5V 0 0 VA V CVF Current on AIN or AIN Note 8 Range 25 mV 55 mV or 100 mV 100 300 pA Range 1 V 2 5 V or5 V 10 nA Input Current Drift Note 8 Range 25 mV 55 mV or 100 mV 1 pA C Input Leakage for Multiplexer when Off 10 x pA Common Mode Rejection dc 120 dB 50 60 Hz 120 dB Input Capacitance 10 S pF Voltage Reference Input Range VREF VREF 1 2 5 VA V VREF VREF 1 VA V VREF NBV VREF 1 V CVF Current Note 8 5 0 nA Common Mode Rejection dc 110 dB 50 60 Hz 130 dB Input Capacitance 16 S pF System Calibration Specifications Full Scale Calibration Range VREF 2 5V Bipolar Unipolar Mode 25 mV 10 32 5 mV 55mV 25 71 5 mV 100 mV 40 105 mV 1V 0 40 1 30 V 2 5V 1 0 3 25 V 5V 2 0 VA V Offset Calibration Range Bipolar Unipolar Mode 25 mV 12 5 mV 55 mV 27 5 mV 100 mV Note 9 50 mV 1V 0 5 V 2 5 V 1 25 V 5V 2 50 V Notes 7 For the CS5528 the 25 mV 55 mV and 100 mV ranges cannot be used unless NBV is powered at 1 8 to 2 5 V 8 See the section of the data sheet which discusses input models Chop clock is 256 Hz XIN 128 for PGIA programmable gain instrumentation amplifier XIN 32 768 kHz 9 The maximum full scale signal can be limited by saturation of circuitry within the internal signal path 6 DS317F4
42. Voltage pin allowing the CS5521 22 23 24 28 to be operated in either of two analog input configurations The NBV pin can be bi ased to a negative voltage between 1 8 V and 2 5 V or tied to AGND for the CS5528 NBV has to be between 1 8 V and 2 5 V forthe ranges below 100 mV when the amplifier is engaged The com mon mode plus signal range of the instrumentation amplifier is 1 85 V to 2 65 V with NBV grounded The common mode plus signal range of the instru mentation amplifier is 0 150 V to 0 950 V with NBV between 1 8 V to 2 5 V Whether NBV is tied between 1 8 V and 2 5 V or tied to AGND the Common Mode Signal input on AIN and AIN must stay between NBV and VA Figure 5 illustrates an analog input model for the ADCs when the instrumentation amplifier is en gaged The CVF sampling input current for each of the analog input pins depends on the CFS1 and CFSO Chop Frequency Select bits in the configu ration register see Configuration Register for de tails Note that the CVF current is lowest with the 25 mV 55 mV and 100 mV Ranges v e gt AIN D C 48 pF y Vos 25 mV in fVos C CFS1 CFSO 00 f 256 Hz CFS1 CFS0 01 f 4096 Hz CFS1 CFSO 10 f 16 384 kHz CFS1 CFS0 11 f 1024 Hz Figure 5 Input Models for AIN and AIN pins lt 100 mV Input Ranges 14 CFS bits in their default states cleared to logic Os Further note that the CVF current into the instru mentation
43. ak noise calibration should be performed at lower output word rates Also to minimize digital noise near the device the user should wait for each calibration step to be completed before reading or writing to the serial port For maximum accuracy calibrations should be per formed for offset and gain selected by changing the G2 G0 bits of the desired Setup Note that only one gain range can be calibrated per physical chan nel If factory calibration of the user s system is performed using the system calibration capabilities of the CS5521 22 23 24 28 the offset and gain reg ister contents can be read by the system microcon troller and recorded in EEPROM These same calibration words can then be uploaded into the off set and gain registers of the converter when power is first applied to the system or when the gain range is changed 34 CS5521 22 23 24 28 2 3 4 Limitations in Calibration Range System calibration can be limited by signal head room in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet For gain calibration the full scale input signal can be reduced to the point in which the gain register reaches its upper limit of 4 2 decimal or FFFFFF hexadecimal Under nominal condi tions this occurs with a full scale input signal equal to about 1 4 the nominal full scale With the converter s intrinsic gain error this full scale input signal may be higher or lower In
44. al data output It will output a high impedance state if CS 1 SCLK Serial Clock Input A clock signal on this pin determines the input output rate of the data for the SDI SDO pins respectivelv This input is a Schmitt trigger to allow for slow rise time signals The SCLK pin will recognize clocks only when GS is low AO A1 Logic Outputs The logic states of A0 A1 mimic the states of the D22 D10 D23 D11 bits of the channel setup register Logic Output 0 AGND and Logic Output 1 VA 3 3 Measurement and Reference Inputs AIN1 AIN1 AIN2 AIN2 AIN3 AIN3 AIN4 AIN4 Differential Analog Input Differential input pins into the CS5522 and CS5524 devices AIN1 AIN2 AIN3 AIN4 AINS AIN6 AIN7 AIN8 Single Ended Analog Input Single ended input pins into the CS5528 VREF VREF Voltage Reference Input Fully differential inputs which establish the voltage reference for the on chip modulator DS317F4 49 ii EE emm SSS CIRRUS LOGIC CS5521 22 23 24 28 NBV Negative Bias Voltage Input pin to supply the negative supply voltage for the 20X gain instrumentation amplifier and coarse fine charge buffers May be tied to AGND if AIN and AIN inputs are centered around 2 5 V or it may be tied to a negative supply voltage 2 1 V typical to allow the amplifier to handle low level signals more negative than ground When using the CS5528 in either the 25 mV 55 mV or 100 mV range the anal
45. amplifier is less than 300 pA over 40 C to 85 C Note that Figure 5 is for input current modeling only For physical input capacitance see Input Capacitance specification under ANALOG CHARACTERISTICS Also refer to Applications Note AN30 Switched Capacitor A D Converter Input Structures for more details on input models and input sampling currents Note Residual noise appears in the converter s baseband for output word rates greater than 61 6 Sps if the CFS bits are logic 0 chop clock 256 Hz For word rates of 30 Sps and lower 256 Sps chopping is recommended and for 61 6 Sps 84 5 Sps and 101 1 Sps word rate set tings 4096 Hz chopping is recommended 2 1 2 Coarse Fine Charge Buffers The unity gain buffers are activated any time conver sions are performed with the high level inputs rang es 1 V 2 5 V and 5 V The unity gain buffers are designed to accommodate rail to rail input signals The common mode plus signal range for the unity gain buffer amplifier is NBV to VA Typical CVF sampling current for the unity gain buffer amplifiers is about 10 nA XIN 32 768 kHz see Figure 6 1 V 2 5 V and 5 V Ranges 4 Fine 6 Coarse AIN NM e ox Vos 25 mV ie in fVos C f 32 768 kHz Figure 6 Input Models for AIN and AIN pins gt 100 mV input ranges DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 2 1 3 Analog Input Span Considerations The CS5521 22 23 24 28 i
46. ative than zero unipolar mode or when the input is more neg ative than the negative full scale bipolar mode D3 DO Not Used NU 0000 R Must always be logic 0 R indicates the bit value after the part is reset 30 Table 4 Configuration Register DS317F4 2 3 Calibration The CS5521 22 23 24 28 offer four different cali bration functions including self calibration and sys tem calibration However after the devices are reset the converter is functional and can perform measurements without being calibrated In this case the converter will utilize the initialized values of the on chip registers Gain 1 0 Offset 0 0 to calculate output words for the 100 mV range Any initial offset and gain errors in the internal cir cuitry of the chip will remain The gain and offset registers which are used for both self and system calibration are used to set the zero and full scale points of the converter s transfer function One LSB in the offset register is qu pro portion of the input span when the gain register is set to 1 0 decimal bipolar span is 2 times the uni polar span The MSB in the offset register deter mines if the offset to be trimmed is positive or negative 0 positive 1 negative The converter can typically trim 50 percent of the input span The CS5521 22 23 24 28 gain register spans from 0 to 4 2 72 The decimal equivalent meaning of the gain register is N 1 0 f N
47. ay capacitance Note that the oscillator circuit will also operate with a 100 kHz tuning fork type crystal 0 1 1 10 d Led BO e 380 dl 40 50 704 80 90 l 100 _ TIOE L 120 130 fm fe for OWR 15 0 Sps f1 47 5 Hz f2 65 5 Hz mm fS 2 XIN 4 Attenuation dB Figure 18 Filter Response Normalized to Output Word Rate 15 Sps 42 CS5521 22 23 24 28 The converters will operate with an external CMOS compatible clock with frequencies up to 130 kHz CS5521 23 or 200 kHz CS5522 24 28 Figures 19 and 20 detail the CS5521 23 and CS5522 24 28 s performance respectively at in creased clock rates The 32 768 kHz crystal is normally specified as a time keeping crystal with tight specifications for both initial frequency and for drift over tempera ture To maintain excellent frequency stability these crystals are specified only over limited oper ating temperature ranges i e 10 C to 60 C However applications with the CS5521 22 23 24 28 don t generally require such tight tolerances 0 002 0 0018 0 0016 4 0 0014 4 0 0012 0 001 0 0008 0 0006 0 0004 Linearity Error FS XIN kHz Figure 19 Typical Linearity Error for CS5521 23 0 0013 0 0012 0 0011 0 001 0 0009 0 0008 0 0007 0 0006 0 0005 0 0004 Linearity Error FS 20 40
48. converted To read the conversion results 32 SCLKs are then re quired Once acquired the serial port returns to the command mode Example 2 The configuration register has the following bits as shown DP3 DPO XXXX MC 0 LP 1 RC 1 The command byte issued is 1001 1000 These settings instruct the converter to repeatedly convert the fourth Setup as CPB3 CPBO 0011 which happens to be physical channel 2 in this ex ample SDO falls after physical channel 2 is con verted To read the conversion results 32 SCLKs are required The first 8 SCLKs are needed to clear the SDO flag If 0000 0000 is provided to the SDI pin during the first 8 SCLKs the conversion is per formed again on physical channel 2 The converter will remain in data mode until 1111 1111 is pro vided during the first 8 SCLKs following the fall of DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 SDO After 1111 1111 is provided 24 additional SCLKs are required to transfer the last 3 bytes of conversion data before the serial port will return to the command mode Example 3 The configuration register has the following bits as shown DP3 DP 0101 MC 1 LP 0 RC X The command issued is IXXX X000 These settings instruct the converter to perform a single conversion on six Setups once The order in which the channels are converted is 6 1 6 2 6 and 3 SDO falls after physical channel 3 is converted To
49. de Any other bits written to the configuration register at this time will be lost The configuration reg ister must be written again once RS 0 to set any other bits 2 2 2 Serial Port Initialization Sequence The serial port is initialized to the command mode whenever a power on reset is performed inside the converter or when the user transmits the port ini tialization sequence The port initialization se quence involves clocking 15 bytes of all 1 s followed by one byte with the following bit con tents 1111 1110 This sequence places the chip in the command mode where it waits for a valid com mand to be written DS317F4 IC CIRRUS LOG 2 2 3 Command Register Quick Reference CS5521 22 23 24 28 D7 MSB D6 D5 D4 D3 D2 D1 DO CB CS2 CS1 CS0 RAW RSB2 RSB1 RSBO BIT NAME VALUE FUNCTION D7 Command Bit CB 0 Must be logic 0 for these commands 1 See table below D6 D4 Channel Select Bits 000 CS2 CS0 provide the address of one of the eight physical CSB2 CSBO channels These bits are used to access the calibration regis ters associated with respective channels 111 Note These bits are ignored when reading the data register D3 Read Write R W 0 Write to selected register 1 Read from selected register D2 DO Register Select Bit 000 Reserved RSB2 RSBO 001 Offset Register 010 Gain Register 011 Configuration Register 101
50. er than 5 V 16 Figure 8 illustrates the input models for the VREF pins The dynamic input current for each of the pins can be determined from the models shown 2 2 Overview of ADC Register Structure and Operating Modes The CS5521 22 23 24 28 ADCs have an on chip controller which includes a number of user acces sible registers The registers are used to hold offset and gain calibration results configure the chip s operating modes hold conversion instructions and to store conversion data words Figure 9 depicts a block diagram of the on chip controller s internal registers for the CS5523 24 Each of the converters has 24 bit registers to func tion as offset and gain calibration registers for each channel The converters with two channels have two offset and two gain calibration registers the converters with four channels have four offset and four gain calibration registers and the eight chan nel converter has eight offset and eight gain cali bration registers These registers hold calibration results The contents of these registers can be read or written by the user This allows calibration data to be off loaded into an external EEPROM The user can also manipulate the contents of these reg isters to modify the offset or the gain slope of the converter The converters include a 24 bit configuration reg ister of which 17 of the bits are used for setting op tions such as the conversion mode operating power options settin
51. er would transmit the write command 0x05 hexadecimal and follow that command with 24 bits of data Similarly to read CSR1 the user must transmit the command byte OxOD hexadecimal and then read the 24 bits of data To write more than one CSR for instance CSR1 and CSR2 Setupl Setup2 Setup3 and Setup4 the user would first set the depth pointer bits in the configu ration register to 0011 binary The user would then transmit the write CSR command 0x05 hexadeci mal and follow that with the information for Setup1 Setup2 Setup 3 and Setup 4 which is 48 bits of information Note that while reading writing CSRs two Setups are accessed in pairs as a single 24 bit CSR register Even if one of the Setups isn t used it must be written to or read Further note that the CSRs are accessed as a closed array the user can not access CSR2 without accessing CSR1 This requirement means that the depth bits in the config uration register can only be set to one of the follow ing states when the CSRs are being read from or written to 0001 0011 0101 0111 1001 1011 1101 1111 Examples detailing the power of the CSRs are provided in the Performing Conversions and Reading the Data Conversion FIFO section Once the CSRs are written to or read from the serial port returns to the command mode DS317F4
52. erters ADCs which use charge balance techniques to achieve 16 bit CS5521 23 and 24 bit CS5522 24 28 perfor mance The ADCs come as either two channel C55521 22 four channel CS5523 24 or eight channel CS5528 devices and include a low input current chopper stabilized instrumentation ampli fier To permit selectable input spans of 25 mV 55 mV 100 mV 1 V 2 5 V and 5 V the ADCs in clude a PGA programmable gain amplifier To accommodate ground based thermocouple applica tions the devices include a CPD Charge Pump Drive which provides a negative bias voltage to the on chip amplifiers These devices also include a fourth order DS mod ulator followed by a digital filter which provides eight selectable output word rates of 1 88 Sps 3 76 Sps 7 51 Sps 15 Sps 30 Sps 61 6 Sps 84 5 Sps and 101 1 Sps XIN 32 768 kHz The devices are capable of producing output update rates up to 617 Sps when a 200 kHz clock is used CS5522 24 28 or up to 401 Sps using a 130 kHz clock CS5521 23 Further note that the digital fil CS5522 AIN2 I IN AIN2 M AIN1 Il u AIN1 4 1 IN X I I I I I I I I I I I AIN4 41055524 I I AIN4 M IN x e n N12 i I I I I I I I I I I I I I Ap 055528 Differential Digital Programmable Ath order l Filter Gain delta sigma ban modulator ters are designed to settle to full accuracy within one conversio
53. eset valid RV bit is set indicating that the internal logic was properlv reset The RV remains set until the configuration register is read Note that the user must write a logic 0 to the RS bit to take the part out of the reset mode No other bits in the configuration register can be written at this time A subsequent write to the configuration reg ister is necessarv to write to anv other bits in this register Once reset the on chip registers are ini tialized to the following states configuration register 000040 H offset registers 000000 H gain registers 400000 H channel setup registers 000000 H 2 2 8 6 Data Conversion Error Flags The oscillation detect OD and overflow OF bits in the configuration register are flag bits used to in dicate that the ADC performed a conversion on an input signal that was not within the conversion range of the ADC For convenience the OD and OF bits are also in the data conversion word of the CS5521 23 The OF bit is set to logic 1 when the input signal is 1 more positive than full scale 2 more negative than zero in unipolar mode or 3 more negative than negative full scale in bipo lar mode The OF flag is cleared to logic 0 when a conversion occurs which is not out of range The OD bit is set to logic 1 any time that an oscil latory condition is detected in the modulator This does not occur under normal operating conditions but may occur when the input is extremely over
54. g the chop clock rate of the instru 64 Fine 05 Coarse VREF L v 1 gt Vos 25mV KEN in fVosC f 32 768 kHz Figure 8 Input Model for VREF and VREF Pins DS317F4 mentation amplifier and providing a number of flags which indicate converter operation A group of registers called Channel Set up Regis ters are also included in the converters These reg isters are used to hold pre loaded conversion instructions Each channel set up register is 24 bits wide and holds two 12 bit conversion instructions Setups Upon power up these registers can be initialized by the user s microcontroller with con version instructions The user can then use bits in the configuration register to choose a conversion mode Several conversion modes are possible Using the single conversion mode an 8 bit command word can be written into the serial port The command in cludes pointer bits which point to a 12 bit com mand in one of the Channel Setup Registers which is to be executed The 12 bit commands can be set up to perform a conversion on any of the input channels of the converter More than one of the 12 bit Setups can be used for the same analog input channel This allows the user to convert on the same signal with either a different conversion speed a different gain range or any of the other op tions available in the Setup Register The user can CS5521 22 23 24 28 set up the registers to perform co
55. gain The RC bit is ignored during calibrations Refer to Calibration Protocol for details D15 D12 Depth Pointer DP3 DPO 0000 R When writing or reading the CSRs these bits DP3 DPO determine the l number of CSR s to be accessed 0000 1 Thev are also used to deter e mine how many Setups are converted when MC 1 and a command byte 1111 with its MSB 1 is issued Note that the CS5522 has two CSRS the CS5524 has four CSRs and the CS5528 has 8 CSRs D11 Power Save Select PSS 0 R Standby Mode Oscillator active allows quick power up 1 Sleep Mode Oscillator inactive D10 Pump Disable PD 0 R Charge Pump Enabled 1 For PD 1 the CPD pin goes to a Hi Z output state D9 Power Save Run PS R 0 R Run 1 Power Save D8 Low Power Mode LPM 0 R Normal Mode LPM bit is only for the CS5522 24 28 1 Reduced Power Mode D7 Reset System RS 0 R Normal Operation 1 Activate a Reset cycle To return to Normal Operation write bit to zero D6 Reset Valid RV 0 No reset has occurred or bit has been cleared read only 1 R Bitis set after a Valid Reset has occurred Cleared when read D5 Oscillation Detect OD 0 R Bit is clear when an oscillation condition has not occurred read only 1 Bit is set when an oscillatory condition is detected in the modulator D4 Overrange Flag OF 0 R Bit is clear when an overrange condition has not occurred read only 1 Bit is set when input signal is more positive than the positive full scale more neg
56. han 0 6 This can enable the converter to accept a 40 mV input signal on the 25 mV range when using a voltage reference of 2 5 V Caution though in scaling the gain register below 1 0 on the 100 mV 2 5 and 5 volt ranges as the analog signal path into the converter may saturate before the expected full scale code output is produced by the converter Note that digital gain scaling will directly influence the number of digital output codes affected by noise The effects can be analytically determined by calculating the size of the codes V Count which result from a given gain scaling condition and relating the amount of noise in the converter relative to the determined code size The evalua tion board for the converter is a useful tool to aid the assessment of noise performance with various voltage reference values input range settings and gain register settings The evaluation board sup ports noise analysis through data capture and noise histogram analysis 46 2 10 Getting Started The CS5521 22 23 24 28 have many features From a software programmer s perspective what should be done first To begin a 32 768 kHz crys tal takes approximately 500 ms to start up To ac commodate for this it is recommended that a software delay of approximately 500 ms to 1 sec ond precede the processors ADC initialization code before any registers are accessed in the ADC This delay time is dependent on the start up delay of the clock source If a
57. input all scale directly with the value of the voltage reference The values in the table assume a2 5 V VREF voltage 2 The 2 8 V limit at the output of the 20X amplifier is the differential output voltage DS317F4 15 l CIRRUS LOGIC CS5521 22 23 24 28 mentation amplifier typically 100 pA is low enough to permit large external resistors to divide down a large external signal without significant loading Figure 7 illustrates an example circuit Re fer to Application Note 158 for more details on high voltage gt 5 V measurement 2 1 5 Voltage Reference The CS5521 22 23 24 28 devices are specified for operation with a 2 5 V reference voltage between the VREF and VREF pins of the device For a single ended reference voltage such as the LT1019 2 5 the reference voltage is input into the VREF pin of the converter and the VREF pin is grounded The differential voltage between the VREF and VREF can be any voltage from 1 0 V up to VA however the VREF cannot go above VA and the VREF pin can not go below NBV 45V t 0 1 pF I E o1uF VA VD 2 5 V o VREF VREF NC 1MQ 10Vo N e P Voltage 10 Ka PGIA AX ADC Divider E NA PGIA set for NA 100 mV chop clock 256 Hz NEWL lg CPD DGND EE iE mns V 2AV 1N4148 0 033 uF Charge Pump IBAT85 SZ 10uF SZ 1N4148 Circuitry l l I Figure 7 Input Ranges Great
58. iss cise ne arm te ees te tope hes Eee ERR a irene 28 2 2 7 2 Channel Select Bits A 28 2 2 7 3 Output Word Rate Selection ssssssssssseenene 28 2 2 7 4 Qain BIS eee acento Re ra 28 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject t change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant infor mation to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplier at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for thi use of this information including use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property righ
59. l one s gain register the user must first transmit the command byte 0x0A hexadeci mal and then read the 24 bits of data Once an off set a gain or the configuration register is written to or read from the serial port returns to the command mode 2 2 7 Reading Writing the Channel Setup Reg isters The CS5521 22 have two 24 bit channel setup reg isters CSRs The CS5523 24 have four CSRs and the CS5528 has eight CSRs refer to Table 3 for more detail on the CSRs These registers are ac cessed in conjunction with the depth pointer bits in the configuration register Each CSR contains two 12 bit Setups which are programmed by the user to contain data conversion or calibration information such as 1 state of the output latch pins 2 output word rate 3 gain range 4 polarity 5 the address of a physical input channel to be converted 26 Once programmed they are used to determine the mode e g unipolar 15 Sps 100 mV range etc the ADC will operate in when future conversions or calibrations are performed To access the CSRs the user must first initialize the depth pointer bits in the configuration register as these bits determine the number of CSRs to read from or write to For example to write CSR1 Setup1 and Setup2 the user would first program the configuration register s depth pointer bits with 0001 binary This notifies the ADC s serial port that only the first CSR is to be accessed Then the us
60. me physical channel referenced by a different Setup with different filter rates gain ranges or con version modes the last calibration results will re place the effects from the previous calibration as only one offset and gain register is available per physical channel One final note is that only one calibration is performed with each command byte To calibrate all the channels additional calibration commands are necessary 38 2 4 3 Example of Using the CSRs to Perform Conversions and Calibrations Any time a calibration command is issued CB 1 and proper CC2 CCO bits set or any time a normal conversion command is issued CB 1 CC2 CC1 CC0 0 MC 0 the bits D6 D3 or CSRP3 CSRPO in the command byte are used as pointers to address one of the Setups in the chan nel setup registers CSRs Five example situations that a user might encounter when acquiring a con version or calibrating the converter follow These examples assume that the user is using a CS5528 16 Setups and that its CSRs are programmed with the following physical channel order 6 1 6 2 6 3 6 4 6 5 6 2 6 7 6 8 Example 1 The configuration register has the following bits as shown DP3 DP0 XXXX MC 0 L 0 RC X The command issued is 11110000 These settings instruct the converter to convert the 15th Setup once as CPB3 CPBO 1110 which happens to be physical channel 6 in this example SDO falls after physical channel 6 is
61. mmable gain amplifier To ac commodate ground based thermocouple applications the devices include a charge pump drive which provides a negative bias voltage to the on chip amplifiers These devices also include a fourth order AX modulator followed by a digital filter which provides eight selectable output word rates The digital filters are designed to settle to full accuracy within one conversion cycle and when operated at word rates below 30 Sps they reject both 50 Hz and 60 Hz interference These single supply products are ideal solutions for measuring isolated and non isolated low level signals in process control applications ORDERING INFORMATION See page 52 DGND VD A Controller AINE 2 n Setup Registers AIN1 9 Digital Filter amp ES Channel Scan AIN2 SO Logic AIN2 MUX 8 Modulator a AIN3 9 CS5524 Shown v CS AING AIN4 Serial Port SCLK Interface AIN4 Clock Data FIFO amp SDI Gen Calibration Registers SDO NBV CPD AO A1 XIN XOUT gt e CIRRUS LOGIC AUG 05 ved Copyright O Cirrus Logic Inc 2005 http www cirrus com d Tan Rights En DS317F4 l CS5521 22 23 24 28 CIRRUS LOGIC TABLE OF CONTENTS 1 CHARACTERISTICS AND SPECIFICATIONS eene nnne nnne nennen nnn nnne 5 ANALOG CHARACTERISTIGQS f a din 5 TYPICAL RMS NOISE Cp 7 TYPICAL NOISE FREE RESOLUT
62. n 0 2 Plastic SSOP 2 240 C 365 Days CS5524 ASZ 24 pin 0 2 Plastic SSOP Lead Free 3 260 C 7 Days CS5528 AS 24 pin 0 2 Plastic SSOP 2 240 C 365 Days CS5528 ASZ 24 pin 0 2 Plastic SSOP Lead Free 3 260 C 7 Days MSL Moisture Sensitivity Level as specified by IPC JEDEC J STD 020 52 DS317F4 US LOGIC CS5521 22 23 24 28 7 PACKAGE DIMENSION DRAWINGS 20 PIN PLASTIC PDIP 300 MIL PACKAGE DRAWING H eB gu gu B den E1 L E 1 ng hg faz fa SEATING E L PLANE TOP VIEW Cup L a gt bi Le b AT eA BOTTOM VIEW SIDE VIEW INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A 0 000 0 210 0 00 5 33 A1 0 015 0 020 0 025 0 38 0 508 0 64 A2 0 115 0 130 0 195 2 92 3 302 4 95 b 0 014 0 018 0 022 0 36 0 4572 0 56 bi 0 045 0 058 0 070 1 14 1 46 1 78 c 0 008 0 010 0 014 0 20 0 25 0 36 D 0 980 1 030 1 060 24 89 26 162 26 92 E 0 300 0 310 0 325 7 62 7 874 8 26 E1 0 240 0 252 0 280 6 10 6 40 7 11 e 0 090 0 100 0 110 2 29 2 54 2 79 eA 0 280 0 30 0 320 7 11 7 62 8 13 eB 0 300 0 37 0 430 7 62 9 40 10 92 eC 0 000 0 060 0 00 1 52 L 0 115 0 130 0 150 2 92 3 302 3 81 oc 0 8 15 0 8 15 JEDEC MS 001 Controling Dimension is Inches Notes 1 Positional tolerance of leads shall be within 0 25 mm 0 010 in at maximum material condition in relation to seating plane and each
63. n conversions are performed The multi ple conversion MC bit instructs the converter to perform conversions on the number of Setups in the channel setup registers which are referenced by the depth pointer bits The converter begins with Setupl and moves sequentially through the Setups in this mode The Loop LP bit instructs the con verter to continuously perform conversions until a Stop command is sent to the converter The read convert RC bit instructs the converter to wait until the conversion data is read before performing the next conversion or set of conversions 2 2 8 3 Power Consumption Control Bits The CS5522 24 28 devices accommodate four power consumption modes normal low power standby and sleep The CS5521 23 accommodate three power consumption modes normal standby and sleep The normal default mode is entered af ter a power on reset In normal mode the DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 CS5522 24 28 typically consume 9 0mW The C55521 23 typically consume 6 0 mW The low power mode is an alternate mode in the CS5522 24 28 that reduces the consumed power to 5 5 mW It is entered by setting bit D8 the low power mode bit in the configuration register to logic 1 Slightly degraded noise or linearity perfor mance should be expected in the low power mode Note that the XIN clock should not exceed 130 kHz in low power mode The final two modes accom modated in all devices are referred
64. n cycle and simultaneously reject both 50 Hz and 60 Hz interference when operated at word rates below 30 Sps assuming a XIN clock frequency of 32 768 kHz To ease communication between the ADCs and a micro controller the converters include an easy to use three wire serial interface which is SPITM and Microwire compatible 2 1 Analog Input Figure 4 illustrates a block diagram of the analog in put signal path inside the CS5521 22 23 24 28 The front end consists of a multiplexer break before make configuration a chopper stabilized instru mentation amplifier with fixed gain of 20X coarse fine charge buffers and a programmable gain section For the 25 mV 55 mV and 100 mV input ranges the input signals are amplified by the 20X in strumentation amplifier For the 1 V 2 5 V and 5 V input ranges the instrumentation amplifier is by passed and the input signals are connected to the Programmable Gain block via coarse fine charge buffers VREF VREF NBV also supplies the negative supply voltage for the coarse fine change buffers Figure 4 Multiplexer Configurations DS317F4 13 l CIRRUS LOGIC CS5521 22 23 24 28 2 1 1 Instrumentation Amplifier The instrumentation amplifier is chopper stabilized and is activated anv time conversions are performed with the low level input ranges lt 100 mV The am plifier is powered from VA and from the NBV Negative Bias
65. n this conversion mode the ADC will repeatedly perform conversions referencing only one Setup The 8 bit command word contains the CSRP bits which instruct the converter which Setup to use when performing the conversion Note that in this mode every conversion word must be read The part will wait for the current conversion word to be read before performing the next conversion To perform repeated one Setup conversions with wait the MC bit must be set to 0 the LP bit must be set to 1 and the RC bit must be set to 1 in the Configuration Register Then the 8 bit command word that references the desired Setup must be sent to the converter The ADC will then begin per forming conversions on the referenced Setup and SDO will fall to indicate when a conversion is com plete and data is available Thirty two SCLKs are then needed to read the conversion word from the data register The first 8 SCLKs are used to clear the SDO flag During the last 24 SCLKs the data word will be output from the converter on the SDO line If during the first 8 SCLKs 00000000 is provided on SDI the converter will remain in this conversion mode and continue to perform conver sions on the selected Setup after each data word is read To exit this conversion mode 1111 1111 must be provided on SDI during the first 8 SCLKs If the user decides to exit 24 more SCLKs are re 36 quired to read the final conversion word from the data register and re
66. ndicator CI bits keep track of which physical channel was convert ed and the overrange flag OF and the oscillation detect OD bits monitor conversions to determine if a valid conversion was performed Refer to the Conversion Data FIFO Descriptions section for more details The CS5521 22 23 24 28 output data conversions in binary format when operating in unipolar mode and in two s complement when operating in bipolar mode Refer to the Conversion Data FIFO De scriptions section for more details CS5522 24 28 24 Bit Output Coding Unipolar Input Offset Bipolar Input Two s Unipolar Input Offset Bipolar Input Two s Voltage Binary Voltage Complement Voltage Binary Voltage Complement gt VFS 1 5 LSB FFFF gt VFS 1 5 LSB 7FFF gt VFS 1 5 LSB FFFFFF gt VFS 1 5 LSB 7FFFFF VFS 1 5 LSB FFFF 7FFF VFS 1 5LSB FFFFFF 7FFFFF SE VFS 1 5 LSB VFS 1 5 LSB Gen FFFE 7FFE FFFFFE 7FFFFE VFS 2 0 5 LSB 8000 0000 VFS 2 0 5 LSB 800000 000000 0 5 LSB 0 5 LSB 7FFF FFFF 7FFFFF FFFFFF 40 5 LSB 0001 8001 40 5 LSB 000001 800001 VFS 0 5 LSB VFS 0 5 LSB 0000 8000 000000 800000 lt 0 5 LSB 0000 lt VFS 0 5 LSB 8000 lt 0 5 LSB 000000 lt VFS 0 5 LSB 800000 Note VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges or the voltage between full scale for an
67. nversions using different conversion options on each of the input channels The ADCs also include multiple channel conver sion capabilitv User bits in the configuration regis ter of the ADCs can be configured to sequence through the 12 bit command Setups performing a conversion according to the content of each 12 bit Setup This channel scanning capabilitv can be configured to run continuously or to scan through a specified number of Setup Registers and stop un til commanded to continue In the multiple channel scanning modes the conversion data words are loaded into an on chip data FIFO The converter is sues a flag on the SDO pin when a scan cycle is completed so the user can read the FIFO More de tails are given in the following pages Instructions are provided on how to initialize the converter perform offset and gain calibrations and to configure the converter for the various conver sion modes Each of the bits of the configuration register and of the Channel Setup Registers is de scribed A list of examples follows the description section Table 2 can be used to decode all valid commands the first 8 bits into the serial port 4 24 4 24 AIN1 Off 1 Gain 1 AIN2 Off 2 Gain 2 AINS Off 3 Gain 3 AIN4 Off 4 Gain 4 1x24 Configuration 4 12x2 Sach eg PORTS DATA Setup 5 Setup 6 1 Setup
68. o 20 after self calibration of gain Therefore a system gain calibration is required to get better ac curacy except for the 2 5 V range 2 3 2 System Calibration For the system calibration functions the user must supply the calibration signals to the converter which represent ground and full scale When a system offset calibration is performed a ground referenced signal must be applied to the converters See Figures 14 and 15 As shown in Figures 16 and 17 the user must input a signal representing the positive full scale point to OPEN AIN ve S eo v S3 CLOSED AIN C S2 OPEN v VREF a s4 kI CLOSED Figure 12 Self Calibration of Offset High Ranges External Connections Figure 14 System Calibration of Offset Low Ranges DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 perform a svstem gain calibration In either case the calibration signals must be within the specified calibration limits for each specific calibration step refer to the Svstem Calibration Specifications in ANALOG CHARACTERISTICS If a system gain calibration is performed the following conditions must be met External gt Connections b oe AIN Figure 15 System Calibration of Offset High Ranges External KS Connections kul AIN Full Scale Figure 16 System Calibration of Gain Low Ranges External
69. o the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1 s density The nominal full scale input span of the modulator from 30 per cent to 70 percent 1 s density is determined by the VREF voltage divided by the Gain Factor See Table 1 to determine if the CS5521 22 23 24 28 is being used properly For example in the 55 mV range to determine the nominal input voltage to the modulator divide VREF 2 5 V by the Gain Fac tor 2 2727 When a smaller voltage reference is used the re sulting code widths are smaller causing the con verter output codes to exhibit more changing codes for a fixed amount of noise Table 1 is based upon a VREF 2 5 V For other values of VREF the values in Table 1 must be scaled accordingly 2 1 4 Measuring Voltages Higher than 5 V Some systems require the measurement of voltages greater than 5 V The input current of the instru i i nali 1 Input Range Max mr VREF Gain Factor Ee cd 25 mV 28 va 2 5V 5 05V 075V 55 mV 28 ve 2 5V 2 272727 1 1V 1 65 V 100 mV 28 ve 2 5V 1 25 20 V 3 0 V 1 0 V 2 5V 2 5 1 0 V t1 5V 2 5V 2 5V 1 0 2 5V 50 V 50 V 2 5V 0 5 5 0V OV VA Table 1 Relationship between Full Scale Input Gain Factors and Internal Analog Signal Limitations Note 1 The converter s actual input range the delta sigma s nominal full scale input and the delta sigma s maximum full scale
70. og inputs are expected to be ground referenced therefore NBV must be between 1 8 to 2 5 to ensure proper operation CPD Charge Pump Drive Square wave output used to provide energy for the charge pump 3 4 Power Supply Connections VA Positive Analog Power Positive analog supply voltage Nominally 45 V VD Positive Digital Power Positive digital supply voltage Nominally 43 0 V or 5 V AGND Analog Ground Analog Ground DGND Digital Ground Digital Ground 50 DS317F4 ii EE emm CIRRUS LOGIC CS5521 22 23 24 28 4 SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A D Converter transfer function One endpoint is located 1 2 LSB below the first code transition and the other endpoint is located 1 2 LSB bevond the code transition to all ones Units in percent of full scale Differential Nonlinearitv The deviation of a code s width from the ideal width Units in LSBs Full Scale Error The deviation of the last code transition from the ideal VREF VREF 3 2 LSB Units are in LSBs Unipolar Offset The deviation of the first code transition from the ideal 1 2 LSB above the voltage on the AIN pin When in unipolar mode U B bit 1 Units are in LSBs Bipolar Offset The deviation of the mid scale transition 111 111 to 000 000 from the ideal 1 2 LSB below the voltage on the AIN
71. olar mode or when the input is more negative than the negative full scale bipolar mode CI Channel Indicator Bits 1 0 These bits indicate which physical input channel was converted 00 Physical Channel 1 CS5521 23 only 01 Physical Channel 2 CS5521 23 only 10 Physical Channel 3 CS5523 only 11 Physical Channel 4 CS5523 only DS317F4 41 2 6 Digital Filter The CS5521 22 23 24 28 have eight different lin ear phase digital filters which set the output word rates OWRs shown in Table 3 These rates as sume that XIN is 32 768 kHz Each of the filters has a magnitude response similar to that shown in Figure 18 The filters are optimized to settle to full accuracy every conversion and yield better than 80 dB rejection for both 50 and 60 Hz with output word rates at or below 15 0 Sps The converter s digital filters scale with XIN For example with an output word rate of 15 Sps the fil ter s corner frequency is typically 12 7 Hz using a 32 768 kHz clock If XIN is increased to 65 536 kHz the OWR doubles and the filter s cor ner frequencv moves to 25 4 Hz 2 7 Clock Generator The CS5521 22 23 24 28 include a gate which can be connected with an external crystal to provide the master clock for the chip The chips are designed to operate using a low cost 32 768 kHz tuning fork type crystal One lead of the crystal should be con nected to XIN and the other to XOUT Lead lengths should be minimized to reduce str
72. onally SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto isolator LED SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA LSB en ji EN Command Time Data Time 24 SCLKs 8 SCLKs Write Cycle CS SCLK SDI d Command Time 8 SCLKs SDO MSBI LSB 4 4 b Data Time 24 SCLKs Read Cvcle SCLK u SD 4 gt Ze XIN OWR Command Time Z d 8 SCLKs la 7 Clock Cycles SDO A 8 SCLKs Clear SDO Flag Ip g s L G d td XIN OWR clock cycles for each conversion except the Data Time first conversion which will take XIN OWR 7 clock cycles 24 SCLKs Figure 10 Command and Data Word Timing DS317F4 25 l CIRRUS LOGIC CS5521 22 23 24 28 2 2 6 Reading Writing the Offset Gain and Configuration Registers The CS5521 22 23 24 28 s offset gain and config uration registers are accessed individually and can be read from or written to To write to an offset a gain or the configuration register the user must transmit the appropriate write command which ac cesses the particular register and then follow that command with 24 bits of data refer to Figure 10 for details For example to write 0x800000 hexadeci mal to phvsical channel one s gain register the user would transmit the command byte 0x02 hexadeci mal and then follow that command byte with the data 0x800000 hexadecimal Similarly to read physical channe
73. or all ranges and output rates 16 Forinput ranges 100 mV and output rates 260 Sps 16 384 kHz chopping frequency is used TYPICAL NOISE FREE RESOLUTION BITS CS5522 24 28 Note 17 Output Rate l 3 dB Filter Input Range Bipolar Mode Sps Frequencv 25 mV 55 mV 100 mV 1V 2 5V 5V 1 88 1 64 16 17 18 18 18 18 3 76 3 27 16 17 17 17 18 18 7 51 6 55 15 16 17 17 17 17 15 0 12 7 30 0 25 4 14 61 6 Note 16 50 4 12 12 12 12 12 12 84 5 Note 16 70 7 10 10 10 10 10 10 101 1 Note 16 84 6 8 8 8 8 8 8 Notes 17 For bipolar mode the number of bits of Noise Free Resolution is LOG 2XInput Range 6 6xRMS Noise LOG 2 rounded to the nearest bit For unipolar mode the number of bits of Noise Free Resolution is LOG Input Range 6 6xRMS Noise LOG 2 rounded to the nearest bit Also the CS5522 24 28 s output conversions are 24 bits Noise free Resolution numbers are based upon VREF 2 5 V and XIN 32 768 kHz The values will be affected directly by changes in VREF but the effects due to changes in the XIN frequency will be minor DS317F4 5 V DIGITAL CHARACTERISTICS T 25 C VA VD 5 V 5 GND 0 See Notes 2 and 18 CS5521 22 23 24 28 Parameter Svmbol Min Tvp Max Unit High level Input Voltage All Pins Except XIN and SCLK Vin 0 6 VD V XIN VD 0 5 V SCLK VD 0 45
74. p that was referenced until all of the data has been read from the part The data word from Setup1 is output first followed by the data word from Setup2 and so on for the appropriate number of Setups The part returns to command mode im mediately after the final data word has been read and waits for the next command to be issued DS317F4 l CIRRUS LOGIC CS5521 22 23 24 28 2 4 1 5 Repeated Multiple Setup Conversions without Wait LP 1MC 1RC 0 In this conversion mode the ADC will repeatedly perform conversions referencing multiple Setups The CSRP bits in the command word are ignored in this mode Instead the Depth Pointer DP3 DPO bits in the Configuration Register are accessed to determine the number of Setups to reference when collecting the data The number of Setups refer enced will be equal to DP3 DPO 1 and will be accessed in order beginning with Setup1 Note that in this mode the part will continually perform con versions looping back to Setupl when finished with each set and the user need not read every con version set as it becomes available The SDO line rises and falls to indicate the availability of new conversion data sets When new data is available the current conversion data set will be lost or in the case that the user has only read a part of the conver sion set the remainder of the conversion set will be corrupted To perform repeated multiple Setup conversions with no wait
75. pin When in bipolar mode U B bit 0 Units are in LSBs DS317F4 51 5 ORDERING INFORMATION CS5521 22 23 24 28 Model Number Package Bits Channels Linearity Error Max Temperature Range CS5521 AS 20 pin 0 2 Plastic SSOP 16 0 003 CS5521 ASZ 20 pin 0 2 Plastic SSOP Lead Free CS5522 AP 20 pin 0 3 Plastic DIP 2 CS5522 AS 20 pin 0 2 Plastic SSOP 24 0 0015 CS5522 ASZ 20 pin 0 2 Plastic SSOP Lead Free CS5523 AS 24 pin 0 2 Plastic SSOP 16 0 003 40 C to 85 C CS5523 ASZ 24 pin 0 2 Plastic SSOP Lead Free CS5524 AP 24 pin 0 3 Plastic DIP 4 CS5524 AS 24 pin 0 2 Plastic SSOP CS5524 ASZ 24 pin 0 2 Plastic SSOP Lead Free 24 30 001596 CS5528 AS 24 pin 0 2 Plastic SSOP B CS5528 ASZ 24 pin 0 2 Plastic SSOP Lead Free 6 ENVIRONMENTAL MANUFACTURING amp HANDLING INFORMATION Model Number Package MSL Rating Peak Reflow Temp Max Floor Life CS5521 AS 20 pin 0 2 Plastic SSOP 2 240 C 365 Days CS5521 ASZ 20 pin 0 2 Plastic SSOP Lead Free 3 260 C 7 Days CS5522 AP 20 pin 0 3 Plastic DIP 1 260 C No Limit CS5522 AS 20 pin 0 2 Plastic SSOP 2 240 C 365 Days CS5522 ASZ 20 pin 0 2 Plastic SSOP Lead Free 3 260 C 7 Days CS5523 AS 24 pin 0 2 Plastic SSOP 2 240 C 365 Days CS5523 ASZ 24 pin 0 2 Plastic SSOP Lead Free 3 260 C 7 Days CS5524 AP 24 pin 0 3 Plastic DIP 1 260 C No Limit CS5524 AS 24 pi
76. rd rate of 15 0 Sps 2 2 7 4 Gain Bits The gain bits G2 G0 of the channel setup regis ters set the full scale differential input range for the ADC when a conversion is performed with a partic ular Setup The input ranges in the table assume a 2 5 V reference voltage and scale linearly when using other reference voltages 2 2 7 5 Unipolar Bipolar Bit The unipolar bipolar bit is used to determine the type of conversion unipolar or bipolar that will be performed with a particular Setup 28 CS5521 22 23 24 28 2 2 8 Configuration Register The configuration register is 24 bits long The fol lowing subsections detail the bits in the configura tion register Table 4 summarizes the configuration register 2 2 8 1 Chop Frequency Select The chop frequency select CFS1 CFS0 bits are used to set the rate at which the instrumentation amplifier s chop switches modulate the input sig nal The 256 Hz rate is desirable as it provides the lowest input CVF sampling current 300 pA over 40 to 85 C The higher rates can be used to eliminate modulation aliasing effects as the fre quency of the input signal increases 2 2 8 2 Conversion Calibration Control Bits The conversion calibration control bits in the con figuration register are used to control the particular type of conversion required for the users applica tions In short the depth pointer DP3 DPO bits determine the number of Setups that will be refer enced whe
77. rises and falls to indicate the availabilitv of new conversion data When new data is available the current conversion data will be lost or in the case that the user has onlv read a part of the conversion word the remainder of the conversion word will be corrupted To perform repeated one Setup conversions with no wait the MC bit must be set to O the LP bit must be set to 1 and the RC bit must be set to O in the Configuration Register Then the 8 bit com mand word that references the desired Setup must be sent to the converter The ADC will then begin performing conversions on the referenced Setup and SDO will fall to indicate when a conversion is complete and data is available Thirtv two SCLKs are then needed to read the conversion word from the data register The first 8 SCLKs are used to clear the SDO flag During the last 24 SCLKs the data word will be output from the converter on the 35 l CIRRUS LOGIC CS5521 22 23 24 28 SDO line If during the first 8 SCLKs 00000000 is provided on SDI the converter will remain in this conversion mode and continue to perform conversions on the selected Setup To exit this conversion mode 11111111 must be provid ed on SDI during the first 8 SCLKs If the user de cides to exit 24 more SCLKs are required to read the final conversion word from the data register and return to command mode 2 4 1 3 Repeated One Setup Conversions with Wait LP 1MC 0RC 1 I
78. s designed to measure full scale ranges of 25 mV 55 mV 100 mV 1 V 2 5 V and 5 V Other full scale values can be ac commodated by performing a system calibration within the limits specified See the Calibration sec tion for more details Another way to change the full scale range is to increase or to decrease the voltage reference to a voltage other than 2 5 See the Voltage Reference section for more details Three factors set the operating limits for the input span They include instrumentation amplifier satu ration modulator 1 s density and a lower reference voltage When the 25 mV 55 mV or 100 mV range is selected the input signal including the common mode voltage and the amplifier offset voltage must not cause the 20X amplifier to satu rate in either its input stage or output stage To pre vent saturation the absolute voltages on AIN and AIN must stay within the limits specified refer to the Analog Input section Additionally the differ ential output voltage of the amplifier must not ex ceed 2 8 V The equation ABS VIN VOS x 20 2 8 V defines the differential output limit where VIN AIN AIN is the differential input voltage and VOS is the ab solute maximum offset voltage for the instrumenta tion amplifier VOS will not exceed 40 mV If the differential output voltage from the amplifier ex ceeds 2 8 V the amplifier may saturate which will cause a measurement error The input voltage int
79. se 36 2 4 1 5 Repeated Multiple Setup Conversions without Wait 37 2 4 1 6 Repeated Multiple Setup Conversions with Wait 37 2 4 2 Calibration Protocol nn nenne nnn enn snnt 38 2 4 3 Example of Using the CSRs to Perform Conversions and Calibrations 38 2 5 Conversion Output Coding LL nn Han a nnn enn nnne ns 40 2 5 1 Conversion Data FIFO Descriptions sse 41 PEONBIEIRUI TEE 42 Klee TEE 42 2 8 Power Supply Arrangements eee nn nnnnnnn nanna nn renn nknnn artna nn ntnnnnnnnnanznnnzztzznn 43 2 8 1 Charge Pump Drive Circuits L sss 45 2 9 Digital Gain Scaling esseesiieeseseseeeeeene aaaea aaea ai annt ennt 45 2 10 Getting Started EE 46 adii 47 3 PIN DESCRIPTIONS CERE 48 3 1 Clock Generator ER 49 3 2 Control Pins and Serial Data I O Lara 49 3 3 Measurement and Reference Inputs L nnnnn nr nnnnn rna artna 49 3 4 Power Supply Connections L nanna nsa nanna nre e nnns ann nanna 50 4 SPECIFICATION DEFINITIONS rnnvvrnrnavennnnvvnnnsvnennnnnnnnnnvnnnnnnnnnnnnennnnnnnnnvennnnnnnnnnnvnnnnnnnnnnnennnnn 51 5 ORDERING INFORMATION eic l inden e EEN 52 6 ENVIRONMENTAL MANUFACTURING amp HANDLING INFORMATION 52 7 PACKAGE DIMENSION DRAWINGS nnmssmenenvvnnnnnvnnnnvvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnennnnvnnnnnr 53 DS317F4 3
80. set Drift Notes 3 and 4 20 20 NV C Bipolar Gain Error 8 31 8 31 ppm Unipolar Gain Error 16 62 16 62 ppm Gain Drift Note 4 1 3 1 3 ppm C Power Supplies Power Supply Currents Normal Mode lA 1 0 1 4 1 5 1 9 mA Note 5 Ip 90 135 90 135 uA INBv 400 570 525 700 uA Power Consumption Note 6 Normal Mode 6 0 8 9 9 12 mW Low Power Mode N A N A N A 5 5 7 5 mW Standbv 1 2 1 2 mW Sleep 500 500 uw Power Supply Rejection Positive Supplies 120 120 dB dc NBV 110 110 dB Notes 1 Applies after system calibration at any temperature within 40 C 4857 C 2 Specifications guaranteed by design characterization and or test 3 Specification applies to the device only and does not include any effects by external parasitic thermocouples LSBy N is 16 for the CS5521 23 and N is 24 for the CS5522 24 28 4 Drift over specified temperature range after calibration at power up at 25 C Measured with Charge Pump Drive off All outputs unloaded All input CMOS levels and the CS5521 23 do not have a low power mode DS317F4 5 Lem iex CS5521 22 23 24 28 ANALOG CHARACTERISTICS Continued Parameter Min Typ Max Unit Analog Input Common Mode Signal on AIN or AIN Bipolar Unipolar Mode NBV 1 8 to 2 5 V Range 25 mV 55 mV or 100 mV 0 150 0 950 V Range 1V 2 5V or5V NB
81. t range setting the gain register can be changed from 1 000 to 2 000 shift the entire regis ter contents to the left one position to achieve an input span of 12 5 mV Under this condition the full span of the converter codes will appear across a 12 5 mV span The amount of noise in the con e LI 2N5087 or similar 34 8K0 2 0KQ 10uF NBV l 7 L10uF 4 cu up o BAT85 FT A NBV 7 7 30 19 BAT85 2 1KQ 5V 5V Figure 25 Alternate NBV Circuits 45 l CIRRUS LOGIC CS5521 22 23 24 28 verter stavs constant but the number of codes af fected is doubled because the code size has been reduced by half The converter input ranges are specified with a voltage reference of 2 5 V The device can be op erated with the reference tied directly to the 5 V supply When this is done the input span of the in put ranges is doubled the 25 mV range actually be comes a 50 mV range The gain register can be set to 2 0 shift contents left one bit and the input range will be scaled back to 25 mV Since the gain register can actually be as great as 4 27 decimal one could scale the input span on the 25 mV range to accept an analog full scale span of about 6 25 mV This is useful for ratiometric bridge mea surement of low level differential outputs The gain register can also be scaled manually to a value lower than 1 0 It is not recommended to use the devices with the gain register scaled lower t
82. t the converter which Setup to use when performing the conversion To perform a single one Setup conversion the MC and LP bits in the Configuration Register must be set to 0 Then the 8 bit command word that refer ences the desired Setup must be sent to the convert er The ADC will then perform a single conversion on the referenced Setup and SDO will fall to indi cate that the conversion is complete Thirty two DS317F4 SCLKs are then needed to read the conversion word from the data register The first 8 SCLKs are used to clear the SDO flag During the last 24 SCLKs the data word will be output from the con verter on the SDO line The part returns to com mand mode immediately after the data word has been read where it waits for the next command to be issued 2 4 1 2 Repeated One Setup Conversions with out Wait LP 1MC ORC 0 In this conversion mode the ADC will repeatedly perform conversions referencing onlv one Setup The 8 bit command word contains the CSRP bits Which instruct the converter which Setup to use when performing the conversion Note that in this mode the part will continuallv perform conver sions and the user need not read everv conversion as it becomes available Although conversions can be read whenever thev are needed thev must be read within one conversion cvcle defined bv the referenced Setup as the data word will be over written when new conversion data becomes avail able The SDO line
83. the MC bit must be set to 1 the LP bit must be set to 1 and the RC bit must be set to 0 in the Configuration Register Then the 8 bit command word to start a conversion must be sent to the converter Because the CSRP bits of the command word are ignored in this mode a start convert command referencing any of the available Setups will begin the conversions The ADC will then perform conversions using the appropriate number of Setups as dictated by the DP bits in the Configuration Register beginning with Setupl The SDO line will fall after the final conversion to indicate that the data is ready Eight SCLKs plus 24 SCLKs for each Setup referenced are required to read the conversion words from the data FIFO The first 8 SCLKs are used to clear the SDO flag Ev ery 24 bits thereafter consist of the data words of each Setup that was referenced until all of the data DS317F4 has been read from the part If during the first 8 SCLKs 00000000 is provided on SDI the con verter will remain in this conversion mode and continue to perform conversions on the desired number of Setups To exit this conversion mode 1111 1111 must be provided on SDI during the first 8 SCLKs If the user decides to exit 24 more SCLKs for each referenced Setup are required to read the final conversion data set from the FIFO and return to command mode 2 4 1 6 Repeated Multiple Setup Conversions with Wait LP 1MC 1RC 1 In this conversion mode
84. ts Cirrus owns the copyrights associated with the information contained herein and gives consent for copie to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not exten to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPER TY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED FOR USE If AIRCRAFT SYSTEMS MILITARY APPLICATIONS PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BI FULLY AT THE CUSTOMER S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IMPLIEI WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS CUSTOM ER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIBUTORS AND OTHER AGENTS FROM AN AND ALL LIABILITY INCLUDING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARI
85. turn to command mode 2 4 1 4 Single Multiple Setup Conversions LP 0MC 1RC X In this conversion mode the ADC will perform sin gle conversions referencing multiple Setups and return to command mode after the data for all con versions have been read The CSRP bits in the command word are ignored in this mode Instead the Depth Pointer DP3 DPO bits in the Configu ration Register are accessed to determine the num ber of Setups to reference when collecting the data The number of Setups referenced will be equal to DP3 DPO 1 and will be accessed in order be ginning with Setup1 To perform single multiple Setup conversions the MC bit must be set to 1 and the LP bit must be set to O in the Configuration Register Then the 8 bit command word to start a conversion must be sent to the converter Because the CSRP bits of the command word are ignored in this mode a start convert command referencing any of the available Setups will begin the conversions The ADC will then perform conversions using the appropriate number of Setups as dictated by the DP bits in the Configuration Register beginning with Setupl The SDO line will fall after the final conversion to indicate that the data is ready Eight SCLKs plus 24 SCLKs for each Setup referenced are required to read the conversion words from the data FIFO The first 8 SCLKs are used to clear the SDO flag Ev ery 24 bits thereafter consist of the data words of each Setu
86. up registers CSRs because the depth information contained in the configuration regis ter defines how many of the CSRs to use 2 The CSRs need to be written regardless of single conversion or multiple single conversion mode 3 When single Setup conversions MC 0 are de sired the channel address is embedded in the command byte In the multiple Setup conversion mode MC 1 channels are selected in a pre programmed order based on information con tained in the CSRs and the depth bits DP3 DPO 39 CIRRUS LOGIC CS5521 22 23 24 28 of the configuration register 4 Once the CSRs are programmed repeated conver sions on up to 16 Setups can be performed by is suing only one command byte 5 The single conversion mode also requires only one command but whenever another or a different single conversion is wanted this command or a modified version of it has to be issued again 6 The NULL command is used to keep the serial port in command mode once it is in command mode 2 5 Conversion Output Coding The CS5521 22 23 24 28 devices output 16 bit CS5521 23 and 24 bit CS5522 24 28 data con version words To read a conversion word the user must read the conversion data FIFO The conver sion data FIFO is up to 192 bits long and outputs CS5521 23 16 Bit Output Coding the conversions MSB first The last byte of the con version data word CS5521 23 only contains data monitoring flags The channel i
87. ups are converted in the background while the data is being read the user must finish reading the conversion data FIFO be fore it is updated with new conversions To exit this conversion mode the user must provide 1111 1111 to SDI during the first 8 SCLKs If a byte of 1 s is provided the serial port returns to the command mode only after the conversion data FIFO is emptied in this case 10 conversions are performed Note that in this example physical channel 6 is converted five times Each conversion could be with the same or different filter rates de pending on the setting of Setups 1 3 5 7 and 9 Note that there is only one offset and one gain reg ister per physical channel Therefore any physical channel can only be calibrated for the gain range selected during calibration Specifying a different gain range in the Setup other than the range that was calibrated will result in a gain error Example 5 The configuration register has the following bits as shown DP3 DP0 XXXX MC X LP X RC X The command issued is 10101101 These settings instruct the converter to perform a system offset calibration of the 6th Setup which is physical channel 3 in this example During cali bration the serial port remains in the command mode Once the calibration is completed SDO falls To perform additional calibrations more commands have to be issued Notes 1 The configuration register must be written before channel set
88. voltag es the following equations allow the user to manu ally compute the calibration register s values based on two uncalibrated conversions see note The offset and gain calibration registers are used to ad just a typical conversion as follows Rc Ru Co Cg 2 Calibration can be performed using the following equations Co Rc0 G Ru0 Cg 2 G where G Rc1 RcO Ru1 RuO Note Uncalibrated conversions imply that the gain and off set registers are at default gain register 0x400000 Hex and offset register 0x000000 Hex J 33 CIRRUS LOGIC The variables are defined below VO First calibration voltage V1 Second calibration voltage greater than VO Ru Result of any uncalibrated conversion Ru0 Result of uncalibrated conversion VO 24 bit integer or 2 s complement Rul Result of uncalibrated conversion of V1 24 bit integer or 2 s complement Rc Result of any conversion RcO Desired calibrated result of converting VO 24 bit integer or 2 s complement Rel Desired calibrated result of converting V1 24 bit integer or 2 s complement Co Offset calibration register value 24 bit 2 s complement Cg Gain calibration register value 24 bit integer 2 3 3 Calibration Tips Calibration steps are performed at the output word rate selected by the WR2 WRO bits of the configu ration register Since higher word rates result in conversion words with more peak to pe
89. y of the bipolar gain ranges See text about error flags under overrange conditions Table 6 Output Coding for 16 bit CS5521 23 and 24 bit CS5522 24 28 40 DS317F4 CS5521 22 23 24 28 CIRRUS LOGIC 2 5 1 Conversion Data FIFO Descriptions CS5521 23 EACH 16 BIT CONVERSIONS D23 D22 D21 D20 D19 D18 Di7 D16 D15 D14 D13 D12 MSB 14 13 12 11 10 9 8 7 6 5 4 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 3 2 1 LSB 1 1 1 0 CH CIO OD OF CS5522 24 28 EACH 24 BIT CONVERSION LEVELS D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 MSB 22 21 20 19 18 17 16 15 14 13 12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO 11 10 9 8 7 6 5 4 3 2 1 LSB Conversion Data Bits 23 8 for CS5521 23 23 0 for CS5522 24 28 These bits depict the latest output conversion OD Oscillation detect Flag Bit 0 Bit is clear when oscillatory condition in modulator does not exist bit is read only 1 Bit is set any time an oscillatory condition is detected in the modulator This does not occur under normal operation conditions but may occur when the input is extremely overranged The OD flag will be cleared to logic 0 when the modulator becomes stable OF Over range Flag Bit 0 Bit is clear when over range condition has not occurred bit is read only 1 Bit is set when input signal is more positive than the positive full scale more negative than zero unip

CIRRUS LOGIC -CS5521/22/23/24/28 handbook

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