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ON SEMICONDUCTOR MC74HC244A handbook

1. Guaranteed Limit 55 to Symbol Parameter Test Conditions V 25 C lt 85 C lt 125 C lin Maximum Input Leakage Current Vin Voc or GND 6 0 0 1 1 0 1 0 loz Maximum Three State Leakage Output in High Impedance State 6 0 t 0 5 5 0 10 Vin Vip or Vin Vout Voc or GND loc Maximum Quiescent Supply Vin Voc or GND 6 0 4 0 40 160 uA Current per Package lout 0 uA NOTE Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book DL129 D AC ELECTRICAL CHARACTERISTICS C 50 pF Input t t 6 ns Guaranteed Limit Vcc 55 to Symbol Parameter V 25 C Maximum Propagation Delay to YA or B to YB 2 0 96 Figures 1 and 3 3 0 50 4 5 18 6 0 15 tpi z Maximum Propagation Delay Output Enable to YA or YB 2 0 110 tPuz Figures 2 and 4 3 0 60 4 5 22 6 0 19 Maximum Propagation Delay Output Enable to YA or 2 0 110 Figures 2 and 4 3 0 60 4 5 22 6 0 19 tri Hs Maximum Output Transition Time Any Output 2 0 60 Figures 1 and 3 3 0 23 4 5 12 6 0 10 Cin Maximum Input Capacitance 10 Cout Maximum Three State Output Capacitance 15 15 Output in High Impedance State NOTE For propagation delays with loads other than 50 pF and information on typical parametric values see Chapter 2 of the ON
2. YB2 YB3 4 Pins 18 16 14 12 9 7 5 3 Device outputs Depending upon the state of the output enable pins these outputs are either noninverting outputs or high impedance outputs http onsemi com 5 DATA INPUT AORB ENABLE A OR ENABLE B MC74HC244A LOGIC DETAIL TO THREE OTHER A OR B INVERTERS ONE OF 8 INVERTERS http onsemi com 6 MC74HC244A PACKAGE DIMENSIONS SEATING PLANE D 20 PL 10x 0 25 00 PDIP 20 N SUFFIX PLASTIC DIP PACKAGE CASE 738 03 ISSUE E NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSION B DOES NOT INCLUDE MOLD FLASH INCHES MILLIMETERS lt MIN MAX MIN MAX A 1 010 1 070 25 66 27 17 B 0 240 0 260 6 10 6 60 0 150 0 180 3 81 4 57 D 0 015 0 022 0 39 0 55 E 0 050BSC 1 27 BSC 0 050 0 070 1 27 1 77 G 0 100BSC 2 54 BSC J 0 008 0 015 0 21 0 38 K 0 110 0 140 2 80 3 55 L 0300BSC 7 62 BSC J 20PL M 0 159 0 159 N 0 020 0 040 0 51 1 01 0 25 0 010 T B 0 0 25 0 010 02 T 4 SOIC 20 DW SUFFIX CASE 751D 05 ISSUE G NOTES 0 1 DIMENSION
3. Semiconductor High Speed CMOS Data Book DL129 D Typical 25 C Vcc 5 0 V Cpp Power Dissipation Capacitance Per Buffer 34 Used to determine the no load dynamic power consumption Pp Cpp 2 Icc Vcc For load considerations see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book DL129 D http onsemi com 4 MC74HC244A SWITCHING WAVEFORMS tr ti Vcc DATA INPUT Vcc ENABLE AORB AORB GND GND HIGH OUTPUT Eo GUTES IMPEDANCE YA OR YB 10 9 10 VoL 90 OUTPUT Y HIGH IMPEDANCE Figure 1 Figure 2 TEST CIRCUITS TEST POINT TEST POINT CONNECT TO Vec WHEN OUTPUT OUTPUT TESTING tp z AND DEVICE DEVICE CONNECT TO GND WHEN UNDER UNDER TESTING tpyz AND tpzy TEST Ct Includes all probe and jig capacitance Figure 3 Test Circuit TEST Includes all probe and jig capacitance Figure 4 Test Circuit PIN DESCRIPTIONS INPUTS A1 A2 A3 A4 B1 B2 B3 B4 Pins 2 4 6 8 11 13 15 17 Data input pins Data on these pins appear in noninverted form on the corresponding Y outputs when the outputs are enabled CONTROLS Enable A Enable B Pins 1 19 Output enables active low When a low level is applied to these pins the outputs are enabled and the devices function as noninverting buffers When a high level is applied the outputs assume the high impedance state OUTPUTS 1 YA2 YA3 4 1
4. mW C from 65 to 125 C For high frequency or heavy load considerations see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book DL129 D RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Voc DC Supply Voltage Referenced to GND 2 0 6 0 Vin Vout DC Input Voltage Output Voltage Referenced to GND 0 Voc Ta Operating Temperature All Package Types 55 125 tr t Input Rise and Fall Time Voc 2 0 V 0 1000 Figure 1 Voc 4 5 V 0 500 Voc 6 0 V 0 400 DC ELECTRICAL CHARACTERISTICS Voltages Referenced to GND Guaranteed Limit 55 to Symbol Parameter Test Conditions V 25 C lt 85 C lt 125 C Minimum High Level Input Voltage Vout Vcc 0 1 V 2 0 1 5 1 5 V 20 uA 3 0 2 1 2 1 4 5 3 15 3 15 6 0 4 2 4 2 Maximum Low Level Input Voltage Vout 0 1 V 2 0 0 5 0 5 20 uA 3 0 0 9 0 9 4 5 1 35 1 35 6 0 1 8 1 8 VoH Minimum High Level Output Vin 2 0 1 9 1 9 Voltage 20 uA 4 5 4 4 4 4 6 0 5 9 5 9 Vin Vin 2 4 mA 3 0 2 48 2 34 6 0 mA 4 5 3 98 3 84 7 8 6 0 5 48 5 34 VoL Maximum Low Level Output Vin VIL 2 0 0 1 0 1 Voltage 20 pA 4 5 0 1 0 1 6 0 0 1 0 1 Vin Vit 2 4 3 0 0 26 0 33 6 0 mA 4 5 0 26 0 33 7 8 mA 6 0 0 26 0 33 http onsemi com 3 MC74HC244A DC ELECTRICAL CHARACTERISTICS Voltages Referenced to GND
5. 4A SUFFIX CASE 967 o WLYWWG 1UU UB gguuut A Assembly Location WL L Wafer Lot YY Y Year WW W Work Week G Pb Free Package Pb Free Package Note Microdot may be in either location ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet Publication Order Number MC74HC244A D MC74HC244A PIN ASSIGNMENT LOGIC DIAGRAM YA1 A2 YA2 A3 4 4 DATA NONINVERTING INPUTS OUTPUTS B1 YB1 B2 YB2 B3 YB3 B4 4 PIN 20 Vcc OUTPUT ENABLE A PIN 10 GND ENABLES 1 ENABLE Z high impedance ORDERING INFORMATION MC74HC244AN PDIP 20 18 Units Rail MC74HC244ANG SOIC 20 18 Units Rail Pb Free MC74HC244ADW SOIC 20 WIDE 38 Units Rail MC74HC244ADWG SOIC 20 WIDE 38 Units Rail Pb Free MC74HC244ADWR2 SOIC 20 WIDE 1000 Tape amp Reel MC74HC244ADWR2G SOIC 20 WIDE 1000 Tape amp Reel Pb Free MC74HC244AFG SOEIAJ 20 40 Units Rail Pb Free MC74HC244AFEL SOEIAJ 20 2000 Tape amp Reel MC74HC244AFELG SOEIAJ 20 2000 Tape amp Reel Pb Free TFor information on tape and reel specifications including part orientation and tape sizes please refer to our Tape and Reel Packaging Specifications Brochure BRD8011 D This package is inherently Pb Free http onsemi com 2 MC74HC244A MAXIMUM RATINGS Symbol Parameter Value This device contains pr
6. E LOWER RN RADIUS OR THE FOOT MINIMUM SPACE N BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0 46 0 018 i MILLIMETERS INCHES DIM MIN MAX MIN MAX Se A 205 0 081 Ai 005 020 0 002 0 008 b 035 050 0 014 0 020 p 0 13 0 005 O 0 10 0 004 c 018 027 0 07 0 011 D i235 12 80 0 486 0 504 E 510 545 0201 0215 e 1 27 BSC 0 050 BSC He 740 820 0 291 0 323 L 050 045 0 020 0 033 Le 110 150 0 043 0 059 M 0 10 091 10 01 070 090 0 028 0 035 z os1 0032 http onsemi com 9 MC74HC244A ON Semiconductor and Q are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters inclu
7. MC74HC244A Octal 3 State Noninverting Buffer Line Driver Line Receiver High Performance Silicon Gate CMOS The MC74HC2AAA is identical in pinout to 1 5244 The device inputs are compatible with standard CMOS outputs with pullup resistors they are compatible with LSTTL outputs This octal noninverting buffer line driver line receiver is designed to be used with 3 state memory address drivers clock drivers and other bus oriented systems The device has noninverting outputs and two active low output enables The HC244A is similar in function to the HC240A Features Output Drive Capability 15 LSTTL Loads Outputs Directly Interface to CMOS NMOS and TTL Operating Voltage Range 2 0 to 6 0 V Low Input Current 1 uA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7A Chip Complexity 136 FETs or 34 Equivalent Gates Pb Free Packages are Available additional information on our Pb Free strategy and soldering details please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual SOLDERRM D Semiconductor Components Industries LLC 2005 1 July 2005 Rev 10 ON Semiconductor http onsemi com MARKING DIAGRAMS MC74HC244AN AWLYYWWG SOIC 20 DW SUFFIX CASE 751D 74HC244A AWLYYWWG 20 SUFFIX CASE 738 55 20 DT SUFFIX 1 CASE 948 200nnnnnnnnpn 74HC24
8. S ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION 4 MAXIMUM MOLD PROTRUSION 0 15 PER SIDE a 5 DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE PROTRUSION SHALL 0 13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION MILLIMETERS A piM MN MAX lt Meke SEARES AT c http onsemi com 7 e Je milo lo z D a a MC74HC244A PACKAGE DIMENSIONS TSSOP 20 DT SUFFIX CASE 948 02 ISSUE B Fj 20x K REF TD MENSIONING AND TOLERANCING 1 0 15 0 006 T U 0 10 0 004 T 2 CONTROLLING DIMENSION MILLIMETER 8 DIMENSION A DOES NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0 15 0 006 PER SIDE 4 DIMENSION B DOES NOT INCLUDE NTERLEAD FLASH OR PROTRUSION NTERLEAD FLASH OR PROTRUSION SECTION N N SHALL NOT EXCEED 0 25 0 010 PER SIDE 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE 0 25 0 010 DAMBAR PROTRUSION SHALL BE 0 08 0 003 TOTAL IN EXCESS OF THE K LE LE LI LI LI LI NS DIMENSION AT MAXIMUM MATERIAL CONDITION M 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY zm 7 DIMEN
9. SION A AND B ARE TO BE DETERMINED AT DATUM PLANE W i 4 F MILLIMETERS INCHES MIN MAX MIN MAX 2e 6 40 6 60 0 252 0 260 DETAIL E B 430 450 0 169 0 177 c 120 007 Mo EN D 0 05 015 0 002 0 006 AAA pde ponam G 0 65 BSC 0 026 BSC tH eH HB tH HP tB EH td HH tS 027 037 0011 0 015 G J 009 020 0 004 0 008 D H 009 016 0 004 0 006 DETAIL E 019 030 0007 0 012 C 0 100 0 004 ki 019 025 0 007 0 010 T SEATING L 6 40 BSC 0 252 BSC _ PLANE m 0 8 0 8 http onsemi com 8 MC74HC244A PACKAGE DIMENSIONS SOEIAJ 20 F SUFFIX CASE 967 01 ISSUEO NOTES Le 1 DIMENSIONING AND TOLERANCING PER ANSI 14 5 1982 CONTROLLING DIMENSION MILLIMETER 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD M FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0 15 0 006 e PER SIDE L 4 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY 5 THE LEAD WIDTH DIMENSION b DOES NOT DETAIL P INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 0 003 TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON TH
10. ding Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT American Technical Support 800 282 9855 Toll Free ON Semiconductor Website http onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 61312 Phoenix Arizona 85082 1312 USA Order Litera
11. otection Voc DC Supply Voltage Referenced to GND 0 5 to 7 0 circuitry to guard against damage due to high static voltages or electric Vin DC Input Voltage Referenced to GND 0 5 to Vcc 0 5 fields However precautions must E be taken to avoid applications of any Vout DC Output Voltage Referenced to GND 0 5 to Vcc 0 5 voltage higher than maximum rated lin DC Input Current per Pin 20 voltages to this high impedance cir cuit For proper operation Vi and lout Dec per Pin 2 Vout should be constrained to the lcc DC Supply Current Voc and GND Pins t75 range GND x Vin or Vout Voc ea ae EE Unused inputs must always be Pp Power Dissipation in Still Air 750 tied to an appropriate logic voltage S ackaget 500 level e g either GND or Voc TSSOP Packaget 450 Unused outputs must be left open Tstg Storage Temperature 65 to 150 TL Lead Temperature 1 mm from Case for 10 Seconds Plastic DIP SOIC SSOP or TSSOP Package 260 Maximum ratings are those values beyond which device damage can occur Maximum ratings applied to the device are individual stress limit values not normal operating conditions and are not valid simultaneously If these limits are exceeded device functional operation is not implied damage may occur and reliability may be affected TDerating Plastic DIP 10 mW C from 65 to 125 C SOIC Package 7 mW C from 65 to 125 C TSSOP Package 6 1
12. ture http www onsemi com litorder Phone 480 829 7710 or 800 344 3860 Toll Free USA Canada Japan ON Semiconductor Japan Customer Focus Center MES Fax 480 829 7709 or 800 344 3867 Toll Free USA Canada 2 9 1 Kamimeguro Meguro ku Tokyo Japan 153 0051 For additional information please contact your Email orderlit onsemi com Phone 81 3 5773 3850 local Sales Representative MC74HC244A D

ON SEMICONDUCTOR MC74HC244A handbook

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