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STMICROELECTRONICS STD70N02L STD70N02L-1 Manual

1. 11 17 Package mechanical data STD70NO2L STD70NO2L 1 4 12 17 Package mechanical data In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a Lead free second level interconnect The category of second level interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com STD70NO2L STD70NO2L 1 Package mechanical data 251 IPAK MECHANICAL DATA DIM mm inch MIN TYP MAX MIN TYP MAX A 2 2 2 4 0 086 0 094 1 0 9 1 1 0 035 0 043 A3 0 7 1 3 0 027 0 051 B 0 64 0 9 0 025 0 031 B2 5 2 5 4 0 204 0 212 B3 0 85 0 033 B5 0 3 0 012 B6 0 95 0 037 0 45 0 6 0 017 0 023 C2 0 48 0 6 0 019 0 023 D 6 6 2 0 236 0 244 E 6 4 6 6 0 252 0 260 G 44 46 0 173 0 181 H 15 9 16 3 0 626 0 641 L 9 9 4 0 354 0 370 L1 0 8 1 2 0 031 0 047 L2 0 8 1 0 031 0 039 0068771 E 13 17 Package mechanical data STD70NO2L STD70NO2L 1 DPAK MECHANICAL DATA mm inch DIM MIN TYP MAX MIN TYP MAX
2. 20 40 60 80 Iso A Figure 12 Normalized Bypss vs temperature V BR bss norm 0 95 698750 Ves 0 p 250A 50 0 100 CC 7 17 Electrical characteristics STD70NO2L STD70NO2L 1 Figure 13 Allowable lay vs time in avalanche HV30840 lav jz29 C 7 6 5 4 3 19 0 0 0 0 his The previous curve gives the single pulse safe operating area for unclamped inductive loads under the following conditions 70 5 1 3 Bypss lay Eas AR tav Where lay is the allowable current in avalanche is the average power dissipation in avalanche single pulse tay is the time in avalanche 8 17 ky STD70NO2L STD70NO2L 1 Appendix A Figure 14 Synchronous buck converter SW D p 8 L 1 D G Vin a G A C Control IC 4 Vo 5 SW Ld e Appendix The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below The formulas give a good approximation for the sake of perf
3. THERMAL PAD c2 oe Ep Teh gt 0068772 14 17 STD70NO2L STD70NO2L 1 Package mechanical data 5 DPAK FOOTPRINT Package mechanical data All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA mm inch DIM MIN MAX MIN MAX A 330 12 992 i B 0 059 C 128 13 2 0 504 0 520 D 202 0 795 164 18 4 0 645 0 724 9 measured 1 968 224 0 881 BASE QTY BULK QTY 2500 2500 oat rS FEED DIRECTION 40 mm min Access hole FN at slot location 1 p AN Full radius n ope pum tape start Im TAPE MECHANICAL DATA mm inch DIM MIN MAX MIN MAX A0 6 8 7 0 267 0 275 BO 10 4 10 6 0 409 0 417 B1 12 1 0 476 D 125 1 6 0 059 0 063 By D1 1 5 0 059 1 65 1 85 0 065 0 073 F 74 76 0291 0 299 KO 2 55 2 75 0 100 0 108 PO 3 9 41 0 153 0 161 P1 7 9 81 0 311 0 319 P2 1 9 2 1 0 075 0 082 R 40 1 574 Ww 15 7 16 3 0 618 0 641
4. Center line of cavity R min Bending radius 15 17 Revision history STD70NO2L STD70NO2L 1 6 Revision history Table 9 Revision history Date Revision Changes 29 Aug 2005 1 First release 02 Dec 2005 2 Modified Appendix A 07 Apr 2006 3 New template 03 May 2006 4 New value in Table 3 new curve see Figure 13 16 17 r STD70NO2L STD70NO2L 1 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any m
5. STD70NO2L STD70NO2L 1 Electrical ratings Electrical ratings Table 1 Absolute maximum ratings Symbol Parameter Value Unit 7 Drain source voltage rating 30 V Vps Drain source voltage Vas 0 24 V Drain gate voltage Reg 20kQ 24 V Vas Gate source voltage 20 V Ip 2 Drain current continuous at 25 C 60 A Ip Drain current continuous at Tc 100 C 42 A Ip Drain current pulsed 240 A Total dissipation at Tc 25 C 60 Derating factor 0 4 W C Single pulse avalanche energy 280 mJ i sors 1 Guaranted when external Rg 4 7Q and Tf lt Tfmax 2 Value limited by wire bonding 3 Pulse width limited by safe operating area 4 Starting Tj 25 C Id 30A 15V Table 2 Thermal data Symbol Parameter Value Unit Rthj case Thermal resistance junction case Max 2 5 C W Rthj amb Thermal resistance junction amb Max 100 C W T Maximum lead temperature for soldering purpose 275 C 3 17 Electrical characteristics STD70NO2L STD70NO2L 1 2 Electrical characteristics Tcase 25 C unless otherwise specified Table 3 On off states Symbol Parameter Test conditions Min Typ Max Unit Drain source breakdown V BR DSS Veneer WN Ip 25mA Vas 0 24 Zero gate voltage drain Vps
6. 2 fe 0 2 468 2 4 68 2 4 1072 10 09 10 0 1075 1074 10735 1022 16 tP Figure Output characterisics Figure 4 Transfer characteristics GC98660 GC99670b Ves 10V io A 6v 160 160 5V WAA 120 120 4 80 80 3V 40 40 2V 2 0 4 8 12 16 0 2 4 6 8 Ves V Figure 5 Transconductance Figure 6 Static drain source on resistance GC98680 27440 945 15 P Ves 10V Ti2 85 C 250 18 6 8 175 C 12 6 6 6 6 4 6 2 0 4 8 12 16 1 0 20 40 60 80 6 17 STD70NO2L STD70NO2L 1 Electrical characteristics Figure 7 Gate charge vs gate source voltage Figure 8 Capacitance variations GC98700 GC98710 Ves V um f 1MHz Vos 0V 60 12 2000 9 1500 WSS 6 1000 Coss 3 500 Crss 0 6 12 18 24 Qg nC 0 4 8 12 16 Vps V Figure 9 Normalized gate threshold voltage Figure 10 Normalized resistance vs vs temperature temperature 6C98720 GC98730b Ros on on 2 Ves 10V lo 30 1 0 1 4 0 8 1 0 0 6 0 6 0 4 0 2 50 0 50 100 50 0 50 100 Figure 11 Source drain diode forward characteristics Vso V 0 8 0 4 GC98740 175 C
7. 57 STD70NO2L STD70NO2L 1 N channel 24V 0 00680 60A STripFET Power MOSFET General features Type Vpss Rps on Ip STD70NO2L 24V 0 0080 60A STD70NO2L 1 24V 0 0080 60A Description Rps on Qg industry s benchmark Conduction losses reduced Switching losses reduced Low threshold device DPAK IPAK This series of products utilizes the latest advanced design rules of ST s proprietary STripFET technology This is suitable for the most demanding DC DC converter application Internal schematic diagram where high efficiency is to be achieved Pm or 2 Applications m Switching application G 1 5 5 5 08440 Order codes Part number Marking Package Packaging STD70NO2L 1 D70NO2L IPAK Tube STD70NO2L D70NO2L DPAK Tape amp reel May 2006 Rev 4 1 17 www st com Contents STD70NO2L STD70NO2L 1 Contents 1 Electrical ratings 3 2 Electrical characteristics 4 2 1 Electrical characteristics curves 6 3 TGSLCUCUNS E ERRARE wand 11 4 Package mechanical data 12 5 Package mechanical data 15 6 Revision history 16 2 17 ky
8. 20V 1 DSS current Ves 0 Vps 20V Te 125 C 10 pA Gate body leakage 7 less current Vos _ 0 Ves 20V 100 nA Gate threshold voltage Vps Vas Ip 250A 1 1 8 R Static drain source _ Vas 10V Ip 30A 0 0068 0 008 DS on resistance 5V Ip 15A 0 090 0 014 Table 4 Dynamic Symbol Parameter Test conditions Min Typ Max Unit Forward 1 Vps 15V Ip 30A transconductance DS B ey Gs Input capacitance 1400 pF Cs Output capacitance Vps 16V f 1MHz Vag 0 400 pF Reverse transfer 55 F res capacitance P Total gate charge 10 Ip 60A 24 32 nC Qgs Gate source charge Veg 10V 5 nC Gate drain charge see Figure 15 3 4 nC f 1MHz Gate DC Bias 0 Reg Gate input resistance test signal level 20mV 0 5 1 5 3 Q open drain Output charge Vps 16V Veg 0V 9 4 nC 1 Pulsed pulse duration 300us duty cycle 1 5 2 Coss D Vin Coss Cga Cga see Appendix 4 17 STD70NO2L STD70NO2L 1 Electrical characteristics Table 5 Switching times Symbol Parameter Test conditions Typ Max Unit Turn on delay time 10 I5 30A 10 ns 7 Rise time Dp s i 130 ns Rg 4 7Q 10 t Turn off delay time 27 ns see Figure 17 Fall time 16 21 6 ns Table 6 Source drain diode Symbol Parameter
9. Test conditions Min Typ Max Unit Isp Source drain current 50 A Isom Source drain current pulsed 200 A Forward on voltage 30 Vgg 0 13 V trr Reverse recovery time Isp 60A di dt 100A us 36 ns Qr Reverse recovery charge Vpp 20V Tj 150 C 36 nC Reverse recovery current see Figure 20 2 A 1 Pulsed pulse duration 300us duty cycle 1 5 5 17 Electrical characteristics STD70NO2L STD70NO2L 1 2 1 Electrical characteristics curves Figure 1 Safe operating area Figure 2 Thermal impedance HV27420 280DPC ofA 52505 4 4 Te 25 C 2 Single E E pulse 0 42 SN 0 2 BRA 100us 0 1 y n LE 0 05 4 10ms 0 02 Zin 0 01 6 0 SINGLE PULSE
10. anner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST ST PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2006 STMicroel
11. ble 8 Power losses parameters Paramter Meaning d Duty cycle Qgsth Post threshold gate charge Third quadrant gate charge Pconduction On state losses Pswitching On off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate driver losses Paoss Output capacitance losses STD70NO2L STD70NO2L 1 Test circuits 3 Test circuits Figure 15 Switching times test circuit for resistive load Figure 16 Gate charge test circuit T E Ay R 2200 3 3 AF HF Von E Vp o v 20v Vguy 9 CONST 1000 2 pur Vas 25 iu m Re D U T zo v pr 2 7 G Pw T 40 m 5 05990 1 4 Figure 17 Test circuit for inductive load Figure 18 Unclamped inductive load test switching and diode recovery times circuit gt A 1 1 1 2 L hima queen _ 3 8 1000 2200 zs 250 D u M NM EE el 2 158 lp 3 3 T 5 Vi C L e Ri La Sco6010 5 05970 Figure 19 Unclamped inductive waveform Figure 20 Switching time waveform V BR DsS Vop 5 05980
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13. ormance comparison of how different pairs of devices affect the converter efficiency However a very important parameter the wotking temperature is not considered The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature The low side SW2 device requires Very low RDS on to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn on The Cgd Cgs ratio lower than Vth Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon The high side SW1 device requires Small Rg and Lg to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS on to reduce the conduction losses 9 17 STD70NO2L STD70NO2L 1 10 17 Table 7 Power losses High side switch SW1 Low side switch SW2 R 2 6 2 Pconduction DS on L Rps on el 1 9 Pswitching Vin Qgsthesw1 Qgacsw1y f Zero voltage switching recovery Not applicable Wa Qrresw2 ef Pdiode conduction Not applicable tyeadtime P gate Qg Qgsw1 Vgg f Qaisisw2 Vgg f Paoss Vin Qossisw1 f Vin Goss swa 2 2 Ta

STMICROELECTRONICS STD70N02L STD70N02L-1 Manual

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