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MICROCHIP PIC18F2455/2550/4455/4550 Data Sheet1

1. 4 RB3 is the alternate pi n for CCP2 multiplexing Table Pointer lt 21 gt PORTA i Data Latch inc dec logic 8 8 Le Data Memory PCLATU PCLATH 2 Kbytes Address Latch PCU PCH PCL TI Program Counter 4 2 Data Address lt 12 gt 31 Level Stack pore 5 evel Staci Address Latch 4 1 2 f 4 BSR FSR Access Program Memory STKPTR 0 Bank T 24 32 Kbytes FSR1 Data Latch he 12 inc dec Table Latch r PORTC ROM Latch Address Instruction Bus lt 16 gt Decode kl i IR _ 8 j Instruction State Machine 7 Decode amp B Control Signals Control PRODH PRODL PORTD 8 x 8 Multiply Von Vs KX gt 3 Internal Power up 2 p Oscillator SO BITOP W osci2 D lak Timer 5 osc2 DQ P TAG Oscillator lt gt Start up Timer T10SI Kh Oscillator 8 Power on Xx Oscillator Reset ALU lt 8 gt Watchdog 8 icpac X gt Single Supply Timer IcPGD De ci Bronnen PORTE In Circuit ICPO
2. FIGURE 12 2 TIMER1 BLOCK DIAGRAM 16 BITREAD WRITE MODE Timer1 Oscillator i 1 T1OSO T13CKI bx gt 1 Lose Prescaler Synchronize OSC D 0 internal 1 2 4 8 4 Detect 0 T1OSI X i SIROS S APRES es Sleep Input TIOSCEN TMRICS Timer1 T1CKPS1 T1CKPSO On Off TISYNC TMR1ON Y Set Clear TMRI P TMRIL High Byte gt TMRIIF CCP Special Event Trigger TX 8 on Overflow aN Read TMRIL Write TMRIL 48 8 TMR1H 8 N 5 lt Ta gt Internal Data Bus Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain DS39632B page 130 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 12 2 Timer1 16 Bit Read Write Mode Timer1 can be configured for 16 bit reads and writes see Figure 12 2 When the RD16 control bit TICON lt 7 gt is set the address for TMR1H is mapped to a buffer register for the high byte of Timer1 A read from TMRIL will load the contents of the high byte of Timer into the Timer1 high byte buffer This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the low byte has become invalid
3. des Control Signals PRODH PRODL PORTC g ESP Multiply RCO T10SO T13CKI 8 RC1 T10SI CCP26 UOE osc12 Internal Power up STOR W RC2 CCP1 a ra Timer 8 RC4 D VM osc2 bd gt Oscillator LS RCS D VP INTRG Start up Timer RC6 TX CK TIOSI X1 Oscillator Power on 8 8 k gt X RC7 RX DT SDO Reset 8 MHz ALU lt 8 gt T10SO X1 Oscillator Watchdog Timer 8 MCLAM X Single Supply PA Programming ee In Circuit al oate Von vss Xp Debugger Clock Monitor PORTE USB Voltage Band Gap ws Die Regulator Reference D MCLR VPP RE3 BOR Data i HLVD EEPROM Timer0 Timer1 Timer2 Timer3 Comparator CCP1 CCP2 MSSP EUSART Ano USB Note 1 RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled 2 OSC1 CLKI and OSC2 CLKO are only available in select oscillator modes and when these pins are not being used as digital I O Refer to Section 2 0 Oscillator Configurations for additional information 3 RB3 is the alternate pin for CCP2 multiplexing DS39632B page 10 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 1 2 PIC18F4455 4550 40 44 PIN BLOCK DIAGRAM Data Bus lt 8 gt
4. 00 Single Output PIA Modulated alej Delay Delay PIA Modulated lt gt Ben 10 Half Bridge P41B Modulated PIA Active Full Bridge P1B Inactive a 01 Forward I I P1C Inactive j P1D Modulated PIA Inactive i a Full Bridge P1B Modulated ___ Reverse P1C Active y I P1D Inactive FIGURE 16 3 PWM OUTPUT RELATIONSHIPS ACTIVE LOW STATE 0 Duty PR2 1 CCP1CON SIGNAL is i lt 7 6 gt y Period gt oo Single Output P1A Modulated PIA Modulated __ Z lt gt f Delay Delay 1 10 Half Bridge P1B Modulated gt i P1A Active Full Bridge P1B Inactive M I x 01 Forward P1C Inactive i P1D Modulated PIA Inactive I I i P1B Modulated ey Full Bridge h 1 Reverse i P1C Active P1D Inactive Relationships e Period 4 Tosc PR2 1 TMR2 Prescale Value Duty Cycle Tosc CCPR1L lt 7 0 gt CCP1CON lt 5 4 gt TMR2 Prescale Value Delay 4 Tosc ECCP1DEL lt 6 0 gt Note 1 Dead band delay is programmed using the ECCP1DEL register Section 16 4 6 Programmable Dead Band Delay 2004 Microchip Technology Inc Preliminary DS39632B page 153 PIC18F2455 2550 4455 4550 16 4 4 HAL
5. V Standard Half Bridge Circuit Push Pull NEJ PIC18FX455 X550 FET Driver va PIA gt y Load FET Driver le ae 4 ap Ta V Half Bridge Output Driving a Full Bridge Circuit x V PIC18FX455 X550 FET FET Driver Driver m gt PUN MI o FET Load FET Driver Driver D ae P1B gt le lt x D DS39632B page 154 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 16 4 5 FULL BRIDGE MODE In Full Bridge Output mode four pins are used as outputs however only two outputs are active at a time In the Forward mode pin PIA is continuously active and pin P1D is modulated In the Reverse mode pin P1C is continuously active and pin P1B is modulated These are illustrated in Figure 16 6 FIGURE 16 6 FULL BRIDGE PWM OUTPUT PIA P1B P1C and PID outputs are multiplexed with the PORTC lt 2 gt PORTD lt 5 gt PORTD lt 6 gt and PORTD lt 7 gt data latches The TRISC lt 2 gt TRISD lt 5 gt TRISD lt 6 gt and TRISD lt 7 gt bits must be cleared to make the P1A P1B P1C and P1D pins outputs Forward Mode Period 1 2 Output signal is shown as active high l gt P1A 2 Duty Cycle a I I I P1B I I I I I P1C 2 I I I I I I I I I I P1p 2 ao jz I
6. ered AT YN E kapak ut Py VATA es SE A TE V S P s Pe I eet ae ee eee ae DO CK1SPP 1 1 1 1 stan OTTA EO VY a A Swat States 2 Wai Sales 2 Wai States Z Wai Sates FIGURE 18 4 TIMING FOR USB WRITE ADDRESS AND READ DATA 4 WAIT STATES USB Clock PEE np na c A EUR o a A OESPP N CSSPP CK1SPP M CK2SPP SPP lt 7 0 gt Y X M A 2004 Microchip Technology Inc Preliminary DS39632B page 189 PIC18F2455 2550 4455 4550 18 2 Setup for USB Control When the SPP is configured for USB operation data can be clocked directly to and from the USB peripheral without intervention of the microcontroller thus no process time is reguired Data is clocked into or out from the SPP with endpoint address information first followed by one or more bytes of data as shown in Figure 18 5 This is ideal for applications that reguire isochronous large volume data movement The following steps are reguired to set up the SPP for USB control 1 Configure the SPP as desired including wait states and clocks 2 Setthe SPPOWN bit for USB ownership 3 Set the buffer descriptor starting address BDNADRL BDNADRH to FFFFh 4 Set the KEN bit BDnSTAT lt 5 gt so the buffer descriptor is kept indefinitely by the SIE 5 Set the INCDIS bit BDnSTAT lt 4 gt to disable automatic buffer address increment 6 Setthe SPPEN
7. 26 2 2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR Syntax ADDFSR f k Operands 0 lt k lt 63 fe 0 1 2 Operation FSR f k gt FSR f Status Affected None Encoding 1110 1000 ffkk kkkk Description The 6 bit literal K is added to the contents of the FSR specified by f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to literal k Data FSR Example ADDFSR 2 23h Before Instruction FSR2 After Instruction FSR2 03FFh 0422h ADDULNK Add Literal to FSR2 and Return Syntax ADDULNK k Operands 0 lt k lt 63 Operation FSR2 k gt FSR2 TOS gt PG Status Affected None Encoding 1110 1000 11kk kkkk Description The 6 bit literal k is added to the contents of FSR2 A RETURN is then executed by loading the PC with the TOS The instruction takes two cycles to execute a NOP is performed during the second cycle This may be thought of as a special case of the ADDFSR instruction where f 3 binary 11 it operates only on FSR2 Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to literal k Data FSR No No No No Operation Operation Operation Operation Example ADDULNK 23h Before Instruction FSR2 03FFh PC 0100h After Instruction FSR2 0422h PC TOS Note All PIC18 instructions may take an optional label argument preceding
8. Industrial Operating temperature 40 C lt TA lt 85 C for industrial pial Device Min Typ Max Units Conditions INTOSC Accuracy Freq 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz PIC18LF2455 2550 4455 4550 2 1 2 25 C VDD 2 7 3 3V 5 5 10 C to 85 C VDD 2 7 3 3V 10 1 10 40 C to 85 C VDD 2 7 3 3V PIC18F2455 2550 4455 4550 2 1 2 25 C VDD 4 5 5 5V 4 5 10 C to 85 C VDD 4 5 5 5V 10 1 10 40 C to 85 C VDD 4 5 5 5V INTRC Accuracy Freq 31 kHz PIC18LF2455 2550 4455 4550 26 562 35 938 kHz 40 C to 85 C VDD 2 7 3 3V PIC 18F2455 2550 4455 4550 26 562 35 938 kHz 40 C to 85 C VDD 4 5 5 5V Shading of rows is to assist in readability of the table Frequency calibrated at 25 C OSCTUNE register can be used to compensate for temperature drift INTRC frequency after calibration Change of INTRC frequency as VDD changes 2004 Microchip Technology Inc Preliminary DS39632B page 377 PIC18F2455 2550 4455 4550 FIGURE 28 6 CLKO AND I O TIMING lt sz I O pin K i i Output Old Value l New Value 20 21 Note Refer to Figure 28 4 for load conditions TABLE 28 11 CLKO AND I O TIMING REQUIREMENTS pe Symbol Characteristic Min Typ Max Units Condition
9. DECF Decrement f Syntax DECF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation f 1 gt dest Status Affected C DC N OV Z Encoding 0000 01da EEFE ffff Description Decrement register f If d is o the result is stored in W If is 1 the result is stored back in register f default If a is o the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity 01 Q2 03 Q4 Decode Read Process Write to register f Data destination Example DECF CNT 1 0 Before Instruction CNT Oth Z 0 After Instruction CNT 0h Z 1 DS39632B page 320 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 DECFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Decrement f Skip if 0 DECFSZ f d a 0 lt f lt 255 de 0 1 ae 0 1 f 1 gt dest skip if result 0 None 0010 lida ffff ffff The contents of register f are decremented If is
10. SUBLW Subtract W from Literal Syntax SUBLW k Operands 0 lt k lt 255 Operation k W gt W Status Affected N OV C DC Z Encoding 0000 1000 kkkk kkkk Description W is subtracted from the eight bit literal K The result is placed in W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example 1 SUBLW 02h Before Instruction W 01 C After Instruction w Oth C gt I result is positive Z 0 N 0 Example 2 SUBLW 02h Before Instruction W C After Instruction W 00h C wl result is zero Z 1 N 0 Example 3 SUBLW 02h Before Instruction W C After Instruction W FFh 2 s complement C 0 result is negative Z 0 N 1 SUBWF Subtract W from f Syntax SUBWF f d a Operands 0 lt f lt 255 d e 0 1 ae 0 1 Operation f W dest Status Affected N OV C DC Z Encoding 0101 11da F FEFE Description Subtract W from register f 2s complement method If d is o the result is stored in W If is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt
11. Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On Chip Program Memory 7FFFh 8 a 8000h 0p gt o g lt z wn 2 Read 0 1FFFFFh 200000h 2004 Microchip Technology Inc Preliminary DS39632B page 57 PIC18F2455 2550 4455 4550 9 1 1 PROGRAM COUNTER The Program Counter PC specifies the address of the instruction to fetch for execution The PC is 21 bits wide and is contained in three separate 8 bit registers The low byte known as the PCL register is both readable and writable The high byte or PCH register contains the PC lt 15 8 gt bits it is not directly readable or writable Updates to the PCH register are performed through the PCLATH register The upper byte is called PCU This register contains the PC lt 20 16 gt bits it is also not directly readable or writable Updates to the PCU register are performed through the PCLATU register The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL Similarly the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL This is useful for computed offsets to the PC see Section 5 1 4 1 Computed GOTO The PC addresses bytes in the program memory To prevent the PC from becoming misaligned with word instructions the Least Significant bit of PCL is
12. Q O GlOCkK spa on ha ee aba ea ave hh 147 152 R RAM See Data Memory RG UIDEE Modes n aQ SAL conan eas 41 RE RUNMOME sioni inu apunpa 37 R AL RAO AN an 331 RCON Register Bit Status During Initialization 50 Register File enren ia u mu m ay umuq u s Sau ss 65 Register File Summary a 67 70 Registers ADCONO A D Control 0 ADCONI A D Control 1 ADCON2 A D Control 2 BAUDCON Baud Rate Control 236 BDnSTAT Buffer Descriptor n Status GPU Mode jive cane ia ade ai ai 173 BDnSTAT Buffer Descriptor n Status SIE Mode 220 40 Lus anse Arno 174 CCP1CON Enhanced CCP Control 1 149 CCPxCON Standard Capture Compare PWM Control di si eee CMCON Comparator Control CONFIG1H Configuration 1 High CONFIGIL Configuration 1 Low CONFIG2H Configuration 2 High CONFIG2L Configuration 2 Low CONFIG3H Configuration 3 High CONFIGAL Configuration 4 Low CONFIGSH Configuration 5 High CONFIGEL Configuration 5 Low CONFIG6H Configuration 6 High CONFIGGL Configuration 6 Low CONFIG7H Configuration 7 High CONFIG7L Configuration 7 Low CVRCON Comparator Voltage Z RA RO Reference Control a 269 DEVID1 Device ID 1 a 290 DEVID2 Device ID 2
13. 2004 Microchip Technology Inc Preliminary DS39632B page 239 PIC18F2455 2550 4455 4550 20 1 3 AUTO BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate This feature is active only in Asynchronous mode and while the WUE bit is clear The automatic baud rate measurement seguence Figure 20 1 begins whenever a Start bit is received and the ABDEN bit is set The calculation is self averaging In the Auto Baud Rate Detect ABD mode the clock to the BRG is reversed Rather than the BRG clocking the incoming RX signal the RX signal is timing the BRG In ABD mode the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream Once the ABDEN bit is set the state machine will clear the BRG and look for a Start bit The Auto Baud Rate Detection must receive a byte with the value 55h ASCII U which is also the LIN bus Sync character in order to calculate the proper bit rate The measure ment is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal After a Start bit the SPBRG begins counting up using the preselected clock source on the first rising edge of RX After eight bits on the RX pin or the fifth rising edge an accumulated value totalling the proper BRG period is left in the SPBRGH SPBRG register pair Once the 5th edge
14. 122 O Summary LATD Register PORTD Register TRISD Register U un asas 120 PORTE Associated Registers 124 VO Summary a LATE Register 3 PORTE Register u 123 TRISE Register 54 al 123 Postscaler WDT Assignment PSA Bit Rate Select TOPS2 TOPSO Bits Switching Between Timer0 and WDT ty Power Managed Modes and A D Operation u and EUSART Operation M and Multiple Sleep Commands and PWM Operation a Clock Sources Clock Transitions and Status Indicators ENETH sr ere aC r rn Exiting Idle and Sleep Modes se DY Interrup Ja un SIG Zaa by RESET uu u sr teen cnrs by WDT Time out Without an Oscillator Start up Delay se Vlei est ets ala sl UL 39 Idle Modes PRI IDLE ziskava se su 40 RC_IDLE 41 SEC IDLE aaa quan r saan uta 40 DS39632B page 414 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 R R MOSS iiss uka a hu Na ha En LN RN 36 PRISR N ina rer renier ae 36 RC RUN SEC RUN uuu aaa D ha aa 36 Sel cting A rr sis 35 Sleep Summary table J eee u
15. Status Affected None Status Affected None Encoding 1110 0011 nnnn nnnn Encoding 1110 0111 nnnn nnnn Description If the Carry bit is o then the program Description If the Negative bit is o then the will branch program will branch The 2 s complement number 2n is The 2 s complement number 2n is added to the PC Since the PC will have added to the PC Since the PC will have incremented to fetch the next incremented to fetch the next instruction the new address will be instruction the new address will be PC 2 2n This instruction is then a PC 2 2n This instruction is then a two cycle instruction two cycle instruction Words 1 Words 1 Cycles 1 2 Cycles 1 2 Q Cycle Activity Q Cycle Activity If Jump If Jump 01 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC Decode Read literal Process Write to PC n Data n Data No No No No No No No No operation operation operation operation operation operation operation operation If No Jump If No Jump Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal Process No Decode Read literal Process No n Data operation n Data operation Example HERE BNC Jump Example HERE BNN Jump Before Instruction Before Instruction PC address HERE PC address HERE After Instruction After Instruction If Carry 0 If Negative 0 PC address Jump PC address Jump If Carry If Negative 1 PC address HERE 2 PC address
16. 171 Buffer Descriptors a Address Validation 174 Assignment in Different Buffering Modes 176 BDnSTAT Register CPU Mode 172 BDnSTAT Register SIE Mode 174 Byte Count 174 Example 171 Memory Map 175 Ownership 171 Ping Pong Buffering 175 Register Summary 176 Status and Configuration 171 Class Specifications and Drivers Descriplors sis wae Endpoint Control Enumeration si usun lia External Pull up Resistors suu External Transceiver Eye Pattern Test Enable Firmware and Drivers Frame Number Registers Frames ete an las clei hiedves Met dadap aie Internal Pull up Resistors s Internal Transceiver Internal Voltage Regulator Interrupts and USB Transactions Interrupt Logic Layered Framework Oscillator Requirements Output Enable Monitor a Overview s Ping Pong Buffer Configuration 167 PoWer aan aya r 184 Bus Power Only a 182 Dual Power with Self Power DOMINANCE a
17. RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax RETURN s Syntax RLCF f d a Operands se 0 1 Operands 0 lt f lt 255 Operation TOS gt PC de Ae ifs 1 ae 0 1 WS gt W Operation f lt n gt dest lt n 1 gt STATUSS Status f lt 7 gt C BSRS BSR C dest lt 0 gt PCLATU PCLATH are unchanged Status Affected C N Z Status Affected None Encoding 0011 01da ffff ffff Encoding BOSD LOU M VOTS Description The contents of register f are rotated Description Return from subroutine The stack is one bit to the left through the Carry popped and the top of the stack TOS flag If d is o the result is placed in is loaded into the program counter If W If d is 1 the result is stored back s 1 the contents of the shadow in register f default registers WS STATUSS and BSRS are If a is 0 the Access Bank is loaded into their corresponding selected If a is 1 the BSR is used to registers W Status and BSR If select the GPR bank default s 0 no update of these registers If a is o and the extended instruction occurs default set is enabled this instruction Words 4 operates in Indexed Literal Offset Addressing mode whenever Cycles 2 f lt 95 5Fh See Section 26 2 3 Q Cycle Activity Byte Oriented and Bit Oriented ai a2 a3 Q4 aoe nr Literal Offset Decode No Process Po
18. TABLE 21 2 REGISTERS ASSOCIATED WITH A D OPERATION Reset Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRI1IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMRSIE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 ADRESH A D Result Register High Byte 52 ADRESL A D Result Register Low Byte 52 ADCONO CHS3 CHS2 CHS1 CHSO GO DONE ADON 52 ADCON1 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 52 ADCON2 ADFM ACQT2 ACQT1 ACQTO ADCS2 ADCS1 ADCSO 52 PORTA RAG RA5 RA4 RA3 RA2 RAI RAO 54 TRISA TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 54 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 54 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATBO 54 PORTE RDPU RE313 RE24 RE1 REO 54 TRISE TRISE2 TRISE1 TRISEO 54 LATE LATE2 LATE1 LATEO 54 Legend unimplemented read as 0 Shaded cells are not used for A D conversion Note 1 Implemented only when Master Clear functionality is disabled MCLRE configu
19. 290 ECCP1AS ECCP Auto Shutdown Control er aa a dis BR ne se ECCP1DEL PWM Configuration EECON1 Data EEPROM Control 1 81 90 HLVDCON High Low Voltage Detect Control a INTCON Interrupt Control INTCON2 Interrupt Control 2 INTCONS Interrupt Control 3 IPR1 Peripheral Interrupt Priority 1 106 IPR2 Peripheral Interrupt Priority 2 107 OSCCON Oscillator Control wees OSCTUNE Oscillator Tuning 28 PIE Peripheral Interrupt Enable 1 104 PIE2 Peripheral Interrupt Enable 2 105 2004 Microchip Technology Inc Preliminary DS39632B page 415 PIC18F2455 2550 4455 4550 PIR1 Peripheral Interrupt Request FAQ A u saa as N 102 PIR2 Peripheral Interrupt Request Flag 2 u a a ala PORTE Sa a ya NI RCON Reset Control i RCSTA Receive Status and Control 235 SPPCFG SSP Configuration 188 SPPCON SPP Control 187 SPPEPS SPP Endpoint Address and Status 191 SSPCONI MSSP Control 1 C Mode 204 SSPCON1 MSSP Control 1 SPI Mode 195 SSPCON2 MSSP Control 2 C Mode
20. 71 Voltage RA2 g CVREF Output Reference Output Impedance Note 1 Ris dependent upon the voltage reference configuration bits CVRCON lt 3 0 gt and CVRCON lt 5 gt TABLE 23 1 REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Reset Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVRI CVRO 53 CMCON C20UT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53 TRISA TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 54 Legend Shaded cells are not used with the comparator voltage reference Note 1 PORTA pins are enabled based on oscillator configuration 2004 Microchip Technology Inc Preliminary DS39632B page 271 PIC18F2455 2550 4455 4550 NOTES O S EE S a i r r c F DS39632B page 272 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 24 0 HIGH LOW VOLTAGE DETECT HLVD PIC18F2455 2550 4455 4550 devices have a High Low Voltage Detect module HLVD This is a pro grammable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point If the device experiences an excursion past the trip point in that direction an interrupt flag is set If the interrupt is enabled the program execution will branch to the interrupt vector address and the software can then respond to the interrupt RE
21. bit 7 Unimplemented Read as 0 bit 6 EBTRB Boot Block Table Read Protection bit 1 Boot block 000000 0007FFh not protected from table reads executed in other blocks 0 Boot block 000000 0007FFh protected from table reads executed in other blocks bit 5 0 Unimplemented Read as 0 Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state 2004 Microchip Technology Inc Preliminary DS39632B page 289 PIC18F2455 2550 4455 4550 REGISTER 25 13 bit 7 5 bit 4 0 REGISTER 25 14 bit 7 0 DEVID1 DEVICE ID REGISTER 1 FOR PIC18F2455 2550 4455 4550 DEVICES R R R R R R R R DEV2 DEV1 DEVO REV4 REV3 REV2 REV1 REVO bit 7 bit 0 DEV2 DEVO Device ID bits 011 PIC18F2455 010 PIC18F2550 001 PIC18F4455 000 PIC18F4550 REV4 REVO Revision ID bits These bits are used to indicate the device revision Legend R Read only bit P Programmable bit U Unimplemented bit read as V n Value when device is unprogrammed u Unchanged from programmed state DEVID2 DEVICE ID REGISTER 2 FOR PIC18F2455 2550 4455 4550 DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 DEV10 DEV3 Device ID bits These bits are used with the DEV2 DEVO bits in the Device ID Register 1 to identify the part number 0001 0010 PIC1
22. 144 Device Clock 24 Enhanced PWM 151 EUSART Receive sssssssssessssssrsesrrresrrnsrresnrrneessnne 244 EUSART Transmit a u nu 242 External Power on Reset Circuit Slow VDD Power up Fail Safe Clock Monitor Generic VO Port High Low Voltage Detect with External Input 274 MSSP IC Master Mode aaa 217 MSSP I2C Mode MSSP SPI Mode On Chip Reset Circuit 43 PIC18F2455 2550 s PIC18F 4455 4550 PLL HS Mode uya na uh hk hn PWM Operation Simplified Ps Reads from Flash Program Memory 83 Single Comparator 265 SPP Data Path s Table Read Operation 1 Table Write Operation Table Writes to Flash Program Memory wat TimerO in 16 Bit Mode TimerO in 8 Bit Mode Timer1 Timer1 16 Bit Read Write Mode TIMEZ u D N T nee E ha PL TIMES z S ee a aan Timer3 16 Bit Read Write Mode USB Interrupt Logic USB Peripheral and Options Voltage Reference Output Buffer Example 271 Watchdog Timer a a 291 BN u aa aa um uu aa uka unas 310 BN
23. See MCLR VPP RES pin VUSB 14 O Internal USB 3 3V voltage regulator Vss 8 19 P Ground reference for logic and I O pins VDD 20 P Positive supply for logic and I O pins Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared 2 Default assignment for CCP2 when CCP2MX configuration bit is set 2004 Microchip Technology Inc Preliminary DS39632B page 15 PIC18F2455 2550 4455 4550 TABLE 1 3 PIC18F4455 4550 PINOUT O DESCRIPTIONS Pin Name s Pin Buffer Description PDIP QFN TQFP Type Type F MCLR VPP RE3 1 18 18 Master Clear input or programming voltage input MCLR ST Master Clear Reset input This pin is an active low Reset to the device VPP P Programming voltage input RE3 ST Digital input OSC1 CLKI 13 32 30 Oscillator crystal or external clock input OSC1 I Analog Oscillator crystal input or external clock source input CLKI Analog External clock source input Always associated with pin function OSC1 See OSC2 CLKO pins OSC2 CLKO RA6 14 33 31 Oscillator crystal or clock output OSC2 O Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode CLKO O In RC mode OSC2 pin outputs CLKO which has 1 4 the frequency of OSC1 and den
24. 35 Power on Reset POR a 45 Oscillator Start up Timer OST 47 Power up Timer PWRT 47 Time out Sequence 47 Power Up Delays 112121s0500 10 2110 110111 000 a 33 Power up Timer PWRT 33 47 Prescaler TE O O O 152 Prescaler Timer0 127 Assignment PSA Bit 127 Rate Select TOPS2 TOPSO Bits 127 Switching Between Timer0 and WDT 127 Prescaler Timer2 La PRI IDLE MOJE surement tennis PRI RUN Mode U U u PRO MATE II Universal Device Programmer u Program Counter ooo eee eee eeeeeceeeeseeseaeeseeeseneeeeeeeees PCL PCH and PCU Registers PCLATH and PCLATU Registers Program Memory and the Extended Instruction Set 75 Code Protection INStUICHIONS Len AA AA Two Word Interrupt Vector Look up Tables Map and Stack diagram 57 Reset Vector Program Verification and Code Protection 296 Associated Registers 296 Programming Device Instructions
25. DS39632B page 90 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 7 2 Reading the Data EEPROM Memory To read a data memory location the user must write the address to the EEADR register clear the EEPGD control bit EECON1 lt 7 gt and then set control bit RD EECON1 lt 0 gt The data is available on the very next instruction cycle therefore the EEDATA register can be read by the next instruction EEDATA will hold this value until another read operation or until it is written to by the user during a write operation The basic process is shown in Example 7 1 7 3 Writing to the Data EEPROM Memory To write an EEPROM data location the address must first be written to the EEADR register and the data written to the EEDATA register The seguence in Example 7 2 must be followed to initiate the write cycle The write will not begin if this sequence is not exactly followed write 55h to EECON2 write OAAh to EECON2 then set WR bit for each byte It is strongly recommended that interrupts be disabled during this code segment Additionally the WREN bit in EECON1 must be set to enable writes This mechanism prevents accidental writes to data EEPROM due to unexpected code exe cution i e runaway programs The WREN bit should be kept clear at all times except when updating the EEPROM The WREN bit is not cleared by hardware After a write sequence has been initiated EECON1 EEADR an
26. 126 Overflow Interrupt oo eee cece 127 Prescaler See Prescaler Timer0 TImmOeri ini 129 16 Bit Read Write Mode Associated Registers 133 Interrupt 132 Operation ses 130 Oscillator Zoan um ua as 129 131 Layout Considerations 132 Low Power Option 2 Using Timer1 as a Clock Source 131 Overflow Interrupt a 129 Resetting Using a Special Event Trigger Output CCP 132 Special Event Trigger ECCP 150 TMRI1H Register TMRIL Register Use as a Real Time Clock ssssesseeriererreererern 132 Timer2 a Associated Registers 136 Interr pt ASP ay u au aN Operation a O tpub asa anun or a al PR2 Regisler s 1 1 15 002 0x ar TMR2 to PR2 Match Interrupt TIMES yz sh ote re BN een 16 Bit Read Write Mode Associated Registers ae OPS ALON reines rie ao OSCINATOF pasa ated eee terse ee Overflow Interrupt Special Event Trigger CCP TMR3H Register ae TMRSL Register Timing Diagrams A D Conversion aa 393 Acknowledge Sequence 226 Asynchronous Reception 245 Asynchronous Transmission
27. FIGURE 22 2 SINGLE COMPARATOR VIN Output ViN Output l i 22 3 1 EXTERNAL REFERENCE SIGNAL When external voltage references are used the comparator module can be configured to have the com parators operate from the same or different reference sources However threshold detector applications may require the same reference The reference signal must be between Vss and VDD and can be applied to either pin of the comparator s 22 3 2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module This module is described in more detail in Section 23 0 Comparator Voltage Reference Module The internal reference is only available in the mode where four inputs are multiplexed to two comparators CM2 CMO 110 In this mode the internal voltage reference is applied to the VIN pin of both comparators 22 4 Comparator Response Time Response time is the minimum time after selecting a new reference voltage or input source before the comparator output has a valid level If the internal ref erence is changed the maximum delay of the internal voltage reference must be considered when using the comparator outputs Otherwise the maximum delay of the comparators should be used see Section 28 0 Electrical Characteristics 22 5 Comparator Outputs The comparator outputs are
28. LPT1OSC PBADEN CCP2MX 1 0 300006h CONFIG4L DEBUG XINST ICPRT LVP STVREN 100 1 300008h CONFIG5L cp3 1 CP2 CP1 CP0 11 300009h CONFIG5H CPD CPB 48222 30000Ah CONFIG6L WRT3 wRT2 WRT1 WRTO 11 30000Bh CONFIG6H WRTD WRTB WRTC Ae Ses 30000Ch CONFIG7L EBTR3 EBTR2 EBTR1 EBTRO SEJE A 30000Dh CONFIG7H EBTRB Hesse 3FFFFEh DEVID1 DEV2 DEV DEVO REV4 REV3 REV2 REV1 REVO xxxx xxxx 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010 Legend x unknown u unchanged unimplemented Shaded cells are unimplemented read as o Note 1 Unimplemented in PIC18FX455 devices maintain this bit set 2 See Register 25 15 for DEVID1 values DEVID registers are read only and cannot be programmed by the user DS39632B page 280 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 25 1 bit 7 6 bit 5 bit 4 3 bit 2 0 CONFIGIL CONFIGURATION REGISTER 1 LOW BYTE ADDRESS 300000h U 0 U 0 R P 0 R P 0 R P 0 R P 0 R P 0 R P 0 USBDIV CPUDIV1 CPUDIVO PLLDIV2 PLLDIV1 PLLDIVO bit 7 bit 0 Unimplemented Read as 0 USBDIV USB Clock Selection bit used in Full Speed USB mode only UCFG FSEN 1 1 USB clock source comes from the 96 MHz PLL divided by 2 0 USB clock source comes directly from th
29. a1 Selection Using OSCCON Register 31 CL RF nl ee en GR DR RAGE 317 ERAAN BI EEEE AN nn 317 Code Examples 16 x 16 Signed Multiply Routine 96 16 x 16 Unsigned Multiply Routine 96 8 x 8 Signed Multiply Routine wed 8 x 8 Unsigned Multiply Routine 95 Changing Between Capture Prescalers 143 Computed GOTO Using an Offset Value s a u SD S R a lane 60 Data EEPROM Read wie Data EEPROM Refresh Routine 92 Data EEPROM Write a 91 Erasing a Flash Program Memory Row s Fast Register Stack oooonnnornnn non How to Clear RAM Bank 1 Using Indirect Addressing 72 Implementing a Real Time Clock Using a Timer1 Interrupt Service 133 Initializing PORTA Initializing PORTB Initializing PORTO ns 117 Initializing PORTD Initializing PORTE Loading the SSPBUF SSPSR REGISLCD veces a sawanapak qaa anus 196 Reading a Flash Program Memory Word seins asus 83 Saving Status WREG and BSR Registers IN RAM sentier Writing to Flash Program Memory Code Protection a Comparator 424 lav ara at 263 Analog Input Connection Considerations 267 Associated Registers M Configuration a
30. 301 Pulse Width Modulation See PWM CCP Module and PWM ECCP Module PUSHA u aska Aa heat edd ale Ah o Lak aka PUSH and POP Instructions PUSFIE z sm annua aa n Usu aS ase PWM CCP Module Associated Registers xx tn 146 Auto Shutdown CCP1 only 147 Duty Cycle 146 Example Freguencies Resolutions 147 Period niet r 146 Setup for PWM Operation ee eee eeeees 147 TMR2 to PR2 Match eerren 146 151 PWM ECCP Module CCPRIH CCPRIL Registers 151 Direction Change in Full Bridge Output Mode ss D ty GCyele_ u l scesvardeveeavebed nee Effects of a Reset u Enhanced PWM Auto Shutdown an Example Frequencies Resolutions 152 Full Bridge Application Example 156 Full Bridge Mode me Half Bridge Mode sesesssssiessessreresrruensrresenreresenrinees 154 Half Bridge Output Mode Applications Example 154 Operation in Power Managed Modes sssesseeeesen 161 Operation with Fail Safe Clock Monitor saseaee 161 Output Configurations Output Relationships Active High Prodi see sir na n suu s amy m asal utana mus Programmable Dead Band Delay Setup for PWM Operation Start up Considerations
31. 9 1 2 2 Return Stack Pointer STKPTR The STKPTR register Register 5 1 contains the Stack Pointer value the STKFUL Stack Full status bit and the STKUNF Stack Underflow status bits The value of the Stack Pointer can be 0 through 31 The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack On Reset the Stack Pointer value will be zero The user may read and write the Stack Pointer value This feature can be used by a Real Time Operating System RTOS for return stack maintenance After the PC is pushed onto the stack 31 times without popping any values off the stack the STKFUL bit is set The STKFUL bit is cleared by software or by a POR The action that takes place when the stack becomes full depends on the state of the STVREN Stack Overflow Reset Enable configuration bit Refer to Section 25 1 Configuration Bits for a description of the device configuration bits If STVREN is set default the 31st push will push the PC 2 value onto the stack set the STKFUL bit and reset the device The STKFUL bit will remain set and the Stack Pointer will be set to zero If STVREN is cleared the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31 Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31 When the stack has been popped enough times to unload the stack the next pop will return a
32. POR gee gt i PWRT i i Time out t 32 lt Oscillator Time out Internal g S Reset j Watchdog ss Timer i Reset a 31 314 34 lt O pins gt J Note Refer to Figure 28 4 for load conditions FIGURE 28 8 BROWN OUT RESET TIMING VDD BVDD gt 35 VBGAP 1 2V VIRVST Fa Enable Internal l Reference Voltage I Internal Reference l Voltage Stable le 36 TABLE 28 12 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER POWER UP TIMER AND BROWN OUT RESET REGUIREMENTS k Symbol Characteristic Min Typ Max Units Conditions 30 TmeL MCLR Pulse Width low 2 us 31 TWDT Watchdog Timer Time out Period 4 00 TBD ms no postscaler 32 Tost Oscillation Start up Timer Period 1024 Tosc 1024 Tosc Tosc OSC1 period 33 TPWRT Power up Timer Period 65 5 TBD ms 34 Toz I O High Impedance from MCLR 2 us Low or Watchdog Timer Reset 35 TBOR Brown out Reset Pulse Width 200 us VDD lt Bvpp see D005 36 TIRVST Time for Internal Reference 20 50 us Voltage to become Stable 37 TLVD Low Voltage Detect Pulse Width 200 us VDD lt VLVD 38 TcsD CPU Start up Time 5 10 us 39 TioBsT Time for INTOSC to Stabilize 1 ms Legend TBD To Be Determined 2004 Microchip Techno
33. RA2 AN2 _D_ VIN VREF CVREF Four Inputs Multiplexed to Two Comparators CM2 CMO 110 A RAO ANO 0 GIS 20 VIN RA3 AN3 o CIS 1 a C1OUT VREF VIN PON RAI AN1 A CIS 0 VIN RA2 AN2 A s CIS 1 VREF CVREF Vis C2 C2OUT Ed From VREF Module A Analog Input port reads zeros always D Digital Input Setting the TRISA lt 5 4 gt bits will disable the comparator outputs by configuring the pins as inputs CIS CMCON lt 3 gt is the Comparator Input Switch DS39632B page 264 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 22 2 Comparator Operation A single comparator is shown in Figure 22 2 along with the relationship between the analog input levels and the digital output When the analog input at VIN is less than the analog input VIN the output of the comparator is a digital low level When the analog input at VIN is greater than the analog input VIN the output of the comparator is a digital high level The shaded areas of the output of the comparator in Figure 22 2 represent the uncertainty due to input offsets and response time 22 3 Comparator Reference Depending on the comparator operating mode either an external or internal voltage reference may be used The analog signal present at VIN is compared to the signal at VIN and the digital output of the comparator is adjusted accordingly Figure 22 2
34. REGISTER 20 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BAUDCON BAUD RATE CONTROL REGISTER R W 0 R 1 U 0 R W 0 R W 0 U 0 R W 0 R W 0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN bit 7 bit 0 ABDOVF Auto Baud Acquisition Rollover Status bit 1 A BRG rollover has occurred during Auto Baud Rate Detect mode must be cleared in software 0 No BRG rollover has occurred RCIDL Receive Operation Idle Status bit 1 Receive operation is Idle o Receive operation is active Unimplemented Read as SCKP Synchronous Clock Polarity Select bit Asynchronous mode Unused in this mode Synchronous mode 1 Idle state for clock CK is a high level 0 Idle state for clock CK is a low level BRG16 16 bit Baud Rate Register Enable bit 1 16 bit Baud Rate Generator SPBRGH and SPBRG 0 8 bit Baud Rate Generator SPBRG only Compatible mode SPBRGH value ignored Unimplemented Read as WUE Wake up Enable bit Asynchronous mode 1 EUSART will continue to sample the RX pin interrupt generated on falling edge bit cleared in hardware on following rising edge o RX pin not monitored or rising edge detected Synchronous mode Unused in this mode ABDEN Auto Baud Detect Enable bit Asynchronous mode 1 Enable baud rate measurement on the next character Requires reception of a Sync field 55h cleared in hardware upon completion 0 Baud rate measurement disabled or complet
35. WY NY NZ 17 6 3 DUAL POWER WITH SELF POWER DOMINANCE Some applications may require a dual power option This allows the application to use internal power prima rily but switch to power from the USB when no internal power is available Figure 17 12 shows a simple Dual Power with Self Power Dominance example which automatically switches between Self Power Only and USB Bus Power Only modes FIGURE 17 12 DUAL POWER EXAMPLE 100 kQ Attach Sense f ANN VO pin vBUS I VDD 100 a E VUSB NS gt t vss N yv NN yv Si Note Users should keep in mind the limits for devices drawing power from the USB According to USB Specification 2 0 this cannot exceed 100 mA per low power device or 500 mA per high power device 17 7 Streaming Parallel Port The Streaming Parallel Port SPP is an alternate route option for data besides USB RAM Using the SPP an endpoint can be configured to send data to or receive data directly from external hardware This methodology presents design possibilities where the microcontroller acts as a data manager allowing the SPP to pass large blocks of data without the micro controller actually processing it An application example might include a data acguisition system where data is streamed from an external FIFO through USB to the host computer In this case endpoint control is managed by the microcontroller and raw data movement is processed exter
36. Not Optional Write to SSPBUF J spo CE ARE Gss 2 CH CH ET HOCI OS Pox 1000 SMP o 1 bit 7 Input 4 i 4 i 4 i Sample i i 4 1 1 1 i 1 SMP 0 I i SSPIF Interrupt i i i I A Flag i i y 1 i A i Next Q4 Cycle SSPSRto i i paer Q2l SSPBUF__ l DS39632B page 200 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 3 8 OPERATION IN POWER MANAGED MODES In SPI Master mode module clocks may be operating at a different speed than when in full power mode in the case of the Sleep mode all clocks are halted In most power managed modes a clock is provided to the peripherals That clock should be from the primary clock source the secondary clock Timer1 oscillator at 32 768 kHz or the INTOSC source See Section 2 4 Clock Sources and Oscillator Switching for additional information In most cases the speed that the master clocks SPI data is not important however this should be evaluated for each system If MSSP interrupts are enabled they can wake the con troller from Sleep mode or one of the Idle modes when the master completes sending data If an exit from Sleep or Idle mode is not desired MSSP interrupts should be disabled If the Sleep mode is selected all module clocks are halted and
37. and Two Speed Start up DS39632B page 24 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 2 2 2 CRYSTAL OSCILLATOR CERAMIC RESONATORS In HS HSPLL XT and XTPLL Oscillator modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation Figure 2 2 shows the pin connections The oscillator design requires the use of a parallel cut crystal Note Use of a series cut crystal may give a fre quency out of the crystal manufacturer s specifications FIGURE 2 2 CRYSTAL CERAMIC RESONATOR OPERATION XT HS OR HSPLL CONFIGURATION OSC1 I XTAL Rs ca OSC2 Note 1 See Table 2 1 and Table 2 2 for initial values of C1 and C2 2 Aseries resistor Rs may be required for AT strip cut crystals 3 RF varies with the oscillator mode chosen PIC18FXXXX TABLE 2 1 CAPACITOR SELECTION FOR CERAMIC RESONATORS TABLE 2 2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested Osc Type Freq C1 C2 XT 4 MHz 27 pF 27 pF HS 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15pF 15 pF Capacitor values are for design guidance only These capacitors were tested with the crystals listed below for basic start up and operation These values are not optimized Different capacitor values may be reguired to produce accep
38. 0 bits and a Stop bit The Frame Break character is sent whenever the SENDB and TXEN bits TXSTA lt 3 gt and TXSTA lt 5 gt are set while the Transmit Shift Register is loaded with data Note that the value of data written to TXREG will be ignored and all o s will be transmitted The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent This allows the user to preload the transmit FIFO with the next transmit byte following the Break character typically the Sync character in the LIN specification Note that the data value written to the TXREG for the Break character is ignored The write simply serves the purpose of initiating the proper sequence The TRMT bit indicates when the transmit operation is active or Idle just as it does during normal transmis sion See Figure 20 10 for the timing of the Break character sequence 20 2 5 1 The following sequence will send a message frame header made up of a Break followed by an Auto Baud Sync byte This sequence is typical of a LIN bus master Break and Sync Transmit Sequence 1 Configure the EUSART for the desired mode 2 Set the TXEN and SENDB bits to set up the Break character 3 Load the TXREG with a dummy character to initiate transmission the value is ignored 4 Write 55h to TXREG to load the Sync character into the transmit FIFO buffer 5 After the Break has been sent the SENDB bit is reset by hardware The Sync
39. FIGURE 14 2 TIMER3 BLOCK DIAGRAM 16 BIT READ WRITE MODE Timer1 Oscillator T3CKPS1 T3CKPSO T3SYNC Timer1 Clock Input 1 Prescaler Synchronize T1OSO T13CKI x gt 1 Fosc 4 1 2 4 Detect 0 in Internal A 4 0 TIOSI X Clock 1 VEN Po Sleep Input T1OSCEN TMR3CS Timer3 TMR3ON CCP1 CCP2 Special Event Trigger Clear TMR3 TMR3 Set CCP1 CCP2 Select from T3CON lt 6 3 gt TMRSL High Byte gt TMR3IF ZN ST on Overflow Note 1 When enable bit TIOSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain e ZN 8 NA 7 Read TMRIL Write TMRIL N8 L8 TMR3H 8 gt Internal Data Bus DS39632B page 138 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 14 2 Timer3 16 Bit Read Write Mode Timer3 can be configured for 16 bit reads and writes see Figure 14 2 When the RD16 control bit T3CON lt 7 gt is set the address for TMR3H is mapped to a buffer register for the high byte of Timer3 A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 high byte buffer This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte followed by a read of the
40. 00h will set flag bit TMROIF In 16 bit mode an overflow in the TMROH TMROL regis ter pair FFFFh gt 0000h will set TMROIF The interrupt can be enabled disabled by setting clearing enable bit TMROIE INTCON lt 5 gt Interrupt priority for TimerO is determined by the value contained in the interrupt priority bit TMROIP INTCON2 lt 2 gt See Section 13 0 Timer2 Module for further details on the TimerO module 9 9 PORTB Interrupt on Change An input change on PORTB lt 7 4 gt sets flag bit RBIF INTCON lt 0 gt The interrupt can be enabled disabled by setting clearing enable bit RBIE INTCON lt 3 gt Interrupt priority for PORTB interrupt on change is determined by the value contained in the interrupt priority bit RBIP INTCON2 lt 0 gt 9 10 Context Saving During Interrupts During interrupts the return PC address is saved on the stack Additionally the WREG Status and BSR registers are saved on the fast return stack If a fast return from interrupt is not used see Section 5 3 Data Memory Organization the user may need to save the WREG Status and BSR registers on entry to the Interrupt Service Routine Depending on the user s application other registers may also need to be saved Example 9 1 saves and restores the WREG Status and BSR registers during an Interrupt Service Routine EXAMPLE 9 1 SAVING STATUS WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP i W TEMP is in virtual bank MOVFF STATUS
41. 1 Least Significant Byte of Program Memory Word Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows no change post increment pre increment Q2 post decrement Q3 Q4 Decode No operation No operation No operation No operation No operation Read Program Memory No operation No operation Write TABLAT TBLRD Table Read Continued Example 1 TBLRD Before Instruction TABLAT 55h TBLPTR 00A356h MEMORY 00A 356h 34h After Instruction TABLAT 34h TBLPTR 00A357h Example 2 TBLRD Before Instruction TABLAT AAh TBLPTR 01A357h MEMORY 01A357h 12h MEMORY 01A358h 34h After Instruction TABLAT 34h TBLPTR 01A358h 2004 Microchip Technology Inc Preliminary DS39632B page 339 PIC18F2455 2550 4455 4550 TBLWT Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Table Write TBLWT None if TBLWT TABLAT Holding Register TBLPTR No Change if TBLWT TABLAT Holding Register TBLPTR 1 TBLPTR if TBLWT TABLAT Holding Register TBLPTR 1 gt TBLPTR if TBLWT TBLPTR 1 TBLPTR TABLAT Holding Register None 0000 0000 0000 11nn nn 0 l 2 3 This instruction uses t
42. 351 Device Differences in Device Ove vieW n i a assis cess Features table J u u New Core Features SA Other Special Features a Device Reset Timers u una a Oscillator Start up Timer OST PEL Loek Time oUt s u dezcs2ccececeessaat jostsecenedsvecstee Power up Timer PWRT Direct Addressing a E Effect on Standard PIC Instructions 75 348 Electrical Characteristics 357 Enhanced Capture Compare PWM ECCP 149 Associated Registers a Capture and Compare Modes 150 Capture Mode See Capture ECCP Module Outputs and Configuration 150 Pin Configurations for ECCP1 150 PWM Mode See PWM ECCP Module Standard PWM Mode 150 Timer Resources Enhanced PWM Mode See PWM ECCP Module Enhanced Universal Synchronous Receiver Transmitter USART See EUSART Equations A D Acquisition Time A D Minimum Charging Time Calculating the Minimum Required A D Acquisition Time 258 EUSART Asynchronous Mode Associated R
43. 390 EUSART Synchronous Transmission Master Slave Example SPI Master Mode CKE 0 Example SPI Master Mode CKE 1 Example SPI Slave Mode CKE 0 Example SPI Slave Mode CKE 1 External Clock All Modes Except PLL Fail Safe Clock Monitor First Start Bit Timing a Full Bridge PWM Output Half Bridge PWM Output High Low Voltage Detect Characteristics 373 High Voltage Detect VDIRMAG 1 EC Bus Datta us sasa ai auqa IC Bus Start Stop Bits J aaa I C Master Mode 7 or 10 Bit Transmission 224 IC Master Mode 7 Bit Reception 225 IC Slave Mode 10 Bit Reception SEN 0 210 IC Slave Mode 10 Bit Reception SEN 1 215 IC Slave Mode 10 Bit Transmission 211 IC Slave Mode 7 Bit Reception SEN 0 208 IC Slave Mode 7 Bit Reception SEN 1 214 IC Slave Mode 7 Bit Transmission 209 I2C Slave Mode General Call Address Sequence 7 or 10 Bit Address Mode 216 Low Voltage Detect VDIRMAG 0 Master SSP C Bus Data Master SSP IC Bus Start Stop Bits PWM Auto Shutdown PRSEN 0 Auto Restart Dis abled uu a asawa au e a sa es 160 PWM Auto Shutdown PRSEN 1 Auto Restart Ena
44. Alternate Run Modes By clocking the controller from the Timer1 source or the internal oscillator block power consumption during code execution can be reduced by as much as 90 Multiple Idle Modes The controller can also run with its CPU core disabled but the peripherals still active In these states power consumption can be reduced even further to as little as 4 of normal operation requirements On the fly Mode Switching The power managed modes are invoked by user code during operation allowing the user to incorporate power saving ideas into their application s software design e Low Consumption in Key Modules The power requirements for both Timer1 and the Watchdog Timer are minimized See Section 28 0 Electrical Characteristics for values 1 1 2 UNIVERSAL SERIAL BUS USB Devices in the PIC18F2455 2550 4455 4550 family incorporate a fully featured Universal Serial Bus communications module that is compliant with the USB Specification Revision 2 0 The module supports both low speed and full speed communication for all sup ported data transfer types It also incorporates its own on chip transceiver and 3 3V regulator and supports the use of external transceivers and voltage regulators 1 1 3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2455 2550 4455 4550 family offer twelve different oscillator options allowing users a wide range of choices in developing application hardware
45. DS39632B page 120 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 10 7 PORTD I O SUMMARY Pin Function hin VO VO Type Description RDO SPPO RDO 0 OUT DIG LATD lt 0 gt data output 1 IN ST PORTD lt 0 gt data input SPPO 1 OUT DIG SPP lt 0 gt output data takes priority over port data 1 IN TTL SPP lt 0 gt input data RD1 SPP1 RD1 0 OUT DIG LATD lt 1 gt data output IN ST PORTD lt 1 gt data input SPP1 OUT DIG SPP lt 1 gt output data takes priority over port data 1 IN TTL SPP lt 1 gt input data RD2 SPP2 RD2 0 OUT DIG LATD lt 2 gt data output IN ST PORTD lt 2 gt data input SPP2 OUT DIG SPP lt 2 gt output data takes priority over port data 1 IN TTL SPP lt 2 gt input data RD3 SPP3 RD3 0 OUT DIG LATD lt 3 gt data output IN ST PORTD lt 3 gt data input SPP3 a OUT DIG SPP lt 3 gt output data takes priority over port data ab IN TTL SPP lt 3 gt input data RD4 SPP4 RD4 0 OUT DIG LATD lt 4 gt data output IN ST PORTD lt 4 gt data input SPP4 1 OUT DIG SPP lt 4 gt output data takes priority over port data 1 IN TIL SPP lt 4 gt input data RD5 SPP5 P1B RD5 0 OUT DIG LATD lt 5 gt data output 1 IN ST PORTD lt 5 gt data input SPP5 1 OUT DIG SPP lt 5 gt output data takes priority over port data 1 IN TTL SPP lt 5 gt input data P1B 0 OUT DIG ECCP
46. Single Word SRAM EEPROM VO ch pwm SPP spim Master S 8 16 bit bytes Instructions bytes bytes CTM a E oO PIC18F2455 24K 12288 2048 256 24 10 2 0 No Y Y 1 2 1 3 PIC18F2550 32K 16384 2048 256 24 10 2 0 No Y Y 1 2 1 3 PIC18F4455 24K 12288 2048 256 35 13 1 1 Yes Y Y 1 2 1 3 PIC18F4550 32K 16384 2048 256 35 13 1 1 Yes Y Y 1 2 1 3 2004 Microchip Technology Inc Preliminary DS39632B page 1 PIC18F2455 2550 4455 4550 Pin Diagrams 28 Pin PDIP SOIC MCLR VPP RE3 L 191 SJ 28 Fr RB7 KBI3 PGD RAO ANO 2 2711 RB6 KBI2 PGC RAI AN1 L 3 26 1 RB5 KBI1 PGM RA2 AN2 VREF CVREF LI 4 251 RB4 AN11 KBIO RAS ANS VREF L 5 02 24 1 RB3 AN9 CCP2 l yVPO RA4 TOCKI C1OUT RCV L 6 a8 23 RB2 AN8 INT2 VMO RA5 AN4 SS HLVDIN C20UT lt 7 U I 221 1 RB1 AN10 INT1 SCK SCL Vss O 8 rr 21 RB0 AN12 INTO FLTO SDI SDA OSCI CLKI 9 gg 20 1 voo OSC2 CLKO RA6 10 191 vss RCO T10SO T13CKI lt gt L 11 18 RC7 RX DT SDO RCI T10OSI CCP
47. 0 will make the corresponding PORTE pin an output i e put the contents of the output latch on the selected pin In PIC18F2455 2550 4455 4550 devices the RC3 pin is not implemented The Data Latch register LATC is also memory mapped Read modify write operations on the LATC register read and write the latched output value for PORTC PORTC is primarily multiplexed with serial communica tions modules including the EUSART MSSP module and the USB module Table 10 5 Except for RC4 and RC5 PORTC uses Schmitt Trigger input buffers Pins RC4 and RC5 are multiplexed with the USB module Depending on the configuration of the module they can serve as the differential data lines for the on chip USB transceiver or the data inputs from an external USB transceiver Both RC4 and RC5 have TTL input buffers instead of the Schmitt Trigger buffers on the other pins Unlike other PORTC pins RC4 and RC5 do not have TRISC bits associated with them As digital ports they can only function as digital inputs When configured for USB operation the data direction is determined by the configuration and status of the USB module at a given time If an external transceiver is used RC4 and RC5 always function as inputs from the transceiver If the on chip transceiver is used the data direction is determined by the operation being performed by the module at that time When the external transceiver is enabled RC2 also serves as the output enab
48. 2n This instruction is a two cycle instruction Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data Push PC to stack No No No No operation operation operation operation Example HERE RCALL Jump Before Instruction PC Address HERE After Instruction PC Address Jump TOS Address HERE 2 RESET Reset Syntax RESET Operands None Operation Reset all registers and flags that are affected by a MCLR Reset Status Affected All Encoding 0000 0000 PITI TITI Description This instruction provides a way to execute a MCLR Reset in software Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Start No No Reset operation operation Example RESET After Instruction Registers Reset Value Flags Reset Value 2004 Microchip Technology Inc Preliminary DS39632B page 331 PIC18F2455 2550 4455 4550 RETFIE Return from Interrupt RETLW Return Literal to W Syntax RETFIE s Syntax RETLW k Operands s e 0 1 Operands 0 lt k lt 255 Operation TOS PC Operation k W 1 GIE GIEH or PEIE GIEL TOS PC if s 1 PCLATU PCLATH are unchanged WS gt W Status Affected None STATUSS Status BSRS BSR Encoding 0000 1100 kkkk kkkk PCLATU PCLATH are unchanged Description W is loaded wi
49. 34h DS39632B page 340 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TSTFSZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Test f Skip if 0 TSTFSZ f a O lt f lt 255 ae 0 1 skip if f 0 None 0110 Olla ffff ffff If f 0 the next instruction fetched during the current instruction execution is discarded and a NOP is executed making this a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction Q1 Q2 Q3 Q4 Decode Read Process No register f Data operation If skip Q1 Q2 93 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE TSTFSZ CNT 1 NZERO ZERO Before Instruction PC Address HERE After Instruction If CNT 00h PC Address ZERO
50. 4 Set the TMR2 prescale value then enable Timer2 by writing to T2CON 5 Configure the CCPx module for PWM operation 2004 Microchip Technology Inc Preliminary DS39632B page 147 PIC18F2455 2550 4455 4550 TABLE 15 5 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 RCON IPEN SBOREN RI TO PD POR BOR 52 PIR1 SPPIF2 ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP2 ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 54 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 54 TMR2 Timer2 Register 52 PR2 Timer2 Period Register 52 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPSO 52 CCPRIL Capture Compare PWM Register 1 Low Byte 53 CCPRIH Capture Compare PWM Register 1 High Byte 53 CCPICON P1M1 P1M0 DCIB DC1BO CCP1M3 CCP1M2 CCP1M1 CCP1MO 53 CCPR2L Capture Compare PWM Register 2 Low Byte 53 CCPR2H Capture Compare PWM Register 2 High Byte 53 CCP2CON DC2B1 DC2BO CCP2M3 CCP2M2 CCP2M1 CCP2M0 53 ECCPIAS ECCPASE ECCPAS2 ECCPAS1 ECCPASO PSSAC1 PSSACO PSSBD1 PS
51. If CNT PC Address NZERO XORLW Exclusive OR Literal with W Syntax XORLW k Operands 0 lt k lt 255 Operation W XOR k gt W Status Affected N Z Encoding 0000 1010 kkkk kkkk Description The contents of W are XORed with the 8 bit literal k The result is placed in W Words 1 Cycles 1 Q Cycle Activity 01 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example XORLW OAFh Before Instruction W B5h After Instruction W 1Ah 2004 Microchip Technology Inc Preliminary DS39632B page 341 PIC18F2455 2550 4455 4550 XORWF Exclusive OR W with f Syntax XORWF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation W XOR f gt dest Status Affected N Z Encoding 0001 10da ffff ffff Description Exclusive OR the contents of W with register f If d is o the result is stored in W If d is 1 the result is stored back in the register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity
52. PIC18F2455 2550 4455 4550 TABLE 28 1 MEMORY PROGRAMMING REQUIREMENTS DC Characteristics ee icles Sym Characteristic Min Typt Max Units Conditions Internal Program Memory Programming Specifications D110 VPP Voltage on MCLR VPP RE3 pin 9 00 13 25 V Note 3 D113 IDDP Supply Current during 10 mA Programming Data EEPROM Memory D120 ED Byte Endurance 100K 1M E W 40 C to 85 C D121 VDRW VDD for Read Write VMIN 5 5 V Using EECON to read write VMIN Minimum operating voltage D122 TDEW Erase Write Cycle Time 4 ms D123 TRETD Characteristic Retention 40 Year Provided no other specifications are violated D124 TREF Number of Total Erase Write 1M 10M E W 40 C to 85 C Cycles before Refresh 2 Program Flash Memory D130 EP Cell Endurance 10K 100K EMW 40 C to 85 C D131 VPR VDD for Read VMIN 5 5 V VMIN Minimum operating voltage D132 VIE Vpp for Block Erase 4 5 5 5 V Using ICSP port D132A Viw Vpp for Externally Timed Erase 4 5 5 5 V Using ICSP port or Write D132B VPEW VDD for Self timed Write VMIN 5 5 V VMI Minimum operating voltage D133 TIE ICSP Block Erase Cycle Time 4 ms VDD gt 4 5V D133A Tiw ICSP Erase or Write Cycle Time 1 ms VDD gt 4 5V externally timed D133A TIW Self timed Write Cycle Time 2 ms D134 TRETD Characteristic Retention 40 100 Year Provided no other
53. PSP INTn pins and others Peripherals that may add significant current consumption are listed in Section 28 2 DC Characteristics Power Down and Supply Current 2 6 Power up Delays Power up delays are controlled by two timers so that no external Reset circuitry is required for most applications The delays ensure that the device is kept in Reset until the device power supply is stable under normal circum stances and the primary clock is operating and stable For additional information on power up delays see Section 4 5 Device Reset Timers The first timer is the Power up Timer PWRT which provides a fixed delay on power up parameter 33 Table 28 12 It is enabled by clearing 0 the PWRTEN configuration bit The second timer is the Oscillator Start up Timer OST intended to keep the chip in Reset until the crystal oscillator is stable XT and HS modes The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device When the HSPLL Oscillator mode is selected the device is kept in Reset for an additional 2 ms following the HS mode OST delay so the PLL can lock to the incoming clock frequency There is a delay of interval TCSD parameter 38 Table 28 12 following POR while the controller becomes ready to execute instructions This delay runs concurrently with any other delays This may be the only delay that occurs when any of the EC or internal oscillator modes
54. Preliminary DS39632B page 71 PIC18F2455 2550 4455 4550 5 4 Data Addressing Modes Note The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction setis enabled See Section 5 6 Data Memory and the Extended Instruction Set for more information While the program memory can be addressed in only one way through the program counter information in the data memory space can be addressed in several ways For most instructions the addressing mode is fixed Other instructions may use up to three modes depending on which operands are used and whether or not the extended instruction set is enabled The addressing modes are Inherent Literal Direct Indirect An additional addressing mode Indexed Literal Offset is available when the extended instruction set is enabled XINST configuration bit 1 Its operation is discussed in greater detail in Section 5 6 1 Indexed Addressing with Literal Offset 9 4 1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all they either perform an operation that globally affects the device or they operate implicitly on one register This addressing mode is known as Inherent Addressing Examples include SLEEP RESET and DAW Other instructions work in a similar way but require an additional explicit argument in the opcode This is known as Lite
55. SDA SEN cleared automatically because of bus collision SSP module reset into Idle state SSPIF and BCLIF are cleared in software SCL Set SEN enable Start aa condition if SDA 1 SCL 1 SEN SDA sampled low before Start condition Set BCLIF S bit and SSPIF set because BCLIF SDA 0 SCL 1 s SSPIF E SSPIF and BCLIF are cleared in software DS39632B page 228 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 19 27 BUS COLLISION DURING START CONDITION SCL 0 SDA 0 SOL 21 k TBRG te TBRG gt SDA SCL Set SEN enable Start Ue sequence if SDA 1 SCL 1 v t SCL 0 before SDA 0 bus collision occurs Set BCLIF SEN SCL 0 before BRG time out pi bus collision occurs Set BCLIF BCLIF a Interrupt cleared L_ in software s 0 o SSPIF 0 FIGURE 19 28 BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA 0 SCL 1 Set S Set SSPIF Less than TBRG e TERG SDA SDA pulled low by other master N Reset BRG and assert SDA 77X I SCL S N I I I 4 SCL pulled low after BRG I SEN time out Set SEN enable Start sequence if SDA 1 SCL 1 BCLIF I g I I S I SSPIF 1 SDA 0 SOL 1 Interrupts clear
56. The use of Indexed Literal Offset Addressing mode effectively changes how the lower portion of Access RAM 00h to 5Fh is mapped Rather than containing just the contents of the bottom half of Bank 0 this mode maps the contents from Bank 0 and a user defined window that can be located anywhere in the data memory space The value of FSR2 establishes the lower boundary of the addresses mapped into the window while the upper boundary is defined by FSR2 plus 95 5Fh Addresses in the Access RAM above 5Fh are mapped as previously described see Section 5 3 3 Access Bank An example of Access Bank remapping in this addressing mode is shown in Figure 5 9 Remapping of the Access Bank applies only to opera tions using the Indexed Literal Offset mode Operations that use the BSR Access RAM bit is 1 will continue to use direct addressing as before Any indirect or indexed operation that explicitly uses any of the indirect file operands including FSR2 will continue to operate as standard indirect addressing Any instruction that uses the Access Bank but includes a register address of greater than 05Fh will use direct addressing and the normal Access Bank map 5 6 4 BSR IN INDEXED LITERAL OFFSET MODE Although the Access Bank is remapped when the extended instruction set is enabled the operation of the BSR remains unchanged Direct addressing using the BSR to select the data memory bank operates in the same manner as previ
57. s interrupt funnel REGISTER 17 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 UIR USB INTERRUPT STATUS REGISTER U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R W 0 SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF bit 7 bit 0 Unimplemented Read as 0 SOFIF START OF FRAME Token Interrupt bit 1 A START OF FRAME token received by the SIE 0 No START OF FRAME token received by the SIE STALLIF A STALL Handshake Interrupt bit 1 A STALL handshake was sent by the SIE 0 A STALL handshake has not been sent IDLEIF Idle Detect Interrupt bit 1 Idle condition detected constant Idle state of 3 ms or more 0 No Idle condition detected TRNIF Transaction Complete Interrupt bit 2 1 Processing of pending transaction is complete read USTAT register for endpoint information 0 Processing of pending transaction is not complete or no transaction is pending ACTVIF Bus Activity Detect Interrupt bit 1 Activity on the D D lines was detected 0 No activity detected on the D D lines UERRIF USB Error Condition Interrupt bit 1 An unmasked error condition has occurred 0 No unmasked error condition has occurred URSTIF USB Reset Interrupt bit 1 Valid USB Reset occurred 00h is loaded into UADDR register o No USB Reset has occurred Note 1 Once an ldle state is detected the user may want to place the USB module in Suspend mode 2 Clearing this bit will cause the USTAT FI
58. 113 UEP15 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP14 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP13 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP12 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP11 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP10 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP9 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP8 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP7 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP6 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP5 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP4 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP3 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP2 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEP1 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 UEPO EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 0 0000 55 169 Legend x unknown u unchanged unimplemented g value depends on condition Note 1 Bit21 ofthe TBLPTRU allows access to the device configuration bits 2 The SBOREN bit is only avai
59. 17 2 2 8 Internal Regulator The PIC18FX455 X550 devices have a built in 3 3V reg ulator to provide power to the internal transceiver and provide a source for the internal external pull ups An external 220 nF 20 capacitor is required for stability Note The drive from VUSB is sufficient to only drive an external pull up in addition to the internal transceiver The regulator is enabled by default and can be disabled through the VREGEN configuration bit When enabled the voltage is visible on pin VusB When the regulator is disabled a 3 3V source must be provided through the VUSB pin for the internal transceiver If the internal transceiver is disabled VUSB is not used Note 1 Do not enable the internal regulator if an external regulator is connected to VUSB 2 VDD must be greater than VUSB at all times even with the regulator disabled 2004 Microchip Technology Inc Preliminary DS39632B page 167 PIC18F2455 2550 4455 4550 17 2 3 USB STATUS REGISTER USTAT The USB Status register reports the transaction status within the SIE When the SIE issues a USB transfer complete interrupt USTAT should be read to determine the status of the transfer USTAT contains the transfer endpoint number direction and ping pong buffer pointer value if used The USTAT register is actually a read window into a four byte status FIFO maintained by the SIE It allows the microcontroller to process o
60. 2550 4455 4550 X XXXX u uuuu u uuuu TMROH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TMROL 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu TOCON 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu OSCCON 2455 2550 4455 4550 0100 g000 0100 00g0 uuuu uuqu HLVDCON 2455 2550 4455 4550 0 00 0101 0 00 0101 u uu uuuu WDTCON 2455 2550 4455 4550 0 o u RCON 2455 2550 4455 4550 0g 1 11g0 0g g qquu ug u qquu TMRIH 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu TMR1L 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu T1CON 2455 2550 4455 4550 0000 0000 uduu uuuu uuuu uuuu TMR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PR2 2455 2550 4455 4550 IILI Ad 1111 1111 1111 1111 T2CON 2455 2550 4455 4550 000 0000 000 0000 uuu uuuu SSPBUF 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu SSPADD 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SSPCON1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SSPCON2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu ADRESH 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu ADRESL 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu ADCON0 2455 2550 4455 4550 00 0000 00 0000 uu uuuu ADCON1 2455 2550 4455 4550 00 Oqqq 00 0Oggg uu uuuu ADCON2 2455 2550 4455 4550 0 00 0
61. 3 2 2 SEC RUN MODE The SEC RUN mode is the compatible mode to the clock switching feature offered in other PIC18 devices In this mode the CPU and peripherals are clocked from the Timer1 oscillator This gives users the option of lower power consumption while still using a high accuracy clock source SEC RUN mode is entered by setting the SCS1 SCSO bits to 01 The device clock source is switched to the Timer1 oscillator see Figure 3 1 the primary oscillator is shut down the T1RUN bit T1CON lt 6 gt is set and the OSTS bit is cleared Note The Timeri oscillator should already be running prior to entering SEC_RUN mode If the T1OSCEN bit is not set when the SCS1 SCSO0 bits are set to 01 entry to SEC_RUN mode will not occur If the Timer1 oscillator is enabled but not yet running device clocks will be delayed until the oscillator has started In such situations initial oscillator operation is far from stable and unpredictable operation may result On transitions from SEC_RUN mode to PRI_RUN the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started When the primary clock becomes ready a clock switch back to the primary clock occurs see Figure 3 2 When the clock switch is complete the T1RUN bit is cleared the OSTS bit is set and the primary clock is providing the clock The IDLEN and SCS bits are not affected by the wake up the Timer1 oscillator conti
62. 46 E 47 O 12 24 25 25 26 48 E 49 O 50 E 51 O 13 26 27 27 28 52 E 53 O 54 E 55 O 14 28 29 29 30 56 E 57 O 58 E 59 O 15 30 31 31 32 60 E 61 O 62 E 63 O Legend E Even transaction buffer O Odd transaction buffer TABLE 17 5 SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDNSTATU UOWN DTS PID3 2 PID2 2 PID1 PIDO BC9 BC8 KEN INCDIS DTSEN BSTALL BDnCNTU Byte Count BDnADRL Buffer Address Low BDnADRH Buffer Address High Note 1 For buffer descriptor registers n may have a value of 0 to 63 For the sake of brevity all 64 registers are shown as one generic prototype All registers have indeterminate Reset values xxxx xxxx 2 Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3 PIDO values once the register is turned over to the SIE UOWN bit is set Once the registers have been under SIE control the values written for KEN INCDIS DTSEN and BSTALL are no longer valid 3 Prior to turning the buffer descriptor over to the SIE UOWN bit is cleared bits 5 through 2 of the BDNSTAT register are used to configure the KEN INCDIS DTSEN and BSTALL settings DS39632B page 176 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 5 USB Interrupts Figure 17 8 shows the interrupt logic for the USB a module There are two layers of in
63. 64 1 Error Calculated Baud Rate Desired Baud Rate Desired Baud Rate TABLE 20 2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented read as 0 Shaded cells are not used by the BRG 2004 Microchip Technology Inc Preliminary DS39632B page 237 PIC18F2455 2550 4455 4550 TABLE 20 3 BAUD RATES FOR ASYNCHRONOUS MODES SYNC 0 BRGH 0 BRG16 0 ape Fosc 40 000 MHz Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Eiror value Rate Error value Rate Eitor value K decimal K decimal K decimal K decimal 0 3 1 2 1 221 1 73 255 1 202 0 16 129 1201 0 16 103 2 4 2 441 1 73 255 2 404 0 16 129 2 404 0 16 64 2403 0 16 51 9 6 9 615 0 16 64 9 766 1 73 31 9 766 1 73 15 9615 0 16 12 19 2 19 531 1 73 31 19 531 1 73 15 19 531 1 73 57 6 56 818 1 36 10 62 500 8 51 4 52 0
64. 73 FSR2L Indirect Data Memory Address Pointer 2 Low Byte XXXX xxxx 52 73 STATUS N OV Z DC C x xxxx 52 71 TMR0H Timer0 Register High Byte 0000 0000 52 127 TMR0L Timer0 Register Low Byte XXXX xxxx 52 127 TOCON TMROON TOBBIT TOCS TOSE PSA TOPS2 TOPS1 TOPSO 1111 1111 52 125 Legend x unknown u unchanged unimplemented g value depends on condition Note 1 Bit21 of the TBLPTRU allows access to the device configuration bits 2 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as o 3 These registers and or bits are not implemented on 28 pin devices and are read as 0 Reset values are shown for 40 44 pin devices individual unimplemented bits should be interpreted as 4 RA6 is configured as a port pin based on various primary oscillator modes When the port pin is disabled all of the associated bits read o 5 RE is only available as a port pin when the MCLRE configuration bit is clear otherwise the bit reads as 0 6 RC5 and RCA are only available as port pins when the USB module is disabled UCON lt 3 gt 0 2004 Microchip Technology Inc Preliminary DS39632B page 67 PIC18F2455 2550 4455 4550 TABLE 5 2 REGISTER FILE SUMMARY PIC18F2455 2550 4455
65. ADCONO 3 Select A D acquisition time ADCON2 s 003h e Select A D conversion clock ADCON2 Argo i e Turn on A D module ADCON0 i 2 Configure A D interrupt if desired 001h Clear ADIF bit j i Set ADIE bit 000h l l m m m mm m m m a ca Set GIE bit A SAB a A Ao A ZN 3 Wait the required acquisition time if required GUS A Na g 4 Start conversion Nue Set GO DONE bit ADCONO register Analog Input Voltage FIGURE 21 3 ANALOG INPUT MODEL vpn Sampling L Switch S m aa se A VT 0 6V eed a Rs AN Ric lt ik SS Rss I AM XX AM e Gene ja ieee R VAIN ale ILEAKAGE ou SpE A VT 0 6V Gi 100 nA NR vss Legend CPIN Input Capacitance VT Threshold Voltage 6V ILEAKAGE Leakage Current at the pin due to VDD N af various junctions av 1 RIC Interconnect Resistance 2V SS Sampling Switch CHOLD Sample hold Capacitance from DAC 1 2 3 4 Rss Sampling Switch Resistance Sampling Switch kQ 2004 Microchip Technology Inc Preliminary DS39632B page 257 PIC18F2455 2550 4455 4550 21 1 A D Acquisition Requirements For the A D converter to meet its specified accuracy the charge holding capacitor CHOLD must be allowed to fully charge to the input channel voltage level The analog input model is shown in Figure 21 3 The source impedance Rs and the internal sampling switch Rss impedance directly affect
66. All other pin functions are disabled when ICSP or ICD operation is enabled 4 40 44 pin devices only TABLE 10 4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO 54 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATBO 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 54 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 INTCON2 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP 51 INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 51 ADCON1 VCFG1 VCFGO PCFG3 PCFG2 PCFG1 PCFGO 52 SPPCON SPPOWN SPPEN 55 SPPCFG CLKCFG1 CLKCFGO CSEN CLKIEN WS3 WS2 WS1 WS0 55 UCON PPBRST SEO PKTDIS USBEN RESUME SUSPND 55 Legend unimplemented read as 0 Shaded cells are not used by PORTB Note 1 These registers are unimplemented on 28 pin devices DS39632B page 116 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 10 3 PORTC TRISC and LATC Registers PORTC is a 7 bit wide bidirectional port The corre sponding data direction register is TRISC Setting a TRISC bit 1 will make the corresponding PORTC pin an input i e put the corresponding output driver in a high impedance mode Clearing a TRISC bit
67. Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 107 PIC18F2455 2550 4455 4550 9 6 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake up from Idle or Sleep modes RCON also contains the IPEN bit which enables interrupt priorities REGISTER 9 10 RCON RESET CONTROL REGISTER R W 0 R W 1 U 0 R W 1 R 1 R 1 R W 0 R W 0 IPEN SBOREN RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts PIC16CXXX Compatibility mode bit 6 SBOREN BOR Software Enable bit For details of bit operation see Register 4 1 bit 5 Unimplemented Read as 0 bit 4 RI RESET Instruction Flag bit For details of bit operation see Register 4 1 bit 3 TO Watchdog Time out Flag bit For details of bit operation see Register 4 1 bit 2 PD Power Down Detection Flag bit For details of bit operation see Register 4 1 bit 1 POR Power on Reset Status bit For details of bit operation see Register 4 1 bit 0 BOR Brown out Reset Status bit For details of bit operation see Register 4 1 Note Actual Reset values are determined by device configuration and the nature of the device Reset See Register 4 1 for additional information Legend R Readable bit W Writable bit U Unimplemente
68. FIGURE 25 5 CODE PROTECTED PROGRAM MEMORY FOR PIC18F2455 2550 4455 4550 MEMORY SIZE DEVICE Block Code Protection 24 Kbytes 32 Kbytes Address Controlled By PIC18F 2455 2555 PIC18F2550 4550 Range 000000h Boot Block Boot Block 0007FFh CPB WRTB EBTRB 000800h Block 0 Block 0 CPO WRTO EBTRO 001FFFh 002000h Block 1 Block 1 CP1 WRT1 EBTR1 003FFFh 004000h Block 2 Block 2 CP2 WRT2 EBTR2 OO5FFFh Unimplemented 0960008 A p ai Block 3 CP3 WRT3 EBTR3 okr 007FFFh 008000h Unimplemented Unimplemented Read o s Read 0s Unimplemented Memory Space 1FFFFFh TABLE 25 3 SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L cp3 1 CP2 CP1 CP0 300009 CONFIG5H CPD CPB 30000Ah CONFIG6L WRT3 WRT2 WRT1 WRTO 30000Bh CONFIG6H WRTD WRTB WRTC 30000Ch CONFIG7L EBTR3 EBTR2 EBTR1 EBTRO 30000Dh CONFIG7H EBTRB Legend Shaded cells are unimplemented Note 1 Unimplemented in PIC18FX455 devices maintain this bit set DS39632B page 296 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 25 5 1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions The device ID may be read with table reads The configuration registers may
69. GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 2 Note 3 cycles if skip and followed by a 2 word instruction Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process No register f Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE BTFSC FLAG 1 0 FALSE TRUE Before Instruction PC address HERE After Instruction If FLAG lt 1 gt PC address TRUE If FLAG lt 1 gt 1 PC address FALSE BTFSS Bit Test File Skip if Set Syntax BTFSS f b a Operands 0 lt f lt 255 0 lt b lt 7 ae 0 1 Operation skip if f lt b gt 1 Status Affected None Encoding 1010 bbba ffff FEEF Description If bit b in register f is 1 then the next instruction is skipped If bit b is 1 then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank is sele
70. INT2IE INT1IE INT2IF INT1IF bit 7 bit 0 INT2IP INT2 External Interrupt Priority bit 1 High priority 0 Low priority INT1IP INT1 External Interrupt Priority bit 1 High priority 0 Low priority Unimplemented Read as INT2IE INT2 External Interrupt Enable bit 1 Enables the INT2 external interrupt 0 Disables the INT2 external interrupt INT1IE INT1 External Interrupt Enable bit 1 Enables the INT1 external interrupt 0 Disables the INT1 external interrupt Unimplemented Read as INT2IF INT2 External Interrupt Flag bit 1 The INT2 external interrupt occurred must be cleared in software 0 The INT2 external interrupt did not occur INT1IF INT1 External Interrupt Flag bit 1 The INT1 external interrupt occurred must be cleared in software 0 The INT1 external interrupt did not occur Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared x Bit is unknown Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling 2004 Microchip Technology Inc Preliminary DS39632B page 101 PIC18F2455 2550 4455 4550 9 3 PIR Registers Note 1
71. INTOIE RBIE TMROIF INTOIF RBIF 51 EECON2 EEPROM Control Register 2 not a physical register 53 EECON1 EEPGD CFGS FREE WRERR WREN WR RD 53 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMRSIP CCP2IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54 Legend unimplemented read as o Shaded cells are not used during Flash EEPROM access 2004 Microchip Technology Inc Preliminary DS39632B page 87 PIC18F2455 2550 4455 4550 NOTES DS39632B page 88 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 7 0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array separate from the data RAM and program memory that is used for long term storage of program data It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers SFRs The EEPROM is readable and writable during normal operation over the entire VDD range Four SFRs are used to read and write to the data EEPROM as well as the program memory They are EECON1 e EECON2 EEDATA e EEADR The data EEPROM allows byte read and write When interfacing to the data memory block EEDATA holds the 8 bit data for read write and the EEADR register holds the address of the EEPROM location being accessed The EEPROM data memory is rated for high erase write cycle en
72. Interrupt flag bits are set when an interrupt The PIR registers contain the individual flag bits for the condition occurs regardless of the state of peripheral interrupts Due to the number of peripheral its corresponding enable bit or the Global interrupt sources there are two Peripheral Interrupt Interrupt Enable bit GIE INTCON lt 7 gt Request Flag registers PIR1 and PIR2 2 User software should ensure the appropri ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt REGISTER 9 4 PIR1 PERIPHERAL INTERRUPT REQUEST FLAG REGISTER 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R W 0 R W 0 R 0 R 0 R W 0 R W 0 R W 0 R W 0 SPPIFO ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF bit 7 bit 0 SPPIF Streaming Parallel Port Read Write Interrupt Flag bit 1 A read or a write operation has taken place must be cleared in software 0 No read or write has occurred Note 1 This bit is reserved on 28 pin devices always maintain this bit clear ADIF A D Converter Interrupt Flag bit 1 AnA D conversion completed must be cleared in software 0 The A D conversion is not complete RCIF EUSART Receive Interrupt Flag bit 1 The EUSART receive buffer RCREG is full cleared when RCREG is read 0 The EUSART receive buffer is empty TXIF EUSART Transmit Interrupt Flag bit 1 The EUSART transmit buffer TXREG is empty clea
73. Note The EEIF interrupt flag bit PIR2 lt 4 gt is set when the write is complete It must be cleared in software DS39632B page 80 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 6 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EECON1 DATA EEPROM CONTROL REGISTER 1 R W x R W x U 0 R W 0 R W x R W 0 R S 0 R S 0 EEPGD CFGS FREE WRERR WREN WR RD bit 7 bit 0 EEPGD Flash Program or Data EEPROM Memory Select bit 1 Access Flash program memory 0 Access data EEPROM memory CFGS Flash Program Data EEPROM or Configuration Select bit 1 Access configuration registers 0 Access Flash program or data EEPROM memory Unimplemented Read as 0 FREE Flash Row Erase Enable bit 1 Erase the program memory row addressed by TBLPTR on the next WR command cleared by completion of erase operation 0 Perform write only WRERR Flash Program Data EEPROM Error Flag bit 1 A write operation is prematurely terminated any Reset during self timed programming in normal operation or an improper write attempt 0 The write operation completed Note When a WRERR occurs the EEPGD and CFGS bits are not cleared This allows tracing of the error condition WREN Flash Program Data EEPROM Write Enable bit 1 Allows write cycles to Flash program data EEPROM 0 Inhibits write cycles to Flash program data EEPROM WR Write Control bit 1 Initiat
74. Note 1 66 ms 65 5 ms is the nominal Power up Timer PWRT delay 2 2msis the nominal time required for the PLL to lock 2004 Microchip Technology Inc Preliminary DS39632B page 47 PIC18F2455 2550 4455 4550 FIGURE 4 3 TIME OUT SEQUENCE ON POWER UP MCLR TIED TO Vpb Vpp RISE lt TPWRT VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET a TPWRT gt ma TOST m FIGURE 4 4 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO Vpp CASE 1 VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET TPWRT gt FIGURE 4 5 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED TO Vpb CASE 2 VDD MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET la TPWRT gt DS39632B page 48 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 4 6 SLOW RISE TIME MCLR TIED TO Vpp VoD RISE gt TPWRT FIGURE 4 7 TIME OUT SEQUENCE ON POR W PLL ENABLED MCLR TIED TO VDD EE auca rrn r 2004 Microchip Technology Inc Preliminary DS39632B page 49 PIC18F2455 2550 4455 4550 4 6 Reset State of Registers Most registers are unaffected by a Reset Their status is unknown on POR and unchanged by all other Resets The other registers are f
75. PC 001006h TOS address HERE 2 PCLATH 10h PCLATU 00h W 06h Description The contents of the source register are moved to destination register fy The actual address of the source register is determined by adding the 7 bit literal offset z in the first word to the value of FSR2 The address of the destination register is specified by the 12 bit literal fy in the second word Both addresses can be anywhere in the 4096 byte data space 000h to FFFh The MOVSF instruction cannot use the PCL TOSU TOSH or TOSL as the destination register If the resultant source address points to an indirect addressing register the value returned will be 00h Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode No No Write operation operation register f No dummy dest read Example MOVSF 05h REG2 Before Instruction FSR2 80h Contents of 85h 33h REG2 1th After Instruction FSR2 80h Contents of 85h 33h REG2 33h 2004 Microchip Technology Inc Preliminary DS39632B page 345 PIC18F2455 2550 4455 4550 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2 Decrement FSR2 Syntax MOVSS Zz Za Syntax PUSHL k Operands 0 lt 2z lt 127 Operands 0 lt k lt 255 0 lt Zg lt 127 Operation k FSR2 Operati
76. PWM Delay register ECCP1DEL which is loaded at either the duty cycle boundary or the boundary period whichever comes first Because of the buffering the module waits until the assigned timer resets instead of starting immediately This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle 4 Tosc As before the user must manually configure the appropriate TRIS bits for output 16 4 1 PWM PERIOD The PWM period is specified by writing to the PR2 register The PWM period can be calculated using the following equation EQUATION 16 1 PWM Period PR2 1 4 Tosc TMR2 Prescale Value PWM frequency is defined as 1 PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle e TMR2 is cleared The CCP1 pin is set if PWM duty cycle 0 the CCP1 pin will not be set e The PWM duty cycle is copied from CCPRIL into CCPRIH Note The Timer2 postscaler see Section 13 0 Timer2 Module is not used in the determination of the PWM frequency The postscaler could be used to have a servo update rate at a different freguency than the PWM output FIGURE 16 1 SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE Da da eas CCP1CON lt S
77. The microcontroller core owns the BD and its corresponding buffer DTS Data Toggle Synchronization bit 2 1 Data 1 packet o Data 0 packet KEN BD Keep Enable bit 1 USB will keep the BD indefinitely once UOWN is set required for SPP endpoint configuration 0 USB will hand back the BD once a token has been processed INCDIS Address Increment Disable bit 1 Address increment disabled required for SPP endpoint configuration 0 Address increment enabled DTSEN Data Toggle Synchronization Enable bit 1 Data toggle synchronization is enabled data packets with incorrect Sync value will be ignored o No data toggle synchronization is performed BSTALL Buffer Stall Enable bit 1 Buffer stall enabled STALL handshake issued if a token is received that would use the BD in the given location UOWN bit remains set BD value is unchanged 0 Buffer stall disabled BC9 BC8 Byte Count bits 9 and 8 The byte count bits represent the number of bytes that will be transmitted for an IN token or received during an OUT token Together with BC lt 7 0 gt the valid byte counts are 0 1023 Note 1 This bit must be initialized by the user to the desired value prior to enabling the USB module 2 This bit is ignored unless DTSEN 1 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Techno
78. UCFG lt 3 gt controls the transceiver it is enabled by default UTRDIS 0 The FSEN bit UCFG lt 2 gt controls the transceiver speed setting the bit enables full speed operation The on chip USB pull up resistors are controlled by the UPUEN bit UCFG lt 4 gt They can only be selected when the on chip transceiver is enabled The USB specification requires 3 3V operation for communications however the rest of the chip may be running at a higher voltage Thus the transceiver is supplied power from a separate source VUSB 17 2 2 2 External Transceiver This module provides support for use with an off chip transceiver The off chip transceiver is intended for applications where physical conditions dictate the loca tion of the transceiver to be away from the SIE For example applications that require isolation from the USB could use an external transceiver through some isolation to the microcontroller s SIE Figure 17 2 External transceiver operation is enabled by setting the UTRDIS bit FIGURE 17 2 TYPICAL EXTERNAL TRANSCEIVER WITH ISOLATION PIC VDD Isolated 3 3V Derived Microcontroller from USB from USB VDD VUSB 1 5 KQ ve Isolation Transceiver RCV lt lt lt D VMO fe S D Note The above setting shows a simplified schematic for a full speed configuration using an external transceiver with isolation 2004 Microchip Technology Inc Prelim
79. UIR SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 000 oooo 55 178 UFRMH FRM10 FRM9 FRM8 xxx 55 170 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRMO xxxx xxxx 55 170 SPPCON SPPOWN SPPEN oo 55 187 SPPEPS 3 RDSPP WRSPP SSPBUSY ADDR3 ADDR2 ADDR1 ADDRO 00 0 0000 55 191 SPPCFG CLKCFG1 CLKCFGO CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 55 188 SPPDATA DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATAO 0000 0000 55 192 Legend x unknown u unchanged unimplemented q value depends on condition Note 1 Bit 21 of the TBLPTRU allows access to the device configuration bits 2 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as o 3 These registers and or bits are not implemented on 28 pin devices and are read as 0 Reset values are shown for 40 44 pin devices individual unimplemented bits should be interpreted as 4 RAGis configured as a port pin based on various primary oscillator modes When the port pin is disabled all of the associated bits read o 5 RE is only available as a port pin when the MCLRE configuration bit is clear otherwise the bit reads as o 6 RC5 and RCA are only available as port pins when the USB module is disabled UCON lt 3 gt 0 DS39632B page 70 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 9 3 6 STATUS REGISTER The Status regist
80. application shutdown e Two Speed Start up This option allows the internal oscillator to serve as the clock source from Power on Reset or wake up from Sleep mode until the primary clock source is available 2004 Microchip Technology Inc Preliminary DS39632B page 7 PIC18F2455 2550 4455 4550 1 2 Other Special Features Memory Endurance The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase write cycles up to 100 000 for program memory and 1 000 000 for EEPROM Data retention without refresh is conservatively estimated to be greater than 40 years Self Programmability These devices can write to their own program memory spaces under internal software control By using a bootloader routine located in the protected Boot Block at the top of program memory it becomes possible to create an application that can update itself in the field e Extended Instruction Set The PIC18F2455 2550 4455 4550 family introduces an optional extension to the PIC 18 instruction set which adds 8 new instructions and an Indexed Literal Offset Addressing mode This extension enabled as a device configuration option has been specifically designed to optimize re entrant application code originally developed in high level languages such as C e Enhanced CCP Module In PWM mode this module provides 1 2 or 4 modulated outputs for controlling half bridge and full bridge driver
81. bit 7 6 Unimplemented Read as 0 bit 5 2 CHS3 CHSO Analog Channel Select bits 0000 Channel 0 ANO 0001 Channel 1 0010 Channel 2 AN2 0011 Channel 3 AN3 0100 Channel 4 0101 Channel 5 AN5 12 0110 Channel 6 AN6 2 0111 Channel 7 AN7 2 1000 Channel 8 AN8 1001 Channel 9 AN9 1010 Channel 10 AN10 1011 Channel 11 AN11 1100 Channel 12 AN12 1101 Unimplemented 1110 Unimplemented 1111 Unimplemented 2 Note 1 These channels are not implemented on 28 pin devices 2 Performing a conversion on unimplemented channels will return a floating input measurement bit 1 GO DONE A D Conversion Status bit When ADON 1 1 A D conversion in progress o A D Idle bit 0 ADON A D On bit 1 A D converter module is enabled 0 A D converter module is disabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 253 PIC18F2455 2550 4455 4550 REGISTER 21 2 ADCON1 A D CONTROL REGISTER 1 U 0 U 0 R W 0 Rw 0 RW 00 RAW RAO RW VCFG1 VCFGO PCFG3 PCFG2 PCFG1 PCFGO bit 7 bit 0 bit 7 6 Unimplemented Read as bit 5 VCFG1 Voltage Reference Configuration bit V
82. immediately after any POR event IF BOR is while POR is 1 it can be reliably assumed that a BOR event has occurred 4 4 3 DISABLING BOR IN SLEEP MODE When BOREN1 BORENO 10 the BOR remains under hardware control and operates as previously described Whenever the device enters Sleep mode however the BOR is automatically disabled When the device returns to any other operating mode BOR is automatically re enabled This mode allows for applications to recover from brown out situations while actively executing code when the device requires BOR protection the most At the same time it saves additional power in Sleep mode by eliminating the small incremental BOR current TABLE 4 1 BOR CONFIGURATIONS BOR Configuration Status of SBOREN BOREN1 BORENO RCON lt 6 gt BOR Operation 0 0 Unavailable BOR disabled must be enabled by reprogramming the configuration bits 0 1 Available BOR enabled in software operation controlled by SBOREN 1 0 Unavailable BOR enabled in hardware in Run and Idle modes disabled during Sleep mode 1 Unavailable BOR enabled in hardware must be disabled by reprogramming the configuration bits DS39632B page 46 Preliminary 2004 Microchip Technology lnc PIC18F2455 2550 4455 4550 4 5 Device Reset Timers PIC18F2455 2550 4455 4550 devices incorporate three separate on chip timers that help regulate the Power on Reset
83. is set 15 3 1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit Note Clearing the CCP2CON register will force the RB3 or RC1 compare output latch depending on device configuration to the default low level This is not the PORTB or PORTC I O data latch 15 3 2 TIMER1 TIMER3 MODE SELECTION Timer1 and or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature In Asynchronous Counter mode the compare operation may not work 15 3 3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen CCPxM3 CCPxMO 1010 the corresponding CCPx pin is not affected Only a CCP interrupt is generated if enabled and the CCPXIE bit is set 15 3 4 SPECIAL EVENT TRIGGER Both CCP modules are eguipped with a special event trigger This is an internal hardware signal generated in Compare mode to trigger actions by other modules The special event trigger is enabled by selecting the Compare Special Event Trigger mode CCPxM3 CCPxMO 1011 For either CCP module the special event trigger resets the timer register pair for whichever timer resource is currently assigned as the module s time base This allows the CCPRx registers to serve as a programmable period register for either timer The special event trigger for CCP2 can also start an A D conversion In order to do this the A D converter
84. might refer to the control register for CCP1 CCP2 or ECCP1 CCPxCON is used throughout these sections to refer to the module control register regardless of whether the CCP module is a standard or Enhanced implementation CCPxCON STANDARD CCP CONTROL REGISTER U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 0 0 DCxB1 DCxBO CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7 6 Unimplemented Read as 0 Note 1 These bits are not implemented on 28 pin devices and are read as 0 bit 5 4 DCxB1 DCxBO PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode Unused Compare mode Unused PWM mode These bits are the two LSbs bit 1 and bit 0 of the 10 bit PWM duty cycle The eight MSbs DCx9 DCx2 of the duty cycle are found in CCPRxL bit 3 0 CCPxM3 CCPxMO CCP Module x Mode Select bits 0000 Capture Compare PWM disabled resets CCP module 0001 Reserved 0010 Compare mode toggle output on match CCPIF bit is set 0011 Reserved 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edge 0111 Capture mode every 16th rising edge 1000 Compare mode initialize CCP pin low on compare match force CCP pin high CCPIF bit is set 1001 Compare mode initialize CCP pin high on compare match force CCP pin low CCPIF bit is set 1010 Compare mode generate software interrupt on compare
85. must already be enabled FIGURE 15 2 COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Ti 1 Ti R CCPRIH CCPRIL Set GER Timer1 Timer3 Reset CCP1 pin v Compare Output Q Comparator 7 Match Logic R i TRIS 4 Output Enable CCP1CON lt 3 0 gt 0 TMR1H TMR1L o 1 TMR3H TMR3L 1 Special Event Trigger Timer1 Timer3 Reset A D Trigger T3CCP1 T3CCP2 Set CCP2IF CCP2 pin gt gt Q Comparator Compare gt ee il A TRIS CCPR2H CCPR2L 4 Output Enable CCP2CON lt 3 0 gt DS39632B page 144 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 15 3 REGISTERS ASSOCIATED WITH CAPTURE COMPARE TIMER1 AND TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 RCON IPEN SBOREN RI TO PD POR BOR 52 PIR SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRI1IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BC
86. occur A maximum source impedance of 10 kQ is recommended for the analog sources Any external component connected to an analog input pin such as a capacitor or a Zener diode should have very little leakage current FIGURE 22 4 COMPARATOR ANALOG INPUT MODEL VDD Rs lt 10k AVT SON Ric AAA MN p gt Comparator i AIN Input ILEAKAGE SpF T AVT 0 6V 1 500 nA a COTE UE SA Vss Legend CPIN Input Capacitance VT Threshold Voltage ILEAKAGE Leakage Current at the pin due to various junctions RIC Interconnect Resistance Rs Source Impedance VA Analog Voltage TABLE 22 1 REGISTERS ASSOCIATED WITH COMPARATOR MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 53 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVRO 53 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 PORTA RAG RA5 RA4 RA3 RA2 RA1 RAO 54 LATA LATA6 1 LATA5 LATA4 LATA3 LATA2 LATA1 LATAO 54 TRISA TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 54 Legend unimplemented read as 0 Shaded cells are unused by the comparator modu
87. other Reset Comparator 22 6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator Software will need to maintain information about the status of the output bits as read from CMCON lt 7 6 gt to determine the actual change that occurred The CMIF bit PIR2 lt 6 gt is the Comparator Interrupt Flag The CMIF bit must be reset by clearing it Since it is also possible to write a 1 to this register a simulated interrupt may be initiated Both the CMIE bit PIE2 lt 6 gt and the PEIE bit INTCON lt 6 gt must be set to enable the interrupt In addition the GIE bit INTCON lt 7 gt must also be set If any of these bits are clear the interrupt is not enabled though the CMIF bit will still be set if an interrupt condition occurs Note If a change in the CMCON register C1OUT or C2OUT should occur when a read operation is being executed start of the Q2 cycle then the CMIF PIR registers interrupt flag may not get set The user in the Interrupt Service Routine can clear the interrupt in the following manner a Any read or write of CMCON will end the mismatch condition b Clear flag bit CMIF A mismatch condition will continue to set flag bit CMIF Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared 22 7 Comparator Operation During Sleep When a comparator is active and the
88. specifications are violated t Data in Typ column is at 5 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 These specifications are for programming the on chip program memory through the use of table write instructions 2 Refer to Section 7 7 Using the Data EEPROM for a more detailed discussion on data EEPROM endurance 3 Required only if Single Supply Programming is disabled DS39632B page 370 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 28 2 COMPARATOR SPECIFICATIONS Operating Conditions 3 0V lt VDD lt 5 5V 40 C lt TA lt 85 C unless otherwise stated Param No Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage 5 0 10 mV D301 VICM Input Common Mode Voltage 0 VpD 15 V D302 CMRR Common Mode Rejection Ratio 55 dB 300 TRESP Response Time TABLE 28 3 VOLTAGE REFERENCE SPECIFICATIONS 2004 Microchip Technology Inc Preliminary DS39632B page 371 PIC18F2455 2550 4455 4550 TABLE 28 4 USB MODULE SPECIFICATIONS Operating Conditions 40 C lt TA lt 85 C unless otherwise stated a Sym Characteristic Min Typ Max Units Comments D313 VUSB USB Voltage 3 0 3 6 V Voltage on bus must be in this range for proper USB operation D314 HL Input Leakage on pin 1 uA Vss lt VP
89. the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details 1 1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example SWAPF REG 1 0 Before Instruction REG 53h After Instruction REG 35h DS39632B page 338 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TBLRD Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Qi Table Read TBLRD None if TBLRD Prog Mem TBLPTR TABLAT TBLPTR No Change if TBLRD Prog Mem TBLPTR gt TABLAT TBLPTR 1 TBLPTR if TBLRD Prog Mem TBLPTR gt TABLAT TBLPTR 1 gt TBLPTR if TBLRD TBLPTR 1 gt TBLPTR Prog Mem TBLPTR TABLAT None 0000 0000 0000 This instruction is used to read the contents of Program Memory P M To address the program memory a pointer called Table Pointer TBLPTR is used The TBLPTR a 21 bit pointer points to each byte in the program memory TBLPTR has a 2 Mbyte address range TBLPTRI0 o TBLPTRI0
90. the inter rupt generated will wake the chip from the low power mode If the global interrupt is enabled the program will branch to the interrupt vector To set up a Synchronous Slave Reception 1 Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 To enable reception set enable bit CREN Flag bit RCIF will be set when reception is complete An interrupt will be generated if enable bit RCIE was set 6 Read the RCSTA register to get the ninth bit if enabled and determine if any error occurred during reception 7 Read the 8 bit received data by reading the RCREG register 8 If any error occurred clear the error by clearing bit CREN 9 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set OVP TABLE 20 10 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receiv
91. 0 16 25 9 6 9 615 0 16 25 9615 0 16 12 19 2 19 231 0 16 12 57 6 62 500 8 51 3 115 2 125 000 8 51 1 SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 ATE Fosc 40 000 MHz Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal K decimal 0 3 0 300 0 00 33332 0 300 0 00 16665 0 300 0 00 8332 300 0 01 6665 1 2 1 200 0 00 8332 1 200 0 02 4165 1 200 0 02 2082 1200 0 04 1665 2 4 2 400 0 02 4165 2 400 0 02 2082 2 402 0 06 1040 2400 0 04 832 9 6 9 606 0 06 1040 9 596 0 03 520 9 615 0 16 259 9615 0 16 207 19 2 19 193 0 03 520 19 231 0 16 259 19 231 0 16 129 19230 0 16 103 57 6 57 803 0 35 172 57 471 0 22 86 58 140 0 94 42 57142 0 79 34 115 2 114 943 0 22 86 116 279 0 94 42 113 636 1 36 21 117647 2 12 16 SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 HATE Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Rate Eitor value Rate Erot value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 01 3332 300 0 04 1665 300 0 04 832 1 2 1 200 0 04 832 1201 0 16 415 1201 0 16 207 2 4 2 404 0 16 415 2403 0 16 207 2403 0 16 103 9 6 9 615 0 16 103 9615 0 16 51 9615 0 16 25 19 2 19 231 0 16 51 19230 0 16 25 19230 0 16 12 57 6 58 824 2 12 16 55555 3 55 8 115 2 111 111 3 55 8
92. 0 R W 0 R W 0 R 1 R W 0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC Clock Source Select bit Asynchronous mode Don t care Synchronous mode 1 Master mode clock generated internally from BRG 0 Slave mode clock from external source bit 6 TX9 9 bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission bit 5 TXEN Transmit Enable bit 1 Transmit enabled 0 Transmit disabled Note SREN CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode bit 4 SYNC EUSART Mode Select bit 1 Synchronous mode 0 Asynchronous mode bit 3 SENDB Send Break Character bit Asynchronous mode 1 Send Sync Break on next transmission cleared by hardware upon completion 0 Sync Break transmission completed Synchronous mode Don t care bit 2 BRGH High Baud Rate Select bit Asynchronous mode 1 High speed 0 Low speed Synchronous mode Unused in this mode bit 1 TRMT Transmit Shift Register Status bit 1 TSR empty 0 TSR full bit 0 TX9D Ninth bit of Transmit Data DS39632B page 234 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 20 2 RCSTA RECEIVE STATUS AND CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R 0 R x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN 2004 Microchip Technology Inc Preliminary DS39632B page 235 PIC18F2455 2550 4455 4550
93. 0 gt data output not affected by analog input INTO FLTO 1 IN TTL PORTB lt 0 gt data input weak pull up when RBPU bit is cleared SDI SDA Disabled when analog input enabled AN12 1 IN ANA _ A D input channel 1201 INTO 1 IN ST External Interrupt 0 input FLTO 1 IN ST Enhanced PWM Fault input ECCP1 module enabled in software SDI 1 IN ST SPI data input MSSP module SDA 1 OUT DIG PCTV data output MSSP module takes priority over port data 1 IN I C SMB C data input MSSP module input type depends on module setting RB1 AN10 RB1 0 OUT DIG LATB lt 1 gt data output not affected by analog input INT1 SCK 1 IN TTL PORTB lt 1 gt data input weak pull up when RBPU bit is cleared SCL Disabled when analog input enabled AN10 1 IN ANA A D input channel 10 INT1 1 IN ST External interrupt 1 input SCK 0 OUT DIG SPI clock output MSSP module takes priority over port data 1 IN ST SPI clock input MSSP module SOL 0 OUT DIG C clock output MSSP module takes priority over port data 1 IN 2C SMB I2C clock input MSSP module input type depends on module setting RB2 AN8 RB2 0 OUT DIG LATB lt 2 gt data output not affected by analog input INT2 VMO 1 IN TTL PORTB lt 2 gt data input weak pull up when RBPU bit is cleared Disabled when analog input enabled AN8 1 IN ANA _ A D input channel 8 INT2 IN ST External Interrupt 2 input VMO 0 OUT DIG External USB transceiver VMO data output RB3 AN9 RB3 0
94. 000 XT HS EC ECIO None 00 4 MHz 2 01 2 MHz 3 10 1 33 MHz 4 11 1 MHz HSPLL ECPLL XTPLL 2 00 48 MHz ECPIO 3 01 32 MHz 4 10 24 MHz 6 11 16 MHz Legend All clock frequencies except 24 MHz are exclusively associated with full speed USB operation USB clock of 48 MHz Bold is used to highlight clock selections that are compatible with low speed USB operation system clock of 24 MHz USB clock of 6 MHz Note 1 Only valid when the USBDIV configuration bit is cleared DS39632B page 30 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 2 4 Clock Sources and Oscillator Switching Like previous PIC18 enhanced devices the PIC18F2455 2550 4455 4550 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low freguency clock source PIC18F2455 2550 4455 4550 devices offer two alternate clock sources When an alternate clock source is enabled the various power managed operating modes are available Essentially there are three clock sources for these devices Primary oscillators Secondary oscillators e Internal oscillator block The primary oscillators include the External Crystal and Resonator modes the External Clock modes and the internal oscillator block The particular mode is defined by the FOSC3 FOSCO configuration bits The details of these modes are covered earlier in this chapter The secondary oscill
95. 1 RCIF bit i Interrupt i Read I RCREG SPBRG XXXXh D I 1Ch SPBRGH XXXXh y 00h Note The ABD seguence reguires the EUSART module to be configured in Asynchronous mode and WUE 0 FIGURE 20 2 BRG OVERFLOW SEGUENCE OLI MALL z s 2004 Microchip Technology Inc Preliminary DS39632B page 241 PIC18F2455 2550 4455 4550 20 2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit TXSTA lt 4 gt In this mode the EUSART uses the standard Non Return to Zero NRZ format one Start bit eight or nine data bits and one Stop bit The most common data format is eight bits An on chip dedicated 8 bit 16 bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator The EUSART transmits and receives the LSb first The EUSART s transmitter and receiver are functionally independent but use the same data format and baud rate The Baud Rate Generator produces a clock either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits TXSTA lt 2 gt and BAUDCON lt 3 gt Parity is not supported by the hardware but can be implemented in software and stored as the ninth data bit When operating in Asynchronous mode the EUSART module consists of the following importa
96. 111 1111 uuu uuuu PIR1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuul 2455 2550 4455 4550 000 0000 000 0000 uuu uuuu PIE1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu 2455 2550 4455 4550 000 0000 000 0000 uuu uuuu OSCTUNE 2455 2550 4455 4550 0 0 0000 0 0 0000 u u uuuu TRISE 2455 2550 4455 4550 111 111 uuuu uuu TRISD 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu TRISC 2455 2550 4455 4550 11 111 11 111 uu uuu TRISB 245b 2550 4455 4550 PALE T QE TILL 1111 uuuu uuuu TRISA 2455 2550 4455 4550 111 11110 111 11116 uuu uuu LATE 2455 2550 4455 4550 XXX uuu uuu LATD 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu LATG 2455 2550 4455 4550 XX XXX uu uuu uu uuu LATB 245b 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu LATA 2455 2550 4455 4550 xxx xxxx uuu uuu uuu uuu PORTE 2455 2550 4455 4550 0 x000 0 x000 u uuuu PORTD 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu PORTG 2455 2550 4455 4550 XXXX XXX uuuu uuu uuuu uuu PORTB 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu PORTA 2455 2550 4455 4550 x0x 0000 udu 00000 uuu uuu Legend u unchanged x unknown unimplemented bit read as 0 g value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 When the wake up is du
97. 2004 Microchip Technology Inc Preliminary DS39632B page 283 PIC18F2455 2550 4455 4550 REGISTER 25 4 CONFIG2H CONFIGURATION REGISTER 2 HIGH BYTE ADDRESS 300003h U 0 U 0 U 0 R P 1 R P 1 R P 1 R P 1 R P 1 WDTPS3 WDTPS2 WDTPS1 WDTPSO WDTEN bit 7 bit 0 bit 7 5 Unimplemented Read as 0 bit 4 1 WDTPS3 WDTPSO Watchdog Timer Postscale Select bits 1111 1 32 768 1110 1 16 384 1101 1 8 192 1100 1 4 096 1011 1 2 048 1010 1 1 024 1001 1 512 1000 1 256 0111 1 128 0110 1 64 0101 1 32 0100 1 16 0011 1 8 0010 1 4 0001 1 2 0000 1 1 bit 0 WDTEN Watchdog Timer Enable bit 1 WDT enabled 0 WDT disabled control is placed on the SWDTEN bit Legend R Readable bit P Programmable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state DS39632B page 284 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 25 5 CONFIG3H CONFIGURATION REGISTER 3 HIGH BYTE ADDRESS 300005h R P 1 U 0 U 0 U 0 U 0 R P 0 R P 1 R P 1 MCLRE LPTIOSC PBADEN CCP2MX bit 7 bit 0 bit 7 MCLRE MCLR Pin Enable bit 1 MCLR pin enabled RE3 input pin disabled 0 RE3 input pin enabled MCLR disabled bit 6 3 Unimplemented Read as 0 bit 2 LPT10SC Low Power Timer 1 Oscillator Enable bit 1 Timer1 configured for low power operation 0 Timer1 configured for h
98. 243 Asynchronous Transmission Back to Back 243 Automatic Baud Rate Calculation 241 Auto Wake up Bit WUE During Normal Operation 246 Auto Wake up Bit WUE During Sleep 246 Baud Rate Generator with Clock Arbitration pana ia nl nn l 220 BRG Overflow Sequence 241 BRG Reset Due to SDA Arbitration During Start Condition 229 Brown out Reset BOR 1 379 Bus Collision During a Repeated Start Condition Case 1 230 Bus Collision During a Repeated Start Condition Case 2 230 Bus Collision During a Start Condition SCL 0 229 Bus Collision During a Start Condition SDA only 228 Bus Collision During a Stop Condition Case 1 231 Bus Collision During a Stop Condition Case 2 231 Bus Collision for Transmit and Acknowledge 227 Capture Compare PWM CCP 381 GEKO and VO rizoto 378 Clock Synchronization F Clock Instruction Cycle a 61 EUSART Synchronous Receive Master Slave
99. 3 f lt b gt Status Affected None Encoding 1000 bbba ffff ffff Description Bit b in register f is set If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity 01 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example BSF FLAG_REG 7 1 Before Instruction FLAG REG 0Ah After Instruction FLAG REG 8Ah 2004 Microchip Technology Inc Preliminary DS39632B page 313 PIC18F2455 2550 4455 4550 BTFSC Bit Test File Skip if Clear Syntax BTFSC f b a Operands 0 lt f lt 255 O0 lt b lt 7 ae 0 1 Operation skip if f lt b gt 0 Status Affected None Encoding 1011 bbba F CE ffff Description If bit b in register f is o then the next instruction is skipped If bit b is o then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the
100. 4 gt While in Slave mode the external clock is supplied by the external clock source on the SCK pin This external clock must meet the minimum high and low times as specified in the electrical specifications While in Sleep mode the slave can transmit receive data When a byte is received the device will wake up from Sleep 19 3 7 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode The SPI must be in Slave mode with SS pin control enabled SSPCON1 lt 3 0 gt 04h The pin must not be driven low for the SS pin to function as an input The data latch FIGURE 19 4 must be high When the SS pin is low transmission and reception are enabled and the SDO pin is driven When the SS pin goes high the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output External pull up pull down resistors may be desirable depending on the application Note 1 When the SPI module is in Slave mode with SS pin control enabled SSPCON1 lt 3 0 gt 0100 the SPI module will reset if the SS pin is set to VDD 2 If the SPI is used in Slave mode with CKE set then the SS pin control must be enabled When the SPI module resets the bit counter is forced to 0 This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit To emulate two wire communication the SDO pin can be connected to the SDI pin When the SPI module needs
101. 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial fl Symbol Characteristic Min Typ Max Units Conditions D001 VDD Supply Voltage 2 0 55 V EC HS XT and Internal Oscillator modes 3 0 55 V HSPLL XTPLL ECPIO and ECPLL modes D002 VDR RAM Data Retention 1 5 V Voltage D003 VPOR VDD Start Voltage 0 7 V See Section 4 3 Power on Reset POR to ensure internal Power on for details Reset signal D004 SVDD Vpp Rise Rate 0 05 V ms See Section 4 3 Power on Reset POR to ensure internal Power on for details Reset signal D005 VBOR Brown out Reset Voltage BORV1 BORVO 11 2 00 2 05 2 16 V BORV1 BORVO 10 2 65 2 79 2 93 V BORV1 BORVO 01 4 11 4 33 455 V BORV1 BORVO 00 4 36 4 59 4 82 V Legend Shading of rows is to assist in readability of the table Note 1 This is the limit to which VDD can be lowered in Sleep mode or during a device Reset without losing RAM data 2004 Microchip Technology Inc Preliminary DS39632B page 359 PIC18F2455 2550 4455 4550 28 2 DC Characteristics Power Down and Supply Current PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless o
102. 4550 CONTINUED File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bito POR BOB prin OSCCON IDLEN IRCF2 IRCF1 IRCFO OSTS IOFS SCS1 SCS0 0100 g000 52 32 HLVDCON VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDLO 0 00 0101 52 273 WDTCON SWDTEN o 52 292 RCON IPEN SBOREN RI TO PD POR BOR 0g 1 11g0 52 44 TMRIH Timer1 Register High Byte XXXX xxxx 52 133 TMRIL Timer1 Register Low Byte XXXX xxxx 52 133 T1CON RD16 TIRUN TICKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMRION 0000 0000 52 129 TMR2 Timer2 Register 0000 0000 52 136 PR2 Timer2 Period Register 1111 1111 52 136 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPSO TMR2ON T2CKPS1 T2CKPSO 000 0000 52 135 SSPBUF SSP Receive Buffer Transmit Register XXXX XXXX ja SSPADD SSP Address Register in CTM Slave Mode SSP Baud Rate Reload Register in IC Master Mode 0000 0000 52 202 SSPSTAT SMP CKE D A P S RW UA BF 0000 0000 52 194 203 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 0000 0000 set SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 52 205 ADRESH A D Result Register High Byte XXXX XXXX 52 262 ADRESL A D Result Register Low Byte XXXX xxxx 52 262 ADCONO CHS3 CHS2 CHS1 CHS0 GO DONE ADON 00 0000 52 253 ADCON1 VCFG1 VCFGO PCFG3 PCFG2 PCFG1 PCFGO 00 Oggg 52 254 ADCON2 ADFM ACQT2 ACQT1 ACQTO ADCS2 ADCS1 ADCSO 0 00 0000 52 255 CCPRIH Capture Compare PWM Register 1 High Byte X
103. 7 0 Before Instruction FLAG REG C7h After Instruction FLAG REG 47h BN Branch if Negative Syntax BN n Operands 128 lt n lt 127 Operation if Negative bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0110 nnnn nnnn Description If the Negative bit is 1 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BN Jump Before Instruction PC After Instruction If Negative PC If Negative PC address HERE 1 address Jump address HERE 2 DS39632B page 310 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 BNC Branch if Not Carry BNN Branch if Not Negative Syntax BNC n Syntax BNN n Operands 128 lt n lt 127 Operands 128 lt n lt 127 Operation if Carry bit is 0 Operation if Negative bit is o PC 2 2n PC PC 2 2n gt PC
104. 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example 1 SUBWF REG 1 0 Before Instruction 3 W 2 C a After Instruction REG 1 W 2 C 1 result is positive Z 0 N 0 Example 2 SUBWF REG 0 0 Before Instruction 2 W 2 C 2 After Instruction REG 2 w 0 C 1 result is zero Z 1 N 0 Example 3 SUBWF REG 1 0 Before Instruction REG 1 W 2 C After Instruction REG FFh 2 s complement W C result is negative Z 0 N 1 2004 Microchip Technology Inc Preliminary DS39632B page 337 PIC18F2455 2550 4455 4550 SUBWFB Subtract W from f with Borrow Syntax SUBWFB f d a Operands 0 lt f lt 255 de 0 1 a e 0 1 Operation f W C dest Status Affected N OV C DC Z Encoding 0101 10da FEFE EEFE Description Subtract W and the Carry flag borrow from register f 2 s complement method If is 0 the result is stored in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction opera
105. ASIA PACIFIC India Bangalore Tel 91 80 2229 0061 Fax 91 80 2229 0062 India New Delhi Tel 91 11 5160 8631 Fax 91 11 5160 8632 Japan Kanagawa Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Taiwan Hsinchu Tel 886 3 572 9526 Fax 886 3 572 6459 EUROPE Austria Weis Tel 43 7242 2244 399 Fax 43 7242 2244 393 Denmark Ballerup Tel 45 4450 2828 Fax 45 4485 2829 France Massy Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Ismaning Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 England Berkshire Tel 44 118 921 5869 Fax 44 118 921 5820 10 20 04 Preliminary DS39632B page 424 2004 Microchip Technology Inc
106. Blockn whenever WRTn 0 2004 Microchip Technology Inc Preliminary DS39632B page 297 PIC18F2455 2550 4455 4550 FIGURE 25 7 EXTERNAL BLOCK TABLE READ EBTRn DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB EBTRB 11 0007FFh 000800h TBLPTR 0008FFh WRTO EBTRO 10 001FFFh 002000h WRT1 EBTRI 11 PC 003FFEh TBLRD 003FFFh 004000h WRT2 EBTR2 11 OO5FFFh 006000h WRT3 EBTR3 11 007FFFh Results All table reads from external blocks to Blockn are disabled whenever EBTRn 0 TABLAT register returns a value of 0 FIGURE 25 8 EXTERNAL BLOCK TABLE READ EBTRn ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB EBTRB 11 0007FFh TBLPTR 0008FFh 000800h WRTO EBTRO 10 PC 001FFEh TBLRD 001FFFh 002000h WRT1 EBTR1 11 003FFFh 004000h WRT2 EBTR2 11 OO5FFFh 006000h WRT3 EBTR3 11 007FFFh Results Table reads permitted within Blockn even when EBTRBn o TABLAT register returns the value of the data at the location TBLPTR DS39632B page 298 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 25 5 2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits CPD and WRTD CPD inhibits external reads and writes of data EEPROM WRTD inhibits internal and external wr
107. Characteristics 373 Current Consumption Effects of a Reset a Operation usa aterioi iee atiis During Sleep SOUP soeh in nari A a A ia stari up TIME vcs cevs aa Typical Application a HLVD See High Low Voltage Detect l I O POVSTANIA 111 IC Mode MSSP Acknowledge Sequence Timing 226 Associated Registers 232 Baud Rate Generator 219 Bus Collision During a Repeated Start Condition 230 During a Stop Condition 231 Clock Arbitration Clock Stretching 10 Bit Slave Receive Mode SEN 1 212 10 Bit Slave Transmit Mode 7 Bit Slave Receive Mode SEN 1 212 7 Bit Slave Transmit Mode Clock Synchronization and the CKP Bit Effect of a Reset ss General Call Address Support C Clock Rate w BRG Master Mode Operation Reception Repeated Start Condition Timing Start Condition Timing 221 Transmission taii hae a ea aie 223 Transmit Sequence 218 Multi Master Communication Bus
108. Collision and Arbitration Multi Master Mode sssssesseeseesseessreesresrrnsrrnsernes Operation isidin Read Write Bit Information RAN Bit IROGISLCIS a ae an a Serial Clock RB1 AN10 INT1 SCK SCL 207 Slave Mode nan eae 206 Addressing s uama T sayaa sn ri 206 Reception TransMISSION u nn kasna r Sleep Operation sssssssseessessrerressrernsrnerrneenereneensrnernn Stop Condition Timing ID LOCAUONS u u yy rires Idle Modes sise INGE INCFSZ In Circuit Debugger In Circuit Serial Programming ICSP 279 299 Indexed Literal Offset Addressing and Standard PIC18 Instructions 348 Indexed Literal Offset Mode 75 77 348 Indirect Addressing ray Ae INESNZ es a ae S eee Mat al dn Aah ste 323 Initialization Conditions for all Registers 51 55 Instruction Cycle c scccsseccccessecesseceisecuecetseetestqueceestsetservesssbess 61 Clocking Scheme fs Flow Pipeli ing a 61 Instruction Format a 303 ADDWF Indexed Literal Offset mode os ADDWE GS Sa Regie late A ed ih cae ler DECFSZ aga GOTO A H S ING Pec ities aan a osha a ahs ana ayu ocd INCFSZ x INESNZ op O asas aiassa DS39632B page 412 Preliminary 2004 Microchip Technology Inc PIC
109. Effects of a Reset J s asa LAI Qua Interrupts a OPETAN id O TV Operation During Sleep 266 Outputs 265 Reference 265 External Signal 265 Internal Signal 265 Response Time 265 Comparator Specifications 151 371 Comparator Voltage Reference 269 Accuracy and Error 270 Associated Registers 271 CONPIQUIING asas na dn 269 Connection Considerations 270 Effects of a Reset A Operation During Sleep a a 270 Compare CCP Module a Associated Registers CCPRx Register Pin Configuration Software Interrupt Special Event Trigger Timer1 Timer3 Mode Selection 144 Compare ECCP Module ss Special Event Trigger a Configuration Bits a Configuration Register Protection Context Saving During Interrupts Conversion Considerations CPFSEQ CPFSGT CPFSLT Crystal Oscillator Ceramic Resonator 25 D Data Addressing Modes 72 Comparing Addressing Modes with the Extended Instruction Set Enabled 76 Direct ke Indexe
110. FIGURE 3 4 TRANSITION TIMING FROM RC RUN MODE TO PRI RUN MODE at Q a O4 plno 02 08 04 Q1 Q2 os BE Ng eae OSC NN UNE FL IMUUUUI TosT gt TPL is Ty Ay aie i 12 1 i D Bers x ROOMS Glock 10 0 NE DS CPU Clock j K Trans Mon s AA j v AY FRA m V a N Program PC X PC 2 X PC 4 SCS1 SCS0 bits Changed OSTS bit Set Note 1 Tost 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 2 4 Tosc DS39632B page 38 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 3 3 The Power Managed Sleep mode in the PIC18F2455 2550 4455 4550 devices is identical to the legacy Sleep mode offered in all other PICmicro devices It is entered by clearing the IDLEN bit the default state on device Reset and executing the SLEEP instruction This shuts down the selected oscillator Figure 3 5 All clock source status bits are cleared Sleep Mode Entering the Sleep mode from any other mode does not reguire a clock switch This is because no clocks are needed once the controller has entered Sleep If the WDT is selected the INTRC source will continue to operate If the Timer1 oscillator is enabled it will also continue to run When awake event occurs in Sleep mode by interrupt Reset or WDT time out the device will not be clocked until the clock source selected by the SCS1 SC SO bit
111. HIGH BYTE ADDRESS 300001h R P 0 R P 0 U 0 U 0 R P 0 R P 1 R P 0 R P 1 IESO FCMEN FOSC3 FOSC2 FOSC1 FOSCO bit 7 bit 0 IESO Internal External Oscillator Switchover bit 1 Oscillator Switchover mode enabled 0 Oscillator Switchover mode disabled FCMEN Fail Safe Clock Monitor Enable bit 1 Fail Safe Clock Monitor enabled 0 Fail Safe Clock Monitor disabled Unimplemented Read as FOSC3 FOSCO Oscillator Selection bits 111x HS oscillator PLL enabled HSPLL 110x HS oscillator HS 1011 Internal oscillator HS oscillator used by USB INTHS 1010 Internal oscillator XT used by USB INTXT 1001 Internal oscillator CLKO function on RA6 EC used by USB INTCKO 1000 Internal oscillator port function on RA6 EC used by USB INTIO 0111 EC oscillator PLL enabled CLKO function on RA6 ECPLL 0110 EC oscillator PLL enabled port function on RA6 ECPIO 0101 EC oscillator CLKO function on RA6 EC 0100 EC oscillator port function on RA6 ECIO 001x XT oscillator PLL enabled XTPLL 000x XT oscillator XT Note 1 The microcontroller and USB module both use the selected oscillator as their clock source in XT HS and EC modes The USB module uses the indicated XT HS or EC oscillator as its clock source whenever the microcontroller uses the internal oscillator block Legend R Readable bit P Programmable bit U Unimplemented bit read as n Value when device is
112. I I I 1 1 Reverse Mode s Period S Duty Cycle PIA I I P1B I I I I I P1c 2 I I l l P1D I I I Note 1 At this time the TMR2 register is equal to the PR2 register 2004 Microchip Technology Inc Preliminary DS39632B page 155 PIC18F2455 2550 4455 4550 FIGURE 16 7 EXAMPLE OF FULL BRIDGE APPLICATION V PIC18FX455 X550 FET QA QC FET Driver Driver PIA le x D P1B Load FET FET Driver Driver y r PH P1C ob ap V P1D 16 4 5 1 Direction Change in Full Bridge Mode Figure 16 9 shows an example where the PWM direc In the Full Bridge Output mode the P1M1 bit in the CCP1CON register allows the user to control the forward reverse direction When the application firm ware changes this direction control bit the module will assume the new direction on the next PWM cycle Just before the end of the current PWM period the modulated outputs P1B and P1D are placed in their inactive state while the unmodulated outputs PIA and P1C are switched to drive in the opposite direction This occurs in a time interval of 4 Tosc Timer2 Prescale Value before the next PWM period begins The Timer2 prescaler will be either 1 4 or 16 depending on the value of the T2CKPS1 T2CKPSO bits T2CON lt 1 0 gt During the interval from t
113. I O RB1 AN10 INT1 SCK 34 10 9 SCL RB1 VO TTL Digital I O AN10 I Analog Analog input 10 INT1 ST External interrupt 1 SCK O ST Synchronous serial clock input output for SPI mode SCL O ST Synchronous serial clock input output for C mode RB2 AN8 INT2 VMO 35 11 10 RB2 VO TTL Digital I O AN8 I Analog Analog input 8 INT2 ST External interrupt 2 VMO O External USB transceiver VMO output RB3 O TTL Digital I O AN9 I Analog Analog input 9 ccp21 O ST Capture 2 input Compare 2 output PWM 2 output VPO O External USB transceiver VPO output RB4 VO TTL Digital I O AN11 Analog Analog input 11 KBIO TTL Interrupt on change pin CSSPP O SPP chip select control output RB5 KBI1 P GM 38 15 15 RB5 VO TTL Digital I O KBI1 TTL Interrupt on change pin PGM O ST Low Voltage ICSP Programming enable pin RB6 KBI2 PGC 39 16 16 RB6 VO TTL Digital I O KBI2 TTL Interrupt on change pin PGC O ST In Circuit Debugger and ICSP programming clock pin RB7 KBI3 PGD 40 17 17 RB7 VO TTL Digital I O KBI3 TTL Interrupt on change pin PGD O ST In Circuit Debugger and ICSP programming data pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared 2 Default assignment for CCP2 when CCP2MX config
114. ICRST ICVPP 32 RC0 T1OSO T13CKI 31 OSC2 CLKO RA6 30 OSC1 CLKI PIC18F4455 M v DD PIC18F4550 27 RE2 AN7 OESPP 26 RE1 AN6 CK2SPP 25 RE0 AN5 CK1SPP 0 24 RA5 AN4 SS HLVDIN C2OUT 1 23 RA4 TOCKI C10UT RCV NOTFTOONRNDDOrA rTT ING awoas0qgMOort DATSCOWZZ EE GOVfICAeSsaze AgHAGFLSZOS 0205000 21 11 FE X IE uz SN OBGRNLI LS KE lt m m m O OOTrE CS ac 992 lt So lt Q zz lt a oc PIC18F4455 PIC18F4550 2004 Microchip Technology Inc Preliminary DS39632B page 3 PIC18F2455 2550 4455 4550 Table of Contents 1 0 Device OVelVI6W ugnu u AN a a 20 Oscillator ConfiguratiohS u uuu u a u ni init en starter anne natal hit dt 3 0 Power Managed Modes a 407 MRSS OL tam km a ipana awkina mamas ama kus SB sana sest s kuma ku a Nik een nant uhaq a h a G Quam Ma 5 0 M mory Organization sus n es s a cot n sa D s aa aS a aS amas e ide ent re ama 6 0 Flash Program Memory z 7 0 Data EEPROM M mor in asr na rar at hur lan un aula 8 0 8x8 Hardware Whultiplier i a ss zvara aa a a 9 0 Interrupts 10 0 I O Ports 11 0 Timer0 Module 12 0 Timer1 Module 13 0 Timer2 Module 14 0 Timer3 Module 15 0 Capture Compare PWM CCP Modules 16 0 Enhanced Capture Compare PWM ECCP Module 17 0 Universal Serial Bus USB a eee eee z 18 0 Str
115. Inc PIC18F2455 2550 4455 4550 26 0 INSTRUCTION SET SUMMARY PIC18F2455 2550 4455 4550 devices incorporate the standard set of 75 PIC18 core instructions as well as an extended set of eight new instructions for the optimization of code that is recursive or that utilizes a software stack The extended set is discussed later in this section 26 1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets while maintaining an easy migration from these PICmicro instruction sets Most instructions are a single program memory word 16 bits but there are four instructions that require two program memory locations Each single word instruction is a 16 bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction The instruction set is highly orthogonal and is grouped into four basic categories Byte oriented operations Bit oriented operations e Literal operations Control operations The PIC18 instruction set summary in Table 26 2 lists byte oriented bit oriented literal and control operations Table 26 1 shows the opcode field descriptions Most byte oriented instructions have three operands 1 The file register specified by f 2 The destination of the result specified by d 3 The accessed memory specified by a The file register designator f
116. Interrupts Watchdog Timer WDT Fail Safe Clock Monitor Two Speed Start up e Code Protection ID Locations In Circuit Serial Programming The oscillator can be configured for the application depending on frequency power accuracy and cost All of the options are discussed in detail in Section 2 0 Oscillator Configurations A complete discussion of device Resets and interrupts is available in previous sections of this data sheet In addition to their Power up and Oscillator Start up Tim ers provided for Resets PIC18F2455 2550 4455 4550 devices have a Watchdog Timer which is either permanently enabled via the configuration bits or software controlled if configured as disabled The inclusion of an internal RC oscillator also provides the additional benefits of a Fail Safe Clock Monitor FSCM and Two Speed Start up FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure Two Speed Start up enables code to be executed almost immediately on start up while the primary clock 2004 Microchip Technology Inc Preliminary DS39632B page 279 PIC18F2455 2550 4455 4550 25 1 The configuration bits can be programmed read as 0 or left unprogrammed read as 1 to select various device configurations These bits are mapped starting at program memory location 300000h The user will note that address 300000h is beyond the user program memo
117. J DFNBEE UERRIF CRC16EF UERRE CRCIGEE STALLIF 4 CROSEF 4 CROSEE 1 STALLIES to o ACTVIF PIDEE ACTVIE URSTIF 4 URSTIE FIGURE 17 9 EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS From Host From Host To Host DP 8 gt SETUP Token Data ACK 1 9 SetTRNIF From Host To Host From Host USB Reset IN Token Data ACK Set TRNIF URSTIF From Host From Host To Host S pr ME OUT Token Empty Data ACK gt Set TRNIF 0 Transaction gt I Transaction Complete RESET SOF SETUP DATA STATUS SOF Differential Data lt Control Transfer m 1 ms Frame Note 1 The control transfer shown here is only an example showing events that can occur for every transaction Typical control transfers will spread across multiple frames 2004 Microchip Technology Inc Preliminary DS39632B page 177 PIC18F2455 2550 4455 4550 17 5 1 USB INTERRUPT STATUS Once an interrupt bit has been set by the SIE it must REGISTER UIR be cleared by software by writing a o The flag bits The USB Interrupt Status register Register 17 7 con tains the flag bits for each of the USB status interrupt can also be set in software which can aid in firmware debugging sources Each of these sources has a corresponding interrupt enable bit in the UIE register All of the USB status flags are ORed together to generate the USBIF interrupt flag for the microcontroller
118. JSUen SeJeuILUIS dojseu sng va lt 0 gt 1VLSASS 44 semyos u plea Y OIEMYJOS u peJesj9 1 lt gt Hld didSS d ee i oi VA AA DU i i All sa P Ri j VETE EP AJ 1 VT VJ EP V hos foaXta za Kea va sa ea Na Jyo 0a fra Na yea Yra Ysa y q Y za sov ov Y lv zv yev ow XV Novy 2Y woo MON l g Leeq 2119904 914g geq 8118904 90e d uaye sey GdvdSs Jo lepdn lun MOJ p u SI 40019 sselppy Jo l g puodas 8118984 o d USMEJ seu qavdSsS Jo lepdn iun MOJ p u SI 0019 zov Verve JU vas 0 WH ee a ssaippy JO 914 1S113 9119094 2004 Microchip Technology lnc Iminary Prel DS39632B page 210 PIC18F2455 2550 4455 4550 FIGURE 19 11 CT SLAVE MODE TIMING TRANSMISSION 10 BIT ADDRESS BF SSPSTAT lt 0 gt SDA SCL SSPIF 2004 Microchip Technology Inc Preliminary DS39632B page 211 PIC18F2455 2550 4455 4550 19 4 4 CLOCK STRETCHING Both 7 and 10 bit Slave modes implement automatic clock stretching during a transmit sequence The SEN bit SSPCON2 lt 0 gt allows clock stretching to be enabled during receives Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence 19 4 4 1 Clock Stretching for 7 bit Slave Receive Mode SEN 1 In 7 bit Slave Receive mode on the falling edge of the ninth clock at the end of the ACK sequence
119. Master mode in that the shift clock is 2 Clear bits CREN Ang SREN supplied externally at the CK pin instead of being 3 If interrupts are desired set enable bit TXIE supplied internally in Master mode This allows the 4 If9 bit transmission is desired set bit TX9 device to transfer or receive data while in any 5 Enable the transmission by setting enable bit low power mode TXEN 20 4 1 EUSART SYNCHRONOUS 6 If 9 bit transmission is selected the ninth bit SLAVE TRANSMIT should be loaded in bit TX9D 7 Start transmission by loading data to the The operation of the Synchronous Master and Slave TXREGx register modes is identical except in the case of Sleep mode 8 If using interrupts ensure that the GIE and PEIE If two words are written to the TXREG register and then the SLEEP instruction is executed the following will occur a The first word will immediately transfer to the TSR register and transmit b The second word will remain in the TXREG register c Flag bit TXIF will not be set d When the first word has been shifted out of TSR the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set e If enable bit TXIE is set the interrupt will wake the chip from Sleep If the global interrupt is enabled the program will branch to the interrupt vector bits in the INTCON register INTCON lt 7 6 gt are set T
120. None 2nd word 1111 kkkk kkkk kkkk CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO PD DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None 2nd word 1111 kkkk kkkk kkkk NOP No Operation 1 0000 0000 0000 0000 None NOP No Operation 1 1111 XXXX XXXX xxxx None 4 POP Pop top of return stack TOS 1 0000 0000 0000 0110 None PUSH Push top of return stack TOS 1 0000 0000 0000 0101 None RCALL n Relative Call 2 1101 1nnn nnnn nnnn None RESET Software device Reset 1 0000 0000 1111 1111 All RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE GIEH PEIE GIEL RETLW Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO PD Note 1 When a Port register is modified as a function of itself e g MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a o If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP Some instructions are two word instruct
121. O SPP5 O TTL Streaming Parallel Port data P1B O Enhanced CCP1 PWM output channel B RD6 SPP6 P1C 29 4 4 RD6 O ST Digital I O SPP6 O TTL Streaming Parallel Port data P1C O Enhanced CCP1 PWM output channel C RD7 SPP7 P1D 30 5 5 RD7 O ST Digital I O SPP7 O TTL Streaming Parallel Port data P1D O Enhanced CCP1 PWM output channel D Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared 2 Default assignment for CCP2 when CCP2MX configuration bit is set 3 These pins are No Connect unless the ICPRT configuration bit is set For NC ICPORTS the pin is No Connect unless ICPRT is set and the DEBUG configuration bit is cleared DS39632B page 20 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 1 3 PIC18F4455 4550 PINOUT O DESCRIPTIONS CONTINUED Pin Name pu Number n j Burer Description PDIP QFN TQFP Type Type r PORTE is a bidirectional I O port REO AN5 CK1SPP 8 25 25 REO O ST Digital I O AN5 I Analog Analog input 5 CK1SPP O SPP clock 1 output RE1 AN6 CK2SPP 9 26 26 RE1 I O ST Digital I O AN6 I Analog Analog input 6 CK2SPP O SPP clock 2 output RE2 AN7 OESPP 10 27 27 RE2 O ST Digital I O AN7 I Ana
122. OUT DIG LATB lt 3 gt data output not affected by analog input CCP2 VPO 1 IN TTL PORTB lt 3 gt data input weak pull up when RBPU bit is cleared Disabled when analog input enabled AN9 1 IN ANA _ A D input channel 9 ccp2 2 0 OUT DIG CCP2 Compare and PWM output 1 IN ST CCP2 Capture input VPO 0 OUT DIG External USB transceiver VPO data output RB4 AN11 RB4 0 OUT DIG LATB lt 4 gt data output not affected by analog input KBI0 CSSPP 1 IN TTL PORTB lt 4 gt data input weak pull up when RBPU bit is cleared Disabled when analog input enabled AN11 1 IN ANA _ A D input channel 1101 KBIO 1 IN TTL Interrupt on pin change cssppP 4 0 IN DIG SPP chip select control output RB5 KBI1 RB5 0 OUT DIG LATB lt 5 gt data output PGM 1 IN TTL PORTB lt 5 gt data input weak pull up when RBPU bit is cleared KBI1 1 IN TTL Interrupt on pin change PGM x IN ST Single Supply Programming mode entry ICSP Enabled by LVP configuration bit all other pin functions disabled Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input C SMB I C SMBus input buffer TTL TTL Buffer Input x Don t care TRIS bit does not affect port direction or is overridden for this option Note 1 Configuration on POR is determined by PBADEN configuration bit Pins are configured as analog inputs when PBADEN is set and digital inputs when PBADEN is cleared 2 Alternate pin assignment for CCP2 w
123. On the following cycle of the device clock DS39632B page 394 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 29 0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time EE EE a eee 2004 Microchip Technology Inc Preliminary DS39632B page 395 PIC18F2455 2550 4455 4550 NOTES DS39632B page 396 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 30 0 PACKAGING INFORMATION 30 1 Package Marking Information 28 Lead PDIP Skinny DIP XXXXXXXXXXXXXXXXX O XXXXXXXXXXXXXXXXX LAN YYWWNNN 28 Lead SOIC KXXXXXXXXXX XXX XXX XXX KXXXXXXXXXXXXX XXX XXX KXXXXXXXXXX XXX XXX XXX 6 LAN YYWWNNN 40 Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX O XXXXXXXXXXXXXXXXXX O YYWWNNN MICROCHIP Example PIC18F2455 I SP O AN 0410017 O Example PIC18F2550 E SO 0410017 Example PIC18F4455 1 P 0410017 O MICROCHIP T O Legend XX X Customer specific information Y Year code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer sp
124. On the other hand errors in data may sug gest that the clock speed is too low to compensate increment OSCTUNE to increase the clock frequency It is also possible to verify device clock speed against a reference clock Two timers may be used one timer is clocked by the peripheral clock while the other is clocked by a fixed reference source such as the Timer oscillator Both timers are cleared but the timer clocked by the reference generates interrupts When an interrupt occurs the internally clocked timer is read and both timers are cleared If the internally clocked timer value is greater than expected then the internal oscillator block is running too fast To adjust for this decrement the OSCTUNE register Finally a CCP module can use free running Timer1 or Timer3 clocked by the internal oscillator block and an external event with a known period i e AC power frequency The time of the first event is captured in the CCPRxH CCPRxL registers and is recorded for use later When the second event causes a capture the time of the first event is subtracted from the time of the second event Since the period of the external event is known the time difference between events can be calculated If the measured time is much greater than the calcu lated time the internal oscillator block is running too fast to compensate decrement the OSCTUNE register If the measured time is much less than the calculated time the internal os
125. Output Compare or PWM mode or the primary oscillator using the OSC2 pin a grounded guard ring around the oscillator circuit as shown in Figure 12 4 may be helpful when used on a single sided PCB or in addition to a ground plane FIGURE 12 4 OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD Vss OSC1 OSC2 RC0 RC1 RC2 Note Not drawn to scale 12 4 Timer1 Interrupt The TMR1 register pair TMR1H TMR1L increments from 0000h to FFFFh and rolls over to 0000h The Timert interrupt if enabled is generated on overflow which is latched in interrupt flag bit TMRIIF PIR1 lt 0 gt This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit TMRIIE PIE1 lt 0 gt 12 5 Resetting Timer1 Using the CCP Special Event Trigger If either of the CCP modules is configured in Compare mode to generate a special event trigger CCP1M3 CCP1MO or CCP2M3 CCP2M0 1011 this signal will reset Timer1 The trigger from CCP2 will also start an A D conversion if the A D module is enabled see Section 15 3 4 Special Event Trigger for more information The module must be configured as either a timer or a synchronous counter to take advantage of this feature When used this way the CCPRH CCPRL register pair effectively becomes a period register for Timer1 If Timer1 is running in Asynchronous Counter mode this Reset operation may not work In the event
126. Pull up Enable bit 1 All PORTB pull ups are disabled o PORTB pull ups are enabled by individual port latch values INTEDGO External Interrupt 0 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge INTEDG1 External Interrupt 1 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge INTEDG2 External Interrupt 2 Edge Select bit 1 Interrupt on rising edge 0 Interrupt on falling edge Unimplemented Read as 0 TMROIP TMRO Overflow Interrupt Priority bit 1 High priority 0 Low priority Unimplemented Read as 0 RBIP RB Port Change Interrupt Priority bit 1 High priority 0 Low priority bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set V Bit is cleared x Bit is unknown Note Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling DS39632B page 100 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 9 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 INTCON3 INTERRUPT CONTROL REGISTER 3 R W 1 R W 1 U 0 R W 0 R W 0 U 0 R W 0 R W 0 INT2IP INT1IP
127. RBO AN12 INTO FLTO SDI SDA Serial Clock SCK RB1 AN10 INT1 SCK SCL Additionally a fourth pin may be used when in a Slave mode of operation Slave Select SS RA5 AN4 SS HLVDIN C2OUT Figure 19 1 shows the block diagram of the MSSP module when operating in SPI mode FIGURE 19 1 MSSP BLOCK DIAGRAM SPITM MODE K Internal Data Bus Read Ay Write SSPBUF reg ZN Z SSPSR reg RBO SDI SDA bito A Shift x Clock RC7 SDO fe SS Control gt Enable RA5 SS Edge Select 2 Clock Select SSPM3 SSPM0 y2 4 TMR2 Outpul gt l Edge Select J Prescaler TOSC RB1 SCK SCL 4 16 64 Data to TX RX in SSPSR TRIS bit Note Only those pin functions relevant to SPITM operation are shown here 2004 Microchip Technology Inc Preliminary DS39632B page 193 PIC18F2455 2550 4455 4550 19 3 1 REGISTERS The MSSP module has four registers for SPI mode operation These are MSSP Control Register 1 SSPCON1 MSSP Status Register SSPSTAT Serial Receive Transmit Buffer Register SSPBUF MSSP Shift Register SSPSR Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation The SSPCON1 register is readable and writable The lower six bits of the SSPSTAT are read only The upper two bits
128. SETUP transac tions note that the corresponding EPINEN and EPOUTEN bit must be set to enable IN and OUT transactions For Endpoint 0 this bit should always be cleared since the USB specifications identify Endpoint 0 as the default control endpoint The EPOUTEN bit UEPn lt 2 gt is used to enable or dis able USB OUT transactions from the host Setting this bit enables OUT transactions Similarly the EPINEN bit UEPn lt 1 gt enables or disables USB IN transactions from the host The EPSTALL bit UEPn lt 0 gt is used to indicate a STALL condition for the endpoint If a STALL is issued on a particular endpoint the EPSTALL bit for that end point pair will be set by the SIE This bit remains set until it is cleared through firmware or until the SIE is reset REGISTER 17 4 UEPn USB ENDPOINT n CONTROL REGISTER UEPO THROUGH UEP15 U 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL bit 7 bit 0 bit 7 5 Unimplemented Read as bit 4 EPHSHK Endpoint Handshake Enable bit 1 Endpoint handshake enabled 0 Endpoint handshake disabled typically used for isochronous endpoints bit 3 EPCONDIS Bidirectional Endpoint Control bit If EPOUTEN 1 and EPINEN 1 1 Disable Endpoint n from control transfers only IN and OUT transfers allowed 0 Enable Endpoint n for control SETUP transfers IN and OUT transfers also allowed bit 2 EPOUTEN
129. SIE is listening to the bus or actively driving the bus This is enabled by default when using an external transceiver or when UCFG lt 6 gt 1 The OE monitoring is useful for initial system debugging as well as scope triggering during eye pattern generation tests 17 2 2 7 Eye Pattern Test Enable An automatic eye pattern test can be generated by the module when the UCFG lt 7 gt bit is set The eye pattern output will be observable based on module settings meaning that the user is first responsible for configuring the SIE clock settings pull up resistor and Transceiver mode In addition the module has to be enabled Once UTEYE is set the module emulates a switch from a receive to transmit state and will start transmitting a J K J K bit sequence K J K J for full speed The sequence will be repeated indefinitely while the Eye Pattern Test mode is enabled Note that this bit should never be set while the module is connected to an actual USB system This test mode is intended for board verification to aid with USB certi fication tests It is intended to show a system developer the noise integrity of the USB signals which can be affected by board traces impedance mismatches and proximity to other system components It does not properly test the transition from a receive to a transmit state Although the eye pattern is not meant to replace the more complex USB certification test it should aid during first order system debugging
130. SPP address write mc MCLR cc CCP1 osc OSC1 ck CLKO rd RD cs cs rw RD or WR da SPP data write sc SCK di SDI ss SS do SDO to TOCKI dt Data in t1 T13CKI io I O port wr WR Uppercase letters and their meanings S F Fall P Period H High R Rise Invalid High impedance V Valid L Low Z High impedance IC only AA output access High High BUF Bus free Low Low Tcc srT IC specifications only CC HD Hold SU Setup ST DAT DATA input hold STO Stop condition STA Start condition DS39632B page 374 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 28 4 2 TIMING CONDITIONS The temperature and voltages specified in Table 28 7 apply to all timing specifications unless otherwise noted Figure 28 4 specifies the load conditions for the timing specifications Note Because of space limitations the generic terms PIC18FXXXX and PIC18LFXXXX are used throughout this section to refer to the PIC18F2455 2550 4455 4550 and PIC18LF2455 2550 4455 4550 families of devices specifically and only those devices TABLE 28 7 TEMPERATURE AND VOLTAGE SPECIFICATIONS AC AC CHARACTERISTICS Section 28 3 Operating temperature Standard Operating Conditions unless otherwise stated 40 C lt TA lt 85 C for industrial Operating voltage VDD range as described in DC spec Section 28 1 and LF parts operate for industrial temperatures only FIGURE 28 4 LOAD C
131. Stack Pointer is decremented The Stack Pointer is initialized to 00000 after all Resets There is no RAM associated with the location corresponding to a Stack Pointer value of 00000 this is only a Reset value Status bits indicate if the stack is full has overflowed or has underflowed 5 1 2 1 Top of Stack Access Only the top of the return address stack TOS is readable and writable A set of three registers TOSU TOSH TOSL hold the contents of the stack loca tion pointed to by the STKPTR register Figure 5 2 This allows users to implement a software stack if necessary After a CALL RCALL or interrupt the software can read the pushed value by reading the TOSU TOSH TOSL registers These values can be placed on a user defined software stack At return time the software can return these values to TOSU TOSH TOSL and do a return The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption FIGURE 5 2 RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack lt 20 0 gt 11111 Top of Stack Registers T Stack Pointer TOSU TOSH TOSL a aS STKPTR lt 4 0 gt 00h 1Ah 34h e li Ag 00010 X z 00011 ee gt gt Top of Stack 001A34h 00010 000D58h 00001 00000 DS39632B page 58 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550
132. Start condition is detected on the SDA and SCL pins the S bit SSPSTAT lt 3 gt will be set The SSPIF bit will not be set until the Baud Rate Generator has timed out 19 4 9 FIGURE 19 20 Note 1 If RSEN is programmed while any other event is in progress it will not take effect 2 Abus collision during the Repeated Start condition occurs if SDA is sampled low when SCL goes from low to high e SCL goes low before SDA is asserted low This may indicate that another master is attempting to transmit a data 1 Immediately following the SSPIF bit getting set the user may write the SSPBUF with the 7 bit address in 7 bit mode or the default first address in 10 bit mode After the first eight bits are transmitted and an ACK is received the user may then transmit an additional eight bits of address 10 bit mode or eight bits of data 7 bit mode 19 4 9 1 WCOL Status Flag If the user writes the SSPBUF when a Repeated Start sequence is in progress the WCOL is set and the contents of the buffer are unchanged the write doesn t occur Note Because queueing of events is not allowed writing of the lower five bits of SSPCON2Z is disabled until the Repeated Start condition is complete REPEAT START CONDITION WAVEFORM Write to SSPCON2 SDA Falling edge of ninth clock end of Xmit occurs here SDA 3 At completion of Start bit SDA 1 SCL 1 hardware clears RSEN bit S
133. Start up Timer has timed out and the primary clock is providing the device clock in primary clock modes The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes The T1RUN bit TICON lt 6 gt indicates when the Timer1 oscillator is providing the device clock in secondary clock modes In power managed modes only one of these three bits will be set at any time If none of these bits are set the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3 0 Power Managed Modes Note 1 The Timer1 oscillator must be enabled to select the secondary clock source The Timer oscillator is enabled by setting the TIOSCEN bit in the Timer1 Control regis ter T1CON lt 3 gt If the Timer1 oscillator is not enabled then any attempt to select a secondary clock source will be ignored 2 It is recommended that the Timer oscillator be operating and stable prior to switching to it as the clock source other wise a very long delay may occur while the Timer1 oscillator starts 2004 Microchip Technology Inc Preliminary DS39632B page 31 PIC18F2455 2550 4455 4550 2 4 2 OSCILLATOR
134. TISYNC TMR1CS TMR1ON 52 T3CON RD16 T3CCP2 T3CKPS1 T3CKPSO T3CCP1 TZSYNC TMR3CS TMR3ON 53 Legend unimplemented read as 0 Shaded cells are not used by the Timer3 module 2004 Microchip Technology Inc Preliminary DS39632B page 139 PIC18F2455 2550 4455 4550 NOTES AEO aun rr r r rrrr n w DS39632B page 140 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 15 0 CAPTURE COMPARE PWM CCP MODULES PIC18F2455 2550 4455 4550 devices all have two CCP Capture Compare PWM modules Each module contains a 16 bit register which can operate as a 16 bit Capture register a 16 bit Compare register or a PWM Master Slave Duty Cycle register In 28 pin devices the two standard CCP modules CCP1 and CCP2 operate as described in this chapter In 40 44 pin devices CCP1 is implemented as an Enhanced CCP module with standard Capture and Compare modes and Enhanced PWM modes The ECCP implementation is discussed in Section 16 0 Enhanced Capture Compare PWM ECCP Module REGISTER 15 1 The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules Note Throughout this section and Section 16 0 Enhanced Capture Compare PWM ECCP Module references to the register and bit names for CCP modules are referred to gener ically by the use of x or y in place of the specific module number Thus CCPxCON
135. TMR2ON T2CKPS1 T2CKPSO bit 7 bit 7 bit 6 3 Unimplemented Read as 0 0000 1 1 Postscale 0001 1 2 Postscale 1111 1 16 Postscale TMR2ON Timer2 On bit 1 Timer2 is on 0 Timer2 is off bit 2 bit 1 0 00 Prescaler is 1 01 Prescaler is 4 1x Prescaler is 16 bit 0 T2OUTPS3 T2OUTPSO Timer2 Output Postscale Select bits T2CKPS1 T2CKPSO Timer2 Clock Prescale Select bits Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 135 PIC18F2455 2550 4455 4550 13 2 Timer2 Interrupt Timer2 also can generate an optional device interrupt The Timer2 output signal TMR2 to PR2 match pro vides the input for the 4 bit output counter postscaler This counter generates the TMR2 match interrupt flag which is latched in TMR2IF PIR1 lt 1 gt The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit TMR2IE PIE1 lt 1 gt A range of 16 postscale options from 1 1 through 1 16 inclusive can be selected with the postscaler control bits T2OUTPS3 T20UTPSO T2CON lt 6 3 gt 13 3 TMR2 Output The unscaled output of TMR2 is available primarily to the CCP modules where it is used as a time base for operations in PWM mode Timer2 can be optionally used as the shift clock source f
136. TRANSITIONS PIC18F2455 2550 4455 4550 devices contain circuitry to prevent clock glitches when switching between clock sources A short pause in the device clock occurs during the clock switch The length of this pause is the REGISTER 2 2 R W 0 R W 1 R W 0 sum of two cycles of the old clock source and three to four cycles of the new clock source This formula assumes that the new clock source is stable Clock transitions are discussed in greater detail in Section 3 1 2 Entering Power Managed Modes OSCCON OSCILLATOR CONTROL REGISTER R W 0 RM R 0 R W 0 R W 0 IDLEN IRCF2 IRCF1 IRCFO OSTS IOFS SCS1 SCS0 bit 7 bit 7 IDLEN ldle Enable bit 1 Device enters Idle mode on SLE 0 Device enters Sleep mode on SLI bit 0 EP instruction EEP instruction bit 6 4 IRCF2 IRCFO Internal Oscillator Frequency Select bits 111 8 MHz INTOSC drives clock directly 110 4 MHz 101 2 MHz 100 1 MHz 011 500 kHz 010 250 kHz 001 125 kHz 000 31 kHz from either INTOSC 256 or INTRC directly bit 3 OSTS Oscillator Start up Time out Status bit 1 Oscillator Start up Timer time out has expired primary oscillator is running 0 Oscillator Start up Timer time out is running primary oscillator is not ready bit 2 IOFS INTOSC Frequency Stable bit 1 INTOSC frequency is stable 0 INTOSC frequency is not stable bit 1 0 SCS1 SCSO System Clock Select bits
137. TTL PORTA lt 0 gt data input disabled when analog input enabled ANO 1 IN ANA A D input channel 0 and Comparator C1 input Default configuration on POR does not affect digital output RA1 AN1 RA1 0 OUT DIG LATA lt 1 gt data output not affected by analog input 1 IN TTL PORTA lt 1 gt data input reads 0 on POR AN1 ak IN ANA A D input channel 1 and Comparator C2 input Default configuration on POR does not affect digital output RA2 AN2 RA2 0 OUT DIG LATA lt 2 gt data output not affected by analog input Disabled when VREF CVREF CVREF output enabled 1 IN TTL PORTA lt 2 gt data input Disabled when analog functions enabled disabled when CVREF output enabled AN2 1 IN ANA A D input channel 2 and Comparator C2 input Default configuration on POR not affected by analog output VREF 1 IN ANA A D and comparator voltage reference low input CVREF x OUT ANA Comparator voltage reference output Enabling this feature disables digital I O RA3 AN3 RA3 0 OUT DIG LATA lt 3 gt data output not affected by analog input VREF 1 IN TTL PORTA lt 3 gt data input disabled when analog input enabled AN3 1 IN ANA A D input channel 3 and Comparator C1 input Default configuration on POR VREF 1 IN ANA A D and comparator voltage reference high input RA4 TOCKI RA4 0 OUT DIG LATA lt 4 gt data output not affected by analog input C1OUT RCV al IN ST PORTA lt 4 gt data input disabled when analog input enabled TOCKI 1 IN ST Timer0 clock
138. These include Four Crystal modes using crystals or ceramic resonators Four External Clock modes offering the option of using two pins oscillator input and a divide by 4 clock output or one pin oscillator input with the second pin reassigned as general I O An internal oscillator block which provides an 8 MHz clock 2 accuracy and an INTRC source approximately 31 kHz stable over temperature and VDD as well as a range of 6 user selectable clock frequencies between 125 kHz to 4 MHz for a total of 8 clock frequencies This option frees an oscillator pin for use as an additional general purpose I O A Phase Lock Loop PLL frequency multiplier available to both the high speed crystal and external oscillator modes which allows a wide range of clock speeds from 4 MHz to 48 MHz e Asynchronous dual clock operation allowing the USB module to run from a high frequency oscillator while the rest of the microcontroller is clocked from an internal low power oscillator Besides its availability as a clock source the internal oscillator block provides a stable reference source that gives the family additional features for robust operation e Fail Safe Clock Monitor This option constantly monitors the main clock source against a reference signal provided by the internal oscillator If a clock failure occurs the controller is switched to the internal oscillator block allowing for continued low speed operation or a safe
139. These values must be preconfigured prior to enabling the module 3 This bit is only valid when the on chip transceiver is active UTRDIS 0 otherwise it is ignored Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared x Bit is unknown There are 6 signals from the module to communicate The VPO and VMO signals are outputs from the SIE to with and control an external transceiver VM Input from the single ended D line VP Input from the single ended D line RCV Input from the differential receiver VMO Output to the differential line driver VPO Output to the differential line driver OE Output enable the external transceiver The RCV signal is the output from the external transceiver to the SIE it represents the differential signals from the serial bus translated into a single pulse train The VM and VP signals are used to report conditions on the serial bus to the SIE that can t be captured with the RCV signal The combinations of states of these signals and their interpretation are listed in Table 17 1 and Table 17 2 DS39632B page 166 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 17 1 DIFFERENTIAL OUTPUTS TO TRANSCEIVER Bus State VPO VMO Single Ended Zero Differential 0 Differential 1 Illegal Condition H H HIlolo HO a o TABL
140. Type Type p SOIC PORTB is a bidirectional I O port PORTB can be software programmed for internal weak pull ups on all inputs RBO AN12 INTO FLTO 21 SDI SDA RBO O TTL Digital I O AN12 Analog Analog input 12 INTO ST External interrupt 0 FLTO l ST PWM Fault input CCP1 module SDI ST SPI data in SDA O ST IC data I O RB1 AN10 INT1 SCK 22 SCL RB1 O TTL Digital I O AN10 Analog Analog input 10 INT1 ST External interrupt 1 SCK O ST Synchronous serial clock input output for SPI mode SCL O ST Synchronous serial clock input output for C mode RB2 AN8 INT2 VMO 23 RB2 O TTL Digital I O AN8 Analog Analog input 8 INT2 ST External interrupt 2 VMO O External USB transceiver VMO output RB3 AN9 CCP2 VPO 24 RB3 O TTL Digital I O AN9 Analog Analog input 9 ccp2 1 O ST Capture 2 input Compare 2 output PWM 2 output VPO O External USB transceiver VPO output RB4 AN11 KBIO 25 RB4 O TTL Digital I O AN11 Analog Analog input 11 KBIO TTL Interrupt on change pin RB5 KBI1 P GM 26 RB5 O TTL Digital I O KBI1 TTL Interrupt on change pin PGM O ST Low Voltage ICSPTM Programming enable pin RB6 KBI2 PGC 27 RB6 O TTL Digital O KBI2 TTL Interrupt on change pin PGC O ST In Circuit Debugger and ICSP programming clock pin RB7 KBI3 PGD 28 RB7 O TTL Digital I O KBI3 TTL Interrupt on change pin PGD O ST In Circuit Debugger and ICSP programming data pin
141. USB events by the USBIP bit For additional details on USB interrupt logic refer to Section 17 5 USB Interrupts 2004 Microchip Technology Inc Preliminary DS39632B page 97 PIC18F2455 2550 4455 4550 FIGURE 9 1 INTERRUPT LOGIC Wake up if in Sleep Mode TMROIF Sale PN TMROIE J TMROIP RBIF x RBIE RBIP a J INTOIF 4 hH INTOIE Interrupt to CPU INTIIF 7X Vector to Location INTIIE 0008h Peripheral Interrupt Flag bit EN INTHIP Peripheral Interrupt Enable bit RE D Peripheral Interrupt Priority bit P P i INT2P B TMRIIF u GIEH GIE TMR1IE TMRIIP A Z B IPEN Ep js ray UBF IPEN nterrupt Logic USBIE jJ USBIP GIEL PEIE IPEN 4 gt Additional Peripheral Interrupts 1 High Priority Interrupt Generation O Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit y Interrupt to CPU TMROIF Vector to Location TMROIE A 0018h TMR1IF N TMROIP TMRIIE TMRIIP RBIF__ j gt From USB RBIE A USBIF 4 RBIP GIEL PEIE Interrupt Logic USBIE USBIP GIE GEIH INT1IF 3 g INT1IE A Peripheral kre pz dditional Peripheral Interrupts INTIIP NY L
142. Users should proceed cautiously when working on these registers particularly if their code uses indirect addressing Similarly operations by indirect addressing are gener ally permitted on all other SFRs Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device DS39632B page 74 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 5 5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set Enabling the extended instruction set adds eight additional two word commands to the existing PIC18 instruction set ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR and SUBULNK These instructions are executed as described in Section 5 2 4 Two Word Instructions 5 6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set XINST configuration bit 1 significantly changes certain aspects of data memory and its addressing Specifically the use of the Access Bank for many of the core PIC18 instructions is different this is due to the introduction of a new addressing mode for the data memory space This mode also alters the behavior of indirect addressing using FSR2 and its associated operands What does not change is just as important The size of the data memory space is unchanged as well as its linea
143. Write Fo SSPCON1 L i I 2004 Microchip Technology Inc Preliminary DS39632B page 213 PIC18F2455 2550 4455 4550 CT SLAVE MODE TIMING WITH SEN 1 RECEPTION 7 BITADDRESS FIGURE 19 13 S1N990 BUIUJIEJIS yoolo pue 0 0 19S01 SI dHO MO0 9 UJUIU y JO SBpe Bulle eye Jes s 4g 11290 IM Bulyoyeus 390 OU pue 0 01 18881 89 JOU IIIA 4MO aremyos 90J9 UJUIU y Jo 6p ul T 0 Buie au 0 1oud USHUM pee peueelo SI 44 J 4 do ques JOU SI MOV IN INS SI angdSS sneosg 198 S AOSS U lt 9g gt INOOdSS AOdSS peal si INGdSS 1 SIEMYOS ul paread lt 0 gt 1V1SdSS 4a 49 SUEJ U s leuluuel Y I Von lt e gt Luld 4I4SS i 6 3e V NY NS V v V V 1 W VU VW VIN XV w q F p p R po 5 j ss WA xY Asa X ta X za X ea X va X sa X90 Xa Yoa X ra X za X ea X va X sa X sa Xza HOV V v Kaw Yev Y ww sv ov X zv N vas Res MOV T MOV osneoeg MO PISU JOU SI 3X90 O geq BUINISISY I IRUN MOJ p u SI 49019 MOV eyeq Bunieosy 0 19S SI 43M0 X9019 ululu JO 5 obpe ulje 0 aoud 18819 s 1g ag In4 19 yng sneo q MOJ PISU JOU SI M909 0 WH ssaippy BUINI9094 2004 Microchip Technology Inc Iminary Prel DS39632B page 214 PIC18F2455 2550 4455 4550 IC SLAVE MODE TIMING WITH SEN 1 RECEPTION 1
144. X O INT2IF 4 INT2IE INT2IP DS39632B page 98 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 9 2 INTCON Registers Note The INTCON registers are readable and writable registers which contain various enable priority and flag bits REGISTER 9 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt This feature allows for software polling INTCON INTERRUPT CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W x GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF bit 7 bit 0 GIE GIEH Global Interrupt Enable bit When IPEN s 0 1 Enables all unmasked interrupts 0 Disables all interrupts When IPEN 1 1 Enables all high priority interrupts 0 Disables all high priority interrupts PEIE GIEL Peripheral Interrupt Enable bit When IPEN s 0 1 Enables all unmasked peripheral interrupts 0 Disables all peripheral interrupts When IPEN 1 1 Enables all low priority peripheral interrupts 0 Disables all low priority peripheral interrupts TMROIE TMRO Overflow Interrupt Enable bit 1 Enables the TMRO overflow
145. a certain threshold This allows the device to start in the initialized state when VDD is adequate for operation To take advantage of the POR circuitry tie the MCLR pin through a resistor 1 KQ to 10 kQ to VDD This will eliminate external RC components usually needed to create a Power on Reset delay A minimum rise rate for VDD is specified parameter D004 Section 28 1 DC Characteristics For a slow rise time see Figure 4 2 When the device starts normal operation i e exits the Reset condition device operating parameters volt age frequency temperature etc must be met to ensure operation If these conditions are not met the device must be held in Reset until the operating conditions are met POR events are captured by the POR bit RCON lt 1 gt The state of the bit is set to o whenever a POR occurs it does not change for any other Reset event POR is not reset to 1 by any hardware event To capture multiple events the user manually resets the bit to 1 in software following any POR 2004 Microchip Technology Inc 3 FIGURE 4 2 EXTERNAL POWER ON RESET CIRCUIT FOR SLOW Vpp POWER UP VDD VDD ZAD R MCLR c PIC18FXXXX Note 1 External Power on Reset circuit is required only if the VDD power up slope is too slow The diode D helps discharge the capacitor quickly when VDD powers down R lt 40 kQ is recommended to make sure that the voltage drop across
146. all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or Vss MCLR VDD WDT enabled disabled as specified 3 Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications 2004 Microchip Technology Inc Preliminary DS39632B page 363 PIC18F2455 2550 4455 4550 28 2 DC Characteristics Power Down and Supply Current PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Continued PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial oe Device Typ Max Units Conditions Supply Current IDD PIC18LFX455 X550 65 130 uA 40 C 65 120 LA 25 C VDD 2 0V 70 115 uA 85 C PIC18LFX455 X550 120 270 HA 40 C Fosc 1 MHz 120 250 HA 25 C VDD 3 0V PRI_IDLE mode 130 240 uA 85 C EC oscillator All devic
147. all details but may be used with care where higher rates are reguired by the application 2004 Microchip Technology Inc Preliminary DS39632B page 219 PIC18F2455 2550 4455 4550 19 4 7 1 Clock Arbitration Clock arbitration occurs when the master during any receive transmit or Repeated Start Stop condition deasserts the SCL pin SCL allowed to float high When the SCL pin is allowed to float high the Baud Rate Generator BRG is suspended from counting until the SCL pin is actually sampled high When the FIGURE 19 18 SCL pin is sampled high the Baud Rate Generator is reloaded with the contents of SSPADD lt 6 0 gt and begins counting This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device Figure 19 18 BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX x DX 1 SCL SCL deasserted but slave holds SCL low clock arbitration re ee SOL allowed to transition high BRG decrements on Q2 and Q4 cycles BRG l A X 03h X 02h X 01h X 00h hold off X 03h A 02h SCL is sampled high reload takes place and BRG starts its count Y Reload DS39632B page 220 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 C MASTER MODE START CONDITION TIMING To initiate a Start condition the user sets
148. ami g Parallel POM z um att e aere aE Aiae a Nara aE e Ean aTa eni enn Rae aeoea a a a 19 0 Master Synchronous Serial Port MSSP Module nn n nn n anan 20 0 Enhanced Universal Synchronous Receiver Transmitter EUSART u i 21 0 10 Bit Analog to Digital Converter A D Module sisi 22 0 Comparator Module vet uu Rs oa 23 0 Comparator Voltage Reference Module DE 24 0 High Low Voltage Detect EVD L os kd tn a 25 0 Special Feat res of the CPU siii ua al a a alla 26 0 Instruction Set Summary A 27 0 Development Support n as La uama ama aasawa aE ra s Sen kla 28 0 Electrical Characteristics 29 0 DC and AC Characteristics Graphs and Tables Ae 0 0 PACKAGING IMO ALON sar n a scents coe r r o a lu ln Appendix A Revision HISIOry u kura ru uu au Appendix B Device Differences K Appendix O Conversion Considerations eso0oornocnovon no no RR Appendix D Migration From Baseline to Enhanced Devices sise Appendix E Migration From Mid Range to Enhanced Devices ae Appendix F Migration From High End to Enhanced Devices sisi U O Ea E ASA mener et nee de re On Line Support Systems Information and Upgrade Hot Line Reader Response sas ce PIC18F2455 2550 4455 4550 Product Identification System sisi DS39632B page 4 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TO OUR VALUED CUSTOMERS It is our intention to provide our valued cust
149. and temperature range that is expected for the application Resonators Used 4 0 MHz 8 0 MHz 16 0 MHz An internal postscaler allows users to select a clock frequency other than that of the crystal or resonator Frequency division is determined by the CPUDIV configuration bits Users may select a clock frequency of the oscillator frequency or 1 2 1 3 or 1 4 of the frequency An external clock may also be used when the micro controller is in HS Oscillator mode In this case the OSC2 CLKO pin is left open Figure 2 3 2004 Microchip Technology Inc Preliminary DS39632B page 25 PIC18F2455 2550 4455 4550 FIGURE 2 3 EXTERNAL CLOCK INPUT OPERATION HS OSC CONFIGURATION Clock from 0501 Ext System PIC18FXXXX Open osc HS Mode 2 2 3 EXTERNAL CLOCK INPUT The EC ECIO ECPLL and ECPIO Oscillator modes require an external clock source to be connected to the OSC1 pin There is no oscillator start up time required after a Power on Reset or after an exit from Sleep mode In the EC and ECPLL Oscillator modes the oscillator frequency divided by 4 is available on the OSC2 pin This signal may be used for test purposes or to synchronize other logic Figure 2 4 shows the pin connections for the EC Oscillator mode FIGURE 2 4 EXTERNAL CLOCK INPUT OPERATION EC AND ECPLL CONFIGURATION Clock from OSC1 CLKI Ext System PIC18FXXXX Fosc 4 OSC2 C
150. and the device will wake up from Sleep Device execution will continue from the interrupt vector address if interrupts have been globally enabled 24 7 Effects of a Reset A device Reset forces all registers to their Reset state This forces the HLVD module to be turned off TABLE 24 1 REGISTERS ASSOCIATED WITH HIGH LOW VOLTAGE DETECT MODULE Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page HLVDCON VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDLO 52 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 Legend unimplemented read as 0 Shaded cells are unused by the HLVD module 2004 Microchip Technology Inc Preliminary DS39632B page 277 PIC18F2455 2550 4455 4550 NOTES DS39632B page 278 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 25 0 SPECIAL FEATURES OF THE CPU PIC18F2455 2550 4455 4550 devices include several features intended to maximize reliability and minimize cost through elimination of external components These are e Oscillator Selection e Resets Power on Reset POR Power up Timer PWRT Oscillator Start up Timer OST Brown out Reset BOR e
151. are used as the primary clock source TABLE 2 4 OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin INTCKO Floating pulled by external clock At logic low clock 4 output INTIO Floating pulled by external clock Configured as PORTA bit 6 ECIO ECPIO Floating pulled by external clock Configured as PORTA bit 6 EC Floating pulled by external clock At logic low clock 4 output XT and HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent voltage level voltage level Note See Table 4 2 in Section 4 0 Reset for time outs due to Sleep and MCLR Reset 2004 Microchip Technology Inc Preliminary DS39632B page 33 PIC18F2455 2550 4455 4550 NOTES AEO O EO i a E O Sy DS39632B page 34 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 3 0 POWER MANAGED MODES PIC18F2455 2550 4455 4550 devices offer a total of seven operating modes for more efficient power management These modes provide a variety of options for selective power conservation in applications where resources may be limited i e battery powered devices There are three categories of power managed modes e Run modes Idle modes Sleep mode These categories define which portions of the device are clocked and sometimes what speed The Run and Idle modes may use any of the three available clock sources primary secondary or internal
152. as Literature Number DS00726 2004 Microchip Technology Inc Preliminary DS39632B page 407 PIC18F2455 2550 4455 4550 NOTES AEO E O EO EE r m m O O Sy DS39632B page 408 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 INDEX A AID sz NAN 253 Acquisition Requirements 258 ADCONO Register ADCONI Register ADCON2 Register ADRESH Register ADRESL Register Analog Port Pins Configuring 260 Associated Registers 262 Configuring the Module y Conversion Clock TAD Conversion Status GO DONE Bit 256 Conversions a Converter Characteristics a 393 Converter Interrupt Configuring 257 Discharge sia Operation in Power Managed Modes 260 Selecting and Configuring Acquisition Time rn 259 Special Event Trigger CCP2 Special Event Trigger ECCP 3 Use of the CCP2 Trigger 262 Absolute Maximum Ratings AP AC Timing Characteristics 374 Load Conditions for Device Timing Specifications Parameter Symbology ws Temperature and Voltage Specifications 375 Timing Co
153. assembler features include Integration into MPLAB IDE projects e User defined macros to streamline assembly code Conditional assembly for multi purpose source files e Directives that allow complete control over the assembly process 2004 Microchip Technology Inc Preliminary DS39632B page 351 PIC18F2455 2550 4455 4550 273 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip s PIC17CXXX and PIC18CXXX family of microcontrollers These compilers provide powerful integration capabilities superior code optimization and ease of use not found with other compilers For easy source level debugging the compilers provide symbol information that is optimized to the MPLAB IDE debugger 27 4 MPLINK Object Linker MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers It can link relocatable objects from precompiled libraries using directives from a linker script The MPLIB object librarian manages the creation and modification of library files of precompiled code When a routine from a library is called from a source file only the modules that contain that routine will be linked in with the application This allows large libraries to be used efficiently in many different applications The object linker library features include e E
154. be read and written with the table read and table write instructions In normal execution mode the CPn bits have no direct effect CPn bits inhibit external reads and writes A block of user memory may be protected from table writes if the WRTn configuration bit is o The EBTRn bits control table reads For a block of user memory with the EBTRn bit set to 0 a table read instruction that executes from within that block is allowed to read FIGURE 25 6 A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading o s Figures 25 6 through 25 8 illustrate table write and table read protection Note Code protection bits may only be written to a from a 1 state It is not possible to write a 1 to a bit in the o state Code protection bits are only set to 1 by a full Chip Erase or Block Erase function The full Chip Erase and Block Erase functions can only be initiated via ICSP operation or an external programmer TABLE WRITE WRTn DISALLOWED Register Values Program Memory Configuration Bit Settings TBLPTR 0008FFh PC 001FFEh TBLWT PC 005FFEh TBLWT 000000h WRTB EBTRB 11 0007FFh 000800h WRTO EBTRO 01 001FFFh 002000h WRT1 EBTR1 11 OO3FFFh 004000h WRT2 EBTR2 11 OOSFFFh 006000h WRT3 EBTRS 11 007FFFh Results All table writes disabled to
155. bit must be cleared to make the CCP2 pin an output Note Clearing the CCP2CON register will force the RB3 or RC1 output latch depending on device configuration to the default low level This is not the PORTB or PORTC I O data latch Figure 15 3 shows a simplified block diagram of the CCP module in PWM mode For a step by step procedure on how to set up the CCP module for PWM operation see Section 15 4 4 Setup for PWM Operation FIGURE 15 3 SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers Pas CCPxCON lt 5 4 gt CCPRxL M SZ CCPRxH Slave Comparator R Q CCPx Output TMR2 Note 1 L 7 Corresponding Comparator a Clear Timer TRIS bit ZN CCPx pin and PRO latch D C Note 1 The 8 bit timer TMR2 value is concatenated with 2 bit internal G clock or 2 bits of the prescaler to create the 10 bit time base A PWM output Figure 15 4 has a time base period and a time that the output stays high duty cycle The freguency of the PWM is the inverse of the period 1 period FIGURE 15 4 PWM OUTPUT Period lt p Duty Cycle TMR PR2 TMR2 Duty Cycle TMR2 PR2 15 4 1 PWM PERIOD The PWM period is specified by writing to the PR2 register The PWM period can be calculated using the following formula EQUATION 15 1 PWM Period PR2 1 4 T
156. bit oriented commands is replaced with the literal offset value k As already noted this occurs only when f is less than or egualto 5Fh When an offset value is used it must be indicated by square brackets As with the extended instructions the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset Omitting the brackets or using a value greater than 5Fh within brackets will generate an error in the MPASM Assembler If the index argument is properly bracketed for Indexed Literal Offset Addressing mode the Access RAM argument is never specified it will automatically be assumed to be 0 This is in contrast to standard operation extended instruction set disabled when a is set on the basis of the target address Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler The destination argument d functions as before In the latest versions of the MPASM assembler language support for the extended instruction set must be explicitly invoked This is done with either the command line option y or the PE directive in the source listing 26 2 4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruc tion set may not be beneficial to all users In particular users who are not writing code that uses a software stack may not benefit from using the extensions
157. bit to enable the module Note If a USB endpoint is configured to use the SPP the data transfer type of that endpoint must be Isochronous only 18 3 Setup for Microcontroller Control The SPP can also act as a parallel port for the microcontroller In this mode the SPPEPS register Register 18 3 provides status and address write control Data is written to and read from the SPPDATA register When the SPP is owned by the microcontroller the SPP clock is driven by the instruction clock FOSC 4 The following steps are required to set up the SPP for microcontroller operation 1 Configure the SPP as desired including wait states and clocks 2 Clear the SPPOWN bit 3 Set SPPEN to enable the module FIGURE 18 5 18 3 1 SPP INTERRUPTS When owned by the microcontroller core control can generate an interrupt to notify the application when each read and write operation is completed The interrupt flag bit is SPPIF PIR1 lt 7 gt and is enabled by the SSPIE bit PIE1 lt 7 gt Like all other microcontroller level interrupts it can be set to a low or high priority This is done with the SSPIP bit IPR1 lt 7 gt 18 3 2 WRITING TO THE SPP Once configured writing to the SPP is performed by writing to the SPPEPS and SPPDATA registers If the SPP is configured to clock out endpoint address infor mation with the data writing to the SPPEPS register initiates the address write cycle Otherwise the write is sta
158. bit which is set when the TSR register is empty No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty Note 1 The TSR register is not mapped in data memory so it is not available to the user 2 Flag bit TXIF is set when enable bit TXEN is set To set up an Asynchronous Transmission 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN 3 If interrupts are desired set enable bit TXIE 4 If 9 bit transmission is desired set transmit bit TX9 Can be used as address data bit 5 Enable the transmission by setting bit TXEN which will also set bit TXIF 6 If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Load data to the TXREG transmission 8 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are register starts set FIGURE 20 3 EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF HIGH TXREG Register TXIE 8 MSO ES s Pin Buffer gt i 8 ED i and Control at S PCNA TSR Register 0 TX pin Interrupt A TXEN
159. cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 125 PIC18F2455 2550 4455 4550 11 1 Timer0 Operation Timer0 can operate as either a timer or a counter the mode is selected by clearing the TOCS bit TOCON lt 5 gt In Timer mode the module increments on every clock by default unless a different prescaler value is selected see Section 11 3 Prescaler If the TMRO register is written to the increment is inhibited for the following two instruction cycles The user can work around this by writing an adjusted value to the TMRO register The Counter mode is selected by setting the TOCS bit 1 In Counter mode TimerO increments either on every rising or falling edge of pin RA4 TOCKI The incrementing edge is determined by the Timer0 Source Edge Select bit TOSE TOCON lt 4 gt clearing this bit selects the rising edge Restrictions on the external clock input are discussed below An external clock source can be used to drive Timer0 however it must meet certain requirements to ensure that the external clock can be synchronized with the FIGURE 11 1 internal phase clock Tosc There is a delay between synchronization and the onset of incrementing the timer counter 11 2 Timer0 Reads and Writes in 16 Bit Mode TMROH is not the actual high byte of TimerO in 16 bit mode it is actually a buffered version of the real high byte of TimerO which is not directly r
160. clock transition delays These are discussed in Section 3 1 3 Clock Transitions and Status Indicators and subseguent sections Entry to the Power Managed ldle or Sleep modes is triggered by the execution of a SLEEP instruction The actual mode that results depends on the status of the IDLEN bit Depending on the current mode and the mode being switched to a change to a power managed mode does not always reguire setting all of these bits Many transitions may be done by changing the oscillator select bits or changing the IDLEN bit prior to issuing a SLEEP instruction If the IDLEN bit is already configured correctly it may only be necessary to perform a SLEEP instruction to switch to the desired mode TABLE 3 1 POWER MANAGED MODES OSCCON Bits Module Clocking Mode Available Clock and Oscillator Source IDLEN SCS1 SCSO CPU Peripherals Sleep 0 N A Off Off None all clocks are disabled PRI RUN N A 00 Clocked Clocked Primary all oscillator modes This is the normal full power execution mode SEC RUN N A 01 Clocked Clocked Secondary Timer1 oscillator RC RUN N A 1x Clocked Clocked Internal oscillator block PRI IDLE 1 00 Off Clocked Primary all oscillator modes SEC IDLE 1 01 Off Clocked Secondary Timer1 oscillator RC IDLE 1x Off Clocked Internal oscillator block Note 1 IDLEN reflects its value when the SLEEP instruction is executed 2 Include
161. configurations depending on whether the microcontroller or the USB module is modifying the BD and buffer at a particular time Only three bit definitions are shared between the two 17 4 1 1 Buffer Ownership Because the buffers and their BDs are shared between the CPU and the USB module a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory This is done by using the UOWN bit BDnSTAT lt 7 gt as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory UOWN is the only bit that is shared between the two configurations of BDnSTAT When UOWN is clear the BD entry is owned by the microcontroller core When the UOWN bit is set the BD entry and the buffer memory are owned by the USB peripheral the core should not modify the BD or its corresponding data buffer during this time Note that the microcontroller core can still read BDNSTAT while the SIE owns the buffer and vice versa The buffer descriptors have a different meaning based on the source of the register update Prior to placing ownership with the USB peripheral the user can con figure the basic operation of the peripheral through the BDnSTAT bits During this time the byte count and buffer location registers can also be set When UOWN is set the user can no longer depend on the values that were written to the BDs From this point the SIE updates the BDs as nece
162. desirable For example the HLVD module could be periodically enabled to detect Universal Serial Bus USB attach or detach This assumes the device is powered by a lower voltage source than the USB when detached An attach would indicate a high voltage detect from for example 3 3V to 5V the voltage on USB and vice versa for a detach This feature could save a design a few extra components and an attach signal input pin For general battery applications Figure 24 4 shows a possible voltage curve Over time the device voltage decreases When the device voltage reaches voltage VA the HLVD logic generates an interrupt at time TA The interrupt could cause the execution of an ISR which would allow the application to perform house keeping tasks and perform a controlled shutdown before the device voltage exits the valid operating range at TB The HLVD thus would give the applica tion a time window represented by the difference between TA and TB to safely exit DS39632B page 276 Preliminary FIGURE 24 4 TYPICAL HIGH LOW VOLTAGE DETECT APPLICATION VA VB D s s TA TB Time Legend VA HLVD trip point VB Minimum valid device operating voltage 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 24 6 Operation During Sleep When enabled the HLVD circuitry continues to operate during Sleep If the device voltage crosses the trip point the HLVDIF bit will be set
163. device is placed in Sleep mode the comparator remains active and the interrupt is functional if enabled This interrupt will wake up the device from Sleep mode when enabled Each operational comparator will consume additional current as shown in the comparator specifications To minimize power consumption while in Sleep mode turn off the comparators CM2 CMO 111 before entering Sleep If the device wakes up from Sleep the contents of the CMCON register are not affected 22 8 Effects of a Reset A device Reset forces the CMCON register to its Reset state causing the comparator modules to be turned off CM2 CMO 111 However the input pins RAO through RA3 are configured as analog inputs by default on device Reset The I O configuration for these pins is determined by the setting of the PCFG3 PCFGO bits ADCON1 lt 3 0 gt Therefore device current is minimized when analog inputs are present at Reset time DS39632B page 266 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 22 9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 22 4 Since the analog pins are connected to a digital output they have reverse biased diodes to VDD and Vss The analog input therefore must be between Vss and VDD If the input voltage deviates from this range by more than 0 6V in either direction one of the diodes is forward biased and a latch up condition may
164. due to a rollover between reads A write to the high byte of Timer1 must also take place through the TMR1H Buffer register The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMRIL This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once The high byte of Timer1 is not directly readable or writable in this mode All reads and writes must take place through the Timer1 High Byte Buffer register Writes to TMR1H do not clear the Timer1 prescaler The prescaler is only cleared on writes to TMRIL 1233 Timer1 Oscillator An on chip crystal oscillator circuit is incorporated between pins T1OSI input and T1OSO amplifier output It is enabled by setting the Timer1 Oscillator Enable bit TIOSCEN T1CON lt 3 gt The oscillator is a low power circuit rated for 32 kHz crystals It will continue to run during all power managed modes The circuit for a typical LP oscillator is shown in Figure 12 3 Table 12 1 shows the capacitor selection for the Timer1 oscillator The user must provide a software time delay to ensure proper start up of the Timer1 oscillator EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR FIGURE 12 3 Gi PIC18FXXXX b SH T1081 r XTAL T 32 768 kHz T 1 XH T10SO C2 33 pF Note See the Notes with Table 12 1 for additional information about capacitor selection TABLE 12 1 CAPACITOR SELECTION FOR THE
165. f If d is Words 4 o the result is placed in W If d 5 1 the result is placed back in register f Cycles 1 default Q Cycle Activity If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the 1 2 Q3 Q4 D a 2 P Wi W GPR bank default ecode li a feat rite to If a is o and the extended instruction itera ata set is enabled this instruction operates in Indexed Literal Offset Addressing Example IORLW 35h mode whenever f lt 95 5Fh See Before Instruction Section 26 2 3 Byte Oriented and eo e ns Bit Oriented Instructions in Indexed w 9Ah s Literal Offset Mode for details After Instruction w BFh Words 1 Cycles 1 Q Cycle Activity 01 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example IORWF RESULT 0 1 Before Instruction RESULT 13h W 91h After Instruction RESULT 13h w 93h DS39632B page 324 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 LFSR Load FSR Syntax LFSR f k Operands O lt f lt 2 0 lt k lt 4095 Operation k FSRf Status Affected None Encoding 1110 1110 ooff k kkk 1111 0000 kjkkk kkkk Description The 12 bit literal k is loaded into the File Select Register pointed to by f Words 2 Cycles 2 Q Cycle Activity Q1 Q2 03 Q4 Decode Read literal Process Write K MSB
166. f Skip if not 0 DCFSNZ f d a 0 lt f lt 255 d e 0 1 a e 0 1 f 1 gt dest skip if result z o None 0100 11da TETE Ferre The contents of register f are decremented If is o the result is placed in W If d is 1 the result is placed back in register f default If the result is not o the next instruction which is already fetched is discarded and a NOP is executed instead making it a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction Preliminary Q1 Q2 93 Q4 Decode Read Process Write to register f Data destination If skip Q1 Q2 03 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE DCFSNZ TEMP 1 0 ZERO NZERO Before Instruction TEMP gt v After Instruction TEMP TEMP 1 If TEMP 0
167. first time initiates the read operation When the read is finished indicated by returned The SPP automatically starts the read cycle for the next read the SSPBUSY bit the SPPDATA will be loaded with the 4 Monitor the SSPBUSY bit to determine when the current data The following is an example read sequence data has been read The duration depends on the wait states 5 Go back to step 3 to read the current byte from 1 Write the 4 bit address to the SPPEPS register the SPP and start the next read cycle The SPP automatically starts writing the address If address write is not used then skip to step 3 2 Monitorthe SSPBUSY bit to determine when the address has been sent The duration depends on the wait states REGISTER 18 3 SPPEPS SPP ENDPOINT ADDRESS AND STATUS REGISTER bit 7 bit 6 bit 5 bit 4 bit 3 0 R 0 R 0 U 0 R 0 R W 0 R W 0 R W 0 R W 0 RDSPP WRSPP SPPBUSY ADDR3 ADDR2 ADDR1 ADDRO bit 7 bit 0 RDSPP SPP Read Status bit Valid when SPPCON lt SSPOWN gt 1 USB 1 The last transaction was a read from the SPP 0 The last transaction was not a read from the SPP WRSPP SPP Write Status bit Valid when SPPCON lt SSPOWN gt 1 USB 1 The last transaction was a write to the SPP 0 The last transaction was not a write to the SPP Unimplemented Read as 0 SPPBUSY SPP Handshaking Override bit 1 The SPP is busy 0 The SPP is ready to acce
168. fixed to a value of 0 The PC increments by 2 to address sequential instructions in the program memory The CALL RCALL and GOTO program branch instructions write to the program counter directly For these instructions the contents of PCLATH and PCLATU are not transferred to the program counter 5 1 2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur The PC is pushed onto the stack when a CALL or RCALL instruc tion is executed or an interrupt is Acknowledged The PC value is pulled off the stack on a RETURN RETLW or a RETFIE instruction PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions The stack operates as a 31 word by 21 bit RAM anda 5 bit Stack Pointer STKPTR The stack space is not part of either program or data space The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the top of stack Special File Registers Data can also be pushed to or popped from the stack using these registers A CALL type instruction causes a push onto the stack The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC already pointing to the instruction following the CALL A RETURN type instruction causes a pop from the stack The contents of the location pointed to by the STKPTR are transferred to the PC and then the
169. for the current Idle mode For example when waking from RC_IDLE mode the internal oscillator block will clock the CPU and peripherals in other words RC RUN mode The IDLEN and SCS bits are not affected by the wake up While in any Idle mode or the Sleep mode a WDT time out will result in a WDT wake up to the Run mode currently specified by the SCS1 SC SO bits TRANSITION TIMING FOR ENTRY TO SLEEP MODE OSC1 GROG a Ike aes ie a S aS p SEK Sa S s as as ys a T Clock Peripheral Clock V U U N Sleep 7 Program PC M PC 2 A FIGURE 3 6 TRANSITION TIMING FOR WAKE FROM SLEEP HSPLL 02 93 04 01 02 03 04 01 92 03 24 01 02 AZ AL osor VON LU VU VU U VU I 1 pean Re nn NTN N SPU FUN TAT U A EN Peripheral N EE ee a e Wake Event OSTS bit Set Note1 TosT 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2004 Microchip Technology Inc Preliminary DS39632B page 39 PIC18F2455 2550 4455 4550 3 4 1 PRI IDLE MODE This mode is unique among the three Low Power Idle modes in that it does not disable the primary device clock For timing sensitive applications this allows for the fastest resumption of device operation with its more accurate primary clock source since the clock source does not have to warm up or transition from another oscillator PRI IDLE mode is entered from PR
170. if the BF bit is set the CKP bit in the SSPCON1 register is automatically cleared forcing the SCL output to be held low The CKP bit being cleared to o will assert the SCL line low The CKP bit must be set in the user s ISR before reception is allowed to continue By holding the SCL line low the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence This will prevent buffer overruns from occurring see Figure 19 13 19 4 4 3 Clock Stretching for 7 bit Slave Transmit Mode 7 bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear This occurs regardless of the state of the SEN bit The user s ISR must set the CKP bit before transmis sion is allowed to continue By holding the SCL line low the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence see Figure 19 9 Note 1 If the user loads the contents of SSPBUF setting the BF bit before the falling edge of the ninth clock the CKP bit will not be cleared and clock stretching will not occur 2 The CKP bit can be set in software regardless of the state of the BF bit Note 1 If the user reads the contents of the SSPBUF before the falling edge of the ninth clock thus clearing the BF bit the CKP bit will not be clear
171. is seen this should correspond to the Stop bit the ABDEN bit is automatically cleared If a rollover of the BRG occurs an overflow from FFFFh to 0000h the event is trapped by the ABDOVF status bit BAUDCON lt 7 gt It is set in hardware by BRG roll overs and can be set or cleared by the user in software ABD mode remains active after rollover events and the ABDEN bit remains set Figure 20 2 While calibrating the baud rate period the BRG registers are clocked at 1 8th the preconfigured clock rate Note that the BRG clock will be configured by the BRG16 and BRGH bits Independent of the BRG16 bit setting both the SPBRG and SPBRGH will be used as a 16 bit counter This allows the user to verify that no carry occurred for 8 bit modes by checking for 00h in the SPBRGH register Refer to Table 20 4 for counter clock rates to the BRG While the ABD sequence takes place the EUSART state machine is held in Idle The RCIF interrupt is set once the fifth rising edge on RX is detected The value in the RCREG needs to be read to clear the RCIF interrupt The contents of RCREG should be discarded Note 1 If the WUE bit is set with the ABDEN bit Auto Baud Rate Detection will occur on the byte following the Break character 2 It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source Some combinations of oscillator frequency and EUSART baud rates are not possible due
172. lt 0 gt data output not affected by analog input CK1SPP 1 IN ST PORTE lt 0 gt data input disabled when analog input enabled AN5 1 IN ANA _ A D input channel 5 default configuration on POR CK1SPP 0 OUT DIG SPP clock 1 output SPP enabled RE1 AN6 RE1 0 OUT DIG LATE lt 1 gt data output not affected by analog input CK2SPP 1 IN ST PORTE lt 1 gt data input disabled when analog input enabled AN6 1 IN ANA _ A D input channel 6 default configuration on POR CK2SPP 0 OUT DIG SPP clock 2 output SPP enabled RE2 AN7 RE2 0 OUT DIG LATE lt 2 gt data output not affected by analog input OESPP 1 IN ST PORTE lt 2 gt data input disabled when analog input enabled AN7 1 IN ANA A D input channel 7 default configuration on POR OESPP 0 OUT DIG SPP enable output SPP enabled MCLR vPP RE3 1 IN ST PORTE lt 3 gt data input enabled when MCLRE configuration bit is RE3 clear MCLR 1 IN ST External Master Clear input enabled when MCLRE configuration bit is set VPP 1 IN ANA High voltage detection used for ICSPTM mode entry detection Always available regardless of pin mode Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input Note 1 TABLE 10 10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE RE3 does not have a corresponding TRISE lt 3 gt bit This pin is always an input regardless of mode Reset Name Bit 7 B
173. lt 2 gt must specify a write so the slave device will receive the second address byte For a 10 bit address the first byte would equal 11110 A9 AB 0 where A9 and As are the two MSbs of the address The sequence of events for 10 bit address is as follows with steps 7 through 9 for the slave transmitter 1 Receive first high byte of address bits SSPIF BF and UA SSPSTAT lt 1 gt are set 2 Update the SSPADD register with second low byte of address clears bit UA and releases the SCL line 3 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 4 Receive second low byte of address bits SSPIF BF and UA are set 5 Update the SSPADD register with the first high byte of address If match releases SCL line this will clear bit UA 6 Read the SSPBUF register clears bit BF and clear flag bit SSPIF 7 Receive Repeated Start condition 8 Receive first high byte of address bits SSPIF and BF are set 9 Read the SSPBUF register clears bit BF and clear flag bit SSPIF DS39632B page 206 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 3 2 Reception When the R W bit of the address byte is clear and an address match occurs the R W bit of the SSPSTAT register is cleared The received address is loaded into the SSPBUF register and the SDA line is held low ACK When the address byte overflow condition exists then the no Acknowledge ACK
174. may be accessed by Direct Indirect or Indexed Addressing modes Addressing modes are discussed later in this subsection To ensure that commonly used registers SFRs and select GPRs can be accessed in a single cycle PIC18 devices implement an Access Bank This is a 256 byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR Section 5 3 3 Access Bank provides a detailed description of the Access RAM 5 3 1 USB RAM Banks 4 through 7 of the data memory are actually mapped to special dual port RAM When the USB module is disabled the GPRs in these banks are used like any other GPR in the data memory space When the USB module is enabled the memory in these banks is allocated as buffer RAM for USB operation This area is shared between the microcontroller core and the USB Serial Interface Engine SIE and is used to transfer data directly between the two It is theoretically possible to use the areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage In prac tice the dynamic nature of buffer allocation makes this risky at best Additionally Bank 4 is used for USB buffer management when the module is enabled and should not be used for any other purposes during that time Additional information on USB RAM and buffer operation is provided in Section 17 0 Universal Serial Bus USB 5 3 2 BANK SELECT REGISTER BS
175. must also be considered especially in applications using oscillators with longer start up intervals i e XT or HS mode The Sync Break or Wake up Signal character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART 20 2 4 2 Special Considerations Using tne WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data As noted setting the WUE bit places the EUSART in an ldle mode The wake up event causes a receive interrupt by setting the RCIF bit The WUE bit is cleared after this when a rising edge is seen on RX DT The interrupt condition is then cleared by read ing the RCREG register Ordinarily the data in RCREG will be dummy data and should be discarded The fact that the WUE bit has been cleared or is still set and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG Users should consider implementing a parallel method in firmware to verify received data integrity To assure that no actual data is lost check the RCIDL bit to verify that a receive operation is not in process If a receive operation is not occurring the WUE bit may then be set just prior to entering the Sleep mode FIGURE 20 8 AUTO WAKE UP BIT WUE TIMINGS DURING NORMAL OPERATION G1 Q2
176. not become full or overflowed bit 6 STKUNF Stack Underflow Flag bit 1 1 Stack underflow occurred 0 Stack underflow did not occur bit 5 Unimplemented Read as 0 bit 4 0 SP4 SP0 Stack Pointer Location bits Note 1 Bit 7 and bit 6 are cleared by user software or by a POR Legend R Readable bit W Writable bit U Unimplemented C Clearable only bit n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 59 PIC18F2455 2550 4455 4550 5 1 2 4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L When STVREN is set a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset When STVREN is cleared a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset The STKFUL or STKUNF bits are cleared by user software or a Power on Reset 5 1 3 FAST REGISTER STACK A fast register stack is provided for the Status WREG and BSR registers to provide a fast return option for interrupts Each stack is only one level deep and is neither readable nor writable It is loaded with the current value of the corresponding register when the processor vectors for an interrupt All interrupt sources will push values into the stack r
177. not the case an array refresh must be performed For this reason variables that change infrequently such as constants IDs calibration etc should be stored in Flash program memory A simple data EEPROM refresh routine is shown in Example 7 3 Note If data EEPROM is only used to store constants and or data that changes rarely an array refresh is likely not required See specification D124 or D124A EXAMPLE 7 3 DATA EEPROM REFRESH ROUTINE CLRF EEADR Start at address 0 BCF EECON1 CFGS Set for memory BCF EECON1 EEPGD Set for Data EEPROM BCF INTCON GIE Disable interrupts BSF EECON1 WREN Enable writes Loop Loop to refresh array BSF EECON1 RD Read current address MOVLW 55h Required MOVWF EECON2 Write 55h Sequence MOVLW OAAh MOVWF EECON2 Write OAAh BSF EECON1 WR Set WR bit to begin write BTFSC EECON1 WR Wait for write to complete BRA 2 INCFSZ EEADR F Increment address BRA LOOP Not zero do it again BCF EECON1 WREN Disable writes BSF INTCON GIE Enable interrupts DS39632B page 92 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 7 1 REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 EEADR EEPROM Addres
178. of the SSPSTAT are read write SSPSR is the shift register used for shifting data in or out SSPBUF is the buffer register to which data bytes are written to or read from In receive operations SSPSR and SSPBUF together create a double buffered receiver When SSPSR receives a complete byte it is transferred to SSPBUF and the SSPIF interrupt is set During transmission the SSPBUF is not double buffered A write to SSPBUF will write to both SSPBUF and SSPSR REGISTER 19 1 SSPSTAT MSSP STATUS REGISTER SPI MODE R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 SMP CKE D A P S RW UA BF bit 7 bit O bit7 SMP Sample bit SPI Master mode 1 Input data sampled at end of data output time 0 Input data sampled at middle of data output time SPI Slave mode SMP must be cleared when SPI operation is used in Slave mode bit 6 CKE SPI Clock Select bit 1 Transmit occurs on transition from active to Idle clock state 0 Transmit occurs on transition from Idle to active clock state Polarity of clock state is set by the CKP bit SSPCON1 lt 4 gt bit5 D A Data Address bit Used in I C mode only bit 4 P Stop bit Used in I C mode only This bit is cleared when the MSSP module is disabled SSPEN is cleared bit 3 S Start bit Used in I C mode only bit 2 RW Read Write bit Information Used in I C mode only bit 1 UA Update Address bit Used in I C mode only bit 0 BF Buffer Full S
179. pins needed as analog inputs must have their corresponding TRIS bits set input If the TRIS bit is cleared output the digital output level VOH or VOL will be converted The A D operation is independent of the state of the CHS3 CHSO bits and the TRIS bits Note 1 When reading the Port register all pins configured as analog input channels will read as cleared a low level Pins config ured as a digital input will convert as an analog input Analog levels on a digitally configured input will be accurately converted 2 Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device s specification limits 3 The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by control ling how the PCFGO bits in ADCON1 are reset DS39632B page 260 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 216 AD Conversions Figure 21 4 shows the operation of the A D converter after the GO DONE bit has been set and the ACQT2 ACQTO bits are cleared A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins Figure 21 5 shows the operation of the A D converter after the GO DONE bit has been set the ACQT2 ACQTO bits are set to 010 and selecting a 4 TAD acquisition time before the conversion starts Clearing the GO DONE b
180. process Their main function is to ensure that the device clock is stable before code is executed These timers are Power up Timer PWRT Oscillator Start up Timer OST e PLL Lock Time out 4 5 1 POWER UP TIMER PWRT The Power up Timer PWRT of PIC18F2455 2550 4455 4550 devices is an 11 bit counter which uses the INTRC source as the clock input This yields an approximate time interval of 2048 x 32 us 65 6 ms While the PWRT is counting the device is held in Reset The power up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation See DC parameter 33 Table 28 12 for details The PWRT is enabled by clearing the PWRTEN configuration bit 4 5 2 OSCILLATOR START UP TIMER OST The Oscillator Start up Timer OST provides a 1024 oscillator cycle from OSC1 input delay after the PWRT delay is over parameter 33 Table 28 12 This ensures that the crystal oscillator or resonator has started and stabilized The OST time out is invoked only for XT HS and HSPLL modes and only on Power on Reset or on exit from most power managed modes 4 5 3 PLL LOCK TIME OUT With the PLL enabled in its PLL mode the time out sequence following a Power on Reset is slightly differ ent from other oscillator modes A separate timer is used to provide a fixed time out that is sufficient for the PLL to lock to the main oscillator frequency This PLL lock time out TPLL is typical
181. pulse is given An overflow condition is defined as either bit BF SSPSTAT lt 0 gt is set or bit SSPOV SSPCON1 lt 6 gt is set An MSSP interrupt is generated for each data transfer byte Flag bit SSPIF PIR1 lt 3 gt must be cleared in software The SSPSTAT register is used to determine the status of the byte If SEN is enabled SSPCON2 lt 0 gt 1 RB1 AN10 INT1 SCK SCL will be held low clock stretch following each data transfer The clock must be released by setting bit CKP SSPCON1 lt 4 gt See Section 19 4 4 Clock Stretching for more detail 19 4 3 3 Transmission When the R W bit of the incoming address byte is set and an address match occurs the R W bit of the SSPSTAT register is set The received address is loaded into the SSPBUF register The ACK pulse will be sent on the ninth bit and pin RB1 AN10 INT1 SCK SCL is held low regardless of SEN see Section 19 4 4 Clock Stretching for more detail By stretching the clock the master will be unable to assert another clock pulse until the slave is done preparing the transmit data The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register Then pin RB1 AN10 INT1 SCK SCL should be enabled by setting bit CKP SSPCON1 lt 4 gt The eight data bits are shifted out on the falling edge of the SCL input This ensures that the SDA signal is valid during the SCL high time Figure 19 9 The ACK pulse from the master receiv
182. resolution The equations used to calculate the output of the comparator voltage reference are as follows If CVRR 1 CVREF CVR3 CVRO 24 x CVRSRC If CVRR o CVREF CVRSRC 4 CVR3 CVRO 32 x CVRSRC The comparator reference supply voltage can come from either VDD and Vss or the external VREF and VREF that are multiplexed with RA2 and RA3 The voltage source is selected by the CVRSS bit CVRCON lt 4 gt The settling time of the comparator voltage reference must be considered when changing the CVREF output see Table 28 3 in Section 28 0 Electrical Characteristics REGISTER 23 1 CVRCON COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CVREN CVROF CVRR CVRSS CVR3 CVR2 CVR1 CVRO bit 7 bit 0 bit 7 CVREN Comparator Voltage Reference Enable bit 1 CVREF circuit powered on 0 CVREF circuit powered down bit 6 CVROE Comparator VREF Output Enable bit 1 CVREF voltage level is also output on the RA2 AN2 VREF CVREF pin 0 CVREF voltage is disconnected from the RA2 AN2 VREF CVREF pin Note 1 CVROE overrides the TRISA lt 2 gt bit setting bit 5 CVRR Comparator VREF Range Selection bit 1 0 to 0 667 CVRSRC with CVRSRC 24 step size low range 0 0 25 CVRSRC to 0 75 CVRSRC with CVRSRC 32 step size high range bit 4 CVRSS Comparator VREF Source Selection bit 1 Comparator reference source CVRSRC
183. runs in either a Command Line mode for automated tasks or from MPLAB IDE This high speed simulator is designed to debug analyze and optimize time intensive DSP routines DS39632B page 352 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 27 9 MPLAB ICE 2000 High Performance Universal In Circuit Emulator The MPLAB ICE 2000 universal in circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers Software control of the MPLAB ICE 2000 in circuit emulator is advanced by the MPLAB Integrated Development Environment 2004 Microchip Technology Inc Preliminary DS39632B page 353 PIC18F2455 2550 4455 4550 27 14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy to use low cost prototype programmer It con nects to the PC via a COM RS 232 port MPLAB Integrated Development Environment software makes using the programmer simple and efficient The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins Larger pin count devices such as the PIC16C92X and PIC17C76X may be supported with an adapter socket The PICSTART Plus development programmer is CE compliant 27 15 PICDEM 1 PlCmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X PIC16C54 to PIC16C58A PIC16C61 PIC16C62X P
184. specifies which file register is to be used by the instruction The destination designator d specifies where the result of the opera tion is to be placed If d is zero the result is placed in the WREG register If d is one the result is placed in the file register specified in the instruction All bit oriented instructions have three operands 1 The file register specified by f 2 The bit in the file register specified by b 3 The accessed memory specified by a The bit field designator b selects the number of the bit affected by the operation while the file register designator f represents the number of the file in which the bit is located The literal instructions may use some of the following Operands A literal value to be loaded into a file register specified by k The desired FSR register to load the literal value into specified by f e No operand required specified by The control instructions may use some of the following Operands A program memory address specified by n The mode of the CALL or RETURN instructions specified by s The mode of the table read and table write instructions specified by m e No operand required specified by All instructions are a single word except for four double word instructions These instructions were made double word to contain the required information in 32 bits In the se
185. sv Nov v A vas T NOOdSS Ul IYLSMOV JIEH puoo s JO geq BuusueiL lt 9 gt ZNOOdSS 14 1Y LSMOV 18819 8AEIS WOI 0 N3S sul6aq uollipuoo yes T NAS lt 0 gt 2NOOdSS SIUM 2004 Microchip Technology Inc iminary Prel DS39632B page 224 PIC18F2455 2550 4455 4550 12CT MASTER MODE WAVEFORM RECEPTION 7 BITADDRESS FIGURE 19 22 NZAMOV In ins S N4dSS sneo q 19S SI NOdSS i I AOdSS nadSS ou p peolun ele slu luo5 A DUE HSASS Olu POS SI1G 121 lt 0 gt ee I JldSS 0 spuodsej 3IdSS pue mewJoS Wx gt 1VLSdSS Pere SIEMIJOS Ul PSIESIO pm S4BMYOS u p 1e9 O AJEMYOS u PSE aJEMYOS u PEIES D Peony ae 10 4108 p 1 y Y Y 1 5 99uenbes 4IdSS DD AOUNOV JO pus JE bes f 9909 JO pu ye Sony bus TE t idrulelu 41dSS 19S A anuon 4IdSS PS 1dnu lui 414SS 19S AI 981 JO pue JE JIdSS 199 M19 40 6p Bulijej uo u sa eq vy 6 8 ZNN sf Y n A xw V 9 W NEJ Ve VEJ 6 8 V o 57 W e lel VL 23 49 SUEJ I I I Serene was JOU SI HOW 1 J9 se u sng I I I as I 1 2 V oq YraXzaxeaXraYsaXoaX2a yo v PN vas 919UY UBNIIM 1 14 N3d T LOMOV vas gouanbas abpajmouyoy HEIS NIMOY 18S Va XraXzaYea raYsaXoaYza sov IV YzgvXevXyvXsvX9vX v 1 Areogeuojne poseejo NOY eAeIS woy EJEG BUINIS
186. that particular oscillator type under standard operating conditions with the device executing code Exceeding these specified limits may result in an unstable oscillator operation and or higher than expected current consumption All devices are tested to operate at min values with an external clock applied to the OSC1 CLKI pin When an external clock input is used the max cycle time limit is DC no clock for all devices DS39632B page 376 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 28 9 PLL CLOCK TIMING SPECIFICATIONS Vpp 4 2V TO 5 5V aaa Sym Characteristic Min Typt Max Units Conditions F10 Fosc Oscillator Frequency Range 4 48 MHz F11 Fsys On Chip VCO System Frequency 96 MHz F12 tre PLL Start up Time Lock Time M 2 ms F13 ACLK CLKO Stability Jitter 0 25 0 25 Data in Typ column is at 5V 25 C unless otherwise stated These parameters are for design guidance only and are not tested TABLE 28 10 AC CHARACTERISTICS INTERNAL RC ACCURACY PIC18F2455 2550 4455 4550 INDUSTRIAL PIC18LF2455 2550 4455 4550 INDUSTRIAL PIC18LF2455 2550 4455 4550 Industrial Operating temperature Standard Operating Conditions unless otherwise stated 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated
187. the SDO data is valid before there is a clock edge on SCK The change of the input sample is shown based on the state of the SMP bit The time when the SSPBUF is loaded with the received data is shown SPI MODE WAVEFORM MASTER MODE Write to SSPBUF J SCK CKP 0 CKE 0 SCK CKP 1 CKE 0 SCK CKP 0 CKE 1 SCK CKP 1 CKE 1 SDO PKO bit7 D bit 6 gt bit 5 gt bit bit 3 X bit 2 gt bit 1 gt bit 0 CKE 0 SDO bit 7 gt bit 6 gt bit 5 gt bit 4 bit 3 X bit 2 X bit 1X bito CKE 1 abt Ce VE nm S eae ay Q G SMP o S V 1 1 1 bit 0 SMP o gni gt aE BY SMF Sa bit 7 ot t t t s ss bit 0 t ft 1 Sample SMP 1 SSPIF SSPSR to SSPBUF 4 Next Q4 Cycle 1 after Q2 DS39632B page 198 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 3 6 SLAVE MODE In Slave mode the data is transmitted and received as the external clock pulses appear on SCK When the last bit is latched the SSPIF interrupt flag bit is set Before enabling the module in SPI Slave mode the clock line must match the proper Idle state The clock line can be observed by reading the SCK pin The ldle state is determined by the CKP bit SSPCON1 lt
188. the result is stored is set Watchdog Timer and its in W If d is 1 the result is stored in postscaler are cleared register f default The processor is put into Sleep mode If a is 0 the Access Bank is with the oscillator stopped selected If a is 1 the BSR is used Words 1 to select the GPR bank default If a is o and the extended instruction Cycles 1 set is enabled this instruction Q Cycle Activity eae in s Offset ressing mode whenever Sa Q2 ae a4 f lt 95 5Fh See Section 26 2 3 Decode No Process Go to Byte Oriented and Bit Oriented operation Data Sleep Instructions in Indexed Literal Offset Mode for details Example SLEEP Words 1 Before Instruction Cycles 1 TO 7 PD Q Cycle Activity After Instruction Q1 Q2 Q3 Q4 TO 1 Decode Read Process Write to PD 0 register f Data destination Example 1 SUBFWB REG 1 0 If WDT causes wake up this bit is cleared Before Instruction REG 9 w 2 G 1 After Instruction RE FF w 2 C 0 Z N 1 resultis negative Example 2 SUBFWB REG 0 0 Before Instruction 2 W 5 G A After Instruction RE 2 w a 3 C d Z 0 N 0 resultis positive Example 3 SUBFWB REG 1 0 Before Instruction 1 W 2 G 0 After Instruction REG 0 w 2 C 1 Z resultis zero N 0 DS39632B page 336 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550
189. the time reguired to charge the capacitor CHOLD The sampling switch RSS impedance varies over the device voltage To calculate the minimum acquisition time Equation 21 1 may be used This equation assumes that 1 2 LSb error is used 1024 steps for the A D The 1 2 LSb error is the maximum error allowed for the A D to meet its specified resolution Example 21 3 shows the calculation of the minimum required acquisition time TACQ This calculation is based on the following application system assumptions VDD The source impedance affects the offset voltage CHOLD 25pF at the analog input due to pin leakage current The Rs 2 5kQ maximum recommended impedance for analog Conversion Error lt 1 2 LSb sources is 2 5 kO After the analog input channel is VDD 5V gt RsS 2kQ selected changed the channel must be sampled for Temperature 85 C system max at least the minimum acquisition time before starting a conversion Note When the conversion is started the holding capacitor is disconnected from the input pin EQUATION 21 1 ACQUISITION TIME TACQ Amplifier Settling Time Holding Capacitor Charging Time Temperature Coefficient TAMP TC TCOFF EQUATION 21 2 A D MINIMUM CHARGING TIME VHOLD VREF VREF 2048 1 eC P CHOLPRIC RSS RS or Tc CHOLD RIC RSS RS In 1 2048 EQUATION 21 3 CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ T
190. the transmission reception will remain in that state until the devices wakes After the device returns to Run mode the module will resume transmitting and receiving data In SPI Slave mode the SPI Transmit Receive Shift register operates asynchronously to the device This allows the device to be placed in any power managed mode and data to be shifted into the SPI Transmit Receive Shift register When all eight bits have been received the MSSP interrupt flag bit will be set and if enabled will wake the device 19 3 9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer 19 3 10 BUS MODE COMPATIBILITY Table 19 1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits TABLE 19 1 SPI BUS MODES Standard SPI Control Bits State Mode Terminology CKP CKE 0 0 0 1 0 1 0 0 1 50 1 1 ly 1 0 There is also an SMP bit which controls when the data is sampled TABLE 19 2 REGISTERS ASSOCIATED WITH SPI OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMRZIF TMRAIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1I
191. to bit error rates Overall system timing and communication baud rates must be taken into consideration when using the Auto Baud Rate Detection feature TABLE 20 4 BRG COUNTER CLOCK RATES BRG16 BRGH BRG Counter Clock 0 0 Fosc 512 0 1 Fosc 128 1 0 Fosc 128 1 1 Fosc 32 Note During the ABD sequence SPBRG and SPBRGH are both used as a 16 bit counter independent of BRG16 setting 20 1 3 1 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisi tion the EUSART transmitter cannot be used during ABD This means that whenever the ABDEN bit is set TXREG cannot be written to Users should also ensure that ABDEN does not become set during a transmit sequence Failing to do this may result in unpredictable EUSART operation DS39632B page 240 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 20 1 AUTOMATIC BAUD RATE CALCULATION BRG Value 7x500 Y 000090 n Edge 1 Edge 2 Edge 3 ppEdge 4 pi Edge 5 RX pin i Start Bto Bit1 Bt2 1 Bit3 Bt4 L Bit5 Bte Bit 7 Stop Bit BRG Clock I I Set by User j Auto Cleared ABDEN bit A
192. to the memory should be verified against the original value This should be used in applications where excessive writes can stress bits near the specification limit 6 5 3 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event such as loss of power or an unexpected Reset the memory location just programmed should be verified and repro grammed if needed If the write operation is interrupted by a MCLR Reset or a WDT Time out Reset during normal operation the user can check the WRERR bit and rewrite the location s as needed WRITES To protect against spurious writes to Flash program memory the write initiate sequence must also be followed See Section 25 0 Special Features of the CPU for more detail 6 6 Flash Program Operation During Code Protection See Section 25 5 Program Verification and Code Protection for details on code protection of Flash program memory TABLE 6 2 REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page TBLPTRU bit 21 Program Memory Table Pointer Upper Byte TBLPTR lt 20 16 gt 51 TBPLTRH Program Memory Table Pointer High Byte TBLPTR lt 15 8 gt 51 TBLPTRL Program Memory Table Pointer Low Byte TBLPTR lt 7 0 gt 51 TABLAT Program Memory Table Latch 51 INTCON GIE GIEH PEIE GIEL TMROIE
193. to the contents of W by stored in W If d is 1 mihe result is performing an unsigned subtraction stored back in register f default If f W then the fetched instruction is If a is 0 the Access Bank is selected discarded and a NOP is executed If a is 1 the BSR is used to select the instead making this a two cycle GPR bank default instruction If a is o and the extended instruction If a is 0 the Access Bank is selected set is enabled this instruction operates If a is a the BSR is used to select the in Indexed Literal Offset Addressing GPR bank default mode whenever lt 95 5Fh See If a is o and the extended instruction Section 26 2 3 Byte Oriented and set is enabled this instruction operates Bit Oriented Instructions in Indexed in Indexed Literal Offset Addressing Literal Offset Mode for details mode whenever f lt 95 5Fh See Words 1 Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed les 1 CHERS R Literal Offset Mode for details Q Cycle g Words 1 2 a 3 at Cycles 1 2 Decode Read Process Write to Note 3 cycles if skip and followed register f Data destination by a 2 word instruction Q Cycle Activity Example COMF REG 0 0 at Q2 Q3 Q4 Before Instruction Decode Read Process No REG 13h register f Data operation After Instruction If skip REG 13h 01 Q2 Q3 Q4 W AE No No No No operation operation operation opera
194. transition interval The SCS bits are cleared on all forms of Reset The Internal Oscillator Frequency Select bits IRCF2 IRCFO select the frequency output of the internal oscillator block to drive the device clock The choices are the INTRC source the INTOSC source 8 MHz or one of the frequencies derived from the INTOSC postscaler 31 kHz to 4 MHz If the internal oscillator block is supplying the device clock changing the states of these bits will have an immediate change on the internal oscil lators output On device Resets the default output frequency of the internal oscillator block is set at 1 MHz When an output frequency of 31 kHz is selected IRCF2 IRCFO 000 users may choose which inter nal oscillator acts as the source This is done with the INTSRC bit in the OSCTUNE register OSCTUNE lt 7 gt Setting this bit selects INTOSC as a 31 25 kHz clock source by enabling the divide by 256 output of the INTOSC postscaler Clearing INTSRC selects INTRC nominally 31 kHz as the clock source This option allows users to select the tunable and more precise INTOSC as a clock source while maintaining power savings with a very low clock speed Regardless of the setting of INTSRC INTRC always remains the clock source for features such as the Watchdog Timer and the Fail Safe Clock Monitor The OSTS IOFS and T1RUN bits indicate which clock source is currently providing the device clock The OSTS bit indicates that the Oscillator
195. type of transfer method allows for large amounts of data to be transferred with ensured data integrity however the delivery timeliness is not ensured Interrupt This type of transfer provides for ensured timely delivery for small blocks of data Plus data integrity is ensured Control This type provides for device setup control While full speed devices support all transfer types low speed devices are limited to interrupt and control transfers only 17 10 4 POWER Power is available from the Universal Serial Bus The USB specification defines the bus power requirements Devices may either be self powered or bus powered Self powered devices draw power from an external source while bus powered devices use power supplied from the bus FIGURE 17 13 USB LAYERS Device To other Configurations if any Configuration To other Interfaces if any Interface Interface Endpoint Endpoint Endpoint Endpoint Endpoint DS39632B page 184 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 The USB specification limits the power taken from the bus Each device is ensured 100 mA at approximately 5V one unit load Additional power may be reguested up to a maximum of 500 mA Note that power above one unit load is a reguest and the host or hub is not obligated
196. u u send nr ua aB iu uwhia hu qayana sa as 65 C to 150 C Voltage on any pin with respect to Vss except VDD MCLR and RA4 a a aaa 0 3V to VDD 0 3V Voltage on VDD WIth TeSPOCttO VSS in honu anal hala 0 3V to 7 5V Voltage on MCLR with respect to VSS Note 2 OV to 13 25V Total power dissipation Note 1 2c sccccsdcc hedeciescasedsnsedigs sbecesin cnvedecnaeacpegedecdsbediedderecsdiasisvenecpducdeansusnessdegenvedecadsceneses 1 0W Maximum current out Of VSS P N sirean reiteeni eeoa deveevdeceeceeceedactesvete TE 300 mA Maximum Current into VDD pir u u W ln nu 250 mA Input clamp current lk VI lt 0 or VI gt VDD eecccscesessesesseseeseseesesecseeseseesesecsesecseseeseeseseesesecseeeseceeseeseseeseeseseeseneeseeees 20 mA Qutputiclamp current ok Vo lt 0 61 VO gt VDD a hriala ha rain a dn 20 mA Maximum output current sunk by any I O pin RR 25 MA Maximum output current sourced by any I O pin sisi 25 mA Maximumicurrent sunk by all ports ini uu o na 200 mA Maximum current sourced by all ports iii 200 mA Note 1 Power dissipation is calculated as follows Pdis VDD x IDD Z IOH Z VDD VOH x lOH gt VOL x IOL 2 Voltage spikes below Vss at the MCLR VPP RE3 pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 100Q should be used when applying a low level to the MCLR VPP RE3 pin rather than pulling this pin directly to VSS N
197. u u u Power Managed Idle or Sleep modes Interrupt Exit from PC 2 ul u u 0 u u u u Power Managed modes Legend u unchanged Note 1 When the wake up is due to an interrupt and the GIEH or GIEL bits are set the PC is loaded with the interrupt vector 008h or 0018h 2 Reset state is 1 for POR and unchanged for all other Resets when software BOR is enabled BOREN1 BORENDO configuration bits 01 and SBOREN 1 otherwise the Reset state is 0 DS39632B page 50 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS MCLR Resets Rogister Applicable Devices foworon est WOT Reset Wakeup via WoT Stack Resets TOSU 2455 2550 4455 4550 0 0000 0 0000 0 uuu TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuul STKPTR 2455 2550 4455 4550 00 0 0000 uu 0 0000 uu u uuu PCLATU 2455 2550 4455 4550 0 0000 0 0000 u uuuu PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC 202 TBLPTRU 2455 2550 4455 4550 00 0000 00 0000 UU uuuu TBLPTRH 245b 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TBLPTRL 24
198. unprogrammed u Unchanged from programmed state DS39632B page 282 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 25 3 CONFIG2L CONFIGURATION REGISTER 2 LOW BYTE ADDRESS 300002h U 0 U 0 R P 0 R P 1 R P 1 R P 1 R P 1 R P 1 VREGEN BORV1 BORVO BOREN1 2 BORENO PNRTEN bit 7 bit 0 bit 7 6 Unimplemented Read as 0 bit 5 VREGEN USB Internal Voltage Regulator Enable bit 1 USB voltage regulator enabled 0 USB voltage regulator disabled bit 43 BORV1 BORVO Brown out Reset Voltage bits 11 Minimum setting 00 Maximum setting bit 2 1 BOREN1 BORENO Brown out Reset Enable bits 2 11 Brown out Reset enabled in hardware only SBOREN is disabled 10 Brown out Reset enabled in hardware only and disabled in Sleep mode SBOREN is disabled 01 Brown out Reset enabled and controlled by software SBOREN is enabled 00 Brown out Reset disabled in hardware and software bitO PWRTEN Power up Timer Enable bit 1 PWRT disabled 0 z PWRT enabled Note 1 See Section 28 0 Electrical Characteristics for the specifications 2 The Power up Timer is decoupled from Brown out Reset allowing these features to be independently controlled Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value when device is unprogrammed u Unchanged from programmed state
199. until the Start condition is complete Write to SEN bit occurs here Set S bit SSPSTAT lt 3 gt SDA 1 x SCL 21 At completion of Start bit hardware clears SEN bit and sets SSPIF bit l TBRG gt TBRG M Write to SSPBUF occurs here DE 1st bit 2nd bit SDA RER i HUS k TBRG gt SCL i A p lt if 2004 Microchip Technology Inc Preliminary DS39632B page 221 PIC18F2455 2550 4455 4550 C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit SSPCON2 lt 1 gt is programmed high and the Ko logic module is in the Idle state When the RSEN bit is set the SCL pin is asserted low When the SCL pin is sam pled low the Baud Rate Generator is loaded with the contents of SSPADD lt 5 0 gt and begins counting The SDA pin is released brought high for one Baud Rate Generator count TBRG When the Baud Rate Genera tor times out if SDA is sampled high the SCL pin will be deasserted brought high When SCL is sampled high the Baud Rate Generator is reloaded with the contents of SSPADD lt 6 0 gt and begins counting SDA and SCL must be sampled high for one TBRG This action is then followed by assertion of the SDA pin SDA 0 for one TBRG while SCL is high Following this the RSEN bit SSPCON2 lt 1 gt will be automatically cleared and the Baud Rate Generator will not be reloaded leaving the SDA pin held low As soon as a
200. value of kz k4 Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write literal literal k Data K to BSR Example MOVLB 5 Before Instruction BSR Register 02h After Instruction BSR Register Il o a a DS39632B page 326 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 MOVLW Move literal to W Syntax MOVLW k Operands 0 lt k lt 255 Operation k gt w Status Affected None Encoding 0000 1110 kkkk kkkk Description The eight bit literal k is loaded into W Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to W literal k Data Example MOVLW 5Ah After Instruction W 5Ah MOVWF Move W to f Syntax MOVWF f a Operands 0 lt f lt 255 ae 0 1 Operation W f Status Affected None Encoding 0110 111a F ES FEFE Description Move data from W to register f Location f can be anywhere in the 256 byte bank If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activ
201. value of zero to the PC and sets the STKUNF bit while the Stack Pointer remains at zero The STKUNF bit will remain set until cleared by software or until a POR occurs Note Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector where the stack conditions can be verified and appropriate actions can be taken This is not the same as a Reset as the contents of the SFRs are not affected 5 1 2 3 PUSH and POP Instructions Since the Top of Stack is readable and writable the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature The PIC18 instruction set includes two instructions PUSH and POP that permit the TOS to be manipulated under software control TOSU TOSH and TOSL can be modified to place data or a return address on the stack The PUSH instruction places the current PC value onto the stack This increments the Stack Pointer and loads the current PC value onto the stack The POP instruction discards the current TOS by decre menting the Stack Pointer The previous value pushed onto the stack then becomes the TOS value REGISTER 5 1 STKPTR STACK POINTER REGISTER R C 0 R C 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 STKFULU STKUNF SP4 SP3 SP2 SP1 SPO bit 7 bit 0 bit 7 STKFUL Stack Full Flag bit 1 Stack became full or overflowed 0 Stack has
202. 0 ns TscL2ssH Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used 2004 Microchip Technology Inc Preliminary DS39632B page 385 PIC18F2455 2550 4455 4550 FIGURE 28 15 IC BUS START STOP BITS TIMING 91 93 92 Note Refer to Figure 28 4 for load conditions TABLE 28 19 IC BUS START STOP BITS REQUIREMENTS SLAVE MODE FIGURE 28 16 IC BUS DATA TIMING DS39632B page 386 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 28 20 IC BUS DATA REQUIREMENTS SLAVE MODE da Symbol Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 4 0 us PIC18FXXXX must operate at a minimum of 1 5 MHz 400 kHz mode 0 6 us PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1 5 TCY 101 TLOW Clock Low Time 100 kHz mode 4 7 us PIC18FXXXX must operate at a minimum of 1 5 MHz 400 kHz mode 1 3 us PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 1 5 Tcy 102 TR SDA and SCL Rise 100 kHz mode 1000 ns Time 400 kHz mode 20 0 1CB 300 ns CBis specified to be from 10 to 400 pF 103 TF SDA and SCL Fall 100 kHz mode 300 ns Time 400 kHz mode 20 0 1 CB 300 ns CBis specified to be from 10 to 400 pF 90 TSU STA Start Condition 100 kHz mode 4 7 us Only relevant for Rep
203. 0 FIGURE 28 14 EXAMPLE SPI SLAVE MODE TIMING CKE 1 SCK CKP 1 SDO SDI Note Refer to Figure 28 4 for load conditions TABLE 28 18 EXAMPLE SPI SLAVE MODE REQUIREMENTS CKE 1 r Symbol Characteristic Min Max Units Conditions 70 TssL2scH SS J to SCK J or SCK T Input Tcy ns TssL2scL 71 TscH SCK Input High Time Continuous 1 25 TCY 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK Input Low Time Continuous 1 25 TCY 30 ns 72A Slave mode Single Byte 40 ns Note 1 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1 5 TCY 40 ns Note 2 74 TscH2dil Hold Time of SDI Data Input to SCK Edge 100 ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 2 0V 76 TdoF SDO Data Output Fall Time 25 ns 77 TssH2doZ SS T to SDO Output High Impedance 10 50 ns 78 TscR SCK Output Rise Time PIC18FXXXX 25 ns Master mode PIC18LFXXXX 45 ns VoD 2 0V 79 TscF SCK Output Fall Time Master mode 25 ns 80 TscH2doV SDO Data Output Valid after SCK PIC18FXXXX 50 ns TscL2doV Edge PIC18LFXXXX 100 ns Vpp 2 0V 82 TssL2doV SDO Data Output Valid after SS L PIC18FXXXX 50 ns Edge PIC18LFXXXX 100 ns Vpp 2 0V 83 TscH2ssH SS T after SCK Edge 1 5 Toy 4
204. 0 HA 85 C PIC18LFX455 X550 2 5 12 HA 40 C 3 7 12 uA 25 C VDD 2 0V 4 5 12 uA 85 C PIC18LFX455 X550 5 0 15 uA 40 C Fosc 32 kHz 3 5 4 15 uA 25 C VDD 3 0V SEC_IDLE mode 6 3 15 uA 85 C Timer1 as clock All devices 8 5 25 uA 40 C 9 0 25 uA 25 C VDD 5 0V 10 5 36 uA 85 C Legend Shading of rows is to assist in readability of the table Note 1 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or Vss MCLR VDD WDT enabled disabled as specified 3 Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specificatio
205. 0 Write Note This bit holds the RAN bit information following the last address match This bit is only valid from the address match to the next Start bit Stop bit or not ACK bit In Master mode 1 Transmit is in progress 0 Transmit is not in progress Note ORing this bit with SEN RSEN PEN RCEN or ACKEN will indicate if the MSSP is in Idle mode UA Update Address bit 10 bit Slave mode only 1 Indicates that the user needs to update the address in the SSPADD register 0 Address does not need to be updated BF Buffer Full Status bit In Transmit mode 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty In Receive mode ia 1 Data transmit in progress does not include the ACK and Stop bits SSPBUF is full 0 Data transmit complete does not include the ACK and Stop bits SSPBUF is empty Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 203 PIC18F2455 2550 4455 4550 REGISTER 19 4 SSPCON1 MSSP CONTROL REGISTER 1 1 C MODE R W 0 R W 0 RMW 0 R W 0 R W 0 R W 0 R W 0 R W 0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO bit 7 bit 0 bit 7 WCOL Write Collision Detect bit In Master Transmit mode 1 A write to the SSPBUF register was attempted wh
206. 0 BIT ADDRESS FIGURE 19 14 payepdn 8q 0 speeu qavdss yey Buneoipui jes SI VN p Bulle 1oye sseuppe jo 9 4g abpe Bulle saye ss ippe Jo 914g payepdn y6iy UJIM perepdn si qqvqdSS MOJ yum poJepdn s GavdSS eq 0 Spesu qqvdSS SU USUM SJEMPIEY Aq pejesj9 4 u ym arempsey Aq peueej9 7 F yeu Buneolpui jes S VN lt L gt 1VLSdSS vn Bel 4g 12919 0 HSdSS Jo slu juoo 3 8dSS jo pees Auuunq q T Humuenmsiodngdss lt 0 gt 1v1SdSS 44 AJEMYOS u poJeSejJ 1 lt gt Luld 414SS 49JSUEJ SOJEUIWS dajsew sng aJEMYOs u pasea Y RU EPA EN WAP PEN P y u TEE PER PV PP EP ATA ET N hos M yoa a Xea ea va salsa za yov 00 tg Yza ea va sa Yoa za yow v Yiv Yew ev yw sv jov X w 7 r Vev Yow YoY iY rye Ye A tt ov eMg EJEG SAlEosy 914g 2q 3A199094 ssauppy Jo 9144 puo58S SN1999H ssalppy JO 94g 15114 9418094 lt qs 9oe d USMEJ seu qavdss Jo lepdn HUN Mo pj y S 49019 DS39632B page 215 Iminary Prel 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 5 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the 1 C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master The exception is the general call address which can address all devices Whe
207. 00 0000 1010 None TBLRD Table Read with pre increment 0000 0000 0000 1011 None TBLWT Table Write 2 0000 0000 0000 1100 None TBLWT Table Write with post increment 0000 0000 0000 1101 None TBLWT Table Write with post decrement 0000 0000 0000 1110 None TBLWT Table Write with pre increment 0000 0000 0000 1111 None Note 1 When a Port register is modified as a function of itself e g MOVF PORTB 1 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a o 2 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned 3 If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP 4 Some instructions are two word instructions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction DS39632B page 306 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 26 1 1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD V to f Syntax ADDLW
208. 000 ADDWF REG3 continue code CASE 2 Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 Yes execute this word WIWI OO OO O 2nd word of instruction 0010 0100 0000 0000 ADDWF REG3 continue code DS39632B page 62 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 5 3 Data Memory Organization Note The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled See Section 5 6 Data Memory and the Extended Instruction Set for more information The data memory in PIC18 devices is implemented as static RAM Each register in the data memory has a 12 bit address allowing up to 4096 bytes of data memory The memory space is divided into as many as 16 banks that contain 256 bytes each PIC18F2455 2550 4455 4550 devices implement 8 com plete banks for a total of 2048 bytes Figure 5 5 shows the data memory organization for the devices The data memory contains Special Function Registers SFRs and General Purpose Registers GPRs The SFRs are used for control and status of the controller and peripheral functions while GPRs are used for data storage and scratchpad operations in the user s application Any read of an unimplemented location will read as 0 s The instruction set and architecture allow operations across all banks The entire data memory
209. 000 0 00 0000 u uu uuuu Legend u unchanged x unknown unimplemented bit read as 0 g value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 2 Oneor more bits in the INTCONx or PIRx registers will be affected to cause wake up 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 4 See Table 4 3 for Reset value for specific condition 5 PORTA lt 6 gt LATA lt 6 gt and TRISA lt 6 gt are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 DS39632B page 52 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Applicable Devices BrownoutReset RESET Instruction orinterrupt Stack Resets CCPRIH 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu CCPR1L 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu CCP1CON 2455 2550 4455 4550 00 0000 00 0000 uu uuuu 2455
210. 000 bbbo kkkk kkkk Description The contents of W are added to the Description Bit b of the register indicated by FSR2 contents of the register indicated by offset by the value k is set FSR2 offset by the value k Words 1 If is 0 the result is stored in W If d is 1 the result is stored back in Cycles 1 register f default Q Cycle Activity Words 1 Q1 Q2 Q3 Q4 Cycles 1 Decode Read Process Write to fete register f Data destination Q Cycle Activity Q1 Q2 Q3 Q4 Example BSF FLAG OFST 7 Decode Read k Process Write to Before Instruction Data destination FLAG OFST OAh FSR2 OAOOh Example ADDWF OFST 0 Contents Before of 0A0Ah 55h i k v nstruction n After Instruction OFST gt 20h Contents ESR2 OAO0Oh of OAOAh D5h Contents of OA2Ch 20h After Instruction W 37h Contents DE SETF Set Indexed of 0A2Ch 20 Indexed Literal Offset mode Syntax SETF k Operands 0 lt k lt 95 Operation FFh gt FSR2 k Status Affected None Encoding 0110 1000 kkkk kkkk Description The contents of the register indicated by FSR2 offset by k are set to FFh Words 1 Cycles 1 Q Cycle Activity Q1 Q2 03 04 Decode Read k Process Write Data register Example SETF OFST Before Instruction OFST 2Ch FSR2 OAOOh Contents of OA2Ch 00h After Instruction Contents of OA2Ch FFh 2004 Microchip Technology Inc Preliminary DS39632B page 349 PIC18F2455
211. 00a EEEF EEEE Description The contents of the specified register are set to FFh If a is o the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example SETF REG 1 Before Instruction REG 5Ah After Instruction REG FFh 2004 Microchip Technology Inc Preliminary DS39632B page 335 PIC18F2455 2550 4455 4550 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax SLEEP Syntax SUBFWB f df a Operands None Operands 0 lt f lt 255 Operation 00h gt WDT de 0 1 0 gt WDT postscaler ae 0 1 a 1 TO Operation W f C gt dest PERTE Status Affected N OV C DC Z Status Affected ro Encoding 0101 olda fff Encoding 9999 5900 5909 Gort Description Subtract register and Carry flag Description The Power Down status bit PD is _ borrow from W 2 s complement cleared The Time out status bit TO method If d is o
212. 01 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example XORWF REG 1 0 Before Instruction REG AFh W B5h After Instruction REG 1Ah w B5h DS39632B page 342 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 26 2 Extended lnstruction Set In addition to the standard 75 instructions of the PIC18 instruction set PIC18F2455 2550 4455 4550 devices also provide an optional extension to the core CPU functionality The added features include eight addi tional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions The additional features of the extended instruction set are disabled by default To enable them users must set the XINST configuration bit The instructions in the extended set can all be classified as literal operations which either manipulate the File Select Registers or use them for indexed addressing Two of the instructions ADDFSR and SUBFSR each have an additional special instantiation for using FSR2 These versions ADDULNK and SUBULNK allow for automatic return after execution The extended instructions are specifically implemented to optimize re entrant program code that is code that is recursive or that uses a software stack written in high level languages particularly C Among other things they allow us
213. 1 Compare mode trigger special event CCP1 resets TMR1 or TMR3 sets CCP1IF bit 1100 PWM mode P1A P1C active high P1B P1D active high 1101 PWM mode P1A P1C active high P1B P1D active low 1110 PWM mode PIA P1C active low P1B P1D active high 1111 PWM mode PIA P1C active low P1B P1D active low Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 149 PIC18F2455 2550 4455 4550 In addition to the expanded range of modes available through the CCP1CON register the ECCP module has two additional registers associated with Enhanced PWM operation and auto shutdown features They are e ECCP1DEL Dead Band Delay e ECCP1AS Auto Shutdown Configuration 16 1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs depending on the selected operating mode These outputs designated PIA through PID are multiplexed with I O pins on PORTC and PORTD The outputs that are active depend on the CCP operating mode selected The pin assignments are summarized in Table 16 1 To configure the I O pins as PWM outputs the proper PWM mode must be selected by setting the P1M1 P1MO and CCP1M3 CCP1MO bits The appropriate TRISC and TRISD direction bits for the port pins must also be set as outputs 16 1 1 E
214. 1 Enhanced PWM output channel B takes priority over port and SPP data RD6 SPP6 P1C RD6 0 OUT DIG LATD lt 6 gt data output 1 IN ST PORTD lt 6 gt data input SPP6 1 OUT DIG SPP lt 6 gt output data takes priority over port data 1 IN TTL SPP lt 6 gt input data P1C 0 OUT DIG ECCP1 Enhanced PWM output channel C takes priority over port and SPP data RD7 SPP7 P1D RD7 0 OUT DIG LATD lt 7 gt data output 1 IN ST PORTD lt 7 gt data input SPP7 1 OUT DIG SPP lt 7 gt output data takes priority over port data 1 IN TTL SPP lt 7 gt input data PID 0 OUT DIG ECCP1 Enhanced PWM output channel D takes priority over port and SPP data Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input TTL TTL Buffer Input Note 1 May be configured for tri state during Enhanced PWM shutdown events 2004 Microchip Technology Inc Preliminary DS39632B page 121 PIC18F2455 2550 4455 4550 TABLE 10 8 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bito Values on page PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO 54 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATDO 54 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISDO 54 PORTE RDPU RE3 12 RE26 RE1 REO 54 CCP1CON Pim1 P1MO DC1B1 DCIBO CCP1M3 CCPiM2 CCP1M1 C
215. 1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example RLNCF REG 1 0 Before Instruction REG 1010 1011 After Instruction REG 0101 0111 RRCF Rotate Right f through Carry Syntax RRCF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation f lt n gt gt dest lt n 1 gt f lt 0 gt gt C C dest lt 7 gt Status Affected C N Z Encoding 0011 00da FEEF FEEF Description The contents of register f are rotated one bit to the right through the Carry flag If d is o the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details C register f jaa Words 1 Cycles 1 Q Cycle Activity Q1 Q2 03 Q4 Decode Read Process Write to register f Data destination Example RRCF REG 0 0 Before Instruction REG 1110 0110 C 0 After Instruction REG 1110 0110 w 0111 0011 C 0 DS39632B page 334 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 445
216. 18F2455 2550 4455 4550 IORWE saa l A au nanus 324 IPR REJIS OrS s u Sau aaa qaq 106 L CESR sas au s 325 Low Voltage ICSP Programming See Single Supply ICSP Programming M Master Clear Reset MCLR eeeeseeeneeeneeeeee 45 Master Synchronous Serial Port MSSP See MSSP Memory Organization a 57 Data Memory u 63 Program Memory ss 57 RETLW Memory Programming Requirements s nsnnsnsssneineeeeeee 370 Migration from Baseline to Enhanced Devices ss 406 Migration from High End to Enhanced Devices ss 407 Migration from Mid Range to Enhanced Devices a 407 MOM WE parece mm a nr a der 327 MPLAB ASM30 Assembler Linker Pibrarianty sk AAA k n a a kusha dint 352 MPLAB ICD 2 In Circuit Debugger 353 MPLAB ICE 2000 High Performance Universal In Circuit Emulator 353 MPLAB ICE 4000 High Performance INTCON Register Universal In Circuit Emulator 353 RBIEBIUEZ a ua ana Pade 114 MPLAB Integrated Development INT ON R gisters u ana aaa Du aS 99 Environment Software a 351 Inter Integrated Circuit See l2C MPLAB PM3 Device Programmer 353 Internal Oscillator Block aaa 27 MPLINK Object Linker MPLIB Object Librarian 352 Adjust
217. 18F2455 2550 4455 4550 REGISTER 25 11 CONFIG7L CONFIGURATION REGISTER 7 LOW BYTE ADDRESS 30000Ch U 0 U 0 U 0 U 0 R C 1 R C 1 R C 1 R C 1 EBTR3 EBTR2 EBTR1 EBTRO bit 7 bit O bit 7 4 Unimplemented Read as 0 bit3 EBTR3 Table Read Protection bit 1 Block 3 006000 007FFFh not protected from table reads executed in other blocks 0 Block 3 006000 007FFFh protected from table reads executed in other blocks Note 1 Unimplemented in PIC18FX455 devices maintain this bit set bit 2 EBTR2 Table Read Protection bit 1 Block 2 004000 005FFFh not protected from table reads executed in other blocks 0 Block 2 004000 005FFFh protected from table reads executed in other blocks bit 1 EBTR1 Table Read Protection bit 1 Block 1 002000 003FFFh not protected from table reads executed in other blocks 0 Block 1 002000 003FFFh protected from table reads executed in other blocks bit 0 EBTRO Table Read Protection bit 1 Block 0 000800 001FFFh not protected from table reads executed in other blocks 0 Block 0 000800 001FFFh protected from table reads executed in other blocks Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state REGISTER 25 12 CONFIG7H CONFIGURATION REGISTER 7 HIGH BYTE ADDRESS 30000Dh U 0 R C 1 U 0 U 0 U 0 U 0 U 0 U 0 EBTRB bit 7 bit O
218. 1INV 0 1 C1 VIN gt C1 VIN 0 C1 VIN lt C1 VIN When C1INV 1 1 C1 VIN lt C1 VIN 0 C1 VIN gt C1 VIN bit 6 bit 5 1 C2 output inverted 0 C2 output not inverted bit 4 1 C1 output inverted o C1 output not inverted bit 3 CIS Comparator Input Switch bit When CM2 CMO 110 1 C1 VIN connects to RA3 AN3 C2 VIN connects to RA2 AN2 o C1 VIN connects to RAO ANO C2 VIN connects to RA1 AN1 CM2 CMO Comparator Mode bits bit 2 0 bit 0 C2INV Comparator 2 Output Inversion bit C1INV Comparator 1 Output Inversion bit Figure 22 1 shows the Comparator modes and CM2 CMO bit settings Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 263 PIC18F2455 2550 4455 4550 22 1 Comparator Configuration There are eight modes of operation for the compara tors shown in Figure 22 1 Bits CM2 CMO of the CMCON register are used to select these modes The TRISA register controls the data direction of the comparator pins for each mode If the Comparator mode is changed the comparator output level may not be valid for the specified mode change delay shown in Section 28 0 Electrical Characteristics Note Comparator interrupts should be disabled during a Comparator mode change Otherwise a fals
219. 1x Internal oscillator block 01 Timer1 oscillator 00 Primary oscillator Note 1 Depends on the state of the IESO configuration bit 2 Source selected by the INTSRC bit OSCTUNE lt 7 gt see text 3 Default output frequency of INTOSC on Reset Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 32 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 2 5 Effects of Power Managed Modes on the Various Clock Sources When PRI IDLE mode is selected the designated primary oscillator continues to run without interruption For all other power managed modes the oscillator using the OSC1 pin is disabled Unless the USB module is enabled the OSC1 pin and OSC2 pin if used by the oscillator will stop oscillating In secondary clock modes SEC RUN and SEC IDLE the Timer1 oscillator is operating and providing the device clock The Timer1 oscillator may also run in all power managed modes if reguired to clock Timer1 or Timers In internal oscillator modes RC_RUN and RC_IDLE the internal oscillator block provides the device clock source The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features regardless of the power managed mode see Section 25 2 Watchdog Timer WDT Section 25 3 Two Speed
220. 205 SSPSTAT MSSP Status IC Mode 203 SSPSTAT MSSP Status SPI Mode 194 Stat Ssk u reese a aaas ord STKPTR Stack Pointer 59 TOCON TimerO Control a 125 T1CON Timer 1 Control T2CON Timer2 Control T3CON Timer3 Control TXSTA Transmit Status and Control UCFG USB Configuration UCON USB Control oo eee eee eeeteeees UEIE USB Error Interrupt Enable UEIR USB Error Interrupt Status UEPn USB Endpoint n Control 169 UIE USB Interrupt Enable UIR USB Interrupt Status USTAT USB Status WDTCON Watchdog Timer Control RESET s usu aa umasa a ma aaa vies OEE Reset State of Registers Resets a Brown out Reset BOR a Oscillator Start up Timer OST Power on Reset POR Power up Timer PWRT a RET EIB sine ennemie and Associated Registers Return Stack Pointer STKPTR Revision History RLGF ini SEC IDLE Mode SEC RUN Mode Serial Clock SCK u n n no Sus on aai 193 Serial Data In SDI states dire 193 Serial
221. 21 UOE 112 17 1 RC6 TX CK RC2 CCP1 lt gt lt gt RC5 D VP VUSB RC4 D VM 40 Pin PDIP MCLR VPP RE3 RB7 KBI3 PGD RAO ANO RB6 KBI2 PGC RA1 AN1 RB5 KBI1 PGM RA2 AN2 VREF CVREF RB4 AN11 KBI0 CSSPP RA3 AN3 VREF RB3 AN9 CCP2 VPO RA4 TOCKI C1OUT RCV RB2 AN8 INT2 VMO RA5 AN4 SS HLVDIN C2OUT RB1 AN10 INT1 SCK SCL REO AN5 CK1SPP RBO AN12 INTO FLTO SDI SDA RE1 AN6 CK2SPP VDD RE2 AN7 OESPP Vss VDD RD7 SPP7 P1D Vss RD6 SPP6 P1C OSC1 CLKI RD5 SPP5 P1B OSC2 CLKO RA6 RD4 SPP4 RCO T10SO T13CKI RC7 RX DT SDO RC1 T1OSICCP2 U UOE RC6 TX CK RC2 CCP1 P1A RC5 D VP VUSB RC4 D VM RDO SPPO RD3 SPP3 RD1 SPP1 RD2 SPP2 DS39632B page 2 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 Pin Diagrams Continued 44 Pin TQFP RC7 RX DT SDO lt RD4 SPP4 lt gt RD5 SPP5 P1B RD6 SPP6 P1C Vss VDD RBO AN12 INTO FLTO SDI SDA RB1 AN10 INT1 SCK SCL RB2 AN8 INT2 VMO RB3 AN9 CCP2 VPO 44 Pin QFN HE 00 ID LL Ne N g a S OSSONre AUS 71000 Ore BGU OB SAFSATA B0900000 3000 adca rm gt x FNN O LO S ST sf F lt C 0 CO CO C TEE 2 o 33 NC
222. 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu CCPR2H 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu CCPR2L 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu CCP2CON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu BAUDCON 2455 2550 4455 4550 01 0 0 00 01 0 0 00 uu u u uu ECCP1DEL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu ECCP1AS 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu CVRCON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu CMCON 2455 2550 4455 4550 0000 0111 0000 0111 uuuu uuuu TMR3H 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu TMR3L 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu T3CON 2455 2550 4455 4550 0000 0000 uuuu uuuu uuuu uuuu SPBRGH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu SPBRG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu RCREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TXREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TXSTA 2455 2550 4455 4550 0000 0010 0000 0010 uuuu uuuu RCSTA 2455 2550 4455 4550 0000 000x 0000 000x uuuu uuuu EEADR 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu EEDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu EECON2 2455 2550 4455 4550 0000 0000 0000 0000 0000 0000 EECON1 2455 2550 4455 4550 xx 0 x000 uu 0 u000 uu 0 u000 Legend u unchanged x unknown unimplemented bit read as 0 g value depends on condition S
223. 2550 4455 4550 26 2 5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB IDE TOOLS The latest versions of Microchip s software tools have been designed to fully support the extended instruction set of the PIC18F2455 2550 4455 4550 family of devices This includes the MPLAB C18 C compiler MPASM Assembly language and MPLAB Integrated Development Environment IDE When selecting a target device for software development MPLAB IDE will automatically set default configuration bits for that device The default setting for the XINST configuration bit is 0 disabling the extended instruction set and Indexed Literal Offset Addressing mode For proper execution of applications developed to take advantage of the extended instruction set XINST must be set during programming To develop software for the extended instruction set the user must enable support for the instructions and the Indexed Addressing mode in their language tool s Depending on the environment being used this may be done in several ways A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project e A command line option e A directive in the source code These options vary between different compilers assemblers and development environments Users are encouraged to review the documentation accompany ing their development systems for the appropriate information DS39632B page 350
224. 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump 01 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BNZ Jump address HERE After Instruction If Overflow PC If Overflow PC 0 address Jump 1 address HERE 2 If Zero P If Zero P 0 address Jump 1 address HERE 2 DS39632B page 312 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 Before Instruction PC After Instruction PC address HERE address Jump BRA Unconditional Branch Syntax BRA n Operands 1024 lt n lt 1023 Operation PC 2 2n gt PC Status Affected None Encoding 1101 Onnn nnnn nnnn Description Add the 2 s complement number 2n to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is a two cycle instruction Words 1 Cycles 2 Q Cycle Activity 01 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation Example HERE BRA Jump BSF Bit Set f Syntax BSF f b a Operands 0 lt f lt 255 O0 lt b lt 7 ae 0 1 Operation 1
225. 4 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers This board provides the basis for future USB products 27 25 Evaluation and Programming Tools In addition to the PICDEM series of circuits Microchip has a line of evaluation kits and demonstration software for these products KEELOO evaluation and programming tools for Microchip s HCS Secure Data Products CAN developers kit for automotive network applications Analog design boards and filter design software PowerSmart battery charging evaluation calibration kits IrDA development kit microlD development and rfLab development software e SEEVALS designer kit for memory evaluation and endurance calculations PICDEM MSC demo boards for Switching mode power supply high power IR driver delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits 2004 Microchip Technology Inc Preliminary DS39632B page 355 PIC18F2455 2550 4455 4550 NOTES A rs Css rnnF r r r F F sy DS39632B page 356 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 28 0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias ori hatte ee a p ahus tite 40 C to 85 G Storage temperature ie
226. 4 gt P1M1 P1M0 CCP1M3 CCP1M0 yeye A 2 4 CCPRIL CCP1 P1A ee X CCP1 P1A TRISD lt 4 gt CCPR1H Slave u PB P NX PIB Output TRISD lt 5 gt Comparator R Q Controller Pe gt A ic TMR2 Note 1 T s TRISD lt 6 gt P1D Comparator a Ti gt x PID ear Timer LS set CCP1 pin and ZN RISD s 2 4 latch D C PRZ ECCP1DEL Note The 8 bit TMR2 register is concatenated with the 2 bit internal Q clock or 2 bits of the prescaler to create the 10 bit time base 2004 Microchip Technology Inc Preliminary DS39632B page 151 PIC18F2455 2550 4455 4550 16 4 2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRIL register and to the CCP1CON lt 5 4 gt bits Up to 10 bit resolution is available The CCPR1L contains the eight MSbs and the CCP1CON lt 5 4 gt contains the two LSbs This 10 bit value is represented by CCPR1L CCP1CON lt 5 4 gt The PWM duty cycle is calculated by the following equation EQUATION 16 2 PWM Duty Cycle CCPRIL CCP1CON lt 5 4 gt Tosc TMR2 Prescale Value CCPRIL and CCP1CON lt 5 4 gt can be written to at any time but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs i e the period is complete In PWM mode CCPR1H is a read only register The CCPRIH register and a 2 bit internal latch are used to double buffer the PWM duty cycle This double buffering is essential for glitchless PWM opera tion When the CCPR1H
227. 5 4550 RRNCF Syntax Operands Operation Status Affected Rotate Right f no carry RRNCF f d a 0 lt f lt 255 de 0 1 ae 0 1 f lt n gt gt dest lt n 1 gt f lt 0 gt gt dest lt 7 gt N Z Encoding 0100 00da FEEF EEEE Description The contents of register f are rotated one bit to the right If d is 0 the result is placed in W If is 1 the result is placed back in register f default If a is 0 the Access Bank will be selected overriding the BSR value If a is 1 then the bank will be selected as per the BSR value default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details register f eal Words 1 Cycles 1 Q Cycle Activity 01 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example 1 RRNCF REG 1 0 Before Instruction REG 1101 0111 After Instruction REG 1110 1011 Example 2 RRNCF REG 0 0 Before Instruction W REG z 1101 0111 After Instruction W 1110 1011 REG 1101 0111 SETF Set f Syntax SETF f a Operands 0 lt f lt 255 ae 0 1 Operation FFh f Status Affected None Encoding 0110 1
228. 5 4550 TABLE 28 22 MASTER SSP IC BUS DATA REQUIREMENTS Param No Symbol Characteristic Min Max Units Conditions 100 THIGH Clock High Time 100 kHz mode 2 Tosc BRG 1 ms 400 kHz mode 2 Tosc BRG 1 ms 1 MHz model 2 Tosc BRG 1 ms 101 TLOW Clock Low Time 100 kHz mode 2 Tosc BRG 1 ms 400 kHz mode 2 Tosc BRG 1 ms 1 MHz model 2 Tosc BRG 1 ms 102 TR SDA and SCL 100 kHz mode 1000 ns CBis specified to be from Rise Time 400 kHz mode 20 0 1 CB 300 ns 10 to 400 pF 1 MHz mode gt 300 ns 103 TF SDA and SCL 100 kHz mode 300 ns CB is specified to be from Fall Time 400 kHz mode 20 0 1 CB 300 ns 10 to 400 pF 1 MHz mode 100 ns 90 TSU STA Start Condition 100 kHz mode 2 Tosc BRG 1 ms Only relevant for Setup Time 400 kHz mode 2 Tosc BRG 1 ms Repeated Start 1 MHz mode 2 ToscBRG 1 ms nation 91 THD STA Start Condition 100 kHz mode 2 Tosc BRG 1 ms After this period the first Hold Time 400 kHz mode 2 Tosc BRG 1 ms clock pulse is generated 1 MHz mode 2 Tosc BRG 1 ms 106 THD DAT Data Input 100 kHz mode 0 ns Hold Time 400 kHz mode 0 0 9 ms 107 TSU DAT Data Input 100 kHz mode 250 ns Note 2 Setup Time 400 kHz mode 100 ns 92 TSU STO Stop Condit
229. 55 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu PRODH 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu PRODL 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuu INTCON2 2455 2550 4455 4550 iiti 1 1 aie Z uuuu u u INTCON3 2455 2550 4455 4550 11 0 0 00 11 0 0 00 uu u u uuf INDFO 2455 2550 4455 4550 N A N A N A POSTINCO 245b 2550 4455 4550 N A N A N A POSTDECO 245b 2550 4455 4550 N A N A N A PREINCO 2455 2550 4455 4550 N A N A N A PLUSW0 2455 2550 4455 4550 N A N A N A FSROH 2455 2550 4455 4550 0000 0000 uuuu FSROL 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu WREG 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu INDF1 2455 2550 4455 4550 N A N A N A POSTINCI 2455 2550 4455 4550 N A N A N A POSTDECI 2455 2550 4455 4550 N A N A N A PREINCI 245b 2550 4455 4550 N A N A N A PLUSW1 2455 2550 4455 4550 N A N A N A FSR1H 2455 2550 4455 4550 0000 0000 uuuu FSRIL 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu BSR 2455 2550 4455 4550 0000 0000 uuuu Legend u unchanged x unknown unimplemented bit read as 0 q value depends on condition Shaded cells indicate conditions do not apply for the designated device Note 1 When the wake up is due
230. 55 2550 4455 4550 REGISTER 2 1 OSCTUNE OSCILLATOR TUNING REGISTER R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 INTSRC TUN4 TUN3 TUN2 TUN1 TUNO bit 7 bit 0 bit 7 INTSRC Internal Oscillator Low Frequency Source Select bit 1 31 25 kHz device clock derived from 8 MHz INTOSC source divide by 256 enabled 0 31 kHz device clock derived directly from INTRC internal oscillator bit 6 5 Unimplemented Read as bit 4 0 TUN4 TUNO Frequency Tuning bits 01111 Maximum frequency 00001 00000 Center frequency Oscillator module is running at the calibrated frequency 11111 10000 Minimum frequency Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2 2 5 4 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register This has no effect on the INTRC clock source frequency Tuning the INTOSC source requires knowing when to make the adjustment in which direction it should be made and in some cases how large a change is needed When using the EUSART for example an adjustment may be required when it begins to generate framing errors or receives data with errors while in Asynchronous mode Framing errors indicate that the device clock frequency is too high to adjust for this decrement the value in OSCTUNE to reduce the clock frequency
231. 550 9 2 3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes Instruc tions are stored as two bytes or four bytes in program memory The Least Significant Byte of an instruction word is always stored in a program memory location with an even address LSb 0 To maintain alignment with instruction boundaries the PC increments in steps of 2 and the LSb will always read o see Section 5 1 1 Program Counter Figure 5 4 shows an example of how instruction words are stored in the program memory The CALL and GOTO instructions have the absolute program memory address embedded into the instruc tion Since instructions are always stored on word boundaries the data contained in the instruction is a word address The word address is written to PC lt 20 1 gt which accesses the desired byte address in program memory Instruction 2 in Figure 5 4 shows how the instruction GOTO 0006h is encoded in the program memory Program branch instructions which encode a relative address offset operate in the same manner The offset value stored in a branch instruction represents the number of single word instructions that the PC will be offset by Section 26 0 Instruction Set Summary provides further details of the instruction set FIGURE 5 4 INSTRUCTIONS IN PROGRAM MEMORY Word Address LSB 1 LSB 0 Program Memory 000000h Byte Locations 000002
232. 6 3 81 4 06 Base to Seating Plane A1 015 0 38 Shoulder to Shoulder Width E 595 600 625 15 11 15 24 15 88 Molded Package Width E1 530 545 560 13 46 13 84 14 22 Overall Length D 2 045 2 058 2 065 51 94 52 26 52 45 Tip to Seating Plane L 120 130 135 3 05 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 030 050 070 0 76 1 27 1 78 Lower Lead Width B 014 018 022 0 36 0 46 0 56 Overall Row Spacing eB 620 650 680 15 75 16 51 17 27 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 2004 Microchip Technology Inc Preliminary DS39632B page 401 PIC18F2455 2550 4455 4550 44 Lead Plastic Thin Guad Flatpack PT 10x10x1 mm Body 1 0 0 10 mm Lead Form TGFP Footprint Reference F 039 1 00 Pin 1 Corner Chamfer CH 025 035 045 0 64 0 89 1 14 Controlling Parameter Notes Dimensions D1 and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 026 Drawing No C04 076 DS39632B page 402 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 44 Lead Plastic Quad Flat No Lead Package ML 8x8 mm Body GFN Contact Width B 008 Controlling Parameter Notes 1 2 Drawing No C04 103 OE OD DSO DDS rr s rr r c r rr mm ir 2004 Microchip Technology Inc Preliminary DS39632B pa
233. 6 bit micro controller market The MPLAB IDE is a Windows based application that contains An interface to debugging tools simulator programmer sold separately emulator sold separately in circuit debugger sold separately A full featured editor with color coded context A multiple project manager e Customizable data windows with direct edit of contents e High level source code debugging e Mouse over variable inspection e Extensive on line help The MPLAB IDE allows you to Edit your source files either assembly or C One touch assemble or compile and download to PICmicro emulator and simulator tools automatically updates all project information e Debug using Source files assembly or C mixed assembly and C machine code MPLAB IDE supports multiple debugging tools in a single development paradigm from the cost effective simulators through low cost in circuit debuggers to full featured emulators This eliminates the learning curve when upgrading to tools with increasing flexibility and power 27 2 MPASM Assembler The MPASM assembler is a full featured universal macro assembler for all PICmicro MCUs The MPASM assembler generates relocatable object files for the MPLINK object linker Intel standard HEX files MAP files to detail memory usage and symbol ref erence absolute LST files that contain source lines and generated machine code and COFF files for debugging The MPASM
234. 632B page 256 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 The value in the ADRESH ADRESL registers is not modified for a Power on Reset The ADRESH ADRESL registers will contain unknown data after a Power on Reset After the A D module has been configured as desired the selected channel must be acquired before the con version is started The analog input channels must have their corresponding TRIS bits selected as an input To determine acguisition time see Section 21 1 A D Acquisition Requirements After this acguisi tion time has elapsed the A D conversion can be started An acguisition time can be programmed to 5 Wait for A D conversion to complete by either Polling for the GO DONE bit to be cleared OR e Waiting for the A D interrupt 6 Read A D Result registers ADRESH ADRESL clear bit ADIF if required 7 For next conversion go to step 1 or step 2 as required The A D conversion time per bit is defined as TAD A minimum wait of 3 TAD is required before the next acquisition starts occur between setting the GO DONE bit and the actual FIGURE 21 2 A D TRANSFER FUNCTION start of the conversion The following steps should be followed to perform an 3FFh A D conversion 1 Configure the A D module 3FEh Configure analog pins voltage reference and i digital I O ADCON1 6 Select A D input channel
235. 7 bit 0 bit 7 PRSEN PWM Restart Enable bit 1 Upon auto shutdown the ECCPASE bit clears automatically once the shutdown event goes away the PWM restarts automatically 0 Upon auto shutdown ECCPASE must be cleared in software to restart the PWM bit 6 0 PDC6 PDCO PWM Delay Count bits Delay time in number of Fosc 4 4 Tosc cycles between the scheduled and actual time for a PWM signal to transition to active Note 1 Reserved on 28 pin devices maintain these bits clear Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 158 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 16 3 ECCP1AS ENHANCED CAPTURE COMPARE PWM AUTO SHUTDOWN CONTROL REGISTER R W 0 R W 0 R W 0 RW 0 RW 0 RW 0 R W 0 R W 0 ECCPASE ECCPAS2 ECCPAS1 ECCPASO PSSAC1 PSSACO PSSBD1 1 PSSBDO bit 7 bit 0 bit 7 ECCPASE ECCP Auto Shutdown Event Status bit 1 A shutdown event has occurred ECCP outputs are in shutdown state 0 ECCP outputs are operating bit 6 4 ECCPAS2 ECCPASO ECCP Auto Shutdown Source Select bits 111 FLTO or Comparator 1 or Comparator 2 110 FLTO or Comparator 2 101 FLTO or Comparator 1 100 FLTO 011 Either Comparator 1 or 2 010 Comparator 2 output 001 Comparator 1 output 000 Auto shutdown is disabled bit 3 2 PSSAC1 PSSACO Pins
236. 83 9 58 2 115 2 125 000 8 51 4 104 167 9 58 2 78 125 32 18 SYNC 0 BRGH 0 BRG16 0 E Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 16 207 300 0 16 103 300 0 16 51 1 2 1 202 0 16 51 1201 0 16 25 1201 0 16 12 2 4 2 404 0 16 25 2403 0 16 12 9 6 8 929 6 99 6 19 2 20 833 8 51 2 57 6 62 500 8 51 0 115 2 62 500 45 75 0 SYNC 0 BRGH 1 BRG16 0 anes Fosc 40 000 MHz Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Eitor value Rate Erot value Rate Error value K decimal K decimal K decimal K decimal 0 3 1 2 2 4 2 441 1 73 255 2403 0 16 207 9 6 9 766 1 73 255 9 615 0 16 129 9 615 0 16 64 9615 0 16 51 19 2 19 231 0 16 129 19 231 0 16 64 19 531 1 73 31 19230 0 16 25 57 6 58 140 0 94 42 56818 1 36 21 56 818 1 36 10 55555 3 55 8 115 2 113 636 1 36 21 113 636 1 36 10 125 000 8 51 4 SYNC 0 BRGH 1 BRG16 0 RIE Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Rate Errot value Rate Error value Rate Error value K decimal K decimal K decimal 0 3 300 0 16 207 1 2 1 202 0 16 207 1201 0 16 103 1201 0 16 51 2 4 2 404 0 16 103 2403 0 16 51 2403 0 16 25 9 6 9 615 0 16 25 9615 0 16 12 1
237. 86 MHz 11 43 MHz 40 0 MHz 22 86 MHz 40 0 MHz 22 86 MHz 1 00 MHz 1 00 MHz 2 2004 Microchip Technology Inc Preliminary DS39632B page 259 PIC18F2455 2550 4455 4550 21 4 Operation in Power Managed Modes The selection of the automatic acguisition time and A D conversion clock is determined in part by the clock source and freguency while in a power managed mode If the A D is expected to operate while the device is in a power managed mode the ACQT2 ACQTO and ADC S2 ADCSO bits in ADCON2 should be updated in accordance with the clock source to be used in that mode After entering the mode an A D acquisition or conversion may be started Once started the device should continue to be clocked by the same clock source until the conversion has been completed If desired the device may be placed into the corresponding Idle mode during the conversion If the device clock freguency is less than 1 MHz the A D RC clock source should be selected Operation in the Sleep mode requires the A D FRC clock to be selected If bits ACOT2 A CGTO are set to 00 and a conversion is started the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode The IDLEN bit OSCCON lt 7 gt must have already been cleared prior to starting the conversion 21 5 Configuring Analog Port Pins The ADCON1 TRISA TRISB and TRISE registers all configure the A D port pins The port
238. 8F2455 2550 4455 4550 devices Note These values for DEV10 DEV3 may be shared with other devices The specific device is always identified by using the entire DEV10 DEVO bit sequence Legend R Read only bit P Programmable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state DS39632B page 290 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 25 2 Watchdog Timer WDT For PIC18F2455 2550 4455 4550 devices the WDT is driven by the INTRC source When the WDT is enabled the clock source is also enabled The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator The 4 ms period of the WDT is multiplied by a 16 bit postscaler Any output of the WDT postscaler is selected by a multiplexer controlled by bits in Configu ration Register 2H Available periods range from 4 ms to 131 072 seconds 2 18 minutes The WDT and postscaler are cleared when any of the following events occur a SLEEP Or CLRWDT instruction is executed the IRCF bits OSCCON lt 6 4 gt are changed or a clock failure has occurred FIGURE 25 1 WDT BLOCK DIAGRAM Note 1 The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed 2 Changing the setting of the IRCF bits OSCCON lt 6 4 gt clears the WDT and postscaler counts 3 When a CLRWDT instruction is executed the postscaler count will be
239. 9 2 19 231 0 16 12 57 6 62 500 8 51 3 115 2 125 000 8 51 1 DS39632B page 238 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 20 3 BAUD RATES FOR ASYNCHRONOUS MODES CONTINUED SYNC 0 BRGH 0 BRG16 1 RTE Fosc 40 000 MHz Fosc 20 000 MHz Fosc 10 000 MHz Fosc 8 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal K decimal 0 3 0 300 0 00 8332 0 300 0 02 4165 0 300 0 02 2082 300 0 04 1665 1 2 1 200 0 02 2082 1 200 0 03 1041 1 200 0 03 520 1201 0 16 415 2 4 2 402 0 06 1040 2 399 0 03 520 2 404 0 16 259 2403 0 16 207 9 6 9 615 0 16 259 9 615 0 16 129 9 615 0 16 64 9615 0 16 51 19 2 19 231 0 16 129 19 231 0 16 64 19 531 1 73 31 19230 0 16 25 57 6 58 140 0 94 42 56818 1 36 21 56 818 1 36 10 55555 3 55 8 115 2 113 636 1 36 21 113 636 1 36 10 125 000 8 51 4 SYNC 0 BRGH 0 BRG16 1 AE Fosc 4 000 MHz Fosc 2 000 MHz Fosc 1 000 MHz K Actual SPBRG Actual SPBRG Actual SPBRG Rate Error value Rate Error value Rate Error value K decimal K decimal K decimal 0 3 0 300 0 04 832 300 0 16 415 300 0 16 207 1 2 1 202 0 16 207 1201 0 16 103 1201 0 16 51 2 4 2 404 0 16 103 2403 0 16 51 2403
240. A 25 C VDD 3 0V PRI_RUN 460 650 uA 485 C EC oscillator All devices 1 2 1 6 mA 40 C 1 1 1 5 mA 25 C VDD 5 0V 1 0 1 4 mA 85 C PIC18LFX455 X550 0 74 2 0 mA 40 C 0 74 2 0 mA 25 C VDD 2 0V 0 74 2 0 mA 85 C PIC18LFX455 X550 1 3 3 0 mA 40 C Fosc 4 MHz 1 3 3 0 mA 25 C VDD 3 0V PRI RUN 13 30 mA 85 C EC oscillator All devices 2 7 6 0 mA 40 C 2 6 6 0 mA 25 C VDD 5 0V 2 5 6 0 mA 85 C All devices 15 35 mA 40 C 16 35 mA 25 C VDD 4 2V 16 35 A 85 C Fosc 40 MHz a a PRI_RUN All devices 21 40 mA 40 C EC oscillator 21 40 mA 25 C VDD 5 0V 21 40 mA 85 C All devices 20 40 mA 40 C 20 40 mA 25 C VDD 4 2V 20 40 A 85 C Fosc 48 MHz PRI_RUN All devices 25 50 mA 40 C EC oscillator 25 50 mA 25 C VDD 5 0V 25 50 mA 85 C Legend Shading of rows is to assist in readability of the table Note 1 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for
241. A and C Shutdown State Control bits 1x Pins A and C tri state 40 44 pin devices 01 Drive Pins A and C to 1 00 Drive Pins A and C to o bit 1 0 PSSBD1 PSSBDO Pins B and D Shutdown State Control bits 1x Pins B and D tri state 01 Drive Pins B and D to 1 00 Drive Pins B and D to o Note 1 Reserved on 28 pin devices maintain these bits clear Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR V Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 159 PIC18F2455 2550 4455 4550 16 4 7 1 Auto Shutdown and Auto Restart The auto shutdown feature can be configured to allow automatic restarts of the module following a shutdown event This is enabled by setting the PRSEN bit of the ECCP1DEL register ECCP1DEL lt 7 gt In Shutdown mode with PRSEN 1 Figure 16 10 the ECCPASE bit will remain set for as long as the cause of the shutdown continues When the shutdown condi tion clears the ECCP1ASE bit is cleared If PRSEN 0 Figure 16 11 once a shutdown condition occurs the ECCPASE bit will remain set until it is cleared by firmware Once ECCPASE is cleared the Enhanced PWM will resume at the beginning of the next PWM period Note Writing to the ECCPASE bit is disabled while a shutdown condition is active Independent of the PRSEN bit setting if the auto shutdown
242. A1 AN1 3 RA O TTL Digital I O AN1 Analog Analog input 1 RA2 AN2 VREF CVREF 4 RA2 0 TTL Digital I O AN2 Analog Analog input 2 VREF Analog A D reference voltage low input CVREF O Analog Analog comparator reference output RA3 AN3 VREF 5 RA3 O TTL Digital I O AN3 Analog Analog input 3 VREF Analog A D reference voltage high input RA4 TOCKI C1OUT RCV 6 RA4 O ST Digital O TOCKI ST TimerO external clock input C1OUT O Comparator 1 output RCV TTL External USB transceiver RCV input RAS5 AN4 SS 7 HLVDIN C2OUT RA5 O TTL Digital I O AN4 Analog Analog input 4 ss TTL SPITM slave select input HLVDIN Analog High Low Voltage Detect input C2OUT O Comparator 2 output RA6 See the OSC2 CLKO RA6 pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared 2 Default assignment for CCP2 when CCP2MX configuration bit is set 2004 Microchip Technology Inc Preliminary DS39632B page 13 PIC18F2455 2550 4455 4550 ST Schmitt Trigger input with CMOS levels O Output Alternate assignment for CCP2 when CCP2MX configuration bit is cleared Note 1 TABLE 1 2 PIC18F 2455 2550 PINOUT I O DESCRIPTIONS CONTINUED Pin Number Pin Buffer sin Pin Name Description PDIP
243. A3 24 21 22 as AS 21 AZ AZ 24 01 lo2 oslo4 qQi Q2 Q3 o4 Q1 o2 o3 Q4 Q1 o2 o3 Q4 a1 a2 a3 G4 qi o2 o3 o4 Q1 o2 o3 o4 OSC1 TUUUVU VU VY VU VV VV VV VU VV VV VV UV VU AT UTA Bit set by user i I ME ot Auto Cleared WUE bit lt 1a T T T Er nn ad RX DT Line l ez NS 7 A i RCIF Note 1 The EUSART remains in Idle while the WUE bit is set Cleared due to user read of RCREG FIGURE 20 9 AUTO WAKE UP BIT WUE TIMINGS DURING SLEEP G1 92 A3 24 91 A2 A3 A4 01 Q2 a3 a4 Q1 o2 o3 Q4 Q1 o2 o3 o4 Q1 o2 Q3 o4 a1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 osci MU UUV UVVU UV UVUVI UUUU VU VV RAA EU UT v ba Bit set by N an ene x RX DT Line i i i z oa i Cleared due to user read of RCREG RCIF Sleep Command Executed 1 2 The EUSART remains in Idle while the WUE bit is set Sleep Ends Note 1 If the wake up event requires long oscillator warm up time the auto clear of the WUE bit can occur while the stposc signal is still active This sequence should not depend on the presence of Q clocks DS39632B page 246 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 20 2 5 BREAK CHARACTER SEGUENCE The Enhanced EUSART module has the capability of sending the special Break character seguences that are reguired by the LIN bus standard The Break char acter transmit consists of a Start bit followed by twelve
244. ABLE 20 9 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 TXREG EUSART Transmit Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH JEUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented read as 0 Shaded cells are not used for synchronous slave transmission Note 1 Reserved in 28 pin devices always maintain these bits clear 2004 Microchip Technology Inc Preliminary DS39632B page 251 PIC18F2455 2550 4455 4550 20 4 2 EUSART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode and bit SREN which is a don t care in Slave mode If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode then a word may be received while in this low power mode Once the word is received the RSR register will transfer the data to the RCREG register if the RCIE enable bit is set
245. AD lt VDD Pin at high impedance D315 VILUSB Input Low Voltage for USB 0 8 V For VUSB range Buffer D316 VIHUSB Input High Voltage for USB 2 0 V For VUSB range Buffer D317 VcRS Crossover Voltage 1 3 2 0 V Voltage range for pad dp and pad dm crossover to occur D318 VpiFs Differential Input Sensitivity 0 2 V The difference between D and D must exceed this value while VCM is met D319 VCM Differential Common Mode 0 8 2 5 V Range D320 ZouT Driver Output Impedance 28 44 Q D321 VOL Voltage Output Low 0 0 0 3 V 1 5 KQ load connected to 3 6V D322 VOH Voltage Output High 2 8 3 6 V 15 KQ load connected to ground TABLE 28 5 USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions 40 C lt TA lt 85 C unless otherwise stated Param No Sym Characteristics Min Typ Max Units Comments D323 VUSBANA Regulator Output Voltage 3 0 3 6 D324 CUSB External Filter Capacitor 220 nF Must hold sufficient charge Value for peak load with minimal voltage drop These parameters are characterized but not tested Parameter numbers not yet assigned for these specifications DS39632B page 372 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 28 3 HIGH LOW VOLTAGE DETECT CHARACTERISTICS For VDIRMAG 1 VDD HLVDIF set by hardware HLVDIF can be i cleared in software For VDIR
246. AMP TC TCOFF TAMP 0 21s TCOFF Temp 25 C 0 02 us C 50 C 25 C 0 02 us C 1 2 us Temperature coefficient is only required for temperatures gt 25 C Below 25 C TCOFF 0 ms Tc CHOLD RIC RSS RS In 1 2047 us 25 pF 1 KQ 2 KQ 2 5 KQ In 0 0004883 us 5 03 us TACO 0 2 us 5 us 1 2 us 6 4 us DS39632B page 258 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 21 2 Selecting and Configuring Acguisition Time The ADCONZ2 register allows the user to select an acguisition time that occurs each time the GO DONE bit is set It also gives users the option to use an automatically determined acguisition time Acquisition time may be set with the ACQT2 ACQTO bits ADCON2 lt 5 3 gt which provide a range of 2 to 20 TAD When the GO DONE bit is set the A D module continues to sample the input for the selected acquisi tion time then automatically begins a conversion Since the acquisition time is programmed there may be no need to wait for an acquisition time between selecting a channel and setting the GO DONE bit Manual acguisition is selected when ACGT2 ACOTO 000 When the GO DONE bit is set sampling is stopped and a conversion begins The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO DONE bit This option is also the default Reset state of the ACQT2 ACQTO b
247. ATB F6Ah UEIR EEADR F89h LATA F69h UIE EEDATA F88h 2 F68h UIR EECONZ2 1 F87h F67h UFRMH EECON1 F86h V F66h UFRML 2 F85h F65h SPPCON 2 F84h PORTE F64h SPPEPS 2 F83h PORTD F63h SPPCFG IPR2 F82h PORTC F62h SPPDATA PIR2 F81h PORTB F61h PIE2 F80h PORTA F60h 2 2 Unimplemented registers are read as 0 3 These registers are implemented only on 40 44 pin devices DS39632B page 66 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 5 2 REGISTER FILE SUMMARY PIC18F2455 2550 4455 4550 File Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ORECH p lia TOSU Top of Stack Upper Byte TOS lt 20 16 gt 0 0000 51 58 TOSH Top of Stack High Byte TOS lt 15 8 gt 0000 0000 51 58 TOSL Top of Stack Low Byte TOS lt 7 0 gt 0000 0000 51 58 STKPTR STKFUL STKUNF Return Stack Pointer 00 0 0000 51 59 PCLATU Holding Register for PC lt 20 16 gt 0 0000 51 58 PCLATH Holding Register for PC lt 15 8 gt 0000 0000 51 58 PCL PC Low Byte PC lt 7 0 gt 0000 0000 51 58 TBLPTRU bit 21 1 Program Memory Table Pointer Upper Byte TBLPTR lt 20 16 gt 00 0000 51 82 TBLPTRH Progra
248. BLAT IR 9 SEICE el Read Register EXAMPLE 6 1 READING A FLASH PROGRAM MEMORY WORD MOVLW CODE ADDR UPPER Load TBLPTR with the base MOVWF BLPTRU address of the word MOVLW CODE ADDR HIGH MOVWF BLPTRH MOVLW CODE ADDR LOW MOVWF BLPTRL READ WORD TBLRD read into TABLAT and increment MOVF ABLAT W get data MOVWF WORD EVEN TBLRD read into TABLAT and increment MOVF ABLAT W get data MOVF WORD ODD 2004 Microchip Technology Inc Preliminary DS39632B page 83 PIC18F2455 2550 4455 4550 6 4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes Only through the use of an external programmer or through ICSP control can larger blocks of program memory be Bulk Erased Word Erase in the Flash array is not supported When initiating an erase sequence from the micro controller itself a block of 64 bytes of program memory is erased The Most Significant 16 bits of the TBLPTR lt 21 6 gt point to the block being erased TBLPTR lt 5 0 gt are ignored The EECONI register commands the erase operation The EEPGD bit must be set to point to the Flash program memory The WREN bit must be set to enable write operations The FREE bit is set to select an erase operation For protection the write initiate sequence for EECON2 must be used A long write is necessary for erasing the internal Flash Instruction execution is halted while in a long write cycle The long write will be t
249. Baud Rate CLK a TT P CSS a TRMT SPEN BRG1 G16 SPBRGH SPBRG 7X9 Baud Rate Generator TX9D DS39632B page 242 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 20 4 ASYNCHRONOUS TRANSMISSION i CC A 2 Shift Clock TC TX i 1 1 1 pin TAN Startbit K H0 gt biti gt SE lt bt78_ Z Stop bit Word 1 m TXIF bit Transmit Buffer 1 TCY Reg Empty Flag 45 Word 1 TRMT bit it Shi Transmit Shift Transmit Shift Reg Reg Empty Flag c 51 FIGURE 20 5 ASYNCHRONOUS TRANSMISSION BACK TO BACK Write to TXREG cc Word 1 Word 2 JJ BRG Output C Shift Clock 5 TX d pin N Start bit LO biti XT bi78 J Stop bit N Start bit X bto TXIF bit To e Word 1 gt lt Word 2 Interrupt Reg Flag h 1 gt 1 TOY S Word 1 Mr Word2 TRMT bit Transmit Shift Reg Transmit Shift Reg Transmit Shift Reg Empty Flag SS Note This timing diagram shows two consecutive transmissions TABLE 20 5 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Reset Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va
250. C 22 60 uA 40 C 26 60 uA 25 C VDD 3 0V 32 kHz on Timer1 2 9 6 0 uA 85 C 3 0 8 0 uA 40 C 3 2 80 uA 25 C VDD 5 0V 32 kHz on Timer1 3 4 8 0 uA 85 C D026 A D Converter 1 0 2 0 uA 40 C to 85 C VpD 2 0V AlAD 10 20 pA 40 Cto 85 C Vpp 3 0V A D on not converting 1 0 2 0 uA 40 C to 85 C VDD 5 0V Legend Shading of rows is to assist in readability of the table Note 1 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or Vss MCLR VDD WDT enabled disabled as specified 3 Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption wil
251. C Slave mode 7 bit address Note Bit combinations not specifically listed here are either reserved or implemented in SPI mode only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 204 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 19 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPCON2 MSSP CONTROL REGISTER 2 PC MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEND bit 7 bit 0 GCEN General Call Enable bit Slave mode only 1 Enable interrupt when a general call address 0000h is received in the SSPSR 0 General call address disabled ACKSTAT Acknowledge Status bit Master Transmit mode only 1 Acknowledge was not received from slave 0 Acknowledge was received from slave ACKDT Acknowledge Data bit Master Receive mode only 1 Not Acknowledge 0 Acknowledge Note Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive ACKEN Acknowledge Sequence Enable bit Master Receive mode only 1 Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit Automatically cleared by hardware 0 Acknowledge sequence Idle RCEN Receive Enable bit Master mode only 1 Enables
252. C nn nine SI v 311 BNN 311 BNOV Sun i AA NA aa 312 BNZ a kata amaka s L Pisu ha umasha 312 BOR See Brown out Reset BOV nitrates ai Da iu Sau sau mkuu a ss 315 BRA ski snanta aasan Rte Lane Ress 313 BRG See Baud Rate Generator Brown out Reset BOR 1 Detecting aa oil Disabling in Sleep Mode x Software Enabled DS39632B page 409 PIC18F2455 2550 4455 4550 C C Compilers MPLAB C17 ooo uqu asa anu au hatu 352 Capture CCP Module 143 Associated Registers a 145 CCP Pin Configuration CCPRxH CCPRXxL Registers 143 Pr scaler its kt hk at sh ok kky Atuk h AST Software Interrupt Timer1 Timer3 Mode Selection 143 Capture ECCP Module 150 Capture Compare PWM CCP 141 Capture Mode See Capture CCP Mode and Timer Resources 142 CCPRxH Register CCPRxL Register Compare Mode See Compare Interaction of Two CCP Modules for Timer Resources ssessesssseneeeseinrresserrrrresererene 142 Module Configuration 142 Clock Sources wi ol Selecting the 31 kHz Source
253. CCP MODULES AND TIMER RESOURCES Like the standard CCP modules the ECCP module can utilize Timers 1 2 or 3 depending on the mode selected Timer1 and Timers are available for modules in Capture or Compare modes while Timer2 is available for modules in PWM mode Interactions between the standard and Enhanced CCP modules are identical to those described for standard CCP modules Additional details on timer resources are provided in Section 15 1 1 CCP Modules and Timer Resources 16 2 Capture and Compare Modes Except for the operation of the special event trigger discussed below the Capture and Compare modes of the ECCP module are identical in operation to that of CCP These are discussed in detail in Section 15 2 Capture Mode and Section 15 3 Compare Mode 16 2 1 SPECIAL EVENT TRIGGER The special event trigger output of ECCP resets the TMR1 or TMR3 register pair depending on which timer resource is currently selected This allows the CCPRIH CCPRIL registers to effectively be a 16 bit programmable period register for Timer1 or Timer3 16 3 Standard PWM Mode When configured in Single Output mode the ECCP module functions identically to the standard CCP module in PWM mode as described in Section 15 4 PWM Mode This is also sometimes referred to as Compatible CCP mode as in Table 16 1 Note When setting up single output PWM Operations users are free to use either of the processes described in Sec
254. CK Master mode must have TRISB lt 1 gt bit cleared SCK Slave mode must have TRISB lt 1 gt bit set SS must have TRISA lt 5 gt bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction TRIS register to the opposite value 19 3 4 TYPICAL CONNECTION Figure 19 2 shows a typical connection between two microcontrollers The master controller Processor 1 initiates the data transfer by sending the SCK signal Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock Both processors should be pro grammed to the same Clock Polarity CKP then both controllers would send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software This leads to three scenarios for data transmission e Master sends data Slave sends dummy data e Master sends data Slave sends data e Master sends dummy data Slave sends data FIGURE 19 2 SPI MASTER SLAVE CONNECTION SPI Master SSPM3 SSPMO 00xxb SPI Slave SSPM3 SSPMO 010xb i SDO SDI I I I I I I I I Serial Input Buffer Serial Input Buffer I SSPBUF SSPBUF I I I I I I I I I I I I I I Shift Register SDI ee SED Shift Register SSPSR SSPSR I I I I MSb LSb i MSb LSb Serial Clock SCK SCK
255. CKI 1 IN ST PORTC lt 0 gt data input T10SO x OUT ANA Timer1 oscillator output enabled when Timer1 oscillator enabled Disables digital I O T13CKI 1 IN ST Timer1 Timer3 counter input RC1 T1OSI RC1 0 OUT DIG LATC lt 1 gt data output CCP2 UOE 1 IN ST PORTC lt 1 gt data input T10SI x IN ANA Timer1 oscillator input enabled when Timer1 oscillator enabled Disables digital I O ccp2 1 0 OUT DIG CCP2 Compare and PWM output takes priority over port data 1 IN ST CCP2 Capture input UOE 0 OUT DIG External USB transceiver OE output RC2 CCP1 RC2 0 OUT DIG LATC lt 2 gt data output PIA 1 IN ST PORTC lt 2 gt data input CCP1 0 OUT DIG ECCP1 Compare and PWM output takes priority over port data 1 IN ST ECCP1 Capture input P1A 0 OUT DIG ECCP1 Enhanced PWM output channel A takes priority over port data May be configured for tri state during Enhanced PWM shutdown events RC4 D VM RC4 2 IN TTL PORTC lt 4 gt data input disabled when USB enabled D OUT XCVR USB bus differential minus line output internal transceiver 2 IN XCVR USB bus differential minus line input internal transceiver VM 2 IN TTL External USB transceiver VM input RC5 D VP RC5 2 IN TTL PORTC lt 5 gt data input disabled when USB enabled D OUT XCVR USB bus differential plus line output internal transceiver IN XCVR_ USB bus differential plus line input internal transceiver VP 2 IN TTL Ex
256. CL no change and sets SSPIF TBRG gt K TBRG TBRG gt Set S SSPSTAT lt 3 gt 1st bit X Write to SSPBUF occurs here lt TBRG scl ITBRG gt Sr Repeated Start DS39632B page 222 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 10 C MASTER MODE TRANSMISSION Transmission of a data byte a 7 bit address or the other half of a 10 bit address is accomplished by simply writing a value to the SSPBUF register This action will set the Buffer Full flag bit BF and allow the Baud Rate Generator to begin counting and start the next trans mission Each bit of address data will be shifted out onto the SDA pin after the falling edge of SCL is asserted see data hold time specification parameter 106 Table 28 20 SCL is held low for one Baud Rate Generator rollover count TBRG Data should be valid before SCL is released high see data setup time specification parameter 107 Table 28 20 When the SCL pin is released high it is held that way for TBRG The data on the SDA pin must remain stable for that duration and some hold time after the next fall ing edge of SCL After the eighth bit is shifted out the falling edge of the eighth clock the BF flag is cleared and the master releases SDA This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred or if data was received pro
257. CP1MO 53 SPPCON SPPOWN SPPEN 55 Legend unimplemented read as 0 Shaded cells are not used by PORTD Note 1 Implemented only when Master Clear functionality is disabled MCLRE configuration bit o 2 RE is the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 3 These registers and or bits are unimplemented on 28 pin devices DS39632B page 122 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 10 5 PORTE TRISE and LATE Registers Depending on the particular PIC18F2455 2550 4455 4550 device selected PORTE is implemented in two different ways For 40 44 pin devices PORTE is a 4 bit wide port Three pins REO AN5 CK1SPP RE1 AN6 CK2SPP and RE2 AN7 OESPP are individually configurable as inputs or outputs These pins have Schmitt Trigger input buffers When selected as an analog input these pins will read as 0s The corresponding data direction register is TRISE Setting a TRISE bit 1 will make the corresponding PORTE pin an input i e put the corresponding output driver in a high impedance mode Clearing a TRISE bit 0 will make the corresponding PORTE pin an output i e put the contents of the output latch on the selected pin In addition to port data the PORTE register Register 10 1 also contains the RDPU control bit PORTE lt 7 gt
258. CV TTL External USB transceiver RCV input RA5 AN4 SS 7 24 24 HLVDIN C20UT RA5 O TTL Digital I O AN4 I Analog Analog input 4 ss TTL SPI slave select input HLVDIN Analog High Low Voltage Detect input C2OUT O Comparator 2 output RA6 See the OSC2 CLKO RA6 pin Legend TTL TTL compatible input CMOS CMOS compatible input or output U 4 I Schmitt Trigger input with CMOS levels O Output Alternate assignment for CCP2 when CCP2MX configuration bit is cleared P Input Power 2 Default assignment for CCP2 when CCP2MxX configuration bit is set 3 These pins are No Connect unless the ICPRT configuration bit is set For NC ICPORTS the pin is No Connect unless ICPRT is set and the DEBUG configuration bit is cleared 2004 Microchip Technology Inc Preliminary DS39632B page 17 PIC18F2455 2550 4455 4550 TABLE 1 3 PIC18F4455 4550 PINOUT I O DESCRIPTIONS CONTINUED Pin Number Pin Buffer Pin Name Description PDIP QFN TQFP Type Type RB3 AN9 CCP2 VPO 36 12 11 RB4 AN11 KBIO CSSPP 37 14 14 PORTB is a bidirectional I O port PORTB can be software programmed for internal weak pull ups on all inputs RBO AN12 INTO 33 9 8 FLTO SDI SDA RBO VO TTL Digital I O AN12 I Analog Analog input 12 INTO ST External interrupt 0 FLTO ST Enhanced PWM Fault input ECCP1 module SDI l ST SPI data in SDA VO ST IC data
259. Call Address RW o Receiving Data ACK Address is compared to General Call Address after ACK set interrupt SDA pa i LACK D7 X D6 X D5 X D4 X D3 X D2 X D1 X DO SSPIF s TA A A AA AAA n a PX AAA AR AUS BF SSPSTAT lt 0 gt SSPOV SSPCON1 lt 6 gt 4 __ Cleared in software ___SSPBUF is read GCEN SSPCON2 lt 7 gt DS39632B page 216 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 6 MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit In Master mode the SCL and SDA lines are manipulated by the MSSP hardware Master mode operation is supported by interrupt generation on the detection of the Start and Stop conditions The Stop P and Start S bits are cleared from a Reset or when the MSSP module is disabled Control of the 12C bus may be taken when the P bit is set or the bus is Idle with both the S and P bits clear In Firmware Controlled Master mode user code conducts all 12C bus operations based on Start and Stop bit conditions Once Master mode is enabled the user has six options 1 Assert a Start condition on SDA and SCL 2 Assert a Repeated Start condition on SDA and SCL 3 Write to the SSPBUF register initiating transmission of data address 170 0392 Tn0 0084 T 001 n 12 ionoSSEe03 Tma 2004 Microchip Techno
260. Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example CLRF FLAG_REG 1 Before Instruction FLAG REG 5Ah After Instruction FLAG_REG 00h CLRWDT Clear Watchdog Timer Syntax CLRWDT Operands None Operation 000h WDT 000h gt WDT postscaler 1 TO 1 PD Status Affected TO PD Encoding 0000 0000 0000 0100 Description CLRWDT instruction resets the Watchdog Timer It also resets the gt postscaler of the WDT Status bits TO and PD are set Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No Process No operation Data operation Example CLRWDT Before Instruction WDT Counter After Instruction WDT Counter 0h WDT Postscaler 0 19 PD 2004 Microchip Technology Inc Preliminary DS39632B page 317 PIC18F2455 2550 4455 4550 COMF Complement f CPFSEQ Compare f with W Skip if f W Syntax COMF f d a Syntax CPFSEQ ftaj Operands 0 lt f lt 255 Operands 0 lt f lt 255 de 0 1 ae 0 1 ae 0 1 Operation f W Operation f gt dest skip if 9 W 5 AR g Nee unsigned comparison tatus Affected sia Status Affected None encoding a za eee Grae Encoding 0110 001a feet Description The contents of register are Description Compares the contents of data memory complemented If d is o the result is location
261. DD WDT enabled disabled as specified 3 Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications DS39632B page 360 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 Supply Current Ipp 2 PIC18LFX455 X550 15 32 uA 40 C 15 30 uA 25 C VDD 2 0V 15 29 pA 85 C PIC18LFX455 X550 40 63 HA 40 C Fosc 31 kHz 35 60 uA 25 C VDD 3 0V RC_RUN mode INTRC source EE aia 2004 Microchip Technology Inc Preliminary DS39632B page 361 PIC18F2455 2550 4455 4550 28 2 DC Characteristics Power Down and Supply Current PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Continued PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial Ne Device Typ Max Units Conditions Supply Current Ipp PIC18LFX455 X550 2 9 8 uA 40 C 3 1 8 uA 25 C VDD 2 0
262. DE d a f FILE ADDWF MYREG W B d 0 for result destination to be WREG register d 1 for result destination to be file register f a 0 to force Access Bank a 1 for BSR to select bank f 8 bit file register address Byte to Byte move operations 2 word 15 12 11 0 OPCODE f Source FILE MOVFF MYREG1 MYREG2 15 12 11 0 1111 f Destination FILE f 12 bit file register address Bit oriented file register operations 15 12 11 9 8 7 0 OPCODE b BIT a f FILE BSF MYREG bit B b 3 bit position of bit in file register f a o to force Access Bank a 1 for BSR to select bank f 8 bit file register address Literal operations 15 8 7 0 OPCODE k literal MOVLW 7Fh k 8 bit immediate value Control operations CALL GOTO and Branch operations 15 87 0 OPCODE n lt 7 0 gt literal GOTO Label 15 12 11 0 1111 n lt 19 8 gt literal n 20 bit immediate value 15 8 7 0 OPCODE S n lt 7 0 gt literal CALL MYFUNC 15 12 11 0 1111 n lt 19 8 gt literal S Fast bit 15 11 10 0 OPCODE n lt 10 0 gt literal BRA MYFUNC 15 87 0 OPCODE n lt 7 0 gt literal BC MYFUNC 2004 Microchip Technology Inc Preliminary DS39632B page 303 PIC18F2455 2550 4455 4550 TABLE 26 2 PIC18FXXXX INSTRUCTI
263. DUSTRIAL fray Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution 10 bit AVREF gt 3 0V A03 EIL Integral Linearity Error lt 1 LSb AVREF gt 3 0V A04 EDL Differential Linearity Error lt 1 LSb AVREF gt 3 0V A06 EoFF Offset Error lt 1 5 LSb AVREF gt 3 0V A07 EGN Gain Error lt 1 LSb AVREF gt 3 0V A10 Monotonicity Guaranteed VSS lt VAIN lt VREF A20 AVREF Reference Voltage Range 1 8 V VDD lt 3 0V VREFH VREFL 3 V VbD 3 0V A21 VREFH Reference Voltage High Vss VREFH V A22 VREFL Reference Voltage Low Vss 0 3V M VDD 3 0V V A25 VAIN Analog Input Voltage VREFL VREFH V A30 ZAIN Recommended Impedance of 2 5 ko Analog Voltage Source A50 IREF VREF Input Current 5 uA During VAIN acquisition M 150 uA During A D conversion cycle Note 1 The A D conversion result never decreases with an increase in the input voltage and has no missing codes 2 VREFH current is from RA3 AN3 VREF pin or VDD whichever is selected as the VREFH source VREFL current is from RA2 AN2 VREF CVREF pin or Vss whichever is selected as the VREFL source FIGURE 28 23 A D CONVERSION TIMING BSF ADCON0 co X Note 2 131 a Q4 i ee 130 mow FL TTL POEET EE ja A D DATA To EP CD CD ED ED EX ADRES OLD_DATA ADIF Y NEW_DATA k Ty GO SAMPLE Note 1 SAMPLING
264. Data Bus Read WT Write SSPBUF reg oe Snif Clock NZ lt 1 SSPSR reg RBO SDI SDA MSb LSb Z Match Detect gt Addr Match ZN SSPADD reg Start and Set Reset Stop bit Detect gt S P bits SSPSTAT reg Note Only those pin functions relevant to IZCTM operation are shown here 19 4 1 REGISTERS The MSSP module has six registers for I C operation These are e MSSP Control Register 1 SSPCON1 e MSSP Control Register 2 SSPCON2 e MSSP Status Register SSPSTAT Serial Receive Transmit Buffer Register SSPBUF e MSSP Shift Register SSPSR Not directly accessible e MSSP Address Register SSPADD SSPCON1 SSPCON2 and SSPSTAT are the control and status registers in IC mode operation The SSPCONI and SSPCON2 registers are readable and writable The lower six bits of the SSPSTAT are read only The upper two bits of the SSPSTAT are read write SSPSR is the shift register used for shifting data in or out SSPBUF is the buffer register to which data bytes are written to or read from SSPADD register holds the slave device address when the SSP is configured in PC Slave mode When the SSP is configured in Master mode the lower seven bits of SSPADD act as the Baud Rate Generator reload value In receive operations SSPSR and SSPBUF together create a double buffered receiver When SSPSR r
265. Data Out SDO a 193 Serial Peripheral Interface See SPI Mode SETF hrali 335 Slave Select SS 193 SLEEP nent dentelle arsu a 336 Sleep OSC1 and OSC2 Pin States 33 Sleep Mode A Software Simulator MPLAB SIM 352 Software Simulator MPLAB SIM30 352 Special Event Trigger See Compare CCP Module Special Event Trigger See Compare ECCP Module Special Features of the CPU Special ICPORT Features SPI Mode MSSP Associated Registers Bus Mode Compatibility Effects of a Reset Enabling SPI I O Master Mode ue Master Slave Connection nr Op ratin ssssscssrsressemesrereneersrerersetsmteeiess Operation in Power Managed Modes ari Serial Clock roserne ni Serial Data IN a a Serial Data Out sue Slave MOS aa aan esters rentestrsgerdereensese Slave Select sites li Slave Select Synchronization SPICIOCK ty Z uu A u wanta Sam yta Typical Connection SPP See Streaming Parallel Port SS Meal dolna lod lana Lit rat 193 SSPOV sects NE AO HOP aus 223 SSPOV Status Flag a 223 SSPSTAT Register RAM Bit i l
266. Data Out Valid PIC18FXXXX 40 ns PIC18LFXXXX 100 ns VDD 2 0V 121 Tckrf Clock Out Rise Time and Fall Time PIC18FXXXX 20 ns Master mode PIC18LFXXXX 50 ns Vpp 2 0V 122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX 20 ns PIC18LFXXXX 50 ns VDD 2 0V FIGURE 28 20 EUSART SYNCHRONOUS RECEIVE MASTER SLAVE TIMING ROGTXCK XO pin s 1252 RC7 RX DT pin x X lt 126 gt Note Refer to Figure 28 4 for load conditions TABLE 28 24 EUSART SYNCHRONOUS RECEIVE REQUIREMENTS ae Symbol Characteristic Min Max Units Conditions 125 TDTV2CKL SYNC RCV MASTER 8 SLAVE Data Hold before CK J DT hold time 10 ns 126 TCKL2DTL Data Hold after CK J DT hold time 15 ns DS39632B page 390 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 28 21 USB SIGNAL TIMING USB Data Differential Lines TLR TFR TIF TFF TABLE 28 25 USB LOW SPEED TIMING REGUIREMENTS ne Symbol Characteristic Min Typ Max Units Conditions TLR Transition Rise Time 75 300 ns CL 200 to 600 pF TLF Transition Fall Time 75 300 ns CL 200 to 600 pF TLRFM Rise Fall Time Matching 80 125 TABLE 28 26 USB FULL SPEED REGUIREMENTS r Symbol Characteristic Min Typ Max Units Conditio
267. Data literal k MSB to FSRfH Decode Read literal Process Write literal k K LSB Data to FSRfL Example LFSR 2 3ABh After Instruction FSR2H 03h FSR2L ABh MOVF Move f Syntax MOVF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation f dest Status Affected N Z Encoding 0101 00da ffff ffff Description The contents of register f are moved to a destination dependent upon the status of d If is 0 the result is placed in W If d is 1 the result is placed back in register f default Location f can be anywhere in the 256 byte bank If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity 01 Q2 03 Q4 Decode Read Process Write W register f Data Example MOVF REG 0 0 Before Instruction REG 22h W FFh After Instruction REG 22h W 22h 2004 Microchip Technology Inc Preliminary DS39632B page 325 PIC18F2455 2550 4455 4550 MOVFF Move f to f Syntax MOVFF ffq Operands 0 lt fs lt 4095 0 lt fy lt 4095 O
268. E 17 2 SINGLE ENDED INPUTS FROM TRANSCEIVER Bus State VP VM Single Ended Zero Low Speed High Speed Error 0 1 0 1 F P O j O The OE signal toggles the state of the external trans ceiver This line is pulled low by the device to enable the transmission of data from the SIE to an external device 17 2 2 3 Internal Pull up Resistors The PIC18FX455 X550 devices have built in pull up resistors designed to meet the requirements for low speed and full speed USB The UPUEN bit UCFG lt 4 gt enables the internal pull ups Figure 17 1 shows the pull ups and their control 17 2 2 4 External Pull up Resistors External pull up may also be used The VusB pin may be used to pull up D or D The pull up resistor must be 1 5 kQ 15 as required by the USB specifications Figure 17 3 shows an example FIGURE 17 3 EXTERNAL CIRCUITRY PIC Host Microcontroller Controller HUB VUSB 1 5 KQ Note The above setting shows a typical connection for a full speed configuration using an on chip regulator and an external pull up resistor 17 2 2 5 Ping Pong Buffer Configuration The usage of ping pong buffers is configured using the PPB1 PPBO bits Refer to Section 17 4 4 Ping Pong Buffering for a complete explanation of the ping pong buffers 17 2 2 6 USB Output Enable Monitor The USB OE monitor provides indication as to whether the
269. E 28 15 EXAMPLE SPITM MODE REQUIREMENTS MASTER MODE CKE 0 Param No Symbol Characteristic Min Max Units Conditions 70 TssL2scH SS J to SCK J or SCK T Input Tcy ns TssL2scL 71 TscH SCK Input High Time Continuous 1 25 Tcy 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK Input Low Time Continuous 1 25 TCY 30 ns 72A Slave mode Single Byte 40 ns Note 1 73 TdiV2scH Setup Time of SDI Data Input to SCK Edge 100 ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1 5 Toy 40 ns Note 2 of Byte 2 74 TscH2diL Hold Time of SDI Data Input to SCK Edge 100 ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX s 45 ns Vpp 2 0V 76 TdoF SDO Data Output Fall Time 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX 25 ns Master mode PIC18LFXXXX 45 ns Voo 2 0V 79 TscF SCK Output Fall Time Master mode 25 ns 80 TscH2doV SDO Data Output Valid after PIC18FXXXX 50 ns TsoL2doV SCK Edge PIC18LFXXXX 100 ns Voo 2 0V Note 1 Reguires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used DS39632B page 382 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 28 12 EXAMPLE SPITM MASTER MODE TIMING CKE 1 Note d Refer to Figure 28 4
270. EG Note Timing diagram demonstrates Sync Master mode with bit SREN 1 and bit BRGH 0 TABLE 20 8 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRI1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented read as 0 Shaded cells are not used for synchronous master reception Note 1 Reserved in 28 pin devices always maintain these bits clear DS39632B page 250 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 20 4 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit CSRC TXSTA lt 7 gt This mode differs from the To set up a Synchronous Slave Transmission 1 Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC Synchronous
271. EN Timer1 can be enabled or disabled by setting or clearing control bit TMRION TICON lt O gt REGISTER 12 1 T1CON TIMER1 CONTROL REGISTER R W 0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 RD16 TIRUN T1CKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16 16 Bit Read Write Mode Enable bit 1 Enables register read write of Tlmer1 in one 16 bit operation 0 Enables register read write of Timer1 in two 8 bit operations bit 6 T1RUN Timer1 System Clock Status bit 1 Device clock is derived from Timer1 oscillator 0 Device clock is derived from another source bit 5 4 T1CKPS1 TICKPSO Timer1 Input Clock Prescale Select bits 11 1 8 Prescale value 10 1 4 Prescale value 01 1 2 Prescale value 00 1 1 Prescale value bit 3 TIOSCEN Timer1 Oscillator Enable bit 1 Timer oscillator is enabled 0 Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2 TISYNC Timer1 External Clock Input Synchronization Select bit When TMRICS 1 1 Do not synchronize external clock input 0 Synchronize external clock input When TMRICS 0 This bit is ignored Timer1 uses the internal clock when TMR1CS o bit 1 TMR1CS Timer1 Clock Source Select bit 1 External clock from pin RCO T1OSO T13CKI on the rising edge 0 Internal clock Fosc 4 bit 0 TMRI1ON Timer1 On bit 1 Enables T
272. ETWEEN CAPTURE PRESCALERS CCP2 SHOWN CLRF CCP2CON Turn CCP module off MOVLW NEW CAPT PS Load WREG with the new prescaler mode value and CCP ON MOVWF CCP2CON Load CCP2CON with this value FIGURE 15 1 CAPTURE MODE OPERATION BLOCK DIAGRAM CCP1 pin Prescaler A and 1 x 1 4 16 Edge Detect Set CCP1IF P 4 CCP1CON lt 3 0 gt Set CCP2IF Q1 Q4 J CCP2CON lt 3 0 gt T3CCP1 3 TMR3H TMR3L T3CCP2 TMR3 I Enable CCP2 pin V TMR3H TMR3L T3CCP2 TMR3 N Enable CCPR1H CCPR1L TMR1 T3CCP2 er ZN TMR1H TMRIL 4 CCPR2H CCPR2L Prescaler F and 1 q 1 4 16 Edge Detect D TMR1 Enable T3CCP2 ceo se D TMRIH TMRIL 2004 Microchip Technology Inc Preliminary DS39632B page 143 PIC18F2455 2550 4455 4550 15 3 Compare Mode In Compare mode the 16 bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value When a match occurs the CCPx pin can be e driven high driven low toggled high to low or low to high remain unchanged that is reflects the state of the I O latch The action on the pin is based on the value of the mode select bits CCPxM3 CCPxMO At the same time the interrupt flag bit CCPXIF
273. Endpoint Output Enable bit 1 Endpoint n output enabled 0 Endpoint n output disabled bit 1 EPINEN Endpoint Input Enable bit 1 Endpoint n input enabled 0 Endpoint n input disabled bit 0 EPSTALL Endpoint Stall Enable bit 1 Endpoint n is stalled 0 Endpoint n is not stalled Note 1 Valid only if Endpoint n is enabled otherwise the bit is ignored Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 169 PIC18F2455 2550 4455 4550 17 2 5 USB ADDRESS REGISTER UADDR The USB Address register contains the unigue USB address that the peripheral will decode when active UADDR is reset to 00h when a USB Reset is received indicated by URSTIF or when a Reset is received from the microcontroller The USB address must be written by the microcontroller during the USB setup phase enumeration as part of the Microchip USB firmware support 17 2 6 USB FRAME NUMBER REGISTERS UFRMH UFRML The Frame Number registers contain the 11 bit frame number The low order byte is contained in UFRML while the three high order bits are contained in UFRMH The register pair is updated with the current frame number whenever a SOF token is received For the microcontroller these registers are read only The Frame Number register is primarily use
274. F BRIDGE MODE In the Half Bridge Output mode two pins are used as outputs to drive push pull loads The PWM output sig nal is output on the PIA pin while the complementary PWM output signal is output on the P1B pin Figure 16 4 This mode can be used for half bridge applications as shown in Figure 16 5 or for full bridge applications where four power switches are being modulated with two PWM signals In Half Bridge Output mode the programmable dead band delay can be used to prevent shoot through current in half bridge power devices The value of bits PDC6 PDCO sets the number of instruction cycles before the output is driven active If the value is greater than the duty cycle the corresponding output remains inactive during the entire cycle See Section 16 4 6 Programmable Dead Band Delay for more details of the dead band delay operations Since the PIA and P1B outputs are multiplexed with the PORTC lt 2 gt and PORTD lt 5 gt data latches the TRISC lt 2 gt and TRISD lt 5 gt bits must be cleared to configure PIA and P1B as outputs FIGURE 16 5 FIGURE 16 4 HALF BRIDGE PWM OUTPUT Period Period Duty Cycle 1 td Dead Band Delay PR2 register 2 Output signals are shown as active high 1 Note 1 At this time the TMR2 register is equal to the EXAMPLES OF HALF BRIDGE OUTPUT MODE APPLICATIONS
275. F2 IRCFO immediately after Reset For wake ups from Sleep the INTOSC or postscaler clock sources can be selected by setting IRCF2 IRCFO prior to entering Sleep mode The FSCM will detect failures of the primary or second ary clock sources only If the internal oscillator block fails no failure would be detected nor would any action be possible 25 4 1 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator Since the WDT operates with a separate divider and counter disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled As already noted the clock source is switched to the INTOSC clock when a clock failure is detected Depending on the frequency selected by the IRCF2 IRCFO bits this may mean a substantial change in the speed of code execution If the WDT is enabled with a small prescale value a decrease in clock speed allows a WDT time out to occur and a subsequent device Reset For this reason Fail Safe Clock Monitor events also reset the WDT and postscaler allowing it to start timing from when execution speed was changed and decreasing the likelinood of an erroneous time out 25 4 2 EXITING FAIL SAFE OPERATION The fail safe condition is terminated by either a device Reset or by entering a power managed mode On Reset the controller starts the primary clock source specified in Configuration Register 1H with any start up delays that are required fo
276. FCFh TMR1H FAFh FEEh POSTINCOU FCEh TMRIL FAEh FEDh POSTDECO FCDh TICON FADh FECh PREINCO FCCh TMR2 FACh FEBh PLUSW0 1 FCBh PR2 FABh FEAh FSROH FCAh T2CON FAAh FE9h FSROL FC9h SSPBUF FA9h FE8h WREG FC8h SSPADD FA8h FE7h INDF1 FC7h SSPSTAT FA7h FE6h POSTINC1 FC6h SSPCON1 FA6h FE5h POSTDEC1 1 FC5h SSPCON2 FA5h FE4h PREINC1 FC4h ADRESH FA4h FE3h PLUSW1 FC3h ADRESL FA3h FE2h FSR1H FC2h ADCONO FA2h FE h FSRIL FCih ADCON1 FAth FEOh BSR FCOh ADCON2 FAOh Note 1 Nota physical register Name Address Name Address Name CCPR1H F9Fh IPR1 F7Fh UEP15 CCPRIL F9Eh PIR1 FTEh UEP14 CCP1CON F9Dh PIE1 F7Dh UEP13 CCPR2H F9Ch F7Ch UEP12 CCPR2L F9Bh OSCTUNE F7Bh UEP11 CCP2CON F9Ah 2 FZAh UEP10 2 F99h 2 F79h UEP9 BAUDCON F98h F78h UEP8 ECCP1DEL F97h F77h UEP7 ECCP1AS F96h TRISE F76h UEP6 CVRCON F95h TRISD F75h UEP5 CMCON F94h TRISC F74h UEP4 TMR3H F93h TRISB F73h UEP3 TMR3L F92h TRISA F72h UEP2 T3CON F91h F71h UEP1 SPBRGH F90h F70h UEPO SPBRG F8Fh 8 F6Fh UCFG RCREG F8Eh 2 F6Eh UADDR TXREG F8Dh LATE F6Dh UCON TXSTA F8Ch LATD F6Ch USTAT RCSTA F8Bh LATC F6Bh UEIE i F8Ah L
277. FIGURE 19 9 AEMYOS U 19S SI MO JEMYOS u 18S SI dHO USI 4IdSS Wol4 eleMJOS u pereSjJ AJEMYOS U UBTM SI INGdSS Y dO AJEMYOS U SWUM SI INGdSS_ YSI dIdSS W014 9JEMIJOS u paea Y lt 0 gt 1yLSgSS 4d lt e gt LHId 4I4SS i I aes 0 spuodsej Ado elm p ldues NO Id 1999 ul ejeg fes ra za Xea a Ysa Yoa Yza MOV eyeq Bunwsuesy wwe iid Vee bi AUR x E Kea fsa X MODE NI C2 0 C2 C ET V A EJEG BuiusueJ T WH ssoppy BUIAIS98H hs DS39632B page 209 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 IC SLAVE MODE TIMING WITH SEN 0 RECEPTION 10 BIT ADDRESS FIGURE 19 10 0 NAS USUM 0 0 S 1 JOU s op 4M dy porepdn eq 0 speeu qavdss yeu Buneoipui jes s YN ssaippe Jo 914g ssaippe Jo 9149 MOJ UJIM pojepdn uBiu ym porepdn SI qqvdSS u ym eiempieu Aq paire Was JOU SI MOV INF INS s INAdSS osnessg 105 sI AOdSS 7 payepdn s qavdss ueym 9JEMPiL Aq peiee 9 eq 0 sposu qqdvdSS eur yeu Buyeoipul 49S S VN lt L gt LWLSdSs vn Bey 4g 18919 0 ANadSs jo pees Auuung lt 9 gt LNOOdSS AOdSS HSdSS Jo slu luoo T M vonum SI 4NAdSS 9 JEMYJOS ul pesesjJ Y 81EMYOS u paea 7 1
278. FO to advance valid only for IN OUT and SETUP tokens 3 This bit is typically unmasked only following the detection of a UIDLE interrupt event 4 Only error conditions enabled through the UEIE register will set this bit This bit is a status bit only and cannot be set or cleared by the user Legend R Readable bit W Writable bit U Unimplemented bit read as 0 DS39632B page 178 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 5 2 USB INTERRUPT ENABLE REGISTER UIE The USB Interrupt Enable register Register 17 8 contains the enable bits for the USB status interrupt sources Setting any of these bits will enable the respective interrupt source in the UIR register REGISTER 17 8 U 0 R W 0 R W 0 The values in this register only affect the propagation of an interrupt condition to the microcontroller s inter rupt logic The flag bits are still set by their interrupt conditions allowing them to be polled and serviced without actually generating an interrupt UIE USB INTERRUPT ENABLE REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE bit 7 bit 7 bit 6 Unimplemented Read as bit 0 SOFIE START OF FRAME Token Interrupt Enable bit 1 START OF FRAME token interrupt enabled 0 START OF FRAME token interrupt disabled bit 5 1 STALL interrupt enabled 0 STALL interrupt
279. Failure 294 Fast Register Stack 1 uuu Firmware Instructions es Flash Program Memory a 79 Associated Registers 87 Control Registers 80 EECONI and EECON2 80 TABLAT Table Latch Register 82 TBLPTR Table Pointer Register 82 Erase Seguence i Y 84 Erasing 84 Operation During Code Protect 87 Protection Against Spurious Writes 87 Reading asan a aa tnt A pasan 83 Table Pointer Boundaries Based on Operation 82 2004 Microchip Technology Inc Preliminary DS39632B page 411 PIC18F2455 2550 4455 4550 Table Pointer Boundaries 82 Table Reads and Table Writes 79 Unexpected Termination of Write k Write Sequence u u 85 Write Verify u aaa i 87 Writing TO iiss ana rv 85 FSCM See Fail Safe Clock Monitor G GOTO AST ein Ge ee 322 H Hardware Multiplier a 95 INtFOGUGTION suu u ei de AE 95 Operation i Performance Comparison a 95 High Low Voltage Detect 273 Applications Associated Registers a 277
280. For 8 bit addresses of 60h and above this means that users can evaluate and operate on SFRs more efficiently The Access RAM below 60h is a good place for data values that the user might need to access rapidly such as immediate computational results or common program variables Access RAM also allows for faster and more code efficient context saving and switching of variables The mapping of the Access Bank is slightly different when the extended instruction set is enabled XINST configuration bit 1 This is discussed in more detail in Section 5 6 3 Mapping the Access Bank in Indexed Literal Offset Mode 5 3 4 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area This is data RAM which is available for use by all instructions GPRs start at the bottom of Bank 0 address 000h and grow upwards towards the bottom of the SFR area GPRs are not initialized by a Power on Reset and are unchanged on all other Resets 2004 Microchip Technology Inc Preliminary DS39632B page 65 PIC18F2455 2550 4455 4550 5 3 5 SPECIAL FUNCTION REGISTERS The Special Function Registers SFRs are registers used by the CPU and peripheral modules for controlling the desired operation of the device These registers are implemented as static RAM in the data memory space SFRs start at the top of data memory and extend down ward to occupy the top segment of Bank 15 from F60h to FFFh A list of these register
281. GISTER 24 1 The High Low Voltage Detect Control register Register 24 1 completely controls the operation of the HLVD module This allows the circuitry to be turned off by the user under software control which minimizes the current consumption for the device The block diagram for the HLVD module is shown in Figure 24 1 HLVDCON HIGH LOW VOLTAGE DETECT CONTROL REGISTER R W 0 U 0 R 0 R W 0 R W 0 R W 1 R W 0 R W 1 VDIRMAG IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDLO bit 7 bit 0 bit 7 VDIRMAG Voltage Direction Magnitude Select bit 1 Event occurs when voltage equals or exceeds trip point HLVDL3 HLDVLO 0 Event occurs when voltage equals or falls below trip point HLVDL3 HLVDLO bit 6 Unimplemented Read as bit 5 IRVST Internal Reference Voltage Stable Flag bit 1 Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN High Low Voltage Detect Power Enable bit 1 HLVD enabled 0 HLVD disabled bit 3 0 HLVDL3 HLVDLO Voltage Detection Limit bits 1111 External analog input is used input comes from the HLVDIN pin 1110 Maximum setting 0000 Minimum setting Note 1 See Table 28 6 in Section 28 0 Electrical Characteristics for spe
282. HERE 2 2004 Microchip Technology Inc Preliminary DS39632B page 311 PIC18F2455 2550 4455 4550 BNOV Branch if Not Overflow Syntax BNOV n Operands 128 lt n lt 127 Operation if Overflow bit is o PC 2 2n gt PC Status Affected None Encoding 1110 0101 nnnn nnnn Description If the Overflow bit is o then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words d Cycles 1 2 Q Cycle Activity If Jump 01 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BNOV Jump Before Instruction PC After Instruction address HERE Before Instruction PC BNZ Branch if Not Zero Syntax BNZ n Operands 128 lt n lt 127 Operation if Zero bit is 0 PC 2 2n PC Status Affected None Encoding 1110 0001 nnnn nnnn Description If the Zero bit is 0 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2
283. I RUN mode by setting the IDLEN bit and executing a SLEEP instruc tion If the device is in another Run mode set IDLEN first then clear the SCS bits and execute SLEEP Although the CPU is disabled the peripherals continue to be clocked from the primary clock source specified by the FOSC3 FOSCO configuration bits The OSTS bit remains set see Figure 3 7 When a wake event occurs the CPU is clocked from the primary clock source A delay of interval TCSD is reguired between the wake event and when code execution starts This is reguired to allow the CPU to become ready to execute instructions After the wake up the OSTS bit remains set The IDLEN and SCS bits are not affected by the wake up see Figure 3 8 FIGURE 3 7 TRANSITION TIMING FOR ENTRY TO IDLE MODE 3 4 2 SEC IDLE MODE In SEC IDLE mode the CPU is disabled but the peripherals continue to be clocked from the Timeri oscillator This mode is entered from SEC RUN by set ting the IDLEN bit and executing a SLEEP instruction If the device is in another Run mode set IDLEN first then set SCS1 SCS0 to 01 and execute SLEEP When the clock source is switched to the Timer1 oscillator the primary oscillator is shut down the OSTS bit is cleared and the T1RUN bit is set When a wake event occurs the peripherals continue to be clocked from the Timer1 oscillator After an interval of TCSD following the wake event the CPU begins exe cuting code being clocked by the
284. I mode operation is used to set the SCL clock freguency for either 100 kHz 400 kHz or 1 MHz C operation See Section 19 4 7 Baud Rate for more detail DS39632B page 218 A typical transmit seguence would go as follows 1 10 11 12 Preliminary The user generates a Start condition by setting the Start Enable bit SEN SSPCON2 lt 0 gt SSPIF is set The MSSP module will wait the reguired start time before any other operation takes place The user loads the SSPBUF with the slave address to transmit Address is shifted out the SDA pin until all eight bits are transmitted The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCONZ register SSPCON2 lt 6 gt The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit The user loads the SSPBUF with eight bits of data Data is shifted out the SDA pin until all eight bits are transmitted The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCONZ register SSPCON2 lt 6 gt The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit The user generates a Stop condition by setting the Stop Enable bit PEN SSPCON2 lt 2 gt Interrupt is generated once the Stop condition is complete 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 7 BAUD RATE In IZC Master mode the Ba
285. IC16C71 PIC16C8X PIC17C42 PIC17C43 and PIC17C44 All necessary hardware and software is included to run basic demo programs The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program mer or a PICSTART Plus development programmer The PICDEM 1 demonstration board can be connected to the MPLAB ICE in circuit emulator for testing A prototype area extends the circuitry for additional appli cation components Features include an RS 232 interface a potentiometer for simulated analog input push button switches and eight LEDs 27 16 PICDEM net Internet Ethernet Demonstration Board The PICDEM net demonstration board is an Internet Ethernet demonstration board using the PIC18F452 microcontroller and TCP IP firmware The board supports any 40 pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452 This kit features a user friendly TCP IP stack web server with HTML a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM ICSP MPLAB ICD 2 interface con nector an Ethernet interface RS 232 interface and a 16 x 2 LCD display Also included is the book and CD ROM TCP IP Lean Web Servers for Embedded Systems by Jeremy Bentham 27 17 PICDEM 2 Plus Demonstration Board The PICDEM 2 Plus demonstration board supports many 18 28 and 40 pin microcontrollers including PIC16F87X and PIC18FXX2 devices All the neces sary
286. IHH to the MCLR pin 2 While in Low Voltage ICSP Programming mode the RB5 pin can no longer be used as a general purpose I O pin and should be held low during normal operation 3 When using Low Voltage ICSP Program ming LVP and the pull ups on PORTB are enabled bit 5 in the TRISB register must be cleared to disable the pull up on RB5 and ensure the proper operation of the device 4 If the device Master Clear is disabled verify that either of the following is done to ensure proper entry into ICSP mode a disable Low Voltage Programming CONFIG4L lt 2 gt 0 or b make certain that RB5 KBI1 P GM is held low during entry into ICSP If Single Supply ICSP Programming mode will not be used the LVP bit can be cleared RB5 KBI1 PGM then becomes available as the digital I O pin RB5 The LVP bit may be set or cleared only when using standard high voltage programming VIHH applied to the MCLR VPP RE3 pin Once LVP has been disabled only the standard high voltage programming is available and must be used to program the device Memory that is not code protected can be erased using either a Block Erase or erased row by row then written atany specified VDD If code protected memory is to be erased a Block Erase is required If a Block Erase is to be performed when using Low Voltage Programming the device must be supplied with VDD of 4 5V to 5 5V DS39632B page 300 Preliminary 2004 Microchip Technology
287. INCDIS BDnSTAT lt 4 gt controls the SIE s automatic address increment function Setting INCDIS disables the auto increment of the buffer address by the SIE for each byte transmitted or received This feature should only be enabled when using the Streaming Parallel Port where each data byte is processed to or from the same memory location The Data Toggle Sync Enable bit DTSEN BDnSTAT lt 3 gt controls data toggle parity checking Setting DTSEN enables data toggle synchronization by the SIE when enabled it checks the data packet s par ity against the value of DTS BDnSTAT lt 6 gt If a packet arrives with an incorrect synchronization the data will essentially be ignored it will not be written to the USB RAM and the USB transfer complete interrupt flag will not be set The SIE will send an ACK token back to the host to Acknowledge receipt however The effects of the DTSEN bit on the SIE are summarized in Table 17 3 The Buffer Stall bit BSTALL BDnSTAT lt 2 gt provides support for control transfers usually one time stalls on Endpoint 0 It also provides support for the SET_FEATURE CLEAR_FEATURE commands speci fied in Chapter 9 of the USB specification typically continuous STALLs to any endpoint other than the default control endpoint The BSTALL bit enables buffer stalls Setting BSTALL causes the SIE to return a STALL token to the host if a received token would use the BD in that location The EPSTALL bit in th
288. ION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bito Petails on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRBIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMRSIE CCP2IE 54 UCON PPBRST SEO PKTDIS USBEN RESUME SUSPND 55 UCFG UTEYE UOEMON UPUEN UTRDIS FSEN PPB1 PPB0 55 USTAT ENDP3 ENDP2 ENDP1 ENDPO DIR PPBI 55 UADDR ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO 55 UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRMO 55 UFRMH FRM10 FRM9 FRM8 55 UIR SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 55 UIE SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 55 UEIR BTSEF BTOEF DFNBEF CRC16EF CRCSEF PIDEF 55 UEIE BTSEE BTOEE DFNBEE CRC GEE CRC5EE PIDEE 55 UEPO EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP1 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP2 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP3 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP4 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP5 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP6 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP7 E
289. ISD lt 7 0 gt must be set 1 e Bits TRISE lt 2 1 gt must be cleared 0 If CK1SPP is to be used Bit TRISE lt 0 gt must be cleared 0 If CSPP is to be used Bit TRISB lt 4 gt must be cleared 0 REGISTER 18 1 SPPCON SPP CONTROL REGISTER U 0 U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 SPPOWN SPPEN bit 7 bit 0 bit 7 2 Unimplemented Read as 0 bit 1 SPPOWN SPP Ownership bit 1 USB peripheral controls the SPP 0 Microcontroller directly controls the SPP bit 0 SPPEN SPP Enable bit 1 SPP is enabled 0 SPP is disabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 187 PIC18F2455 2550 4455 4550 REGISTER 18 2 SPPCFG SPP CONFIGURATION REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CLKCFG1 CLKCFGO CSEN CLKIEN WS3 WS2 WS1 WS0 bit 7 bit 0 bit 7 6 CLKCFG1 CLKCFGO SPP Clock Configuration bits 1x CLK1 toggles on read or write of an odd endpoint address CLK2 toggles on read or write of an even endpoint address 01 CLK1 toggles on write CLK2 toggles on read 00 CLK1 toggles only on endpoint address write CLK2 toggles on data read or write bit 5 CSEN SPP Chip Select Pin Enable bit 1 RB4 pin is controlled by the SPP module and f
290. ISH t eAl8981 JXSU pes T N394 0 LOMOV vas 19 SEUI wo MOV Ajpeoyewoyne pejesjo NIDH t N39H lt gt ZNODASS Buiuue1Boid Aq AJ AI9991 E SE peinfyuoo J9 SEN 0 lt g gt ZNOOdS S LAHOY VAS 99uenbes p jmouy y HEJS 0 lt v gt cNOOdSS 01 IUM SNEJS woy EJEJ Buoy AIS W01 MOV SAIS 0 SSEJPPY 1ILUSUEJ LINX HEIS a194 sinooo 4MGdSS 0 SIUM 0 N3S uolnipuoO ues UIBSF T NAS lt 0 gt ZNOD4SS 0 AHM DS39632B page 225 iminary Prel 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge seguence is enabled by setting the Acknowledge sequence enable bit ACKEN SSPCON2 lt 4 gt When this bit is set the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin If the user wishes to gen erate an Acknowledge then the ACKDT bit should be cleared If not the user should set the ACKDT bit before starting an Acknowledge sequence The Baud Rate Generator then counts for one rollover period TBRG and the SCL pin is deasserted pulled high When the SCL pin is sampled high clock arbitration the Baud Rate Generator counts for TBRG The SCL pin is then pulled low Following this the ACKEN bit is automatically cleared the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode Figure 19 23 19 4 12 1 WCOL Status Flag If the user writes the SSPBUF w
291. ISTER 2 R W 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADFM ACQT2 ACQT1 ACQTO ADCS2 ADCS1 ADCSO bit 7 bit 0 ADFM A D Result Format Select bit 1 Right justified 0 Left justified Unimplemented Read as ACGT2 ACGTO A D Acquisition Time Select bits 111 20 TAD 110 16 TAD 101 12 TAD 100 8 TAD 011 6 TAD 010 4 TAD 001 2 TAD 000 0 Tap ADCS2 ADCS0 A D Conversion Clock Select bits 111 FRc clock derived from A D RC oscillator 110 Fosc 64 101 Fosc 16 100 Fosc 4 011 Frc clock derived from A D RC oscillator 010 Fosc 32 001 Fosc 8 000 Fosc 2 Note 1 If the A D FRc clock source is selected a delay of one Toy instruction cycle is added before the A D clock starts This allows the SLEEP instruction to be executed before starting a conversion Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 255 PIC18F2455 2550 4455 4550 The analog reference voltage is software selectable to either the device s positive and negative supply voltage VDD and Vss or the voltage level on the RA3 AN3 VREF and RA2 AN2 VREF CVREF pins The A D converter has a unique feature of being able to operate while the device is in Sleep mode To operate in Sleep the A D conversion clock must be
292. KPS1 T3CKPSO T3CCP1 T3SYNC TMR3CS TMR3ON 53 COPRIL Capture Compare PWM Register 1 LSB 53 CCPR1H Capture Compare PWM Register 1 MSB 53 CCP1CON Pim 2 P1mo DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53 ECCPIAS ECCPASE ECCPAS2 ECCPAS1 ECCPASO PSSACI PSSACO PSSBD1 PSsBDO 53 ECCPIDEL PRSEN PDC60 Pocs PDC40O PDC3 PDC202 PDC1 PDC00 53 Legend unimplemented read as 0 Shaded cells are not used during ECCP operation Note 1 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 2 These bits or registers are unimplemented in 28 pin devices always maintain these bits clear DS39632B page 162 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 0 UNIVERSAL SERIAL BUS USB This section describes the details of the USB peripheral Because of the very specific nature of the module knowledge of USB is expected Some high level USB information is provided in Section 17 10 Overview of USB only for application design reference Designers are encouraged to refer to the official specification published by the USB Imple menters Forum USB IF for the latest information USB Specification Revision 2 0 is the most current specification at the time of publication of this document 17 1 Overview of the USB Peripheral The PIC18FX455 X550 device family contains a full speed and low speed compatible USB Serial Interface Eng
293. L ARG2H gt MOVFF PRODL RES2 PRODH PRODL F MOVF PRODL W i in ce ARG1L ARG2H gt Pee Cass en P Bad STORE id MOVF PRODH W products I PRODH PRODL ADDWFC RES2 F 7 MOVF PRODL W CLRF WREG A ADDWF RES1 F Add cross ADDWFC RES3 F MOVF PRODH W products oz AE E MOVF ARGIH W i ae WREG f MULWF ARG2L s ARGIH ARG2L gt ADDWEC BESS SE PRODH PRODL f MOVF PRODL W a eus ARG1H ARG2L gt NE RSS pa E A KON s MOVF PRODH W products PRODH PRODL ADDWFC RES2 F MOVE PRODL W CLRF WREG i ADDWF RES1 F Add cross ADDWFC RES3 F MOVF PRODH W products I iz R SE E I BTFSS ARG2H 7 ARG2H ARG2L neg SURE WREG BRA SIGN_ARG1 no check ARG1 ADDWEC IA MOVF ARGIL W SUBWF RES2 Example 8 4 shows the sequence to do a 16 x 16 MOVF ARGIH W i signed multiply Eguation 8 2 shows the algorithm SUBWFB RES3 used The 32 bit result is stored in four registers i RES3 RESO To account for the sign bits of the SIGN_ARG1 arguments the MSb for each argument pair is tested Bee res F DRG TH RA Tag and the appropriate subtractions are done PRA CONT CODE eno one MOVF ARG2L W SUBWF RES2 7 MOVE ARG2H W SUBWFB RES3 CONT_CODE DS39632B page 96 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 9 0 INTERRUPTS The PIC18F2455 2550 4455 4550 devices have multiple interrupt sources and an interrupt priority feature that allows eac
294. LIE HLVDIE TMRSIE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 54 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 54 TMRIL Timer1 Register Low Byte 52 TMR1H Timer1 Register High Byte 52 TICON RD16 TIRUN T1CKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMR1ON 52 TMR3H Timer3 Register High Byte 53 TMR3L Timer3 Register Low Byte 53 T3CON RD16 T3CCP2 T3CKPS1 T3CKPSO T3CCP1 TZSYNC TMR3CS TMR3ON 53 CCPRIL Capture Compare PWM Register 1 Low Byte 53 CCPRIH Capture Compare PWM Register 1 High Byte 53 CCPICON P1M1 P1M0 DC1B1 DCIBO CCP1M3 CCP1M2 CCP1M1 CCP1MO 53 CCPR2L Capture Compare PWM Register 2 Low Byte 53 CCPR2H Capture Compare PWM Register 2 High Byte 53 CCP2CON DC2B1 DC2BO CCP2M3 CCP2M2 CCP2M1 CCP2M0 53 Legend unimplemented read as 0 Shaded cells are not used by Capture Compare Timer1 or Timers Note 1 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 2 These bits are unimplemented on 28 pin devices always maintain these bits clear 2004 Microchip Technology Inc Preliminary DS39632B page 145 PIC18F2455 2550 4455 4550 15 4 PWM Mode In Pulse Width Modulation PWM mode the CCPx pin produces up to a 10 bit resolution PWM output Since the CCP2 pin is multiplexed with a PORTB or PORTC data latch the appropriate TRIS
295. LKO The ECIO and ECPIO Oscillator modes function like the EC and ECPLL modes except that the OSC2 pin becomes an additional general purpose I O pin The I O pin becomes bit 6 of PORTA RA6 Figure 2 5 shows the pin connections for the ECIO Oscillator mode FIGURE 2 5 EXTERNAL CLOCK INPUT OPERATION ECIO AND ECPIO CONFIGURATION Clock from OSC1 CLKI Ext System PIC18FXXXX VO OSC2 The internal postscaler for reducing clock frequency in XT and HS modes is also available in EC and ECIO modes 2 2 4 PLL FREQUENCY MULTIPLIER PIC18F2455 2550 4255 4550 devices include a Phase Locked Loop PLL circuit This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source The PLL is enabled in HSPLL XTPLL ECPLL and ECPIO Oscillator modes It is designed to produce a fixed 96 MHz reference clock from a fixed 4 MHz input The output can then be divided and used for both the USB and the microcontroller core clock Because the PLL has a fixed frequency input and output there are eight prescaling options to match the oscillator input frequency to the PLL There is also a separate postscaler option for deriving the microcontroller clock from the PLL This allows the USB peripheral and microcontroller to use the same oscillator input and still operate at different clock speeds In contrast to the postscaler for XT HS and EC modes the availab
296. Legend unimplemented read as 0 Shaded cells are not used by the Watchdog Timer Note 1 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 DS39632B page 292 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 25 3 Two Speed Start up The Two Speed Start up feature helps to minimize the latency period from oscillator start up to code execu tion by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available It is enabled by setting the IESO configuration bit Two Speed Start up should be enabled only if the primary oscillator mode is XT HS XTPLL or HSPLL Crystal based modes Other sources do not reguire an OST start up delay for these Two Speed Start up should be disabled When enabled Resets and wake ups from Sleep mode cause the device to configure itself to run from the inter nal oscillator block as the clock source following the time out of the Power up Timer after a Power on Reset is enabled This allows almost immediate code execution while the primary oscillator starts and the OST is running Once the OST times out the device automatically switches to PRI RUN mode Because the OSCCON register is cleared on Reset events the INTOSC or postscaler clock source is not initially available after a Reset event the INTRC clock is used directly at its base
297. Legend TTL TTL compatible input CMOS CMOS compatible input or output Input P Power 2 Default assignment for CCP2 when CCP2MX configuration bit is set DS39632B page 14 Preliminary 2004 Microchip Technology lnc PIC18F2455 2550 4455 4550 TABLE 1 2 PIC18F2455 2550 PINOUT I O DESCRIPTIONS CONTINUED Pin i Number Pin Buffer ga Pin Name Description PDIP Type Type p SOIC PORTE is a bidirectional I O port RCO0 T10SO T13CKI 11 RCO 1 0 ST Digital O T1OSO O Timer1 oscillator output T13CKI ST Timer1 Timer3 external clock input RC1 T1OSI CCP2 UOE 12 RCI I O ST Digital O T1OSI l CMOS Timer1 oscillator input ccp2 6 O ST Capture 2 input Compare 2 output PWM 2 output UOE External USB transceiver OE output RC2 CCP1 13 RC2 I O ST Digital O CCP1 O ST Capture 1 input Compare 1 output PWM 1 output RC4 D VM 15 RC4 TTL Digital input D O USB differential minus line input output VM TTL External USB transceiver VM input RC5 D VP 16 RC5 TTL Digital input D O USB differential plus line input output VP O TTL External USB transceiver VP input RC6 TX CK 17 RC6 I O ST Digital 1 0 TX O EUSART asynchronous transmit CK O ST EUSART synchronous clock see RX DT RC7 RX DT SDO 18 RC7 O ST Digital I O RX ST EUSART asynchronous receive DT O ST EUSART synchronous data see TX CK SDO O SPI data out RE3
298. Literal Offset Mode for details 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction 2004 Microchip Technology Inc Q1 Q2 Q3 Q4 Decode Read Process No register f Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE CPFSGT REG 0 NGREATER GREATER Before Instruction PC Address HERE w Sr wo After Instruction If REG gt PC Address GREATER If REG lt PC Address NGREATER CPFSLT Compare f with W Skip if f lt W Syntax CPFSLT f a Operands 0 lt f lt 255 ae 0 1 Operation f W Status Affected Encoding Description Words Cycles Q Cycle Activity skip if f lt W unsigned comparison None 0110 000a SELL EGEE Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction If the contents of f are less than the contents of W then the fetched instruction is discarded and a NOP is executed instead making this a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default 1 1 2 Note 3 cycles if skip and followed by a 2 word instru
299. MAG o VDD HLVDIF TABLE 28 6 HIGH LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt Ta lt 85 C for industrial Param No Symbol Characteristic Min Typ Max Units Conditions D420 HLVD Voltage on VDD HLVDL 0000 2 06 2 17 2 28 Transition High to Low HLVDL 0001 2 12 2 23 2 34 HLVDL 0010 2 24 2 36 2 48 HLVDL 0011 2 32 2 44 2 56 HLVDL 0100 2 47 2 60 2 73 HLVDL 0101 2 65 2 79 2 93 HLVDL 0110 2 74 2 89 3 04 HLVDL 0111 2 96 3 12 3 28 HLVDL 1000 3 22 3 39 3 56 HLVDL 1001 3 37 3 55 3 73 HLVDL 1010 3 52 3 71 3 90 HLVDL 1011 3 70 3 90 4 10 HLVDL 1100 3 90 4 11 4 32 HLVDL 1101 4 11 4 33 4 55 lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt HLVDL 1110 4 36 4 59 4 82 2004 Microchip Technology Inc Preliminary DS39632B page 373 PIC18F2455 2550 4455 4550 28 4 AC Timing Characteristics 28 4 1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats 1 TppS2ppS 3 Tcc sT I2C specifications only 2 TppS 4 Ts I2C specifications only T F Frequency T Time Lowercase letters pp and their meanings pp ad
300. MICROCHIP PIC18F2455 2550 4455 4550 Data Sheet 28 40 44 Pin High Performance Enhanced Flash USB Microcontrollers with nanoWatt Technology bza nn ii iii iii i iii ii i A 2004 Microchip Technology Inc Preliminary DS39632B Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may be a violation of the Digital Millennium Copyright Ac
301. N bit and executing a SLEEP instruction If the device is in another Run mode first set IDLEN then set the SCS1 bit and execute SLEEP Although its value is ignored it is recommended that SC SO also be cleared this is to maintain software compatibility with future devices The INTOSC multiplexer may be used to select a higher clock freguency by modifying the IRCF bits before executing the SLEEP instruction When the clock source is switched to the INTOSC multiplexer the primary oscillator is shut down and the OSTS bit is cleared If the IRCF bits are set to any non zero value or the INTSRC bit is set the INTOSC output is enabled The IOFS bit becomes set after the INTOSC output becomes stable after an interval of TIOBST parameter 39 Table 28 12 Clocks to the peripherals continue while the INTOSC source stabilizes If the IRCF bits were previously at a non zero value or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable the IOFS bit will remain set If the IRCF bits and INTSRC are all clear the INTOSC output will not be enabled the IOFS bit will remain clear and there will be no indication of the current clock source When a wake event occurs the peripherals continue to be clocked from the INTOSC multiplexer After a delay of Tcsp following the wake event the CPU begins executing code being clocked by the INTOSC multi plexer The IDLEN and SCS bits are not affected by the wake u
302. No No No Operation Operation Operation Operation Example SUBULNK 23h Before Instruction FSR2 O3FFh PC 0100h After Instruction FSR2 03DCh PC TOS 2004 Microchip Technology Inc Preliminary DS39632B page 347 PIC18F2455 2550 4455 4550 26 2 3 BYTE ORIENTED AND BIT ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Note Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely In addition to eight new commands in the extended set enabling the extended instruction set also enables Indexed Literal Offset Addressing mode Section 5 6 1 Indexed Addressing with Literal Offset This has a significant impact on the way that many commands of the standard PIC 18 instruction set are interpreted When the extended set is disabled addresses embed ded in opcodes are treated as literal memory locations either as a location in the Access Bank a 0 orina GPR bank designated by the BSR a 1 When the extended instruction set is enabled and a 0 however a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as aliteral address For practical purposes this means that all instructions that use the Access RAM bit as an argument that is all byte oriented and bit oriented instructions or almost half of the core PIC18 instructions may behave differently when t
303. ON SET Mnemonic MN 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BYTE ORIENTED OPERATIONS ADDWF f d a Add WREG and f 1 0010 Olda ffff ffff C DC Z OV N 1 2 ADDWFC f d a Add WREG and Carry bit tof 1 0010 00da ffff ffff C DC Z OV N 1 2 ANDWF f d a JAND WREG with f 1 0001 Olda ffff ffff Z N 1 2 CLRF f a Clear f 1 0110 10la ffff ffff Z 2 COMF f d a Complement f 1 0001 lida ffff ffff Z N 1 2 CPFSEQ f a Compare f with WREG skip 1 20r3 0110 00la ffff ffff None 4 CPFSGT fa Compare f with WREG skip gt 1 20r3 0110 010a ffff ffff None 4 CPFSLT fa Compare f with WREG skip lt 1 20r3 0110 000a ffff ffff None 1 2 DECF f d a Decrement f 1 0000 Olda ffff ffff C DC Z OV N 1 2 3 4 DECFSZ f d a Decrement f Skip if 0 1 20r 3 0010 lida ffff ffff None 1 2 3 4 DCFSNZ f d a Decrement f Skip if Not 0 1 20r3 0100 11da ffff ffff None 1 2 INCF f d a Increment f 1 0010 10da ffff ffff C DC Z OV N 1 2 3 4 INCFSZ f d a Increment f Skip if 0 1 20r3 0011 11da ffff ffff None 4 INFSNZ f d a Increment f Skip if Not 0 1 20r3 0100 10da ffff ffff None 1 2 IORWF f d a Inclusive OR WREG with f 1 0001 00da ffff ffff Z N 1 2 MOVF f d a Move f 1 0101 00da ffff ffff Z N 1 MOVFF fs fy Move f source to 1stword 2 1100 ffff ffff ffff None fa destination 2nd word 1111 ffff ffff FEFE MOVWF fa Move WREG to f 1 0110 llla ffff ffff None MULWF f a Multiply WREG with f 1 0000 00la
304. ONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Vpp 2 o RL 464Q Vss CL 50pF Load Condition 2 for all pins except OSC2 CLKO and including D and E outputs as ports 2004 Microchip Technology Inc Preliminary DS39632B page 375 PIC18F2455 2550 4455 4550 28 4 3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28 5 EXTERNAL CLOCK TIMING ALL MODES EXCEPT PLL OSC1 CLKO TABLE 28 8 EXTERNAL CLOCK TIMING REQUIREMENTS S Symbol Characteristic Min Max Units Conditions 1A Fosc External CLKI Frequency DC 48 MHz EC ECIO Oscillator mode Oscillator Frequency 0 1 4 MHz XT XTPLL Oscillator mode 4 25 MHz _ HS Oscillator mode 4 48 MHz HSPLL Oscillator mode 1 Tosc External CLKI Period 20 8 ns EC ECIO Oscillator mode Oscillator Period 250 10 000 ns XT Oscillator mode 25 250 ns HS Oscillator mode 20 8 250 ns HSPLL Oscillator mode 2 TCY Instruction Cycle Time 83 3 ns Toy 4 Fosc 3 TosL External Clock in OSC1 30 ns XT Oscillator mode TosH High or Low Time 10 ns HSOscillator mode 4 TosR External Clock in OSC1 20 ns XTOscilator mode TosF Rise or Fall Time 7 5 ns HS Oscillator mode Note 1 Instruction cycle period Tcy eguals four times the input oscillator time base period for all configurations except PLL All specified values are based on characterization data for
305. ORTA RAG 1 RA5 RA4 RA3 RA2 RA1 RAO 54 LATA LATA6 1 LATA5 LATA4 LATA3 LATA2 LATA1 LATAO 54 TRISA TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 54 ADCON1 VCFGI VCFGO PCFG3 PCFG2 PCFG1 PCFGO 52 CMCON C20UT C10UT C2INV C1INV CIS CM2 CM1 CM0 53 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 53 UCON PPBRST SEO PKTDIS USBEN RESUME SUSPND 55 Legend unimplemented read as 0 Shaded cells are not used by PORTA Note 1 RA6 and its associated latch and data direction bits are enabled as I O pins based on oscillator configuration otherwise they are read as 0 2004 Microchip Technology Inc Preliminary DS39632B page 113 PIC18F2455 2550 4455 4550 10 2 PORTB TRISB and LATB Registers PORTB is an 8 bit wide bidirectional port The corre sponding data direction register is TRISB Setting a TRISB bit 1 will make the corresponding PORTB pin an input i e put the corresponding output driver in a high impedance mode Clearing a TRISB bit 0 will make the corresponding PORTB pin an output i e putthe contents of the output latch on the selected pin The Data Latch register LATB is also memory mapped Read modify write operations on the LATB register read and write the latched output value for PORTB Each of the PORTB pins has a weak internal pull up A single control bit can turn on all the pull ups This is performed by c
306. OSC TMR2 Prescale Value PWM frequency is defined as 1 PWM period When TMR2 is equal to PR2 the following three events occur on the next increment cycle e TMR2 is cleared e The CCPx pin is set exception if PWM duty cycle 0 the CCPx pin will not be set e The PWM duty cycle is latched from CCPRxL into CCPRxH Note The Timer2 postscalers see Section 13 0 Timer2 Module are not used in the determination of the PWM frequency The postscaler could be used to have a servo update rate at a different frequency than the PWM output 15 4 2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON lt 5 4 gt bits Up to 10 bit resolution is available The CCPRxL contains the eight MSbs and the CCPxCON lt 5 4 gt contains the two LSbs This 10 bit value is represented by CCPRxL CCPxCON lt 5 4 gt The following equation is used to calculate the PWM duty cycle in time EQUATION 15 2 PWM Duty Cycle CCPRXL CCPXCON lt 5 4 gt Tosc TMR2 Prescale Value CCPRxL and CCPxCON lt 5 4 gt can be written to at any time but the duty cycle value is not latched into CCPRxH until after a match between PR2 and TMR2 occurs i e the period is complete In PWM mode CCPRxH is a read only register DS39632B page 146 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 The CCPRxH register and a 2 bit internal latch a
307. OSC1 and T1OSI 0 7 VDD VDD V XT HS HSPLL modes D043 OSC1 0 8 VDD VDD V EC model VIHU D D Input 2 4 V VDD 4 35V USB suspended liL Input Leakage Current D060 I O ports 1 HA VSS lt VPIN lt VDD Pin at high impedance D061 MCLR 5 uA Vss lt VPIN lt VDD D063 OSC1 5 HA Vss lt VPIN lt VDD IPU Weak Pull up Current D070 IPURB PORTB weak pull up current 50 400 uA VDD 5V VPIN VSS Note 1 In RC oscillator configuration the OSC1 CLKI pin is a Schmitt Trigger input It is not recommended that the PICmicro device be driven with an external clock while in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin Parameter is characterized but not tested 5 D parameters per USB Specification 2 0 DS39632B page 368 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 28 3 DC Characteristics PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Continued Standard Operating Conditions unless otherwise stated DO CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for industrial Ne Symbol Characteristic Min Max Units Conditi
308. OTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 2004 Microchip Technology Inc Preliminary DS39632B page 357 PIC18F2455 2550 4455 4550 FIGURE 28 1 PIC18F2455 2550 4455 4550 VOLTAGE FREQUENCY GRAPH INDUSTRIAL 6 0V 5 5V 5 0V PIC18FX455 X550 4 5V 4 0V 3 5V 3 0V 2 5V 2 0V 4 2V Voltage 48 MHz Frequency FIGURE 28 2 PIC18LF2455 2550 4455 4550 VOLTAGE FREGUENCY GRAPH INDUSTRIAL 6 0V 5 5V 5 0V PIC18LFX455 X550 4 5V 4 0V 3 5V 3 0V 2 5V 1 2 0V 4 2V Voltage 4 MHz 16 MHZ 25 MHz 48 MHz Freguency Note VDDAPPMIN is the minimum voltage of the PICmicro device in the application DS39632B page 358 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 28 1 DC Characteristics Supply Voltage PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature
309. P 54 TRISA TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 54 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 54 SSPBUF Synchronous Serial Port Receive Buffer Transmit Register 52 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 52 SSPSTAT SMP CKE D A P S RAN UA BF 52 Legend unimplemented read as o Shaded cells are not used by the MSSP in SPI mode Note 1 These bits are unimplemented in 28 pin devices always maintain these bits clear 2 RA6 is configured as a port pin based on various primary oscillator modes When the port pin is disabled all of the associated bits read o 2004 Microchip Technology Inc Preliminary DS39632B page 201 PIC18F2455 2550 4455 4550 19 4 IC Mode The MSSP module in 12C mode fully implements all master and slave functions including general call support and provides interrupts on Start and Stop bits in hardware to determine a free bus multi master function The MSSP module implements the standard mode specifications as well as 7 bit and 10 bit addressing Two pins are used for data transfer e Serial clock SCL RB1 AN10 INT1 SCK SCL e Serial data SDA RBO AN12 INTO FLTO SDI SDA The user must configure these pins as inputs or outputs through the TRISB lt 1 0 gt bits FIGURE 19 7 MSSP BLOCK DIAGRAM I2C MODE Internal
310. P1M2 CCP1M1 CCP1M0 bit 7 bit 0 bit 7 6 P1M1 P1MO Enhanced PWM Output Configuration bits If CCP1M3 CCP1M2 00 01 10 xx P1A assigned as Capture Compare input output P1B P1C P1D assigned as port pins If CCP1M3 CCP1M2 11 00 Single output P1A modulated P1B P1C P1D assigned as port pins 01 Full bridge output forward P1D modulated P1A active P1B P1C inactive 10 Half bridge output P1A P1B modulated with dead band control P1C P1D assigned as port pins 11 Full bridge output reverse P1B modulated P1C active P1A P1D inactive bit 5 4 DC1B1 DC1B0 PWM Duty Cycle bit 1 and bit 0 Capture mode Unused Compare mode Unused PWM mode These bits are the two LSbs of the 10 bit PWM duty cycle The eight MSbs of the duty cycle are found in CCPRIL bit 30 CCP1IM3 CCP1MO Enhanced CCP Mode Select bits 0000 Capture Compare PWM off resets ECCP module 0001 Reserved 0010 Compare mode toggle output on match 0011 Capture mode 0100 Capture mode every falling edge 0101 Capture mode every rising edge 0110 Capture mode every 4th rising edge 0111 Capture mode every 16th rising edge 1000 Compare mode initialize CCP1 pin low set output on compare match set CCP1IF 1001 Compare mode initialize CCP1 pin high clear output on compare match set CCP1IF 1010 Compare mode generate software interrupt only CCP1 pin reverts to I O state 101
311. PC Address ZERO If TEMP 0 PC Address NZERO DS39632B page 321 PIC18F2455 2550 4455 4550 GOTO Unconditional Branch Syntax GOTO k Operands 0 lt k lt 1048575 Operation k gt PC lt 20 1 gt Status Affected None Encoding 1st word k lt 7 0 gt 1110 1111 kjkkk kkkk 2nd word k lt 19 8 gt 1111 k okkk kkkk kkkk Description GOTO allows an unconditional branch anywhere within the entire 2 Mbyte memory range The 20 bit value K is loaded into PC lt 20 1 gt GOTO is always a two cycle instruction Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal No Read literal K lt 7 0 gt operation K lt 19 8 gt Write to PC No No No No operation operation operation operation Example GOTO THERE After Instruction PC Address THERE INCF Increment f Syntax INCF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation f 1 3 dest Status Affected C DC N OV Z Encoding 0010 10da ff ff ffff Description The contents of register f are incremented If d is o the result is placed in W If d is 1 the result is placed back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this inst
312. PDIP Type Type SOIC MCLR VPP RE3 1 Master Clear input or programming voltage input MCLR ST Master Clear Reset input This pin is an active low Reset to the device VPP P Programming voltage input RE3 ST Digital input OSC1 CLKI 9 Oscillator crystal or external clock input OSC1 Analog Oscillator crystal input or external clock source input CLKI Analog External clock source input Always associated with pin function OSC1 See OSC2 CLKO pins OSC2 CLKO RA6 10 Oscillator crystal or clock output OSC2 O Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode CLKO O In select modes OSC2 pin outputs CLKO which has 1 4 the frequency of OSC1 and denotes the instruction cycle rate RA6 O TTL General purpose I O pin Legend TTL TTL compatible input CMOS CMOS compalible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared 2 Default assignment for CCP2 when CCP2MX configuration bit is set DS39632B page 12 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 1 2 PIC18F2455 2550 PINOUT I O DESCRIPTIONS CONTINUED Pin Number Pin Buffer on Pin Name Description PDIP Type Type p SOIC PORTA is a bidirectional I O port RAO ANO 2 RAO O TTL Digital I O AN0 Analog Analog input 0 R
313. PHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP8 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP9 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP10 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP11 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP12 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP13 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP14 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 UEP15 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 55 Legend unimplemented read as 0 Shaded cells are not used by the USB module Note 1 This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space The Buffer Descriptor registers which are mapped into Bank 4 and are not true SFRs are listed separately in Table 17 5 2004 Microchip Technology Inc Preliminary DS39632B page 183 PIC18F2455 2550 4455 4550 17 10 Overview of USB This section presents some of the basic USB concepts and useful information necessary to design a USB device Although much information is provided in this section there is a plethora of information provided within the USB specifications and class specifications Thus the reader is encouraged to refer to the USB specifications for more information www usb org If you are very familiar with the details of USB then this section serves as a basic high l
314. PROCESSOR 1 PROCESSOR 2 i 2004 Microchip Technology Inc Preliminary DS39632B page 197 PIC18F2455 2550 4455 4550 19 3 5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK The master determines when the slave Processor 2 Figure 19 2 is to broadcast data by the software protocol In Master mode the data is transmitted received as soon as the SSPBUF register is written to If the SPI module is only going to receive the SDO output could be disabled programmed as an input The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate As each byte is received it will be loaded into the SSPBUF register as if a normal received byte interrupts and status bits appropriately set This could be useful in receiver applications as a Line Activity Monitor mode FIGURE 19 3 The clock polarity is selected by appropriately programming the CKP bit SSPCON1 lt 4 gt This then would give waveforms for SPI communication as shown in Figure 19 3 Figure 19 5 and Figure 19 6 where the MSB is transmitted first In Master mode the SPI clock rate bit rate is user programmable to be one of the following e Fosc 4 or TCY e Fosc 16 or 4 TCY e Fosc 64 or 16 TCY e Timer2 output 2 This allows a maximum data rate at 40 MHz of 10 00 Mbps Figure 19 3 shows the waveforms for Master mode When the CKE bit is set
315. PTRU allows access to the device configuration bits 2 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as o 3 These registers and or bits are not implemented on 28 pin devices and are read as o Reset values are shown for 40 44 pin devices individual unimplemented bits should be interpreted as 4 RAGis configured as a port pin based on various primary oscillator modes When the port pin is disabled all of the associated bits read o 5 REBisonly available as a port pin when the MCLRE configuration bit is clear otherwise the bit reads as 0 6 RC5 and RC4 are only available as port pins when the USB module is disabled UCON lt 3 gt 0 DS39632B page 68 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 5 2 REGISTER FILE SUMMARY PIC18F2455 2550 4455 4550 CONTINUED File Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOR BOR m pa EEADR EEPROM Address Register 0000 0000 53 89 EEDATA EEPROM Data Register 0000 0000 53 89 EECON2 EEPROM Control Register 2 not a physical register 0000 0000 53 80 EECON1 EEPGD CFGS FREE WRERR WREN WR RD xx 0 x000 53 81 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMRSIP CCP2IP 1111 1111 54 107 PI
316. Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 27 0 DEVELOPMENT SUPPORT The PICmicro microcontrollers are supported with a full range of hardware and software development tools e Integrated Development Environment MPLAB IDE Software e Assemblers Compilers Linkers MPASM Assembler MPLAB C17 and MPLAB C18 C Compilers MPLINK Object Linker MPLIB Object Librarian MPLAB C30 C Compiler MPLAB ASM30 Assembler Linker Library Simulators MPLAB SIM Software Simulator MPLAB dsPIC30 Software Simulator e Emulators MPLAB ICE 2000 In Circuit Emulator MPLAB ICE 4000 In Circuit Emulator In Circuit Debugger MPLAB ICD 2 e Device Programmers PRO MATE II Universal Device Programmer PICSTART Plus Development Programmer MPLAB PM3 Device Programmer e Low Cost Demonstration Boards PICDEM 1 Demonstration Board PICDEM net Demonstration Board PICDEM 2 Plus Demonstration Board PICDEM 3 Demonstration Board PICDEM 4 Demonstration Board PICDEM 17 Demonstration Board PICDEM 18R Demonstration Board PICDEM LIN Demonstration Board PICDEM USB Demonstration Board Evaluation Kits KEELOQ Evaluation and Programming Tools PICDEM MSC microlD Developer Kits CAN PowerSmart Developer Kits Analog 27 1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8 1
317. Program Memory Instructions 12288 16384 12288 16384 Data Memory Bytes 2048 2048 2048 2048 Data EEPROM Memory Bytes 256 256 256 256 Interrupt Sources 19 19 20 20 I O Ports Ports A B C E Ports A B C E Ports A B C D E Ports A B C D E Timers 4 4 4 4 Capture Compare PWM Modules 2 2 1 1 Enhanced Capture 0 0 1 1 Compare PWM Modules Serial Communications MSSP MSSP MSSP MSSP Enhanced USART Enhanced USART Enhanced USART Enhanced USART Universal Serial Bus USB Module 1 1 1 1 Streaming Parallel Port SPP No No Yes Yes 10 bit Analog to Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels Comparators 2 2 2 2 Resets and Delays POR BOR POR BOR POR BOR POR BOR RESET Instruction RESET Instruction RESET Instruction RESET Instruction Stack Full Stack Full Stack Full Stack Full Stack Underflow Stack Underflow Stack Underflow Stack Underflow PWRT OST PWRT OST PWRT OST PWRT OST MCLR optional MCLR optional MCLR optional MCLR optional WDT WDT WDT WDT Programmable Low Voltage Yes Yes Yes Yes Detect Programmable Brown out Reset Yes Yes Yes Yes Instruction Set 75 Instructions 83 with Extended Instruction Set 75 Instructions 83 with Extended Instruction Set 75 Instructions 83 with Extended Instruction Set 75 Instructions 83 with Extended In
318. R Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible Ideally this means that an entire address does not need to be provided for each read or write operation For PIC18 devices this is accom plished with a RAM banking scheme This divides the memory space into 16 contiguous banks of 256 bytes Depending on the instruction each location can be addressed directly by its full 12 bit address or an 8 bit low order address and a 4 bit bank pointer Most instructions in the PIC18 instruction set make use of the bank pointer known as the Bank Select Register BSR This SFR holds the 4 Most Significant bits of a location s address the instruction itself includes the 8 Least Significant bits Only the four lower bits of the BSR are implemented BSR3 BSRO The upper four bits are unused they will always read 0 and cannot be written to The BSR can be loaded directly by using the MOVLB instruction The value of the BSR indicates the bank in data memory The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank s lower boundary The relationship between the BSR s value and the bank division in data memory is shown in Figure 5 6 Since up to 16 registers may share the same low order address the user must always be careful to ensure that the proper bank is selected before performing a data read or write For example writ
319. R does not violate the device s electrical specification R1 gt 1 KQ will limit any current flowing into MCLR from external capacitor C in the event of MCLR VPP pin breakdown due to Electro static Discharge ESD or Electrical Overstress EOS Preliminary DS39632B page 45 PIC18F2455 2550 4455 4550 4 4 Brown out Reset BOR PIC18F2455 2550 4455 4550 devices implement a BOR circuit that provides the user with a number of configuration and power saving options The BOR is controlled by the BORV1 BORVO and BOREN1 BORENO configuration bits There are a total of four BOR configurations which are summarized in Table 4 1 The BOR threshold is set by the BORV1 BORVO bits If BOR is enabled any values of BOREN1 BORENO except 00 any drop of VDD below VBOR parameter D005 Section 28 1 DC Characteristics for greater than TBOR parameter 35 Table 28 12 will reset the device A Reset may or may not occur if VDD falls below VBOR for less than TBOR The chip will remain in Brown out Reset until VDD rises above VBOR If the Power up Timer is enabled it will be invoked after VDD rises above VBOR it then will keep the chip in Reset for an additional time delay TPWRT parameter 33 Table 28 12 If VDD drops below VBOR while the Power up Timer is running the chip will go back into a Brown out Reset and the Power up Timer will be initialized Once VDD rises above VBOR the Power up Timer will execute the ad
320. R2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 0000 0000 54 103 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMRSIE CCP2IE 0000 0000 54 105 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 54 106 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 54 102 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 54 104 OSCTUNE INTSRC TUN4 TUN3 TUN2 TUN1 TUNO 0 0 0000 54 28 TRISE TRISE2 TRISE1 TRISEO 111 54 124 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISDO 1111 1111 54 122 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 11 111 54 119 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 1111 1111 54 116 TRISA TRISAG6 4 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISAO 111 1111 54 113 LATE LATE2 LATE1 LATEO xxx 54 124 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATDO XXXX xxxx 54 122 LATC LATC7 LATC6 LATC2 LATC1 LATCO xx xxx 54 119 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATBO XXXX xxxx 54 116 LATA LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATAO xxx xxxx 54 113 PORTE RDPU RE3 RE26 RE1 REO o x000 54 123 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 54 122 PORTC RC7 RC6 RC5 6 RC4 6 RC2 RC1 RCO xxxx xxx 54 119 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO XXXX xxxx 54 116 PORTA RAG RA5 RA4 RA3 RA2 RA1 RAO x0x 0000 54
321. RAM bank is specified by BSR register bbb Bit address within an 8 bit file register 0 to 7 BSR Bank Select Register Used to select the current RAM bank ALU status bits Carry Digit Carry Zero Overflow Negative Destination select bit d 0 store result in WREG d 1 store result in file register f dest Destination either the WREG register or the specified register file location f 8 bit register file address 00h to FFh or 2 bit FSR designator 0h to 3h 12 bit register file address 000h to FFFh This is the source address fa 12 bit register file address 000h to FFFh This is the destination address GIE Global Interrupt Enable bit k Literal field constant data or label may be either an 8 bit 12 bit or a 20 bit value label Label name mm The mode of the TBLPTR register for the table read and table write instructions Only used with table read and table write instructions No change to register such as TBLPTR with table reads and writes Post Increment register such as TBLPTR with table reads and writes Post Decrement register such as TBLPTR with table reads and writes Pre Increment register such as TBLPTR with table reads and writes n The relative address 2 s complement number for relative branch instructions or the direct address for Call Branch and Return instructions PC Program Cou
322. REF source 1 VREF AN2 0 VSS bit 4 VCFGO Voltage Reference Configuration bit VREF source 1 VREF AN3 0 VDD bit 3 0 PCFG3 PCFGO A D Port Configuration Control bits PCFG3 D o lt eee n a le PCFGO Z z z z z Zz Z Z lt lt lt lt lt lt lt lt lt lt lt lt lt 00001 A A A A A A A A A A A A A 0001 A A A A A A A A A A A A A 0010 A A A A A A A A A A A A A 0011 D A A A A A A A A A A A A 0100 D D A A A A A A A A A A A 0101 D D D A A A A A A A A A A 0110 D D D D A A A A A A A A A 01110 D D D D D A A A A A A A A 1000 D D D D D D A A A A A A A 1001 D D D D D D D A A A A A A 1010 D D D D D D D D A A A A A 1011 D D D D D D D D D A A A A 1100 D D D D D D D D D D A A A 1101 D D D D D D D D D D D A A 1110 D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D A Analog input D Digital I O Note 1 The POR value of the PCFG bits depends on the value of the PBADEN configuration bit When PBADEN 1 PCFG lt 3 0 gt 0000 when PBADEN o PCFG lt 3 0 gt 0111 2 AN5 through AN7 are available only on 40 44 pin devices Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 254 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 21 3 bit 7 bit 6 bit 5 3 bit 2 0 ADCON2 A D CONTROL REG
323. RF POSTINCO Clear INDF register then inc pointer BTFSS FSROH 1 All done with Bank1 BRA NEXT NO clear next CONTINUE VES continue DS39632B page 72 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 5 4 3 1 FSR Registers and the INDF Operand At the core of indirect addressing are three sets of registers FSRO FSR1 and FSR2 Each represents a pair of 8 bit registers FSRnH and FSRnL The four upper bits of the FSRnH register are not used so each FSR pair holds a 12 bit value This represents a value that can address the entire range of the data memory in a linear fashion The FSR register pairs then serve as pointers to data memory locations Indirect addressing is accomplished with a set of Indirect File Operands INDFO through INDF2 These can be thought of as virtual registers they are FIGURE 5 7 INDIRECT ADDRESSING mapped in the SFR space but are not physically imple mented Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair A read from INDF 1 for example reads the data at the address indicated by FSR1H FSR1L Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction s target The INDF operand is just a convenient way of using the pointer Because indirect addressing uses a full 12 bit address data RAM banking
324. RISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISDO 54 SSPBUF Synchronous Serial Port Receive Buffer Transmit Register 52 SSPADD Synchronous Serial Port Address Register in I C Slave mode 52 SSP Baud Rate Register in C Master mode TMR2 Timer2 Register 52 PR2 Timer2 Period Register 52 SSPCONI WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO 52 SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 52 SSPSTAT SMP CKE D A P S R W UA BF 52 Legend unimplemented read as 0 Shaded cells are not used by the MSSP in IC mode Note 1 These registers or bits are not implemented in 28 pin devices DS39632B page 232 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 20 0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER EUSART The Universal Synchronous Asynchronous Receiver Transmitter USART module is one of the two serial O modules USART is also known as a Serial Communications Interface or SCI The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers It can also be configured as a half duplex synchronous system that can communicate with peripheral devices such as A D or D A integrated circuits serial EEPROMs and so on The Enhanced Universal Synchronous Receiver Transmitter EUSART module implements additional features including Automatic Baud Rate Detection ABD a
325. RTS X gt Debugger Fail Safe Clock Monitor Band Gap TCRST 3 ICRST Xt Reference MORD D USB Voltage Regulator VusB De BOR Data n N i HLVD EEPROM Timer0 Timer1 Timer2 Timer3 ADC Comparator ECCP1 CCP2 MSSP EUSART 10 bit USB Note 1 RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled RAO ANO RA1 AN1 RA2 AN2 VREF CVREF RA3 AN3 VREF RA4 TOCKI C1OUT RCV RAS AN4 SS HLVDIN C2OUT OSC2 CLKO RA6 RBO AN12 INTO FLTO SDI SDA RB1 AN10 INT1 SCK SCL RB2 ANB INT2 VMO RB3 AN9 CCP24 VPO RB4 AN11 KBIO CSSPP RB5 KBI1 PGM RB6 KBI2 PGC RB7 KBI3 PGD RCO T10SO T13CKI RC1 T10SI CCP2 U0E RC2 CCP1 P1A RC4 D VM RC5 D VP RC6 TX CK RC7 RX DT SDO RDO SPPO RD4 SPP4 RD5 SPP5 P1B RD6 SPP6 P1C RD7 SPP7 P1D REO AN5 CK1SPP RE1 AN6 CK2SPP RE2 AN7 OESPP MCLR VPP RE301 2 OSC1 CLKI and OSC2 CLKO are only available in select oscillator modes and when these pins are not being used as digital I O Refer to Section 2 0 Oscillator Configurations for additional information 3 These pins are only available on 44 pin TQFP under certain conditions Refer to Section 25 9 Special ICPORT Features Designated Packages Only for additional information 2004 Microchip Technology Inc Preliminary DS39632B page 11 PIC18F2455 2550 4455 4550 TABLE 1 2 PIC18F2455 2550 PINOUT I O DESCRIPTIONS Pin Pin Name Number Pin Buffer Description
326. Receive mode for 1 C 0 Receive Idle PEN Stop Condition Enable bit Master mode only 1 Initiate Stop condition on SDA and SCL pins Automatically cleared by hardware 0 Stop condition Idle RSEN Repeated Start Condition Enabled bit Master mode only 1 Initiate Repeated Start condition on SDA and SCL pins Automatically cleared by hardware 0 Repeated Start condition Idle SEN Start Condition Enabled Stretch Enabled bit In Master mode 1 Initiate Start condition on SDA and SCL pins Automatically cleared by hardware 0 Start condition Idle In Slave mode 1 Clock stretching is enabled for both slave transmit and slave receive stretch enabled 0 Clock stretching is disabled Note 1 For bits ACKEN RCEN PEN RSEN SEN If the I C module is not in the Idle mode these bits may not be set no spooling and the SSPBUF may not be written or writes to the SSPBUF are disabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 205 PIC18F2455 2550 4455 4550 19 4 2 OPERATION The MSSP module functions are enabled by setting MSSP enable bit SSPEN SSPCON1 lt 5 The SSPCON1 register allows control of the 2C operation Four mode selection bits SSPCON1 lt 3 0 gt allow one of the following 12C modes to be selected 12C Mas
327. S Example Operation on Table Pointer ansk TBLPTR is not modified BLWT an m TBLPTR is incremented after the read write A n TBLPTR is decremented after the read write ace TBLPTR is incremented before the read write FIGURE 6 3 TABLE POINTER BOUNDARIES BASED ON OPERATION 21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 A TABLE ERASE TBLPTR lt 21 6 gt TABLE WRITE TBLPTR lt 21 5 gt TABLE READ TBLPTR lt 21 0 gt DS39632B page 82 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 6 3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM Table reads from program memory are performed one byte at a time FIGURE 6 4 TBLPTR points to a byte address in program space Executing TBLRD places the byte pointed to into TABLAT In addition TBLPTR can be modified automatically for the next table read operation The internal program memory is typically organized by words The Least Significant bit of the address selects between the high and low bytes of the word Figure 6 4 shows the interface between the internal program memory and the TABLAT READS FROM FLASH PROGRAM MEMORY Even Byte Address Program Memory Odd Byte Address TBLPTR xxxxx1 TBLPTR xxxxx0 Instruction Register TA
328. S39632B page 308 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 ANDWF AND W with f Syntax ANDWF f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation W AND f gt dest Status Affected N Z Encoding 0001 01da FEEL Eee Description The contents of W are ANDed with register f If is o the result is stored in W If d is 1 the result is stored back in register f default If a is o the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 03 Q4 Decode Read Process Write to register f Data destination Example ANDWF REG 0 0 Before Instruction W 17h REG C2h After Instruction w 02h REG C2h BC Branch if Carry Syntax BC n Operands 128 lt n lt 127 Operation if Carry bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0010 nnnn nnnn Description If the Carry bit is 1 then the program will branch The 2 s complement number 2n is adde
329. SBDO 53 ECCPIDEL PRSEN PDC6 PDC5 PDC4 PDC32 PDC20 PDCI Poco 53 Legend unimplemented read as 0 Shaded cells are not used by PWM or Timer2 Note 1 The SBOREN bit is only available when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 2 These bits are unimplemented on 28 pin devices always maintain these bits clear DS39632B page 148 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 16 0 ENHANCED CAPTURE COMPARE PWM ECCP MODULE Note The ECCP module is implemented only in 40 44 pin devices In PIC18F4455 4550 devices CCP 1 is implemented as a standard CCP module with Enhanced PWM capabilities These include the provision for 2 or 4 output channels user selectable polarity dead band control and automatic shutdown and restart The Enhanced features are discussed in detail in Section 16 4 Enhanced PWM Mode Capture Compare and single output PWM functions of the ECCP module are the same as described for the standard CCP module The control register for the Enhanced CCP module is shown in Register 16 1 It differs from the CCPxCON registers in PIC18F2255 2550 devices in that the two Most Significant bits are implemented to control PWM functionality REGISTER 16 1 CCP1CON ECCP CONTROL REGISTER 40 44 PIN DEVICES R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 P1MI P1MO DC1B1 DC1BO CCP1M3 CC
330. STATUS TEMP STATUS TEMP located anywhere BSR TMEP located anywhere MOVFF BSR BSR TEMP USER ISR CODE MOVFF BSR TEMP BSR MOVE W TEMP W MOVFF STATUS TEMP STATUS Restore BSR Restore WREG Restore STATUS 2004 Microchip Technology Inc Preliminary DS39632B page 109 PIC18F2455 2550 4455 4550 NOTES DS39632B page 110 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 10 0 1 0 PORTS Depending on the device selected and features enabled there are up to five ports available Some pins of the I O ports are multiplexed with an alternate function from the peripheral features on the device In general when a peripheral is enabled that pin may not be used as a general purpose I O pin Each port has three registers for its operation These registers are TRIS register data direction register e Port register reads the levels on the pins of the device e LAT register output latch The Data Latch register LATA is useful for read modify write operations on the value that the I O pins are driving A simplified model of a generic I O port without the interfaces to other peripherals is shown in Figure 10 1 FIGURE 10 1 GENERIC I O PORT OPERATION RD LAT Data BUS p a gt x WRLAT VO pin or Port b CK N Data Latch e D Q e WR TRIS CK TRIS Latch Input U Jette e RD TRIS lt l
331. STOPPED DONE If the A D clock source is selected as RC a time of Tcy is added before the A D clock starts This allows the SLEEP instruction to be executed 2 This is a minimal RC delay typically 100 ns which also disconnects the holding capacitor from the analog input 2004 Microchip Technology Inc Preliminary DS39632B page 393 PIC18F2455 2550 4455 4550 TABLE 28 29 A D CONVERSION REGUIREMENTS t Symbol Characteristic Min Max Units Conditions 130 TAD A D Clock Period PIC18FXXXX 0 7 25 001 us TOSC based VREF gt 3 0V PIC18LFXXXX 14 25 07 us Vpp 2 0V Tosc based VREF full range PIC18FXXXX TBD 1 us A D RC mode PIC18LFXXXX TBD 3 us VDD 2 0V A D RC mode 131 TCNV Conversion Time 11 12 TAD not including acquisition time Note 2 132 TACQ Acquisition Time Note 3 1 4 us 40 C to 85 C TBD us 0 C lt to lt 85 C 135 Tswc Switching Time from Convert Sample Note 4 137 TDIS Discharge Time 0 2 us Legend TBD To Be Determined Note 1 Thetime of the A D clock period is dependent on the device frequency and the TAD clock divider 2 ADRES register may be read on the following TCY cycle 3 The time for the holding capacitor to acquire the New input voltage when the voltage changes full scale after the conversion VDD to Vss or Vss to VDD The source impedance RS on the input channels is 50Q 4
332. Start up and Section 25 4 Fail Safe Clock Monitor for more information on WDT Fail Safe Clock Monitor and Two Speed Start up The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler The INTOSC output is disabled if the clock is provided directly from the INTRC output Regardless of the Run or Idle mode selected the USB clock source will continue to operate If the device is operating from a crystal or resonator based oscillator that oscillator will continue to clock the USB module the core and all other modules will switch to the new clock source If the Sleep mode is selected all clock sources are stopped Since all the transistor switching currents have been stopped Sleep mode achieves the lowest current consumption of the device only leakage currents Sleep mode should never be invoked while the USB module is operating and connected The only exception is when the device has been issued a Suspend com mand over the USB Once the module has suspended Operation and shifted to a low power state the microcontroller may be safely put into Sleep mode Enabling any on chip feature that will operate during Sleep will increase the current consumed during Sleep The INTRC is required to support WDT operation The Timer1 oscillator may be operating to support a real time clock Other features may be operating that do not require a device clock source i e SSP slave
333. TABLE 28 17 EXAMPLE SPITM MODE REGUIREMENTS SLAVE MODE TIMING CKE 0 de Symbol Characteristic Min Max Units Conditions 70 TssL2scH SS L to SCK L or SCK T Input Tcv ns TssL2scL 71 TscH SCK Input High Time Continuous 1 25 TCY 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK Input Low Time Continuous 1 25 TCY 30 ns 72A Slave mode Single Byte 40 ns Note 1 73 TdiV2scH Setup Time of SDI Data Input to SCK Edge 100 ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1 5 TCY 40 ns Note 2 74 TscH2diL Hold Time of SDI Data Input to SCK Edge 100 ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 2 0V 76 TdoF SDO Data Output Fall Time 25 ns 77 TssH2doZ SS T to SDO Output High Impedance 10 50 ns 78 TscR SCK Output Rise Time Master mode PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 2 0V 79 TscF SCK Output Fall Time Master mode 25 ns 80 TscH2doV SDO Data Output Valid after SCK Edge PIC18FXXXX 50 ns TscL2doV PIC18LFXXXX 100 ns VoD 2 0V 83 TscH2ssH SS T after SCK edge 1 5 TcY 40 ns TscL2ssH Note 1 Requires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used DS39632B page 384 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 455
334. TERS ASSOCIATED WITH PORTC Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTC RC7 RC6 Rc5 RCA RC2 RC1 RCO 54 LATC LATC7 LATC6 LATC2 LATC1 LATCO 54 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 54 UCON PPBRST SEO PKTDIS USBEN RESUME SUSPND 55 Legend unimplemented read as 0 Shaded cells are not used by PORTC Note 1 RC5 and RCA are only available as port pins when the USB module is disabled UCON lt 3 gt 0 2004 Microchip Technology Inc Preliminary DS39632B page 119 PIC18F2455 2550 4455 4550 10 4 PORTD TRISD and LATD Registers Note PORTD is only available on 40 44 pin devices PORTD is an 8 bit wide bidirectional port The corre sponding data direction register is TRISD Setting a TRISD bit 1 will make the corresponding PORTD pin an input i e put the corresponding output driver in a high impedance mode Clearing a TRISD bit 0 will make the corresponding PORTD pin an output i e put the contents of the output latch on the selected pin The Data Latch register LATD is also memory mapped Read modify write operations on the LATD register read and write the latched output value for PORTD All pins on PORTD are implemented with Schmitt Trigger input buffers Each pin is individually configurable as an input or output Each of the PORTD pins has a weak in
335. TIMEROSCILLATOR 23 4 Osc Type Freg C1 C2 LP 32 kHz 27 pF 27 pF Note 1 Microchip suggests these values as a starting point in validating the oscillator circuit 2 Higher capacitance increases the stability of the oscillator but also increases the start up time 3 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropriate values of external components 4 Capacitor values are for design guidance only 12 3 1 USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power managed modes By setting the clock select bits SCS1 SCSO OSCCON lt 1 0 gt to 01 the device switches to SEC RUN mode both the CPU and peripherals are clocked from the Timer1 oscillator If the IDLEN bit OSCCON lt 7 gt is cleared and a SLEEP instruction is executed the device enters SEC_IDLE mode Additional details are available in Section 3 0 Power Managed Modes Whenever the Timer1 oscillator is providing the clock source the Timer1 system clock status flag T1RUN TICON lt 6 gt is set This can be used to determine the controller s current clocking mode It can also indicate the clock source being currently used by the Fail Safe Clock Monitor If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock polling the T1RUN bit will indicate whether the
336. The internal oscillator s output has been calibrated at the factory but can be adjusted in the user s applica tion This is done by writing to the OSCTUNE register Register 2 1 The tuning sensitivity is constant throughout the tuning range When the OSCTUNE register is modified the INTOSC and INTRC frequencies will begin shifting to the new frequency The INTRC clock will reach the new frequency within 8 clock cycles approximately 8 32 us 256 us The INTOSC clock will stabilize within 1 ms Code execution continues during this shift There is no indication that the shift has occurred The OSCTUNE register also contains the INTSRC bit The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected This is covered in greater detail in Section 2 4 1 Oscillator Control Register 2 2 5 3 Internal Oscillator Output Frequency and Drift The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8 0 MHz However this frequency may drift as VDD or tempera ture changes which can affect the controller operation in a variety of ways The low frequency INTRC oscillator operates indepen dently of the INTOSC source Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa 2004 Microchip Technology Inc Preliminary DS39632B page 27 PIC18F24
337. Timer1 oscillator The IDLEN and SCS bits are not affected by the wake up the Timer1 oscillator continues to run see Figure 3 8 Note The Timeri oscillator should already be running prior to entering SEC_IDLE mode If the T1OSCEN bit is not set when the SLEEP instruction is executed the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur If the Timer1 oscillator is enabled but not yet running peripheral clocks will be delayed until the oscillator has started In such situations initial oscillator operation is far from stable and unpredictable operation may result 91 Q a HO LE Se Nee Al Ad cpu cee VM j MVE NE NE zat a a Va a SE za NU za NE sa NE dane 2I PC X PC 2 FIGURE 3 8 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE QE pei EE S gt a2 93 Q4 OSC1 NA f f N TA TT f CPU Clock Peripheral TT ca TE Clock i 1 Pau FC Wake Event DS39632B page 40 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 3 4 3 RC IDLE MODE In RC IDLE mode the CPU is disabled but the periph erals continue to be clocked from the internal oscillator block using the INTOSC multiplexer This mode allows for controllable power conservation during Idle periods From RC RUN this mode is entered by setting the IDLE
338. V 3 6 11 uA 85 C PIC18LFX455 X550 4 5 11 uA 40 C Fosc 31 kHz 4 8 11 uA 25 C VDD 3 0V RC_IDLE mode 5 8 15 uA 85 C INTRC source All devices 9 2 16 uA 40 C 9 8 16 uA 25 C VDD 5 0V 11 4 36 uA 85 C PIC18LFX455 X550 165 350 LA 40 C 175 350 UA 25 C VDD 2 0V 190 350 UA 85 C PIC18LFX455 X550 250 500 HA 40 C Fosc 1 MHz 270 500 HA 25 C VDD 3 0V RC_IDLE mode 290 500 uA 85 C INTOSC source All devices 0 50 1 mA 40 C 0 52 1 mA 25 C VDD 5 0V 0 55 1 mA 85 C PIC18LFX455 X550 340 500 LA 40 C 350 500 A 25 C Vpp 2 0V 360 500 HA 85 C PIC18LFX455 X550 520 900 HA 40 C Fosc 4 MHz 540 900 LA 25 C VDD 3 0V RC_IDLE mode 580 900 uA 85 C INTOSC source All devices 1 0 1 6 mA 40 C 1 1 1 5 mA 25 C VDD 5 0V 1 1 1 4 mA 85 C Legend Shading of rows is to assist in readability of the table Note 1 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current c
339. VREF VREF 0 Comparator reference source CVRSRC VDD Vss bit 3 0 CVR3 CVRO Comparator VREF Value Selection bits 0 lt CVR3 CVRO lt 15 When CVRR 1 CVREF CVR3 CVRO 24 x CVRSRC When CVRR 0 CVREF CVRSRC 4 CVR3 CVRO 32 x CVRSRC Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 269 PIC18F2455 2550 4455 4550 COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVR3 CVRO nl p CVREF 16 to 1 MUX FIGURE 23 1 CVRSS 1 VREF v VDD T CVRSS 0 8R CVRE R R R R 16 Steps 4 I R R R CVRR CVRSS 1 VREF c be q es 0 23 2 Voltage Reference Accuracy Error The full range of voltage reference cannot be realized due to the construction of the module The transistors on the top and bottom of the resistor ladder network Figure 23 1 keep CVREF from approaching the refer ence source rails The voltage reference is derived from the reference source therefore the CVREF output changes with fluctuations in that source The tested absolute accuracy of the voltage reference can be found in Section 28 0 Electrical Characteristics 23 3 Operation During Sleep When the device wakes up from Sl
340. Vic cs k EK USB Bus USB Clock from the FS lt X D 4 Oscillator Module Eu oE D Pd D v I A na External I 24 OE Transceiver USB Control qe peeve ET USB Bus ang X ve lt 1 Configuration 11 lt 5 ROV lt gt gt lt t USB 1 1 I ED vmo OL __ SIE J gt X veo X SPP7 SPPO 1 Kbyte maa CK1SPP USB RAM p _ RC CK2SPP gt CSSPP CIX OESPP I s s s Note 1 This signal is only available if the internal transceiver is disabled UTRDIS 1 2 The internal pull up resistors should be disabled UPUEN o if external pull up resistors are used 3 Do not enable the internal regulator when using an external 3 3V supply 2004 Microchip Technology Inc Preliminary DS39632B page 163 PIC18F2455 2550 4455 4550 17 2 USB Status and Control The operation of the USB module is configured and managed through three control registers In addition a total of 19 registers are used to manage the actual USB transactions The registers are USB Control register UCON USB Configuration register UCFG USB Transfer Status register USTAT USB Device Address register UADDR Frame Number registers UFRMH UFRML e Endpoint Enable registers 0 through 15 UEPn 17 2 1 USB CONTROL REGISTER UCON The USB Control register Register 17 1 contains bits needed to control the module behavior during transfers The register contai
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342. XT Oscillator used as USB clock source 11 INTIO Internal Oscillator used as microcontroller clock source EC Oscillator used as USB clock source digital I O on RA6 12 INTCKO Internal Oscillator used as microcontroller clock source EC Oscillator used as USB clock source Fosc 4 output on RA6 2 2 1 OSCILLATOR MODES AND USB OPERATION Because of the unigue reguirements of the USB module a different approach to clock operation is necessary In previous PlCmicro devices all core and peripheral clocks were driven by a single oscillator source the usual sources were primary secondary or the internal oscillator With PIC18F2455 2550 4455 4550 devices the primary oscillator becomes part of the USB module and cannot be associated to any other clock source Thus the USB module must be clocked from the primary clock source however the microcontroller core and other peripherals can be separately clocked from the secondary or internal oscillators as before Because of the timing requirements imposed by USB an internal clock of either 6 MHz or 48 MHz is required while the USB module is enabled Fortunately the microcontroller and other peripherals are not required to run at this clock speed when using the primary oscillator There are numerous options to achieve the USB module clock requirement and still provide flexibil ity for clocking the rest of the device from the primary oscillator source These are detailed in Section 2 3 Os
343. XXX xxxx 53 142 CCPRIL Capture Compare PWM Register 1 Low Byte XXXX xxxx 53 142 CCP1CON Pim1 P1MO6 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1MO 0000 0000 53 141 149 CCPR2H Capture Compare PWM Register 2 High Byte XXXX xxxx 53 142 CCPR2L Capture Compare PWM Register 2 Low Byte XXXX xxxx 53 142 CCP2CON DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 00 0000 53 141 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01 0 0 00 53 236 ECCP1DEL PRSEN PDC6 PDC5 PDCA46 PDC36 PDC26 PDC16 PDCO 0000 0000 53 158 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPASO PSSAC1 PSSACO PSSBD1 PSSBDO 0000 0000 53 159 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVRO 0000 0000 53 269 CMCON C20UT C1OUT C2INV CTINV CIS CM2 CM1 CMO 0000 0111 53 263 TMR3H Timer3 Register High Byte XXXX XXXX 53 139 TMR3L Timer3 Register Low Byte XXXX XXXX 53 139 T3CON RD16 T3CCP2 T3CKPS1 T3CKPSO T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 53 137 SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 53 237 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 53 237 RCREG EUSART Receive Register 0000 0000 53 244 TXREG EUSART Transmit Register 0000 0000 53 242 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 53 234 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 53 235 Legend x unknown u unchanged unimplemented g value depends on condition Note 1 Bit21 ofthe TBL
344. a write to the port can cause a capture condition 15 2 2 TIMER1 TIMER3 MODE SELECTION The timers that are to be used with the capture feature Timer1 and or Timer3 must be running in Timer mode or Synchronized Counter mode In Asynchronous Counter mode the capture operation will not work The timer to be used with each CCP module is selected in the T3CON register see Section 15 1 1 CCP Modules and Timer Resources 15 2 3 SOFTWARE INTERRUPT When the Capture mode is changed a false capture interrupt may be generated The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts The interrupt flag bit CCPxIF should also be cleared following any such change in operating mode 15 2 4 CCP PRESCALER There are four prescaler settings in Capture mode they are specified as part of the operating mode selected by the mode select bits CCPxM3 CCPxMO Whenever the CCP module is turned off or Capture mode is disabled the prescaler counter is cleared This means that any Reset will clear the prescaler counter Switching from one capture prescaler to another may generate an interrupt Also the prescaler counter will not be cleared therefore the first capture may be from a non zero prescaler Example 15 1 shows the recommended method for switching between capture prescalers This example also clears the prescaler counter and will not generate the false interrupt EXAMPLE 15 1 CHANGING B
345. access Wait state clocking is based on the data source clock If the SPP is configured to operate as a USB endpoint then wait states are based on the USB clock Likewise if the SPP is configured to operate from the micro controller then wait states are based on the instruction rate FOSC 4 The WS3 WS0 bits set the wait states used by the SPP with a range of no wait states to 30 wait states in multi ples of two The wait states are added symmetrically to all transactions with one half added following each of the two clock cycles normally required for the transaction Figure 18 3 and Figure 18 4 show signalling examples with 4 wait states added to each transaction 18 1 4 SPP PULL UPS The SPP data lines SPP lt 7 0 gt are equipped with internal pull ups for applications that may leave the port in a high impedance condition The pull ups are enabled using the control bit RDPU PORTE lt 7 gt DS39632B page 188 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 18 2 TIMING FOR MICROCONTROLLER WRITE ADDRESS WRITE DATA AND READ DATA NO WAIT STATES Fosc 4 AA a O EN O TENTE RS RENDUES O TJ AE a a NE T S s S a CK1SPP T za a Te T S LE a r SPP lt 7 0 gt Y ADDR XY Y DATA Y Y DATA X Write Address Write Data Read Data MOVWF SPPEPS MOVWF SPPDATA MOVF SPPDATA W FIGURE 18 3 TIMING FOR USB WRITE ADDRESS AND DATA 4 WAIT STATES
346. achieve a slow baud rate for a fast oscillator frequency Writing a new value to the SPBRGH SPBRG registers causes the BRG timer to be reset or cleared This ensures the BRG does not wait for a timer overflow before outputting the new baud rate 20 1 1 OPERATION IN POWER MANAGED MODES The device clock is used to generate the desired baud rate When one of the power managed modes is entered the new clock source may be operating at a different frequency This may require an adjustment to the value in the SPBRG register pair 20 1 2 SAMPLING The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin Configuration Bits BRG EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8 bit Asynchronous Fosc 64 n 1 0 0 a 8 bit Asynchronous F 1 1 0 1 0 16 bit Asynchronous eee lean ty 0 1 1 16 bit Asynchronous 1 0 x 8 bit Synchronous Fosc 4 n 1 1 1 x 16 bit Synchronous Legend x Don t care n value of SPBRGH SPBRG register pair EXAMPLE 20 1 CALCULATING BAUD RATE ERROR Solving for SPBRGH SPBRG x 16000000 9600 64 1 25 042 25 16000000 64 25 1 9615 Calculated Baud Rate 9615 9600 9600 0 16 For a device with Fosc of 16 MHz desired baud rate of 9600 Asynchronous mode 8 bit BRG Desired Baud Rate Fosc 64 ISPBRGH SPBRG 1 Fosc Desired Baud Rate
347. adable and writable A simplified block diagram of the TimerO module in 8 bit mode is shown in Figure 11 1 Figure 11 2 shows a simplified block diagram of the timer module in 16 bit mode TOCON TIMERO CONTROL REGISTER R W 1 R W 1 R W 1 R W 1 R W 1 TMROON TOBBIT TOCS TOSE PSA TOPS2 TOPS1 TOPSO bit 7 bit 7 TMROON Timer0 On Off Control bit 1 Enables Timer0 0 Stops Timer0 bit 6 TOBBIT TimerO 8 bit 16 bit Control bit bit 0 1 Timer0 is configured as an 8 bit timer counter 0 Timer0 is configured as a 16 bit timer counter bit 5 TOCS Timer0 Clock Source Select bit 1 Transition on TOCKI pin 0 Internal instruction cycle clock CLKO bit 4 TOSE Timer0 Source Edge Select bit 1 Increment on high to low transition on TOCKI pin 0 Increment on low to high transition on TOCKI pin bit 3 PSA Timer0 Prescaler Assignment bit 1 TimerO prescaler is NOT assigned Timer0 clock input bypasses prescaler 0 TimerO prescaler is assigned TimerO clock input comes from prescaler output bit 2 0 TOPS2 TOPSO Timer0 Prescaler Select bits 111 1 256 Prescale value 110 1 128 Prescale value 101 1 64 Prescale value 100 1 32 Prescale value 011 1 16 Prescale value 010 1 8 Prescale value 001 1 4 Prescale value 000 1 2 Prescale value Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is
348. ake up from Reset or Sleep mode TIMING TRANSITION FOR TWO SPEED START UP INTOSC TO HSPLL Q Q 8 Qi o O2 AZ A4 Q1 A2 AZ al RA A A S AN osor NL PUY 1 I TPU t 1 1 1 ara Ea CPU Clock j V Clock Transition PEPPER i a eee Be ee NIU mY AAA Program Ge ROY PC 2 PC 4 X FC 6 Counter Wake from Interrupt Event OSTS bit Set Note 1 Tost 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2004 Microchip Technology Inc Preliminary DS39632B page 293 PIC18F2455 2550 4455 4550 25 4 Fail Safe Clock Monitor The Fail Safe Clock Monitor FSCM allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block The FSCM function is enabled by setting the FCMEN configuration bit When FSCM is enabled the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure Clock monitoring shown in Figure 25 3 is accomplished by creating a sample clock signal which is the INTRC out put divided by 64 This allows ample time between FSCM sample clocks for a peripheral clock edge to occur The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch CM The CM is set on the
349. an OUT transfer and the actual number of bytes transmitted on an IN transfer Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 174 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 4 4 PING PONG BUFFERING An endpoint is defined to have a ping pong buffer when it has two sets of BD entries one set for an Even transfer and one set for an Odd transfer This allows the CPU to process one BD while the SIE is processing the other BD Double buffering BDs in this way allows for maximum throughput to from the USB The USB module supports three modes of operation No ping pong support Ping pong buffer support for OUT Endpoint 0 only Ping pong buffer support for all endpoints The ping pong buffer settings are configured using the PPB1 PPBO bits in the UCFG register The USB module keeps track of the ping pong pointer individually for each endpoint All pointers are initially reset to the Even BD when the module is enabled After the completion of a transaction UOWN cleared by the FIGURE 17 7 SIE the pointer is toggled to the Odd BD After the completion of the next transaction the pointer is toggled back to the Even BD and so on The Even Odd status of the last transaction is stored in the PPBI bit of the USTAT register The user can reset all ping p
350. an nasa any se asaaaa 182 Self Power Only 182 RAM astra 170 Memory Map 170 Speed 185 Status and Control 164 Transfer Types 184 UFRMH UFRML Registers 170 USB Memory 63 USBRAM de s hsna nn 63 USB See Universal Serial Bus DS39632B page 418 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 V Voltage Reference Specifications 371 W Watchdog Timer WDT a 279 291 Associated Registers 292 Control Register 291 During Oscillator Failure 294 Programming Considerations 291 WCOL gi a umay re sa 221 222 223 226 WCOL Status Flag oe eee 221 222 223 226 WWW On Line Support a 5 X KOR EW a Ca yana a Po ne ste test eine 341 XORWF ee Rene anu are arrete 2 arene 342 2004 Microchip Technology Inc Preliminary DS39632B page 419 PIC18F2455 2550 4455 4550 NOTES AEO E O r s r r F rr DS39632B page 420 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 ON LINE SUPPORT Microchip provides on line support on the Microchip World Wide Web site The web site is used by Microchip as a means to ma
351. and 2 bit latch match TMR2 concatenated with an internal 2 bit Q clock or two bits of the TMR2 prescaler the CCP1 pin is cleared The maximum PWM resolution bits for a given PWM frequency is given by the following equation EQUATION 16 3 PWM Resolution max x bits Note If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared 16 4 3 PWM OUTPUT CONFIGURATIONS The P1M1 P1MO bits in the CCP1CON register allow one of four configurations Single Output Half Bridge Output Full Bridge Output Forward mode Full Bridge Output Reverse mode The Single Output mode is the standard PWM mode discussed in Section 16 4 Enhanced PWM Mode The Half Bridge and Full Bridge Output modes are covered in detail in the sections that follow The general relationship of the outputs in all configurations is summarized in Figure 16 2 and Figure 16 3 TABLE 16 2 EXAMPLE PWM FREGUENCIES AND RESOLUTIONS AT 40 MHz PWM Freguency 2 44 kHz 9 77 kHz 39 06 kHz 156 25 kHz 312 50 kHz 416 67 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution bits 10 10 10 8 7 6 58 DS39632B page 152 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 16 2 PWM OUTPUT RELATIONSHIPS ACTIVE HIGH STATE 0 PR2 1 Duty GOPICON SIGNAL a Cycle gt lt 7 6 gt
352. anged to INTOSC must be cleared in software 0 System clock operating CMIF Comparator Interrupt Flag bit 1 Comparator input has changed must be cleared in software 0 Comparator input has not changed USBIF USB Interrupt Flag bit 1 USB has requested an interrupt must be cleared in software 0 No USB interrupt request EEIF Data EEPROM Flash Write Operation Interrupt Flag bit 1 The write operation is complete must be cleared in software 0 The write operation is not complete or has not been started BCLIF Bus Collision Interrupt Flag bit 1 Abus collision has occurred must be cleared in software 0 No bus collision occurred HLVDIF High Low Voltage Detect Interrupt Flag bit 1 Ahigh low voltage condition occurred must be cleared in software 0 No high low voltage event has occurred TMR3IF TMR3 Overflow Interrupt Flag bit 1 TMR3 register overflowed must be cleared in software 0 TMR3 register did not overflow CCP2IF CCP2 Interrupt Flag bit Capture mode 1 TMR1 or TMR3 register capture occurred must be cleared in software o No TMR1 or TMR3 register capture occurred Compare mode 1 TMR1 or TMR3 register compare match occurred must be cleared in software o No TMR1 or TMRS register compare match occurred PWM mode Unused in this mode Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR T Bit is set 0 Bit is cleare
353. are products Plus this line provides information on how customers can receive the most current upgrade kits The Hot Line Numbers are 1 800 755 2345 for U S and most of Canada and 1 480 792 7302 for the rest of the world 042003 2004 Microchip Technology Inc Preliminary DS39632B page 421 PIC18F2455 2550 4455 4550 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod uct If you wish to provide your comments on organization clarity subject matter and ways in which our documentation can better serve you please FAX your comments to the Technical Publications Manager at 480 792 4150 Please list the following information and use this outline to provide us with your comments about this document To Technical Publications Manager Total Pages Sent RE Reader Response From Name Company Address City State ZIP Country Telephone FAX Application optional Would you like a reply Y N Device PIC18F2455 2550 4455 4550 Literature Number DS39632B Questions 1 Whal are the best features of this document 2 How does this document meet your hardware and software development needs 3 Do you find the organization of this document easy to follow If not why 4 What additions to the document do you think would enhance the structure and subject 5 What deletions from
354. ast page When contacting a sales office please specify which device revision of silicon and data sheet include literature number you are using Customer Notification System Register on our web site at www microchip com to receive the most current information on all of our products 2004 Microchip Technology Inc Preliminary DS39632B page 5 PIC18F2455 2550 4455 4550 NOTES nr rr r rr hr c r Sy DS39632B page 6 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 1 0 DEVICE OVERVIEW This document contains device specific information for the following devices e PIC18F2455 e PIC18F2550 e PIC18LF2455 e PIC18LF2550 e PIC18F4455 e PIC18LF4455 e PIC18F4550 e PIC18LF4550 This family of devices offers the advantages of all PIC18 microcontrollers namely high computational performance at an economical price with the addition of high endurance Enhanced Flash program memory In addition to these features the PIC18F2455 2550 4455 4550 family introduces design enhancements that make these microcontrollers a log ical choice for many high performance power sensitive applications 1 1 New Core Features 1 1 1 nanoWatt TECHNOLOGY All of the devices in the PIC18F2455 2550 4455 4550 family incorporate a range of features that can signifi cantly reduce power consumption during operation Key items include
355. ators are those external sources not connected to the OSC1 or OSC2 pins These sources may continue to operate even after the controller is placed in a power managed mode PIC18F2455 2550 4455 4550 devices offer the Timer1 oscillator as a secondary oscillator This oscillator in all power managed modes is often the time base for functions such as a real time clock Most often a 32 768 kHz watch crystal is connected between the RCO T1OSO T13CKI and RC1 T1OSI UOE pins Like the XT and HS mode oscillator circuits loading capacitors are also connected from each pin to ground The Timer1 oscillator is discussed in greater detail in Section 12 3 Timer1 Oscillator In addition to being a primary clock source the internal oscillator block is available as a power managed mode clock source The INTRC source is also used as the clock source for several special features such as the WDT and Fail Safe Clock Monitor 2 4 1 OSCILLATOR CONTROL REGISTER The OSCCON register Register 2 2 controls several aspects of the device clock s operation both in full power operation and in power managed modes The System Clock Select bits SCS1 SCSO select the clock source The available clock sources are the primary clock defined by the FOSC3 FOSCO configu ration bits the secondary clock Timer1 oscillator and the internal oscillator block The clock source changes immediately after one or more of the bits is written to following a brief clock
356. ault If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example BTG PORTC 4 0 Before Instruction 0111 0101 75h After Instruction 0110 0101 65h PORTC PORTC BOV Branch if Overflow Syntax BOV n Operands 128 lt n lt 127 Operation if Overflow bit is 1 PC 2 2n gt PC Before Instruction Status Affected None Encoding 1110 0100 nnnn nnnn Description If the Overflow bit is 1 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump Q1 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 03 Q4 Decode Read literal Process No n Data operation Example HERE BOV Jump PC address HERE After Instruction If Overflow 1 PC address Jump If Overflow PC address HERE 2 2004 M
357. begins with the Program Counter PC incrementing in Q1 In the execution cycle the fetched instruction is latched into the Instruction Register IR in cycle Q1 This instruction is then decoded and executed during the Q2 Q3 and Q4 cycles Data memory is read during Q2 operand read and written during Q4 destination write FIGURE 5 3 CLOCK INSTRUCTION CYCLE Qi Q2 93 Q4 Qi AZ AZ Q AI Q2 AZ a4 OSC1 N LS _ NA FX Nas AN Qi TTX i or N 0200 7 N N Internal o M T TAN Gos Q4 PC PC K PC 2 Y PC 4 Execute INST PC 2 OSC2 CLKO O_o oo __ RC mode Fetch INST PC Execute INST PC Fetch INST PC 2 Execute INST PC 2 Fetch INST PC 4 EXAMPLE 5 3 INSTRUCTION PIPELINE FLOW Tcv0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5 1 MOVLW 55h Fetch 1 Execute 1 2 MOVWF PORTB Fetch 2 Execute 2 3 BRA SUB 1 4 BSF PORTA BIT3 Forced NOP 5 Instruction address SUB 1 Fetch 3 Execute 3 Note All instructions are single cycle except for any program branches These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed Fetch 4 Flush NOP Fetch SUB 1 Execute SUB 1 2004 Microchip Technology Inc Preliminary DS39632B page 61 PIC18F2455 2550 4455 4
358. bit 3 bit 2 bit 1 bit 0 RCON RESET CONTROL REGISTER RW 0 RW 10 U 0 R W 1 R 1 R 1 R W 0 RMW 0 IPEN SBOREN RI TO PD POR BOR bit 7 bit 0 IPEN Interrupt Priority Enable bit 1 Enable priority levels on interrupts 0 Disable priority levels on interrupts PIC16CXXX Compatibility mode SBOREN BOR Software Enable bi If BOREN1 BORENO 01 1 BOR is enabled 0 BOR is disabled If BOREN1 BORENO 00 10 or 11 Bit is disabled and read as o Unimplemented Read as RI RESET Instruction Flag bit 1 The RESET instruction was not executed set by firmware only 0 The RESET instruction was executed causing a device Reset must be set in software after a Brown out Reset occurs TO Watchdog Time out Flag bit 1 Set by power up CLRWDT instruction or SLEEP instruction 0 WDT time out occurred PD Power Down Detection Flag bit 1 Set by power up or by the CLRWDT instruction 0 Set by execution of the SLEEP instruction POR Power on Reset Status bit 2 1 A Power on Reset has not occurred set by firmware only 0 A Power on Reset occurred must be set in software after a Power on Reset occurs BOR Brown out Reset Status bit 1 A Brown out Reset has not occurred set by firmware only 0 A Brown out Reset occurred must be set in software after a Brown out Reset occurs Note 1 If SBOREN is enabled its Reset state is 1 otherw
359. bit and appropriate global interrupt enable bit are set the interrupt will vector immediately to address 000008h or 000018h depending on the priority bit setting Individual inter rupts can be disabled through their corresponding enable bits When the IPEN bit is cleared default state the interrupt priority feature is disabled and interrupts are compatible with PICmicro mid range devices In Compatibility mode the interrupt priority bits for each source have no effect INTCON lt 6 gt is the PEIE bit which enables disables all peripheral interrupt sources INTCON lt 7 gt is the GIE bit which enables disables all interrupt sources All interrupts branch to address 000008h in Compatibility mode When an interrupt is responded to the global interrupt enable bit is cleared to disable further interrupts If the IPEN bit is cleared this is the GIE bit If interrupt priority levels are used this will be either the GIEH or GIEL bit High priority interrupt sources can interrupt a low priority interrupt Low priority interrupts are not processed while high priority interrupts are in progress The return address is pushed onto the stack and the PC is loaded with the interrupt vector address 000008h or 000018h Once in the Interrupt Service Routine the source s of the interrupt can be deter mined by polling the interrupt flag bits The interrupt flag bits must be cleared in software before re enabling interrupts to avoid recursive inter
360. ble only on PIC18F4455 4550 devices in 44 pin TQFP packages Always leave this bit clear in all other devices Unimplemented Read as LVP Single Supply ICSP Enable bit 1 Single Supply ICSP enabled 0 Single Supply ICSP disabled Unimplemented Read as STVREN Stack Full Underflow Reset Enable bit 1 Stack full underflow will cause Reset 0 Stack full underflow will not cause Reset Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state DS39632B page 286 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 25 7 bit 7 4 bit 3 bit 2 bit 1 bit 0 REGISTER 25 8 bit 7 bit 6 bit 5 0 CONFIG5L CONFIGURATION REGISTER 5 LOW BYTE ADDRESS 300008h U 0 U 0 U 0 U 0 R C 1 R C 1 R C 1 R C 1 cp3 1 CP2 CP1 CPO bit 7 bit 0 Unimplemented Read as 0 CP3 Code Protection bit 1 Block 3 006000 007FFFh not code protected 0 Block 3 006000 007FFFh code protected Note 1 Unimplemented in PIC18FX455 devices maintain this bit set CP2 Code Protection bit 1 Block 2 004000 005FFFh not code protected 0 Block 2 004000 005FFFh code protected CP1 Code Protection bit 1 Block 1 002000 003FFFh not code protected 0 Block 1 002000 003FFFh code protected CPO Code Protection bit 1 Block 0 000800 001FFFh not code p
361. bled 160 PWM Direction Change PWM Direction Change at Near 100 Duty Cycle 157 PWM Output ie 146 Repeat Start Condition a 222 Reset Watchdog Timer WDT Oscillator Start up Timer OST and Power up Timer PWRT 379 Send Break Character Sequence 247 Slave Synchronization 1 199 Slow Rise Time MCLR Tied to Vpp VDD Rise gt TPWRT ss SPI Mode Master Mode SPI Mode Slave Mode with CKE 0 SPI Mode Slave Mode with CKE 1 SPP Write Address and Data for USB 4 Wait States 189 2004 Microchip Technology Inc Preliminary DS39632B page 417 PIC18F2455 2550 4455 4550 SPP Write Address Write and Read Data No Wait States oo cece Stop Condition Receive or Transmit Mode Streaming Parallel Port PIC18F4455 4550 Synchronous Reception Master Mode SREN Synchronous Transmission Synchronous Transmission Through TXENJ Time out Sequence on POR w PLL Enabled MCLR Tied to VDD Time out Sequence on Power up MCLR Not Tied to VDD Case 1 Time out Sequence on Power up MCLR Not T
362. bled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 105 PIC18F2455 2550 4455 4550 9 5 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts Due to the number of peripheral interrupt sources there are two Peripheral Interrupt Priority registers IPR1 and IPR2 Using the priority bits requires that the Interrupt Priority Enable IPEN bit be set REGISTER 9 8 IPR1 PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 SPPIP Streaming Parallel Port Read Write Interrupt Priority bit 1 1 High priority 0 Low priority Note 1 This bit is reserved on 28 pin devices always maintain this bit set bit 6 ADIP A D Converter Interrupt Priority bit 1 High priority 0 Low priority bit 5 RCIP EUSART Receive Interrupt Priority bit 1 High priority 0 Low priority bit 4 TXIP EUSART Transmit Interrupt Priority bit 1 High priority 0 Low priority bit 3 SSPIP Master Synchronous Serial Port Interrupt Priority bit 1 High priority 0 Low priority bit 2 CCP1IP CCP1 Interrupt Priority bit 1 High priority 0 Low priority bit 1 TMR2IP TMR2 to PR2 Match In
363. bles the timer and configures the prescaler and postscaler Timer2 can be shut off by clearing control bit TMR2ON T2CON lt 2 gt to minimize power consumption A simplified block diagram of the module is shown in Figure 13 1 REGISTER 13 1 U 0 R W 0 R W 0 13 1 In normal operation TMR2 is incremented from 00h on each clock Fosc 4 A 2 bit counter prescaler on the clock input gives direct input divide by 4 and divide by 16 prescale options These are selected by the prescaler control bits T2CKPS1 T2CKP SO T2CON lt 1 0 gt The value of TMR2 is compared to that of the period register PR2 on each clock cycle When the two values match the comparator generates a match signal as the timer output This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter postscaler see Section 13 2 Timer2 Interrupt The TMR2 and PR2 registers are both directly readable and writable The TMR2 register is cleared on any device Reset while the PR2 register initializes at FFh Both the prescaler and postscaler counters are cleared on the following events Timer2 Operation awrite to the TMR2 register awrite to the T2CON register any device Reset Power on Reset MCLR Reset Watchdog Timer Reset or Brown out Reset TMR2 is not cleared when T2CON is written T2CON TIMER2 CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPSO
364. buffer pointers not being reset bit 5 SEO Live Single Ended Zero Flag bit 1 Single ended zero active on the USB bus 0 No single ended zero detected bit 4 PKTDIS Packet Transfer Disable bit 1 SIE token and packet processing disabled automatically set when a SETUP token is received 0 SIE token and packet processing enabled bit 3 USBEN USB Module Enable bit 1 USB module and supporting circuitry enabled device attached o USB module and supporting circuitry disabled device detached bit 2 RESUME Resume Signaling Enable bit 1 Resume signaling activated 0 Resume signaling disabled bit 1 SUSPND Suspend USB bit 1 USB module and supporting circuitry in Power Conserve mode SIE clock inactive 0 USB module and supporting circuitry in normal operation SIE clock clocked at the configured rate bit 0 Unimplemented Read as o Legend C Clearable bit n Value at POR R Readable bit U Unimplemented bit read as 0 T Bit is set W Writable bit 0 Bit is cleared x Bit is unknown DS39632B page 164 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 The PPBRST bit UCON lt 6 gt controls the Reset status when Double Buffering mode ping pong buffering is used When the PPBRST bit is set all ping pong buffer pointers are set to the Even buffers PPBRST has to be cleared by firmware This bit is ignored in buffering mod
365. can also trigger a shutdown The auto shutdown feature can be disabled by not selecting any auto shutdown sources The auto shutdown sources to be used are selected using the ECCPAS2 ECCPASO bits bits lt 6 4 gt of the ECCP1AS register When a shutdown occurs the output pins are asynchronously placed in their shutdown states specified by the PSSAC1 PSSACO and PSSBD1 PSSBDO bits ECCP1AS3 ECCP1AS0 Each pin pair P1A P1C and P1B P1D may be set to drive high drive low or be tri stated not driving The ECCPASE bit ECCP1AS lt 7 gt is also set to hold the Enhanced PWM outputs in their shutdown states The ECCPASE bit is set by hardware when a shutdown event occurs If automatic restarts are not enabled the ECCPASE bit is cleared by firmware when the cause of the shutdown clears If automatic restarts are enabled the ECCPASE bit is automatically cleared when the cause of the auto shutdown has cleared If the ECCPASE bit is set when a PWM period begins the PWM outputs remain in their shutdown state for that entire PWM period When the ECCPASE bit is cleared the PWM outputs will return to normal operation at the beginning of the next PWM period Writing to the ECCPASE bit is disabled while a shutdown condition is active Note ECCP1DEL PWM CONFIGURATION REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PRSEN Ppce PpC5 PDC4 Ppc3s PDC2 PDC1 PDco bit
366. cation in the 100h Access RAM between 060h 00h and 0FFh This is the same as Bank 1 60h the SFRs or locations F60h to 2 through A OFFh Bank 15 of data pank Valid range memory FFh Locations below 60h are not Fogh ae Access RAM available in this addressing F60h Seated mode SERE FFFh Data Memory When a 0 and f lt 5Fh 000h The instruction executes in Bank 0 Indexed Literal Offset mode f 080h is interpreted as an offset to the address value in FSR2 The 1090 001001da ffffffff two are added together to obtain the address of the target J Pa J 5 mr gh a register for the instruction The Bank 14 address can be anywhere in FSR2H FSR2L the data memory space FOOh Note that in this mode the Bank 15 correct syntax is now Pee ere pat ADDWF k d SFRs where k is the same as f FFFh Data Memory BSR When a 1 all values of f 000h 00000000 The instruction executes in Banko y Direct mode also known as oe s Direct Long mode f is inter 100h preted as a location in one of the 16 banks of the data ak 001001da FFFFFFEE memory space The bank is C2 through YA designated by the Bank Select Bank 14 Register BSR The address can be in any implemented FOOh bank in the data memory Bank 15 space FOON ai SFRs FFFh Data Memory DS39632B page 76 Preliminary 2004 Microchip Technology Inc PIC 18F2455 2550 4455 4550 5 6 3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE
367. ch p 050 1 27 Overall Height A 093 099 104 2 36 2 50 2 64 Molded Package Thickness A2 088 091 094 2 24 2 31 2 39 Standoff Al 004 008 012 0 10 0 20 0 30 Overall Width E 394 407 420 10 01 10 34 10 67 Molded Package Width E1 288 295 299 7 32 7 49 7 59 Overall Length D 695 704 712 17 65 17 87 18 08 Chamfer Distance h 010 020 029 0 25 0 50 0 74 Foot Length L 016 033 050 0 41 0 84 1 27 Foot Angle Top 0 4 8 0 4 8 Lead Thickness c 009 011 013 0 23 0 28 0 33 Lead Width B 014 017 020 0 36 0 42 0 51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 Controlling Parameter Significant Characteristic Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MS 013 Drawing No C04 052 DS39632B page 400 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 40 Lead Plastic Dual In line P 600 mil Body PDIP p E 1 S D I 2 a n O 1 1 ss E m SS A2 I C 4 bp B1 eB B p Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p 100 2 54 Top to Seating Plane A 160 175 190 4 06 4 45 4 83 Molded Package Thickness A2 140 150 160 3 5
368. character now transmits in the preconfigured mode When the TXREG becomes empty as indicated by the TXIF the next data byte can be written to TXREG 20 2 6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways The first method forces configuration of the baud rate at a frequency of 9 13 the typical speed This allows for the Stop bit transition to be at the correct sampling location 13 bits for Break versus Start bit and eight data bits for typical data The second method uses the auto wake up feature described in Section 20 2 4 Auto Wake up on Sync Break Character By enabling this feature the EUSART will sample the next two transitions on RX DT cause an RCIF interrupt and receive the next data byte followed by another interrupt Note that following a Break character the user will typically want to enable the Auto Baud Rate Detect feature For both methods the user can set the ABD bit once the TXIF interrupt is observed FIGURE 20 10 SEND BREAK CHARACTER SEQUENCE i Write to TXREG Dummy Write 5 BRG Output y Shift Clock J TX pin TA Start Bit Bit 0 Bit 1 SE Bit11 _ Stop Bit gt Break M TXIF bit Transmit Buffer C Reg Empty Flag TRMT bit Transmit Shift Reg Empty Flag SENDB SENDB sampled here Auto Cleared A Transmit Shift Reg Em
369. cifications Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 273 PIC18F2455 2550 4455 4550 The module is enabled by setting the HLVDEN bit Each time that the HLVD module is enabled the circuitry requires some time to stabilize The IRVST bit is a read only bit and is used to indicate when the circuit is stable The module can only generate an interrupt after the circuit is stable and IRVST is set The VDIRMAG bit determines the overall operation of the module When VDIRMAG is cleared the module monitors for drops in VDD below a predetermined set point When the bit is set the module monitors for rises in VDD above the set point 24 1 Operation When the HLVD module is enabled a comparator uses an internally generated reference voltage as the set point The set point is compared with the trip point where each node in the resistor divider represents a trip point voltage The trip point voltage is the voltage level at which the device detects a high or low voltage FIGURE 24 1 event depending on the configuration of the module When the supply voltage is equal to the trip point the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module The comparator th
370. cillator Settings for USB 2004 Microchip Technology Inc Preliminary DS39632B page 23 PIC18F2455 2550 4455 4550 FIGURE 2 1 PIC18F2455 2550 4455 4550 CLOCK DIAGRAM PIC18F4550 PLLDIV USB Clock Source 12 lU 10 Zr USBDIV ones Sa S ae 10 4 MHz input only lise Primary Oscillator oscz gt lt Roi 3 ee gt 96 MHz 2 i 24 511 Z PLL A Sleep 3 OTO osci NET 2 50 FSEN 11 ooo HSPLL ECPLL USB I XTPLL ECPIO Peripheral a a tr 2 I CPUDIV 5 g wn a a ie 1 9 a n XTASLEC ECIO TE AU Bae PE CPU fo A I Primary i 5 Clock IDLEN ie i ERIS ot nd pd As O FOSC3 FOSCO Secondary Oscillator gt Peripherals 5 rioso H D T10S E Z ne nable T1OSI gt x Oscillator Co SESS S was S v OSCCON lt 6 4 gt Internal Oscillator OSCCON lt 6 4 gt 8 MHz ml oa n n l 4 MHz Internal 5 110 Clock Oscillator v 2 MHz 10 Control Block Q 1 MH 8 MHz 8 Z 100 X Ih Source amaz 500 kHz gt FOSC3 FOSCO OSCCON lt 1 0 gt INTOSC INTRO 8 250 kHz Source 125 kHz gt 00 Clock Source Option 31 kHz INTRC 31 KHZ ooo for other Modules 0 OSCTUNE lt 7 gt WDT PWRT FSCM
371. cillator block is running too slow to compensate increment the OSCTUNE register DS39632B page 28 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 2 3 Oscillator Settings for USB When the PIC18F4550 is used for USB connectivity it an EE OE O EE i iii a A 2004 Microchip Technology Inc Preliminary DS39632B page 29 PIC18F2455 2550 4455 4550 TABLE 2 3 OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION CONTINUED Input Oscillator PLL Division Clock Mode MCU Clock Division Microcontroller Freguency PLLDIV2 PLLDIVO FOSC3 FOSCO CPUDIV1 CPUDIVO Clock Freguency 20 MHz 5 100 HS EC ECIO None 00 20 MHz 2 01 10 MHz 3 10 6 67 MHz 4 11 5 MHz HSPLL ECPLL ECPIO 2 00 48 MHz 3 01 32 MHz 4 10 24 MHz 6 11 16 MHz 16 MHz 4 011 HS EC ECIO None 00 16 MHz 2 01 8 MHz 3 10 5 33 MHz 4 11 4 MHz HSPLL ECPLL ECPIO 2 00 48 MHz 3 01 32 MHz 4 10 24 MHz 6 11 16 MHz 12 MHz 3 010 HS EC ECIO None 00 12 MHz 2 01 6 MHz 3 10 4 MHz 4 11 3 MHz HSPLL ECPLL ECPIO 2 00 48 MHz 3 01 32 MHz 4 10 24 MHz 6 11 16 MHz 8 MHz 2 001 HS EC ECIO None 00 8 MHz 2 01 4 MHz 3 10 2 67 MHz 4 11 2 MHz HSPLL ECPLL ECPIO 2 00 48 MHz 3 01 32 MHz 4 10 24 MHz 6 11 16 MHz 4 MHz 1
372. cleared 25 2 1 CONTROL REGISTER Register 25 15 shows the WDTCON register This is a readable and writable register which contains a control bit that allows software to override the WDT enable configuration bit but only if the configuration bit has disabled the WDT WDT Counter INTRC Source gt 128 Change on IRCF bits Enable W OTO INTRC Control Wake up from g Power Managed Modes CEET gt gt Programmable Postscaler Reset t ADI 1 1 to 1 32 768 SLEEP All Device Resets WDTPS lt 4 1 gt 4 WDT 2004 Microchip Technology Inc Preliminary DS39632B page 291 PIC18F2455 2550 4455 4550 REGISTER 25 15 WDTCON WATCHDOG TIMER CONTROL REGISTER U 0 U 0 U 0 U 0 U 0 U 0 U 0 R W 0 SWDTEN bit 7 bit O bit 7 1 Unimplemented Read as 0 bitO SWDTEN Software Controlled Watchdog Timer Enable bit 1 Watchdog Timer is on 0 Watchdog Timer is off Note 1 This bit has no effect if the configuration bit WDTEN is enabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR TABLE 25 2 SUMMARY OF WATCHDOG TIMER REGISTERS Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page RCON IPEN SBOREN RI TO PD POR BOR 52 WDTCON SWDTEN 52
373. clock is being provided by the Timer1 oscillator or another source 12 3 2 LOW POWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration When the LPT1OSC configuration bit is set the Timer1 oscillator operates in a low power mode When LPT1OSC is not set Timer1 operates at a higher power level Power consumption for a particular mode is rela tively constant regardless of the device s operating mode The default Timer1 configuration is the higher power mode As the low power Timer1 mode tends to be more sensitive to interference high noise environments may cause some oscillator instability The low power option is therefore best suited for low noise applications where power conservation is an important design consideration 2004 Microchip Technology Inc Preliminary DS39632B page 131 PIC18F2455 2550 4455 4550 12 3 3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer oscillator circuit draws very little power during operation Due to the low power nature of the oscillator it may also be sensitive to rapidly changing signals in close proximity The oscillator circuit shown in Figure 12 3 should be located as close as possible to the microcontroller There should be no circuits passing within the oscillator circuit boundaries other than Vss or VDD If a high speed circuit must be located near the oscilla tor such as the CCP1 pin in
374. cond word the 4 MSbs are 1 s If this second word is executed as an instruction by itself it will execute as a NOP All single word instructions are executed in a single instruction cycle unless a conditional test is true or the program counter is changed as a result of the instruc tion In these cases the execution takes two instruction cycles with the additional instruction cycle s executed as a NOP The double word instructions execute in two instruction cycles One instruction cycle consists of four oscillator periods Thus for an oscillator frequency of 4 MHz the normal instruction execution time is 1 us If a conditional test is true or the program counter is changed as a result of an instruction the instruction execution time is 2 us Two word branch instructions if true would take 3 us Figure 26 1 shows the general formats that the instruc tions can have All examples use the convention nnh to represent a hexadecimal number The Instruction Set Summary shown in Table 26 2 lists the standard instructions recognized by the Microchip MPASM Assembler Section 26 1 1 Standard Instruction Set provides a description of each instruction 2004 Microchip Technology Inc Preliminary DS39632B page 301 PIC18F2455 2550 4455 4550 TABLE 26 1 OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a 0 RAM location in Access RAM BSR register is ignored a 1
375. cted If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 2 Note 3 cycles if skip and followed by a 2 word instruction Q Cycle Activity 01 Q2 Q3 Q4 Decode Read Process No register f Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE BTFSS FLAG 1 0 FALSE TRUE Before Instruction PC address HERE After Instruction If FLAG lt 1 gt PC address FALSE If FLAG lt 1 gt PC address TRUE DS39632B page 314 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 BTG Bit Toggle f Syntax BTG f b a Operands 0 lt f lt 255 0 lt b lt 7 a e 0 1 Operation lt b gt gt f lt b gt Status Affected None Encoding 0111 bbba ffff fff Description Bit b in data memory location f is inverted If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank def
376. ction Q1 Q2 Q3 Q4 Decode Read Process No register f Data operation If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE CPFSLT REG 1 NLESS LESS Before Instruction PC W After Instruction Preliminary Address HERE Address LESS I IN I A Address NLESS DS39632B page 319 PIC18F2455 2550 4455 4550 DAW Decimal Adjust W Register Syntax DAW Operands None Operation If W lt 3 0 gt gt 9 or DC 1 then W lt 3 0 gt 6 W lt 3 0 gt else W lt 3 0 gt gt W lt 3 0 gt If W lt 7 4 gt DC gt 9 or C 1 then W lt 7 4 gt 6 DC gt W lt 7 4 gt else W lt 7 4 gt DC gt W lt 7 4 gt Status Affected C Encoding 0000 0000 0000 0111 Description DAW adjusts the eight bit value in W resulting from the earlier addition of two variables each in packed BCD format and produces a correct packed BCD result Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register W Data w Example 1 DAW Before Instruction w Ash C 0 DC 0 After Instruction w 05h C 1 DC 0 Example 2 Before Instruction W CEh C 0 DC 0 After Instruction w 34h C ll DC 0
377. ction FSR2 80h Contents of 85h 33h Contents of 86h 1th After Instruction FSR2 80h Contents of 85h 33h Contents of 86h 33h DS39632B page 346 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 SUBFSR Subtract Literal from FSR Syntax SUBFSR f k Operands 0 lt k lt 63 fe 0 1 2 Operation FSRf k FSRf Status Affected None Encoding 1110 1001 ffkk kkkk Description The 6 bit literal k is subtracted from the contents of the FSR specified by f Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example SUBFSR 2 23h Before Instruction FSR2 O83FFh After Instruction FSR2 03DCh SUBULNK Subtract Literal from FSR2 and Return Syntax SUBULNK k Operands 0 lt k lt 63 Operation FSR2 k gt FSR2 TOS gt PC Status Affected None Encoding 1110 1001 11kk kkkk Description The 6 bit literal K is subtracted from the contents of the FSR2 A RETURN is then executed by loading the PC with the TOS The instruction takes two cycles to execute a NOP is performed during the second cycle This may be thought of as a special case of the SUBFSR instruction where f 3 binary 11 it operates only on FSR2 Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination No
378. ctive operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or Vss MCLR VDD WDT enabled disabled as specified Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications DS39632B page 364 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 28 2 DC Characteristics Power Down and Supply Current PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Continued PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial fi Device Typ Max Units Conditions Supply Current Ino PIC18LFX455 X550 14 40 uA 40 C 15 40 uA 25 C VDD 2 0V 16 40 uA 85 C PIC18LFX455 X550 40 74 pA 40 C Fosc 32 kHz 3 35 70 uA 25 C VDD 3 0V SEC RUN mode 31 67 uA 85 C Timer1 as clock All devices 99 150 uA 40 C 81 150 uA 25 C VDD 5 0V 75 15
379. cusses the considerations for converting from previous versions of a device to the ones listed in this data sheet Typically these changes are due to the differences in the process technology used An example of this type of conversion is from a PIC16C74A to a PIC16C74B Not Applicable APPENDIX D MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device i e PIC16C5X to an Enhanced MCU device i e PIC18FXXX The following are the list of modifications over the PIC16C5X microcontroller family Not Currently Available DS39632B page 406 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 APPENDIX E MIGRATION FROM MID RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid range MCU devices i e PIC16CXXX and the enhanced devices i e PIC18FXXX is provided in AN716 Migrating Designs from PIC16C74A 74B to PIC18C442 The changes discussed while device specific are generally applicable to all mid range to enhanced device migrations This Application Note is available as Literature Number DS00716 APPENDIX F MIGRATION FROM HIGH END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high end MCU devices i e PIC17CXXX and the enhanced devices i e PIC18FXXX is provided in AN726 PIC17CXXX to PIC18CXXX Migration This Application Note is available
380. d EEDATA cannot be modified The WR bit will be inhibited from being set unless the WREN bit is set The WREN bit must be set on a previous instruc tion Both WR and WREN cannot be set with the same instruction At the completion of the write cycle the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit EEIF is set The user may either enable this interrupt or poll this bit EEIF must be cleared by software 7 4 Write Verify Depending on the application good programming practice may dictate that the value written to the memory should be verified against the original value This should be used in applications where excessive writes can stress bits near the specification limit EXAMPLE 7 1 DATA EEPROM READ MOVLW DATA EE ADDR MOVWF EEADR Lower bits of Data Memory Address to read BCF EECON1 EEPGD Point to DATA memory BCF EECON1 CFGS Access EEPROM BSF EECON1 RD EEPROM Read MOVF EEDATA W W EEDATA EXAMPLE 7 2 DATA EEPROM WRITE MOVLW DATA EE_ADDR MOVWF EEADR Lower bits of Data Memory Address to write MOVLW DATA EE DATA z MOVWF EEDATA Data Memory Value to write BCF EECON1 EPGD Point to DATA memory BCF EECON1 CFGS Access EEPROM BSF EECON1 WREN Enable writes BCF INTCON GIE Disable Interrupts MOVLW SSH 5 Required MOVWF EECON2 Write 55h Sequence MOVLW OAAh MOVWF EECON2 Write OAAh BSF EECON1 WR Set WR bit to begin write BSF INTCON GIE Enable Interrupts U
381. d Literal Offset _ 75 Indirect a a sas anus sa nine 72 Inh rent and Literal n u ha 1 72 Data EEPROM Code Protection unu aan ua Sh a Data EEPROM Memory s Associated Registers 93 EECON1 and EECON2 Registers 89 Operation During Code Protect 92 Protection Against Spurious Write Using 92 Write Verify 91 MV FILING A STA 91 DS39632B page 410 Preliminary 2004 Microchip Technology lnc PIC18F2455 2550 4455 4550 D ta Memiet au u u aD haku aaa ana 63 Access Bank sise 65 and the Extended Instruction Set Bank Select Register BSR General Purpose Registers Map for PIC18F2455 2550 4455 4550 DEVICES sin a NA 64 DC and AC Characteristics Graphs and Tables ba DC Characteristics 368 Power Down and Supply Current Supply Voltage DCFSNZ 321 a 320 BaS TAE N 321 Dedicated ICD ICSP Port 299 Demonstration Boards PICDEM 1 PICDEM 17 wed PIG DEM BRO sluhu asi lord 355 PIC DEM 2 PIUS uu s sn ah 354 PICDEM 3 PICDEM 4 PICDEM LIN PICDEM USB PA PICDEM net Internet Ethernet 354 Development Support a
382. d bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown DS39632B page 108 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 9 7 INTn Pin Interrupts External interrupts on the RBO AN12 INTO FLTO SDI SDA RB1 AN10 INT1 SCK SCL and RB2 AN8 INT2 VMO pins are edge triggered If the corresponding INTEDGx bit in the INTCON2 register is set 1 the interrupt is triggered by a rising edge if the bit is clear the trigger is on the falling edge When a valid edge appears on the RBx INTx pin the corresponding flag bit INTXF is set This interrupt can be disabled by clearing the corresponding enable bit INTXE Flag bit INTxF must be cleared in software in the Interrupt Service Routine before re enabling the interrupt All external interrupts INTO INT1 and INT2 can wake up the processor from the power managed modes if bit INTXE was set prior to going into the power managed modes If the Global Interrupt Enable bit GIE is set the processor will branch to the interrupt vector following wake up Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits INT1IP INTCON3 lt 6 gt and INT2IP INTCON3 lt 7 gt There is no priority bit associated with INTO It is always a high priority interrupt source 9 8 TMRO Interrupt In 8 bit mode which is the default an overflow in the TMRO register FFh
383. d for isochronous transfers 17 3 USB RAM USB data moves between the microcontroller core and the SIE through a memory space known as the USB RAM This is a special dual port memory that is mapped into the normal data memory space in Banks 4 through 7 400h to 7FFh for a total of 1 Kbyte Figure 17 5 Bank 4 400h through 4FFh is used specifically for endpoint buffer control while Banks 5 through 7 are available for USB data Depending on the type of buffering being used all but 8 bytes of Bank 4 may also be available for use as USB buffer space Although USB RAM is available to the microcontroller as data memory the sections that are being accessed by the SIE should not be accessed by the microcontroller A semaphore mechanism is used to determine the access to a particular buffer at any given time This is discussed in Section 17 4 1 1 Buffer Ownership FIGURE 17 5 IMPLEMENTATION OF USB RAM IN DATA MEMORY SPACE i 000h Banks 0 J User Data to3 L 3FFh Buffer Descriptors 400h USB Data or User Data 4FFh 500h Banks 4 J USB Data or to7 User Data USB RAM L 7FFh f 800h Banks 8 lt Unused to 14 ie FOOh Bank15 F60h SFRs FFFh DS39632B page 170 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 4 Buffer Descriptors and the Buffer Descriptor Table The registers in Bank 4 are used specifically for end point buffer control in a st
384. d from each other in six ways 1 Flash program memory 24 Kbytes for PIC18FX455 devices 32 Kbytes for PIC18FX550 2 A D channels 10 for 28 pin devices 13 for 40 44 pin devices 3 VO ports 3 bidirectional ports and 1 input only port on 28 pin devices 5 bidirectional ports on 40 44 pin devices 4 CCP and Enhanced CCP implementation 28 pin devices have 2 standard CCP modules 40 44 pin devices have one standard CCP module and one ECCP module 5 Streaming Parallel Port present only on 40 44 pin devices All other features for devices in this family are identical These are summarized in Table 1 1 The pinouts for all devices are listed in Table 1 2 and Table 1 3 Like all Microchip PIC18 devices members of the PIC18F2455 2550 4455 4550 family are available as both standard and low voltage devices Standard devices with Enhanced Flash memory designated with an F in the part number such as PIC18F2550 accommodate an operating VDD range of 4 2V to 5 5V Low voltage parts designated by LF such as PIC18LF2550 function over an extended VDD range of 2 0V to 5 5V DS39632B page 8 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 1 1 DEVICE FEATURES Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550 Operating Freguency DC 48 MHz DC 48 MHz DC 48 MHz DC 48 MHz Program Memory Bytes 24576 32768 24576 32768
385. d instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example NEGF REG 1 Before Instruction REG 0011 1010 SAh After Instruction REG 1100 0110 C6h NOP No Operation Syntax NOP Operands None Operation No operation Status Affected None Encoding 0000 0000 0000 0000 1111 XXXX XXXX XXXX Description No operation Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No No No operation operation operation Example None 2004 Microchip Technology Inc Preliminary DS39632B page 329 PIC18F2455 2550 4455 4550 POP Pop Top of Return Stack Syntax POP Operands None Operation TOS bit bucket Status Affected None Encoding 0000 0000 0000 0110 Description The TOS value is pulled off the return stack and is discarded The TOS value then becomes the previous value that was pushed onto the return stack This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode No Po
386. d to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words 1 Cycles 1 2 Q Cycle Activity If Jump 01 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BC 5 Before Instruction PC address HERE After Instruction If Carry 1 PC address HERE 12 If Carry PC address HERE 2 2004 Microchip Technology Inc Preliminary DS39632B page 309 PIC18F2455 2550 4455 4550 BCF Bit Clear f Syntax BCF f b a Operands 0 lt f lt 255 O0 lt b lt 7 ae 0 1 Operation 0 f lt b gt Status Affected None Encoding 1001 bbba EEFT ffff Description Bit b in register f is cleared If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data register f Example BCF FLAG REG
387. d x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 103 PIC18F2455 2550 4455 4550 9 4 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts Due to the number of periph eral interrupt sources there are two Peripheral Interrupt Enable registers PIE1 and PIE2 When IPEN o the PEIE bit must be set to enable any of these peripheral interrupts REGISTER 9 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER 1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 SPPIEU ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE bit 7 SPPIE Streaming Parallel Port Read Write Interrupt Enable bit 1 1 Enables the SPP read write interrupt o Disables the SPP read write interrupt Note 1 This bit is reserved on 28 pin devices always maintain this bit clear ADIE A D Converter Interrupt Enable bit 1 Enables the A D interrupt 0 Disables the A D interrupt RCIE EUSART Receive Interrupt Enable bit 1 Enables the EUSART receive interrupt o Disables the EUSART receive interrupt TXIE EUSART Transmit Interrupt Enable bit 1 Enables the EUSART transmit interrupt 0 Disables the EUSART transmit interrupt SSPIE Master Synchronous Serial Port Interrupt Enable bit 1 Enables the MSSP interrupt 0 Disables the MSSP interrupt CCP1IE CCP1 Interr
388. derived from the A D s internal RC oscillator The output of the sample and hold is the input into the converter which generates the result via successive approximation A device Reset forces all registers to their Reset state This forces the A D module to be turned off and any conversion in progress is aborted Each port pin associated with the A D converter can be configured as an analog input or as a digital I O The ADRESH and ADRESL registers contain the result of the A D conversion When the A D conversion is com plete the result is loaded into the ADRESH ADRESL register pair the GO DONE bit ADCONO register is cleared and A D Interrupt Flag bit ADIF is set The block diagram of the A D module is shown in Figure 21 1 FIGURE 21 1 A D BLOCK DIAGRAM CHS3 CHSO ike oe Rod le tran t 1100 ss SG DX ante ee ye X AN11 1010 pag NS gt AN10 1001 SN x ano 1000 o Ni FT AN8 0111 1 a NS X AN7 1 0110 SN X ANG o V tt X AN5 1 I 0100 VAIN i x X ANG 10 bit Input Voltage D L lt AN3 Converter 0010 o A X AN2 i 0001 r LV X AN see 0000 ee ee o o DX ano So do RO I JC ia S A s Se sea VREF XL Reference o 0 5 Vol o oltage VREF tt ox Vss Note 1 Channels AN5 through AN7 are not available on 28 pin devices 2 I O pins have diode protection to VDD and Vss DS39
389. detection of the oscillator s failure to start at all following these events This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start Even so no oscillator failure interrupt will be flagged As noted in Section 25 3 1 Special Considerations for Using Two Speed Start up it is also possible to select another clock configuration and enter an alternate power managed mode while waiting for the primary clock to become stable When the new power managed mode is selected the primary clock is disabled 2004 Microchip Technology Inc Preliminary DS39632B page 295 PIC18F2455 2550 4455 4550 25 5 Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PICmicro devices The user program memory is divided into five blocks One of these is a boot block of 2 Kbytes The remainder of the memory is divided into four blocks on binary boundaries Each of the five blocks has three code protection bits associated with them They are Code Protect bit CPn e Write Protect bit WRTn External Block Table Read bit EBTRn Figure 25 5 shows the program memory organization for 24 and 32 Kbyte devices and the specific code pro tection bit associated with each block The actual locations of the bits are summarized in Table 25 3
390. device is limited to 500 LA of current This is the complete current drawn by the PICmicro device and its sup porting circuitry Care should be taken to assure minimum current draw when the device enters Suspend mode 17 2 2 USBCONFIGURATION REGISTER UCFG Prior to communicating over USB the module s associated internal and or external hardware must be configured Most of the configuration is performed with the UCFG register Register 17 2 The separate USB voltage regulator see Section 17 2 2 8 Internal Regulator is controlled through the configuration registers The UFCG register contains most of the bits that control the system level behavior of the USB module These include Bus speed full speed versus low speed On chip pull up resistor enable On chip transceiver enable Ping pong buffer usage The UCFG register also contains two bits which aid in module testing debugging and USB certifications These bits control output enable state monitoring and eye pattern generation Note The USB speed transceiver and pull up should only be configured during the mod ule setup phase It is not recommended to switch these settings while the module is enabled 17 2 2 1 Internal Transceiver The USB peripheral has a built in USB 2 0 full speed and low speed compliant transceiver internally con nected to the SIE This feature is useful for low cost single chip applications The UTRDIS bit
391. disabled bit 4 1 Idle detect interrupt enabled 0 Idle detect interrupt disabled bit 3 1 Transaction interrupt enabled 0 Transaction interrupt disabled bit 2 STALLIE STALL Handshake Interrupt Enable bit IDLEIE Idle Detect Interrupt Enable bit TRNIE Transaction Complete Interrupt Enable bit ACTVIE Bus Activity Detect Interrupt Enable bit 1 Bus activity detect interrupt enabled 0 Bus activity detect interrupt disabled bit 1 UERRIE USB Error Interrupt Enable bit 1 USB error interrupt enabled 0 USB error interrupt disabled bit 0 1 USB Reset interrupt enabled 0 USB Reset interrupt disabled URSTIE USB Reset Interrupt Enable bit Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 179 PIC18F2455 2550 4455 4550 17 5 3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is REGISTER UEIR detected Thus the interrupt will typically not The USB Error Interrupt Status register Register 17 9 correspond with the ene ola token seing processed contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE it must within the USB peripheral Each of these sources is be cleared by software by writing a 0 controlled by a corresponding interrupt enab
392. ditional time delay BOR and the Power on Timer PWRT are independently configured Enabling BOR Reset does not automatically enable the PWRT 4 4 1 SOFTWARE ENABLED BOR When BOREN1 BORENO 01 the BOR can be enabled or disabled by the user in software This is done with the control bit SBOREN RCON lt 6 gt Setting SBOREN enables the BOR to function as previously described Clearing SBOREN disables the BOR entirely The SBOREN bit operates only in this mode otherwise it is read as 0 Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change BOR configuration It also allows the user to tailor device power consumption in software by elimi nating the incremental current that the BOR consumes While the BOR current is typically very small it may have some impact in low power applications Note Even when BOR is under software control the BOR Reset voltage level is still set by the BORV1 BORVO configuration bits It cannot be changed in software 4 4 2 DETECTING BOR When BOR is enabled the BOR bit always resets to 0 on any BOR or POR event This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone A more reliable method is to simultaneously check the state of both POR and BOR This assumes that the POR bit is reset to 1 in software
393. durance A byte write automatically erases the location and writes the new data erase before write The write time is controlled by an on chip timer it will vary with voltage and temperature as well as from chip to chip Please refer to parameter D122 Table 28 1 in Section 28 0 Electrical Characteristics for exact limits 7 1 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers EECON1 and EECON2 These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM The EECON1 register Register 7 1 is the control register for data and program memory access Control bit EEPGD determines if the access will be to program or data EEPROM memory When clear operations will access the data EEPROM memory When set program memory is accessed Control bit CFGS determines if the access will be to the configuration registers or to program memory data EEPROM memory When set subseguent operations access configuration registers When CFGS is clear the EEPGD bit selects either program Flash or data EEPROM memory The WREN bit when set will allow a write operation On power up the WREN bit is clear The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete Note During normal operation the WRERR is read as 1 This can indicate that a writ
394. e the WCOL is set and the contents of the buffer are unchanged the write doesn t occur WCOL must be cleared in software 19 4 10 3 ACKSTAT Status Flag In Transmit mode the ACKSTAT bit SSPCON2 lt 6 gt is cleared when the slave has sent an Acknowledge ACK 0 and is set when the slave does not Acknowl edge ACK 1 Aslave sends an Acknowledge when it has recognized its address including a general call or when the slave has properly received its data 19 4 11 12C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit RCEN SSPCON2 lt 3 gt Note The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded The Baud Rate Generator begins counting and on each rollover the state of the SCL pin changes high to low low to high and data is shifted into the SSPSR After the falling edge of the eighth clock the receive enable flag is automatically cleared the contents of the SSPSR are loaded into the SSPBUF the BF flag bit is set the SSPIF flag bit is set and the Baud Rate Gener ator is suspended from counting holding SCL low The MSSP is now in Idle state awaiting the next command When the buffer is read by the CPU the BF flag bit is automatically cleared The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge sequence enable bit ACKEN SSPCON2 lt 4 gt 19 4 11 1 BF Status F
395. e operation was prematurely terminated by a Reset or a write operation was attempted improperly The WR control bit initiates write operations The bit cannot be cleared only set in software it is cleared in hardware at the completion of the write operation Note The EEIF interrupt flag bit PIR2 lt 4 gt is set when the write is complete It must be cleared in software Control bits RD and WR start read and erase write operations respectively These bits are set by firmware and cleared by hardware at the completion of the operation The RD bit cannot be set when accessing program memory EEPGD 1 Program memory is read using table read instructions See Section 6 1 Table Reads and Table Writes regarding table reads The EECON2 register is not a physical register It is used exclusively in the memory write and erase sequences Reading EECON2 will read all o s 2004 Microchip Technology Inc Preliminary DS39632B page 89 PIC18F2455 2550 4455 4550 REGISTER 7 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EECON1 DATA EEPROM CONTROL REGISTER 1 R W x R W x U 0 R W 0 R W x R W 0 R S 0 R S 0 EEPGD CFGS FREE WRERR WREN WR RD bit 7 bit 0 EEPGD Flash Program or Data EEPROM Memory Select bit 1 Access Flash program memory 0 Access data EEPROM memory CFGS Flash Program Data EEPROM or Configuration Select bit 1 Access configuration reg
396. e Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented read as 0 Shaded cells are not used for synchronous slave reception Note 1 Reserved in 28 pin devices always maintain these bits clear DS39632B page 252 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 21 0 10 BITANALOG TO DIGITAL CONVERTER A D MODULE The Analog to Digital A D converter module has 10 inputs for the 28 pin devices and 13 for the 40 44 pin devices This module allows conversion of an analog input signal to a corresponding 10 bit digital number The module has five registers A D Result High Register ADRESH e A D Result Low Register ADRESL e A D Control Register 0 ADCONO e A D Control Register 1 ADCON1 e A D Control Register 2 ADCON2 The ADCONO register shown in Register 21 1 controls the operation of the A D module The ADCONI register shown in Register 21 2 configures the functions of the port pins The ADCON2 register shown in Register 21 3 configures the A D clock source programmed acquisition time and justification REGISTER 21 1 ADCONO A D CONTROL REGISTER 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CHS3 CHS2 CHS1 CHSO GO DONE ADON bit 7 bit 0
397. e bank Bank 3 GPR used by the instruction FFh 3FFh a 00h 400h A Bank 4 GPRO FFh 4FFh 0101 00h 500h Bank 5 GPR FFh 5FFh 0110 00h 600h Bank 6 GPRM FFh 6FFh Access Bank 0111 00h 700h 00h Bank 7 GPR Access RAM Low 5Fh FFh A Access RAM High 60h 00h SFRs FFh 1000 dite ja Unused to Read as 00h 1110 Bank 14 FFh EFFh ej 00h Unused EE Bank 15 F60h FFh FFFh Note 1 These banks also serve as RAM buffer for USB operation See Section 5 3 1 USB RAM for more information DS39632B page 64 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 5 6 USE OF THE BANK SELECT REGISTER DIRECT ADDRESSING 1 Data Memory From Opcode 7 nee 0 00h h e ololololo olil1 Bank 0 FEh 111 1 1 1 1 1 1 100h Bank 1 00h Bank Selec Z FFh 200h 00h Bank 2 300h FFh lt 7 00h Bank 3 through A A Bank13 A FFh E00h 00h Bank 14 FEh FOOh 00h Bank 15 FFFh FFh Note 1 The Access RAM bit of the instruction can be used to force an override of the selected bank BSR lt 3 0 gt to the registers of the Access Bank 2 The MOVFF instruction embeds the entire 12 bit address in the instruction 5 3 3 ACCESS BANK While the use of the BSR with an embedded 8 bit address allows users to address the entire range of data memory it also means that the user must always
398. e corresponding UEPn control regis ter is set and a STALL interrupt is generated when a STALL is issued to the host The UOWN bit remains set and the BDs are not changed unless a SETUP token is received In this case the STALL condition is cleared and the ownership of the BD is returned to the microcontroller core The BD9 BD8 bits BDnSTAT lt 1 0 gt store the two most significant digits of the SIE byte count the lower 8 digits are stored in the corresponding BDnCNT register See Section 17 4 2 BD Byte Count for more information TABLE 17 3 EFFECT OF DTSEN BIT ON ODD EVEN DATAO DATA 1 PACKET RECEPTION OUT Packet BDnSTAT Settings Device Response after Receiving Packet from Host DTSEN DTS Handshake UOWN TRNIF BDNSTAT and USTAT Status DATAO 1 0 ACK 0 1 Updated DATA1 1 0 ACK 1 0 Not Updated DATAO 1 1 ACK 0 1 Updated DATA1 1 1 ACK 1 0 Not Updated Either 0 x ACK 0 1 Updated Either with error x x NAK 1 0 Not Updated Legend x don t care DS39632B page 172 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 17 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 0 BDnSTAT BUFFER DESCRIPTOR n STATUS REGISTER BDOSTAT THROUGH BD63STAT CPU MODE DATA IS WRITTEN TO THE SIDE R W x R W x R W x R W x R W x R W x R W x R W x UOWN DTS KEN INCDIS DTSEN BSTALL BC9 BC8 bit 7 bit 0 UOWN USB Own bit 0
399. e device is in when the time out occurs If the device is not executing code all Idle modes and Sleep mode the time out will result in an exit from the power managed mode see Section 3 2 Run Modes and Section 3 3 Sleep Mode If the device is executing code all Run modes the time out will result in a WDT Reset see Section 25 2 Watchdog Timer WDT The WDT timer and postscaler are cleared by execut ing a SLEEP Or CLRWDT instruction the loss of a currently selected clock source if the Fail Safe Clock Monitor is enabled and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source 3 5 3 EXIT BY RESET Normally the device is held in Reset by the Oscillator Start up Timer OST until the primary clock becomes ready At that time the OSTS bit is set and the device begins executing code If the internal oscillator block is the new clock source the IOFS bit is set instead The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake up and the type of oscillator if the new clock source is the primary clock Exit delays are summarized in Table 3 2 Code execution can begin before the primary clock becomes ready If either the Two Speed Start up see Section 25 3 Two Speed Start up or Fail Safe Clock Monitor see Section 25 4 Fail Safe Clock Monitor is enabled the device may begin execut
400. e interrupt may occur FIGURE 22 1 COMPARATOR I O OPERATING MODES Comparators Reset Comparators Off POR Default Value CM2 CMO 000 CM2 CMO 111 RAO ANO VN gt RA3 AN3 A Vivx aa OH Redd as VREF RA1 AN1 V RA2 AN2 A VIN s Off Read as 0 VREF CVREF RAO ANO D VIN RAS AN3 D VINE sq Off Read as o RAI1 AN1 _D_ VIN RA2 AN2 D VIN Off Read as o VREF CVREF L Two Independent Comparators CM2 CM0 010 RAO ANO A VN gt RAS AN3 _A___VIN C1OUT VREF RA1 AN1 RAZ AN2 A Vi C2 C20UT VREF CVREF Two Independent Comparators with Outputs CM2 CMO 011 RAO ANO VW RAS ANS A Vin C1OUT VREF RA4 TOCKI C1OUT RCV RA1 AN1 A MN RA2 AN2 A VIN C2OUT VREF CVREF RAS5 AN4 SS HLVDIN C2OUT Two Common Reference Comparators CM2 CMO 100 RAO ANO VIN 1 T RA3 AN3 i G C10U VREF RA1 AN1 2 MINS RA2 AN2 _D LVIN VREF CVREF C2 C2OUT Two Common Reference Comparators with Outputs CM2 CM0 101 RAO ANO 9 RA3 AN3 A VM VREF RA4 TOCKI C10UT RCV RA1 AN1 A VIN RA2 AN2 D VIN C2OUT VREF CVREF C1OUT RA5 AN4 SS HLVDIN C2OUT One Independent Comparator with Output CM2 CMO 001 RAO ANO VIN RA3 AN3 A VIN g C1 C1OUT VREF RA4 TOCKI C1OUT RCV HAMAN gt VIE PR C2 Off Read as 0
401. e primary oscillator block with no postscale CPUDIV1 CPUDIVO System Clock Postscaler Selection bits For XT HS EC and ECIO Oscillator modes 11 Primary oscillator divided by 4 to derive system clock 10 Primary oscillator divided by 3 to derive system clock 01 Primary oscillator divided by 2 to derive system clock 00 Primary oscillator used directly for system clock no postscaler For XTPLL HSPLL ECPLL and ECPIO Oscillator modes 11 96 MHz PLL divided by 6 to derive system clock 10 96 MHz PLL divided by 4 to derive system clock 01 96 MHz PLL divided by 3 to derive system clock 00 96 MHz PLL divided by 2 to derive system clock PLLDIV2 PLLDIVO PLL Prescaler Selection bits 111 Divide by 12 48 MHz oscillator input 110 Divide by 10 40 MHz oscillator input 101 Divide by 6 24 MHz oscillator input 100 Divide by 5 20 MHz oscillator input 011 Divide by 4 16 MHz oscillator input 010 Divide by 3 12 MHz oscillator input 001 Divide by 2 8 MHz oscillator input 000 No prescale 4 MHz oscillator input drives PLL directly Ne eR Legend R Readable bit P Programmable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 281 PIC18F2455 2550 4455 4550 REGISTER 25 2 bit 7 bit 6 bit 5 4 bit 3 0 CONFIG1H CONFIGURATION REGISTER 1
402. e reguired code is given in Example 6 3 Note Before setting the WR bit the Table Pointer address needs to be within the intended address range of the 32 bytes in the holding register 2004 Microchip Technology Inc Preliminary DS39632B page 85 PIC18F2455 2550 4455 4550 EXAMPLE 6 3 WRITING TO FLASH PROGRAM MEMORY MOVLW D 64 number of bytes in erase block MOVWF COUNTER MOVLW BUFFER ADDR HIGH point to buffer MOVWF FSROH MOVLW BUFFER ADDR LOW MOVWF FSROL MOVLW CODE ADDR UPPER Load TBLPTR with the base MOVWF BLPTRU address of the memory block MOVLW CODE ADDR HIGH MOVWF BLPTRH MOVLW CODE ADDR LOW MOVWF BLPTRL READ BLOCK TBLRD read into TABLAT and inc MOVF TABLAT W get data MOVWF POSTINCO store data DECFSZ COUNTER done BRA READ BLOCK repeat MODIFY WORD MOVLW DATA ADDR HIGH point to buffer MOVWF FSROH MOVLW DATA ADDR LOW MOVWF FSROL MOVLW NEW DATA LOW update buffer word MOVWF POSTINCO MOVLW NEW DATA HIGH MOVWF NDFO ERASE BLOCK MOVLW CODE ADDR UPPER load TBLPTR with the base MOVWF BLPTRU address of the memory block MOVLW CODE ADDR HIGH MOVWF BLPTRH MOVLW CODE ADDR LOW MOVWF BLPTRL BSF EECON1 EEPGD point to Flash program memory BCF EECON1 CFGS access Flash program memory BSF EECON1 WREN enable write to memory BSF EECON1 FREE enable Row Erase operation BCF INTCON GIE di
403. e selectable operation as a 16 bit timer or counter 2004 Microchip Technology Inc Preliminary DS39632B page 137 PIC18F2455 2550 4455 4550 14 1 Timer3 Operation Timer3 can operate in one of three modes e Timer e Synchronous Counter e Asynchronous Counter The operating mode is determined by the clock select bit TMR3CS T3CON lt 1 gt When TMR3CS is cleared 0 Timer3 increments on every internal instruction FIGURE 14 1 TIMER3 BLOCK DIAGRAM cycle Fosc 4 When the bit is set Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled As with Timer1 the RC1 T1OSI UOE and RCO T10SO T13CKI pins become inputs when the Timer oscillator is enabled This means the values of TRISC lt 1 0 gt are ignored and the pins are read as 0 Timer1 Oscillator T10SO T13CKI x T3CKPS1 T3CKPSO Timer1 Clock Input a Prescaler Synchronize 1 2 4 8 4 Detect 0 1 Fosc 4 I Internal i i lock 0 T1OSI x ets TIOSCEN TMR3CS 2 Sleep Input Timer3 g On Off T3SYNC TMR3ON CCP1 CCP2 Special Event Trigger Clear TMR3 Y TMR3 Set CCP1 CCP2 Select from T3CON lt 6 3 gt TMRSL High Byte M gt TMRSIF on Overflow Note 1 When enable bit T1OSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain
404. e to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 2 One or more bits in the INTCONx or PIRx registers will be affected to cause wake up 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 4 See Table 4 3 for Reset value for specific condition 5 PORTA lt 6 gt LATA lt 6 gt and TRISA lt 6 gt are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 DS39632B page 54 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 NOTES DS39632B page 56 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 50 MEMORY ORGANIZATION There are three types of memory in PIC18 enhanced microcontroller devices Program Memory e Data RAM Data EEPROM As Harvard architecture devices the data and program memories use separate busses this allows for con current access of the two memory spaces The data EEPROM for practical purposes can be regarded as a peripheral device since it is addressed and accessed through a set of control registers Additional detailed information on the operation of the Flash program memory is provided in Section 6 0 Flash Program Memory Data EEPROM is discussed sepa
405. e with clock input from TOCKI max prescale gt Internal Data Bus DS39632B page 126 Preliminary 2004 Microchip Technology Inc 2004 Microchip Technology Inc Preliminary DS39632B page 127 PIC18F2455 2550 4455 4550 NOTES AEO rr nm ssnOKr m O O Sy DS39632B page 128 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 12 0 TIMER1 MODULE The Timer1 timer counter module incorporates these features Software selectable operation as a 16 bit timer or counter e Readable and writable 8 bit registers TMR1H and TMRIL Selectable clock source internal or external with device clock or Timer1 oscillator internal options e Interrupt on overflow e Module Reset on CCP special event trigger e Device clock status flag T1RUN A simplified block diagram of the Timer1 module is shown in Figure 12 1 A block diagram of the module s operation in Read Write mode is shown in Figure 12 2 The module incorporates its own low power oscillator to provide an additional clocking option The Timer1 oscillator can also be used as alow power clock source for the microcontroller in power managed operation Timer1 can also be used to provide Real Time Clock RTC functionality to applications with only a minimal addition of external components and code overhead Timer1 is controlled through the T1CON Control register Register 12 1 It also contains the Timer1 Oscillator Enable bit TIOSC
406. eadable nor writable refer to Figure 11 2 TMROH is updated with the contents of the high byte of TimerO during a read of TMROL This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte Similarly a write to the high byte of TimerO must also take place through the TMROH Buffer register The high byte is updated with the contents of TMROH when a write occurs to TMROL This allows all 16 bits of TimerO to be updated at once TIMERO BLOCK DIAGRAM 8 BIT MODE N Fosc 4 0 Prescaler TOSE TOCS 3 TOPS2 TOPSO PSA 1 TOCKI pin 7 Programmable 19 Sync with Set Internal r TMROL 1 gt TMROIF Clocks on Overflow 2 Tcy Delay 8 Note Upon Reset Timer0 is enabled in 8 bit mode with clock input from TOCKI max prescale L lt gt Internal Data Bus FIGURE 11 2 TIMERO BLOCK DIAGRAM 16 BIT MODE Fosc 4 1 J Programmable o TOCKI pin Prescaler TOSE TOCS 3 TOPS2 TOPSO PSA Sync with TMRO Set ae m TMROL High Byte 9 TMROIF AN ZN IIg on Overflow 2 Tcy Delay nes Read TMROL Write TMROL N8 N8 V TMROH i lt Note Upon Reset Timer0 is enabled in 8 bit mod
407. eated Setup Time 400 kHz mode 0 6 us _ Start condition 91 THD STA Start Condition 100 kHz mode 4 0 us After this period the first Hold Time 400 kHz mode 0 6 us clock pulse is generated 106 THD DAT Data Input Hold 100 kHz mode 0 ns Time 400 kHz mode 0 0 9 us 107 TSU DAT Data Input Setup 100 kHz mode 250 ns Note 2 Time 400 kHz mode 100 ns 92 TSU STO Stop Condition 100 kHz mode 4 7 us Setup Time 400 kHz mode 0 6 us 109 TAA Output Valid from 100 kHz mode 3500 ns Note 1 Clock 400 kHz mode ns 110 TBUF Bus Free Time 100 kHz mode 4 7 us Time the bus must be free 400 kHz mode 1 3 us before a new transmission can start D102 CB Bus Capacitive Loading 400 pF Note 1 As a transmitter the device must provide this internal minimum delay time to bridge the undefined region min 300 ns of the falling edge of SCL to avoid unintended generation of Start or Stop conditions 2 A Fast mode I C bus device can be used in a Standard mode 12C bus system but the reguirement TSU DAT gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line TR max TSU DAT 1000 250 1250 ns according to the Standard mode 12C bus specification before the SCL line is released 2004 Microchip Technology Inc Preliminar
408. eceives a complete byte it is transferred to SSPBUF and the SSPIF interrupt is set During transmission the SSPBUF is not double buffered A write to SSPBUF will write to both SSPBUF and SSPSR DS39632B page 202 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 19 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPSTAT MSSP STATUS REGISTER I2C MODE R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 SMP CKE D A P S RW UA BF bit 7 bit 0 SMP Slew Rate Control bit In Master or Slave mode 1 Slew rate control disabled for Standard Speed mode 100 kHz and 1 MHz 0 Slew rate control enabled for High Speed mode 400 kHz CKE SMBus Select bit In Master or Slave mode 1 Enable SMBus specific inputs 0 Disable SMBus specific inputs D A Data Address bit In Master mode Reserved In Slave mode 1 Indicates that the last byte received or transmitted was data 0 Indicates that the last byte received or transmitted was address P Stop bit 1 Indicates that a Stop bit has been detected last 0 Stop bit was not detected last Note This bit is cleared on Reset and when SSPEN is cleared S Start bit 1 Indicates that a Start bit has been detected last 0 Start bit was not detected last Note This bit is cleared on Reset and when SSPEN is cleared R W Read Write bit Information 2C mode only In Slave mode 1 Read
409. ecific information Standard PICmicro device marking consists of Microchip part number year code week code and traceability code For PICmicro device marking beyond this certain price adders apply Please check with your Microchip Sales Office For QTP devices any special marking adders are included in QTP price 2004 Microchip Technology Inc Preliminary DS39632B page 397 PIC18F2455 2550 4455 4550 Package Marking Information Continued 44 Lead TOFP Example MICROCHIP MICROCHIP XXXXXXXXXX PIC18F4550 XXXXXXXXXX PT XXXXXXX XXX 0410017 O YYWWNNN O 44 Lead QFN Example XXXXXXXXXX PIC18F4550 XXXXXXXXXX ML XXXXXXXXXX 0410017 YYWWNNN EE EO EO r sr ccr a r DS39632B page 398 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 30 2 Package Details The following sections give the technical details of the packages 28 Lead Skinny Plastic Dual In line SP 300 mil Body PDIP j El CA GA GA GA GA GA TI GA TI LH LA TI hoh ra ch ch ch rh ch a ch a a rl I i 5 Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p 100 2 54 Top t
410. ed Synchronous mode Unused in this mode Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 236 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 20 1 Baud Rate Generator BRG The BRG is a dedicated 8 bit or 16 bit generator that supports both the Asynchronous and Synchronous modes of the EUSART By default the BRG operates in 8 bit mode setting the BRG16 bit BAUDCON lt 3 gt selects 16 bit mode The SPBRGH SPBRG register pair controls the period of a free running timer In Asynchronous mode bits BRGH TXSTA lt 2 gt and BRG16 BAUDCON lt 3 gt also control the baud rate In Synchronous mode BRGH is ignored Table 20 1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode internally generated clock Given the desired baud rate and Fosc the nearest integer value for the SPBRGH SPBRG registers can be calculated using the formulas in Table 20 1 From this the error in baud rate can be determined An example calculation is shown in Example 20 1 Typical baud rates and error values for the various Asynchronous modes are shown in Table 20 2 It may be advanta TABLE 20 1 BAUD RATE FORMULAS geous to use the high baud rate BRGH 1 or the 16 bit BRG to reduce the baud rate error or
411. ed set SSPIF in software 2004 Microchip Technology Inc Preliminary DS39632B page 229 PIC18F2455 2550 4455 4550 19 4 17 2 Bus Collision During a Repeated Start Condition During a Repeated Start condition a bus collision occurs if a A low level is sampled on SDA when SCL goes from low level to high level b SCL goes low before SDA is asserted low indicating that another master is attempting to transmit a data 1 When the user deasserts SDA and the pin is allowed to float high the BRG is loaded with SSPADD lt 6 0 gt and counts down to o The SCL pin is then deasserted and when sampled high the SDA pin is sampled FIGURE 19 29 If SDA is low a bus collision has occurred i e another master is attempting to transmit a data o see Figure 19 29 If SDA is sampled high the BRG is reloaded and begins counting If SDA goes from high to low before the BRG times out no bus collision occurs because no two masters can assert SDA at exactly the same time If SCL goes from high to low before the BRG times out and SDA has not already been asserted a bus collision occurs In this case another master is attempting to transmit a data 1 during the Repeated Start condition see Figure 19 30 If at the end of the BRG time out both SCL and SDA are still high the SDA pin is driven low and the BRG is reloaded and begins counting At the end of the count regardless of the stat
412. ed and clock stretching will not occur 2 The CKP bit can be set in software regardless of the state of the BF bit The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition 19 4 4 2 Glock Stretching for 10 bit Slave Receive Mode SEN 1 In 10 bit Slave Receive mode during the address seguence clock stretching automatically takes place but CKP is not cleared During this time if the UA bit is set after the ninth clock clock stretching is initiated The UA bit is set after receiving the upper byte of the 10 bit address and following the receive of the second byte of the 10 bit address with the R W bit cleared to 0 The release of the clock line occurs upon updating SSPADD Clock stretching will occur on each data receive seguence as described in 7 bit mode Note Ifthe user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs and if the user hasnt cleared the BF bit by read ing the SSPBUF register before that time then the CKP bit will still NOT be asserted low Clock stretching on the basis of the state of the BF bit only occurs during a data sequence not an address sequence 19 4 4 4 Clock Stretching for 10 bit Slave Transmit Mode In 10 bit Slave Transmit mode clock stretching is controlled during the first two address sequences by the state of the UA b
413. eep through an interrupt or a Watchdog Timer time out the contents of the CVRCON register are not affected To minimize current consumption in Sleep mode the voltage reference should be disabled 23 4 Effects of a Reset A device Reset disables the voltage reference by clearing bit CVREN CVRCON lt 7 gt This Reset also disconnects the reference from the RA2 pin by clearing bit CVROE CVRCON lt 6 gt and selects the high voltage range by clearing bit CVRR CVRCON lt 5 gt The CVR value select bits are also cleared 23 5 Connection Considerations The voltage reference module operates independently of the comparator module The output of the reference generator may be connected to the RAZ pin if the TRISA lt 2 gt bit and the CVROE bit are both set Enabling the voltage reference output onto RA2 when it is configured as a digital input will increase current consumption Connecting RA2 as a digital output with CVRSS enabled will also increase current consumption The RA2 pin can be used as a simple D A output with limited drive capability Due to the limited current drive capability a buffer must be used on the voltage reference output for external connections to VREF Figure 23 2 shows an example buffering technique DS39632B page 270 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 23 2 VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX cre an are Mw F
414. egisters Receive Associated Registers Transmit 243 Auto Wake up on Sync Break 246 Break Character Sequence RECEIVE saranane an Setting up 9 Bit Mode with Address Detect 244 Transmitter Baud Rate Generator BRG Associated Registers 237 Auto Baud Rate Detect 240 Baud Rate Error Calculating 237 Baud Rates Asynchronous Modes 00n 238 High Baud Rate Select BRGH Bit 237 Operation in Power Managed Modes SamBpBliig sodorni n u nG un uu Synchronous Master Mode n Associated Registers Receive Associated Registers Transmit 249 Reception ss Transmission Synchronous Slave Mode Associated Registers Receive Associated Registers Transmit Reception ss TRANSMISSION i us n sa eee at Evaluation and Programming Tools Extended Instruction Set ADDESR A u divn la la a var lak ADDULNK and Using MPLAB IDE Tools F Fail Safe Clock Monitor 279 294 Interrupts in Power Managed Modes 295 POR or Wake up from Sleep WDT During Oscillator
415. egisters The values in the registers are then loaded back into their associated registers if the RETFIE FAST instruction is used to return from the interrupt If both low and high priority interrupts are enabled the stack registers cannot be used reliably to return from low priority interrupts If a high priority interrupt occurs while servicing a low priority interrupt the stack register values stored by the low priority interrupt will be overwritten In these cases users must save the key registers in software during a low priority interrupt If interrupt priority is not used all interrupts may use the fast register stack for returns from interrupt If no interrupts are used the fast register stack can be used to restore the Status WREG and BSR registers at the end of a subroutine call To use the fast register stack for a subroutine call a CALL label FAST instruction must be executed to save the Status WREG and BSR registers to the fast register stack A RETURN FAST instruction is then executed to restore these registers from the fast register stack Example 5 1 shows a source code example that uses the fast register stack during a subroutine call and return EXAMPLE 5 1 FAST REGISTER STACK CODE EXAMPLE CALL SUB1 FAST STATUS WREG BSR SAVED IN FAST REGISTER STACK e e SUBI e RETURN FAST RESTORE VALUES SAVED IN FAST REGISTER STACK 5 1 4 LOOK UP TABLES IN PROGRAM MEMORY There may be pr
416. en generates an interrupt signal by setting the HLVDIF bit The trip point voltage is software programmable to any one of 16 values The trip point is selected by programming the HLVDL3 HLVDLO bits HLVDCON lt 3 0 gt The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source This mode is enabled when bits HLVDL3 HLVDLO are set to 1111 In this state the comparator input is multiplexed from the external input pin HLVDIN This gives users flexibility because it allows them to configure the High Low Voltage Detect interrupt to occur at any voltage in the valid operating range HLVD MODULE BLOCK DIAGRAM WITH EXTERNAL INPUT Set DS39632B page 274 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 24 2 HLVD Setup The following steps are needed to set up the HLVD module 1 Disable the module by clearing the HLVDEN bit HLVDCON lt 4 gt 2 Write the value to the HLVDL3 HLVDLO bits that selects the desired HLVD trip point 3 Set the VDIRMAG bit to detect high voltage VDIRMAG 1 or low voltage VDIRMAG o 4 Enable the HLVD module by setting the HLVDEN bit 5 Clear the HLVD Interrupt Flag HLVDIF PIR2 lt 2 gt which may have been set from a previous interrupt 6 Enable the HLVD interrupt if interrupts are desired by setting the HLVDIE and GIE GIEH bits PIE2 lt 2 gt and INTCON lt 7 gt An inter
417. ensure that the correct bank is selected Otherwise data may be read from or written to the wrong location This can be disastrous if a GPR is the intended target of an operation but an SFR is written to instead Verifying and or changing the BSR for each read or write to data memory can become very inefficient To streamline access for the most commonly used data memory locations the data memory is configured with an Access Bank which allows users to access a mapped block of memory without specifying a BSR The Access Bank consists of the first 96 bytes of memory 00h 5Fh in Bank 0 and the last 160 bytes of memory 60h FFh in Block 15 The lower half is known as the Access RAM and is composed of GPRS This upper half is also where the device s SFRs are mapped These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8 bit address Figure 5 5 The Access Bank is used by core PIC18 instructions that include the Access RAM bit the a parameter in the instruction When a is equal to 1 the instruction uses the BSR and the 8 bit address included in the opcode for the data memory address When a is 0 however the instruction is forced to use the Access Bank address map the current value of the BSR is ignored entirely Using this forced addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first
418. er shown in Register 5 2 contains the arithmetic status of the ALU As with any other SFR it can be the operand for any instruction If the Status register is the destination for an instruction that affects the Z DC C OV or N bits the results of the instruction are not written instead the status is updated according to the instruction performed There fore the result of an instruction with the Status register as its destination may be different than intended As an example CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged 000u uluu It is recommended that only BCF BSF SWAPF MOVFF and MOVWF instructions are used to alter the Status register because these instructions do not affect the Z C DC OV or N bits in the Status register For other instructions that do not affect Status bits see the instruction set summaries in Table 26 2 and Table 26 3 Note The C and DC bits operate as the Borrow and Digit Borrow bits respectively in subtraction REGISTER 5 2 STATUS REGISTER U 0 U 0 U 0 R W x R W x R W x R W x R W x N OV Z DC C bit 7 bit 0 bit 7 5 Unimplemented Read as 0 bit 4 N Negative bit This bit is used for signed arithmetic 2 s complement It indicates whether the result was negative ALU MSB 1 1 Result was negative 0 Result was positive bit 3 OV Overflow bit This bit is used for signed arithmetic 2 s comp
419. er clock source is the internal RC oscillator INTRC which provides a nominal 31 kHz output INTRC is enabled if it is selected as the device clock source it is also enabled automatically when any of the following are enabled Power up Timer Fail Safe Clock Monitor e Watchdog Timer Two Speed Start up These features are discussed in greater detail in Section 25 0 Special Features of the CPU The clock source frequency INTOSC direct INTRC direct or INTOSC postscaler is selected by configuring the IRCF bits of the OSCCON register page 32 2 2 5 1 Internal Oscillator Modes When the internal oscillator is used as the micro controller clock source one of the other oscillator modes External Clock or External Crystal Resonator must be used as the USB clock source The choice of USB clock source is determined by the particular internal oscillator mode There are four distinct modes available 1 INTHS mode The USB clock is provided by the oscillator in HS mode 2 INTXT mode The USB clock is provided by the oscillator in XT mode 3 INTCKO mode The USB clock is provided by an external clock input on OSC1 CLKI the OSC2 CLKO pin outputs Fosc 4 4 INTIO mode The USB clock is provided by an external clock input on OSC1 CLKI the OSC2 CLKO pin functions as a digital I O RA6 Of these four modes only INTIO mode frees up an additional pin OSC2 CLKO RAG6 for port I O use 2 2 5 2 OSCTUNE Register
420. er is latched on the rising edge of the ninth SCL input pulse If the SDA line is high not ACK then the data transfer is complete In this case when the ACK is latched by the slave the slave logic is reset resets SSPSTAT regis ter and the slave monitors for another occurrence of the Start bit If the SDA line was low ACK the next transmit data must be loaded into the SSPBUF register Again pin RB1 AN10 INT1 SCK SCL must be enabled by setting bit CKP SSPCON1 lt 4 gt An MSSP interrupt is generated for each data transfer byte The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte The SSPIF bit is set on the falling edge of the ninth clock pulse 2004 Microchip Technology Inc Preliminary DS39632B page 207 CT SLAVE MODE TIMING WITH SEN 0 RECEPTION 7 BITADDRESS PIC18F2455 2550 4455 4550 FIGURE 19 8 0 NAS USUM 0 0 9S9J JOU SBOP dY dM0 ques JOU SI MOV IN INS s 4INddSs sneosg 18S SI AOdSS Y lt g gt INOOdSS AOdSS peel si 4NAdSS 9JEMIJOS ul parea 7 lt 0 gt 1VLSASS 44 49 SUB1 sejeulW19 Y J9 se u sng lt gt LHid 4IdSS E NE f Vf a a a V VJ V AV 2 2 272 222 VY 2 A A a AYCA E os 2004 Microchip Technology Inc Preliminary DS39632B page 208 PIC18F2455 2550 4455 4550 CT SLAVE MODE TIMING TRANSMISSION 7 BITADDRESS
421. erminated by the internal programming timer 6 4 1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is 1 Load Table Pointer register with address of row being erased 2 Set the EECONI register for the erase operation set EEPGD bit to point to program memory clear the CFGS bit to access program memory e set WREN bit to enable writes set FREE bit to enable the erase Disable interrupts Write 55h to EECON2 Write OAAh to EECON2 Set the WR bit This will begin the Row Erase cycle 7 The CPU wil stall for duration of the erase about 2 ms using internal timer 8 Re enable interrupts DOP OD EXAMPLE 6 2 ERASING A FLASH PROGRAM MEMORY ROW MOVLW CODE ADDR UPPER load TBLPTR with the base MOVWF TBLPTRU address of the memory block MOVLW CODE ADDR HIGH MOVWF TBLPTRH MOVLW CODE ADDR LOW MOVWF TBLPTRL ERASE ROW BSF EECON1 EEPGD point to Flash program memory BCF EECON1 CFGS access Flash program memory BSF EECON1 WREN enable write to memory BSF EECON1 FREE enable Row Erase operation BCF INTCON GIE disable interrupts Required MOVLW Bala Seguence MOVWF EECON2 write 55h MOVLW OAAh MOVWF EECON2 write OAAh BSF EECON1 WR start erase CPU stall BSF INTCON GIE re enable interrupts DS39632B page 84 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 6 5 Wr
422. ers working in high level languages to perform certain operations on data structures more efficiently These include e dynamic allocation and deallocation of software stack space when entering and leaving subroutines e function pointer invocation e software stack pointer manipulation manipulation of variables located in a software stack A summary of the instructions in the extended instruc tion set is provided in Table 26 3 Detailed descriptions are provided in Section 26 2 2 Extended Instruction Set The opcode field descriptions in Table 26 1 page 302 apply to both the standard and extended PIC18 instruction sets The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C the user may likely never use these instructions directly in assembler The syntax for these commands is pro vided as a reference for users who may be reviewing code that has been generated by a compiler Note 26 2 1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments using one of the File Select Registers and some offset to specify a source or destination register When an argument for an instruction serves as part of indexed addressing it is enclosed in square brackets I This is done to indicate that the argument is used as an index or offset The MPASM Assembler will flag an error if it determines that an index or off
423. es 230 480 LA 40 C 240 450 uA 25 C VDD 5 0V 250 430 HA 85 C PIC18LFX455 X550 255 475 LA 40 C 260 450 A 25 C VDD 2 0V 270 430 uA 85 C PIC18LFX455 X550 420 900 HA 40 C Fosc 4 MHz 430 850 A 25 C VDD 3 0V PRI_IDLE mode 450 810 uA 85 C EC oscillator All devices 0 9 1 5 mA 40 C 0 9 1 4 mA 25 C VDD 5 0V 0 9 1 3 mA 85 C All devices 6 0 16 mA 40 C 6 2 16 mA 25 C VDD 4 2V __ 66 16 mA 85 C DLE All devices 8 1 18 mA 40 G EC oscillator 8 3 18 mA 25 C VDD 5 0V 9 0 18 mA 85 C All devices 8 0 18 mA 40 C 8 1 18 mA 25 C VDD 4 2V 82 18 mA 85 C FOSG 4B Mile PRI_IDLE mode All devices 9 8 21 mA 40 C EC oscillator 10 0 21 mA 25 C VDD 5 0V 10 5 21 mA 85 C Shading of rows is to assist in readability of the table The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in a
424. es of the assembler include Support for the entire dsPIC30F instruction set Support for fixed point and floating point data Command line interface e Rich directive set e Flexible macro language e MPLAB IDE compatibility 27 7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code devel opment in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any pin The execu tion can be performed in Single Step Execute Until Break or Trace mode The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers as well as the MPASM assembler The software simulator offers the flexibility to develop and debug code outside of the laboratory environment making it an excellent economical software development tool 27 8 MPLAB SIM30 Software Simulator The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level On any given instruction the data areas can be examined or modified and stimuli can be applied from a file or user defined key press to any of the pins The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler The simulator
425. es a data EEPROM erase write cycle or a program memory erase cycle or write cycle The operation is self timed and the bit is cleared by hardware once write is complete The WR bit can only be set not cleared in software o Write cycle to the EEPROM is complete RD Read Control bit 1 Initiates an EEPROM read Read takes one cycle RD is cleared in hardware The RD bit can only be set not cleared in software RD bit cannot be set when EEPGD 1 or CFGS 1 0 Does not initiate an EEPROM read Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 81 PIC18F2455 2550 4455 4550 6 2 2 TABLE LATCH REGISTER TABLAT The Table Latch TABLAT is an 8 bit register mapped into the SFR space The Table Latch register is used to hold 8 bit data during data transfers between program memory and data RAM 6 2 3 TABLE POINTER REGISTER TBLPTR The Table Pointer TBLPTR register addresses a byte within the program memory The TBLPTR is comprised of three SFR registers Table Pointer Upper Byte Table Pointer High Byte and Table Pointer Low Byte TBLPTRU TBLPTRH TBLPTRL These three regis ters join to form a 22 bit wide pointer The low order 21 bits allow the device to address up to 2 Mbytes of program memory space The 22nd bit allows access to the dev
426. es not using ping pong buffering The PKTDIS bit UCON lt 4 gt is a flag indicating that the SIE has disabled packet transmission and reception This bit is set by the SIE when a SETUP token is received to allow setup processing This bit cannot be set by the microcontroller only cleared clearing it allows the SIE to continue transmission and or reception Any pending events within the Buffer Descriptor Table will still be available indicated within the USTAT register s FIFO buffer The RESUME bit UCON lt 2 gt allows the peripheral to perform a remote wake up by executing Resume signaling To generate a valid remote wake up firm ware must set RESUME for 10 ms and then clear the bit For more information on Resume signaling see Sections 7 1 7 5 11 9 and 11 4 4 in the USB 2 0 specification The SUSPND bit UCON lt 1 gt places the module and supporting circuitry i e voltage regulator in a low power mode The input clock to the SIE is also disabled This bit should be set by the software in response to an IDLEIF interrupt It should be reset by the microcontroller firmware after an ACTVIF interrupt is observed When this bit is active the device remains attached to the bus but the transceiver outputs remain Idle The voltage on the VUSB pin may vary depending on the value of this bit Setting this bit before a IDLEIF request will result in unpredictable bus behavior Note While in Suspend mode a typical bus powered USB
427. evel refresher of USB 17 10 1 LAYERED FRAMEWORK USB device functionality is structured into a layered framework graphically shown in Figure 17 13 Each level is associated with a functional level within the device The highest layer other than the device is the configuration A device may have multiple configura tions for example a particular device may have multiple power requirements based on Self Power Only or Bus Power Only modes For each configuration there may be multiple interfaces Each interface could support a particular mode of that configuration Below the interface is the endpoint s Data is directly moved at this level There can be as many as 16 bidirectional endpoints Endpoint 0 is always a control endpoint and by default when the device is on the bus Endpoint 0 must be available to configure the device 17 10 2 FRAMES Information communicated on the bus is grouped into 1 ms time slots referred to as frames Each frame can contain many transactions to various devices and endpoints Figure 17 9 shows an example of a transaction within a frame 17 10 38 TRANSFERS There are four transfer types defined in the USB specification Isochronous This type provides a transfer method for large amounts of data up to 1023 bytes with timely delivery ensured however the data integrity is not ensured This is good for streaming applications where small data loss is not critical such as audio Bulk This
428. falling edge of the device clock source but cleared on the rising edge of the sample clock FIGURE 25 3 FSCM BLOCK DIAGRAM Clock Monitor Latch CM edge triggered Peripheral p Clock s 6 INTRC Source 64 Q 32 us 488 Hz 2 048 ms Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock If a sample clock falling edge occurs while CM is still set a clock failure has been detected Figure 25 4 This causes the following the FSCM generates an oscillator fail interrupt by setting bit OSCFIF PIR2 lt 7 gt e the device clock source is switched to the internal oscillator block OSCCON is not updated to show the current clock source this is the fail safe condition and the WDT is reset During switchover the postscaler freguency from the internal oscillator block may not be sufficiently stable for timing sensitive applications In tnese cases it may be desirable to select another clock configuration and enter an alternate power managed mode This can be done to attempt a partial recovery or execute a controlled shut down See Section 3 1 4 Multiple Sleep Commands and Section 25 3 1 Special Considerations for Using Two Speed Start up for more details To use a higher clock speed on wake up the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRC
429. ffff ffff None 1 2 NEGF f a Negate f 1 0110 110a ffff ffff C DC Z OV N RLCF f d a Rotate Left f through Carry 1 0011 Olda ffff ffff C Z N 1 2 RLNCF f d a Rotate Left f No Carry 1 0100 Olda ffff ffff Z N RRCF f d a Rotate Right f through Carry 1 0011 00da ffff ffff C Z N RRNCF f d a Rotate Right f No Carry 1 0100 00da ffff ffff Z N SETF f a Set f 1 0110 100a ffff ffff None 1 2 SUBFWB f d a Subtract f from WREG with 1 0101 Olda ffff ffff C DC Z OV N borrow SUBWF f d a Subtract WREG from f 1 0101 lida ffff ffff C DC Z OV N 1 2 SUBWFB f d a Subtract WREG from f with 1 0101 10da ffff ffff C DC Z OV N borrow SWAPF f d a Swap nibbles inf 1 0011 10da ffff ffff None TSTFSZ fa Test f skip if 0 1 20r3 0110 Olla ffff ffff None 1 2 XORWF f d a Exclusive OR WREG with f 1 0001 10da ffff ffff Z N Note 1 When a Port register is modified as a function of itself e g MOVF PORTB 0 the value used will be that value present on the pins themselves For example if the data latch is 1 for a pin configured as input and is driven low by an external device the data will be written back with a o 2 If this instruction is executed on the TMRO register and where applicable d 1 the prescaler will be cleared if assigned 3 If Program Counter PC is modified or a conditional test is true the instruction requires two cycles The second cycle is executed as a NOP 4 Some instructions are two word ins
430. fficient linking of single libraries instead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing replacement deletion and extraction 27 5 MPLAB C30 C Compiler The MPLAB C30 C compiler is a full featured ANSI compliant optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabili ties and afford fine control of the compiler code generator MPLAB C30 is distributed with a complete ANSI C standard library All library functions have been vali dated and conform to the ANSI C library standard The library includes functions for string manipulation dynamic memory allocation data conversion time keeping and math functions trigonometric exponential and hyperbolic The compiler provides symbolic information for high level source debugging with the MPLAB IDE 27 6 MPLAB ASM30 Assembler Linker and Librarian MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices MPLAB C30 compiler uses the assembler to produce it s object file The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file Notable featur
431. for load conditions TABLE 28 16 EXAMPLE SPI MODE REQUIREMENTS MASTER MODE CKE 1 Une Symbol Characteristic Min Max Units Conditions 71 TscH SCK Input High Time Continuous 1 25 TCY 30 ns 71A Slave mode Single Byte 40 ns Note 1 72 TscL SCK Input Low Time Continuous 1 25 TCY 30 ns 72A Slave mode Single Byte 40 ns Note 1 73 TdiV2scH Setup Time of SDI Data Input to SCK Edge 100 ns TdiV2scL 73A Tb2b Last Clock Edge of Byte 1 to the 1st Clock Edge 1 5 Tcy 40 ns Note 2 of Byte 2 74 TscH2diL Hold Time of SDI Data Input to SCK Edge 100 ns TscL2diL 75 TdoR SDO Data Output Rise Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 2 0V 76 TdoF SDO Data Output Fall Time 25 ns 78 TscR SCK Output Rise Time PIC18FXXXX 25 ns Master mode PIC18LFXXXX 45 ns Vpp 2 0V 79 TscF SCK Output Fall Time Master mode 25 ns 80 TscH2doV SDO Data Output Valid after PIC18FXXXX 50 ns TscL2doV SCK Edge PIC18LFXXXX 100 ns voo 2 0V 81 TdoV2scH SDO Data Output Setup to SCK Edge TcY ns TdoV2scL Note 1 Reguires the use of Parameter 73A 2 Only if Parameter 71A and 72A are used 2004 Microchip Technology Inc Preliminary DS39632B page 383 PIC18F2455 2550 4455 4550 FIGURE 28 13 EXAMPLE SPI SLAVE MODE TIMING CKE 0
432. fore the transfer was received In this case the SSPSR register value is not loaded into the SSPBUF but bit SSPIF PIR1 lt 3 gt is set The BF bit is cleared by reading the SSPBUF register while bit SSPOV is cleared through software The SCL clock input must have a minimum high and low for proper operation The high and low times of the IC specification as well as the requirement of the MSSP module are shown in timing parameter 100 and parameter 101 see Table 28 20 19 4 3 1 Addressing Once the MSSP module has been enabled it waits for a Start condition to occur Following the Start condition the eight bits are shifted into the SSPSR register All incoming bits are sampled with the rising edge of the clock SCL line The value of register SSPSR lt 7 1 gt is compared to the value of the SSPADD register The address is compared on the falling edge of the eighth clock SCL pulse If the addresses match and the BF and SSPOV bits are clear the following events occur 1 The SSPSR register value is loaded into the SSPBUF register 2 The Buffer Full bit BF is set An ACK pulse is generated 4 MSSP Interrupt Flag bit SSPIF PIR1 lt 3 gt is set interrupt is generated if enabled on the falling edge of the ninth SCL pulse In 10 bit Address mode two address bytes need to be received by the slave The five Most Significant bits MSbs of the first address byte specify if this is a 10 bit address Bit RW SSPSTAT
433. frequency To use a higher clock speed on wake up the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF2 IRCFO immediately after FIGURE 25 2 Reset For wake ups from Sleep the INTOSC or postscaler clock sources can be selected by setting IRCF2 IRCFO prior to entering Sleep mode In all other power managed modes Two Speed Start up is not used The device will be clocked by the currently selected clock source until the primary clock source becomes available The setting of the IESO bit is ignored 25 3 1 SPECIAL CONSIDERATIONS FOR USING TWO SPEED START UP While using the INTRC oscillator in Two Speed Start up the device still obeys the normal command sequences for entering power managed modes including serial SLEEP instructions refer to Section 3 1 4 Multiple Sleep Commands In practice this means that user code can change the SCS1 SCS0 bit settings or issue SLEEP instructions before the OST times out This would allow an application to briefly wake up perform routine housekeeping tasks and return to Sleep before the device starts to operate from the primary oscillator User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit OSCCON lt 3 gt If the bit is set the primary oscillator is providing the clock Otherwise the internal oscillator block is providing the clock during w
434. g VREF and VREF inputs and the comparator voltage reference output The operation of pins RA3 RAO and RAS as A D converter inputs is selected by clearing setting the control bits in the ADCON1 register A D Control Register 1 Note Ona Power on Reset RAS and RA3 RAO are configured as analog inputs and read as 0 RA4 is configured as a digital input All other PORTA pins have TTL input levels and full CMOS output drivers The TRISA register controls the direction of the RA pins even when they are being used as analog inputs The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs EXAMPLE 10 1 INITIALIZING PORTA CLRF PORTA Initialize PORTA by clearing output data latches CLRF LATA Alternate method to clear output data latches OVLW OFh Configure A D OVWF ADCON1 for digital inputs OVLW 07h Configure comparators OVWF CMCON i for digital input OVLW OCFh Value used to initialize data direction Set RA lt 3 0 gt as inputs RA lt 5 4 gt as outputs OVWF TRISA 2004 Microchip Technology Inc Preliminary DS39632B page 111 PIC18F2455 2550 4455 4550 TABLE 10 1 PORTA I O SUMMARY Pin Function cain 1 0 O Type Description RAO ANO RAO 0 OUT DIG LATA lt 0 gt data output not affected by analog input al IN
435. g individual bytes it is not necessary to load all 32 holding registers before executing a write operation TABLAT Write Register TBLPTR xxxxx0 TBLPTR xxxxx1 TBLPTR xxxxx2 Holding Register Holding Register TBLPTR xxxx1F Holding Register e o Holding Register Program Memory 6 5 1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be 1 Read 64 bytes into RAM 2 Update data values in RAM as necessary 3 Load Table Pointer register with address being erased 4 Execute the Row Erase procedure 5 Load Table Pointer register with address of first byte being written 6 Write 32 bytes into the holding registers with auto increment 7 Setthe EECON1 register for the write operation e set EEPGD bit to point to program memory clear the CFGS bit to access program memory e set WREN to enable byte writes 8 Disable interrupts 9 Write 55h to EECON2 10 Write OAAh to EECON2 11 Setthe WR bit This will begin the write cycle 12 The CPU will stall for duration of the write about 2 ms using internal timer 13 Re enable interrupts 14 Repeat steps 6 through 14 once more to write 64 bytes 15 Verify the memory table read This procedure will reguire about 8 ms to update one row of 64 bytes of memory An example of th
436. ge 403 PIC18F2455 2550 4455 4550 NOTES DS39632B page 404 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 APPENDIX A REVISION HISTORY Revision A May 2004 Original data sheet for PIC18F2455 2550 4455 4550 devices APPENDIX B DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B 1 Revision B October 2004 This revision includes updates to the Electrical Specifi cations in Section 28 0 Electrical Characteristics and includes minor corrections to the data sheet text TABLE B 1 DEVICE DIFFERENCES Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550 Program Memory Bytes 24576 32768 24576 32768 Program Memory Instructions 12288 16384 12288 16384 Interrupt Sources 19 19 20 20 I O Ports Ports A B C E Ports A B C E Ports A B C D E Ports A B C D E Capture Compare PWM Modules 2 2 1 1 Enhanced Capture Compare 0 0 1 1 PWM Modules Parallel Communications SPP No No Yes Yes 10 bit Analog to Digital Module 10 input channels 10 input channels 13 input channels 13 input channels Packages 28 pin PDIP 28 pin PDIP 40 pin PDIP 40 pin PDIP 28 pin SOIC 28 pin SOIC 44 pin TQFP 44 pin TQFP 44 pin QFN 44 pin QFN 2004 Microchip Technology Inc Preliminary DS39632B page 405 PIC18F2455 2550 4455 4550 APPENDIX C CONVERSION CONSIDERATIONS This appendix dis
437. h 000004h 000006h Instruction 1 MOVLW 055h OFh 55h 000008h Instruction 2 GoTo 0006h EFh 03h 00000Ah FOh 00h 00000Ch Instruction 3 MOVFF 123h 456h Cih 23h 00000Eh F4h 56h 000010h 000012h 000014h 5 2 4 TWO WORD INSTRUCTIONS used by the instruction seguence If the first word is The standard PIC18 instruction set has four two word instructions CALL MOVFF GOTO and LSFR ln all cases the second word of the instructions always has 1111 as its four Most Significant bits the other 12 bits are literal data usually a data memory address The use of 1111 in the 4 MSbs of an instruction specifies a special form of NOP If the instruction is executed in proper sequence immediately after the first word the data in the second word is accessed and skipped for some reason and the second word is executed by itself a NOP is executed instead This is necessary for cases when the two word instruction is preceded by a conditional instruction that changes the PC Example 5 4 shows how this works Note See Section 5 5 Program Memory and the Extended Instruction Set for information on two word instruction in the extended instruction set EXAMPLE 5 4 TWO WORD INSTRUCTIONS CASE 1 Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 is RAM location 0 1100 0001 0010 0011 MOVFF REG1 REG2 No skip this word LLL viko OO Maso Execute this word as a NOP 0010 0100 0000 0
438. h interrupt source to be assigned a high priority level or a low priority level The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h High priority interrupt events will interrupt any low priority interrupts that may be in progress There are ten registers which are used to control interrupt operation These registers are RCON e INTCON INTCON2 e INTCON3 e PIR1 PIR2 e PIE1 PIE2 e IPR1 IPR2 It is recommended that the Microchip header files supplied with MPLAB IDE be used for the symbolic bit names in these registers This allows the assembler compiler to automatically take care of the placement of these bits within the specified register Each interrupt source has three bits to control its operation The functions of these bits are Flag bit to indicate that an interrupt event occurred Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set e Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit RCON lt 7 gt When interrupt priority is enabled there are two bits which enable interrupts globally Setting the GIEH bit INTCON lt 7 gt enables all interrupts that have the priority bit set high priority Setting the GIEL bit INTCON lt 6 gt enables all interrupts that have the priority bit cleared low priority When the interrupt flag enable
439. h new data from the TXREG if available Once the TXREG register transfers the data to the TSR register occurs in one TCYCLE the TXREG register is empty and the TXIF flag bit PIR1 lt 4 gt is set The inter rupt can be enabled or disabled by setting or clearing the interrupt enable bit TXIE PIE1 lt 4 gt TXIF is set regardless of the state of enable bit TXIE it cannot be cleared in software It will reset only when new data is loaded into the TXREG register While flag bit TXIF indicates the status of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register TRMT is a read only bit which is set when the TSR is empty No interrupt logic is tied to this bit so the user must poll this bit in order to determine if the TSR register is empty The TSR is not mapped in data memory so it is not available to the user To set up a Synchronous Master Transmission 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRG16 bit as required to achieve the desired baud rate 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC 3 If interrupts are desired set enable bit TXIE 4 If 9 bit transmission is desired set bit TX9 5 Enable the transmission by setting bit TXEN 6 If 9 bit transmission is selected the ninth bit should be loaded in bit TX9D 7 Start transmission by loading data to the TXREG register 8 If using interrup
440. haded cells indicate conditions do not apply for the designated device Note 1 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 2 One or more bits in the INTCONX or PIRx registers will be affected to cause wake up 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 4 See Table 4 8 for Reset value for specific condition 5 PORTA lt 6 gt LATA lt 6 gt and TRISA lt 6 gt are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read 0 2004 Microchip Technology Inc Preliminary DS39632B page 53 PIC18F2455 2550 4455 4550 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Applicable Devices Power on Reset WDT Reset Wake up via WDT Brown out Reset RESET Instruction or Interrupt Stack Resets IPR2 2455 2550 4455 4550 Te Us 1111 1111 uuuu uuuu PIR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuu PIE2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu IPR1 2455 2550 4455 4550 1111 TIIT 1111 Iri uuuu uuuu 2455 2550 4455 4550 111 1111
441. hardware and software is included to run the dem onstration programs The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device program mer PICSTART Plus development programmer or MPLAB ICD 2 with a Universal Programmer Adapter The MPLAB ICD 2 and MPLAB ICE in circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware A prototype area extends the circuitry for additional application components Some of the features include an RS 232 interface a 2 x 16 LCD display a piezo speaker an on board temperature sensor four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers 27 18 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package All the necessary hardware and software is included to run the demonstration programs 27 19 PICDEM 4 8 14 18 Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capa bilities of the 8 14 and 18 pin PIC16XXXX and PIC18XXXX MCUs including the PIC16F818 819 PIC16F87 88 PIC16F62XA and the PIC18F1320 family of microcontrollers PICDEM 4 is intended to showcase the many features of these low pin count parts including LIN and Motor Control using ECCP Special provisions are made for low power operation with the supercapacitor circuit and jumpers allow on board hardware to be disabled to eliminate current draw in t
442. he extended instruction set is enabled When the content of FSR2 is 00h the boundaries of the Access RAM are essentially remapped to their original values This may be useful in creating backward compatible code If this technigue is used it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer Users must also keep in mind the syntax reguirements of the extended instruction set see Section 26 2 3 1 Extended Instruction Syntax with Standard PIC18 Commands Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation it can also be very annoying if a simple aritnmetic operation is carried out on the wrong register Users who are accustomed to the PIC18 programming must keep in mind that when the extended instruction set is enabled register addresses of 5Fh or less are used for Indexed Literal Offset Addressing Representative examples of typical byte oriented and bit oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected The operand conditions shown in the examples are applicable to all instructions of these types 26 2 3 1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled the file register argument in the standard byte oriented and
443. he 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to The holding registers are used to program the contents of Program Memory P M Refer to Section 6 0 Flash Program Memory for additional details on programming Flash memory The TBLPTR a 21 bit pointer points to each byte in the program memory TBLPTR has a 2 Mbyte address range The LSb of the TBLPTR selects which byte of the pro gram memory location to access TBLPTR 0 0 Least Significant Byte of Program Memory Word TBLPTR 0 1 Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows nochange post increment post decrement pre increment 2 Q1 Q2 Q3 Q4 Decode No No No operation operation operation No No No No operation operation operation operation Read Write to TABLAT Holding Register TBLWT Table Write Continued Example 1 TBLWT Before Instruction TABLAT 55h TBLPTR 00A356h HOLDING REGISTER 00A356h FFh After Instructions table write completion TABLAT 55h TBLPTR 00A357h HOLDING REGISTER 00A356h 55h Example 2 TBLWT Before Instruction TABLAT 34h TBLPTR 01389Ah HOLDING REGISTER 01389Ah FFh HOLDING REGISTER 01389Bh FFh After Instruction table write completion TABLAT 34h TBLPTR 01389Bh HOLDING REGISTER 01389Ah FFh HOLDING REGISTER 01389Bh
444. he UIE register the enable bits only affect the REGISTER UEIE propagation of an interrupt condition to the microcon The USB Error Register 17 10 contains the enable bits for each of the USB error interrupt sources Setting any of these troller s interrupt logic The flag bits are still set by their interrupt conditions allowing them to be polled and serviced with actually generating an interrupt Interrupt Enable register bits will enable the respective error interrupt source in the UEIR register to propagate into the UERR bit at the top level of the interrupt logic REGISTER 17 10 UEIE USB ERROR INTERRUPT ENABLE REGISTER bit 7 bit 6 5 bit 4 bit 3 bit 2 bit 1 bit 0 R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 BTSEE BTOEE DFN8EE CRCIGEE CROSEE PIDEE bit 7 bit 0 BTSEE Bit Stuff Error Interrupt Enable bit 1 Bit stuff error interrupt enabled 0 Bit stuff error interrupt disabled Unimplemented Read as BTOEE Bus Turnaround Time out Error Interrupt Enable bit 1 Bus turnaround time out error interrupt enabled 0 Bus turnaround time out error interrupt disabled DFNBEE Data Field Size Error Interrupt Enable bit 1 Data field size error interrupt enabled 0 Data field size error interrupt disabled CRCIGEE CRC16 Failure Interrupt Enable bit 1 CRC16 failure interrupt enabled 0 CRC16 failure interrupt disabled CRC5EE CRC5 Host Error Interr
445. he byte address and the Table Latch TABLAT register contains the data that is read from or written to program memory Data is transferred to or from program memory one byte at a time Table read and table write operations are discussed further in Section 6 1 Table Reads and Table Writes DS39632B page 60 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 5 2 PIC18 Instruction Cycle 9 2 1 CLOCKING SCHEME The microcontroller clock input whether from an internal or external source is internally divided by four to generate four non overlapping guadrature clocks 01 Q2 Q3 and Q4 Internally the program counter is incremented on every 01 the instruction is fetched from the program memory and latched into the instruc tion register during Q4 The instruction is decoded and executed during the following Q1 through Q4 The clocks and instruction execution flow are shown in Figure 5 3 9 2 2 INSTRUCTION FLOW PIPELINING An Instruction Cycle consists of four Q cycles Q1 through Q4 The instruction fetch and execute are pipe lined in such a manner that a fetch takes one instruction cycle while the decode and execute takes another instruction cycle However due to the pipelining each instruction effectively executes in one cycle If an instruction causes the program counter to change e g GOTO then two cycles are required to complete the instruction Example 5 3 A fetch cycle
446. he switch of the unmodulated outputs to the beginning of the next period the modulated outputs P1B and P1D remain inactive This relationship is shown in Figure 16 8 Note that in the Full Bridge Output mode the ECCP module does not provide any dead band delay In gen eral since only one output is modulated at all times dead band delay is not required However there is a situation where a dead band delay might be required This situation occurs when both of the following conditions are true 1 The direction of the PWM output changes when the duty cycle of the output is at or near 100 2 The turn off time of the power switch including the power device and driver circuit is greater than the turn on time tion changes from forward to reverse at a near 100 duty cycle At time ti the outputs PIA and PID become inactive while output P1C becomes active In this example since the turn off time of the power devices is longer than the turn on time a shoot through current may flow through power devices QC and QD see Figure 16 7 for the duration of t The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward If changing PWM direction at high duty cycle is required for an application one of the following requirements must be met 1 Reduce PWM for changing directions 2 Use switch drivers that can drive the switches off faster than they can drive them on a PWM
447. hen CCP2MX o Default assignment is RC1 3 All other pin functions are disabled when ICSP or ICD operation is enabled 4 40 44 pin devices only 2004 Microchip Technology Inc Preliminary DS39632B page 115 PIC18F2455 2550 4455 4550 TABLE 10 3 PORTB I O SUMMARY CONTINUED Pin Function eating 1 0 1 0 Type Description RB6 KBI2 RB6 0 OUT DIG LATB lt 6 gt data output PGC 1 IN TTL PORTB lt 6 gt data input weak pull up when RBPU bit is cleared KBI2 1 IN TTL Interrupt on pin change PGC x IN ST Serial execution ICSP clock input for ICSP and ICD operation RB7 KBI3 RB7 0 OUT DIG LATB lt 7 gt data output PGD 1 IN TTL PORTB lt 7 gt data input weak pull up when RBPU bit is cleared KBI3 1 IN TTL Interrupt on pin change PGD x OUT DIG Serial execution data output for ICSP and ICD operation x IN ST Serial execution data input for ICSP and ICD operation Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input l2C SMB C S overridden for th Configuration on POR is determined by PBADEN configuration bit Pins are configured as analog inputs when PBADEN MBus input buffer TTL TTL Buffer Input x Dont care TRIS bit does not affect port direction or is is option is set and digital inputs when PBADEN is cleared 2 Alternate pin assignment for CCP2 when CCP2MX o Default assignment is RC1 3
448. hen an Acknowledge sequence is in progress then WCOL is set and the contents of the buffer are unchanged the write doesn t occur FIGURE 19 23 19 4 13 STOP CONDITION TIMING A Stop bit is asserted on the SDA pin at the end of a receive transmit by setting the Stop Enable bit PEN SSPCON2 lt 2 gt At the end of a receive transmit the SCL line is held low after the falling edge of the ninth clock When the PEN bit is set the master will assert the SDA line low When the SDA line is sampled low the Baud Rate Generator is reloaded and counts down to o When the Baud Rate Generator times out the SCL pin will be brought high and one TBRG Baud Rate Generator rollover count later the SDA pin will be deasserted When the SDA pin is sampled high while SCL is high the P bit SSPSTAT lt 4 gt is set A TBRG later the PEN bit is cleared and the SSPIF bit is set Figure 19 24 19 4 13 1 WCOL Status Flag If the user writes the SSPBUF when a Stop seguence is in progress then the WCOL bit is set and the contents of the buffer are unchanged the write doesn t occur ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here ACKEN 1 ACKDT 0 F ACKEN automatically cleared write to SSPCON2 an TBRG l TBRG gt SDA x DO ACK I I SCL 8 9 1 I I SSPIF Set SSPIF atthe eee l eT end of receive software Set SSPIF at the end Note TBRG one Baud Rate Generator
449. hese registers and or bits are unimplemented on 28 pin devices DS39632B page 192 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 0 MASTER SYNCHRONOUS SERIAL PORT MSSP MODULE 19 1 Master SSP MSSP Module Overview The Master Synchronous Serial Port MSSP module is a serial interface useful for communicating with other peripheral or microcontroller devices These peripheral devices may be serial EEPROMs shift registers display drivers A D converters etc The MSSP module can operate in one of two modes Serial Peripheral Interface SPI Inter Integrated Circuit IC Full Master mode Slave mode with general address call The 1 C interface supports the following modes in hardware e Master mode e Multi Master mode Slave mode 19 2 Control Registers The MSSP module has three associated registers These include a status register SSPSTAT and two control registers SSPCONI and SSPCON2 The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or 12C mode Additional details are provided under the individual sections 19 3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously All four SPI modes are supported To accomplish communication typically three pins are used Serial Data Out SDO RC7 RX DT SDO Serial Data In SDI
450. his mode Included on the demo board are pro visions for Crystal RC or Canned Oscillator modes a five volt regulator for use with a nine volt wall adapter or battery DB 9 RS 232 interface ICD connector for programming via ICSP and development with MPLAB ICD 2 2 x 16 liquid crystal display PCB footprints for H Bridge motor driver LIN transceiver and EEPROM Also included are header for expansion eight LEDs four potentiometers three push buttons and a proto typing area Included with the kit is a PIC16F627A and a PIC18F1320 Tutorial firmware is included along with the User s Guide DS39632B page 354 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 27 20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers including PIC17C752 PIC17C756A PIC17C762 and PIC17C766 A pro grammed sample is included The PRO MATE II device programmer or the PICSTART Plus development pro grammer can be used to reprogram the device for user tailored application development The PICDEM 17 demonstration board supports program download and execution from external on board Flash memory A generous prototype area is available for user hardware expansion 27 21 PICDEM 18R PIC18C601 801 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601 801 family of Microch
451. hnology Inc Preliminary DS39632B page 413 PIC18F2455 2550 4455 4550 Oscillator Selection 279 Oscillator Settings for USB 1 29 Oscillator Start up Timer OST Oscillator Switehing assarrar 31 Oscillator Transitions nen 32 Oscillator Timer Oscillator Timer3 P Packaging Information 397 Details r s aa rr 399 Marking iiir ir r raa 397 PICkit 1 Flash Starter Kit 355 PICSTART Plus Development Programmer 354 PIE R GISIErS 7 a a a nias s kitu Qua a mtu sasa 104 Pin Functions MCOLR VPPIRES insu rr a aa 12 16 NC ICCK ICPGC NC ICDT ICPGD eh zi ro 21 NOG IGPORTS sci Atte fet taha 21 NC ICRST ICVPP OSCA CLEKI uu isto OSC2 CLKO RAG a 12 16 RAO ANO RATAN I strasna ti Tai 13 17 RA2 AN2 VREF CVREF osassnisssessssnsnssenssrrrneesreeeene 13 17 RAS ANS VREF RA4 TOCKI C1OUT ROV a RAS AN4 SS HLVDIN C2OUT rene RBO AN12 INTO FLTO SDI SDA RB1 AN10 INT1 SCK SCL cr 14 18 RB2 ANB INT2 VMO armes 14 18 RB3 AN9 CCP2 VPO RB4 AN11 KBIO cnrs RB4 AN11 KBI0 CSSPP rennes 18 RBS5 KBI1 PGM res 14 18 RBG KBI2 PGC rennes 14 18 RB7 KBIS PGD rennes 14 18 RC0 T1OSO T13CKI ere 15 19 RC1 T1OSI CCP2 UOE uzanan kaa 15 19 RELI nA V ne te 15 RC2 CCP1 P1A z
452. hutdown ECCP1AS o Configure source FLTO Comparator 1 or Comparator 2 e Wait for non shutdown condition 4 Configure the ECCP module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values Select one of the available output configurations and direction with the P1M1 P1MO bits Select the polarities of the PWM output signals with the CCP1M3 CCP1MO bits 5 Set the PWM duty cycle by loading the CCPRIL register and CCP1CON lt 5 4 gt bits 6 For Half Bridge Output mode set the dead band delay by loading ECCP1DEL lt 6 0 gt with the appropriate value 7 If auto shutdown operation is required load the ECCP1AS register Select the auto shutdown sources using the ECOPAS2 ECCPASO bits Select the shutdown states of the PWM output pins using the PSSAC1 PSSACO and PSSBD1 PSSBDO bits Set the ECCPASE bit ECCP1AS lt 7 gt Configure the comparators using the CMCON register Configure the comparator inputs as analog inputs 8 If auto restart operation is required set the PRSEN bit ECCP1DEL lt 7 gt 9 Configure and start TMR2 e Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit PIR1 lt 1 gt e Set the TMR2 prescale value by loading the T2CKPS bits T2CON lt 1 0 gt Enable Timer2 by setting the TMR2ON bit T2CON lt 2 gt 10 Enable PWM outputs after a new PWM cycle has started e Wait until TMRn overflows TMRNIF bit is set E
453. ial vl 19 ROAID VM arr 15 19 RO S DENB S aaa RI kina chine 15 19 RC6 TX CK o 15 19 RC7 RXDT SDO Lu u u a ir hn 15 19 RD0 SPP0 RD1 SPP1 RD2 SPP2 RD3 SPP3 RD4 SPP4 RD5 SPP5 P1B rennes RD6 SPP6 P1C ag RD7 SPP7 P1D nr RE0 AN5 CK1SPP rennes RE1 AN6 CK2SPP Pinout I O Descriptions PIC18F 2455 2550 PIC18F4455 4550 PIR Registers PLL Frequency Multiplier eee eeeeeeeeeeeeeeeeee HSPLL XTPLL ECPLL and ECPIO Oscillator Modes 26 PLL Lock Time out a 47 ROP Sasa T rs nr 330 POR See Power on Reset PORTA Associated Registers 113 VOSUMMANV u a u al dans usa ays 112 LATA Register u 111 PORTA Register 5 TRISA Register 111 PORTB Associated Registers 116 O S mmMar visionner ion there LATB REGIS semer PORTB Register we RB1 ANTO INT1 SCK SCL Pin 207 RB7 RB4 Interrupt on Change Flag RBIF Bit see nana ava 114 TRISB R gister J n u ana 114 PORTG Associated Registers 119 VO Summary 118 LATC Register se TAZ PORTC Register v LAT TRISC R GISIEr hesia r eaaa 117 PORTD Associated Registers
454. ice This 28 pin Configuration mode is controlled through a single pin NC ICPORTS Connecting this pin to Vss forces the device to function as a 28 pin device fea tures normally associated with the 40 44 pin devices are disabled along with their corresponding control registers and bits This includes PORTD and PORTE the SPP and the Enhanced PWM functionality of CCP1 On the other hand connecting the pin to VDD forces the device to function in its default configuration The configuration option is only available when back ground debugging and the dedicated ICD ICSP port are both enabled DEBUG configuration bit is clear and ICPRT configuration bit is set When disabled NC ICPORTS is a No Connect pin 25 10 Single Supply ICSP Programming The LVP configuration bit enables Single Supply ICSP Programming formerly known as Low Voltage ICSP Programming or LVP When Single Supply Program ming is enabled the microcontroller can be programmed without requiring high voltage being applied to the MCLR VPP RE3 pin but the RB5 KBI1 P GM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I O pin While programming using Single Supply Program ming VDD is applied to the MCLR VPP RE3 pin as in normal execution mode To enter Programming mode VDD is applied to the PGM pin Note 1 High Voltage Programming is always available regardless of the state of the LVP bit by applying V
455. ice ID the user ID and the configuration bits The table pointer TBLPTR is used by the TBLRD and TBLWT instructions These instructions can update the TBLPTR in one of four ways based on the table opera tion These operations are shown in Table 6 1 These operations on the TBLPTR only affect the low order 21 bits 6 2 4 TABLE POINTER BOUNDARIES TBLPTR is used in reads writes and erases of the Flash program memory When a TBLRD is executed all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT When a TBLWT is executed the five LSbs of the Table Pointer register TBLPTR lt 4 0 gt determine which of the 32 program memory holding registers is written to When the timed write to program memory begins via the WR bit the 17 MSbs of the TBLPTR TBLPTR lt 21 6 gt determine which program memory block of 32 bytes is written to For more detail see Section 6 5 Writing to Flash Program Memory When an erase of program memory is executed the 16 MSbs of the Table Pointer register TBLPTR lt 21 6 gt point to the 64 byte block that will be erased The Least Significant bits TBLPTR lt 5 0 gt are ignored Figure 6 3 describes the relevant boundaries of the TBLPTR based on Flash program memory operations TABLE 6 1 TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTION
456. icrochip Technology Inc Preliminary DS39632B page 315 PIC18F2455 2550 4455 4550 BZ Branch if Zero Syntax BZ n Operands 128 lt n lt 127 Operation if Zero bit is 1 PC 2 2n PC Status Affected None Encoding 1110 0000 nnnn nnnn Description If the Zero bit is 1 then the program will branch The 2 s complement number 2n is added to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2 2n This instruction is then a two cycle instruction Words d Cycles 1 2 Q Cycle Activity If Jump 01 Q2 Q3 Q4 Decode Read literal Process Write to PC n Data No No No No operation operation operation operation If No Jump Q1 Q2 Q3 Q4 Decode Read literal Process No n Data operation Example HERE BZ Jump Before Instruction PC address HERE After Instruction If Zero T PC address Jump If Zero 0 PC address HERE 2 CALL Subroutine Call Syntax CALL k s Operands 0 lt k lt 1048575 se 0 1 Operation PC 4 TOS k PC lt 20 1 gt if s 21 W gt WS Status gt STATUSS BSR gt BSRS Status Affected None Encoding 1st word k lt 7 0 gt 1110 110s k kkk kkkky 2nd word k lt 19 8 gt 1111 k kkk kkkk kkkkg Description Subroutine call of entire 2 Mbyte memory range First return addre
457. ied to VDD Case 2 Time out Sequence on Power up MCLR Tied to VDD VDD Rise TPWRT TimerO and Timer1 External Clock Transition for Entry to Idle Mode 40 Transition for Entry to SEC_RUN Mode 497 Transition for Entry to Sleep Mode 39 Transition for Two Speed Start up INTOSC to HSPLL Transition for Wake from Idle to Run Mode i Transition for Wake from Sleep HSPLL Transition from RC RUN Mode to PRI RUN M0ode 2eme 38 Transition from SEC RUN Mode to PRI RUN Mode HSPLL a 37 Transition to RC RUN Mode 1 USB SIGNA u a ra lt Timing Diagrams and Specifications 376 A D Conversion Requirement 394 Capture Compare PWM Requirements CCP 381 CLKO and I O Requirements 378 EUSART Synchronous Receive Requirements sssesssessissserrirsnsrrereerenrrnarrnrreasnn 390 EUSART Synchronous Transmission Requirements 390 Example SPI Mode Requirements Master Mode CKE 0 382 Example SPI Mode Requirements Master Mode CKE 1 383 Example SPI Mode Reguirements Slave Mode CKE 0 384 Examp
458. igher power operation bit 1 PBADEN PORTB A D Enable bit Affects ADCON1 Reset state ADCON1 controls PORTB lt 4 0 gt pin configuration 1 PORTB lt 4 0 gt pins are configured as analog input channels on Reset 0 PORTB lt 4 0 gt pins are configured as digital I O on Reset bit 0 CCP2MX CCP2 Mux bit 1 CCP2 input output is multiplexed with RC1 0 CCP2 input output is multiplexed with RB3 Legend R Readable bit P Programmable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state 2004 Microchip Technology Inc Preliminary DS39632B page 285 PIC18F2455 2550 4455 4550 REGISTER 25 6 bit 7 bit 6 bit 5 bit 4 3 bit 2 bit 1 bit 0 CONFIG4L CONFIGURATION REGISTER 4 LOW BYTE ADDRESS 300006h R P 1 R P 0 R P 0 U 0 U 0 R P 1 U 0 R P 1 DEBUG XINST ICPRTU LVP STVREN bit 7 bit 0 DEBUG Background Debugger Enable bit 1 Background debugger disabled RB6 and RB7 configured as general purpose 1 O pins 0 Background debugger enabled RB6 and RB7 are dedicated to In Circuit Debug XINST Extended Instruction Set Enable bit 1 Instruction set extension and Indexed Addressing mode enabled 0 Instruction set extension and Indexed Addressing mode disabled Legacy mode ICPRT Dedicated In Circuit Debug Programming Port ICPORT Enable bit 1 ICPORT enabled 0 ICPORT disabled Note 1 Availa
459. ile the 12C conditions were not valid for a transmission to be started must be cleared in software 0 No collision In Slave Transmit mode 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision In Receive mode Master or Slave modes This is a don t care bit bit 6 SSPOV Receive Overflow Indicator bit In Receive mode 1 A byte is received while the SSPBUF register is still holding the previous byte must be cleared in software 0 No overflow In Transmit mode This is a don t care bit in Transmit mode bit 5 SSPEN Synchronous Serial Port Enable bit 1 Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 Disables serial port and configures these pins as I O port pins Note When enabled the SDA and SCL pins must be properly configured as input or output bit 4 CKP SCK Release Control bit In Slave mode 1 Release clock 0 Holds clock low clock stretch used to ensure data setup time In Master mode Unused in this mode bit 3 0 SSPM3 SSPMO Synchronous Serial Port Mode Select bits 1111 IC Slave mode 10 bit address with Start and Stop bit interrupts enabled 1110 I C Slave mode 7 bit address with Start and Stop bit interrupts enabled 1011 IC Firmware Controlled Master mode Slave Idle 1000 C Master mode clock Fosc 4 SSPADD 1 0111 IC Slave mode 10 bit address 0110 I
460. imer1 0 Stops Timer Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 129 PIC18F2455 2550 4455 4550 12 1 Timer1 can operate in one of these modes Timer1 Operation e Timer e Synchronous Counter e Asynchronous Counter The operating mode is determined by the clock select bit TMR1CS T1CON lt 1 gt When TMRICS is cleared 0 Timer1 increments on every internal instruction cycle Fosc 4 When the bit is set Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled When Timer1 is enabled the RC1 T1OSI UOE and RCO T1OSO T13CKI pins become inputs This means the values of TRISC lt 1 0 gt are ignored and the pins are read as 0 FIGURE 12 1 TIMER1 BLOCK DIAGRAM Timer1 Oscillator io a V pd On Off 1 T10SO T13CKI X I Z 1 Prescaler Synchronize A i Fosc 4 1 2 4 8 4 Detect 9 i 7 Internal 0 T1OSI XX l i 3 Ce re Sleep Input TIOSCEN TMRICS Timer1 T1CKPS1 T1CKPSO Omo TISYNC TMR1ON U Set Clear TMRI TMRIL High Byte TMRIIE CCP Special Event Trigger on Overflow Note 1 When enable bit TIOSCEN is cleared the inverter and feedback resistor are turned off to eliminate power drain
461. inary DS39632B page 165 PIC18F2455 2550 4455 4550 REGISTER 17 2 UCFG USB CONFIGURATION REGISTER R W 0 R W 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 UTEYE UOEMON UPUEN 9 UTRDIS FSEN PPB1 PPBO bit 7 bit 0 bit 7 UTEYE USB Eye Pattern Test Enable bit 1 Eye pattern test enabled 0 Eye pattern test disabled bit 6 UOEMON USB OE Monitor Enable bit La OE signal active it indicates intervals during which the D D lines are driving 0 OE signal inactive bit 5 Unimplemented Read as bit 4 UPUEN USB On Chip Pull up Enable bit 23 1 On chip pull up enabled pull up on D with FSEN 1 or D with FSEN 0 0 On chip pull up disabled bit 3 UTRDIS On Chip Transceiver Disable bit 1 On chip transceiver disabled digital transceiver interface enabled 0 On chip transceiver active bit 2 FSEN Full Speed Enable bi 1 Full speed device controls transceiver edge rates requires input clock at 48 MHz 0 Low speed device controls transceiver edge rates requires input clock at 6 MHz bit 1 0 PPB1 PPB0 Ping Pong Buffers Configuration bits 11 Reserved 10 Even Odd ping pong buffers enabled for all endpoints 01 Even Odd ping pong buffer enabled for OUT Endpoint 0 00 Even Odd ping pong buffers disabled Note 1 If UTRDIS is set the OE signal will be active independent of the UOEMON bit setting 2 The UPUEN UTRDIS and FSEN bits should never be changed while the USB module is enabled
462. ine SIE that allows fast communications between any USB host and the PIC microcontroller The SIE can be interfaced directly to the USB utilizing the internal transceiver or it can be connected through an external transceiver An internal 3 3V regulator is also available to power the internal transceiver in 5V applications Some special hardware features have been included to improve performance Dual port memory in the device s data memory space USB RAM has been supplied to share direct memory access between the microcontroller core and the SIE Buffer descriptors are also provided allowing users to freely program end point memory usage within the USB RAM space A Streaming Parallel Port has been provided to support the uninterrupted transfer of large volumes of data such as isochronous data to external memory buffers Figure 17 1 presents a general overview of the USB peripheral and its features FIGURE 17 1 USB PERIPHERAL AND OPTIONS PIC18FX455 X550 Family eee 34 3 3V Regulator External 3 3V q VUSB ee 3 I VREGEN EN Supply Optional q Jo P External FSEN UPUEN L Internal Pull ups I I Full L Speed z z ER U c D Xx UTRDIS I Transceiver LSS at
463. ing what should be program data to an 8 bit address of F9h while the BSR is OFh will end up resetting the program counter While any bank can be selected only those banks that are actually implemented can be read or written to Writes to unimplemented banks are ignored while reads from unimplemented banks will return o s Even so the Status register will still be affected as if the operation was successful The data memory map in Figure 5 5 indicates which banks are implemented In the core PIC18 instruction set only the MOVFF instruction fully specifies the 12 bit address of the source and target registers This instruction ignores the BSR completely when it executes All other instructions include only the low order address as an operand and must use either the BSR or the Access Bank to locate their target registers 2004 Microchip Technology Inc Preliminary DS39632B page 63 PIC18F2455 2550 4455 4550 FIGURE 5 5 DATA MEMORY MAP FOR PIC18F2455 2550 4455 4550 DEVICES BSR lt 3 0 gt Data Memory Map Wheres The BSR is ignored and the 060 00h Access RAM yu Access Bank is used Bank 0 060h The first 96 bytes are FFh GPR OFFh general purpose RAM Geer 00h 100h from Bank 0 P Bank 1 GPR The remaining 160 bytes are FFh 1FFh Special Function Registers 0010 00h 200h from Bank 15 Bank 2 GPR FFh 2FFh Whena 1 0011 00h 300h The BSR specifies th
464. input C1OUT 0 OUT DIG Comparator 1 output takes priority over port data RCV x IN TTL External USB transceiver RCV input RA5 AN4 SS RA5 0 OUT DIG LATA lt 5 gt data output not affected by analog input HLVDIN C2OUT a IN TTL PORTA lt 5 gt data input disabled when analog input enabled AN4 1 IN ANA _ A D input channel 4 Default configuration on POR ss al IN TTL Slave select input for SSP MSSP module HLVDIN 1 IN ANA High Low Voltage Detect external trip point input C2OUT 0 OUT DIG Comparator 2 output takes priority over port data OSC2 CLKO RA6 0 OUT DIG LATA lt 6 gt data output Available only in ECIO ECPIO and INTIO RA6 modes otherwise reads as 0 1 IN TTL PORTA lt 6 gt data input Available only in ECIO ECPIO and INTIO modes otherwise reads as 0 OSC2 OUT ANA Main oscillator feedback output connection all XT and HS modes CLKO OUT DIG System cycle clock output Fosc 4 available in EC ECPLL and INTCKO modes Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input TTL TTL Buffer Input x Don t care TRIS bit does not affect port direction or is overridden for this option DS39632B page 112 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 10 2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page P
465. interrupt 0 Disables the TMRO overflow interrupt INTOIE INTO External Interrupt Enable bit 1 Enables the INTO external interrupt 0 Disables the INTO external interrupt RBIE RB Port Change Interrupt Enable bit 1 Enables the RB port change interrupt 0 Disables the RB port change interrupt TMROIF TMRO Overflow Interrupt Flag bit 1 TMRO register has overflowed must be cleared in software 0 TMRO register did not overflow INTOIF INTO External Interrupt Flag bit 1 The INTO external interrupt occurred must be cleared in software 0 The INTO external interrupt did not occur RBIF RB Port Change Interrupt Flag bit 1 At least one of the RB7 RB4 pins changed state must be cleared in software 0 None of the RB7 RB4 pins have changed state Note A mismatch condition will continue to set this bit Reading PORTB will end the mismatch condition and allow the bit to be cleared Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 99 PIC18F2455 2550 4455 4550 REGISTER 9 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 INTCON2 INTERRUPT CONTROL REGISTER 2 R W 1 R W 1 R W 1 R W 1 U 0 R W 1 U 0 R W 1 RBPU INTEDGO INTEDGI INTEDG2 TMROIP RBIP bit 7 RBPU PORTB
466. ion operation operation operation operation operation operation If skip and followed by 2 word instruction If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operation operation operation operation operation operation operation No No No No No No No No operation operation operation operation operation operation operation operation Example HERE INCFSZ CNT 1 0 Example HERE NFSNZ REG 1 0 NZERO ZERO ZERO NZERO Before Instruction Before Instruction PC Address HERE PG Address HERE After Instruction After Instruction CNT CNT 1 REG REG 1 IfCNT 0 IfREG lt 0 PC Address ZERO PG Address NZERO CNT 0 IfREG 0 PC Address NZERO PC Address ZERO 2004 Microchip Technology Inc Preliminary DS39632B page 323 PIC18F2455 2550 4455 4550 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax IORLW k Syntax IORWF f d a Operands 0 lt k lt 255 Operands 0 lt f lt 255 ORA de 0 1 Operation W OR k gt W igh M ae 0 1 Status Affected N Z Operation W OR f gt dest Encoding 0000 1001 kkkk kkkk 9 Status Affected N Z Description The contents of W are ORed with the Encoding ee ee eight bit literal k The result is placed in neoaing YOO Olde W Description Inclusive OR W with register
467. ion 100 kHz mode 2 Tosc BRG 1 ms Setup Time 400 kHz mode 2 Tosc BRG 1 ms 1 MHz model 2 Tosc BRG 1 ms 109 TAA Output Valid 100 kHz mode 3500 ns from Clock 400 kHz mode 1000 ns 1 MHz mode ns 110 TBUF Bus Free Time 100 kHz mode 4 7 ms Time the bus must be free 400 kHz mode 1 3 ms before a new transmission can start D102 CB Bus Capacitive Loading 400 pF Note 1 Maximum pin capacitance 10 pF for all IC pins 2 A Fast mode IC bus device can be used in a Standard mode 1 C bus system but parameter 107 gt 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line parameter 102 parameter 107 1000 250 1250 ns for 100 kHz mode before the SCL line is released 2004 Microchip Technology Inc Preliminary DS39632B page 389 PIC18F2455 2550 4455 4550 FIGURE 28 19 EUSART SYNCHRONOUS TRANSMISSION MASTER SLAVE TIMING RT ON pin ae 121 gt lt 121 MN RC7 RX DT AZ a pin xX X 120 4 Note Refer to Figure 28 4 for load conditions TABLE 28 23 EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS re Symbol Characteristic Min Max Units Conditions 120 TckH2dtV SYNC XMIT MASTER 8 SLAVE Clock High to
468. ion as soon as the Reset source has cleared Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power managed mode is entered before the primary clock becomes ready the primary clock is then shut down 2004 Microchip Technology Inc Preliminary DS39632B page 41 PIC18F2455 2550 4455 4550 3 5 4 EXIT WITHOUT AN OSCILLATOR In these instances the primary clock source either START UP DELAY does not reguire an oscillator start up delay since it is already running PRI_IDLE or normally does not Certain exits from power managed modes do not I require an oscillator start up delay EC and any internal invoke the OST at all There are two cases oscillator modes However a fixed delay of interval PRI IDLE mode where the primary clock source Tcsp following the wake event is still required when is not stopped and the primary clock source is not any of the XT or HS modes DS39632B page 42 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 4 0 RESET The PIC18F2455 2550 4455 4550 devices differentiate between various kinds of Reset a Power on Reset POR MCLR Reset during normal operation c MCLR Reset during power managed modes Watchdog Timer WDT Reset during execution e Programmable Brown out Reset BOR f RESET Ins
469. ion time is shown in Table 8 1 8 2 Example 8 1 shows the instruction sequence for an 8x 8 unsigned multiplication Only one instruction is required when one of the arguments is already loaded in the WREG register Example 8 2 shows the sequence to do an 8 x 8 signed multiplication To account for the sign bits of the arguments each argumen s Most Significant bit MSb is tested and the appropriate subtractions are done Operation EXAMPLE 8 1 8 x 8 UNSIGNED MULTIPLY ROUTINE MOVF ARG1 W i MULWF ARG2 ARG1 ARG2 gt PRODH PRODL EXAMPLE 8 2 8 x 8 SIGNED MULTIPLY ROUTINE MOVF ARG1 W MULWF ARG2 ARG1 ARG2 gt PRODH PRODL Test Sign Bit PRODH PRODH ARG1 BTFSC ARG2 SB SUBWF g O U MOVE ARG2 W BTFSC SUBWF mu gt YF O Q OR EL m rJ w Test Sign Bit PRODH PRODH ARG2 TABLE 8 1 PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Program Cycles Time Routine Multiply Method Memory n Words Max 40 MHz 10 MHz 4 MHz Without h ltipl 1 27 6 69 8x8 unsigned itnout hardware mu tiply 3 69 6 9 us us us Hardware multiply 1 1 100 ns 400 ns 1 us Without hardware multiply 33 91 9 1 us 36 4 us 91 us 8 x 8 signed Hardware multiply 6 6 600 ns 2 4 us 6 us Without hardware multiply 21 242 24 2 us 96 8 us 242 us 16 x 16 unsigned Hardware multiply 28 28 2 8 us 11 2 us 28 us With
470. ions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction 2004 Microchip Technology Inc Preliminary DS39632B page 305 PIC18F2455 2550 4455 4550 TABLE 26 2 PIC18FXXXX INSTRUCTION SET CONTINUED Mnemonic A 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C DC Z OV N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z N LFSR f k Move literal 12 bit 2nd word 2 1110 1110 OOff kkkk None to FSR f 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR lt 3 0 gt 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C DC Z OV N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD Table Read 2 0000 0000 0000 1000 None TBLRD Table Read with post increment 0000 0000 0000 1001 None TBLRD Table Read with post decrement 0000 00
471. ip microcontrollers It provides hardware implementation of both 8 bit Multiplexed Demultiplexed and 16 bit Memory modes The board includes 2 Mb external Flash memory and 128 Kb SRAM memory as well as serial EEPROM allowing access to the wide range of memory types supported by the PIC18C601 801 27 22 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on board LIN transceivers A PIC16F874 Flash microcontroller serves as the master All three micro controllers are programmed with firmware to provide LIN bus communication 27 23 PICkit 1 Flash Starter Kit A complete development system in a box the PICkit Flash Starter Kit includes a convenient multi section board for programming evaluation and development of 8 14 pin Flash PIC microcontrollers Powered via USB the board operates under a simple Windows GUI The PICkit 1 Starter Kit includes the User s Guide on CD ROM PICkit 1 tutorial software and code for various applications Also included are MPLAB IDE Integrated Development Environment software software and hardware Tips n Tricks for 8 pin Flash PIC Microcontrollers Handbook and a USB interface cable Supports all current 8 14 pin Flash PIC microcontrollers as well as many future planned devices 27 2
472. is 0 the next instruction instruction which is already fetched is which is already fetched is discarded discarded and a NOP is executed and a NOP is executed instead making instead making it a two cycle it a two cycle instruction instruction Ifa is 0 the Access Bank is selected If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the If a is 1 the BSR is used to select the GPR bank default GPR bank default If a is 0 and the extended instruction If a is 0 and the extended instruction set is enabled this instruction operates set is enabled this instruction operates in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing mode whenever f lt 95 SFh See mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Bit Oriented Instructions in Indexed Literal Offset Mode for details Literal Offset Mode for details Words 1 Words 1 Cycles 1 2 Cycles 1 2 Note 3 cycles if skip and followed Note 3 cycles if skip and followed by a 2 word instruction by a 2 word instruction Q Cycle Activity Q Cycle Activity 01 02 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register f Data destination register f Data destination If skip If skip 01 02 Q3 Q4 Q1 Q2 Q3 Q4 No No No No No No No No operation operat
473. is rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register On the other hand results of these operations do not change the value of any flags in the Status register e g Z N OV etc The PLUSW register can be used to implement a form of indexed addressing in the data memory space By manipulating the value in the W register users can reach addresses that are fixed offsets from pointer addresses In some applications this can be used to implement some powerful program control structure such as software stacks inside of data memory 5 4 3 3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases For exam ple using an FSR to point to one of the virtual registers will not result in successful operations As a specific case assume that FSROH FSROL contains FE7h the address of INDF1 Attempts to read the value of INDF1 using INDFO as an operand will return 00h Attempts to write to INDF1 using INDFO as the operand will result in a NOP On the other hand using the virtual registers to write to an FSR pair may not occur as planned In these cases the value will be written to the FSR pair but without any incrementing or decrementing Thus writing to INDF2 or POSTDEC2 will write the same value to the FSR2H FSR2L Since the FSRs are physical registers mapped in the SFR space they can be manipulated through all direct operations
474. is not necessary Thus the current contents of the BSR and the Access RAM bit have no effect on determining the target address 2004 Microchip Technology Inc Preliminary DS39632B page 73 PIC18F2455 2550 4455 4550 5 4 3 2 FSR Registers and POSTINC POSTDEC PREINC and PLUSW In addition to the INDF operand each FSR register pair also has four additional indirect operands Like INDF these are virtual registers that cannot be indirectly read or written to Accessing these registers actually accesses the associated FSR register pair but also performs a specific action on it stored value They are e POSTDEC accesses the FSR value then automatically decrements it by 1 afterwards e POSTINC accesses the FSR value then automatically increments it by 1 afterwards PREINC increments the FSR value by 1 then uses it in the operation e PLUSW adds the signed value of the W register range of 127 to 128 to that of the FSR and uses the new value in the operation In this context accessing an INDF register uses the value in the FSR registers without changing them Sim ilarly accessing a PLUSW register gives the FSR value offset by that in the W register neither value is actually changed in the operation Accessing the other virtual registers changes the value of the FSR registers Operations on the FSRs with POSTDEC POSTINC and PREINC affect the entire register pair that
475. ise it is 0 2 The actual Reset value of POR is determined by the type of device Reset See the notes following this table and Section 4 6 Reset State of Registers for additional information Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown Note 1 It is recommended that the POR bit be set after a Power on Reset has been detected so that subsequent Power on Resets may be detected 2 Brown out Reset is said to have occurred when BOR is 0 and POR is 1 assuming that POR was set to 1 by software immediately after POR DS39632B page 44 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 4 2 Master Clear Reset MCLR The MCLR pin provides a method for triggering an external Reset of the device A Reset is generated by holding the pin low These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses The MCLR pin is not driven low by any internal Resets including the WDT In PIC18F2455 2550 4455 4550 devices the MCLR input can be disabled with the MCLRE configuration bit When MCLR is disabled the pin becomes a digital input See Section 10 5 PORTE TRISE and LATE Registers for more information 4 3 Power on Reset POR A Power on Reset pulse is generated on chip whenever VDD rises above
476. isters 0 Access Flash program or data EEPROM memory Unimplemented Read as FREE Flash Row Erase Enable bit 1 Erase the program memory row addressed by TBLPTR on the next WR command cleared by completion of erase operation 0 Perform write only WRERR Flash Program Data EEPROM Error Flag bit 1 A write operation is prematurely terminated any Reset during self timed programming in normal operation or an improper write attempt 0 The write operation completed Note When a WRERR occurs the EEPGD and CFGS bits are not cleared This allows tracing of the error condition WREN Flash Program Data EEPROM Write Enable bit 1 Allows write cycles to Flash program data EEPROM 0 Inhibits write cycles to Flash program data EEPROM WR Write Control bit 1 Initiates a data EEPROM erase write cycle or a program memory erase cycle or write cycle The operation is self timed and the bit is cleared by hardware once write is complete The WR bit can only be set not cleared in software 0 Write cycle to the EEPROM is complete RD Read Control bit 1 Initiates an EEPROM read Read takes one cycle RD is cleared in hardware The RD bit can only be set not cleared in software RD bit cannot be set when EEPGD 1 or CFGS 1 0 Does not initiate an EEPROM read Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR Bit is set 0 Bit is cleared X Bit is unknown
477. it just as it is in 10 bit Slave Receive mode The first two addresses are followed by a third address sequence which contains the high order bits of the 10 bit address and the R W bit set to 1 After the third address sequence is performed the UA bit is not set the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7 bit Slave Transmit mode see Figure 19 11 DS39632B page 212 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 4 5 the CKP bit When the CKP bit is cleared the SCL output is forced to 0 However setting the CKP bit will not assert the Clock Synchronization and already asserted the SCL line The SCL output will remain low until the CKP bit is set and all other devices on the I C bus have deasserted SCL This ensures that a write to the CKP bit will not violate the SCL output low until the SCL output is already Sa time ireguirement for SCL eee sampled low Therefore the CKP bit will not assert the 9 i SCL line until an external C master device has FIGURE 19 12 CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 1Q2 323 24 21 22 Q3 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 22 Q3 Q4 1 I t l SDA DX gt DX 1 I I SCL se Master device A I CKP N asserts clock 1 Master device _ deasserts clock I
478. it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page PORTE RDPU RE3 12 RE2 REIS REO 54 LATE LATE2 LATE LATEO 54 TRISE TRISE2 TRISE1 TRISEO 54 ADCON1 VCFG1 VCFGO PCFG3 PCFG2 PCFG1 PCFG0 52 CMCON C2OUT CIOUT C2INV C1INV CIS CM2 CM1 CM0 53 SPPCON 3 SPPOWN SPPEN 55 SPPCFG CLKCFG1 CLKCFGO CSEN CLK1EN WS3 WS2 WS1 WS0 55 Legend unimplemented read as 0 Shaded cells are not used by PORTE Note 1 Implemented only when Master Clear functionality is disabled MCLRE configuration bit o 2 RES is the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 3 These registers or bits are unimplemented on 28 pin devices DS39632B page 124 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 11 0 TIMERO MODULE The TimerO module incorporates the following features Software selectable operation as a timer or counter in both 8 bit or 16 bit modes Readable and writable registers Dedicated 8 bit software programmable prescaler Selectable clock source internal or external Edge select for external clock Interrupt on overflow REGISTER 11 1 R W 1 R W 1 R W 1 The TOCON register Register 11 1 controls all aspects of the module s operation including the prescale selection It is both re
479. it during a conversion will abort the current conversion The A D Result register pair will NOT be updated with the partially completed A D conversion sample This means the ADRESH ADRESL registers will continue to contain the value of the last completed conversion or the last 2004 Microchip Technology Inc Preliminary DS39632B page 261 PIC18F2455 2550 4455 4550 21 8 Use of the CCP2 Trigger An A D conversion can be started by the special event trigger of the CCP2 module This requires that the CCP2M3 CCP2M0 bits CCP2CON lt 3 0 gt be pro grammed as 1011 and that the A D module is enabled ADON bit is set When the trigger occurs the GO DONE bit will be set starting the A D acguisition and conversion and the Timer1 or Timer3 counter will be reset to zero Timer1 or Timer3 is reset to automat ically repeat the A D acquisition period with minimal software overhead moving ADRESH ADRESL to the desired location The appropriate analog input chan nel must be selected and the minimum acquisition period is either timed by the user or an appropriate TACQ time selected before the special event trigger sets the GO DONE bit starts a conversion If the A D module is not enabled ADON is cleared the special event trigger will be ignored by the A D module but will still reset the Timer1 or Timer3 counter
480. ites to data EEPROM The CPU can continue to read and write data EEPROM regardless of the protection bit settings CONFIGURATION REGISTER PROTECTION The configuration registers can be write protected The WRTC bit controls protection of the configuration registers In normal execution mode the WRTC bit is readable only WRTC can only be written via ICSP operation or an external programmer 25 5 3 25 6 ID Locations Eight memory locations 200000h 200007h are designated as ID locations where the user can store checksum or other code identification numbers These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program verify The ID locations can be read when the device is code protected 25 7 In Circuit Serial Programming PIC18F2455 2550 4455 4550 microcontrollers can be serially programmed while in the end application circuit This is simply done with two lines for clock and data and three other lines for power ground and the programming voltage This allows customers to manu facture boards with unprogrammed devices and then program the microcontroller just before shipping the product This also allows the most recent firmware or a custom firmware to be programmed 25 8 In Circuit Debugger When the DEBUG configuration bit is programmed to a V the In Circuit Debugger functionality is enabled This function allows simple debugging functions when used wi
481. iting to Flash Program Memory The minimum programming block is 16 words or 32 bytes Word or byte programming is not supported Table writes are used internally to load the holding registers needed to program the Flash memory There are 32 holding registers used by the table writes for programming Since the Table Latch TABLAT is only a single byte the TBLWT instruction may need to be executed 32 times for each programming operation All of the table write operations will essentially be short writes because only the holding registers are written At the end of updating the 32 holding registers the EECON1 register must be written to in order to start the programming operation with a long write FIGURE 6 5 TABLE WRITES TO FLASH PROGRAM MEMORY The long write is necessary for programming the internal Flash Instruction execution is halted while in a long write cycle The long write will be terminated by the internal programming timer The EEPROM on chip timer controls the write time The write erase voltages are generated by an on chip charge pump rated to operate over the voltage range of the device Note The default value of the holding registers on device Resets and after write operations is FFh A write of FFh to a holding register does not modify that byte This means that individual bytes of program memory may be modified provided that the change does not attempt to change any bit from a V to a 1 When modifyin
482. its and is compatible with devices that do not offer programmable acquisition times In either case when the conversion is completed the GO DONE bit is cleared the ADIF flag is set and the A D begins sampling the currently selected channel again If an acquisition time is programmed there is nothing to indicate if the acquisition time has ended or if the conversion has begun 21 3 Selecting the A D Conversion Clock The A D conversion time per bit is defined as TAD The A D conversion requires 11 TAD per 10 bit conversion The source of the A D conversion clock is software selectable There are seven possible options for TAD 2 TOSC 4 TOSC 8 TOSC 16 Tosc 32 TOSC 64 TOSC Internal RC Oscillator For correct A D conversions the A D conversion clock TAD must be as short as possible but greater than the minimum TAD see parameter 130 in Table 28 29 for more information Table 21 1 shows the resultant TAD times derived from the device operating freguencies and the A D clock source selected TABLE 21 1 TAD vs DEVICE OPERATING FREQUENCIES AD Clock Source TAD Operation ADCS2 ADCSO 2 Tosc 000 4 Tosc 100 8 Tosc 001 16 Tosc 101 32 Tosc 010 64 Tosc 110 RC x11 Note 1 The RC source has a typical TAD time of 4 ms 2 The RC source has a typical TAD time of 6 ms Maximum Device Frequency PIC18FXXXX PIC18LFXXXX 4 2 86 MHz 1 43 kHz 5 71 MHz 2 86 MHz 11 43 MHz 5 72 MHz 22
483. ity Q1 Q2 03 Q4 Decode Read Process Write register f Data register f Example MOVWF REG 0 Before Instruction W 4Fh REG FFh After Instruction w 4Fh REG 4Fh 2004 Microchip Technology Inc Preliminary DS39632B page 327 PIC18F2455 2550 4455 4550 MULLW Multiply Literal with W Syntax MULLW k Operands 0 lt k lt 255 Operation W xk gt PRODH PRODL Status Affected None Encoding 0000 1101 kkkk kkkk Description An unsigned multiplication is carried out between the contents of W and the 8 bit literal K The 16 bit result is placed in PRODH PRODL register pair PRODH contains the high byte W is unchanged None of the Status flags are affected Note that neither Overflow nor Carry is possible in this operation A zero result is possible but not detected Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write literal k Data registers PRODH PRODL Example MULLW 0c4h Before Instruction W E2h PRODH PRODL 2 After Instruction W E2h PRODH ADh PRODL 08h MULWF Multiply W with f Syntax MULWF f a Operands 0 lt f lt 255 ae 0 1 Operation W x f gt PRODH PRODL Status Affected None Encoding 0000 oola EFEFEF ffff Description An unsigned multiplication is carried out between the contents of W and the register file location f The 16 bit result is stored in the PRODH PRODL
484. ize 6 Get Configuration Descriptors 7 Get any other Descriptors 8 Set a Configuration The exact enumeration process depends on the host 17 10 6 DESCRIPTORS There are eight different standard descriptor types of which five are most important for this device 17 10 6 1 Device Descriptor The device descriptor provides general information such as manufacturer product number serial number the class of the device and the number of configurations There is only one device descriptor 17 10 6 2 Configuration Descriptor The configuration descriptor provides information on the power requirements of the device and how many different interfaces are supported when in this configu ration There may be more than one configuration for a device i e low power and high power configurations 17 10 6 3 Interface Descriptor The interface descriptor details the number of end points used in this interface as well as the class of the interface There may be more than one interface for a configuration 17 10 6 4 Endpoint Descriptor The endpoint descriptor identifies the transfer type Section 17 10 3 Transfers and direction as well as some other specifics for the endpoint There may be many endpoints in a device and endpoints may be shared in different configurations 17 10 6 5 String Descriptor Many of the previous descriptors reference one or more string descriptors String descriptors provide human readable informa
485. k Syntax ADDWF f d a Operands 0 lt k lt 255 Operands 0 lt f lt 255 Al de 0 1 Operation W k gt W parar WES ae 0 1 Status Affected N OV C DC Z a Operation W f gt dest Encoding 0000 1111 kkkk kkkk n9 Status Affected N OV C DC Z Description The contents of W are added to the Encoding SEBE SEBE 8 bit literal K and the result is placed in neoding 0219 otda W Description Add W to register f If is o the Words 4 result is stored in W If d is Le the result is stored back in register f Cycles 1 default Q Cycle Activity If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the 1 2 3 Q4 P Wri W GPR bank default Decode li Ko s meto If a is o and the extended instruction tera ala set is enabled this instruction operates in Indexed Literal Offset Addressing E ja mode whenever f lt 95 5Fh See example APE roh Section 26 2 3 Byte Oriented and Before Instruction Bit Oriented Instructions in Indexed W 10h Literal Offset Mode for details After Instruction Words 1 W 25h Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example ADDWF REG 0 0 Before Instruction W 17h REG OC2h After Instruction W OD9h REG OC2h Note All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for
486. ke files and information easily available to customers To view the site the user must have access to the Internet and a web browser such as Netscape or Microsoft Internet Explorer Files are also available for FTP download from our FTP site Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL www microchip com The file transfer site is available by using an FTP service to connect to ftp ftp microchip com The web site and file transfer site provide a variety of services Users may download files for the latest Development Tools Data Sheets Application Notes User s Guides Articles and Sample Programs A vari ety of Microchip specific business information is also available including listings of Microchip sales offices distributors and factory representatives Other data available for consideration is e Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips e Device Errata e Job Postings e Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Conferences for products Development Systems technical information and more e Listing of seminars and events SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip s development systems softw
487. l be less than the sum of both specifications DS39632B page 366 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 USB and Related Module Differential Currents AIUSBx AIPLL AIUREG AIUSBX USB Module TBD TBD mA 25 C VDD 3 3V with On Chip Transceiver TBD TBD mA 425 C VDD 5 0V AIPLL 96 MHz PLL TBD TBD TBD 25 C VDD Oscillator Module 2004 Microchip Technology Inc Preliminary DS39632B page 367 PIC18F2455 2550 4455 4550 28 3 DC Characteristics PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Standard Operating Conditions unless otherwise stated DC CHARACTERISTICS Operating ma 40 C lt m lt 85 C for industrial rai Symbol Characteristic Min Max Units Conditions VIL Input Low Voltage I O ports except RC4 RC5 in USB mode DO30 with TTL buffer Vss 0 15 VoD V VDD lt 4 5V D030A 0 8 V 4 5V lt VDD lt 5 5V D031 with Schmitt Trigger buffer Vss 0 2 VDD V RC3 and RC4 Vss 0 3 VDD V DO32 MCLR Vss 0 2 Von V DO32A OSC1 and T1OSI Vss 0 3 VDD V XT HS HSPLL modes D033 OSC1 Vss 02Vpp V EC mode VILU D D Input 0 8 V VoD 4 35V USB suspended VIH Input High Voltage I O ports except RC4 RC5 in USB mode D040 with TTL buffer 0 25 VDD 0 8V VDD V VpD lt 4 5V DO40A 2 0 VDD V 45V lt VpD lt 5 5V DO41 with Schmitt Trigger buffer 0 8 VDD VDD V RC3 and RC4 0 7 VDD VDD V DO42 MCLR 0 8 Vpp VDD V DO42A
488. lable when BOREN lt 1 0 gt 01 otherwise the bit reads as 0 3 These registers and or bits are not implemented on 28 pin devices and are read as o Reset values are shown for 40 44 pin devices individual unimplemented bits should be interpreted as 4 RAGis configured as a port pin based on various primary oscillator modes When the port pin is disabled all of the associated bits read o 5 RE3 is only available as a port pin when the MCLRE configuration bit is clear otherwise the bit reads as 0 6 RC5 and RC4 are only available as port pins when the USB module is disabled UCON lt 3 gt 0 2004 Microchip Technology Inc Preliminary DS39632B page 69 PIC18F2455 2550 4455 4550 TABLE 5 2 REGISTER FILE SUMMARY PIC18F2455 2550 4455 4550 CONTINUED File Name Bit7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR aroun UCFG UTEYE UOEMON UPUEN UTRDIS FSEN PPB1 PPBO 00 0 0000 55 166 UADDR ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDRO 000 oooo 55 170 UCON PPBRST SE0 PKTDIS USBEN RESUME SUSPND 0x0 000 55 164 USTAT ENDP3 ENDP2 ENDP1 ENDPO DIR PPBI xxx xxx 55 168 UEIE BTSEE BTOEE DFN8EE CRC16EE CRCSEE PIDEE o 0 0000 55 181 UEIR BTSEF BTOEF DFN8EF CRCIGEF CRCSEF PIDEF 0 0 0000 55 180 UIE SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 000 0000 55 179
489. lag In receive operation tne BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR It is cleared when the SSPBUF register is read 19 4 11 2 SSPOV Status Flag In receive operation the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception 19 4 11 3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress i e SSPSR is still shifting in a data byte the WCOL bit is set and the contents of the buffer are unchanged the write doesn t occur 2004 Microchip Technology Inc Preliminary DS39632B page 223 PIC18F2455 2550 4455 4550 12CTM MASTER MODE WAVEFORM TRANSMISSION 7 OR 10 BITADDRESS FIGURE 19 21 WH asempsey Aq p 1e9 2 NAS UOHIPUO9 LEIS 18 I N3d s JEMYOS ul U NUM SI dangdSS j NAS USHLUM 4NAdgSS 1 lt 0 gt 1YLSdSS 44 MoV SS91ppy 19 0 J0 0 MH eAEIS 0 SSEJPPY HUISUBIL a ul pejeeto 1dnui lu dSS woy i OJEMIJOS u PIED Y SUNOJ SOIUSS BLEMYOS ul PeJESLI TY i y 3IdSS i 3IdSS 0 spuodsej i Ndo alum ae MOJ PIEY TOS 4 Sa S wJ vej VJ Nf VJ V ne XJ V je e V Je Ns Wl Nef Ne u 108 1 JHILUSUEJ yes Bee ee AVE PUE sseippe 119 4 YUM LELUM ANadSS on ae X foa ta za ea va sa X90 za 0 MOV Viv av X ew Y sy X
490. lator Input Frequency Range DC 50 kHz 48 Tcke2tmrl Delay from External T13CKI Clock Edge to Timer 2 Tosc 7 Tosc Increment DS39632B page 380 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 28 10 CAPTURE COMPARE PWM TIMINGS ALL CCP MODULES CCPx Capture Mode A 4077 CCPx 4 ja Compare or PWM Mode 1 Note Refer to Figure 28 4 for load conditions TABLE 28 14 CAPTURE COMPARE PWM REQUIREMENTS ALL CCP MODULES s Ma Symbol Characteristic Min Max Units Conditions 50 TccL CCPx Input Low No prescaler 0 5 TcY 20 ns Time With PIC18FXXXX 10 ns prescaler PIC18LEXXXX 20 ns VDD 2 0V 51 TccH CCPx Input No prescaler 0 5 Tcy 20 ns High Time With PIC18FXXXX 10 ns prescaler PIC18LEXXXX 20 ns VDD 2 0V 52 TccP CCPx Input Period 3 Toy 40 ns N prescale N value 1 4 or 16 53 TccR CCPx Output Fall Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 2 0V 54 TccF CCPx Output Fall Time PIC18FXXXX 25 ns PIC18LFXXXX 45 ns VDD 2 0V 2004 Microchip Technology Inc Preliminary DS39632B page 381 PIC18F2455 2550 4455 4550 FIGURE 28 11 EXAMPLE SPI MASTER MODE TIMING CKE 0 SDI SCK CKP 1 Note AU Ay Refer to Figure 28 4 for load conditions TABL
491. le Note 1 PORTA lt 6 gt and its direction and latch bits are individually configured as port pins based on various oscillator modes When disabled these bits read as 0 2004 Microchip Technology Inc Preliminary DS39632B page 267 PIC18F2455 2550 4455 4550 NOTES SE rw DS39632B page 268 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 23 0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16 tap resistor ladder network that provides a selectable reference voltage Although its primary purpose is to provide a reference for the analog comparators it may also be used independently of them A block diagram of the module is shown in Figure 23 1 The resistor ladder is segmented to provide two ranges of CVREF values and has a power down function to conserve power when the reference is not being used The module s supply reference can be provided from either device VDD VSS or an external voltage reference 23 1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register Register 23 1 The comparator voltage reference provides two ranges of output voltage each with 16 distinct levels The range to be used is selected by the CVRR bit CVRCON lt 5 gt The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits CVR3 CVRO with one range offering finer
492. le SPI Mode Reguirements Slave Mode CKE 1 385 External Clock Requirements 376 IC Bus Data Requirements Slave Mode 387 C Bus Start Stop Bits Requirements 386 Master SSP IC Bus Data Requirements 389 Master SSP IC Bus Start Stop Bits Requirements ssssesesessineserrerersrrereerenrreasrurrensns 388 PEL CIOCK 2 raddi aba ha 377 Reset Watchdog Timer Oscillator Start up Timer Power up Timer and Brown out Reset Requirements 379 Streaming Parallel Port Requirements PIC18F 4455 4550 392 Timer0 and Timer1 External Clock Requirements 380 USB Full Speed Requirements 391 USB Low Speed Requirements 391 Top of Stack Access sssssoeseesseeesesssrrsssrentseeresrnssrennesrnnee 58 TQFP Packages and Special Features 299 T TESZ ua Lu 341 Two Speed Start up 279 293 Two Word Instructions Example Cases u n sa an nu assasi 62 TXSTA Register BRGH Bits nen kein rh 237 U Universal Serial Bus Address Register UADDR 170 and Streaming Parallel Port za Associated Registers 183 Buffer Descriptor Table
493. le bit in the UEIE register All of the USB error flags are ORed together to generate the USB Error Interrupt Flag UERRIF at the top level of the interrupt logic REGISTER 17 9 UEIR USB ERROR INTERRUPT STATUS REGISTER R C 0 U 0 U 0 R C 0 R C 0 R C 0 R C 0 R C 0 BTSEF BTOEF DFNBEF CRCIGEF CRC5EF PIDEF bit 7 bit 0 bit 7 BTSEF Bit Stuff Error Flag bit 1 A bit stuff error has been detected 0 No bit stuff error bit 6 5 Unimplemented Read as 0 bit 4 BTOEF Bus Turnaround Time out Error Flag bit 1 Bus turnaround time out has occurred more than 16 bit times of Idle from previous EOP elapsed 0 No bus turnaround time out bit 3 DFNBEF Data Field Size Error Flag bit 1 The data field was not an integral number of bytes 0 The data field was an integral number of bytes bit 2 CRCIGEF CRC16 Failure Flag bit 1 The CRC16 failed 0 The CRC16 passed bit 1 CRCSEF CRC5 Host Error Flag bit 1 The token packet was rejected due to a CRC5 error 0 The token packet was accepted bit 0 PIDEF PID Check Failure Flag bit 1 PID check failed 0 PID check passed Legend R Readable bit C Clearable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 180 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 5 4 USB ERROR INTERRUPT ENABLE As with t
494. le control to the transceiver Additional information on configuring USB options is provided in Section 17 2 2 2 External Transceiver When enabling peripheral functions on PORTC pins other than RC4 and RC5 care should be taken in defin ing the TRIS bits Some peripherals override the TRIS bit to make a pin an output while other peripherals override the TRIS bit to make a pin an input The user should refer to the corresponding peripheral section for the correct TRIS bit settings Note On a Power on Reset these pins are configured as digital inputs The contents of the TRISC register are affected by peripheral overrides Reading TRISC always returns the current contents even though a peripheral device may be overriding one or more of the pins EXAMPLE 10 3 INITIALIZING PORTC Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction RC lt 5 0 gt as outputs RC lt 7 6 gt as inputs CLRF PORTC CLRF LATC MOVLW 07h MOVWF TRISC 2004 Microchip Technology Inc Preliminary DS39632B page 117 PIC18F2455 2550 4455 4550 TABLE 10 5 PORTC I O SUMMARY Pin Function in VO 1 0 Type Description RC0 T1OSO RC0 0 OUT DIG LATC lt 0 gt data output TIS
495. le options are 1 2 1 3 1 4 and 1 6 of the PLL output The HSPLL ECPLL and ECPIO modes make use of the HS mode oscillator for frequencies up to 48 MHz The prescaler divides the oscillator input by up to 12 to produce the 4 MHz drive for the PLL The XTPLL mode can only use an input frequency of 4 MHz which drives the PLL directly FIGURE 2 6 PLL BLOCK DIAGRAM HS MODE HS EC ECIO XT Oscillator Enable 1 PLL Enable from CONFIG1H Register Phase DT Oscillator Fin Comparator OSC ae Four x rescaler Y Loop Filter Y 24 lt VCO SYSCLK D z DS39632B page 26 Preliminary 2004 Microchip Technology lnc PIC18F2455 2550 4455 4550 2 2 5 INTERNAL OSCILLATOR BLOCK The PIC18F2455 2550 4455 4550 devices include an internal oscillator block which generates two different clock signals either can be used as the microcontroller s clock source If the USB peripheral is not used the internal oscillator may eliminate the need for external oscillator circuits on the OSCI and or OSC2 pins The main output INTOSC is an 8 MHz clock source which can be used to directly drive the device clock It also drives the INTOSC postscaler which can provide a range of clock freguencies from 31 kHz to 4 MHz The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected The oth
496. le still executing code It works well for user applications which are not highly timing sensitive or do not reguire high speed clocks at all times If the primary clock source is the internal oscillator block either INTRC or INTOSC there are no distin guishable differences between PRI RUN and RC_RUN modes during execution However a clock switch delay will occur during entry to and exit from RC_RUN mode Therefore if the primary clock source is the internal oscillator block the use of RC RUN mode is not recommended This mode is entered by setting SCS1 to 1 Although it is ignored it is recommended that SCSO also be cleared this is to maintain software compatibility with future devices When the clock source is switched to the INTOSC multiplexer see Figure 3 3 the primary oscillator is shut down and the OSTS bit is cleared The IRCF bits may be modified at any time to immediately change the clock speed Note Caution should be used when modifying a single IRCF bit If VDD is less than 3V it is possible to select a higher clock speed than is supported by the low VDD Improper device operation may result if the VDD FOSC specifications are violated 2004 Microchip Technology Inc Preliminary DS39632B page 37 PIC18F2455 2550 4455 4550 If the IRCF bits and the INTSRC bit are all clear the INTOSC output is not enabled and the IOFS bit will remain clear there will be no indication of the curre
497. le with the standard CCP module 2004 Microchip Technology Inc Preliminary DS39632B page 161 PIC18F2455 2550 4455 4550 TABLE 16 3 REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3 Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 RCON IPEN SBOREN RI TO PD POR BOR 52 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMRBIP CCP2IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRBIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMRSIE CCP2IE 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 54 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 54 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISDO 54 TMRIL Timer1 Register Low Byte 52 TMR1H Timer1 Register High Byte 52 TICON RD16 TIRUN TICKPS1 TICKPSO TIOSCEN TISYNC TMRICS TMRION 52 TMR2 Timer2 Module Register 52 T2CON T2OUTPS3 T2OUTPS2 T2OUTPS1 TZOUTPSO TMR2ON T2CKPS1 T2CKPSO 52 PR2 Timer2 Period Register 52 TMR3L Timer3 Register Low Byte 53 TMR3H Timer3 Register High Byte 53 T3CON RD16 T3CCP2 T3C
498. learing bit RBPU INTCON2 lt 7 gt The weak pull up is automatically turned off when the port pin is configured as an output The pull ups are disabled on a Power on Reset Note On a Power on Reset RB4 RBO are configured as analog inputs by default and read as 0 RB7 RB5 are configured as digital inputs By programming the configuration bit PBADEN CONFIG3H lt 1 gt RB4 RBO will alternatively be configured as digital inputs on POR Four of the PORTB pins RB7 RB4 have an interrupt on change feature Only pins configured as inputs can cause this interrupt to occur any RB7 RB4 pin configured as an output is excluded from the interrupt on change comparison The pins are compared with the old value latched on the last read of PORTB The mismatch outputs of RB7 RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit RBIF INTCON lt 0 gt The interrupt on change can be used to wake the device from Sleep The user in the Interrupt Service Routine can clear the interrupt in the following manner a Any read or write of PORTB except with the MOVFF ANY PORTB instruction This will end the mismatch condition b Clear flag bit RBIF A mismatch condition will continue to set flag bit RBIF Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared The interrupt on change feature is recommended for wake up on key depression operation and operati
499. lement It indicates an overflow of the 7 bit magnitude which causes the sign bit bit 7 to change state 1 Overflow occurred for signed arithmetic in this arithmetic operation 0 No overflow occurred bit 2 Z Zero bit 1 The result of an arithmetic or logic operation is zero 0 The result of an arithmetic or logic operation is not zero bit 1 DC Digit Carry Borrow bit For ADDWF ADDLW SUBLW and SUBWF instructions 1 A carry out from the 4th low order bit of the result occurred 0 No carry out from the 4th low order bit of the result Note For Borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either bit 4 or bit 3 of the source register bit 0 C Carry Borrow bit For ADDWF ADDLW SUBLW and SUBWF instructions 1 A carry out from the Most Significant bit of the result occurred 0 No carry out from the Most Significant bit of the result occurred Note For Borrow the polarity is reversed A subtraction is executed by adding the two s complement of the second operand For rotate RRF RLF instructions this bit is loaded with either the high or low order bit of the source register Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc
500. lete a full PWM cycle before configuring the PWM pins as outputs The com pletion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins PWM AUTO SHUTDOWN PRSEN 1 AUTO RESTART ENABLED 14 PWM Period b e PWM Period PWM Period PWM Activity a Duty Cycle 3 gt Shutdown Event Dead Time M a Dead Time lt t Duty Cycle 14 Duty Cycle Dead Time ak ECCPASE bit FIGURE 16 11 PWM AUTO SHUTDOWN PRSEN 0 AUTO RESTART DISABLED ma PWM Period lt PWM Period p PWM Period PWM Activity Duty Cycle gt gt Dead Time A a Dead Time s Dead Time LDuty Cycle lt hLuty Cycle gt i Shutdown Event ECCPASE bit ECCPASE Cleared by Firmware DS39632B page 160 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 16 4 9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation 1 Configure the PWM pins PIA and P1B and P1C and P1D if used as inputs by setting the corresponding TRIS bits 2 Set the PWM period by loading the PR2 register 3 If Auto Shutdown is required do the following e Disable Auto S
501. log Analog input 7 OESPP O SPP output enable output RE3 See MCLR VPP RE3 pin Vss 12 31 6 30 6 29 P Ground reference for logic and I O pins 31 VDD 11 32 7 8 7 28 P Positive supply for logic and I O pins 28 29 VUSB 18 37 37 O lnternal USB 3 3V voltage regulator output NC ICCK ICPGC 12 No Connect or dedicated ICD ICSP port clock ICCK O ST In Circuit Debugger clock ICPGC O ST ICSP programming clock NC ICDT ICPGD 13 No Connect or dedicated ICD ICSP port clock ICDT O ST In Circuit Debugger data ICPGD O ST ICSP programming data NC ICRST ICVPP 33 No Connect or dedicated ICD ICSP port Reset ICRST Master Clear Reset input ICVPP P Programming voltage input NC ICPORTS 34 P No Connect or 28 pin device emulation 9 ICPORTS Enable 28 pin device emulation when connected to Vss NC 13 No Connect Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared 2 Default assignment for CCP2 when CCP2MX configuration bit is set 3 These pins are No Connect unless the ICPRT configuration bit is set For NC ICPORTS the pin is No Connect unless ICPRT is set and the DEBUG configuration bit is cleared 2004 Microchip Technolog
502. logy Inc Preliminary DS39632B page 217 PIC18F2455 2550 4455 4550 19 4 6 1 I C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions A transfer is ended with a Stop condition or with a Repeated Start condition Since the Repeated Start condition is also the beginning of the next serial transfer the IC bus will not be released In Master Transmitter mode serial data is output through SDA while SCL outputs the serial clock The first byte transmitted contains the slave address of the receiving device seven bits and the Read Write R W bit In this case the R W bit will be logic o Serial data is transmitted eight bits at a time After each byte is transmitted an Acknowledge bit is received Start and Stop conditions are output to indicate the beginning and the end of a serial transfer In Master Receive mode the first byte transmitted con tains the slave address of the transmitting device 7 bits and the R W bit In this case the R W bit will be logic 1 Thus the first byte transmitted is a 7 bit slave address followed by a 1 to indicate receive bit Serial data is received via SDA while SCL outputs the serial clock Serial data is received eight bits at a time After each byte is received an Acknowledge bit is transmit ted Start and Stop conditions indicate the beginning and end of transmission The Baud Rate Generator used for the SP
503. logy Inc Preliminary DS39632B page 173 PIC18F2455 2550 4455 4550 17 41 3 BDNSTAT Register SIE Mode When the BD and its buffer are owned by the SIE most of the bits in BDnSTAT take on a different meaning The configuration is shown in Register 17 6 Once UOWN is set any data or control settings previously written there by the user will be overwritten with data from the SIE The BDnSTAT register is updated by the SIE with the token Packet Identifier PID which is stored in BDnSTAT lt 5 3 gt The transfer count in the corresponding BDnCNT register is updated values that overflow the 8 bit register carry over to the two most significant digits of the count stored in BDnSTAT lt 1 0 gt 17 4 2 BD BYTE COUNT The byte count represents the total number of bytes that will be transmitted during an IN transfer After an IN transfer the SIE will return the number of bytes sent to the host For an OUT transfer the byte count represents the maximum number of bytes that can be received and stored in USB RAM After an OUT transfer the SIE will return the actual number of bytes received If the number of bytes received exceeds the corresponding byte count the data packet will be rejected and a NAK handshake will be generated When this happens the byte count will not be updated REGISTER 17 6 The 10 bit byte count is distributed over two registers The lower 8 bits of the count reside in the BDnCNT register The upper two bi
504. logy Inc Preliminary DS39632B page 379 PIC18F2455 2550 4455 4550 FIGURE 28 9 TIMERO AND TIMER1 EXTERNAL CLOCK TIMINGS TOCKI N fi q 40 gt lt 41 u lt 42 gt T1OSO T13CKI A lt 45 P a 46 gt I I lt 47 48 Note Refer to Figure 28 4 for load conditions TABLE 28 13 TIMERO AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Gu Symbol Characteristic Min Max Units Conditions 40 TtOH TOCKI High Pulse Width No prescaler 0 5 Tcy 20 ns With prescaler 10 ns 41 TtOL TOCKI Low Pulse Width No prescaler 0 5 Tcy 20 ns With prescaler 10 ns 42 TtoP TOCKI Period No prescaler Toy 10 ns With prescaler Greater of ns N prescale 20 ns or value Tcy 40 N 1 2 4 256 45 TtiH T13CKI High Synchronous no prescaler 0 5 TCY 20 ns Time Synchronous PICI8FXXXX 10 ns with prescaler PIC 18LFXXXX 25 ns vpp 2 0V Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns VDD 2 0V 46 TUL T13CKI Low Synchronous no prescaler 0 5 TCY 5 ns Time Synchronous PICI8FXXXX 10 ns with prescaler PIC18LFXXXX 25 ns vpp 2 0V Asynchronous PIC18FXXXX 30 ns PIC18LFXXXX 50 ns VDD 2 0V 47 TtiP T13CKI Input Synchronous Greater of ns N prescale Period 20 ns or value 1 2 4 8 Tcy 40 N Asynchronous 60 am ns Ft1 T13CKI Oscil
505. low byte has become invalid due to a rollover between reads A write to the high byte of Timer3 must also take place through the TMR3H Buffer register The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once The high byte of Timer3 is not directly readable or writable in this mode All reads and writes must take place through the Timer3 High Byte Buffer register Writes to TMR3H do not clear the Timer3 prescaler The prescaler is only cleared on writes to TMR3 L 14 3 Using the Timer1 Oscillator as the Timer3 Clock Source The Timeri internal oscillator may be used as the clock source for Timer3 The Timer1 oscillator is enabled by setting the TIOSCEN T1CON lt 3 gt bit To use it as the Timer3 clock source the TMR3CS bit must also be set As previously noted this also configures Timer3 to increment on every rising edge of the oscillator source The Timer1 oscillator is described in Section 12 0 Timer1 Module 14 4 Timer Interrupt The TMR3 register pair TMR3H TMR3L increments from 0000h to FFFFh and overflows to 0000h The Timers interrupt if enabled is generated on overflow and is latched in interrupt flag bit TMRSIF PIR2 lt 1 gt This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit TMR3IE PIE2 lt 1 gt 14 5 Resetting Timer3 Using the CCP S
506. lues on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRI1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 TXREG EUSART Transmit Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented locations read as 0 Shaded cells are not used for asynchronous transmission Note 1 Reserved in 28 pin devices always maintain these bits clear 2004 Microchip Technology Inc Preliminary DS39632B page 243 PIC18F2455 2550 4455 4550 20 2 2 EUSART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 20 6 The data is received on the RX pin and drives the data recovery block The data recovery block is actually a high speed shifter operating at x16 times the baud rate whereas the main receive serial shifter operates at the bit rate or at Fosc This mode would typically be used in RS 232 systems To set up an Asynchronous Reception 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate 2 Enable the asynchr
507. ly 2 ms and follows the oscillator start up time out 4 5 4 TIME OUT SEQUENCE On power up the time out sequence is as follows 1 After the POR condition has cleared PWRT time out is invoked if enabled 2 Then the OST is activated The total time out will vary based on oscillator configu ration and the status of the PWRT Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 and Figure 4 7 all depict time out seguences on power up with the Power up Timer enabled and the device operating in HS Oscillator mode Figures 4 3 through 4 6 also apply to devices operating in XT mode For devices in RC mode and with the PWRT disabled on the other hand there will be no time out at all Since the time outs occur from the POR pulse if MCLR is kept low long enough all time outs will expire Bring ing MCLR high will begin execution immediately Figure 4 5 This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel TABLE 4 2 TIME OUT IN VARIOUS SITUATIONS Oscillator Power up and Brown out Exit from Configuration PWRTEN 0 PWRTEN 1 Power Managed Mode HS XT 66 ms 1024 Tosc 1024 Tosc 1024 Tosc HSPLL XTPLL 66 ms 1024 Tosc 2 ms 1024 Tosc 2 ms 1024 Tosc 2 ms EC ECIO 66 msl ECPLL ECPIO 66 ms 2 msl 2 msl 2 msl INTIO INTCKO 66 msl INTHS INTXT 66 ms 1024 Tosc 1024 Tosc 1024 Tosc
508. m Memory Table Pointer High Byte TBLPTR lt 15 8 gt 0000 0000 51 82 TBLPTRL Program Memory Table Pointer Low Byte TBLPTR lt 7 0 gt 0000 0000 51 82 TABLAT Program Memory Table Latch 0000 0000 51 82 PRODH Product Register High Byte xxxx xxxx 51 95 PRODL Product Register Low Byte xxxx xxxx 51 95 INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 0000 000x 51 99 INTCON2 RBPU INTEDGO INTEDG1 INTEDG2 TMROIP RBIP 1111 1 1 51 100 INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 11 0 0 00 51 101 INDFO Uses contents of FSRO to address data memory value of FSRO not changed not a physical register NA 51 73 POSTINCO Uses contents of FSRO to address data memory value of FSRO post incremented not a physical register NA 51 74 POSTDECO Uses contents of FSRO to address data memory value of FSRO post decremented not a physical register NA 51 74 PREINCO Uses contents of FSRO to address data memory value of FSRO pre incremented not a physical register NA 51 74 PLUSWO Uses contents of FSRO to address data memory value of FSRO pre incremented not a physical register N A 51 74 value of FSRO offset by W FSROH Indirect Data Memory Address Pointer 0 High 0000 51 73 FSROL Indirect Data Memory Address Pointer 0 Low Byte XXXX xxxx 51 73 WREG Working Register XXXX XXXX 51 INDF1 Uses contents of FSR1 to address data memory value of FSR1 not changed not a physical regi
509. match CCPIF bit is set CCP pin reflects I O state 1011 Compare mode trigger special event reset timer start A D conversion on CCP2 match CCPIF bit is set 11xx PWM mode Legend R Readable bit W Writable bit n Value at POR 1 Bit is set U Unimplemented bit read as 0 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 141 PIC18F2455 2550 4455 4550 15 1 CCP Module Configuration Each Capture Compare PWM module is associated with a control register generically CCPxCON and a data register CCPRx The data register in turn is comprised of two 8 bit registers CCPRxL low byte and CCPRxH high byte All registers are both readable and writable 15 1 1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1 2 or 3 depending on the mode selected Timer1 and Timer3 are available to modules in Capture or Compare modes while Timer2 is available for modules in PWM mode The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the T3CON register Register 14 1 Both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode Capture Compare or PWM at the same time The interactions between the two modules are summarized in Figure 15 2 In Timer1 in Asynchronous Counter mode the capt
510. me way as the legacy ICSP ICD port on RB6 RB7 Table 25 5 identifies the functionally equivalent pins for ICSP and ICD purposes TABLE 25 4 DEBUGGER RESOURCES I O pins RB6 RB7 Stack 2 levels Program Memory 512 bytes Data Memory 10 bytes TABLE 25 5 EQUIVALENT PINS FOR LEGACY AND DEDICATED ICD ICSP PORTS Pin Name Pin Pin F Legacy Dedicated Type in Function Port Port MCLR VPP NC ICRST P Device Reset and RE3 ICVPP Programming Enable RBG KBI2 NC ICCK Serial Clock PGC ICPGC RB7 KBI3 NC ICDT O Serial Data PGD ICPGD Legend Input O Output P Power 2004 Microchip Technology Inc Preliminary DS39632B page 299 PIC18F2455 2550 4455 4550 Even when the dedicated port is enabled the ICSP and ICD functions remain available through the legacy port When VIH is seen on the MCLR VPP RE3 pin the state of the ICRST ICVPP pin is ignored Note 1 The ICPORT configuration bit can only be programmed through the default ICSP port 2 The ICPORT configuration bit must be maintained clear for all 28 pin and 40 pin devices otherwise unexpected operation may occur 25 9 2 28 PIN EMULATION PIC18F 4455 4550 devices in 44 pin TQFP packages also have the ability to change their configuration under external control for debugging purposes This allows the device to behave as if it were a PIC18F2455 2550 28 pin dev
511. menti z usu non 27 MSSP INTHS INTXT INTCKO and ACK Pulse koni ask Ra Sun ne 206 207 INTIO Modes nainitan bine ese bara Control Registers general 0 0 eee 193 OSCTUNE Register PC Mode See C Mode Internal RC Oscillator Module Overview nn nn nnnnnnnnu 193 Use with WDT mr 291 SPI Master Slave Connection 197 Interrupt Sources a 279 SPI Mode See SPI Mode A D Conversion Complete s 257 SSPBUF Liane meet 198 Capture Complete CCP 143 OSPS i ri 198 Compare Complete CCP 144 MU RE E EA E AA nr 328 Interrupt on Change RB7 RB4 114 MULWEB aaa AO E 328 INTn Pin N PORTB Interrupt on Change Re TMRO ere NEGE ae A 329 TMRO Overflow NOD En e a oe A 329 TMR1 Overflow O TME OV 187189 Opcode Field Descriptions 302 Interrupts Oscillator Configuration 23 PAP TE ESTE ia tia aie cee nase ince oe 98 EB u SADR OR Ah A bua sa 23 USE o s tan sk a aaye 97 ECIO 28 Interrupts Flag Bits are Interrupt on Change RB7 RB4 HS se 33 Flagi RBIF Bit xs Su NOU 114 HSPLL asa u 53 INTOSC Frequency Drift 27 INTCKO vaj 53 INTOSC INTRC See Internal Oscillator Block AA ue fet EN sienne Nu tab abd dieu heaton O Witenes 304 Internal Oscillator Block 27 2004 Microchip Tec
512. mode If an oscillator failure occurs during power managed operation the subsequent events depend on whether or not the oscillator failure interrupt is enabled If enabled OSCFIF 1 code execution will be clocked by the INTOSC multiplexer An automatic transition back to the failed clock source will not occur If the interrupt is disabled subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source 25 4 4 POR OR WAKE UP FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power on Reset POR or Low Power Sleep mode When the primary device clock is either EC or INTRC modes monitoring can begin immediately following these events For oscillator modes involving a crystal or resonator HS HSPLL or XT the situation is somewhat different Since the oscillator may require a start up time con siderably longer than the FCSM sample clock time a false clock failure may be detected To prevent this the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable the OST and PLL timers have timed out This is identical to Two Speed Start up mode Once the primary clock is stable the INTRC returns to its role as the FSCM source Note The same logic that prevents false oscilla tor failure interrupts on POR or wake from Sleep will also prevent the
513. n Stack Full Underflow Resets status Registr srecni irsini rain aa Streaming Parallel Port a Associated Registers 2 Clocking Data aa Configuration sise air ina Internal Pull ups Interrupts z Microcontroller Control Setup 190 Reading from Microcontroller Mode 191 Transfer of Data Between USB SIE and SPP diagram 190 USB Control Setup 190 Wait States 188 Writing to Microcontroller Mode 190 SUBESR ial latte la Va 347 SUBFWB SUBLW SUBULNK S BWE u aaa paynu paq A pah 337 SUBWEB 338 SWAPE suasana aa ll 338 T TOCON Register PSA Bit 127 TOCS Bit uu ara 126 TOPS2 TOPSO BIS Ju Na 127 MOS EIB itt t A spl 126 Table Pointer Operations table 82 DS39632B page 416 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TBLRD TBLWT i Time out in Various Situations table 47 MMEO ner r NU 125 16 Bit Mode Timer Reads and Writes W Associated Registers 127 Clock Source Edge Select TOSE Bit 126 Clock Source Select TOCS Bit 126 Operation
514. n the U S A Analog for the Digital Age Application Maestro dsPICDEM dsPICDEM net dsPICworks ECAN ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC MPASM MPLIB MPLINK MPSIM PICkit PICDEM PICDEM net PICLAB PICtail PowerCal Powerlnfo PowerMate PowerTool rfLAB rfPICDEM Select Mode Smart Serial SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is aservice mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2004 Microchip Technology Incorporated Printed in the U S A All Rights Reserved a Printed on recycled paper Microchip received ISO TS 16949 2002 quality system certification for its worldwide headquarters design and wafer fabrication facilities in Chandler and Tempe Arizona and Mountain View California in October 2003 The Company s quality system processes and procedures are for its PICmicro 8 bit MCUs KEELOG code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is ISO 9001 2000 certified DS39632B page ii Preliminary 2004 Microchip Technology Inc MICROCHIP PIC18F2455 2550 4455 4550 28 40 44 Pin High Performance Enhanced Flash USB Microcontrollers
515. n this address is used all devices should in theory respond with an Acknowledge The general call address is one of eight addresses reserved for specific purposes by the C protocol It consists of all o s with R W 0 The general call address is recognized when the Gen eral Call Enable bit GCEN is enabled SSPCON2 lt 7 gt set Following a Start bit detect 8 bits are shifted into the SSPSR and the address is compared against the SSPADD It is also compared to the general call address and fixed in hardware FIGURE 19 15 If the general call address matches the SSPSR is transferred to the SSPBUF the BF flag bit is set eighth bit and on the falling edge of the ninth bit ACK bit the SSPIF interrupt flag bit is set When the interrupt is serviced the source for the interrupt can be checked by reading the contents of the SSPBUF The value can be used to determine if the address was device specific or a general call address In 10 bit mode the SSPADD is required to be updated for the second half of the address to match and the UA bit is set SSPSTAT lt 1 gt If the general call address is sampled when the GCEN bit is set while the slave is configured in 10 bit Address mode then the second half of the address is not necessary the UA bit will not be set and the slave will begin receiving data after the Acknowledge Figure 19 15 SLAVE MODE GENERAL CALL ADDRESS SEGUENCE 7 OR 10 BITADDRESS MODE General
516. nable the CCP1 P1A P1B P1C and or P1D pin outputs by clearing the respective TRIS bits Clear the ECCPASE bit ECCP1AS lt 7 gt 16 4 10 OPERATION INPOWER MANAGED MODES In Sleep mode all clock sources are disabled Timer2 will not increment and the state of the module will not change If the ECCP pin is driving a value it will continue to drive that value When the device wakes up it will continue from this state If Two Speed Start ups are enabled the initial start up frequency from INTOSC and the postscaler may not be stable immediately In PRI IDLE mode the primary clock will continue to clock the ECCP module without change In all other power managed modes the selected power managed mode clock will clock Timer2 Other power managed mode clocks will most likely be different than the primary clock frequency 16 4 10 1 Operation with Fail Safe Clock Monitor If the Fail Safe Clock Monitor is enabled a clock failure will force the device into the Power Managed RC_RUN mode and the OSCFIF bit PIR2 lt 7 gt will be set The ECCP will then be clocked from the internal oscillator clock source which may have a different clock frequency than the primary clock See the previous section for additional details 16 4 11 EFFECTS OF A RESET Both Power on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states This forces the Enhanced CCP module to reset to a state compatib
517. nally The SPP is enabled as a USB endpoint port through the associated endpoint buffer descriptor The endpoint must be enabled as follows 1 Set BDnADRL BDnADRH to point to FFFFh 2 Set the KEN bit BDnSTAT lt 5 gt to let SIE keep control of the buffer 3 Set the INCDIS bit BDnSTAT lt 4 gt to disable automatic address increment Refer to Section 18 0 Streaming Parallel Port for more information about the SPP Note 1 If an endpoint is configured to use the SPP the SPP module must also be configured to use the USB module Otherwise unexpected operation may occur 2 In addition if an endpoint is configured to use the SPP the data transfer type of that endpoint must be isochronous only DS39632B page 182 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 8 Oscillator 17 9 USB Firmware and Drivers The USB module has specific clock requirements For Microchip provides a number of application specific full speed operation the clock source must be 48 MHz resources such as USB firmware and driver support Even so the microcontroller core and other peripherals Refer to www microchip com for the latest firmware and are not required to run at that clock speed or even from driver support the same clock source Available clocking options are described in detail in Section 2 3 Oscillator Settings for USB TABLE 17 6 REGISTERS ASSOCIATED WITH USB MODULE OPERAT
518. nd SCL pins deasserted When the SDA pin is sampled high the Baud Rate Generator is loaded from SSPADD lt 6 0 gt and counts down to 0 If the SCL pin is sampled low while SDA is high a bus collision occurs because it is assumed that another master is attempting to drive a data 1 during the Start condition FIGURE 19 26 If the SDA pin is sampled low during this count the BRG is reset and the SDA line is asserted early Figure 19 28 If however a 1 is sampled on the SDA pin the SDA pin is asserted low at the end of the BRG count The Baud Rate Generator is then reloaded and counts down to 0 and during this time if the SCL pins are sampled as 0 a bus collision does not occur At the end of the BRG count the SCL pin is asserted low Note The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time Therefore one master will always assert SDA before the other This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition If the address is the same arbitration must be allowed to continue into the data portion Repeated Start or Stop conditions BUS COLLISION DURING START CONDITION SDA ONLY Set BCLIF SDA 0 SCL 1 SDA goes low before the SEN bit is set S bit and SSPIF set because SS a
519. nd calibration automatic wake up on Sync Break reception and 12 bit Break character transmit These features make it ideally suited for use in Local Interconnect Network bus LIN bus systems The EUSART can be configured in the following modes Asynchronous full duplex with Auto wake up on character reception Auto baud calibration 12 bit Break character transmission e Synchronous Master half duplex with selectable clock polarity Synchronous Slave half duplex with selectable clock polarity The pins of the Enhanced USART are multiplexed with PORTC In order to configure RC6 TX CK and RC7 RX DT SDO as a USART bit SPEN RCSTA lt 7 gt must be set 1 bit TRISC lt 7 gt must be set 1 bit TRISC lt 6 gt must be cleared 0 for Asynchronous and Synchronous Master modes or set 1 for Synchronous Slave mode Note The EUSART control will automatically reconfigure the pin from input to output as needed The operation of the Enhanced USART module is controlled through three registers Transmit Status and Control TXSTA e Receive Status and Control RCSTA Baud Rate Control BAUDCON These are detailed on the following pages in Register 20 1 Register 20 2 and Register 20 3 respectively 2004 Microchip Technology Inc Preliminary DS39632B page 233 PIC18F2455 2550 4455 4550 REGISTER 20 1 TXSTA TRANSMIT STATUS AND CONTROL REGISTER R W 0 R W 0 R W 0 R W
520. nd the set point may not be detected during this interval Refer to Figure 24 2 or Figure 24 3 LOW VOLTAGE DETECT OPERATION VDIRMAG 0 CASE 1 HLVDIF may not be set HLVDIF Enable HLVD I I IRVST TIRVST CASE 2 Internal Reference is stable HLVDIF cleared in software VDD ani VHLVD HLVDIF Enable HLVD I I IRVST TIRVST Internal Reference is stable 1 HLVDIF cleared in software HLVDIF cleared in software HLVDIF remains set since HLVD condition still exists 2004 Microchip Technology Inc Preliminary DS39632B page 275 PIC18F2455 2550 4455 4550 FIGURE 24 3 HIGH VOLTAGE DETECT OPERATION VDIRMAG 1 CASE 1 HLVDIF may not be set a A a cay ear 2d ya x m EAEN VHLVD VDD oe an I HLVDIF k Enable HLVD I IRVST le TIRVST A HLVDIF cleared in software Internal Reference is stable CASE 2 A a VHLVD VDD HLVDIF L Enable HLVD IRVST Le TIRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software HLVDIF remains set since HLVD condition still exists 24 5 Applications In many applications the ability to detect a drop below or rise above a particular threshold is
521. nditions 375 AC Characteristics Internal RC Accuracy a 377 Access Bank Mapping with Indexed Literal Offset Mode 77 AGKSTAT eee dain wh en 223 ACKSTAT Status Flag a 223 ADCONO Register vs GO DONE Bit uu L ae ee ADCONI Register aa ADCON2 Register m ADDF SR ega nn nn la au Na ADDLW srst ANO DAL sta ras en ADDULNK a ADDWE sine aii a ADRESH Register ADRESL Register sssssssesssernssrerrisererressnrrnrresrrnsenes Analog to Digital Converter See A D and BSR siasii vata Rue a ha ka 77 Assembler MPASM Assembler Auto Wake up on Sync Break Character Bank Select Register BSR 63 Baud Rate Generator 2004 Microchip Technology Inc Preliminary BF Status Fla izo ri ih 223 Block Diagrams AID ice dit akak Sieh rks Mook nde bk Mobi dh dice thn lhcb A Analog Input Model Baud Rate Generator eseseissieeriesrrierrirerreernes Capture Mode Operation Comparator Analog Input Model 267 Comparator I O Operating Modes Diagram aa a D NA 264 Comparator Output ssseesseessieesresriserrsrrrnserrssrnne 266 Comparator Voltage Reference 270 Compare Mode Operation
522. ne transfer while the SIE processes additional endpoints Figure 17 4 When the SIE completes using a buffer for reading or writing data it updates the USTAT register If another USB transfer is performed before a transaction complete interrupt is serviced the SIE will store the status of the next transfer into the status FIFO REGISTER 17 3 USTAT USB STATUS REGISTER Gst 2 REGsGsr is present9 Gsr ia1 1 t 0E54 n 1 0 c1p2t 3l Clearing the transfer complete flag bit TRNIF causes the SIE to advance the FIFO If the next data in the FIFO holding register is valid the SIE will immediately reassert the interrupt If no additional data is present TRNIF will remain clear USTAT data will no longer be reliable FIGURE 17 4 USTAT FIFO DS39632B page 168 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 17 2 4 USB ENDPOINT CONTROL Each of the 16 possible bidirectional endpoints has its own independent control register UEPn where n rep resents the endpoint number Each register has an identical complement of control bits The prototype is shown in Register 17 4 The EPHSHK bit UEPn lt 4 gt controls handshaking for the endpoint setting this bit enables USB handshaking Typically this bit is always set except when using isochronous endpoints The EPCONDIS bit UEPn lt 3 gt is used to enable or disable USB control operations SETUP through the endpoint Clearing this bit enables
523. ng the write or erase therefore code cannot execute An internal programming timer terminates program memory writes and erases A value written to program memory does not need to be a valid instruction Executing a program memory location that forms an invalid instruction results in a NOP FIGURE 6 1 TABLE READ OPERATION 6 1 Table Reads and Table Writes In order to read and write program memory there are two operations that allow the processor to move bytes between the program memory space and the data RAM Table Read TBLRD Table Write TBLWT The program memory space is 16 bits wide while the data RAM space is 8 bits wide Table reads and table writes move data between these two memory spaces through an 8 bit register TABLAT Table read operations retrieve data from program memory and place it into the data RAM space Figure 6 1 shows the operation of a table read with program memory and data RAM Table write operations store data from the data memory space into holding registers in program memory The procedure to write the contents of the holding registers into program memory is detailed in Section 6 5 Writing to Flash Program Memory Figure 6 2 shows the operation of a table write with program memory and data RAM Table operations work with byte entities A table block containing data rather than program instructions is not required to be word aligned Therefore a table block can start and end at a
524. ns 2004 Microchip Technology Inc Preliminary DS39632B page 365 PIC18F2455 2550 4455 4550 28 2 DC Characteristics Power Down and Supply Current PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Continued PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial PIC 18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial ae Device Typ Max Units Conditions D022 Module Differential Currents 4IWDT AIBOR AILVD AlOSCB AIAD Alwo7 Watchdog Timer 1 3 3 8 uA 40 C 1 4 3 8 uA 25 C VDD 2 0V 2 0 3 8 uA 85 C 1 9 46 LA 40 C 2 0 4 6 uA 25 C VDD 3 0V 28 46 uA 85 C 40 10 uA 40 C 5 5 10 uA 25 C VDD 5 0V 5 6 10 HA 85 C DO22A Brown out Reset 35 40 LA 40 Cto 85 C VpD 3 0V AIBOR 40 45 uA 40 C to 85 C S Vpp 5 0V Sleep mode Of A u BA Re BOREN1 BORENO 10 D022B High Low Volta Je 22 38 HA 40 C to 85 C VpD 2 0V AILVD Detect 25 40 uA 40 Cto 85 C Von 3 0V 29 45 uA 40 C to 85 C VDD 5 0V D025 Timer1 Oscillator 2 1 4 5 uA 40 C Alosce 18 45 pA 25 C VDD 2 0V 32 kHz on Timer1 2 1 4 5 uA 85
525. ns TFR Transition Rise Time 4 20 ns CL 50 pF TFF Transition Fall Time 4 20 ns CL 50 pF TFRFM Rise Fall Time Matching 90 111 1 2004 Microchip Technology Inc Preliminary DS39632B page 391 PIC18F2455 2550 4455 4550 FIGURE 28 22 STREAMING PARALLEL PORT TIMING PIC18F4455 4550 SPP lt 7 0 gt Note CSSPP ToeF2adR A ToeF2daR 1 gt lt Write Address Write Data ToeF adV ToeR2adl ToeF2daV ToeR2adl Refer to Figure 28 4 for load conditions TABLE 28 27 STREAMING PARALLEL PORT REQUIREMENTS PIC18F4455 4550 Param No Symbol Characteristic Min Max Units Conditions ToeF2adR OESPP Falling Edge to CSSPP Rising Edge 0 5 ns Address Out ToeF2adV OESPP Falling Edge to Address Out Valid 0 5 ns ToeR2adl OESPP Rising Edge to Address Out Invalid 0 5 ns ToeF2daR OESPP Falling Edge to CSSPP Rising Edge 0 5 ns Data Out ToeF2daV OESPP Falling Edge to Address Out Valid 0 5 ns ToeR2dal OESPP Rising Edge to Data Out Invalid 0 5 ns DS39632B page 392 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 28 28 A D CONVERTER CHARACTERISTICS PIC18F2455 2550 4455 4550 INDUSTRIAL PIC18LF2455 2550 4455 4550 IN
526. ns configuration bits that control the following e Main USB Peripheral Enable Ping Pong Buffer Pointer Reset REGISTER 17 1 e Control of the Suspend mode e Packet Transfer Disable In addition the USB Control register contains a status bit SEO UCON lt 5 gt which is used to indicate the occurrence of a single ended zero on the bus When the USB module is enabled this bit should be moni tored to determine whether the differential data lines have come out of a single ended zero condition This helps to differentiate the initial power up state from the USB Reset signal The overall operation of the USB module is controlled by the USBEN bit UCON lt 3 gt Setting this bit activates the module and resets all of the PPBI bits in the Buffer Descriptor Table to o This bit also activates the on chip voltage regulator and connects internal pull up resistors if they are enabled Thus this bit can be used as a soft attach detach to the USB Although all status and configuration bits are ignored when this bit is clear the module needs to be fully preconfigured prior to setting this bit UCON USB CONTROL REGISTER U 0 R W 0 R x R C 0 R W 0 R W 0 R W 0 U 0 PPBRST SEO PKTDIS USBEN RESUME SUSPND bit 7 bit 0 bit 7 Unimplemented Read as 0 bit 6 PPBRST Ping Pong Buffers Reset bit 1 Reset all ping pong buffer pointers to the Even Buffer Descriptor BD banks 0 Ping pong
527. nt clock source The INTRC source is providing the device clocks If the IRCF bits are changed from all clear thus enabling the INTOSC output or if INTSRC is set the IOFS bit becomes set after the INTOSC output becomes stable Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST If the IRCF bits were previously at a non zero value or if INTSRC was set before setting SCS1 and the INTOSC source was already stable the IOFS bit will remain set On transitions from RC RUN mode to PRI RUN mode the device continues to be clocked from the INTOSC multiplexer while the primary clock is started When the primary clock becomes ready a clock switch to the primary clock occurs see Figure 3 4 When the clock switch is complete the IOFS bit is cleared the OSTS bit is set and the primary clock is providing the device clock The IDLEN and SCS bits are not affected by the switch The INTRC source will continue to run if either the WDT or the Fail Safe Clock Monitor is enabled FIGURE 3 3 TRANSITION TIMING TO RC_RUN MODE a1la2laslaslat WSS RU ere en PESTE RES 92 93 Q4 Q1 Q2 93 Wm AN VPA PA CA Po a pas apa a osci JA M m m lt Clock Transition i i i i Aca NIN oe NE EN CT NON Peripheral _ nm NTN LY Pu TN oe PC Y PC 2 I PO 4 Note 1 Clock transition typically occurs within 2 4 Tosc
528. nt elements Baud Rate Generator e Sampling Circuit e Asynchronous Transmitter e Asynchronous Receiver e Auto Wake up on Sync Break Character e 12 bit Break Character Transmit Auto Baud Rate Detection EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 20 3 The heart of the transmitter is the Transmit Serial Shift Register TSR The Shift register obtains its data from the Read Write Transmit Buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the Stop bit has been transmitted from the previous load As soon as the Stop bit is transmitted the TSR is loaded with new data from the TXREG register if available 20 2 1 Once the TXREG register transfers the data to the TSR register occurs in one TCY the TXREG register is empty and the TXIF flag bit PIR1 lt 4 gt is set This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit TXIE PIE1 lt 4 gt TXIF will be set regardless of the state of TXIE it cannot be cleared in software TXIF is also not cleared immediately upon loading TXREG but becomes valid in the second instruction cycle following the load instruction Polling TXIF immediately following a load of TXREG will return invalid results While TXIF indicates the status of the TXREG register another bit TRMT TXSTA lt 1 gt shows the status of the TSR register TRMT is a read only
529. nter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch PD Power Down bit PRODH Product of Multiply High Byte PRODL Product of Multiply Low Byte s Fast Call Return mode select bit s 0 do not update into from shadow registers S 1 certain registers loaded into from shadow registers Fast mode TBLPTR 21 bit Table Pointer points to a program memory location TABLAT 8 bit Table Latch TO Time out bit TOS Top of Stack u Unused or unchanged WDT Watchdog Timer WREG Working register accumulator x Don t care 0 or 1 The assembler will generate code with x 0 It is the recommended form of use for compatibility with all Microchip software tools Zs 7 bit offset value for indirect addressing of register files source Za 7 bit offset value for indirect addressing of register files destination 4 Optional argument text Indicates an indexed address text The contents of text expr lt n gt Specifies bit n of the register indicated by the pointer expr gt Assigned to lt gt Register bit field In the set of italics User defined term font is Courier DS39632B page 302 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 26 1 GENERAL FORMAT FOR INSTRUCTIONS Byte oriented file register operations Example Instruction 15 10 9 87 0 OPCO
530. nues to run DS39632B page 36 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 3 1 TRANSITION TIMING FOR ENTRY TO SEC RUN MODE 91la21 AZlA4lA1 l Q2 Q3 Q4 Q1 Q2 Q3 nos ANY gt MUAA PUA TA TATATATATATATA Clock Transition 5 osci JUN CPU Glock SSS Peripheral j NIA SIND NAS Nut NOS JA Program Counter PC Note 1 Clock transition typically occurs within 2 4 Tosc PC 2 i Y PC 4 FIGURE 3 2 TRANSITION TIMING FROM SEC RUN MODE TO PRI RUN MODE HSPLL Q1 Q2 Q3 Qi gt 02 A3 A4 Q1 Q2 Q3 ae s EE A Output j UNIES PLL Clock ut us Vata 2 raise Sh s Clock CPU Clock V Transition 3 L atata a a aval NA A A A AR UNIV AAA Program PG Counter SCS1 SCS0 bits Changed OSTS bit Set Note 1 TosrT 1024 Tosc TPLL 2 ms approx These intervals are not shown to scale 2 Clock transition typically occurs within 2 4 Tosc PC 2 X PC 4 3 2 3 RC RUN MODE In RC RUN mode the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer the primary clock is shut down When using the INTRC source this mode provides the best power conservation of all the Run modes whi
531. ny byte address If a table write is being used to write executable code into program memory program instructions will need to be word aligned Table Pointer Instruction TBLRD Program Memory TBLPTRU TBLPTRH TBLPTRL y Program Memory TBLPTR Table Latch 8 bit TABLAT Note 1 Table Pointer register points to a byte in program memory 2004 Microchip Technology Inc Preliminary DS39632B page 79 PIC18F2455 2550 4455 4550 FIGURE 6 2 TABLE WRITE OPERATION Instruction TBLWT Program Memory Holding Registers Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory TBLPTR Table Latch 8 bit TABLAT Note 1 Table Pointer actually points to one of 32 holding registers the address of which is determined by TBLPTRL lt 4 0 gt The process for physically writing data to the program memory array is discussed in Section 6 5 Writing to Flash Program Memory 6 2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions These include the e EECONI register e EECON2 register TABLAT register TBLPTR registers 6 2 1 EECON1 AND EECON2 REGISTERS The EECON1 register Register 6 1 is the control register for memory accesses The EECONZ2 register is not a physical register it is used exclusively in the memo
532. o the result is placed in W If d is 1 the result is placed back in register f default If the result is 0 the next instruction which is already fetched is discarded and a NOP is executed instead making it a two cycle instruction If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details 1 1 2 Note 3 cycles if skip and followed by a 2 word instruction 01 Q2 03 Q4 Decode Read Process Write to register f Data destination If skip Q1 Q2 Q3 Q4 No No No No operation operation operation operation If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE DECFSZ CNT Ty CT GOTO LOOP CONTINUE Before Instruction PC Address HERE After Instruction CNT CNT 1 IfCNT 0 PC Address CONTINUE If CNT PC Address HERE 2 2004 Microchip Technology Inc DCFSNZ Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Decrement
533. o Seating Plane A 140 150 160 8 56 3 81 4 06 Molded Package Thickness A2 125 130 185 3 18 3 30 3 43 Base to Seating Plane Al 015 0 38 Shoulder to Shoulder Width E 300 310 325 7 62 7 87 8 26 Molded Package Width E 275 285 295 6 99 7 24 7 49 Overall Length D 1 345 1 365 1 385 34 16 34 67 35 18 Tip to Seating Plane L 125 130 135 3 18 3 30 3 43 Lead Thickness c 008 012 015 0 20 0 29 0 38 Upper Lead Width B1 040 053 065 1 02 1 33 1 65 Lower Lead Width B 016 019 022 0 41 0 48 0 56 Overall Row Spacing eB 320 350 430 8 13 8 89 10 92 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter 8 Significant Characteristic Notes Dimension D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side JEDEC Equivalent MO 095 Drawing No C04 070 2004 Microchip Technology Inc Preliminary DS39632B page 399 E t G E1 B Co U DOT UI N at hoe 45 T PIC18F2455 2550 4455 4550 28 Lead Plastic Small Outline SO Wide 300 mil Body SOIC A2 F l RE Aj Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pit
534. ogramming situations that require the creation of data structures or look up tables in program memory For PIC18 devices look up tables can be implemented in two ways e Computed GOTO Table Reads 5 1 4 1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter An example is shown in Example 5 2 A look up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions The W register is loaded with an offset into the table before executing a call to that table The first instruction of the called routine is the ADDWF PCL instruction The next instruction executed will be one of the RETLW nn instructions that returns the value nn to the calling function The offset value in WREG specifies the number of bytes that the program counter should advance and should be multiples of 2 LSb 0 In this method only one data byte may be stored in each instruction location and room on the return address stack is required EXAMPLE 5 2 COMPUTED GOTO USING AN OFFSET VALUE MOVF OFFSET W CALL TABLE ORG nnooh TABLE ADDWF PCL RETLW nnh RETLW nnh RETLW nnh 5 1 4 2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location Look up table data may be stored two bytes per program word by using table reads and writes The Table Pointer TBLPTR register specifies t
535. olution 6 25 ns Tcy 16 Compare is 16 bit max resolution 100 ns Tcy PWM output PWM resolution is 1 to 10 bit Enhanced Capture Compare PWM ECCP module Multiple output modes Selectable polarity Programmable dead time Auto Shutdown and Auto Restart Enhanced USART module LIN bus support e Master Synchronous Serial Port MSSP module supporting 3 wire SPI all 4 modes and IC Master and Slave modes 10 bit up to 13 channels Analog to Digital Converter module A D with programmable acquisition time Dual analog comparators with input multiplexing Special Microcontroller Features C compiler optimized architecture with optional extended instruction set e 100 000 erase write cycle Enhanced Flash program memory typical 1 000 000 erase write cycle Data EEPROM memory typical Flash Data EEPROM Retention gt 40 years Self programmable under software control e Priority levels for interrupts 8x 8 Single Cycle Hardware Multiplier Extended Watchdog Timer WDT Programmable period from 41 ms to 131s Programmable Code Protection e Single Supply 5V In Circuit Serial Programming ICSPTM via two pins In Circuit Debug ICD via two pins Optional dedicated ICD ICSP port 44 pin devices only e Wide operating voltage range 2 0V to 5 5V Program Memory Data Memory MSSP ao 3 10 bit CCP ECCP lt S Timers Device Flash
536. omers with the best documentation possible to ensure successful use of your Microchip products To this end we will continue to improve our publications to better suit your needs Our publications will be refined and enhanced as new volumes and updates are introduced If you have any questions or comments regarding this publication please contact the Marketing Communications Department via E mail at docerrors microchip com or fax the Reader Response Form in the back of this data sheet to 480 792 4150 We welcome your feedback Most Current Data Sheet To obtain the most up to date version of this data sheet please register at our Worldwide Web site at http www microchip com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number e g DS30000A is version A of document DS30000 Errata An errata sheet describing minor operational differences from the data sheet and recommended workarounds may exist for current devices As device documentation issues become known to us we will publish an errata sheet The errata will specify the revision of silicon and revision of document to which it applies To determine if an errata sheet exists for a particular device please check with one of the following e Microchip s Worldwide Web site http www microchip com e Your local Microchip sales office see l
537. on FSR2 zs gt FSR2 zd FSR2 1 FSR2 Status Affected None Status Affected None eneoding Encoding 1111 1010 kkkk kkkk 1st word source 1110 1011 12zz ZZZZs 2nd word dest 1111 xxxx xzzz ZZZZa Description The 8 bit literal k is written to the data Description The contents of the source register are SSS Fee moved to the destination register The as 1 addresses ofthe source and destination This drsn peg users to push values registers are determined by adding the ento a Sol Ware Staci 7 bit literal offsets Z or Zg Words 1 respectively to the value of FSR2 Both Cycles 1 registers can be located anywhere in i a the 4096 byte data memory space Q Cycle Activity 000h to FFFh Q1 Q2 Q3 Q4 The MOVSS instruction cannot use the Decode Read k Process Write to PCL TOSU TOSH or TOSL as the data destination destination register If the resultant source address points to an indirect addressing register the Example PUSHL 08h value returned will be 00h If the Before resultant destination address points to A S O1ECh an indirect addressing register the Memory 01ECh z 00h instruction will execute as a NOP Words 2 After Instruction FSR2H FSR2L O1EBh Cycles 2 Memory 01ECh 08h Q Cycle Activity Q1 Q2 Q3 Q4 Decode Determine Determine Read source addr source addr source reg Decode Determine Determine Write dest addr dest addr to dest reg Example Movss 05h 06h Before Instru
538. on reception has completed The SSPBUF must be read and or written If the interrupt method is not going to be used then software polling can be done to ensure that a write collision does not occur Example 19 1 shows the loading of the SSPBUF SSPSR for data transmission The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register Additionally the MSSP Status register SSPSTAT indicates the various status conditions EXAMPLE 19 1 LOADING THE SSPBUF SSPSR REGISTER LOOP BTFSS SSPSTAT BF BRA LOOP No MOVF SSPBUF W MOVWF RXDATA MOVWF SSPBUF Has data been received transmit complete WREG reg contents of SSPBUF Save in user RAM MOVF TXDATA W W reg contents of TXDATA New data to xmit if data is meaningful DS39632B page 196 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 3 3 ENABLING SPI O To enable the serial port SSP Enable bit SSPEN SSPCON1 lt 5 gt must be set To reset or reconfigure SPI mode clear the SSPEN bit reinitialize the SSPCON registers and then set the SSPEN bit This configures the SDI SDO SCK and SS pins as serial port pins For the pins to behave as the serial port function some must have their data direction bits in the TRIS register appropriately programmed as follows SDI is automatically controlled by the SPI module SDO must have TRISC lt 7 gt bit cleared S
539. ong pointers to Even using the PPBRST bit Figure 17 7 shows the three different modes of operation and how USB RAM is filled with the BDs BDs have a fixed relationship to a particular endpoint depending on the buffering configuration The mapping of BDs to endpoints is detailed in Table 17 4 This relationship also means that gaps may occur in the BDT if endpoints are not enabled contiguously This theoretically means that the BDs for disabled endpoints could be used as buffer space In practice users should avoid using such spaces in the BDT unless a method of validating BD addresses is implemented BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES PPB1 PPBO 00 No Ping Pong Buffers PPB1 PPBO 01 Ping Pong Buffer on EPO OUT 400h s 400h EPO OUT Descriptor EPO IN Descriptor EP1 OUT Descriptor EP1 IN Descriptor 55 EP15 IN Descriptor CL 2 NE EE EE 47Fh Pi Va Au 483h gt vailable as WWI WK 4FFh 4FFh Maximum Memory Used 128 bytes Maximum BDs 32 BDO to BD31 Note Memory area not shown to scale Maximum Memory Used 132 bytes Maximum BDs 33 BDO to BD32 PPB1 PPBO 10 Ping Pong Buffers on all EPs 400h 2 EPO OUT Even IL EPO OUT Even f Descri
540. onous serial port by clearing bit SYNC and setting bit SPEN If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 Enable the reception by setting bit CREN Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set 7 Read the RCSTA register to get the ninth bit if enabled and determine if any error occurred during reception 8 Read the 8 bit received data by reading the RCREG register 9 If any error occurred clear the error by clearing enable bit CREN 10 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set oak w FIGURE 20 6 EUSART RECEIVE BLOCK DIAGRAM 20 2 3 SETTING UP 9 BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS 485 systems To set up an Asynchronous Reception with Address Detect Enable 1 SE Or E 10 11 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRGH and BRG16 bits as required to achieve the desired baud rate Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit If interrupts are required set the RCEN bit and select the desired priority level with the RCIP bit Set the RX9 bit to enable 9 bit reception Set the ADDEN bit to enable address detect Enable reception by setting the CREN bit The RCIF bit will be set when reception is com
541. ons VOL Output Low Voltage DO80 I O ports except RC4 RC5 in 0 6 V loi 8 5 mA VDD 4 5V USB mode 40 C to 85 C D083 OSC2 CLKO 0 6 V loL 1 6 mA VDD 4 5V EC ECIO modes 40 C to 85 C VOLU D D Out 0 3 VDD 4 35V USB suspended VoH Output High Voltage DO90 I O ports except RC4 RC5 in VDD 0 7 V loH 3 0 mA VDD 4 5V USB mode 40 C to 85 C D092 OSC2 CLKO VDD 0 7 V loH 1 3 mA VDD 4 5V EC ECIO ECPIO modes 40 C to 85 C VOHU D D Out 2 8 3 6 V VDD 4 35V USB suspended Capacitive Loading Specs on Output Pins D100 4 Cosc2 OSC2 pin 15 pF In XT and HS modes when external clock is used to drive OSC1 D101 Clo All O pins and OSC2 50 pF To meet the AC Timing in RC mode Specifications D102 CB SCL SDA 400 pF IC Specification Note 1 In RC oscillator configuration the OSC1 CLKI pin is a Schmitt Trigger input It is not recommended that the PICmicro device be driven with an external clock while in RC mode 2 The leakage current on the MCLR pin is strongly dependent on the applied voltage level The specified levels represent normal operating conditions Higher leakage current may be measured at different input voltages 3 Negative current is defined as current sourced by the pin 4 Parameter is characterized but not tested 5 D parameters per USB Specification 2 0 2004 Microchip Technology Inc Preliminary DS39632B page 369
542. ons where PORTB is only used for the interrupt on change feature Polling of PORTB is not recommended while using the interrupt on change feature Pins RB2 and RB3 are multiplexed with the USB peripheral and serve as the differential signal outputs for an external USB transceiver TRIS configuration Refer to Section 17 2 2 2 External Transceiver for additional information on configuring the USB module for operation with an external transceiver RB4 is multiplexed with CSSPP the chip select function for the Streaming Parallel Port SPP TRIS setting Details of its operation are discussed in Section 18 0 Streaming Parallel Port EXAMPLE 10 2 INITIALIZING PORTB CLRF PORTB Initialize PORTB by clearing output data latches Alternate method to clear output data latches OVLW OEh Set RB lt 4 0 gt as OVWEF ADCON1 digital I O pins required if config bit PBADEN is set Value used to initialize data CLRF LATB OVLW OCFh direction Set RB lt 3 0 gt as inputs RB lt 5 4 gt as outputs i RB lt 7 6 gt as inputs OVWF TRISB DS39632B page 114 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 10 3 PORTB I O SUMMARY Pin Function Aine 1 0 1 0 Type Description RBO AN1 2 RBO 0 OUT DIG LATB lt
543. ons that can use direct addressing are potentially affected by the Indexed Literal Offset Addressing mode This includes all byte oriented and bit oriented instructions or almost one half of the standard PIC18 instruction set Instructions that only use Inherent or Literal Addressing modes are unaffected Additionally byte oriented and bit oriented instructions are not affected if they use the Access Bank Access RAM bit is 1 or include a file address of 60h or above Instructions meeting these criteria will continue to execute as before A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 5 8 Those who desire to use byte oriented or bit oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode This is described in more detail in Section 26 2 1 Extended Instruction Syntax 2004 Microchip Technology Inc Preliminary DS39632B page 75 PIC18F2455 2550 4455 4550 FIGURE 5 8 COMPARING ADDRESSING OPTIONS FOR BIT ORIENTED AND BYTE ORIENTED INSTRUCTIONS EXTENDED INSTRUCTION SET ENABLED EXAMPLE INSTRUCTION ADDWF f d a Opcode 0010 01da ffff ffff When a 0 and f gt 60h 000n The instruction executes in 060h Direct Forced mode f is inter 080h Bank 0 preted as a lo
544. onsumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or Vss MCLR VDD WDT enabled disabled as specified 3 Standard low cost 32 kHz crystals have an operating temperature range of 10 C to 70 C Extended temperature crystals are available at a much higher cost 4 BOR and HLVD enable internal band gap reference With both modules enabled current consumption will be less than the sum of both specifications DS39632B page 362 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 28 2 DC Characteristics Power Down and Supply Current PIC18F2455 2550 4455 4550 Industrial PIC18LF2455 2550 4455 4550 Industrial Continued PIC18LF2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial jv Device Typ Max Units Conditions Supply Current Ipp 2 PIC18LFX455 X550 250 500 HA 40 C 250 500 LA 25 C VDD 2 0V 250 500 HA 85 C PIC18LFX455 X550 550 650 A 40 C Fosc 1 MHz 480 650
545. or the MSSP module operating in SPI mode Additional information is provided in Section 19 0 Master Synchronous Serial Port MSSP Module FIGURE 13 1 TIMER2 BLOCK DIAGRAM 4 T20UTPS3 T20UTPSO 14197148 O Set TMR2IF Postscaler 2 T2CKPS1 T2CKP SO TMR2 Output to PWM or MSSP TMR2 PR2 i AAA i Match sian AW C t PR2 Fosc 4 RER TMR2 gt Comparator K gt D 8 8 Internal Data Bus lt yA p TABLE 13 1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIEU ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 54 TMR2 Timer2 Register 52 T2CON T20UTPS3 T2OUTPS2 T2OUTPSI1 T2OUTPSO TMR2ON T2CKPS1 T2CKPSO 52 PR2 Timer2 Period Register 52 Legend unimplemented read as 0 Shaded cells are not used by the Timer2 module Note 1 These bits are unimplemented on 28 pin devices always maintain these bits clear DS39632B page 136 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 14 0 TIMER3 MODULE The Timer3 module timer counter incorporates these features Softwar
546. orced to a Reset state depending on the type of Reset that occurred Most registers are not affected by a WDT wake up since this is viewed as the resumption of normal oper ation Status bits from the RCON register RI TO PD POR and BOR are set or cleared differently in different Reset situations as indicated in Table 4 3 These bits are used in software to determine the nature of the Reset Table 4 4 describes the Reset states for all of the Special Function Registers These are categorized by Power on and Brown out Resets Master Clear and WDT Resets and WDT wake ups TABLE 4 3 STATUS BITS THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program RCON Register STKPTR Register Condition Count es a ounter SBOREN RI TO PD POR BOR STKFUL STKUNF Power on Reset 0000h 1 1 1 0 0 0 0 RESET Instruction 0000h ul 0 u u u u Brown out 0000h ul i u 0 MCLR during Power Managed 0000h ul u 1 u u u u u Run modes MCLR during Power Managed 0000h ul u 1 0 u u u u Idle modes and Sleep mode WDT Time out during Full Power 0000h ul u 0 u u u u u or Power Managed Run modes MCLR during Full Power 0000h ul u u u u u u u Execution Stack Full Reset STVREN 1 0000h ul u Stack Underflow Reset 0000h ul u 1 STVREN 1 Stack Underflow Error not an 0000h ul u u u u u u 1 actual Reset STVREN o WDT Time out during PC 2 ul u 0 0 u
547. oscillator block the Sleep mode does not use a clock source The power managed modes include several power saving features offered on previous PICmicro devices One is the clock switching feature offered in other PIC18 devices allowing the controller to use the Timer1 oscillator in place of the primary oscillator Also included is the Sleep mode offered by all PICmicro devices where all device clocks are stopped 3 1 Selecting Power Managed Modes Selecting a power managed mode requires two decisions if the CPU is to be clocked or not and the selection of a clock source The IDLEN bit OSCCON lt 7 gt controls CPU clocking while the SCS1 SCS0 bits OSCCON lt 1 0 gt select the clock source The individual modes bit settings clock sources and affected modules are summarized in Table 3 1 3 1 1 CLOCK SOURCES The SCS1 SCSO bits allow the selection of one of three clock sources for power managed modes They are e the primary clock as defined by the FOSC3 FOSCO configuration bits e the secondary clock the Timer1 oscillator the internal oscillator block for RC modes 3 1 2 ENTERING POWER MANAGED MODES Switching from one power managed mode to another begins by loading the OSCCON register The SCS1 SCS0 bits select the clock source and determine which Run or Idle mode is to be used Changing these bits causes an immediate switch to the new clock source assuming that it is running The switch may also be subject to
548. otes the instruction cycle rate RA6 VO TTL General purpose I O pin Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels O Output Alternate assignment for CCP2 when CCP2MX configuration bit is cleared P Input Power 2 Default assignment for CCP2 when CCP2MxX configuration bit is set 3 These pins are No Connect unless the ICPRT configuration bit is set For NC ICPORTS the pin is No Connect unless ICPRT is set and the DEBUG configuration bit is cleared DS39632B page 16 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 1 3 PIC18F4455 4550 PINOUT O DESCRIPTIONS CONTINUED Pin Name ber n j Burer Description PDIP QFN TQFP Type Type r PORTA is a bidirectional I O port RAO ANO 2 19 19 RAO VO TTL Digital I O ANO Analog Analog input 0 RA1 AN1 3 20 20 RA VO TTL Digital I O AN1 I Analog Analog input 1 RA2 AN2 VREF 4 21 21 CVREF RA2 VO TTL Digital I O AN2 I Analog Analog input 2 VREF Analog A D reference voltage low input CVREF O Analog Analog comparator reference output RA3 AN3 VREF 5 22 22 RA3 VO TTL Digital I O AN3 I Analog Analog input 3 VREF Analog A D reference voltage high input RA4 TOCKI C1OUT 6 23 23 RCV RA4 O ST Digital I O TOCKI ST Timer0 external clock input C1OUT O Comparator 1 output R
549. ource or destination in their opcodes In these cases the BSR is ignored entirely The destination of the operation s results is determined by the destination bit d When d is 1 the results are stored back in the source register overwriting its origi nal contents When d is the results are stored in the W register Instructions without the d argument have a destination that is implicit in the instruction their destination is either the target register being operated on or the W register 5 4 3 INDIRECT ADDRESSING Indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction This is done by using File Select Registers FSRs as pointers to the locations to be read or written to Since the FSRs are themselves located in RAM as Special File Registers they can also be directly manipulated under program control This makes FSRs very useful in implementing data structures such as tables and arrays in data memory The registers for indirect addressing are also implemented with Indirect File Operands INDFs that permit automatic manipulation of the pointer value with auto incrementing auto decrementing or offsetting with another value This allows for efficient code using loops such as the example of clearing an entire RAM bank in Example 5 5 EXAMPLE 5 5 HOW TO CLEAR RAM BANK 1 USING INDIRECT ADDRESSING LFSR FSRO 100h NEXT CL
550. ously described FIGURE 5 9 REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation ADDWF f d a 000h FSR2H FSR2L 120h S o Bank 0 Locations in the region from the FSR2 pointer 100h 120h to the pointer plus 120h O5Fh 17Fh are mapped 17Fh Window k l 00h to the bottom of the om ae a tn Access RAM 000h 05Fh 200h Bank 1 Window Special File Registers at a F60h through FFFh are mapped to 60h through GA Bank 2 A FFh as usual through SFRs Bank 0 addresses below Bank 14 SFh are not available in FFh this mode They can still Access Bank be addressed by using the Egon BSR Bank 15 F60h SFRs FFFh Data Memory 2004 Microchip Technology Inc Preliminary DS39632B page 77 PIC18F2455 2550 4455 4550 NOTES DS39632B page 78 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 6 0 FLASH PROGRAM MEMORY The Flash program memory is readable writable and erasable during normal operation over the entire VDD range A read from program memory is executed on one byte at a time A write to program memory is executed on blocks of 32 bytes at a time Program memory is erased in blocks of 64 bytes at a time A Bulk Erase operation may not be issued from user code Writing or erasing program memory will cease instruction fetches until the operation is complete The program memory cannot be accessed duri
551. out hardware multiply 52 254 25 4 us 102 6 us 254 us 16 x 16 signed Hardware multiply 35 40 4 0 us 16 0 us 40 us 2004 Microchip Technology Inc Preliminary DS39632B page 95 PIC18F2455 2550 4455 4550 Example 8 3 shows the seguence to do a 16 x 16 unsigned multiplication Equation 8 1 shows algorithm that is used The 32 bit result is stored in four the EQUATION 8 2 16x16 SIGNED MULTIPLICATION ALGORITHM registers RES3 RE SO RES3 RESO ARGIH ARGIL ARG2H ARG2L ARGIH e ARG2H 216 EGUATION 8 1 16 x 16 UNSIGNED ARGIH ARG2L e 28 MULTIPLICATION ARGIL ARG2H e 28 ALGORITHM ARGIL e ARG2L 1 ARG2H lt 7 gt e ARGIH ARGIL e 216 RES3 RESO ARGIH ARGIL ARG2H ARG2L 1 ARGIH lt 7 gt ARG2H ARGZL e 216 ARGIH e ARG2H e 2 6 ARGIH e ARG2L e 28 ARGIL ARG2H 28 EXAMPLE 8 4 16 x 16 SIGNED nl MULTIPLY ROUTINE MOVE ARGIL W EXAMPLE 8 3 16 x 16 UNSIGNED MULWF ARG2L ARGIL ARG2L gt MULTIPLY ROUTINE PRODH PRODL MOVFF PRODH RES1 MOVE ARGIL W MOVFF PRODL RESO MULWF ARG2L ARG1L ARG2L gt A M PRODH PRODL MOVF ARGIH W ee PROPERES b MULWF ARG2H ARG1H ARG2H gt MOVFF PRODL RESO PRODH PRODL _ MOVFF PRODH RES3 MOVE ARGIH W MOVFF PRODL RES2 MULWE ARG2H ARGIH ARG2H gt aS PRODH PRODL MOVF ARGIL W O PROD PRESS I MULWF ARG2H ARG1
552. p The INTRC source will continue to run if either the WDT or the Fail Safe Clock Monitor is enabled 3 5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt a Reset or a WDT time out This section discusses the triggers that cause exits from power managed modes The clocking subsystem actions are discussed in each of the power managed modes see Section 3 2 Run Modes Section 3 3 Sleep Mode and Section 3 4 Idle Modes 3 5 1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode To enable this functionality an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers The exit sequence is initiated when the corresponding interrupt flag bit is set On all exits from Idle or Sleep modes by interrupt code execution branches to the interrupt vector if the GIE GIEH bit INTCON lt 7 gt is set Otherwise code execution continues or resumes without branching see Section 9 0 Interrupts A fixed delay of interval Tcsp following the wake event is required when leaving Sleep and Idle modes This delay is required for the CPU to prepare for execution Instruction execution resumes on the first clock cycle following this delay 3 5 2 EXIT BY WDT TIME OUT A WDT time out will cause different actions depending on which power managed mode th
553. p PC operation Data from stack C lt register f No No No No operation operation operation operation Words 1 Cycles 1 Q Cycle Activity Example RETURN Q1 Q2 Q3 Q4 After Instruction Decode Read Process Write to PC TOS register f Data destination Example RLCF REG 0 0 Before Instruction REG 1110 0110 G 0 After Instruction REG 1110 0110 w 1100 1100 G 1 2004 Microchip Technology Inc Preliminary DS39632B page 333 PIC18F2455 2550 4455 4550 RLNCF Syntax Operands Operation Rotate Left f no carry RLNCF f d a 0 lt f lt 255 d e 0 1 ae 0 1 f lt n gt dest lt n 1 gt f lt 7 gt gt dest lt 0 gt Status Affected N Z Encoding 0100 01da fffft ffff Description The contents of register f are rotated one bit to the left If d is o the result is placed in W If d is 1 the result is stored back in register f default If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details pE register f 45 Words 1 Cycles 1 Q Cycle Activity 0
554. p TOS No operation value operation Example POP GOTO NEW Before Instruction TOS 0031A2h Stack 1 level down 014332h After Instruction TOS 014332h PC NEW PUSH Push Top of Return Stack Syntax PUSH Operands None Operation PC 2 3 TOS Status Affected None Encoding 0000 0000 0000 0101 Description The PC 2 is pushed onto the top of the return stack The previous TOS value is pushed down on the stack This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack Words 1 Cycles 1 Q Cycle Activity 01 Q2 Q3 Q4 Decode Push PC 2 No No onto return operation operation stack Example PUSH Before Instruction TOS 345Ah PC 0124h After Instruction PC 0126h TOS 0126h Stack 1 level down 345Ah DS39632B page 330 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 RCALL Relative Call Syntax RCALL n Operands 1024 lt n lt 1023 Operation PC 2 TOS PC 2 2n PC Status Affected None Encoding 1101 innn nnnn nnnn Description Subroutine call with a jump up to 1K from the current location First return address PC 2 is pushed onto the stack Then add the 2s complement number 217 to the PC Since the PC will have incremented to fetch the next instruction the new address will be PC 2
555. p or f Descriptor lt t lt L EPO OUT Odd L EPO OUT Odd Descriptor J Descriptor 54 EPO IN Even 7 EPO IN P Descriptor d Descriptor J EPO IN Odd r EP1 OUT Descriptor 4 Descriptor 4 EP1 OUT Even f EP1 IN T P Descriptor Descriptor EP1 OUT Odd 7 Descrip or I EP1 IN Even EP15 IN ff Descriptor Descriptor L EP IN Odd Descriptor J KT Fee EP15 IN Odd Descriptor 4FFh Maximum Memory Used 256 bytes Maximum BDs 64 BDO to BD63 2004 Microchip Technology Inc Preliminary DS39632B page 175 PIC18F2455 2550 4455 4550 TABLE 17 4 ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Endpoint Mode 0 Mode 1 Mode 2 No Ping Pong Ping Pong on EPO OUT Ping Pong on all EPs Out In Out In Out In 0 0 1 0 B 1 O 2 0 E 1 O 2 E 3 O 1 2 3 3 4 4 E 5 O 6 E 7 O 2 4 5 5 6 8 E 9 O 10 E 11 O 3 6 7 7 8 12 E 13 O 14 E 15 O 4 8 9 9 10 16 E 17 O 18 E 19 O 5 10 11 11 12 20 E 21 O 22 E 23 O 6 12 13 13 14 24 E 25 O 26 E 27 O 7 14 15 15 16 28 E 29 O 30 E 31 O 8 16 17 17 18 32 E 33 O 34 E 35 O 9 18 19 19 20 36 E 37 O 38 E 39 O 10 20 21 21 22 40 E 41 O 42 E 43 O 11 22 23 23 24 44 E 45 O
556. pecial Event Trigger If the CCP2 module is configured to generate a special event trigger in Compare mode CCP2M3 CCP2M0 1011 this signal will reset Timers It will also start an A D conversion if the A D module is enabled see Section 15 3 4 Special Event Trigger for more information The module must be configured as either a timer or synchronous counter to take advantage of this feature When used this way the CCPR2H CCPR2L register pair effectively becomes a period register for Timers If Timer3 is running in Asynchronous Counter mode the Reset operation may not work In the event that a write to Timer3 coincides with a special event trigger from a CCP module the write will take precedence Note The special event triggers from the CCP2 module will not set the TMRSIF interrupt flag bit PIR2 lt 1 gt TABLE 14 1 REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 TMR3L Timer3 Register Low Byte 53 TMR3H Timer3 Register High Byte 53 T1CON RD16 TIRUN T1CKPS1 TICKPSO TIOSCEN
557. peration fs gt fa Status Affected None Encoding 1st word source 1100 FERF F CE fff 2nd word destin 1111 FETE ffff ffffa Description Words Cycles Q Cycle Activity Qi The contents of source register f are moved to destination register fy Location of source f can be anywhere in the 4096 byte data space 000h to FFFh and location of destination fy can also be anywhere from 000h to FFFh Either source or destination can be W a useful special situation MOVFF is particularly useful for transferring a data memory location to a peripheral register such as the transmit buffer or an I O port The MOVFF instruction cannot use the PCL TOSU TOSH or TOSL as the destination register 2 2 Q2 Q3 Q4 Decode Read register f src Process Data No operation Decode No operation No dummy read No operation Write register f dest Example MOVFF Before Instruction REG1 REG2 33h 11h After Instruction REG1 REG2 33h 33h REG1 REG2 MOVLB Move Literal to Low Nibble in BSR Syntax MOVLW k Operands 0 lt k lt 255 Operation k 3 BSR Status Affected None Encoding 0000 0001 kkkk kkkk Description The eight bit literal k is loaded into the Bank Select Register BSR The value of BSR lt 7 4 gt always remains 0 regardless of the
558. period of Acknowledge sequence FIGURE 19 24 STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 _ SCL 1 for TBRG followed by SDA 1 for TBRG set PEN ter SDA sampled high P bit SSPSTAT lt 4 gt is set Falling edge of PEN bit SSPCON2 lt 2 gt is cleared by ninth clock hardware and the SSPIF bit is set TBRG SCL SDA ACK Z R P v k TBRG gt k TBRG gt k TBRG t SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note TBRG one Baud Rate Generator period DS39632B page 226 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 14 SLEEP OPERATION While in Sleep mode the 1 2004 Microchip Technology Inc Preliminary DS39632B page 227 PIC18F2455 2550 4455 4550 19 4 17 1 Bus Collision During a Start Condition During a Start condition a bus collision occurs if a SDA or SCL are sampled low at the beginning of the Start condition Figure 19 26 b SCL is sampled low before SDA is asserted low Figure 19 27 During a Start condition both the SDA and the SCL pins are monitored If the SDA pin is already low or the SCL pin is already low then all of the following occur e the Start condition is aborted the BCLIF flag is set and the MSSP module is reset to its Idle state Figure 19 26 The Start condition begins with the SDA a
559. period before Other options to prevent shoot through current may exist DS39632B page 156 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 16 8 PWM DIRECTION CHANGE SIGNAL x Period al DC Note 1 The direction bit in the CCP1 Control register CCP1CON lt 7 gt is written any time during the PWM cycle 2 When changing directions the PIA and P1C signals switch before the end of the current PWM cycle at intervals of 4 Tosc 16 Tosc or 64 Tosc depending on the Timer2 prescaler value The modulated P1B and P1D signals FIGURE 16 9 PWM DIRECTION CHANGE AT NEAR 100 DUTY CYCLE 2004 Microchip Technology Inc Preliminary DS39632B page 157 PIC18F2455 2550 4455 4550 16 4 6 PROGRAMMABLE DEAD BAND DELAY Note Programmable dead band delay is not implemented in 28 pin devices with standard CCP modules In half bridge applications where all power switches are modulated at the PWM freguency at all times the power switches normally reguire more time to turn off than to turn on If both the upper and lower power switches are switched at the same time one turned on and the other turned off both switches may be on for a short period of time until one switch completely turns off During this brief interval a very high current shoot through current may flow through both power switches shorting the bridge sup
560. perly The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock If the master receives an Acknowledge the Acknowledge Status bit ACKSTAT is cleared If not the bit is set After the ninth clock the SSPIF bit is set and the master clock Baud Rate Generator is suspended until the next data byte is loaded into the SSPBUF leaving SCL low and SDA unchanged Figure 19 21 After the write to the SSPBUF each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R W bit are completed On the fall ing edge of the eighth clock the master will deassert the SDA pin allowing the slave to respond with an Acknowledge On the falling edge of the ninth clock the master will sample the SDA pin to see if the address was recognized by a slave The status of the ACK bit is loaded into the ACKSTAT status bit SSPCON2 lt 6 gt Following the falling edge of the ninth clock transmis sion of the address the SSPIF is set the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place holding SCL low and allowing SDA to float 19 4 10 1 BF Status Flag In Transmit mode the BF bit SSPSTAT lt 0 gt is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out 19 4 10 2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress i e SSPSR is still shifting out a data byt
561. plete The interrupt will be Acknowledged if the RCIE and GIE bits are set Read the RCSTA register to determine if any error occurred during reception as well as read bit 9 of data if applicable Read RCREG to determine if the device is being addressed If any error occurred clear the CREN bit If the device has been addressed clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU CREN x64 Baud Rate CLK i 264 BRG16 SPBRGH SPBRG or i 16 ESO Sas hens or Baud Rate Generator 4 Pin Buffer Data X and Contro Recovery RX SPEN Interrupt a RX9 RX9D RCREG Register FIFO 8 RCIF Data Bus RCIE DS39632B page 244 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 20 7 ASYNCHRONOUS RECEPTION Start Start RX pin bit bit o bit 1 X SS Vbi 7187 Stop bit foto SG Yoett 78 Stop bit X SS Voit 718 Stop bit i bi Rev Shift Reg Rev Buffer Reg 7 SS A 4 SS Word 1 Le i Read R RCREG Buffer Reg SS SS 7 RCREG RCIF Interrupt Flag SS 5S SS OERR bit SS SS SS s ee amp g Note This
562. ply To avoid this potentially destructive shoot through current from flowing during switching turning on either of the power switches is normally delayed to allow the other switch to completely turn off In the Half Bridge Output mode a digitally program mable dead band delay is available to avoid shoot through current from destroying the bridge power switches The delay occurs at the signal transi tion from the non active state to the active state See Figure 16 4 for illustration Bits PDC6 PDCO of the ECCP1DEL register Register 16 2 set the delay period in terms of microcontroller instruction cycles TCY or 4 Tosc These bits are not available on 28 pin devices as the standard CCP module does not support half bridge operation 16 4 7 ENHANCED PWM AUTO SHUTDOWN When ECCP is programmed for any of the Enhanced PWM modes the active output pins may be configured for auto shutdown Auto shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs REGISTER 16 2 A shutdown event can be caused by either of the comparator modules a low level on the RBO AN12 INTO FLTO SDI SDA pin or any combination of these three sources The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit If the voltage exceeds a threshold the comparator switches state and triggers a shutdown Alternatively a digital signal on the INTO pin
563. pt another read or write request ADDR3 ADDRO SPP Endpoint Address bits 1111 Endpoint Address 15 0001 0000 Endpoint Address 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 191 PIC18F2455 2550 4455 4550 TABLE 18 1 REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BitO Values on page SPPCON SPPOWN SPPEN 55 SPPCFG CLKCFG1 CLKCFGO CSEN CLKIEN WS3 WS2 WS1 WS0 55 SPPEPS RDSPP WRSPP _ SPPBUSY ADDR3 ADDR2 ADDR1 ADDRO 55 SPPDATA SPP Data Register 55 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMRIIE 54 IPR SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PORTE RDPU RE3 12 RE26 RE1 RE0 54 Legend unimplemented read as 0 Shaded cells are not used for the Streaming Parallel Port Note 1 Implemented only when Master Clear functionality is disabled MCLRE configuration bit o 2 REG is the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 3 T
564. pty Flag 2004 Microchip Technology Inc Preliminary DS39632B page 247 PIC18F2455 2550 4455 4550 20 3 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit TXSTA lt 7 gt In this mode the data is transmitted in a half duplex manner i e transmission and reception do not occur at the same time When transmitting data the reception is inhibited and vice versa Synchronous mode is entered by setting bit SYNC TXSTA lt 4 gt In addition enable bit SPEN RCSTA lt 7 gt is set in order to configure the TX and RX pins to CK clock and DT data lines respectively The Master mode indicates that the processor trans mits the master clock on the CK line Clock polarity is selected with the SCKP bit BAUDCON lt 4 gt Setting SCKP sets the Idle state on CK as high while clearing the bit sets the Idle state as low This option is provided to support Microwire devices with this module 20 3 1 EUSART SYNCHRONOUS MASTER TRANSMISSION The EUSART transmitter block diagram is shown in Figure 20 3 The heart of the transmitter is the Transmit Serial Shift Register TSR The Shift register obtains its data from the Read Write Transmit Buffer register TXREG The TXREG register is loaded with data in software The TSR register is not loaded until the last bit has been transmitted from the previous load As soon as the last bit is transmitted the TSR is loaded wit
565. r If interrupts are desired set enable bit RCIE If 9 bit reception is desired set bit RX9 If a single reception is required set bit SREN For continuous reception set bit CREN 7 Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set 8 Read the RCSTA register to get the ninth bit if enabled and determine if any error occurred during reception 9 Read the 8 bit received data by reading the OON Go RCREG register 10 If any error occurred clear the error by clearing bit CREN 11 If using interrupts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set 1 Initialize the SPBRGH SPBRG registers for the appropriate baud rate Set or clear the BRG16 bit as required to achieve the desired baud rate 2 Enable the synchronous master serial port by setting bits SYNC SPEN and CSRC FIGURE 20 13 SYNCHRONOUS RECEPTION MASTER MODE SREN oo os oa oi o2oslo4 a oaJosJod oiJo2 os od o calasjas a acfag cdlarlac asjas larloa os a4lar a2las aslarjazjaslaaiar cefos c i m A OBE ZA gt bt2 gt lt bt3 YC O bite gt lt RC6 TX CK pin SCKP o RC6 TX CK pin SCKP 1 Write to bit SREN bit 7 o nd ohn SREN bit CREN bit o RCIF bit Interrupt i a i t t La Read 1 1 1 i RXR
566. r addressing The SFR map remains the same Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode inherent and literal instructions do not change at all Indirect addressing with FSR0 and FSR1 also remain unchanged 5 6 1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair and its associated file operands Under the proper conditions instructions that use the Access Bank that is most bit oriented and byte oriented instructions can invoke a form of indexed addressing using an offset specified in the instruction This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode When using the extended instruction set this addressing mode requires the following The use of the Access Bank is forced a 0 and e The file address argument is less than or equal to 5Fh Under these conditions the file address of the instruc tion is not interpreted as the lower byte of an address used with the BSR in direct addressing or as an 8 bit address in the Access Bank Instead the value is interpreted as an offset value to an address pointer specified by FSR2 The offset and the contents of FSR2 are added to obtain the target address of the operation 5 6 2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructi
567. r the oscillator mode such as OST or PLL timer The INTOSC multiplexer provides the device clock until the primary clock source becomes ready similar to a Two Speed Start up The clock source is then switched to the primary clock indicated by the OSTS bit in the OSCCON register becoming set The Fail Safe Clock Monitor then resumes monitoring the peripheral clock The primary clock source may never become ready during start up In this case operation is clocked by the INTOSC multiplexer The OSCCON register will remain in its Reset state until a power managed mode is entered DS39632B page 294 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 25 4 FSCM TIMING DIAGRAM Sample Clock Device i i Oscillator Clock i I Failure I Output I i I i CM Output j I l Q I Failure i 2 i i Detected OSCFIF l i i 2 CM Test CM Test CM Test Note The device clock is normally at a much higher frequency than the sample clock The relative frequencies in this example have been chosen for clarity 25 4 3 FSCM INTERRUPTS IN POWER MANAGED MODES By entering a power managed mode the clock multiplexer selects the clock source selected by the OSCCON register Fail Safe Clock Monitoring of the power managed clock source resumes in the power managed
568. ral Addressing mode because they require some literal value as an argument Examples include ADDLW and MOVLW which respectively add or move a literal value to the W register Other examples include CALL and GoTo which include a 20 bit program memory address 5 4 2 DIRECT ADDRESSING Direct addressing specifies all or part of the source and or destination address of the operation within the opcode itself The options are specified by the arguments accompanying the instruction In the core PIC18 instruction set bit oriented and byte oriented instructions use some version of direct addressing by default All of these instructions include some 8 bit literal address as their Least Significant Byte This address specifies either a register address in one of the banks of data RAM Section 5 3 4 General Purpose Register File or a location in the Access Bank Section 5 3 3 Access Bank as the data source for the instruction The Access RAM bit a determines how the address is interpreted When a is 1 the contents of the BSR Section 5 3 2 Bank Select Register BSR are used with the address to determine the complete 12 bit address of the register When a is 0 the address is interpreted as being a register in the Access Bank Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode A few instructions such as MOVFF include the entire 12 bit address either s
569. rately in Section 7 0 Data EEPROM Memory 5 1 Program Memory Organization PIC18 microcontrollers implement a 21 bit program counter which is capable of addressing a 2 Mbyte program memory space Accessing a location between the upper boundary of the physically implemented memory and the 2 Mbyte address will return all o s a NOP instruction The PIC18F2455 and PIC18F4455 each have 24 Kbytes of Flash memory and can store up to 12 288 single word instructions The PIC18F2550 and PIC18F4550 each have 32 Kbytes of Flash memory and can store up to 16 384 single word instructions PIC18 devices have two interrupt vectors The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h The program memory maps for PIC18FX455 and PIC18FX550 devices are shown in Figure 5 1 FIGURE 5 1 PROGRAM MEMORY MAP AND STACK FOR PIC18F2455 2550 4455 4550 DEVICES PIC18FX455 PIC18FX550 PC lt 20 0 gt PC lt 20 0 gt CALL RCALL RETURN 21 CALL RCALL RETURN 21 RETFIE RETLW a RETFIE RETLW ADDULNK Stack Level 1 A Stack Level 1 SUBULNK SUBULNK Stack Level 31 Stack Level 31 Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On Chip Program Memory 5FFFh 6000h o Qa N gt o ec z a Read 0 1FFFFFh 200000h
570. rating in Asynchronous mode The auto wake up feature is enabled by setting the WUE bit BAUDCON lt 1 gt Once set the typical receive seguence on RX DT is disabled and the EUSART remains in an ldle state monitoring for a wake up event independent of the CPU mode A wake up event consists of a high to low transition on the RX DT line This coincides with the start of a Sync Break or a Wake up Signal character for the LIN protocol Following a wake up event the module generates an RCIF interrupt The interrupt is generated synchro nously to the Q clocks in normal operating modes Figure 20 8 and asynchronously if the device is in Sleep mode Figure 20 9 The interrupt condition is cleared by reading the RCREG register The WUE bit is automatically cleared once a low to high transition is observed on the RX line following the wake up event At this point the EUSART module is in Idle mode and returns to normal operation This signals to the user that the Sync Break event is over 20 2 4 1 Special Considerations Using Auto Wake up Since auto wake up functions by sensing rising edge transitions on RX DT information with any state changes before the Stop bit may signal a false end of character and cause data or framing errors To work properly therefore the initial character in the trans mission must be all o s This can be 00h 8 bytes for standard RS 232 devices or 000h 12 bits for LIN bus Oscillator start up time
571. ration bit 0 2 RA6 and its associated latch and data direction bits are enabled as I O pins based on oscillator o configuration otherwise they are read as 0 RE3 port bit is available only as an input pin when the MCLRE configuration bit is o These registers and or bits are not implemented on 28 pin devices DS39632B page 262 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 22 0 COMPARATOR MODULE The analog comparator module contains two compara tors that can be configured in a variety of ways The inputs can be selected from the analog inputs multiplexed with pins RAO through RAS as well as the on chip volt age reference see Section 23 0 Comparator Voltage Reference Module The digital outputs normal or inverted are available at the pin level and can also be read through the control register REGISTER 22 1 R 0 R 0 R W 0 The CMCON register Register 22 1 selects the comparator input and output configuration Block diagrams of the various comparator configurations are shown in Figure 22 1 CMCON COMPARATOR CONTROL REGISTER R W 0 R W 0 R W 1 R W 1 R W 1 C2OUT CIOUT C2INV C1INV CIS CM2 CM1 CMO bit 7 bit 7 C20UT Comparator 2 Output bit When C2INV o 1 C2 VIN gt C2 VIN 0 C2 VIN lt C2 VIN When C2INV 1 1 C2 VIN lt C2 VIN 0 C2 VIN gt C2 VIN C1OUT Comparator 1 Output bit When C
572. re used to double buffer the PWM duty cycle This double buffering is essential for glitchless PWM operation When the CCPRxH and 2 bit latch match TMR2 concatenated with an internal 2 bit Q clock or 2 bits of the TMR2 prescaler the CCPx pin is cleared The maximum PWM resolution bits for a given PWM freguency is given by the eguation EGUATION 15 3 PWM Resolution max bits Note If the PWM duty cycle value is longer than the PWM period the CCPx pin will not be cleared TABLE 15 4 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2 44 kHz 9 77 kHz 39 06 kHz 156 25 kHz 312 50 kHz 416 67 kHz Timer Prescaler 1 4 16 16 4 1 1 1 1 PR2 Value FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution bits 10 10 10 8 7 6 58 15 4 3 PWM AUTO SHUTDOWN 15 4 4 SETUP FOR PWM OPERATION CCP1 ONLY The PWM auto shutdown features of the Enhanced CCP module are also available to CCP1 in 28 pin devices The operation of this feature is discussed in detail in Section 16 4 7 Enhanced PWM Auto Shutdown Auto shutdown features are not available for CCP2 The following steps should be taken when configuring the CCP module for PWM operation 1 Set the PWM period by writing to the PR2 register 2 Set the PWM duty cycle by writing to the CCPRXL register and CCPxCON lt 5 4 gt bits 3 Make the CCPx pin an output by clearing the appropriate TRIS bit
573. read through the CMCON register These bits are read only The comparator outputs may also be directly output to the RA4 and RA5 I O pins When enabled multiplexors in the output path of the RA4 and RAS pins will switch and the output of each pin will be the unsynchronized output of the comparator The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications Figure 22 3 shows the comparator output block diagram The TRISA bits will still function as an output enable disable for the RA4 and RAS pins while in this mode The polarity of the comparator outputs can be changed using the C2INV and C1INV bits CMCON lt 5 4 gt Note 1 When reading the Port register all pins configured as analog inputs will read as a Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification 2 Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified 2004 Microchip Technology Inc Preliminary DS39632B page 265 PIC18F2455 2550 4455 4550 FIGURE 22 3 COMPARATOR OUTPUT BLOCK DIAGRAM x Port pins E gt To RA4 or 2 RA5 pin PI D Q Bus CxINV Data Read CMCON s EN CL gt sJ gt a CMIF bit From
574. red when TXREG is written 0 The EUSART transmit buffer is full SSPIF Master Synchronous Serial Port Interrupt Flag bit 1 The transmission reception is complete must be cleared in software 0 Waiting to transmit receive CCP1IF CCP1 Interrupt Flag bit Capture mode 1 TMRI register capture occurred must be cleared in software 0 No TMR1 register capture occurred Compare mode 1 A TMRI register compare match occurred must be cleared in software 0 No TMRI register compare match occurred PWM mode Unused in this mode TMR2IF TMR2 to PR2 Match Interrupt Flag bit 1 TMR2 to PR2 match occurred must be cleared in software 0 No TMR2 to PR2 match occurred TMRI1IF TMR1 Overflow Interrupt Flag bit 1 TMRI register overflowed must be cleared in software 0 TMRI register did not overflow Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 102 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 9 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PIR2 PERIPHERAL INTERRUPT REGUEST FLAG REGISTER 2 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF bit 7 bit 0 OSCFIF Oscillator Fail Interrupt Flag bit 1 System oscillator failed clock input has ch
575. register pair PRODH contains the high byte Both W and f are unchanged None of the Status flags are affected Note that neither Overflow nor Carry is possible in this operation A zero result is possible but not detected If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write register f Data registers PRODH PRODL Example MULWF REG 1 Before Instruction W C4h REG B5h PRODH 8 PRODL o After Instruction w C4h REG B5h PRODH 8Ah PRODL 94h DS39632B page 328 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 NEGF Negate f Syntax NEGF f a Operands 0 lt f lt 255 a e 0 1 Operation f 1 gt f Status Affected N OV C DC Z Encoding 0110 110a ffff PEF Description Location f is negated using two s complement The result is placed in the data memory location f If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extende
576. rite protected bit 1 WRT1 Write Protection bit 1 Block 1 002000 003FFFh not write protected 0 Block 1 002000 003FFFh write protected bit 0 WRTO Write Protection bit 1 Block 0 000800 001 FFFh not write protected 0 Block 0 000800 001 FFFh write protected Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state REGISTER 25 10 CONFIG6H CONFIGURATION REGISTER 6 HIGH BYTE ADDRESS 30000Bh R C 1 R C 1 R 1 U 0 U 0 U 0 U 0 U 0 WRTD WRTB WRTCU bit 7 bit 0 bit 7 WRTD Data EEPROM Write Protection bit 1 Data EEPROM not write protected 0 Data EEPROM write protected bit 6 WRTB Boot Block Write Protection bit 1 Boot block 000000 0007FFh not write protected 0 Boot block 000000 0007FFh write protected bit 5 WRTC Configuration Register Write Protection bit 1 Configuration registers 300000 3000FFh not write protected 0 Configuration registers 300000 3000FFh write protected Note 1 This bit is read only in normal execution mode it can be written only in Program mode bit 4 0 Unimplemented Read as Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state DS39632B page 288 Preliminary 2004 Microchip Technology Inc PIC
577. rotected 0 Block 0 000800 001FFFh code protected Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state CONFIG5H CONFIGURATION REGISTER 5 HIGH BYTE ADDRESS 300009h R C 1 R C 1 U 0 U 0 U 0 U 0 U 0 U 0 CPD CPB bit 7 bit 0 CPD Data EEPROM Code Protection bit 1 Data EEPROM not code protected 0 Data EEPROM code protected CPB Boot Block Code Protection bit 1 Boot block 000000 0007FFh not code protected 0 Boot block 000000 0007FFh code protected Unimplemented Read as Legend R Readable bit C Clearable bit U Unimplemented bit read as n Value when device is unprogrammed u Unchanged from programmed state 2004 Microchip Technology Inc Preliminary DS39632B page 287 PIC18F2455 2550 4455 4550 REGISTER 25 9 CONFIG6L CONFIGURATION REGISTER 6 LOW BYTE ADDRESS 30000Ah U 0 U 0 U 0 U 0 R C 1 R C 1 R C 1 R C 1 WRT30 WRT2 WRT1 WRTO bit 7 bit 0 bit 7 4 Unimplemented Read as bit 3 WRT3 Write Protection bit 1 Block 3 006000 007FFFh not write protected 0 Block 3 006000 007FFFh write protected Note 1 Unimplemented in PIC18FX455 devices maintain this bit set bit 2 WRT2 Write Protection bit 1 Block 2 004000 005FFFh not write protected 0 Block 2 004000 005FFFh w
578. rted by writing the data to the SPPDATA register The SPPBUSY bit indicates the status of the address and the data write cycles The following is an example write sequence 1 Write the 4 bit address to the SPPEPS register The SPP automatically starts writing the address If address write is not used then skip to step 3 2 Monitor the SSPBUSY bit to determine when the address has been sent The duration depends on the wait states 3 Write the data to the SPPDATA register The SPP automatically starts writing the data 4 Monitor the SSPBUSY bit to determine when the data has been sent The duration depends on the wait states 5 Go back to steps 1 or 3 to write a new address or data Note The SSPBUSY bit should be polled to make certain that successive writes to the SPPEPS or SPPDATA registers do not overrun the wait time due to the wait state setting TRANSFER OF DATA BETWEEN USB SIE AND SPP Write outbound USB data to SPP or read inbound USB data from SPP Write USB endpoint number to SPP fon Endpoint Address Byte 0 Byte 1 Byte 2 Byte 3 coe Byte n DS39632B page 190 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 18 3 3 READING FROM THE SPP 3 Read the data from the SPPDATA register the Reading from the SPP involves reading the SPPDATA data from the previous read operation is register Reading the register the
579. ruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity 01 Q2 03 Q4 Decode Read Process Write to register f Data destination Example INCF CNT 1 0 Before Instruction CNT FFh Z 0 C ro DC 72 After Instruction CNT 0h Z 1 C DC Al DS39632B page 322 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 INCFSZ Increment f Skip if 0 INFSNZ Increment f Skip if not 0 Syntax INCFSZ f d a Syntax INFSNZ f d a Operands O lt f lt 255 Operands 0 lt f lt 255 de 0 1 de 0 1 ae 0 1 ae 0 1 Operation f 1 gt dest Operation ee m sds skip if result 0 Pp result 0 Status Affected None ASIE Nong Encoding 0100 10da ETEF FETE Encoding 0011 11da PET fETT va Me a Description The contents of register f are Description The contents of register f are incremented If d is 0 the result is incremented If d is o the result is placed in W If d is 1 the result is Placed in Mv I d iS s Me Tesut i placed back in register f default placed back in register f default If the result is not 0 the next If the result
580. ructure known as the Buffer Descriptor Table BD T This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration The BDT is composed of Buffer Descriptors BD which are used to define and control the actual buffers in the USB RAM space Each BD in turn consists of four reg isters where n represents one of the 64 possible BDs range of 0 to 63 BDnSTAT BD Status register BDnCNT BD Byte Count register BDnADRL BD Address Low register BDnADRH BD Address High register BDs always occur as a four byte block in the sequence BDnSTAT BDnCNT BDnADRL BDnADRH The address of BDnSTAT is always an offset of 4n 1 in hexa decimal from 400h with n being the buffer descriptor number Depending on the buffering configuration used Section 17 4 4 Ping Pong Buffering there are up to 32 33 or 64 sets of buffer descriptors At a minimum the BDT must be at least 8 bytes long This is because the USB specification mandates that every device must have Endpoint 0 with both input and output for initial setup Depending on the endpoint and buffering configuration the BDT can be as long as 256 bytes Although they can be thought of as special function control registers the Buffer Descriptor Status and Address registers are not hardware mapped as con ventional microcontroller SFRs in Bank 15 are If the endpoint corresponding to a particular BD is not enabled i
581. rupt will not be generated until the IRVST bit is set 24 3 Current Consumption When the module is enabled the HLVD comparator and voltage divider are enabled and will consume static current The total current consumption when enabled is specified in electrical specification parameter DO22 Section 28 2 DC Characteristics FIGURE 24 2 Depending on the application the HLVD module does not need to be operating constantly To decrease the current reguirements the HLVD circuitry may only need to be enabled for short periods where the voltage is checked After doing the check the HLVD module may be disabled 24 4 HLVD Start up Time The internal reference voltage of the HLVD module specified in electrical specification parameter D420 see Table 28 6 in Section 28 0 Electrical Characteris tics may be used by other internal circuitry such as the Programmable Brown out Reset If the HLVD or other circuits using the voltage reference are disabled to lower the device s current consumption the reference voltage circuit will require time to become stable before a low or high voltage condition can be reliably detected This start up time TIRVST is an interval that is indepen dent of device clock speed It is specified in electrical specification parameter 36 Table 28 12 The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached For this reason brief excursions beyo
582. rupts The return from interrupt instruction RETFIE exits the interrupt routine and sets the GIE bit GIEH or GIEL if priority levels are used which re enables interrupts For external interrupt events such as the INT pins or the PORTB input change interrupt the interrupt latency will be three to four instruction cycles The exact latency is the same for one or two cycle instructions Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit Note Donotuse the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled Doing so may cause erratic microcontroller behavior 9 1 USB Interrupts Unlike other peripherals the USB module is capable of generating a wide range of interrupts for many types of events These include several types of normal commu nication and status events and several module level error events To handle these events the USB module is equipped with its own interrupt logic The logic functions in a manner similar to the microcontroller level interrupt fun nel with each interrupt source having separate flag and enable bits All events are funneled to a single device level interrupt USBIF PIR2 lt 5 gt Unlike the device level interrupt logic the individual USB interrupt events cannot be individually assigned their own priority This is determined at the device level interrupt funnel for all
583. ry space In fact it belongs to the configuration memory space 300000h 3FFFFFh which can only be accessed using table reads and table writes Configuration Bits Programming the configuration registers is done in a manner similar to programming the Flash memory The WR bit in the EECON1 register starts a self timed write to the configuration register In normal operation mode a TBLWT instruction with the TBLPTR pointing to the configuration register sets up the address and the data for the configuration register write Setting the WR bit starts a long write to the configuration register The configuration registers are written a byte at a time To write or erase a configuration cell a TBLWT instruction can write a 1 or a 0 into the cell For additional details on Flash programming refer to Section 6 5 Writing to Flash Program Memory TABLE 25 1 CONFIGURATION BITS AND DEVICE IDs Default File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed Value 300000h CONFIGIL USBDIV CPUDIV1 CPUDIVO PLLDIV2 PLLDIV1 PLLDIVO 00 0000 300001h CONFIG1H IESO FCMEN FOSC3 FOSC2 FOSC1 FOSCO 00 010 300002h CONFIG2L VREGEN BORV1 BORVO BOREN1 BORENO PWRTEN 01 1 300003h CONFIG2H WDTPS3 WDTPS2 WDTPS1 WDTPSO WDTEN 1 1 300005h CONFIG3H MCLRE
584. ry write and erase sequences Reading EECON2 will read all o s The EEPGD control bit determines if the access will be a program or data EEPROM memory access When clear any subsequent operations will operate on the data EEPROM memory When set any subsequent operations will operate on the program memory The CFGS control bit determines if the access will be to the configuration calibration registers or to program memory data EEPROM memory When set subsequent operations will operate on configuration registers regardless of EEPGD see Section 25 0 Special Features of the CPU When clear memory selection access is determined by EEPGD The FREE bit when set will allow a program memory erase operation When FREE is set the erase operation is initiated on the next WR command When FREE is clear only writes are enabled The WREN bit when set will allow a write operation On power up the WREN bit is clear The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete Note During normal operation the WRERR is read as 1 This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly The WR control bit initiates write operations The bit cannot be cleared only set in software it is cleared in hardware at the completion of the write operation
585. s Other features include auto shutdown for disabling PWM outputs on interrupt or other select conditions and auto restart to reactivate outputs once the condition has cleared e Enhanced Addressable USART This serial communication module is capable of standard RS 232 operation and provides support for the LIN bus protocol Other enhancements include Automatic Baud Rate Detection and a 16 bit Baud Rate Generator for improved resolution When the microcontroller is using the internal oscillator block the EUSART provides stable operation for applications that talk to the outside world without using an external crystal or its accompanying power requirement e 10 bit A D Converter This module incorporates programmable acquisition time allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus reducing code overhead e Dedicated ICD ICSP Port These devices introduce the use of debugger and programming pins that are not multiplexed with other micro controller features Offered as an option in select packages this feature allows users to develop I O intensive applications while retaining the ability to program and debug in the circuit 1 3 Details on Individual Family Members Devices in the PIC18F2455 2550 4455 4550 family are available in 28 pin and 40 44 pin packages Block diagrams for the two groups are shown in Figure 1 1 and Figure 1 2 The devices are differentiate
586. s 10 TosH2ckL OSC1 T to CLKO 75 200 ns Note 1 11 TosH2ckH OSC1 T to CLKO T 75 200 ns Note 1 12 TckR CLKO Rise Time 35 100 ns Note 1 13 TckF CLKO Fall Time 35 100 ns Note 1 14 TckL2ioV CLKO J to Port Out Valid 05 TCY 20 ns Note 1 15 TioV2ckH Port In Valid before CLKO T 0 25 TCY 25 ns Note 1 16 TckH iol Port In Hold after CLKO T 0 ns Note 1 17 TosH2ioV OSC1 1 Q1 cycle to Port Out Valid 50 150 ns 18 TosH2iol OSC1 T Q2 cycle to PIC18FXXXX 100 ns 18A Port Input Invalid PIC18LFXXXX 200 ns Vpp 2 0V I O in hold time 19 TioV20sH Port Input Valid to OSC1 T I O in setup time 0 ns 20 TioR Port Output Rise Time PIC18FXXXX 10 25 ns 20A PIC18LFXXXX 60 ns VDD 2 0V 21 TioF Port Output Fall Time PIC18FXXXX 10 25 ns 21A PIC18LFXXXX 60 ns VDD 2 0V 221 TINP INT pin High or Low Time Toy ns 23T TRBP RB7 RB4 Change INT High or Low Time TCY ns T These parameters are asynchronous events not related to any internal clock edges Note 1 Measurements are taken in RC mode where CLKO output is 4 x TOSC DS39632B page 378 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 FIGURE 28 7 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING VDD i K _ gt MCLR N Internal lt 30
587. s becomes ready see Figure 3 6 or it will be clocked from the internal oscillator block if either the Two Speed Start up or the Fail Safe Clock Monitor are enabled see Section 25 0 Special Features of the CPU In either case the OSTS bit is set when the primary clock is providing the device clocks The IDLEN and SCS bits are not affected by the wake up FIGURE 3 5 3 4 Idle Modes The Idle modes allow the controllers CPU to be selectively shut down while the peripherals continue to operate Selecting a particular Idle mode allows users to further manage power consumption If the IDLEN bit is set to a 1 when a SLEEP instruction is executed the peripherals will be clocked from the clock source selected using the SCS1 SCSO0 bits however the CPU will not be clocked The clock source status bits are not affected Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode If the WDT is selected the INTRC source will continue to operate If the Timer1 oscillator is enabled it will also continue to run Since the CPU is not executing instructions the only exits from any of the Idle modes are by interrupt WDT time out or a Reset When a wake event occurs CPU execution is delayed by an interval of Tcsp parameter 38 Table 28 12 while it becomes ready to execute code When the CPU begins executing code it resumes with the same clock source
588. s INTOSC and INTOSC postscaler as well as the INTRC source 2004 Microchip Technology Inc Preliminary DS39632B page 35 PIC18F2455 2550 4455 4550 3 1 3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source This formula assumes that the new clock source is stable Three bits indicate the current clock source and its status They are OSTS OSCCON lt 3 gt IOFS OSCCON lt 2 gt e TIRUN T1CON lt 6 gt In general only one of these bits will be set while in a given power managed mode When the OSTS bit is set the primary clock is providing the device clock When the IOFS bit is set the INTOSC output is provid ing a stable 8 MHz clock source to a divider that actually drives the device clock When the T1RUN bit is set the Timer1 oscillator is providing the clock If none of these bits are set then either the INTRC clock source is clocking the device or the INTOSC source is not yet stable If the internal oscillator block is configured as the primary clock source by the FOSC3 FOSCO con figuration bits then both the OSTS and IOFS bits may be set when in PRI RUN or PRI_IDLE modes This indicates that the primary clock INTOSC output is generating a stable 8 MHz output Entering another RC power managed mode at the same frequency would clear the OSTS bit Note 1 Cau
589. s Register 53 EEDATA EEPROM Data Register 53 EECON2 EEPROM Control Register 2 not a physical register 53 EECON1 EEPGD CFGS FREE WRERR WREN WR RD 53 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 54 Legend unimplemented read as o Shaded cells are not used during Flash EEPROM access 2004 Microchip Technology Inc Preliminary DS39632B page 93 PIC18F2455 2550 4455 4550 NOTES AEO O rr r sss r c s F np DS39632B page 94 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 8 0 8x8HARDWARE MULTIPLIER 8 1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU The multiplier performs an unsigned operation and yields a 16 bit result that is stored in the product register pair PRODH PRODL The multiplier s operation does not affect any flags in the Status register Making multiplication a hardware operation allows it to be completed in a single instruction cycle This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applica tions previously reserved for digital signal processors A comparison of various hardware and software multiply operations along with the savings in memory and execut
590. s allowed to float high a bus collision occurs This is another case of another master attempting to drive a data o Figure 19 32 FIGURE 19 31 BUS COLLISION DURING A STOP CONDITION CASE 1 TBRG TBRG TBRG SDA sampled low after TBRG da ea RES MERE N set BCLIF SDA SDA asserted low SCL PEN BCLIF P 0 SSPIF o FIGURE 19 32 BUS COLLISION DURING A STOP CONDITION CASE 2 TBRG TBRG TBRG SDA N Assert SDA SOL goes low before SDA goes high S set BOLIF SOL PEN BCLIF P 0 SSPIF 0 2004 Microchip Technology Inc Preliminary DS39632B page 231 PIC18F2455 2550 4455 4550 TABLE 19 4 REGISTERS ASSOCIATED WITH I2C OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIEU ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMRSIF CCP2IF 54 PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMRSIE CCP2IE 54 IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 54 TRISC TRISC7 TRISC6 TRISC2 TRISC1 TRISCO 54 TRISD T
591. s is given in Table 5 1 and Table 5 2 The SFRs can be classified into two sets those associated with the core device functionality ALU Resets and interrupts and those related to the peripheral functions The Reset and interrupt registers are described in their respective chapters while the ALU s Status register is described later in this section Registers related to the operation of a peripheral feature are described in the chapter for that peripheral The SFRs are typically distributed among the peripherals whose functions they control Unused SFR locations are unimplemented and read as 0 s SPECIAL FUNCTION REGISTER MAP FOR PIC18F2455 2550 4455 4550 DEVICES TABLE 5 1 Address Name Address Name Address FFFh TOSU FDFh INDF2 FBFh FFEh TOSH FDEh POSTINC2 FBEh FFDh TOSL FDDh POSTDEC2 FBDh FFCh STKPTR FDCh PREINC2 FBCh FFBh PCLATU FDBh PLUSW2 FBBh FFAh PCLATH FDAh FSR2H FBAh FF9h PCL FD9h FSR2L FB9h FF8h TBLPTRU FD8h STATUS FB8h FF7h TBLPTRH FD7h TMROH FB7h FF6h TBLPTRL FD6h TMROL FB6h FF5h TABLAT FD5h TOCON FB5h FF4h PRODH FD4h 2 FB4h FF3h PRODL FD3h OSCCON FB3h FF2h INTCON FD2h HLVDCON FB2h FFlh INTCON2 FDih WDTCON FB1h FFOh INTCON3 FD0h RCON FBOh FEFh INDFO
592. s using the same timer as a time base Compare Compare Either module can be configured for the special event trigger to reset the time base Automatic A D conversions on CCP2 trigger event can be done Conflicts may occur if both modules are using the same time base Capture PWM None Compare PWM None PwM0 Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate TMR2 interrupt Note 1 Includes standard and Enhanced PWM operation DS39632B page 142 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 15 2 Capture Mode In Capture mode the CCPRxH CCPRxL register pair captures the 16 bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin An event is defined as one of the following e every falling edge every rising edge every 4th rising edge e every 16th rising edge The event is selected by the mode select bits COPxM3 CCPxMO CCPxCON lt 3 0 gt When a capture is made the interrupt request flag bit CCPxIF is set it must be cleared in software If another capture occurs before the value in register CCPRx is read the old captured value is overwritten by the new captured value 15 2 1 CCP PIN CONFIGURATION In Capture mode the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit Note If RB3 CCP2 or RC1 CCP2 is configured as an output
593. sable interrupts MOVLW 55h Required MOVWF EECON2 write 55h Sequence MOVLW OAAh MOVWF EECON2 write OAAh BSF EECON1 WR start erase CPU stall BSF INTCON GIE re enable interrupts TBLRD Gummy read decrement MOVLW BUFFER ADDR HIGH point to buffer MOVWF FSROH MOVLW BUFFER ADDR LOW MOVWF FSROL MOVLW DEZI MOVWF COUNTER1 WRITE BUFFER BACK MOVLW D 32 number of bytes in holding register MOVWF COUNTER WRITE BYTE TO HREGS MOVF POSTINCO W get low byte of buffer data MOVWF TABLAT present data to table latch TBLWT write data perform a short write to internal TBLWT holding register DECFSZ COUNTER loop until buffers are full BRA WRITE WORD TO HREGS DS39632B page 86 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 EXAMPLE 6 3 WRITING TO FLASH PROGRAM MEMORY CONTINUED PROGRAM MEMORY BSF EECON1 EEPGD point to Flash program memory BCF EECON1 CFGS access Flash program memory BSF EECON1 WREN enable write to memory BCF INTCON GIE disable interrupts MOVLW Sila Required MOVWF EECON2 write 55h Sequence MOVLW OAAh MOVWF EECON2 write OAAh BSF EECON1 WR j Start program CPU stall DECFSZ COUNTER1 BRA WRITE BUFFER BACK BSF INTCON GIE re enable interrupts BCF EECON1 WREN disable write to memory 6 5 2 WRITE VERIFY 6 5 4 PROTECTION AGAINST SPURIOUS Depending on the application good programming practice may dictate that the value written
594. ser code execution BCF EECON1 WREN Disable writes on write complete EEIF set 2004 Microchip Technology Inc Preliminary DS39632B page 91 PIC18F2455 2550 4455 4550 7 5 Data EEPROM memory has its own code protect bits in Configuration Words External read and write operations are disabled if code protection is enabled Operation During Code Protect The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code protect configuration bit Refer to Section 25 0 Special Features of the CPU for additional information 7 6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory To protect against spurious EEPROM writes various mechanisms have been implemented On power up the WREN bit is cleared In addition writes to the EEPROM are blocked during the Power up Timer period TPWRT parameter 33 Table 28 12 The write initiate sequence and the WREN bit together help prevent an accidental write during brown out power glitch or software malfunction 7 7 Using the Data EEPROM The data EEPROM is a high endurance byte address able array that has been optimized for the storage of frequently changing information e g program variables or other data that are updated often Frequently changing values will typically be updated more often than specification D124 or D124A If this is
595. set hours to 1 MOVWF hours RETURN Done TABLE 12 2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER COUNTER Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRIIF 54 PIE1 SPPIE ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIPU ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRAIP 54 TMRIL Timer1 Register Low Byte 92 TMR1H Tlmer1 Register High Byte 92 T1CON RD16 TIRUN T1CKPS1 TICKPSO TIOSCEN TISYNC TMR1CS TMR1ON 52 Legend unimplemented read as 0 Shaded cells are not used by the Timer1 module Note 1 These bits are unimplemented on 28 pin devices always maintain these bits clear 2004 Microchip Technology Inc Preliminary DS39632B page 133 PIC18F2455 2550 4455 4550 NOTES DS39632B page 134 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 13 0 TIMER2 MODULE The Timer2 module timer incorporates the following features 8 bit timer and period registers TMR2 and PR2 respectively e Readable and writable both registers Software programmable prescaler 1 1 1 4 and 1 16 Software programmable postscaler 1 1 through 1 16 Interrupt on TMR2 to PR2 match Optional use as the shift clock for the MSSP module The module is controlled through the T2CON register Register 13 1 which enables or disa
596. set value is not bracketed When the extended instruction set is enabled brackets are also used to indicate index arguments in byte oriented and bit oriented instructions This is in addition to other changes in their syntax For more details see Section 26 2 3 1 Extended Instruction Syntax with Standard PIC18 Commands Note In the past square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets In this text and going forward optional arguments are denoted by braces TABLE 26 3 EXTENSIONS TO THE PIC18 INSTRUCTION SET 16 Bit Instruction Word Mnemonic Description Cycles Status Operands MSb LSb Affected ADDFSR f k Add literal to FSR 1 1110 1000 ffkk kkkk None ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None MOVSF Zs fg Move z source to 1st word 2 1110 1011 Ozzz zzzz None fa destination 2nd word 1111 ffff ffff ffff MOVSS Zs Zg Move z source to 1st word 2 1110 1011 1222 zzzz None Za destination 2nd word 1111 XXXX XZZZ ZZZZ PUSHL k Store literal at FSR2 1 1110 1010 kkkk kkkk None decrement FSR2 SUBFSR f k Subtract literal from FSR 1 1110 1001 ffkk kkkk None SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None return 2004 Microchip Technology Inc Preliminary DS39632B page 343 PIC18F2455 2550 4455 4550
597. source is one of the comparators the shutdown condition is a level The ECCPASE bit cannot be cleared as long as the cause of the shutdown persists The Auto Shutdown mode can be forced by writing a 1 to the ECCPASE bit FIGURE 16 10 16 4 8 START UP CONSIDERATIONS When the ECCP module is used in the PWM mode the application hardware must use the proper external pull up and or pull down resistors on the PWM output pins When the microcontroller is released from Reset all of the I O pins are in the high impedance state The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I O pins with the proper signal levels or activates the PWM output s The CCP1M1 CCP1MO bits CCP1CON lt 1 0 gt allow the user to choose whether the PWM output signals are active high or active low for each pair of PWM output pins P1A P1C and P1B P1D The PWM output polarities must be selected before the PWM pins are configured as outputs Changing the polarity configura tion while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits The P1A P1B P1C and P1D output latches may not be in the proper states when the PWM module is initialized Enabling the PWM pins for output at the same time as the ECCP module may cause damage to the applica tion circuit The ECCP module must be enabled in the proper output mode and comp
598. ss PC 4 is pushed onto the return stack If s 1 the W Status and BSR registers are also pushed into their respective shadow registers WS STATUSS and BSRS If s 0 no update occurs default Then the 20 bit value k is loaded into PC lt 20 1 gt CALL is a two cycle instruction Words 2 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read literal Push PC to Read literal K lt 7 0 gt stack K lt 19 8 gt Write to PC No No No No operation operation operation operation Example HERE CALL THERE 1 Before Instruction PC address HERE After Instruction PC address THERE TOS address HERE 4 WS W BSRS BSR STATUSS Status DS39632B page 316 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 CLRF Clear f Syntax CLRF f a Operands 0 lt f lt 255 ae 0 1 Operation 000h f 1 gt Z Status Affected Z Encoding 0110 101a fffft fffft Description Clears the contents of the specified register If a is o the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q
599. ssary overwriting the original BD values The BDnSTAT register is updated by the SIE with the token PID and the transfer count BDnCNT is updated 2004 Microchip Technology Inc Preliminary DS39632B page 171 PIC18F2455 2550 4455 4550 The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint The SIE will clear the UOWN bit when a transaction has completed The only exception to this is when KEN is enabled and or BSTALL is enabled No hardware mechanism exists to block access when the UOWN bit is set Thus unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it Similarly reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller 17 41 2 BDnSTAT Register CPU Mode When UOWN o the microcontroller core owns the BD At this point the other seven bits of the register take on control functions The Keep Enable bit KEN BDnSTAT lt 5 gt determines if a BD stays enabled If the bit is set once the UOWN bit is set it will remain owned by the SIE independent of the endpoint activity This prevents the USTAT FIFO from being updated as well as the transaction com plete interrupt from being set for the endpoint This fea ture should only be enabled when the Streaming Parallel Port is selected as the data I O channel instead of USB RAM The Address Increment Disable bit
600. ster NA 51 73 POSTINCI Uses contents of FSR1 to address data memory value of FSR1 post incremented not a physical register N A 51 74 POSTDEC1 Uses contents of FSR1 to address data memory value of FSR1 post decremented not a physical register N A 51 74 PREINC1 Uses contents of FSR1 to address data memory value of FSR1 pre incremented not a physical register N A 51 74 PLUSW1 Uses contents of FSR1 to address data memory value of FSR1 pre incremented not a physical register N A 51 74 value of FSR1 offset by W FSR1H Indirect Data Memory Address Pointer 1 High Byte 0000 51 73 FSRIL Indirect Data Memory Address Pointer 1 Low Byte XXXX xxxx 51 73 BSR Bank Select Register 0000 52 63 INDF2 Uses contents of FSR2 to address data memory value of FSR2 not changed not a physical register NA 52 73 POSTINC2 Uses contents of FSR2 to address data memory value of FSR2 post incremented not a physical register N A 52 74 POSTDEC2 Uses contents of FSR2 to address data memory value of FSR2 post decremented not a physical register N A 52 74 PREINC2 Uses contents of FSR2 to address data memory value of FSR2 pre incremented not a physical register N A 52 74 PLUSW2 Uses contents of FSR2 to address data memory value of FSR2 pre incremented not a physical register N A 52 74 value of FSR2 offset by W FSR2H Indirect Data Memory Address Pointer 2 High Byte 0000 52
601. struction Set enabled enabled enabled enabled Packages 28 pin PDIP 28 pin PDIP 40 pin PDIP 40 pin PDIP 28 pin SOIC 28 pin SOIC 44 pin QFN 44 pin QFN 44 pin TQFP 44 pin TQFP 2004 Microchip Technology Inc Preliminary DS39632B page 9 PIC18F2455 2550 4455 4550 FIGURE 1 1 PIC18F2455 2550 28 PIN BLOCK DIAGRAM Data Bus lt 8 gt Table Pointer lt 21 gt PORTA i Dataran kD RAO ANO inc dec logic 8 78 RA1 AN1 Data Memory He X RA2 AN2 VREF CVREF 2 Kbytes RA3 AN3 VREF 21 Pomp Es ST RA4 TOCKI C1OUT RCV 20 f Address Latch RA5 AN4 SS HLVDIN C2OUT PCU PCH PCL gt OSC2 CLKO RA6 Program Counter 12 t Data Address lt 12 gt 31 Level Stack Address Latch 4 12 4 Program Memory STKPTR BSR FSRO fen 24 32 Kbytes FSR1 Data Latch FSR2 12 PORTB RBO AN12 INTO FLTO SDI SDA inc dec RB1 AN10 INT1 SCK SCL Table Latch logic RB2 AN8 INT2 VMO A RB3 AN9 CCP28 VPO RB4 AN11 KBIO ROM Latch gt Address RB5 KBI1 PGM Instruction Bus lt 16 gt Decode X RB6 KBI2 PGC RB7 KBI3 PGD t Instruction gt State Machine
602. stscaler options As configuration bits these are set when the device is programmed and left in that configuration until the device is reprogrammed The OSCCON register Register 2 2 selects the Active Clock mode it is primarily used in controlling clock switching in power managed modes Its use is discussed in Section 2 4 1 Oscillator Control Register The OSCTUNE register Register 2 1 is used to trim the INTRC frequency source as well as select the low frequency clock source that drives several special features Its use is described in Section 2 2 5 2 OSCTUNE Register 2 2 Oscillator Types PIC18F2455 2550 4455 4550 devices can be operated in twelve distinct oscillator modes In contrast with pre vious PIC18 enhanced microcontrollers four of these modes involve the use of two oscillator types at once Users can program the FOSC3 FOSCO configuration bits to select one of these modes 1 XT Crystal Resonator 2 XTPLL Crystal Resonator with PLL enabled 3 HS High Speed Crystal Resonator 4 HSPLL High Speed Crystal Resonator with PLL enabled 5 EC External Clock with Fosc 4 output 6 ECIO External Clock with I O on RA6 7 ECPLL External Clock with PLL enabled and Fosc 4 output on RA6 8 ECPIO External Clock with PLL enabled O on RA6 9 INTHS lnternal Oscillator used as microcontroller clock source HS Oscillator used as USB clock source 10 INTXT Internal Oscillator used as microcontroller clock source
603. t Q D EN RD Port gt Note 1 Opins have diode protection to VDD and Vss 10 1 PORTA TRISA and LATA Registers PORTA is an 8 bit wide bidirectional port The corre sponding data direction register is TRISA Setting a TRISA bit 1 will make the corresponding PORTA pin an input i e put the corresponding output driver in a high impedance mode Clearing a TRISA bit 0 will make the corresponding PORTA pin an output i e put the contents of the output latch on the selected pin Reading the PORTA register reads the status of the pins writing to it will write to the port latch The Data Latch register LATA is also memory mapped Read modify write operations on the LATA register read and write the latched output value for PORTA The RA4 pin is multiplexed with the TimerO module clock input to become the RA4 TOCKI pin The RA6 pin is multiplexed with the main oscillator pin it is enabled as an oscillator or O pin by the selection of the main oscillator in Configuration Register 1H see Section 25 1 Configuration Bits for details When not used as a port pin RA6 and its associated TRIS and LAT bits are read as 0 RA4 is also multiplexed with the USB module it serves as a receiver input from an external USB transceiver For details on configuration of the USB module see Section 17 2 USB Status and Control Several PORTA pins are multiplexed with analog inputs the analo
604. t If such acts allow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WAR RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip s products as critical components in life support systems is not authorized except with express written approval by Microchip No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELoQ microID MPLAB PIC PICmicro PICSTART PRO MATE PowerSmart rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AmpLab FilterLab Migratable Memory MXDEV MXLAB PICMASTER SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated i
605. t as outputs RE lt 2 gt as inputs 10 5 1 PORTE IN 28 PIN DEVICES For 28 pin devices PORTE is only available when Master Clear functionality is disabled MCLRE o In these cases PORTE is a single bit input only port comprised of RES only The pin operates as previously described R 0 U 0 U 0 U 0 R W 1 R W 1 R W 1 R W 1 RDPU RE3 2 RE20 RE1 REO bit 7 bit 0 bit 7 RDPU PORTD Pull up Enable bit 1 PORTD pull ups are enabled by individual port latch values 0 All PORTD pull ups are disabled bit 6 4 Unimplemented Read as bit 3 0 RE3 REO PORTE Data Input bits 1 2 Note 1 Implemented only when Master Clear functionality is disabled MCLRE configuration bit 0 otherwise read as 0 2 RE3 is the only PORTE bit implemented on both 28 pin and 40 44 pin devices All other bits are implemented only when PORTE is implemented i e 40 44 pin devices 3 Unimplemented in 28 pin devices read as 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 123 PIC18F2455 2550 4455 4550 TABLE 10 9 PORTE I O SUMMARY Pin Function Saind VO 1 0 Type Description REO AN5 REO 0 OUT DIG LATE
606. t 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIEU ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMRIIP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 TXREG EUSART Transmit Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented read as 0 Shaded cells are not used for synchronous master transmission Note 1 Reserved in 28 pin devices always maintain these bits clear 2004 Microchip Technology Inc Preliminary DS39632B page 249 PIC18F2455 2550 4455 4550 20 3 2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected reception is enabled by setting either the Single Receive Enable bit SREN ROSTA lt 5 gt or the Continuous Receive Enable bit CREN RCSTA lt 4 gt Data is sampled on the RX pin on the falling edge of the clock If enable bit SREN is set only a single word is received If enable bit CREN is set the reception is continuous until CREN is cleared If both bits are set then CREN takes precedence To set up a Synchronous Master Reception Ensure bits CREN and SREN are clea
607. t and configures these pins as I O port pins Note When enabled these pins must be properly configured as input or output bit 4 CKP Clock Polarity Select bit 1 Idle state for clock is a high level 0 Idle state for clock is a low level bit 3 0 SSPM3 SSPMO Synchronous Serial Port Mode Select bits 0101 SPI Slave mode clock SCK pin SS pin control disabled SS can be used as I O pin 0100 SPI Slave mode clock SCK pin SS pin control enabled 0011 SPI Master mode clock TMR2 output 2 0010 SPI Master mode clock Fosc 64 0001 SPI Master mode clock Fosc 16 0000 SPI Master mode clock Fosc 4 Note Bit combinations not specifically listed here are either reserved or implemented in 12C mode only Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 195 PIC18F2455 2550 4455 4550 19 3 2 OPERATION When initializing SPI operation several options need to be specified This is done by programming the appropriate control bits SSPCON1 lt 5 0 gt and SSPSTAT lt 7 6 gt These control bits allow the following to be specified e Master mode SCK is the clock output Slave mode SCK is the clock input e Clock Polarity Idle state of SCK Data Input Sample Phase middle or end of data output time Clock Edge outpu
608. t data on rising falling edge of SCK e Clock Rate Master mode only e Slave Select mode Slave mode only The MSSP consists of a Transmi Receive Shift register SSP SR and a Buffer register SSPBUF The SSPSR shifts the data in and out of the device MSb first The SSPBUF holds the data that was written to the SSPSR until the received data is ready Once the eight bits of data have been received that byte is moved to the SSPBUF register Then the Buffer Full detect bit BF SSPSTAT lt 0 gt and the interrupt flag bit SSPIF are set This double buffering of the received data SSPBUF allows the next byte to start reception before reading the data that was just received Any write to the SSPBUF register during transmission reception of data will be ignored and the Write Collision detect bit WCOL SSPCON1 lt 7 gt will be set User software must clear the WCOL bit so that it can be determined if the follow ing write s to the SSPBUF register completed successfully When the application software is expecting to receive valid data the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF The Buffer Full bit BF SSPSTAT lt 0 gt indicates when SSPBUF has been loaded with the received data transmission is complete When the SSPBUF is read the BF bit is cleared This data may be irrelevant if the SPlis only a transmitter Generally the MSSP interrupt is used to determine when the transmissi
609. table oscillator operation The user should test the performance of the oscillator over the expected VDD and temperature range for the application See the notes following this table for additional information Crystals Used 4 MHz 8 MHz 20 MHz Typical Capacitor Values Used Mode Freq OSC1 OSC2 XT 4 0 MHZ 33 pF 33 pF HS 8 0 MHz 27 pF 27 pF 16 0 MHz 22 pF 22 pF Capacitor values are for design guidance only These capacitors were tested with the resonators listed below for basic start up and operation These values are not optimized Different capacitor values may be required to produce acceptable oscillator operation The user should test the performance of the oscillator over the expected VDD and temperature range for the application See the notes following Table 2 2 for additional information Note 1 Higher capacitance increases the stability of oscillator but also increases the start up time 2 When operating below 3V VDD or when using certain ceramic resonators at any voltage it may be necessary to use the HS mode or switch to a crystal oscillator 3 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropriate values of external components 4 Rs may be required to avoid overdriving crystals with low drive level specification 5 Always verify oscillator performance over the VDD
610. tal I O RX ST EUSART asynchronous receive DT O ST EUSART synchronous data see TX CK SDO O SPI data out Legend TTL TTL compatible input CMOS CMOS compatible input or output ST Schmitt Trigger input with CMOS levels Input O Output P Power Note 1 Alternate assignment for CCP2 when CCP2MX configuration bit is cleared These Default assignment for CCP2 when CCP2MX configuration bit is set pins are No Connect unless the ICPRT configuration bit is set For NC ICPORTS the pin is No Connect unless ICPRT is set and the DEBUG configuration bit is cleared 2004 Microchip Technology Inc Preliminary DS39632B page 19 PIC18F2455 2550 4455 4550 TABLE 1 3 PIC18F4455 4550 PINOUT O DESCRIPTIONS CONTINUED Pin Name s Pin Buffer Description PDIP QFN TQFP Type Type PORTD is a bidirectional I O port or a Streaming Parallel Port SPP These pins have TTL input buffers when the SPP module is enabled RDO SPPO 19 38 38 RDO O ST Digital I O SPPO O TTL Streaming Parallel Port data RD1 SPP1 20 39 39 RD1 O ST Digital I O SPP1 O TTL Streaming Parallel Port data RD2 SPP2 21 40 40 RD2 O ST Digital I O SPP2 O TTL Streaming Parallel Port data RD3 SPP3 22 41 41 RD3 O ST Digital I O SPP3 O TTL Streaming Parallel Port data RD4 SPP4 27 2 2 RD4 O ST Digital I O SPP4 O TTL Streaming Parallel Port data RD5 SPP5 P1B 28 3 3 RD5 O ST Digital I
611. tatus bit Receive mode only 1 Receive complete SSPBUF is full 0 Receive not complete SSPBUF is empty Legend R Readable bit W Writable bit n Value at POR 1 Bit is set 0 Bit is cleared U Unimplemented bit read as 0 x Bit is unknown DS39632B page 194 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 19 2 SSPCON1 MSSP CONTROL REGISTER 1 SPI MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPMO bit 7 bit 0 bit 7 WCOL Write Collision Detect bit Transmit mode only 1 The SSPBUF register is written while it is still transmitting the previous word must be cleared in software 0 No collision bit 6 SSPOV Receive Overflow Indicator bit SPI Slave mode 1 Anew byte is received while the SSPBUF register is still holding the previous data In case of overflow the data in SSPSR is lost Overflow can only occur in Slave mode The user must read the SSPBUF even if only transmitting data to avoid setting overflow must be cleared in software 0 No overflow Note In Master mode the overflow bit is not set since each new reception and transmission is initiated by writing to the SSPBUF register bit 5 SSPEN Synchronous Serial Port Enable bit 1 Enables serial port and configures SCK SDO SDI and SS as serial port pins 0 Disables serial por
612. te The Streaming Parallel Port is only available on 40 44 pin devices PIC18F4455 4550 USB devices provide a Streaming Parallel Port as a high speed interface for moving data to and from an external system This parallel port operates as a master port complete with chip select and clock outputs to control the movement of data to slave devices Data can be channelled either directly to the USB SIE or to the microprocessor core Figure 18 1 shows a block view of the SPP data path FIGURE 18 1 SPP DATA PATH PIC18F4455 4550 EV EA NE NE TY 7 oe ee ssa CKISPP CK2SPP SPP gt X OESPP Logie gt X CSSPP CPU lt j pX SPP lt 7 0 gt EE NE PE J In addition the SPP can provide time multiplexed addressing information along with the data by using the second strobe output Thus the USB endpoint number can be written in conjunction with the data for that endpoint 18 1 SPP Configuration The operation of the SPP is controlled by two registers SPPCON and SPPCFG The SPPCON register Register 18 1 controls the overall operation of the parallel port and determines if it operates under USB or microcontroller control The SPPCFG register Register 18 2 controls timing configuration and pin outputs 18 1 1 ENABLING THE SPP To enable the SPP set the SPPEN bit SPPCON lt O gt In addition the TRIS bits for the corresponding SPP pins must be properly configured At a minimum e Bits TR
613. ter mode 2C Slave mode 7 bit address 2C Slave mode 10 bit address 12C Slave mode 7 bit address with Start and Stop bit interrupts enabled 2C Slave mode 10 bit address with Start and Stop bit interrupts enabled 2C Firmware Controlled Master mode slave is Idle Selection of any 1 C mode with the SSPEN bit set forces the SCL and SDA pins to be open drain provided these pins are programmed to inputs by setting the appropriate TRISB bits To ensure proper operation of the module pull up resistors must be provided externally to the SCL and SDA pins 19 4 3 SLAVE MODE In Slave mode the SCL and SDA pins must be config ured as inputs TRISB lt 1 0 gt set The MSSP module will override the input state with the output data when required slave transmitter The I C Slave mode hardware will always generate an interrupt on an address match Through the mode select bits the user can also choose to interrupt on Start and Stop bits When an address is matched or the data transfer after an address match is received the hardware automati cally will generate the Acknowledge ACK pulse and load the SSPBUF register with the received value currently in the SSPSR register Any combination of the following conditions will cause the MSSP module not to give this ACK pulse The Buffer Full bit BF SSPSTAT lt 0 gt was set before the transfer was received The overflow bit SSPOV SSPCON1 lt 6 gt was set be
614. ternal USB transceiver VP input RC6 TX CK RC6 0 OUT DIG LATC lt 6 gt data output 1 IN ST PORTC lt 6 gt data input TX 0 OUT DIG Asynchronous serial transmit data output EUSART module takes priority over port data User must configure as output CK 0 OUT DIG Synchronous serial clock output EUSART module takes priority over port data IN ST Synchronous serial clock input EUSART module RC7 RX DT RC7 0 OUT DIG LATC lt 7 gt data output SDO IN ST PORTC lt 7 gt data input RX IN ST Asynchronous serial receive data input EUSART module DT OUT DIG Synchronous serial data output EUSART module takes priority over SPI and port data IN ST Synchronous serial data input EUSART module User must configure as an input SDO 0 OUT DIG SPI data output MSSP module takes priority over port data Legend OUT Output IN Input ANA Analog Signal DIG Digital Output ST Schmitt Buffer Input TTL TTL Buffer Input XCVR USB transceiver x Don t care TRIS bit does not affect port direction or is overridden for this option Note 1 Default pin assignment Alternate pin assignment is RB3 when CCP2MX 0 2 RC4 and RC5 do not have corresponding TRISC bits In Port mode these pins are input only USB data direction is determined by the USB configuration 3 40 44 pin devices only DS39632B page 118 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 10 6 SUMMARY OF REGIS
615. ternal pull up A single control bit RDPU PORTE lt 7 gt can turn on all the pull ups This is performed by setting RDPU The weak pull up is automatically turned off when the port pin is configured as a digital output or as one of the other multiplexed peripherals The pull ups are disabled on a Power on Reset The PORTE register is shown in Section 10 5 PORTE TRISE and LATE Registers Three of the PORTD pins are multiplexed with outputs P1B P1C and PID of the Enhanced CCP module The operation of these additional PWM output pins is covered in greater detail in Section 16 0 Enhanced Capture Compare PWM ECCP Module Note On a Power on Reset these pins are configured as digital inputs PORTD can also be configured as an 8 bit wide Streaming Parallel Port SPP In this mode the input buffers are TTL For additional information on con figuration and uses of the SPP see Section 18 0 Streaming Parallel Port Note When the Enhanced PWM mode is used with either dual or quad outputs the SSP functions of PORTD are automatically disabled EXAMPLE 10 4 INITIALIZING PORTD CLRF PORTD Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data CLRF LATD MOVLW OCFh direction Set RD lt 3 0 gt as inputs RD lt 5 4 gt as outputs RD lt 7 6 gt as inputs MOVWF TRISD
616. terrupt Priority bit 1 High priority 0 Low priority bit 0 TMRIIP TMR1 Overflow Interrupt Priority bit 1 High priority 0 Low priority Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR V Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 106 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 9 9 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IPR2 PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 OSCFIP Oscillator Fail Interrupt Priority bit 1 High priority 0 Low priority CMIP Comparator Interrupt Priority bit 1 High priority 0 Low priority USBIP USB Interrupt Priority bit 1 High priority 0 Low priority EEIP Data EEPROM Flash Write Operation Interrupt Priority bit 1 High priority 0 Low priority BCLIP Bus Collision Interrupt Priority bit 1 High priority 0 Low priority HLVDIP High Low Voltage Detect Interrupt Priority bit 1 High priority 0 Low priority TMRBIP TMR3 Overflow Interrupt Priority bit 1 High priority 0 Low priority CCP2IP CCP2 Interrupt Priority bit 1 High priority 0 Low priority Legend R Readable bit W Writable bit U Unimplemented bit read as n Value at POR Bit is set 0
617. terrupt registers in The USB module can generate multiple interrupt con the USB module The top level consists of overall USB ditions To accommodate all of these interrupt sources status interrupts these are enabled and flagged in the the module is provided with its own interrupt logic UIE and UIR registers respectively The second level structure similar to that of the microcontroller USB consists of USB error conditions which are enabled interrupts are enabled with one set of control registers and flagged in the UEIR and UEIE registers An and trapped with a separate set of flag registers All interrupt condition in any of these triggers a USB Error sources are funneled into a single USB interrupt Interrupt Flag UERRIF in the top level reguest USBIF PIR2 lt 5 gt in the microcontrollers interrupt logic Interrupts may be used to trap routine events in a USB transaction Figure 17 9 shows some common events within a USB frame and their corresponding interrupts FIGURE 17 8 USB INTERRUPT LOGIC FUNNEL Second Level USB Interrupts Top Level USB Interrupts USB Error Conditions USB Status Interrupts UEIR Flag and UEIE Enable Registers UIR Flag and UIE Enable Registers SOFIF 4 SOFIE BTSEF 3 BTSEE TRNIF USBIF TRNIE gt _ gt BTOEF E AEE S IDLEIF DFN8EF D DLEE
618. tes in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity 01 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example 1 SUBWFB REG 1 0 Before Instruction REG M 19h 0001 1001 W ODh 0000 1101 C 1 After Instruction RE OCh 0000 1011 W ODh 0000 1101 C 1 Z 0 N 0 result is positive Example 2 SUBWEB REG 0 0 Before Instruction R 1Bh 0001 1011 w 1Ah 0001 1010 C 0 After Instruction RE 1Bh 0001 1011 W 00h C 1 Z zal result is zero N 0 Example 3 SUBWFB REG 1 0 Before Instruction 03h 0000 0011 W OEh 0000 1101 C 1 After Instruction F5h 1111 0100 2 s comp W 0Eh 0000 1101 C 0 Z 0 N 1 result is negative SWAPF Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Q1 Swap f SWAPF f d a 0 lt f lt 255 de 0 1 ae 0 1 f lt 3 0 gt gt dest lt 7 4 gt f lt 7 4 gt gt dest lt 3 0 gt None 0011 10da F f TEET The upper and lower nibbles of register f are exchanged If is o the result is placed in W If d is 1 the result is placed in register f default If a is 0 the Access Bank is selected If a is 1
619. th MPLAB IDE When the microcontroller has this feature enabled some resources are not available for general use Table 25 4 shows which resources are required by the background debugger To use the In Circuit Debugger function of the micro controller the design must implement In Circuit Serial Programming connections to MCLR VPP RE3 VDD Vss RB7 and RB6 This will interface to the In Circuit Debugger module available from Microchip or one of the third party development tool companies 25 9 Special ICPORT Features Designated Packages Only Under specific circumstances the No Connect NC pins of PIC18F4455 4550 devices in 44 pin TQFP packages can provide additional functionality These features are controlled by device configuration bits and are available only in this package type and pin count 25 9 1 DEDICATED ICD ICSP PORT The 44 pin TQFP devices can use NC pins to provide an alternate port for In Circuit Debugging ICD and In Circuit Serial Programming ICSP These pins are collectively known as the dedicated ICSP ICD port since they are not shared with any other function of the device When implemented the dedicated port activates three NC pins to provide an alternate device Reset data and clock ports None of these ports overlap with standard I O pins making the I O pins available to the users application The dedicated ICSP ICD port is enabled by setting the ICPRT configuration bit The port functions the sa
620. th the eight bit literal k Status Affected GIE GIEH PEIE GIEL The program counter is loaded from the E De top of the stack the return address ncoding 9990 NOOO S 0998 The high address latch PCLATH Description Return from interrupt Stack is popped remains unchanged and Top of Stack TOS is loaded into Words 1 the PC Interrupts are enabled by i setting either the high or low priority Cycles 2 global interrupt enable bit If S 21 the Q Cycle Activity contents of the shadow registers Ws ai a2 a3 Q4 STATUSS and BSRS are loaded into Decod ead P Poo PC f their corresponding registers W ecoge li at M catia op k te Status and BSR If s 0 no update of itera ata stac Wi rite these registers occurs default to Words 4 No No No No oles operation operation operation operation Cycles 2 Q Cycle Activity Example Q1 Q2 Q3 Q4 Decode No No Pop PC from CALL TABLE W contains table operation operation stack Offset value Set GIEH or A GIEL No No No No TABLE operation operation operation operation ADDWF PCL W offset RETLW ko Begin table Example RETFIE RETLW k1 i After Interrupt Aa 2 Ta RETLW kn End of table BSR BSRS Status STATUSS Before Instruction GIE GIEH PEIE GIEL 1 W 07 After Instruction W value of kn DS39632B page 332 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550
621. that a write to Timer1 coincides with a special event trigger the write operation will take precedence Note The special event triggers from the CCP2 module will not set the TMRIIF interrupt flag bit PIR1 lt 0 gt 12 6 Using Timer1 as a Real Time Clock Adding an external LP oscillator to Timer1 such as the one described in Section 12 3 Timer1 Oscillator above gives users the option to include RTC function ality to their applications This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time When operating in Sleep mode and using a battery or supercapacitor as a power source it can completely eliminate the need for a separate RTC device and battery backup The application code routine RTCisr shown in Example 12 1 demonstrates a simple method to increment a counter at one second intervals using an Interrupt Service Routine Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one additional counters for minutes and hours are incremented as the previous counter overflow Since the register pair is 16 bits wide counting up to overflow the register directly from a 32 768 kHz clock would take 2 seconds To force the overflow at the reguired one second intervals it is necessary to pre load it The simplest method is to set the MSb of TMR1H
622. the Start Enable bit SEN SSPCON2 lt 05 If the SDA and SCL pins are sampled high the Baud Rate Generator is reloaded with the contents of SSPADD lt 6 0 gt and starts its count If SCL and SDA are both sampled high when the Baud Rate Generator times out TBRG the SDA pin is driven low The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit SSPSTAT lt 3 gt to be set Following this the Baud Rate Generator is reloaded with the contents of SSPADD lt 6 0 gt and resumes its count When the Baud Rate Generator times out TBRG the SEN bit SSPCON2 lt 0 gt will be automatically cleared by hardware the Baud Rate Generator is suspended leaving the SDA line held low and the Start condition is complete 19 4 8 FIGURE 19 19 FIRST START BIT TIMING Note If at the beginning of the Start condition the SDA and SCL pins are already sam pled low or if during the Start condition the SCL line is sampled low before the SDA line is driven low a bus collision occurs the Bus Collision Interrupt Flag BCLIF is set the Start condition is aborted and the IC module is reset into its Idle state 19 4 8 1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress the WCOL is set and the contents of the buffer are unchanged the write doesn t occur Note Because queueing of events is not allowed writing to the lower five bits of SSPCON2 is disabled
623. the document could be made without affecting the overall usefulness 6 Is there any incorrect or misleading information what and where 7 How would you improve this document DS39632B page 422 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 PIC18F2455 2550 4455 4550 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PART NO x XX XXX JA ne cin Examples Device Temperature Package Pattern a PIC18LF4550 P 301 Industrial temp PDIP Range package Extended VDD limits QTP pattern 301 b PIC18LF2455 I SO Industrial temp SOIC package Extended VDD limits Device PIC18F2455 2550 U PIC18F4455 4550 I c PIC18F4455 l P Industrial temp PDIP PIC18F2455 2550T PIC18F4455 4550T02 package normal VDD limits VDD range 4 2V to 5 5V PIC18LF2455 25500 PIC18LF4455 4550 PIC18LF2455 2550T PIC18LF4455 4550T02 VDD range 2 0V to 5 5V Temperature Range 40 C to 85 C Industrial 40 C to 125 C Extended Package an a eae Thin Quad Flatpack Note 1 F Standard Voltage Range SP Skinny Plastic DIP LF Wide Voltage Range P PDIP 2 T intapeandreel TQFP ML QFN packages only Pattern QTP SQTP Code or Special Requirements blank otherwise 2004 Microchip Technology Inc Preliminary DS39632B page 423 MICROCHIP WORLD
624. the instruction mnemonic for use in symbolic addressing If a label is used the instruction syntax then becomes label instruction argument s DS39632B page 344 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 CALLW Subroutine Call Using WREG Syntax CALLW Operands None Operation PC 2 gt TOS W gt PCL PCLATH PCH PCLATU PCU Status Affected None Encoding 0000 0000 0001 0100 Description First the return address PC 2 is pushed onto the return stack Next the contents of W are written to PCL the existing value is discarded Then the contents of PCLATH and PCLATU are latched into PCH and PCU respectively The second cycle is executed as a NOP instruction while the new next instruction is fetched Unlike CALL there is no option to update W Status or BSR Words 1 Cycles 2 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Push PC to No WREG stack operation No No No No operation operation operation operation Example HERE CALLW Before Instruction MOVSF Move Indexed to f Syntax MOVSF 24 fa Operands 0 lt zs lt 127 0 lt fg lt 4095 Operation FSR2 zs fa Status Affected None Encoding 1st word source 2nd word destin 1110 1011 0zzz 1111 TES EEEE ZZZZs ffffa PC address HERE PCLATH 10h PCLATU 00h W 06h After Instruction
625. therwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial PIC18F2455 2550 4455 4550 Standard Operating Conditions unless otherwise stated Industrial Operating temperature 40 C lt TA lt 85 C for industrial m Device Typ Max Units Conditions Power Down Current lpD PIC18LFX455 X550 0 1 0 95 LA 40 C i A 5 DD 2 0V 0 1 10 uA 25 C Sloan mode 0 2 5 HA 85 C PIC18LFX455 X550 0 1 1 4 uA 40 C V s DD 3 0V 0 1 2 uA 25 C iSieep mode 0 3 8 uA 85 C All devices 0 1 1 9 HA 40 C 7 7 7 DD 5 0V 0 1 20 uA 25 C Sleep mode 0 4 15 uA 85 C Legend Shading of rows is to assist in readability of the table Note 1 The power down current in Sleep mode does not depend on the oscillator type Power down current is measured with the part in Sleep mode with all I O pins in high impedance state and tied to VDD or Vss and all features that add delta current disabled such as WDT Timer1 Oscillator BOR etc 2 The supply current is mainly a function of operating voltage frequency and mode Other factors such as I O pin loading and switching rate oscillator type and circuit internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements in active operation mode are OSC1 external square wave from rail to rail all I O pins tri stated pulled to VDD or VSS MCLR V
626. this enables or disables the weak pull ups on PORTD TRISE controls the direction of the RE pins even when they are being used as analog inputs The user must make sure to keep the pins configured as inputs when using them as analog inputs Note On a Power on Reset RE2 REO are configured as analog inputs The Data Latch register LATE is also memory mapped Read modify write operations on the LATE register read and write the latched output value for PORTE REGISTER 10 1 PORTE REGISTER The fourth pin of PORTE MCLR VPP RE3 is an input only pin Its operation is controlled by the MCLRE configuration bit When selected as a port pin MCLRE 0 it functions as a digital input only pin as such it does not have TRIS or LAT bits associated with its operation Otherwise it functions as the device s Mas ter Clear input In either configuration RE3 also functions as the programming voltage input during programming Note Ona Power on Reset RE3 is enabled as a digital input only if Master Clear functionality is disabled EXAMPLE 10 5 INITIALIZING PORTE CLRF PORTE Initialize PORTE by clearing output data latches CLRF LATE Alternate method to clear output data latches OVLW OAh Configure A D OVWF ADCON1 for digital inputs OVLW 03h Value used to initialize data s direction OVLW 07h Turn off OVWF CMCON comparators OVWF TRISC Set RE lt 0 gt as inputs RE lt 1 g
627. timing diagram shows three words appearing on the RX input The RCREG receive buffer is read after the third word causing the OERR overrun bit to be set TABLE 20 6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on page INTCON GIE GIEH PEIE GIEL TMROIE INTOIE RBIE TMROIF INTOIF RBIF 51 PIR1 SPPIFU ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMRI1IF 54 PIE1 SPPIEU ADIE RCIE TXIE SSPIE CCPIIE TMR2IE TMRIIE 54 IPR1 SPPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend unimplemented locations read as 0 Shaded cells are not used for asynchronous reception Reserved in 28 pin devices always maintain these bits clear Note 1 2004 Microchip Technology Inc Preliminary DS39632B page 245 PIC18F2455 2550 4455 4550 20 2 4 AUTO WAKE UP ON SYNC BREAK CHARACTER During Sleep mode all clocks to the EUSART are suspended Therefore the Baud Rate Generator is inactive and proper byte reception cannot be performed The auto wake up feature allows the controller to wake up due to activity on the RX DT line while the EUSART is ope
628. tion If skip and followed by 2 word instruction Q1 Q2 Q3 Q4 No No No No operation operation operation operation No No No No operation operation operation operation Example HERE CPFSEQ REG 0 NEQUAL EQUAL Before Instruction PC Address HERE W REG After Instruction If REG PC Address EQUAL If REG PC Address NEQUAL DS39632B page 318 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 CPFSGT Syntax Operands Operation Status Affected Encoding Description Words Cycles Q Cycle Activity Compare f with W Skip if f gt W CPFSGT f a 0 lt f lt 255 ae 0 1 f W skip if f gt W unsigned comparison None 0110 010a ffff ffff Compares the contents of data memory location f to the contents of the W by performing an unsigned subtraction If the contents of f are greater than the contents of WREG then the fetched instruction is discarded and a NOP is executed instead making this a two cycle instruction If a is o the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is o and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed
629. tion 15 4 4 Setup for PWM Operation or Section 16 4 9 Setup for PWM Opera tion The latter is more generic but will work for either single or multi output PWM TABLE 16 1 PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES CCP1CON ECCP Mode RC2 Configuration RD5 RD6 RD7 All PIC18F4455 4550 devices Compatible CCP 00xx 11xx CCP1 RD5 SPP5 RD6 SPP6 RD7 SPP7 Dual PWM 10xx llxx P1A P1B RD6 SPP6 RD7 SPP7 Quad PWM x1xx 11xx P1A P1B P1C P1D Legend x Don t care Shaded cells indicate pin assignments not used by ECCP in a given mode DS39632B page 150 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 16 4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applica tions The module is a backward compatible version of the standard CCP module and offers up to four outputs designated PIA through P1D Users are also able to select the polarity of the signal either active high or active low The module s output mode and polarity are configured by setting the P1M1 P1MO and CCP1M3 CCP1M0 bits of the CCP1CON register Figure 16 1 shows a simplified block diagram of PWM operation All control registers are double buffered and are loaded at the beginning of a new PWM cycle the period boundary when Timer2 resets in order to pre vent glitches on any of the outputs The exception is the
630. tion about the layer Section 17 10 1 Layered Framework they describe Often these strings show up in the host to help the user identify the device String descriptors are generally optional to save memory and are encoded in a unicode format 17 10 7 BUS SPEED Each USB device must indicate its bus presence and speed to the host This is accomplished through a 1 5 KQ resistor which is connected to the bus at the time of the attachment event Depending on the speed of the device the resistor either pulls up the D or D line to 3 3V For a low speed device the pull up resistor is connected to the D line For a full speed device the pull up resistor is connected to the D line 17 10 8 CLASS SPECIFICATIONS AND DRIVERS USB specifications include class specifications which operating system vendors optionally support Examples of classes include Audio Mass Storage Communications and Human Interface HID In most cases a driver is required at the host side to talk to the USB device In custom applications a driver may need to be developed Fortunately drivers are available for most common host systems for the most common classes of devices Thus these drivers can be reused 2004 Microchip Technology Inc Preliminary DS39632B page 185 PIC18F2455 2550 4455 4550 NOTES DS39632B page 186 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 18 0 STREAMING PARALLEL PORT No
631. tion should be used when modifying a single IRCF bit If VDD is less than 3V it is possible to select a higher clock speed than is supported by the low VDD Improper device operation may result if the Vpp Fosc specifications are violated 2 Executing a SLEEP instruction does not necessarily place the device into Sleep mode It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes depending on the setting of the IDLEN bit 3 1 4 MULTIPLE SLEEP COMMANDS The power managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed If another SLEEP instruction is executed the device will enter the power managed mode specified by IDLEN at that time If IDLEN has changed the device will enter the new power managed mode specified by the new setting 3 2 Run Modes In the Run modes clocks to both the core and peripherals are active The difference between these modes is the clock source 3 2 1 PRI RUN MODE The PRI RUN mode is the normal full power execution mode of the microcontroller This is also the default mode upon a device Reset unless Two Speed Start up is enabled see Section 25 3 Two Speed Start up for details In this mode the OSTS bit is set The IOFS bit may be set if the internal oscillator block is the primary clock source see Section 2 4 1 Oscillator Control Register
632. to an interrupt and the GIEL or GIEH bit is set the TOSU TOSH and TOSL are updated with the current value of the PC The STKPTR is modified to point to the next location in the hardware stack 2 One or more bits in the INTCONx or PIRx registers will be affected to cause wake up 3 When the wake up is due to an interrupt and the GIEL or GIEH bit is set the PC is loaded with the interrupt vector 0008h or 0018h 4 See Table 4 3 for Reset value for specific condition 5 PORTA lt 6 gt LATA lt 6 gt and TRISA lt 6 gt are enabled depending on the oscillator mode selected When not enabled as PORTA pins they are disabled and read o 2004 Microchip Technology Inc Preliminary DS39632B page 51 PIC18F2455 2550 4455 4550 TABLE 4 4 INITIALIZATION CONDITIONS FOR ALL REGISTERS CONTINUED MCLR Resets Register Applicable Devices Power on Reset WDT Reset Wake up via WDT Brown out Reset RESET lnstruction or Interrupt Stack Resets INDF2 2455 2550 4455 4550 N A N A N A POSTINC2 2455 2550 4455 4550 N A N A N A POSTDEC2 2455 2550 4455 4550 N A N A N A PREINC2 2455 2550 4455 4550 N A N A N A PLUSW2 2455 2550 4455 4550 N A N A N A FSR2H 2455 2550 4455 4550 0000 0000 uuuu FSR2L 2455 2550 4455 4550 XXXX XXXX uuuu uuuu uuuu uuuu STATUS 2455
633. to operate as a receiver the SDO pin can be configured as an input This disables transmissions from the SDO The SDI can always be left as an input SDI function since it cannot create a bus conflict SLAVE SYNCHRONIZATION WAVEFORM spo BJ PK bit 7 gt bit 6 SCK CKP 0 SS CKE 0 SCK j CKP 1 i CKE 0 S Wiet SSPBUF i l bit 7 x x bit 0 x CCR Simi 1 1 lt gt i ey bit7 SMP 0 SSPIF Interrupt Flag SSPSR to SSPBUF 5 Next Q4 Cycle 4 A after Q24 2 2004 Microchip Technology Inc Preliminary DS39632B page 199 PIC18F2455 2550 4455 4550 FIGURE 19 5 SPITM MODE WAVEFORM SLAVE MODE WITH CKE 0 Optional SCK CKP 0 CKE 0 SCK CKP 1 CKE 0 Write to SSPBUF J SDO e S X EXE CH gt bit 3 x bit 2 X bit 1 x bit 0 92000506 SMP 0 bit7 gt Input I I I Sample 1 1 1 1 i t 1 i t SMP 0 U i i a SSPIF Interrupt Flag Next Q4 Cycle i i i I I after 021 SSPSRto i i i i i i i i E SSPBUF U FIGURE 19 6 SPITM MODE WAVEFORM SLAVE MODE WITH CKE 1
634. to provide the extra current Thus a device capable of consuming more than one unit load must be able to maintain a low power configuration of one unit load or less if necessary The USB specification also defines a Suspend mode In this situation current must be limited to 500 uA averaged over 1 second A device must enter a Suspend state after 3 ms of inactivity i e no SOF tokens for 3 ms A device entering Suspend mode must drop current consumption within 10 ms after Suspend Likewise when signaling a wake up the device must signal a wake up within 10 ms of drawing current above the Suspend limit 17 10 5 ENUMERATION When the device is initially attached to the bus the host enters an enumeration process in an attempt to identify the device Essentially the host interrogates the device gathering information such as power consumption data rates and sizes protocol and other descriptive information descriptors contain this information A typical enumeration process would be as follows 1 USB Reset Reset the device Thus the device is not configured and does not have an address address 0 2 Get Device Descriptor The host reguests a small portion of the device descriptor 3 USB Reset Reset the device again 4 SetAddress The host assigns an address to the device 5 Get Device Descriptor The host retrieves the device descriptor gathering info such as manufacturer type of device maximum control packet s
635. to the instruction set Additionally the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled the application may read or write to the wrong data addresses When porting an application to the PIC18F2455 2550 4455 4550 it is very important to consider the type of code A large re entrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set DS39632B page 348 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 ADD W to Indexed Bit Set Indexed ADDWF Indexed Literal Offset mode BSk Indexed Literal Offset mode Syntax ADDWF k d Syntax BSF k b Operands 0 lt k lt 95 Operands 0 lt f lt 95 de 0 1 0 lt b lt 7 Operation W FSR2 k gt dest Operation 1 FSR2 k lt b gt Status Affected N OV C DC Z Status Affected None Encoding 0010 01d0 kkkk kkkk Encoding 1
636. truction g Stack Full Reset h Stack Underflow Reset This section discusses Resets generated by MCLR POR and BOR and covers the operation of the various start up timers Stack Reset events are covered in Section 5 1 2 4 Stack Full and Underflow Resets WDT Resets are covered in Section 25 2 Watchdog Timer WDT FIGURE 4 1 M gt A simplified block diagram of the On Chip Reset Circuit is shown in Figure 4 1 4 1 RCON Register Device Reset events are tracked through the RCON register Register 4 1 The lower five bits of the regis ter indicate that a specific Reset event has occurred In most cases these bits can only be cleared by the event and must be set by the application after the event The state of these flag bits taken together can be read to indicate the type of Reset that just occurred This is described in more detail in Section 4 6 Reset State of Registers The RCON register also has control bits for setting interrupt priority IPEN and software control of the BOR SBOREN Interrupt priority is discussed in Section 9 0 Interrupts BOR is covered in Section 4 4 Brown out Reset BOR SIMPLIFIED BLOCK DIAGRAM OF ON CHIP RESET CIRCUIT 2004 Microchip Technology Inc Preliminary DS39632B page 43 PIC18F2455 2550 4455 4550 REGISTER 4 1 bit 7 bit 6 bit 5 bit 4
637. tructions The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits This ensures that all program memory locations have a valid instruction DS39632B page 304 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 26 2 PIC18FXXXX INSTRUCTION SET CONTINUED Mnemonic A 16 Bit Instruction Word Status Description Cycles Notes Operands MSb LSb Affected BIT ORIENTED OPERATIONS BCF f b a Bit Clear f 1 1001 bbba ffff ffff None 1 2 BSF f b a Bit Set f 1 1000 bbba ffff ffff None 1 2 BTFSC f b a Bit Test f Skip if Clear 1 20r3 1011 bbba ffff ffff None 3 4 BTFSS f b a Bit Test f Skip if Set 1 20r3 1010 bbba ffff ffff None 3 4 BTG f d a Bit Toggle f 1 0111 bbba ffff ffff None 1 2 CONTROL OPERATIONS BC n Branch if Carry 1 2 1110 0010 mnnn nnnn None BN n Branch if Negative 1 2 1110 0110 mnnn nnnn None BNC n Branch if Not Carry 1 2 1110 0011 mnnn nnmnnn None BNN n Branch if Not Negative 1 2 1110 0111 mnnn nnnn None BNOV n Branch if Not Overflow 1 2 1110 0101 mnnn nnnn None BNZ n Branch if Not Zero 1 2 1110 0001 mnnn nnnn None BOV n Branch if Overflow 1 2 1110 0100 mnnn nnnn None BRA n Branch Unconditionally 2 1101 Onnn nnnn nnnn None BZ n Branch if Zero 1 2 1110 0000 mnnn nnnn None CALL n s Call subroutine 1st word 2 1110 110s kkkk kkkk
638. ts ensure that the GIE and PEIE bits in the INTCON register INTCON lt 7 6 gt are set FIGURE 20 11 SYNCHRONOUS TRANSMISSION arfacjasfasiarjae fasfastarfazlasiasiarjae los ac ar az asjas osb4ad ojoso4oibalosbd4loi osha lasiat 22fa3 a4jar fa2 as astar a2 as a4 I II RC7 RX DT La 2 i 2 a B SDO pin xX DO XX btT x bt2 lt gt lt bi 7 X bitd X i bti gt x 46 X bit7 Rene lt Word 1 f gt a Word 2 1 gt 1 SCKP 0 l 6 S RC6 TX CK pin i SCKP 1 i i s Write to TXREG ROJ Write Word 1 Write Word 2 i I i de i temupt Flag I 1 i 2 TRMT bit s i 6 I i TXENbit 2 S l i Note Sync Master mode SPBRG o continuous transmission of two 8 bit words DS39632B page 248 Preliminary 2004 Microchip Technology Inc FIGURE 20 12 PIC18F2455 2550 4455 4550 SYNCHRONOUS TRANSMISSION THROUGH TXEN RC7 RX DT SDO pin X bto X bil Xor 6 X bte X bit 7 RC6 TX CK pin N h Write to TXREG reg i TXIF bit TRMT bit 5 C TXENbit TABLE 20 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Reset Name Bit 7 Bit 6 Bit 5 Bi
639. ts registers are not used Instead of appear ing as unimplemented addresses however they appear as available RAM Only when an endpoint is enabled by setting the UEPn lt 1 gt bit does the memory at those addresses become functional as BD registers As with any address in the data memory space the BD registers have an indeterminate value on any device Reset An example of a BD for a 40 byte buffer starting at 500h is shown in Figure 17 6 A particular set of BD registers is only valid if the corresponding endpoint has been enabled using the UEPn register All BD registers are available in USB RAM The BD for each endpoint should be set up prior to enabling the endpoint 17 4 1 BD STATUS AND CONFIGURATION Buffer descriptors not only define the size of an end point buffer but also determine its configuration and control Most of the configuration is done with the BD Status register BDnSTAT Each BD has its own unique and correspondingly numbered BDnSTAT register FIGURE 17 6 EXAMPLE OF A BUFFER DESCRIPTOR Address Registers Contents 400h BDOSTAT xxh Buffer 401h BDOCNT 40h Size of Block Descriptor 402h BDOADRL 00h f Starting 403h BDOADRH 05h J Address 500h lt Buffer 4 USB Data lt 53Fh Note Memory regions not to scale Unlike other control registers the bit configuration for the BDNSTAT register is context sensitive There are two distinct
640. ts reside in BDnSTAT lt 1 0 gt This represents a valid byte range of 0 to 1023 17 4 3 BD ADDRESS VALIDATION The BD Address register pair contain the starting RAM address location for the corresponding endpoint buffer For an endpoint starting location to be valid it must fall in the range of the USB RAM 400h to 7FFh No mechanism is available in hardware to validate the BD address If the value of the BD address does not point to an address in the USB RAM or if it points to an address within another endpoint s buffer data is likely to be lost or overwritten Similarly overlapping a receive buffer OUT endpoint with a BD location in use can yield unexpected results When developing USB applications the user may want to consider the inclusion of software based address validation in their code BDnSTAT BUFFER DESCRIPTOR n STATUS REGISTER BDOSTAT THROUGH BD63STAT SIE MODE DATA RETURNED BY THE SIDE TO THE MICROCONTROLLER R W x U x R W x R W x R W x R W x R W x R W x UOWN PID3 PID2 PID1 PIDO BC9 BC8 bit 7 bit 0 bit 7 UOWN USB Own bit 1 The SIE owns the BD and its corresponding buffer bit 6 Reserved Not written by the SIE bit 5 2 PID3 PIDO Packet Identifier bits The received token PID value of the last transfer IN OUT or SETUP transactions only bit 1 0 BC9 BC8 Byte Count bits 9 and 8 These bits are updated by the SIE to reflect the actual number of bytes received on
641. ud Rate Generator BRG reload value is placed in the lower seven bits of the SSPADD register Figure 19 17 When a write occurs to SSPBUF the Baud Rate Generator will automatically begin counting The BRG counts down to 0 and stops until another reload has taken place The BRG count is decremented twice per instruction cycle Tcy on the Q2 and Q4 clocks In IC Master mode the BRG is reloaded automatically FIGURE 19 17 Once the given operation is complete i e transmis sion of the last data bit is followed by ACK the internal clock will automatically stop counting and the SCL pin will remain in its last state Table 19 3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3 SSPMO SSPADD lt 6 0 gt SSPM3 SSPMO Reload Reload y SCL Control Z CLKO lt BRG Down Counter lt Fosc 4 TABLE 19 3 I2CTM CLOCK RATE W BRG Fcy Fey 2 BRG Value p jj BR 10 MHz 20 MHz 19h 400 kHz 10 MHz 20 MHz 20h 312 5 kHz 10 MHz 20 MHz 3Fh 100 kHz 4 MHz 8 MHz OAh 400 kHz 4 MHz 8 MHz 0Dh 308 kHz 4 MHz 8 MHz 28h 100 kHz 1 MHz 2 MHz 03h 333 kHz 1 MHz 2 MHz OAh 100 kHz 1 MHz 2 MHz 00h 1 MHz Note 1 The 2CTM interface does not conform to the 400 kHz I2C specification which applies to rates greater than 100 kHz in
642. unctions as SPP CS output 0 RB4 functions as a digital I O port bit 4 CLK1EN SPP CLK1 Pin Enable bit 1 REO pin is controlled by the SPP module and functions as SPP CLK1 output o REO functions as a digital I O port bit 3 0 WS3 WS0 SPP Wait States bits 1111 30 additional wait states 1110 28 additional wait states 0001 2 additional wait states 0000 0 additional wait states Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 18 1 2 CLOCKING DATA The SPP has four control outputs Two separate clock outputs CK1SPP and CK2SPP Output enable OESPP e Chip select CSSPP Together they allow for several different configurations for controlling the flow of data to slave devices When all control outputs are used the three main options are e CLK1 clocks endpoint address information while CLK2 clocks data CLK1 clocks write operations while CLK2 clocks reads e CLK1 clocks odd address data while CLK2 clocks even address data Additional control options are derived by disabling the CK1SPP and CSSPP outputs These are enabled or disabled with the CLK1EN and CSEN bits respectively located in Register 18 2 18 1 3 WAIT STATES The SPP is designed with the capability of adding wait states to read and write operations This allows access to parallel devices that require extra time for
643. upt Enable bit 1 CRC5 host error interrupt enabled 0 CRC5 host error interrupt disabled PIDEE PID Check Failure Interrupt Enable bit 1 PID check failure interrupt enabled 0 PID check failure interrupt disabled Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown 2004 Microchip Technology Inc Preliminary DS39632B page 181 PIC18F2455 2550 4455 4550 17 6 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration The most common power modes encountered are Bus Power Only Self Power Only and Dual Power with Self Power Dominance The most common cases are presented here 17 6 1 BUS POWER ONLY In Bus Power Only mode all power for the application is drawn from the USB Figure 17 10 This is effectively the simplest power method for the device FIGURE 17 10 BUS POWER ONLY ve VDD VUSB _Vss 7v 17 6 2 SELF POWER ONLY In Self Power Only mode the USB application provides its own power with very little power being pulled from the USB Figure 17 11 shows an example Note that an attach indication is added to indicate when the USB has been connected FIGURE 17 11 SELF POWER ONLY Attach Sense VBUS AAW 1O pin 100 ka VSEL VDD 100 ka VusB Vss
644. upt Enable bit 1 Enables the CCP1 interrupt o Disables the CCP1 interrupt TMR2IE TMR2 to PR2 Match Interrupt Enable bit 1 Enables the TMR2 to PR2 match interrupt 0 Disables the TMR2 to PR2 match interrupt TMRIIE TMR1 Overflow Interrupt Enable bit 1 Enables the TMR1 overflow interrupt 0 Disables the TMR1 overflow interrupt bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared X Bit is unknown DS39632B page 104 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 REGISTER 9 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PIE2 PERIPHERAL INTERRUPT ENABLE REGISTER 2 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMRSIE CCP2IE bit 7 bit 0 OSCFIE Oscillator Fail Interrupt Enable bit 1 Enabled 0 Disabled CMIE Comparator Interrupt Enable bit 1 Enabled 0 Disabled USBIE USB Interrupt Enable bit 1 Enabled 0 Disabled EEIE Data EEPROM Flash Write Operation Interrupt Enable bit 1 Enabled 0 Disabled BCLIE Bus Collision Interrupt Enable bit 1 Enabled 0 Disabled HLVDIE High Low Voltage Detect Interrupt Enable bit 1 Enabled 0 Disabled TMRSIE TMR3 Overflow Interrupt Enable bit 1 Enabled 0 Disabled CCP2IE CCP2 Interrupt Enable bit 1 Enabled 0 Disa
645. uration bit is set 3 These pins are No Connect unless the ICPRT configuration bit is set For NC ICPORTS the pin is No Connect unless ICPRT is set and the DEBUG configuration bit is cleared DS39632B page 18 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 TABLE 1 3 PIC18F4455 4550 PINOUT O DESCRIPTIONS CONTINUED Pin Name Fieber n j Burer Description PDIP QFN TQFP Type Type j PORTC is a bidirectional I O port RCO T1O0SO T13CKI 15 34 32 RCO O ST Digital I O T10SO O Timer1 oscillator output T13CKI ST Timer1 Timer3 external clock input RC1 T1OSI CCP2 16 35 35 UOE RC1 O ST Digital I O T10SI CMOS Timer1 oscillator input ccp2 2 O ST Capture 2 input Compare 2 output PWM 2 output UOE O External USB transceiver OE output RC2 CCP1 P1A 17 36 36 RC2 I O ST Digital I O CCP1 O ST Capture 1 input Compare 1 output PWM 1 output PIA O TTL Enhanced CCP 1 PWM output channel A RC4 D VM 23 42 42 RC4 TTL Digital input D O USB differential minus line input output VM TTL External USB transceiver VM input RC5 D VP 24 43 43 RC5 l TTL Digital input D I O USB differential plus line input output VP TTL External USB transceiver VP input RC6 TX CK 25 44 44 RC6 I O ST Digital I O TX O EUSART asynchronous transmit CK I O ST EUSART synchronous clock see RX DT RC7 RX DT SDO 26 1 1 RC7 O ST Digi
646. ure operation will not work 15 1 2 CCP2 PIN ASSIGNMENT The pin assignment for CCP2 Capture input Compare and PWM output can change based on device config uration The CCP2MX configuration bit determines which pin CCP2 is multiplexed to By default it is assigned to RC1 CCP2MX 1 If the configuration bit TABLE 15 1 CCP MODE TIMER is cleared CCP2 is multiplexed with RB3 RESOURCE Changing the pin assignment of CCP2 does not CCP ECCP Mode Timer Resource automatically change any requirements for configuring s the port pin Users must always verify that the appropri Capture Timert or Timer3 ate TRIS register is configured correctly for CCP2 Compare Timer1 or Timer3 operation regardless of where it is located PWM Timer2 TABLE 15 2 INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base The time base can be different for each CCP Capture Compare CCP2 can be configured for the special event trigger to reset TMR1 or TMR3 depending upon which time base is used Automatic A D conversions on trigger event can also be done Operation of CCP1 could be affected if it is using the same timer as a time base Compare Capture CCP1 be configured for the special event trigger to reset TMR1 or TMR3 depending upon which time base is used Operation of CCP2 could be affected if it i
647. us of the SCL pin the SCL pin is driven low and the Repeated Start condition is complete BUS COLLISION DURING A REPEATED START CONDITION CASE 1 SDA SCL Sample SDA when SCL goes high If SDA o set BCLIF and release SDA and SCL Cleared in software o SSPIF 9 FIGURE 19 30 BUS COLLISION DURING REPEATED START CONDITION CASE 2 r TBRG s SDA SOL SCL goes low before SDA BCLIF set BCLIF Release SDA and SCL Interrupt cleared in software DS39632B page 230 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 19 4 17 3 Bus Collision During a Stop Condition Bus collision occurs during a Stop condition if a After the SDA pin has been deasserted and allowed to float high SDA is sampled low after the BRG has timed out b After the SCL pin is deasserted SCL is sampled low before SDA goes high The Stop condition begins with SDA asserted low When SDA is sampled low the SCL pin is allowed to float When the pin is sampled high clock arbitration the Baud Rate Generator is loaded with SSPADD lt 6 0 gt and counts down to o After the BRG times out SDA is sampled If SDA is sampled low a bus collision has occurred This is due to another master attempting to drive a data o Figure 19 31 If the SCL pin is sampled low before SDA i
648. use in symbolic addressing If a label is used the instruction format then becomes label instruction argument s 2004 Microchip Technology Inc Preliminary DS39632B page 307 PIC18F2455 2550 4455 4550 ADDWFC ADD W and Carry bit to f Syntax ADDWFC f d a Operands 0 lt f lt 255 de 0 1 ae 0 1 Operation W f C dest Status Affected N OV C DC Z Encoding 0010 00da ffff fff Description Add W the Carry flag and data memory location f If d is o the result is placed in W If d is 1 the result is placed in data memory location f If a is 0 the Access Bank is selected If a is 1 the BSR is used to select the GPR bank default If a is 0 and the extended instruction set is enabled this instruction operates in Indexed Literal Offset Addressing mode whenever f lt 95 5Fh See Section 26 2 3 Byte Oriented and Bit Oriented Instructions in Indexed Literal Offset Mode for details Words 1 Cycles 1 Q Cycle Activity Q1 Q2 Q3 Q4 Decode Read Process Write to register f Data destination Example ADDWFC REG 0 1 Before Instruction Carry bit 1 REG 02h W 4Dh After Instruction Carry bit 0 REG 02h W 50h ANDLW Syntax Operands Operation Status Affected Encoding AND Literal with W ANDLW k 0 lt k lt 255 W AND k gt W N Z D
649. with a BSF instruction Note that the TMRIL register is never preloaded or altered doing so may introduce cumulative error over many cycles For this method to be accurate Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled PIE1 lt 0 gt 1 as shown in the routine RTCinit The Timer1 oscillator must also be enabled and running at all times DS39632B page 132 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 EXAMPLE 12 1 IMPLEMENTING A REAL TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit OVLW 80h Preload TMR1 register pair OVWE TMR1H for 1 second overflow CLRF TMRIL OVLW b 00001111 Configure for external clock OVWF T10SC Asynchronous operation external oscillator CLRF secs Initialize timekeeping registers CLRF mins OVLW d 12 OVWF hours BSF PIE1 TMRIIE Enable Timerl interrupt RETURN RTCisr BSF TMRIH 7 Preload for 1 sec overflow BCF PIR1 TMRIIF Clear interrupt flag INCF secs F Increment seconds MOVLW a 59 60 seconds elapsed CPFSGT secs RETURN No done CLRF secs Clear seconds INCF mins F Increment minutes MOVLW a 59 60 minutes elapsed CPFSGT mins RETURN No done CLRF mins clear minutes INCF hours F Increment hours MOVLW d 23 24 hours elapsed CPFSGT hours RETURN No done MOVLW a 01 Re
650. with nanoWatt Technology Universal Serial Bus Features USB V2 0 Compliant Low Speed 1 5 Mb s and Full Speed 12 Mb s Supports Control Interrupt Isochronous and Bulk Transfers Supports up to 32 endpoints 16 bidirectional 1 Kbyte dual access RAM for USB On chip USB transceiver with on chip voltage regulator Interface for off chip USB transceiver Streaming Parallel Port SPP for USB streaming transfers 40 44 pin devices only Power Managed Modes Run CPU on peripherals on Idle CPU off peripherals on e Sleep CPU off peripherals off Idle mode currents down to 5 8 uA typical Sleep mode currents down to 0 1 uA typical Timer1 oscillator 1 1 uA typical 32 kHz 2V e Watchdog Timer 2 1 LA typical e Two Speed Oscillator Start up Flexible Oscillator Structure e Four Crystal modes including High Precision PLL for USB Two External Clock modes up to 48 MHz Internal oscillator block 8 user selectable frequencies from 31 kHz to 8 MHz User tunable to compensate for frequency drift Secondary oscillator using Timer1 32 kHz Dual oscillator options allow microcontroller and USB module to run at different clock speeds Fail Safe Clock Monitor Allows for safe shutdown if any clock stops Peripheral Highlights e High current sink source 25 mA 25 mA Three external interrupts Four Timer modules Timer0 to Timer3 Up to 2 Capture Compare PWM CCP modules Capture is 16 bit max res
651. y DS39632B page 387 PIC18F2455 2550 4455 4550 FIGURE 28 17 MASTER SSP IC BUS START STOP BITS TIMING WAVEFORMS SCL Start Condition Stop Condition Note Refer to Figure 28 4 for load conditions TABLE 28 21 MASTER SSP I2C BUS START STOP BITS REQUIREMENTS ae Symbol Characteristic Min Max Units Conditions 90 TSU STA Start Condition 100 kHz mode 2 Tosc BRG 1 ns Only relevant for Setup Time 400 kHz mode 2 Tosc BRG 1 Repeated Start 1 MHz mode 2 Tosc BRG 1 onaition 91 THD STA Start Condition 100 kHz mode 2 Tosc BRG 1 ns After this period the Hold Time 400 kHz mode 2 Tosc BRG 1 first clock pulse is 1 MHz mode 2 Tosc BRG 1 generated 92 Tsu sTo Stop Condition 100 kHz mode 2 Tosc BRG 1 ns Setup Time 400 kHz mode 2 Tosc BRG 1 1 MHz mode 2 Tosc BRG 1 93 THD STO Stop Condition 100 kHz mode 2 Tosc BRG 1 ns Hold Time 400 kHz mode 2 Tosc BRG 1 1 MHz mode 2 Tosc BRG 1 Note 1 Maximum pin capacitance 10 pF for all IC pins FIGURE 28 18 MASTER SSP I2C BUS DATA TIMING lt 100 102 Note 103 lt 107 Refer to Figure 28 4 for load conditions DS39632B page 388 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 445
652. y Inc Preliminary DS39632B page 21 PIC18F2455 2550 4455 4550 NOTES A n c rc c rr rO rr am TF DS39632B page 22 Preliminary 2004 Microchip Technology Inc PIC18F2455 2550 4455 4550 2 0 OSCILLATOR CONFIGURATIONS 2 1 Overview Devices in the PIC18F2455 2550 4455 4550 family incorporate a different oscillator and microcontroller clock system than previous PIC18F devices The addi tion of the USB module with its unique requirements for a stable clock source make it necessary to provide a separate clock source that is compliant with both USB low speed and full speed specifications To accommodate these requirements PIC18F2455 2550 4455 4550 devices include a new clock branch to provide a 48 MHz clock for full speed USB operation Since it is driven from the primary clock source an additional system of prescalers and postscalers has been added to accommodate a wide range of oscillator frequencies An overview of the oscillator structure is shown in Figure 2 1 Other oscillator features used in PIC18 enhanced microcontrollers such as the internal oscillator block and clock switching remain the same They are discussed later in this chapter 2 1 1 OSCILLATOR CONTROL The operation of the oscillator in PIC18F2455 2550 4455 4550 devices is controlled through two configura tion registers and two control registers Configuration registers CONFIGIL and CONFIG1H select the oscillator mode and USB prescaler po

MICROCHIP PIC18F2455/2550/4455/4550 Data Sheet1

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