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ANALOG DEVICES AD1885 Manual

1. Note 2Ch is an alias for 7Ah The VRA bit in register 2Ah must be set for the alias to work if a zero is written to VRA both sample rates are reset to 48 kHz SR 15 0 Writing to this register allows programming of the sampling frequency from 7040 Hz 1B80h to 48 kHz BB80h in 1 Hz increments Programming a value outside of the range 7040 Hz 1b80h to 48000 Hz BB80h causes the codec to saturate For all rates if the value written to the register is supported that value will be echoed back when read otherwise the closest rate supported is returned PCM ADC Rate Register Index 32h Reg Num Name 015 014 Di3 Di2 D11 D10 D8 D7 D6 DS D4 D3 D2 D0 Default 32h 78h PCM ADC Rate SR15 SR14 SRI3 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SRS SR4 SR3 SR2 SR1 SRO BB80h Note 32h is an alias for 78h The VRA bit in register 2Ah must be set for the alias to work if a zero is written to VRA both sample rates are reset to 48 kHz SR 15 0 Writing to this register allows programming of the sampling frequency from 7040 Hz 1B80h to 48 kHz BB80h in 1 Hz increments Programming a value outside of the range 7040 Hz 1b80h to 48000 Hz BB80h causes the codec to saturate For all rates if the value written to the register is supported that value will be echoed back when read otherwise t
2. TO CODEC MIC1 OR MIC2 INPUT lt FROM CODEC VREFOUT Figure 15 Microphone with Additional External Preamp 20 dB Gain LINE OUTPUT CONNECTIONS The AD1885 Codec provides stereo LINE OUT signals at a standard 1 V rms level These signals must be ac coupled before they can be connected to an external load After the ac coupling a minimal resistive load is recommend to keep the capacitors properly biased and reduce click and pop when plugging stereo equipment into the output jack The capacitor values should be selected to provide a desired frequency response taking into account the nominal impedance of the external load To meet the PC99 specifica tion for PCs testing must be performed with a 10 load therefore a 1 uF value is recommended to achieve less than 3 dB roll off at 20 Hz EMC AC COUPLING COMPONENTS E icti dad STEREO LINE OUTJACK e J1 12 6002 1pF FROM CODEC LINE OUT H FROM CODEC LINE OUT L c2 NOTE CT OE OM ER IF AN OUTPUT AMP IS USED THE AC COUPLING CAP VALUES WILL DEPENDEND ONTHE AMP DESIGN gt A x Figure 16 Recommended LINE OUT Connections REV 0 25 AD1885 PC BEEP INPUT CONNECTIONS The recommended PC BEEP input circuit is shown below Under most cases the PC signal should be attenuated filtered and then ac coupled into the Codec c
3. 0 AD1885 ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit Power Supplies Digital AVpp 0 3 3 6 V Analog DVpp 0 3 6 0 V Input Current Except Supply Pins 10 mA Analog Input Voltage Signal Pins 0 3 AVpp 0 3 V Digital Input Voltage Signal Pins 0 3 DVpp 0 3 V Ambient Temperature Operating 0 70 Storage Temperature 65 150 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section ofthis specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability CAUTION ORDERING GUIDE Temperature Package Package Model Range Description Option AD1885JST 0 C to 70 C 48 Lead LOFP ST 48 ST Thin Quad Flatpack ENVIRONMENTAL CONDITIONS Ambient Temperature Rating Tams PD x Oca Case Temperature in C Pp Power Dissipation in W Oca Thermal Resistance Case to Ambient Oja Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Package Oja Oca LQFP 76 2 C W 17 C W 59 2 C W ESD electrostatic discharge sensitive device Electrostatic charges accumulate on the human body and test equipment and ca
4. 12 dB 34 5 dB The default value is 0 dB mute enabled AM Aux Mute When this bit is set to 1 the channel is muted PCM Out Volume Index 18h A Name D15 014 D13 012 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Default PCM Out 18h Volume OM X x LOV4 LOV3 LOV2 LOV1 LOVO X X X ROV4 ROV3 ROV2 ROV1 8808h ROV 4 0 Right PCM Out Volume Allows setting the PCM right channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LOV 4 0 Left PCM Out Volume Allows setting the PCM left channel attenuator in 22 steps The LSB represents 1 5 dB and the range is 12 dB 34 5 dB The default value is 0 dB mute enabled OM PCM Out Volume Mute When this bit is set to 1 the channel is muted Volume Table xM x4 x0 Function 0 00000 12 dB Gain 0 01000 0 dB Gain 0 11111 34 5 dB Gain 1 XXXXX dB Gain REV 0 15 AD1885 Record Select Control Register Index 1Ah Reg Num Name 015 D14 D13 2 Di1 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 Default 1Ah Record Select X X X X x LS2 181 180 X x x x RS2 RS1 RSO 0000h RS 2 0 Right Record Select LS 2 0 Left Record Select Used to select the record source independently for right and left See table for leg
5. DRSR X ARSR 0000h ARSR ADC right sample generator select 0 SRO Selected 32h 1 SRI Selected 2Ch DRSR DAC right sample generator select 0 SRO Selected 32h 1 SRI Selected 2Ch SRX8D7 Multiply SRI rate by 8 7 SRX10D7 Multiply SR1 rate by 10 7 SRX10D7 and SRX8D7 are mutually exclusive MODEN Modem filter enable left channel only Change only when DACs and ADCs are powered down ALSR ADC left sample generator select 0 SRO Selected 32h 1 SRI Selected 2Ch DLSR DAC left sample generator select 0 SRO Selected 32h 1 SRI Selected 2Ch DMS Digital Mono Select 0 Mixer 1 Left DAC and Right DAC DAM Digital Audio Mode DAC Outputs bypass analog mixer and sent directly to the codec output LPMIX Low Power Mixer DACZ Zero fill vs repeat if DAC is starved for data 20 REV 0 AD1885 Sample Rate 0 Index 78h Reg Num Name 015 014 Di3 D12 D10 D9 D8 D7 D6 DS D4 D3 D2 D1 Default 32h 78h Sample Rate 0 SR015 SR014 SRO13 SR012 SRO11 SROIO SRO9 SROS SR07 SR06 5 05 SR04 SRO3 SRO2 SRO1 SROO BBS0h Note 32h is an alias for 78h The VRA bit in register 2Ah must be set for the alias to work if a zero is written to VRA both sample rates are reset to 48 kHz SRO 15 0 Writing to this register allows the user to program the sampling frequency from 7 kHz 1B58h to 48 kHz BB80h in 1 Hertz increments Programming
6. 1 Enabled Gain 20 dB MCM MIC Mute When this bit is set to 1 the channel is muted Line In Volume Index 10h Name D15 014 D13 D12 011 010 D8 D7 D6 D5 D4 D3 D2 D1 DO Default 10h Line In Volume LM X x LLV4 LLV3 LLV2 LLV1 LLVO X X X RLV4 RLV3 RLV2 RLV1 RLVO 8808h RLV 4 0 Right Line In Volume Allows setting the Line In right channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LLV 4 0 Line In Volume Left Allows setting the Line In left channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LM Line In Mute When this bit is set to 1 the channel is muted CD Volume Index 12h Reg Num Name 015 D14 DI3 2 011 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 Default 12h CD Volume X X LCV4 LCV3 LCV2 LCV1 LCVO X x x RCV4 RCV3 RCV2 RCV1 RCVO 8808h RCV 4 0 Right CD Volume Allows setting the CD right channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LCV 4 0 Left CD Volume Allows setting the CD left channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB 34 5 dB The default value is 0 dB mute enabl
7. DACs Power Down Analog Mixer Power Down Digital Interface Power Down Internal Clocks Disabled ADC and DAC Power Down VREF Standby Mode Low Power Mixer Mode CD Mixer Alive Only Mode Mixer Bypass Mode Digital Audio Headphone REV 0 Indexed Control Registers AD1885 Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Reset X SE4 SE3 SE2 SE SEO ID9 1 8 ID7 ID6 ID5 IDA ID3 ID2 ID1 IDO 0410h 02h Master Volume MM X LMV5 LMV4 LMV3 LMV2 LMVI LMVO X X RMV5 RMV4 RMV3 RMV2 RMVI RMVO 8000h 04h Headphones Volume HPM X LHV5 LHV4 LHV3 LHV2 LHVI LHVO X X RHV5 RHV4 RHV3 RHV2 RHVI RHVO 8000h 06h Master Volume Mono MMM X X X X X X X X X X MMV MMV MMV MMV MMV 8000h 4 3 2 1 0 08h Reserved X X X X X X X X X X X X X X X X X OAh PC Beep Volume PCM X X X X X X X X X X PCV2 PCV1 PCVO X 8000h Phone In Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHVO 8008h OEh Volume MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCVI MCVO 8008h 10h Line In Volume LM X X LLV4 LLV3 LLV2 LLVI LLVO X X X RLV4 RLV3 2 RLVI RLVO 8808h 12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV1 LCVO X X X RCV4 RCV3 RCV2 RCVI RCVO 8808h 14h Video Volume VM X X LVV4 LVV3 LVV2 LVVI LVVO X X X RVV4
8. MONO OUT MUTE MONO OUT MUTE NOTE PLUG IN JACK SENSE HIGH PLUG OUT JACK SENSE LOW The Jack Sense inputs are active high and their functionality is enabled by default on CODEC power up If necessary the Jack Sense inputs can be individually disabled by writing to the D8 and D9 bits on the CODEC Jack Sense Index Register 72h The Jack Sense pins contain active internal pull ups If the Jack Sense inputs are not being used they should be pulled down to digital ground using 10 kQ resistors This prevents LINE OUT and MONO_OUT from becoming muted while the Jack Senses are enabled CONNECTING THE JACK SENSES TO THE OUTPUT JACKS Headphone Jack The diagram on Figure 10 shows the preferred method to connect the JS1 Jack Sense line to the HP_OUT jack This scheme requires a stereo jack with a normally closed and isolated single switch The switch holds the Jack Sense line low grounded until an audio plug is inserted causing the switch to open and the Jack Sense line to go high due to the CODEC internal pull up The R2 and R3 resistors keep the electrolytic output caps properly polarized while the HP_OUT jack is not used NOTE LOCATE R1 CLOSETO CODEC R1 2 JACK SENSE LINE TO CODEC JS1 PIN 48 lt C2 OPTIONAL EMC 220 COMPONENTS ISOLATED FROM CODEC HP OUT PIN 41 5S C NC SWITCH 220pF FROM CODEC HP_OUT_L PIN 39 u HEADPHON
9. Output to Telephony Subsystem Speakerphone HP OUT L 39 Headphones Out Left Channel HP OUT R 41 Headphones Out Right Channel g REV 0 AD1885 Filter Reference These signals are connected to resistors capacitors or specific voltages Pin Name LQFP Description VREF 27 O Voltage Reference Filter VREFOUT 28 Voltage Reference Output 5 mA Drive Intended for Mic Bias AFILTI 29 Antialiasing Filter Capacitor ADC Right Channel AFLIT2 30 Antialiasing Filter Capacitor ADC Left Channel FILT R 31 AC Coupling Filter Capacitor ADC Right Channel FILT L 32 AC Coupling Filter Capacitor ADC Left Channel RX3D 33 3D PHAT Stereo Enhancement Resistor CX3D 34 I 3D PHAT Stereo Enhancement Capacitor Power and Ground Signals Pin Name LQFP Type Description 1 Digital 3 3 V DVss 4 I Digital GND DVss2 7 I Digital GND DVpp2 9 I Digital 3 3 V AVpp1 25 I Analog 5 0V AVssi 26 I Analog GND AVpp2 38 I Analog 5 0 V AVss2 40 I Analog GND 43 Analog Vpp 5 0 V AVss3 44 I Analog GND No Connects Pin Name LQFP Type Description NC 42 No Connect JSO EAPD 951 MIC1 VREFOUT MIC2 LINE S E AUX L E CD c T VIDEO 9 ee PHONE IN H4 LS RS 7 LS 5 LL T T isms 6 STEREO MIX R H RS
10. RVV3 RVV2 RVVI RVVO 8808h 16h Aux Volume AM X X LAV4 LAV3 LAV2 LAVI LAVO X X X RAV4 RAV3 2 RAVI RAVO 8808h 18h PCM Out Volume OM X X LOV4 LOV3 LOV2 LOV1 LOVO X X X ROV3 ROV2 ROVI ROVO 8808h lAh Record Select X X X X X LS2 LS1 LSO X X X X X RS2 RS1 RSO 0000h 1Ch Record Gain IM X X X LIM3 LIM2 LIMI LIMO X X X X RIM3 RIM2 RIMI RIMO 8000h 1Eh Reserved X X X X X X X X X X X X X X X X X 20h General Purpose POP X 3D X X X MIX MS LPBK X X X X X X X 0000h 22h 3D Control X X X X X X X X X X X X DP3 DP2 DPO 0000h 26h Power Down Cntrl Stat X X PR5 PRA PR3 PR2 PRI PRO X X X X REF ANL DAC ADC 000Xh 28h Extended Audio ID IDI 1 0 X X X X X X X X X X X X X VRA 0001h 2Ah Extended Audio Stat Ctrl X X X X X X X X X X X X X X X 0000h 2Ch PCM DAC Rate SRI SR15 SRI4 SR13 SRI2 SR11 SRIO SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SRI SRO BB80h 7Ah 32h PCM ADC Rate SRO SR15 SRI4 SR13 SRI2 SR11 SRIO 589 SR8 SR7 SR6 SR5 SR4 SR3 862 SRI SRO BB80h 78h 34h Reserved X X X X X X X X X X X X X X X X X 72h Jack Sense Audio JS1 OUT JSO JS1 JSO 151 750 151 JSO JS1 80_ JS1 JSO AUD JJS1 JSO JS 0000h Interrupt Status FUNCT OUT PUDIS PUDIS OE OE DIS DIS CLR CLR MODE MODE INT INT 74h Serial Configuration SLOT REG REG REG X X DHWR X X X X X X X X 7000h 16 M2 MO 76h Miscellaneous Control DAC LPMI X DAM DMS DLSR X ALSR MOD SRXI
11. Resolution 0 ID8 18 Bit ADC Resolution 0 ID9 20 Bit ADC Resolution 0 SE 4 0 Stereo Enhancement The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement Master Volume Registers Index 02h D15 4 013 12 D11 D10 D9 DS D7 D6 DS D4 D3 D2 D1 DO Default 02h a MM X LMV4 LMV3 LMV2 LMV1 LMV0 X X RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h 5 0 Right Master Volume Control The least significant bit represents 1 5 dB This register controls the output from 0 dB to a maximum attenuation of 94 5 dB LMV 5 0 Left Master Volume Control The least significant bit represents 1 5 dB This register controls the output from 0 dB to a maximum attenuation of 94 5 dB MM Master Volume Mute When this bit is set to 1 the channel is muted MM xMV5 xMV0 Function 0 00 0000 0 dB Attenuation 0 01 1111 46 5 dB Attenuation 0 11 1111 94 5 dB Attenuation 1 XX XXXX o dB Attenuation 12 REV 0 AD1885 Headphones Volume Registers Index 04h Reg Num Name 015 D14 D13 D12 D11 D10 D8 D7 DS D4 D3 D2 Default 04h Headphones Volume HPM X LHVS LHVA LHV3 LHV2 LHVI1 LHVO X X RHVS RHVA RHV3 RHV2 RHV1 RHVO 8000h RHV 5 0 Right Headphone Volume Control The least significant bit repr
12. Select Input 0 Active Low ID1 46 I Chip Select Input 1 Active Low JACK SENSES EAPD GENERAL PURPOSE DIGITAL OUTPUTS These signals can sense the presence of audio jacks in the line out or headphones outputs and automatically mute the other audio outputs JSO can also be programmed for EAPD control Alternatively both pins can be programmed as general purpose digital outputs Pin Name LQFP Type Description JSO 47 IO JACK Sense Input 0 Mutes Mono Output JS1 48 IO JACK Sense Input 1 Mutes Line Out and Mono Outputs or Line Out Only Analog These signals connect the AD1885 component to analog sources and sinks including microphones and speakers Pin Name LQFP Description PC BEEP 12 I PC Beep PC speaker beep passthrough PHONE IN 13 I Phone Input From telephony subsystem speakerphone or handset AUX 14 I Auxiliary Input Left Channel 15 I Auxiliary Input Right Channel VIDEO L 16 I Video Audio Left Channel VIDEO R 17 I Video Audio Right Channel CDL 18 I CD Audio Left Channel CD GND REF 19 I CD Audio Analog Ground Reference for Differential CD Input CD R 20 I CD Audio Right Channel MICI 21 I Microphone 1 Desktop microphone input MIC2 22 I Microphone 2 Second microphone input LINEIN L 23 I Line In Left Channel LINE IN R 24 I Line In Right Channel LINE OUT L 35 Line Out Left Channel LINE OUT R 36 Line Out Right Channel MONO OUT 37 Monaural
13. recommended that the analog power plane for the Codec also be split mirroring the analog ground plane In this case the analog power supply ferrite bead should bridge the isolation trench close to the Codec location 26 REV 0 AD1885 REV 0 OUTLINE DIMENSIONS Dimensions shown in inches and mm 48 Lead Thin Plastic Quad Flatpack LQFP ST 48 0 063 1 60 MAX 0 354 9 00 BSC 0 057 1 45 la 0 276 7 0 BSC 0 030 0 75 Y 0 053 1 35 tap 0 018 E SEATING PLANE Me TOP VIEW PINS DOWN mo ex OG Sos 0 006 39 zat 1 0 002 0 05 0 MIN 0 7 T an 0 007 0 18 0 019685 0 5 0 011 0 27 0 004 0 09 BSC 0 006 0 17 27 C00753 2 5 7 00 rev 0 PRINTED IN U S A
14. 2 PU 0 1 nF PC BEEP FROM ICH 5 k CODEC PC INPUT C1 R2 0 1pF 1 Figure 17 Recommended Connections GROUNDING AND LAYOUT To reduce noise and emissions Analog Devices recommends a split ground plane as shown in Figure 18 The purpose of splitting the ground plane is to create a low noise analog area that is somewhat isolated from the digital ground current noise generated by the system s logic All the analog circuitry should be placed on the analog ground plane area For reference purposes and to return power supply currents the analog and digital ground planes must be connected at some point ideally a small bridge under or near the Codec should be provided A 0 resistor or a ferrite bead should also be considered since these allow some flexibility in optimizing the layout to meet EMC requirements DIGITAL GROUND PLANE CONNECT SPLIT GROUND PLANES AT OR NEAR CODEC ISOLATION AD1885 TRENCH ANALOG GROUND PLANE Figure 18 Recommended Split Ground Plane ANALOG POWER SUPPLY To minimize audio noise the Codec analog power supply AVDD should be well decoupled and regulated In PC systems it is rec ommended that the analog supply be derived from the 12 V PC power supply using a localized linear voltage regulator Preferably the analog power supply should be connected to the Codec s analog section using a ferrite bead If a power plane layer is being used in the system design it is
15. 5 RESET MONO OUT GA S 0x12 0x16 SYNC LCV RCV AD1885 BIT CLK SDATA OUT M M 0x12 0x16 CM AM HP OUT 5 Q 3D 0x20 2 SWITCH LINE OUT RO Nc o HP OUT RO PC BEEP Q SDATA IN LINE OUT L o B M MUTE S SELECTOR OSCILLATORS G GAIN A ATTENUATION Figure 8 Block Diagram Register Map REV 0 9 AD1885 PRODUCT OVERVIEW The AD1885 Codec meets the Audio Codec 97 2 1 Extensions adding support for multiple Codecs and variable sample rates In addition the AD1885 SoundPort Codec is designed to meet all requirements of the Audio Codec 97 Component Specification Revision 1 03 1996 Intel Corporation found at www Intel com The AD1885 also includes other Codec enhanced features such as communicating to three Codecs on the same link integrated headphone driver and built in PHAT Stereo 3D enhancement The AD1885 is an analog front end for high performance PC audio modem or DSP applications The AC 97 architecture defines a 2 chip audio solution comprising a digital audio controller plus a high quality analog component that includes Digital to Analog Converters DACs Analog to Digital Con verters ADCs mixer and I O The main architectural features of the AD1885 are the high quality analog mixer section two channels of A ADC conver sion two channels of A DAC c
16. ANALOG DEVICES AC 97 2 1 FEATURES Variable Sample Rate Audio Multiple Codec Configuration Options External Audio Power Down Control AC 97 FEATURES AC 97 2 1 Compliant Greater than 90 dB Dynamic Range Stereo Headphone Amplifier Multibit A Converter Architecture for Improved S N Ratio Greater than 90 dB 16 Bit Stereo Full Duplex Codec Four Analog Line Level Stereo Inputs for LINE IN CD VIDEO and AUX Two Analog Line Level Mono Inputs for Speakerphone and PC BEEP Mono MIC Input w Built In 20 dB Preamp Switchable from Two External Sources High Quality CD Input with Ground Sense Stereo Line Level Outputs Mono Output for Speakerphone or Internal Speaker Power Management Support 48 Terminal LOFP Package AC 97 SoundMAX Codec AD1885 Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software Enabled Vperour Output for Microphones and External Power Amp Split Power Supplies 3 3 V Digital 5 V Analog Mobile Low Power Mixer Mode Extended 6 Bit Master Volume Control Extended 6 Bit Headphone Volume Control Digital Audio Mixer Mode PHAT Stereo 3D Stereo Enhancement FUNCTIONAL BLOCK DIAGRAM AD1885 JSO EAPD JS1 VREFOUT OdB 20dB Q Q 16 BIT XA A D CONVERTER HP OUT L 16 BIT XA A D CONVERTER SYNC BIT CLK p SDATA_OUT SAMPLE RATE GENERAT
17. CD On LPMIX PR1 PRO 8 26 mA Mixer PR2 21 23 mA ADC Mixer PR2 PRO 19 18 mA DAC Mixer PR2 PRI 19 15 mA ADC DAC Mixer PR2 PRO 8 10 mA Analog CD Only AC Link On LPMIX PR5 PRI PRO 7 22 mA Analog CD Only AC Link Off PRI PRO PRA PR5 0 12 mA Standby PR5 PR4 PR3 PR2 PRO 0 0 1 mA Headphone Standby PR6 21 38 mA NOTES Guaranteed not tested Output jitter is directly dependent on crystal input jitter Specifications subject to change without notice 4 0 TIMING PARAMETERS GUARANTEED OVER OPERATING TEMPERATURE RANGE AD1885 Parameter Symbol Min Typ Max Unit RESET Active Low Pulsewidth tnsT LOW 1 0 us RESET Inactive to BIT_CLK Startup Delay tRST2CLK 162 8 ns SYNC Active High Pulsewidth tsYNC HIGH 1 3 us SYNC Low Pulsewidth tsyNC LOW 19 5 us SYNC Inactive to BIT_CLK Startup Delay tsyNc2cLK 162 8 ns BIT_CLK Frequency 12 288 MHz BIT_CLK Period tcLK_PERIOD 81 4 ns BIT_CLK Output Jitter 750 ps BIT_CLK High Pulsewidth tcLK HIGH 32 56 42 48 84 ns BIT_CLK Low Pulsewidth tcLK LOW 32 56 38 48 84 ns SYNC Frequency 48 0 kHz SYNC Period PERIOD 20 8 Us Setup to Falling Edge of BIT_CLK tsETUP 5 2 5 ns Hold from Falling Edge of BIT CLK tHoLp 5 ns Rise Time 2 4 10 ns BIT CLK Fall Time tFALLCLK 2 4 10 ns SYNC Rise Time tRISESYNC 2 4 10 ns SYNC Fall Time tFALLSYNC 2 4 10 ns SDATA IN Rise Time tRISEDIN 2 4 10 ns SDATA IN Fall Time tFA
18. E OUT Figure 10 Jack Sense Connection to HP OUT Jack Using Isolated Switch Alternatively when an audio output jack containing an isolated switch is not available the circuit shown on Figure 11 can be used While the audio plug is out this circuit keeps the Jack Sense line state low by the pull down affect of R2 with no audio present or by tracking the lower peaks of the HP OUT audio signal Once an audio plug is inserted and the jack switch opens the Jack Sense line switches to a high state due to the CODEC internal pull up which quickly charges C1 to DVDD The R2 and R3 resistors also keep the electrolytic output caps properly polarized while the OUT jack is not used REV 0 23 AD1885 NOTE LOCATE R1 AND C1 CLOSETO CODEC JACK SENSE TO CODEC 451 PIN 48 MMBD914 2 CERAMIC i OPTIONAL EMC ic ala a 7 COMPONENTS C2 oer e 1 2206 L1 6002 C4 470pF J 220 FROM CODEC HP OUT L PIN 39 35 41 L2 6002 HEADPHONE OUT Figure 11 Jack Sense Connection to HP OUT Jack Using Nonisolated Switch LINE OUT Jack Although not shown if a LINE OUT jack is used and the jack sense functionality is desired the LINE OUT jack should be wired in a similar configuration as shown above for the HP OUT jack preferably Figure 10 The LINE OUT jack should normally be connected to the JSO input in order to mute the MONO OUT signa
19. LLDIN 2 4 10 ns SDATA OUT Rise Time tRISEDOUT 2 4 10 ns SDATA OUT Fall Time tFALLDOUT 2 4 10 ns End of Slot 2 to BIT CLK SDATA IN Low 152 PDOWN 0 10 ms Setup to Trailing Edge of RESET Applies to SYNC SDATA OUT tsETUP2RST 15 ns Rising Edge of RESET to HI Z Delay torr 25 ns Propagation Delay 15 ns RESET Rise Time 50 ns Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid 15 ns NOTES Output jitter is directly dependent on crystal input jitter Specifications subject to change without notice REV 0 _5 AD1885 Low OU UU Figure 1 Cold Reset tsyNc_HIGH SYNC BIT_CLK Figure 2 Warm Reset tcik Low BIT CLK N teLk_HIGH tcik PERIOD tsync_Low SYNC tsync_HIGH tsync_PERIOD Figure 3 Clock Timing tsetup lt lt BIT_CLK SYNC SDATA_OUT Figure 4 Data Setup and Hold BIT CLK trisecLk gt jt traLLCLK swe ON trisesync gt jt trALLSYNC soaran triseDIN gt gt 4 lFALLDIN SDATA OUT n MET Mes c 4 gt 4 tFaLLDOUT Figure 5 Signal Rise and Fall Time SYNC SLOT 1 SLOT 2 BIT_CLK WRITE SDATA_OUT TO 0x26 152 PDOWN NOTE BIT_CLK NOT TO SCALE Figure 6 AC Link Low Power Mode Timing RESET SDATA_OUT tseTup2RsT SDATA_IN BIT_CLK HI Z torr Figure 7 ATE Test Mode REV
20. ORS AC LINK LINE_OUT_L 16 BIT D A M CONVERTER SDATA_IN 16 BIT G A XA D A M CONVERTER GAIN ATTENUATE UTE MASTER VOLUME HV HEADPHONE VOLUME G A M M OSCILLATOR RES XTL OUT XTL IN SoundPort is a registered trademark and PHAT is a trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 AD1885 SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 DAC Test Conditions Digital Supply DVpp 3 3 V Calibrated Analog Supply AVpp 5 0 V 3 dB Attenuation Relative to Full Scale Sample Rate Fs 48 kHz Input 0 dB Input Signal 1008 Hz 10 kQ Output Load LINE OUT Analog Output Passband 20 Hz to 20 kHz 32 Q Output Load HP OUT ADC Test Conditions Calibrated 0 dB Gain Input 3 0 dB Relative to Full Scale ANALOG INPUT Parameter Min Typ Max
21. SOPUDIS JS1PUDIS JSO_OUT Enables JSO pin as a general purpose output Enables JS1 pin as a general purpose output Setting the JSOPUDIS bit disables the JSO pin internal pull up Setting the JSIPUDIS bit disables the JS1 pin internal pull up When enabled as GPO the JSO pin reflects the state of the JSO_OUT bit JS1_OUT FUNCT When enabled as GPO the JS1 pin reflects the state of the JS1_OUT bit otherwise this bit can be set to change the functionality of JS1 so that only LINE_OUT is muted when JS1 is high Serial Configuration Index 74h Name 015 014 D13 D12 011 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Serial SLOT h REGM2 REGM1 REGMI X X DHWR X X X X X x x x x x 14 Configuration 16 S GMO Note this register is not reset when the reset register register 00h is written DHWR REGMO REGMI REGM2 SLOTI16 Disable Hardware Reset Master Codec register mask Slave 1 Codec register mask Slave 2 Codec register mask Enable 16 bit slots If your system uses only a single AD1885 you can ignore the register mask SLOTI16 makes all AC Link slots 16 bits in length formatted into 16 slots Miscellaneous Control Bits Index 76h Name 015 D14 D13 D12 D11 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Default 76h Misc Control Bits Lr zs ME X DAM DMS DLSR X ALSR m oa X X
22. SRX8 X X DRSR X ARSR 0404h Bits Z X EN 0D7 D7 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 50 4144h 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 TO REV7 REV6 REV5 REV4 REV3 REV2 REVI REVO 5360h NOTES All registers not shown and bits containing an X are assumed to be reserved Odd register addresses are aliased to the next lower even address Reserved registers should not be written Zeros should be written to reserved bits Indicates Aliased register for AD1819B backward compatibility REV 0 11 AD1885 Reset Index 00h Name 015 014 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Di DO Default 00h Reset x SE4 SE3 SE2 SE1 SEO ID9 ID8 ID7 ID6 IDS ID4 ID3 ID2 ID1 IDO 0410h Note Writing any value to this register performs a register reset which causes all registers to revert to their default values except 74h which forces the serial configuration Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement ID 9 0 Identify Capability The ID decodes the capabilities of AD1885 based on the following Bit 1 Function AD1885 IDO Dedicated MIC PCM In Channel 0 ID1 Modem Line Codec Support 0 ID2 Bass and Treble Control 0 ID3 Simulated Stereo Mono to Stereo 0 ID4 Headphone Out Support 1 ID5 Loudness Bass Boost Support 0 ID6 18 Bit DAC Resolution 0 ID7 20 Bit DAC
23. Unit Input Voltage RMS Values Assume Sine Wave Input LINE IN AUX CD VIDEO PHONE IN PC BEEP 1 V rms 2 83 Vp p MIC with 20 dB Gain M20 1 0 1 V rms 0 283 V p p MIC with 0 dB Gain M20 0 1 V rms 2 83 V p p Input Impedance 20 kQ Input Capacitance 5 7 5 pF MASTER VOLUME Parameter Min Typ Max Unit Step Size 0 dB to 94 5 dB LINE OUT L LINE OUT R 1 5 dB Output Attenuation Range Span 94 5 dB Step Size 0 dB to 46 5 dB MONO OUT 1 5 dB Output Attenuation Range Span 46 5 dB Step Size 6 dB to 88 5 dB HP OUT R HP 1 5 dB Output Attenuation Range Span 94 5 dB Mute Attenuation of 0 dB Fundamental 80 dB PROGRAMMABLE GAIN AMPLIFIER ADC Parameter Min Typ Max Unit Step Size 0 dB to 22 5 dB 1 5 dB PGA Gain Range Span 22 5 dB ANALOG MIXER INPUT GAIN AMPLIFIERS ATTENUATORS Parameter Min Typ Max Unit Signal to Noise Ratio SNR CD to LINE OUT 90 dB Other to LINE OUT 90 dB Step Size 12 dB to 34 5 dB All Steps Tested MIC LINE IN AUX CD VIDEO PHONE IN DAC 1 5 dB Input Gain Attenuation Range MIC LINE AUX CD VIDEO PHONE IN DAC 46 5 dB Step Size 0 dB to 45 dB All Steps Tested PC BEEP 3 0 dB Input Gain Attenuation Range PC BEEP 45 dB Guaranteed not tested 2 0 AD1885 DIGITAL DECIMATION AND INTERPOLATION FILTERS Parameter Min Typ Max Unit Passband 0 0 4 x Fs Hz Passband Ripple 0 09 dB Transition Band 0 4 x Fs 0 6 x Fs Hz Stopband 0 6 x Fs Hz Stopb
24. a value greater than 48 kHz or less than 7 kHz may cause unpredictable results Sample Rate 1 Index 7Ah Reg Num Name 015 014 D13 D12 11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Default 2Ch 7Ah Sample Rate 1 SR115 SR114 58113 SR112 SR111 SR110 SRI9 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h Note 2Ch is an alias for 7Ah The VRA bit in register 2Ah must be set for the alias to work if a zero is written to VRA both sample rates are reset to 48 kHz SRI 15 0 Writing to this register allows the user to program the sampling frequency from 7 kHz 1B58h to 48 kHz BB80h in 1 Hertz increments Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results Vendor ID Registers Index 7Ch Eh Name 015 D14 D13 12 D11 D10 D8 D7 D6 05 04 D3 D2 D1 DO Default 7Ch Vendor 101 F7 F6 FS F4 F3 F2 F1 FO S7 S6 S5 S4 S3 S2 S1 50 4144h S 7 0 This register is ASCII encoded to S F 7 0 This register is ASCII encoded to D udi Name 015 014 013 D12 D11 D10 D9 DS D7 D6 5 4 D3 D2 D1 DO Default 7Eh Vendor ID2 T7 T6 TS T4 T3 T2 T1 TO REV7 REV6 REVS REV4 REV3 REV2 REV1 REVO 5360h T 7 0 This register is ASCII encoded to S REV 7 0 Revision Regi
25. and Rejection 74 dB Group Delay 12 Group Delay Variation Over Passband 0 0 us ANALOG TO DIGITAL CONVERTERS Parameter Min Typ Max Unit Resolution 16 Bits Total Harmonic Distortion THD 84 Dynamic Range 60 dB Input THD N Referenced to Full Scale A Weighted 84 87 dB Signal to Intermodulation Distortion CCIF Method 85 dB ADC Crosstalk Line Inputs Input L Ground R Read R Input R Ground L Read L 100 90 dB LINE IN to Other 90 85 dB Gain Error Full Scale Span Relative to Nominal Input Voltage t10 Interchannel Gain Mismatch Difference of Gain Errors 0 5 dB ADC Offset Error 5 mV DIGITAL TO ANALOG CONVERTERS Parameter Min Typ Max Unit Resolution 16 Bits Total Harmonic Distortion THD LINE_OUT 85 dB Total Harmonic Distortion THD OUT With 10 Load 75 Dynamic Range LINE OUT 60 dB Input THD N Referenced to Full Scale A Weighted 85 90 dB Signal to Intermodulation Distortion CCIF Method 100 dB Gain Error Full Scale Span Relative to Nominal Input Voltage t10 Interchannel Gain Mismatch Difference of Gain Errors 0 7 dB DAC Crosstalk Input L Zero Measure OUT Input R Zero L Measure L_OUT 80 dB Total Audible Out of Band Energy Measured from 0 6 x Fs to 20 kHz 40 dB ANALOG OUTPUT Parameter Min Typ Max Unit Full Scale Output Voltage LINE OUT 1 V rms 2 83 V p p Output Impedance 800 Q External Load Impedan
26. ce 10 kQ Output Capacitance 15 pF External Load Capacitance 100 pF Full Scale Output Voltage HP OUT 0 dB Gain 1 V rms Output Capacitance 100 pF External Load Capacitance 32 Q VREF 2 05 2 25 2 45 V VREFOUT 2 25 V Current Drive 5 mA Mute Click Muted Output Minus Unmuted Midscale DAC Output t5 mV Guaranteed not tested REV 0 3 AD1885 SPECIFICATIONS STATIC DIGITAL SPECIFICATIONS Parameter Min Typ Max Unit High Level Input Voltage Vim Digital Inputs 0 65 x DVpp V Low Level Input Voltage Vr 0 35 x DVpp V High Level Output Voltage 2 mA 0 9 x DVpp V Low Level Output Voltage Voz Io 2 mA 0 1x DVpp V Input Leakage Current 10 10 uA Output Leakage Current 10 10 uA POWER SUPPLY Parameter Min Typ Max Unit Power Supply Range Analog AVpp 4 75 5 25 V Power Supply Range Digital DVpp 3 15 3 45 V Power Dissipation 5 V 3 3 V 355 mW Analog Supply Current 5 V AVpp 50 mA Digital Supply Current 3 3 V DVpp 21 mA Power Supply Rejection 100 mV p p Signal 1 kHz 40 dB At Both Analog and Digital Supply Pins Both ADCs and DACs CLOCK SPECIFICATIONS Parameter Min Typ Max Unit Input Clock Frequency 24 576 MHz Recommended Clock Duty Cycle 40 50 60 POWER DOWN MODE DVpp 3 3 V AVpp 5 V Parameter Set Bits Typ Typ Unit ADC PRO 20 44 mA DAC PRI 20 41 mA ADC and DAC PRI PRO 8 35 mA ADC DAC Mixer Analog
27. dB steps and summed with any of the analog input signals The summed analog signal enters the Master Volume stage where each channel of the mixer out put may be attenuated from 0 dB to 94 5 dB in 1 5 dB steps or muted Analog Outputs The AD1885 offers a line output controlled by the Master Volume control and an integrated headphone driver with independent control Host Based Echo Cancellation Support The AD1885 supports time correlated I O data format by pre senting mic data on the left channel of the ADC and the mono summation of left and right output on the right channel The ADC is splittable left and right ADC data can be sampled at different rates Telephony Modem Support The AD1885 contains a V 34 capable analog front end for sup porting host based and data pump modems The modem DAC typical dynamic range is 90 dB over a 4 2 kHz analog output passband where 12 8 kHz The left channel of the ADC and DAC may be used to convert modem data at the same sample rate in the range between 7040 Hz and 48 kHz All pro grammed sample rates have a resolution of 1 Hz The AD1885 supports irrational V 34 sample rates with 8 7 and 10 7 select able multiplier coefficients Power Management Modes The AD1885 is designed to meet notebook and ACPI power consumption requirements through flexible power management control of all internal resources The following subsections may be independently controlled ADCs and Input Mux Power Down
28. ed CVM CD Volume Mute When this bit is set to 1 the channel is muted 14 REV 0 AD1885 Video Volume Index 14h Reg Num Name 015 D14 D13 2 11 D10 D9 D8 D7 D6 DS D4 D3 D2 D1 D0 Default 14h Video Volume VM X x LVV4 LVV3 LVV2 LVV1 LVVO X X x RVV4 RVV3 RVV2 RVV1 RVVO 8808h RVV 4 0 Right Video Volume Allows setting the Video right channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LVV 4 0 Left Video Volume Allows setting the Video left channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled VM Video Mute When this bit is set to 1 the channel is muted AUX Volume Index 16h Reg Num Name 015 D14 D13 2 Di1 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 Default 16h Aux Volume AM X x LAV4 LAV3 LAV2 LAV1 LAVO X X x RAV4 RAV3 RAV2 RAV1 RAVO 8808h RAV 4 0 Right Aux Volume Allows setting the Aux right channel attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LAV 4 0 Left Aux Volume Allows setting the Aux left channel attenuator in 32 steps The LSB represents 1 5 dB and the range is
29. end The default value is 0000h which corresponds to MIC in RS2 RS0 Right Record Source MIC CD VIDEO R AUX R LINE IN R Stereo Mix R Mono Mix PHONE IN LS2 LS0 Left Record Source MIC CDL VIDEO L LINE IN Stereo Mix L Mono Mix PHONE IN Record Gain Index 1Ch Reg Num Name 015 D14 D13 2 Di1 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 Default 1Ch Record Gain IM X X X LIM3 LIM2 LIMI LIMO X X x x RIM3 RIM2 RIMO 8000h 3 0 Right Input Mixer Gain Control Each LSB represents 1 5 dB 0000 0 dB and the range is 0 dB to 22 5 dB LIM 3 0 Left Input Mixer Gain Control Each LSB represents 1 5 dB 0000 0 dB and the range is 0 dB to 22 5 dB IM Input Mute 0 Unmuted 1 Muted or dB gain IM xIM3 xIMO Function 0 1111 22 5 dB Gain 0 0000 0 dB Gain 1 XXXXX co dB Gain 16 REV 0 AD1885 General Purpose Register Index 20h Reg Num Name 015 014 D13 D12 D11 D10 DS D7 6 05 D4 D3 D2 D1 DO Default 20h General Purpose X 3D x x x MIX MS LPBK X x x x x x x 0000h Note This register should be read before writing to generate a mask for only the bit s that need to be changed LPBK Loopback C
30. esents 1 5 dB This register controls the out put from 6 dB to a maximum attenuation of 88 5 dB LHV 5 0 Left Headphone Volume Control The least significant bit represents 1 5 dB This register controls the output from 6 dB to a maximum attenuation of 88 5 dB HPM Headphone Volume Mute When this bit is set to 1 the channel is muted HPM xHV5 xHV0 Function 0 00 0000 6 dB Gain 0 01 1111 40 5 dB Attenuation 0 11 1111 88 5 dB Attenuation 1 XX XXXX dB Attenuation Master Volume Mono Index 06h Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 5 D4 D3 D2 Default 06h Volume x x x x x x x x x MMV4 MMV3 MMV2 MMV1 S000h 4 0 Mono Master Volume Control The least significant bit represents 1 5 dB This register controls the output from 0 dB to a maximum attenuation of 46 5 dB MMM Mono Master Volume Mute When this bit is set to 1 the channel is muted PC Beep Register Index 0Ah Reg Num Name 015 14 D12 D11 D10 D9 08 D7 D6 D5 D4 D3 D2 Di DO Default 0Ah Volume PCM X X X X X X X X X X PCV3 PCV2 PCV1 PCVO X 8000h PCV 3 0 PC Beep Volume Control The least significant bit represents 3 dB attenuation This register controls the output from 0 dB to a maximum attenuation
31. gnals may be sent to the ADCs for processing by the DC 97 controller or the host and may be used during simultaneous capture and playback at different sample rates Analog to Digital Signal Path The selector sends left and right channel information to the programmable gain amplifier PGA The PGA following the selector allows independent gain control for each channel enter ing the ADC from 0 dB to 22 5 dB in 1 5 dB steps Each channel of the ADC is independent and can process left and right channel data at different sample rates 10 Sample Rates and 025 The AD1885 default mode sets the Codec to operate at 48 kHz sample rates The converter pairs may process left and right channel data at different sample rates The AD1885 sample rate generator allows the Codec to instantaneously change and process sample rates from 7040 Hz to 48 kHz with a resolution of 1 Hz The in band integrated noise and distortion artifacts introduced by rate conversions are below 90 dB The AD1885 uses a 4 bit XA structure and D S to enhance noise immunity on mother boards and in PC enclosures and to suppress idle tones below the device s quantization noise floor The D S process pushes noise and distortion artifacts caused by errors in the multibit DAC to frequencies beyond the auditory response of the human ear and then filters them Digital to Analog Signal Path The analog output of the DAC may be gained or attenuated from 12 dB to 34 5 dB in 1 5
32. he closest rate supported is returned Jack Sense Audio Interrupt Status Register Index 72h cdd Name 015 014 013 012 011 D10 D9 D8 07 D6 05 D4 D3 D2 D1 DO Default aon Jack Sense Audio JS1_OUT JS0_ JS1 Jso 151 1180 751 JSo jsi 50 JSi 150 AUD so 178 ooooh Interrupt Status FUNCT OUT PUDIS PUDIS OE OE DIS DIS CLR MODE MODE INT INT Note all register bits are read write except for AUDINT JSINT 150 and 151 which are read only JSINT Indicates that a jack sense interrupt has been generated by JSO or JS1 Remains set until all JS enabled interrupts are cleared JS0 Indicates Pin JSO state JS1 Indicates Pin JS1 state AUDINT Indicates the Codec has generated audio interrupt Remains set until software clears all pending interrupts JSOMODE Sets JSO pin input mode 1 Interrupt 0 Jack Sense JSIMODE Sets JS1 pin input mode 1 Interrupt 0 Jack Sense JSOCLR This bit is set by the Codec when there is a pending JSO interrupt Software must clear this bit to clear the JSO interrupt status bit JSICLR This bit is set by the Codec when there is a pending JS1 interrupt Software must clear this bit to clear the JS1 interrupt status bit JSODIS If the JSODIS bit is set the Codec ignores Jack Sense pin JSO 151015 If the JSIDIS bit is set the Codec ignores Jack Sense pin 151 REV 0 19 AD1885 180 151 OE J
33. l We recommend that in this case the output coupling caps C2 C3 be set to 2 2 uF All other values should be kept the same APPLICATION CIRCUITS CD ROM CONNECTIONS Typical CD ROM drives generate 2 V rms output and require a voltage divider for compatibility with the Codec input 1 V rms range The recommended circuit is basically a group of divide by two voltage dividers as shown on Figure 12 The CD GND REF pin is used to cancel differential ground noise from the CD ROM For optimum noise cancellation this sec tion of the divider should have approximately half the impedance of the right and left channel section dividers VOLTAGE DIVIDER AC COUPLING r hes i aio ded DE 1 R1 C1 47kO 0 334 F k To CODEC CD L INPUT C2 0 33 pF l CODEC GND REF INPUT HEADER FOR CD ROM AUDIO LGGR 0 33uF HY TO CODEC CD INPUT Figure 12 Typical CD ROM Audio Connections LINE IN AUX AND VIDEO INPUT CONNECTIONS Most of these audio sources also generate 2 V rms audio level and require 6 dB input voltage divider to be compatible with the Codec inputs Figure 13 shows the recommended application circuit For applications requiring EMC compliance the EMC com ponents should be configured and selected to provide adequate RF immunity and emissions control EMC COMPONENTS VOLTAGE DIVIDER AC COUPLING
34. n discharge without detection Although the AD1885 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality as high as 4000 V readily a ESD SENSITIVE DEVICE PIN CONFIGURATION DVpp 1 e MONO OUT 36 LINE OUT R PIN 1 XTL IN 2 IDENTIFIER 35 LINE OUT L xrL our 3 34 CX3D DVss 4 5 RX3D SDATA OUT 5 s2 FILT_L CLK 5 AD1885 31 FILT R DV TOP VIEW 552 Not to Scale 30 AFILT2 SDATA IN s 29 AFILT1 DVpp e 28 VaEFour SYNC VREF RESET 11 26 AVssi PC BEEP 12 25 AVpp 3 22 i23 z oarng anu auntn wxa2mc 10 lann a 55 2 2 9 al a o NC NO CONNECT REV 0 7 AD1885 SPECIFICATIONS PIN FUNCTION DESCRIPTIONS Digital Pin Name LQFP Description XTL IN 2 I Crystal or Clock Input 24 576 MHz XTL OUT 3 Crystal Output SDATA OUT 5 I AC Link Serial Data Output AD1885 Input Stream BIT CLK 6 O I AC Link Bit Clock 12 288 MHz Serial Data Clock Daisy Chain Input Clock SDATA IN 8 AC Link Serial Data Input AD1885 Output Stream SYNC 10 I AC Link Frame Sync RESET 11 I AC Link Reset AD1885 Master H W Reset CHIP SELECTS Pin Name LQFP Type Description IDO 45 I Chip
35. of 45 dB The PC Beep is routed to Left and Right Line outputs even when AD 18835 is a RESET state This is so that Power On Self Test POST codes can be heard by the user in case of a hardware problem with the PC PCM PC Beep Mute When this bit is set to 1 the channel is muted PCM Function 0 0000 0 dB Attenuation 0 1111 45 dB Attenuation 1 XXXX dB Attenuation REV 0 13 AD1885 Phone Volume Index 0Ch Name 015 014 013 D12 D11 010 D9 D8 07 D6 DS D4 D3 D2 D1 Default Phone Volume PHM X X X X X X x X X X PHV4 PHV3 PHV2 PHV1 PHVO 8008h PHV 4 0 Phone Volume Allows setting the Phone Volume Attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled PHM Phone Mute When this bit is set to 1 the channel is muted MIC Volume Index 0Eh 015 014 Di3 012 D10 D9 08 D7 D6 D5 D4 D3 D2 Di Do Default MIC MCM X X X X X X X X M20 X MCV4 MCV3 MCV2 MCV1 MCVO 8008h Volume MCV 4 0 MIC Volume Gain Allows setting the MIC Volume attenuator in 32 steps The LSB represents 1 5 dB and the range is 12 dB 34 5 dB The default value is 0 dB mute enabled M20 Microphone 20 dB Gain Block 0 Disabled Gain 0 dB
36. ommended One Codec PWR Decoupling and AC 97 Connections 22 28 270 0 1pF REV 0 AD1885 JACK SENSE OPERATION The AD1885 features two Jack Sense pins JSO and JS1 that can be used to automatically mute the LINE OUT and or MONO OUT audio outputs When the Jack Sense pins are connected to the output jacks the AD1885 can sense whether an audio plug has been inserted into a particular output jack and automatically mute the other unnecessary audio outputs The 151 pin should normally be connected to the HP OUT jack to automatically mute the and LINE OUT audio signals while the JSO pin should normally be connected to the LINE OUT jack to automatically mute the OUT signal It is also possible to set the D15 bit in the Jack Sense Index Register 72h which causes JS1 to only mute the LINE OUT signal This option may be desirable in certain audio configurations Table I summarizes the Jack Sense operation Table I Jack Sense Operation Table HP OUT Plug LINE OUT Plug Audio Output States Audio Output States 051 780 REG 72h 015 0 REG 72h D15 1 OUT OUT HP OUT ON HP OUT ON LINE OUT ON LINE OUT ON MONO OUT ON MONO OUT ON OUT IN HP OUT ON HP OUT ON LINE OUT ON LINE OUT ON MONO OUT MUTE MONO OUT MUTE IN OUT HP OUT ON HP OUT ON LINE OUT MUTE LINE OUT MUTE MONO OUT MUTE MONO OUT ON IN IN HP OUT ON HP OUT ON LINE OUT MUTE LINE OUT MUTE
37. ontrol ADC DAC Digital Loopback Mode MS MIC Select 0 MICI 1 MIC2 MIX Mono Output Select 0 Mix 1 3 3D Stereo Enhancement 0 PHAT Stereo is off 1 PHAT Stereo is on POP PCM Output Path and Mute The POP bit controls the optional PCM out 3D bypass path the pre and post 3D PCM out paths are mutually exclusive 0 pre 3D 1 post 3D 3D Control Register Index 22h ee Name D15 Di4 Di3 D12 D11 D10 D9 D8 D7 D6 05 D4 D3 D2 D1 Default 22h 30 Control x x x x x x x x x x x x DP3 DP2 DP1 0000 DP 2 0 Depth Control Sets 3D Depth PHAT Stereo enhancement according to table below DP3 DP0 Depth 0000 0 0001 6 67 14 93 33 15 100 REV 0 17 AD1885 Subsection Ready Register Index 26h Reg Num Name D15 014 D13 12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Default 26h Power Down Cntrl Stat PR6 PRS PR4 PR3 PR2 PR1 PRO X x x x REF ANL DAC ADC 000xh Note The ready bits are read only writing to REF ANL DAC ADC will have no effect These bits indicate the status for the AD1885 subsections If the bit is a one then that subsection is ready Ready is defined as the subsection able to perform in its nominal state ADC ADC section ready to transmit data DAC DAC section ready to accep
38. onversion and Data Direct Scrambling D S rate generators FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1885 and is intended as a general introduction to the capabilities of the device Detailed reference information may be found in the descriptions of the Indexed Control Registers Analog Inputs The Codec contains a stereo pair of ZA ADCs Inputs to the ADC may be selected from the following analog signals tele phony PHONE IN mono microphone MICI or MIC2 stereo line LINE IN auxiliary line input AUX stereo CD ROM CD stereo audio from a video source VIDEO and post mixed stereo or mono line output LINE OUT Analog Mixing PHONE IN MICI or MIC2 LINE IN AUX CD and VIDEO can be mixed in the analog domain with the stereo output from the DACs Each channel of the stereo analog inputs may be inde pendently gained or attenuated from 12 dB to 34 5 dB in 1 5 dB steps The summing path for the mono inputs PHONE IN MICI and MIC2 to LINE OUT and OUT duplicates mono chan nel data on both the left and right LINE OUT and OUT Additionally the PC attention signal PC may be mixed with the line output and headphone A switch allows the output of the DACs to bypass the PHAT Stereo 3D enhancement Digital Audio Mode The AD1885 is designed with a Digital Audio Mode DAM that allows mixing of all analog inputs independent of the DAC output signal path Mixed analog input si
39. r Power Down X 0 0 0 0 1 1 0 ADC DAC Mixer Power Down X 0 0 0 0 1 1 1 Standby X 1 1 1 1 1 1 1 Extended Audio ID Register Index 28h uS Name 015 4 013 D12 D11 010 D9 8 D7 D6 DS D4 D3 D2 D1 DO Default 28h Extended Audio ID 101 ID0 X x x x x x x x X X X X X 0001h Note The Extended Audio ID is a read only register VRA Variable Rate Audio VRA 1 indicates support for Variable Rate Audio ID 1 0 ID1 IDO is a 2 bit field that indicates the codec configuration Primary is 00 Secondary is 01 18 REV 0 AD1885 Extended Audio Status and Control Register Index 2Ah Reg Num Name 015 D14 D13 D12 D11 010 D9 D8 D7 06 DS D4 D2 Default 2Ah Extended Audio St Ctrl X x x x x x x x x x x x x x x VRA 0000h Note The Extended Audio Status and Control Register is a read write register that provides status and control of the extended audio features VRA Variable Rate Audio VRA 1 enables support for Variable Rate Audio mode sample rate control registers and SLOTREQ signaling PCM DAC Rate Register Index 2Ch Reg Num Name 015 014 D13 D12 11 010 D9 D8 D7 06 D5 04 D3 D2 Default 2Ch 7Ah PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SRS SR4 SR3 SR2 SR1 SRO BBS0h
40. ster field contains the revision number These bits are read only and should be verified before accessing vendor defined features REV 0 21 AD1885 APPLICATIONS CIRCUITS The AD1885 has been designed to require a minimum amount of external circuitry The recommended applications circuits are shown in Figures 9 18 Reference designs for the AD1885 are available and may be obtained by contacting your local Analog Devices sales representative or authorized distributor Example shell programs for establishing a communications path between the AD1885 and an ADSP 21xx or ADSP 21xxx are also available NOTE IF NOT USED GROUND JACK SENSE PINS DVDD 10pF 0 1pF up Cees 24 576MHz 1 22pF SDATA_OUT L gt SDATA_IN lt _ tH SYNC gt 12 pc RESET gt 1 BIT CLK lt 479 47pF 0 1pF PC_BEEP AVDD EM Ive T 22 2 V CIC LI 48 JS1 47 JSO EAPD AD1885 uj z T ac 4 a e om zz 2420016 x Xu A 5559900 zz 45500 ai lt ioo r oo o o e eo lt paa FB 6002 ic LINE OUT R LINE OUT L CX3D RX3D FILT_L 34 47nF ER AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1 25 37 1 270pFNPO 0 1uF 10pF AVDD NOTE ALL UNUSED ANALOG INPUTS LINE_IN_L R AUX_L R VIDEO_L R MIC1 MIC2 PC_BEEP PHONE_IN AND CD_L R GND MUST BE LEFT UNCONNECTED Figure 9 Rec
41. t data ANL Analog gainuators attenuators and mixers ready REF Voltage References VREF and VREFOUT up to nominal level PR 5 0 AD1885 Power Down Modes The first three bits are to be used individually rather than in combination with each other The last bit PR3 can be used in combination with PR2 or by itself The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down Nothing else can be powered up until the reference is up PRO Power Down ADC PRI Power Down DAC PR2 Power Down Analog Mixer PR3 Power Down Vggg and VgggouT PR4 Power Down AC Link PR5 Power Down Internal Clock PR6 Power Down Headphone EAPD External AMP Power Down Control Signal PR5 has no effect unless all ADCs DACs and the AC Link are powered down The reference and the mixer can either be up or down but all power up sequences must be allowed to run to completion before PR5 and PR4 are both set In multiple codec systems the master codec s PR5 and PR4 bits control the slave codec PR5 is also effective in the slave codec if the master s PR5 bit is clear but the PR4 bit has no effect except to enable or disable PR5 Power Down State EAPD PR6 5 PR4 PR3 PR2 PRI PRO ADC Power Down X 0 0 0 0 0 0 1 DAC Power Down X 0 0 0 0 0 1 0 ADC and DAC Power Down X 0 0 0 0 0 1 1 Mixer Power Down X 0 0 0 0 1 0 0 ADC Mixer Power Down X 0 0 0 0 1 0 1 DAC Mixe
42. ur rere e d Fel Se Toda eoe 1 LINE AUX VIDEO INPUT ORI c3 12 6002 l 0 33pF J1 gt CODEC RIGHT CHANNEL INPUT gt TO CODEC LEFT CHANNEL INPUT L1 600Z Figure 13 LINE_IN AUX and Video Input Connections 24 REV 0 AD1885 MICROPHONE CONNECTIONS The AD1885 contains an internal microphone preamp with 20 dB gain in most cases a direct microphone connection as shown in Figure 14 is adequate If the microphone level is too low an external preamp can be added as shown in Figure 15 In either case the microphone bias can be derived from the Codec s internal reference Vgerour using a 2 2 resistor For the preamp circuit the Vggrour signal can also provide the midpoint bias for the amplifier To meet the PC99 1 0A requirements the MIC signal should be placed on the microphone jack tip and the bias on the ring This configuration supports electret microphones with three conductor plugs as well as dynamic microphones with two conductor plugs ring and sleeve shorted together Additional filtering may be required to limit the microphone response to the audio band of interest EMC COMPONENTS L1 6002 AC COUPLING 12 6002 0 22pF MIC INPUT MIC BIAS lt FROM CODEC VREFOUT Figure 14 Recommended Microphone Input Connections PREAMP 000g re COMPONENTS R3 100 JA L1 6002 AC COUPLING c4 0 22

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