ANALOG DEVICES ADE5166/ADE5169/ADE5566 handbook
Contents
1. 10 100 07411 132 07411 135 CURRENT CHANNEL of Full Scale CURRENT CHANNEL of Full Scale Figure 17 Voltage and Current RMS Error as a Percentage of Reading Figure 20 Active Energy Error as a Percentage of Reading Gain 8 Gain 1 over Power Supply with Internal Reference over Power Factor with Internal Reference Integrator Off 1 0 1 0 GAIN 1 GAIN 8 08 INTEGRATOR OFF 0 8 INTEGRATOR OFF E INTERNAL REFERENCE INTERNAL REFERENCE 0 6 MID CLASS B 0 6 5 04 5 04 o2 1 o2 do PF 0 5 xs 0 o 0 5 5 92 2 0 4 0 4 mm 0 6 55 0 6 0 8 0 8 1 0 3 1 0 8 40 45 50 55 60 65 70 7 01 1 10 100 2 LINE FREQUENCY Hz 5 CURRENT CHANNEL of Full Scale Figure 18 Active Energy Error as Percentage of Reading Gain 1 Figure 21 Reactive Energy Error as a Percentage of Reading Gain 8 over Frequency with Internal Reference Integrator Off over Power Factor with Internal Reference Integrator Off 0 5 1 5 GAIN 8 INTEGRATOR OFF INTERNAL REFERENCE GAIN 7 1 INTEGRATOR OFF INTERNAL REFERENCE 0 4 MID CLASS C VAR 3 13V F ERROR of Read2. Table 51 Temperature and Supply Delta SFR DIFFPROG Address 0xF3 Bit Mnemonic Default Description 7 6 Reserved 00 Reserved 5 3 TEMP_DIFF 00 Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052 TEMP_DIFF Result 000 No interrupt 001 1 LSB 0 8 C 010 2 LSB 1 6 C 011 3 LSB 2 4 C 100 4 LSB 3 2 C 101 5 LSB 4 C 110 6 LSB 4 8 C 111 Every temperature measurement 2 0 VDCIN_DIFF 00 Difference threshold between the last external voltage measurement interrupting 8052 and the new external voltage measurement that should interrupt 8052 VDCIN_DIFF Result 000 No interrupt 001 1 LSB 120 mV 010 2 LSB 240 mV 011 3 LSB 360 mV 100 4 LSB 480 mV 101 5 LSB 600 mV 110 6 LSB 720 mV 111 Every Vocn measurement Table 52 Start ADC Measurement SFR ADCGO Address 0xD8 Bit Bit Address Mnemonic Default Description 7 OxDF PLLACK 0 Set this bit to clear the PLL fault bit PLL_FLT Bit 4 in the PERIPH SFR Address OxF4 A PLL fault is generated if a reset is caused because the PLL lost lock 16 31 OxDE to Reserved 0000 Reserved 2 OxDA VDCIN ADC GO 0 Set this bit to initiate an external voltage measurement This bit is cleared when the measurement request is received by the ADC 1 OxD9 TEMP ADC GO 0 Set this
3. E ES E EE m LT E WATCHDOG TIMEOUT WDIR TEMPADC INTERRUPT IN OUT LATCH WATCHDOG TEMP ADC EXTERNAL INTERRUPT 0 2 Q Q Q INTERRUPT POLLING SEQUENCE TIMER 0 1 PSM2 EXTERNAL NTI 927 222 INTERRUPT 1 1 1 1 SPI INTERRUPT na 12C INTERRUPT gt IN OUT LATCH RESET UART Q Q Q Q O 2 N UART2 INDIVIDUAL INTERRUPT LEGEND ENABLE i AUTOMATIC z GLOBAL lt CLEAR SIGNAL INTERRUPT ENABLE EA n Figure 89 Interrupt System Functional Block Diagram Rev C Page 95 of 156 ADE5166 ADE5169 ADE5566 ADE5569 INTERRUPT VECTORS When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter When the interrupt service routine is complete the program counter is popped off the stack by a RETI instruction This allows program execution to resume from where it was interrupted The interrupt vector addresses are shown in Table 87 Table 87 Interrupt Vector Addresses Source Vector Address IEO 0x0003 TFO 0 000 IE1 0x0013 TF1 0x001B RI 0 0023 2 2 0 002 ITEMP Temperature ADC 0x0033 ISPI I2CI 0x003
4. 7 6 PGA2 GAIN SELECT l SELECTION L PGA1 GAIN SELECT 000 x1 000 x1 INO E 001 x2 001 x2 010 x4 010 x4 011 x8 011 x8 100 16 100 16 Figure 42 PGA Current Channel CFSIGN_OPT RESERVED REGISTER CONTENTS SHOW POWER ON DEFAULTS Figure 41 Analog Gain Register 07411 019 Rev C Page 46 of 156 ADE5166 ADE5169 ADE5566 ADE5569 ANALOG TO DIGITAL CONVERSION Each ADE5166 ADE5169 ADE5566 ADE5569 has two X A analog to digital converters ADCs The outputs of these ADCs are mapped directly to waveform sampling SFRs Address OxE2 to Address OxE7 and are used for energy measurement internal digital signal processing In PSM1 battery mode and PSM2 sleep mode the ADCs are powered down to minimize power consumption For simplicity the block diagram in Figure 44 shows a first order ADC The converter is made up of the Z A modulator and the digital low pass filter LPF modulator converts the input signal into a continuous serial stream of 1s and Os at a rate determined by the sampling clock In ADE5166 ADE5169 ADE5566 ADE5569 sam pling clock is equal to 4 096 MHz 5 The 1 bit DAC in the feedback loop is driven by the serial data stream The DAC output is subtracted from the input signal If the loop gain is high enough the average value of the DAC output and therefore the bit stream can approach that of the input signal level Fo
5. 2 41 0 4 40 Po 5 MISO ZX 39 6 5 0 38 7 65 2 1 2 25 2 1 4 2 23 P1 5 FP22 8 P1 6 FP21 9 1 7 20 P0 1 FP19 P2 0 FP18 2 1 17 13 P2 2 FP16 14 15 LCDVP2 ADE5166 ADE5169 TOP VIEW Not to Scale 21 n FP13 07411 010 Figure 9 ADE5166 ADE5 169 Pin Configuration Table 13 Pin Function Descriptions Pin No Mnemonic Description 1 COM3 FP27 Common Output 3 LCD Segment Output 27 COM3 is used for the LCD backplane 2 COM2 FP28 Common Output 2 LCD Segment Output 28 COM2 is used for the LCD backplane 3 1 Common Output 1 COMI is used for the LCD backplane 4 COMO Common Output 0 COMO is used for the LCD backplane 5 P1 2 FP25 ZX General Purpose Digital I O Port 1 2 LCD Segment Output 25 ZX Output 6 P1 3 T2EX FP24 General Purpose Digital I O Port 1 3 Timer 2 Control Input LCD Segment Output 24 7 P1 4 T2 FP23 General Purpose Digital I O Port 1 4 Timer 2 Input LCD Segment Output 23 8 P1 5 FP22 General Purpose Digital I O Port 1 5 LCD Segment Output 22 9 1 6 21 General Purpose Digital I O Port 1 6 Segment Output 21 10 P1 7 FP20 General Purpose Digital I O Port 1 7 LCD Segment Output 20 11 PO 1 FP19 General Purpose Digital I O Port 0 1 LCD Segment Output 19 12 P2 0 FP18 General Purpose Digital I O Port 2 0 LCD Segment Output 18 13 P2 1 FP17 General Purpo
6. leg active Input Swap Threshold Inactive Input gt Active Input 6 25 of active Or lpg active Accuracy Fault Mode Operation lea Active les AGND 0 1 of reading Over a dynamic range of 500 to 1 lps Active lea AGND 0 1 of reading Over a dynamic range of 500 to 1 Fault Detection Delay 3 Seconds Swap Delay 3 Seconds 1 These specifications are not production tested but are guaranteed by design and or characterization data on production release See the Terminology section for definition 3 Available only in the ADE5166 ADE5169 Rev C Page 6 of 156 ADE5166 ADE5169 ADE5566 ADE5569 ANALOG PERIPHERALS Table 3 Parameter Min Typ Max Unit Test Conditions Comments INTERNAL ADCs BATTERY TEMPERATURE Vocin Power Supply Operating Range 24 3 7 V Measured on Vswour No Missing Codes 8 Bits Conversion Delay 38 us ADC Gain Vocin Measurement 15 3 mV LSB Measurement 14 6 mV LSB Temperature Measurement 0 83 C LSB ADC Offset Measurement at 3 V 200 LSB Measurement at 3 7 V 246 LSB Temperature Measurement at 25 123 LSB Analog Input Maximum Signal Levels 0 33 V Input Impedance DC 1 Low Detection Threshold 1 09 1 2 1 27 POWER ON RESET Voo POR Detection Threshold 2 5 2 95 POR Active Timeout Period 33 ms Vswout POR Detection Threshold 1 8 2 2 POR Active Timeout Period 20 ms Vinto POR Detection Threshold 2 0
7. Rev C Page 150 of 156 ADE5166 ADE5169 ADE5566 ADE5569 PORT O Port 0 is controlled directly through the bit addressable Port 0 SFR Address 0x80 The weak internal pull ups for Port 0 are configured through the Port 0 weak pull up enable SFR PINMAPO Address 0xB2 they are enabled by default The weak internal pull up is disabled by writing a 1 to PINMAPO x Port 0 pins also have various secondary functions as described in Table 168 The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the Port 0 SFR contains a 1 PORT 1 Port 1 is an 8 bit bidirectional port controlled directly through the bit addressable Port 1 SFR P1 Address 0x90 The weak internal pull ups for Port 1 are configured through the Port 1 weak pull up enable SFR PINMAPI Address 0xB3 they are enabled by default The weak internal pull up is disabled by writing a 1 to PINMAPI x Port 1 pins also have various secondary functions as described in Table 169 The alternate functions of Port 1 pins can be activated only if the corresponding bit latch in the Port 1 SFR contains a 1 PORT 2 Port 2 is a 4 bit bidirectional port controlled directly through the bit addressable Port 2 SFR P2 Address 0 Note that P2 3 can be used as an output only Consequently any read operation such as a CPL P2 3 cannot be executed on this I O The weak internal pull ups for Port 2 are configured through the
8. SAG EVENT EVENT IF SWITCHOVER ON LOW IS FSAG 1 FVDCIN 1 ENABLED AUTOMATIC BATTERY SWITCHOVER OCCURS Vswour IS CONNECTED TO Vgar BSO EVENT FBSO 1 07411 015 Figure 36 Power Supply Management Interrupts and Battery Switchover with or Voc Enabled for Battery Switchover Rev C Page 33 of 156 ADE5166 ADE5169 ADE5566 ADE5569 Vp VN SAG LEVEL TRIP POINT VpciN 1 2V Vswour BATTERY SWITCH ENABLED ON LOW Vswour BATTERY SWITCH ENABLED ON LOW Vpp HU SUN Una St UUVMV SAG EVENT Voc EVENT PSM1 5 2 T gi 5 0 I si SS PSMO 7 PSM1 OR 2 77 Figure 37 Power Supply Management Transitions Between Modes Rev C Page 34 of 156 07411 016 ADE5166 ADE5169 ADE5566 ADE5569 OPERATING MODES PSMO NORMAL MODE In 5 0 mode or normal operating mode Vswour is connected to All of the analog circuitry and digital circuitry powered by Vino and are enabled by default In normal mode the default clock frequency which is established during a power on reset or software reset is 1 024 MHz PSM1 BATTERY MODE In 5 mode or battery mode Vswovr is connected to In this operating mode the 8052 core and all of the digital circuitry are enabled by default The analog circuitry for the ADE energy met
9. Bit Mnemonic Default Description 7 R W 0 Read or write LCD bit If this bit is set to 1 the data in the LCD data SFR LCDDAT Address OxAE is written to the address indicated by the ADDRESS bits LCDPTR 3 0 6 Reserved 0 Reserved 5 4 RAM2SCREEN 0 These bits select the screen recipient of the data memory action 3 0 ADDRESS 0 LCD memory address see Table 102 Table 100 LCD Data SFR LCDDAT Address OxAE Bit Mnemonic Default Description 7 0 LCDDATA 0 Data to be written into or read out of the LCD memory SFRs Table 101 LCD Segment Enable 2 SFR LCDSEGE2 Address 0xED Bit Mnemonic Default Description 7 4 Reserved 0 Reserved 3 FP19EN 0 FP19 function select bit 0 general purpose I O 1 LCD function 2 18 0 FP18 function select bit 0 general purpose I O 1 LCD function 1 FP17EN 0 FP17 function select bit 0 general purpose I O 1 LCD function 0 FP16EN 0 FP16 function select bit 0 general purpose I O 1 LCD function LCD SETUP LCD TIMING AND WAVEFORMS The LCD configuration SFR LCDCON Address 0x95 configures the LCD module to drive the type of LCD in the user end system The BIAS bit Bit 2 and the LMUX bits Bits 1 0 in this SFR should be set according to the LCD specifications The COM2 FP28 and COM3 FP27 pins default to LCD segment lines Selecting the 3x multiplex level in the LCD configuration SFR LCDCON Address 0x95 by setting LMUX 1 0 to
10. DPTR Move external 16 data to MOVX Ri A Move A to external data A8 MOVX DPTR A Move A to external data A16 PUSH dir Push direct byte onto stack POP dir Pop direct byte from stack XCH A Rn Exchange A and register XCH A Ri Exchange A and indirect memory XCHD A Ri Exchange A and indirect memory nibble XCH A dir Exchange A and direct byte Boolean CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 Set carry 1 1 SETB bit Set direct bit 2 2 CPLC Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit and carry 2 2 ANL C bit AND direct bit inverse to carry 2 2 ORL bit OR direct bit and carry 2 2 ORL C bit OR Direct bit inverse to carry 2 2 MOV C bit Move direct bit to carry 2 2 MOV bit C Move carry to direct bit 2 2 Rev C Page 87 of 156 ADE5166 ADE5169 ADE5566 ADE5569 Mnemonic Description Bytes Cycles Branching JMP A DPTR Jump indirect relative to DPTR 1 3 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 ACALL addr11 Absolute jump to subroutine 2 3 AJMP addr11 Absolute jump unconditional 2 3 SJMP rel Short jump relative address 2 3 JC rel Jump on carry equal to 1 2 3 JNC rel Jump on carry 0 2 3 JZ rel Jump on accumulator 0 2 3 JNZ rel Jump on accumulator z 0 2 3 DJNZ Rn rel Decrement register JNZ relative 2 3 LJMP Long jump unconditional 3 4 LCALL addr16 Long jump to subroutine 3 4 JB bit rel Jump on dir
11. Bit Mnemonic Default Description 7 0 RTC DATA 0 Location of data for read write RTC operation Table 132 RTC Nominal Compensation SFR RTCCOMP Address 0xF6 Bit Mnemonic Default Description 7 0 0 Holds the nominal RTC compensation value at 25 C Note that this register is reset after watchdog reset an external reset or a power on reset POR Table 133 RTC Temperature Compensation SFR TEMPCAL Address 0xF7 Bit Mnemonic Default Description 7 0 TEMPCAL 0 Calibrates the RTC over temperature This allows the external crystal shift to be compensated over temperature Note that this register is reset after a watchdog reset an external reset power on reset POR Rev C Page 122 of 156 ADE5166 ADE5169 ADE5566 ADE5569 RTC REGISTERS Table 134 RTC Register List Address Signed Default RTCPTR 4 0 Mnemonic R W Length Unsigned Value Description 0x00 Reserved N A N A N A Reserved 0x01 HTHSEC R W 8 U 0 Counter Updates every 1 128 second referenced from the calibrated 32 768 kHz clock It overflows from 127 to 00 incrementing the seconds counter SEC 0x02 SEC R W 8 U 0 Counter Updates every second referenced from the calibrated 32 768 kHz clock It overflows from 59 to 00 incrementing the minutes counter MIN 0x03 MIN RW 8 U 0 Counter Updates every
12. Registers 123 Calendar tecti tte 124 RICInterr pts cite e va cie N 125 REVISION HISTORY 6 10 Rev B to Rev C Changes to Bit 5 148 Changes to Ordering Guide sse 153 11 09 Rev A to Rev B Deleted RTCCAL Function see Throughout Changes to Fault Detection ADE5166 ADE5169 Only Section ice oe t 51 2 09 Rev 0 to Rev A Added 5566 5569 Universal Changes to General Features and Microprocessor Features 1 Change to Figure 29 Figure 30 and Figure 31 23 RTC Crystal Compensation 126 UART Serial Interface UART 127 UART Operation 130 UART Baud Rate Generation serere 131 UART Additional Features 133 UART2 Serial Interface 134 UARIZSFERS G RI 134 UART2 Operation Modes sse 136 UART2 Baud Rate Generation serere 136 UART2 Additional Features 137 Serial Peripheral Interface SPT sss 138 138 SPISPANS E 141 SPI Master Operating 142 SPI Interrupt and Status 143 PC Compatible 144 Serial Clock 144 Slave Addresses j
13. 90 00 90 05 40 45 50 55 60 65 70 FREQUENCY Hz 07411 030 Figure 54 Combined Phase Response of the Digital Integrator and Phase Compensator 40 Hz to 70 Hz Note that the integrator has a 20 dB dec attenuation and an approximately 90 phase shift When combined with a di dt sensor the resulting magnitude and phase response should be a flat gain over the frequency band of interest The di dt sensor has a 20 dB dec gain associated with it It also generates significant high frequency noise Therefore a more effective antialiasing filter is needed to avoid noise due to aliasing see the Antialiasing Filter section When the digital integrator is switched off the ADE5169 ADE5569 can be used directly with a conventional current sensor such as a current transformer CT or with a low resistance current shunt POWER QUALITY MEASUREMENTS Zero Crossing Detection Each ADE5166 ADE5169 ADE5566 ADE5569 has a zero crossing detection circuit on the voltage channel This external zero crossing signal can be output on 0 5 and P1 2 see Table 39 It is also used in calibration mode The zero crossing is generated by default from the output of LPF1 This filter has a low cutoff frequency and is intended for 50 Hz and 60 Hz systems If needed this filter can be disabled to allow a higher frequency signal to be detected or to limit the group delay of the detection If the voltage input fundamental frequency is
14. Rev C Page 17 of 156 ADE5166 ADE5169 ADE5566 ADE5569 E 8 2 2 tu a 5 5 2 8 3 E e S lt 2 gt 6 gt gt gt gt gt dt 2 gt gt 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 cowarrP27 48 iNTO PIN 1 2 28 2 47 XTAL1 1 3 46 XTAL2 cowo 4 45 BCTRL INT1 P0 0 1 2 25 2 5 44 SDEN P2 3 TxD2 P1 3 T2EXIFP24 6 43 0 2 1 1 4 2 23 7 42 2 1 5 22 8 ADES566 ADE5569 41 P0 4 MOSI SDATA TOP VIEW 9 40 1 6 21 Notis Scale P0 5 MISO ZX 1 7 20 10 39 P0 6 SCLK TO PO 1 FP49 11 38 PO 7 SS T4 RxD2 P2 0 FP18 12 37 P1 0 RxD P2 1 FP17 13 36 P1 1 TxD P2 2 FP16 14 35 FPO LCDVC 15 34 1 Lepvp2 16 33 FP2 17 18 19 20 21 221123 24 25 26 27 28 29 1 30 31 32 lt 8 a4 9 Figure 10 ADE5566 ADE5569 Pin Configuration Table 14 Pin Function Descriptions Pin No Mnemonic Description 1 COM3 FP27 Common Output 3 LCD Segment Output 27 COM3 is used for the LCD backplane 2 COM2 FP28 Common Output 2 LCD Segment Output 28 COM2 is used for the LCD backplane 3 COMI Common Output 1 COMI is used for the LCD backplane 4 COMO Common Output 0 COMO is used for the LCD backplane 5 P1 2 FP25 ZX Genera
15. Table 117 Timer 0 Low Byte SFR TLO Address 0x8A Bit Mnemonic Default Description 7 0 TLO 0 Timer 0 data low byte Table 118 Timer 1 High Byte SFR TH1 Address 0x8D Bit Mnemonic Default Description 7 0 TH1 0 Timer 1 data high byte Table 119 Timer 1 Low Byte SFR TL1 Address 0x8B Bit Mnemonic Default Description 7 0 0 Timer 1 data low byte Table 120 Timer 2 High Byte SFR TH2 Address 0xCD Bit Mnemonic Default Description 7 0 TH2 0 Timer 2 data high byte Table 121 Timer 2 Low Byte SFR TL2 Address 0xCC Bit Mnemonic Default Description 7 0 TL2 0 Timer 2 data low byte Table 122 Timer 2 Reload Capture High Byte SFR RCAP2H Address OxCB Bit Mnemonic Default Description 7 0 TH2 0 Timer 2 reload capture high byte Table 123 Timer 2 Reload Capture Low Byte SFR RCAP2L Address 0xCA Bit Mnemonic Default Description 7 0 TL2 0 Timer 2 reload capture low byte TIMER 0 AND TIMER 1 Timer 0 High Low and Timer 1 High Low Data Registers Each timer consists of two 8 bit SFRs For Timer 0 they are Timer 0 high byte THO Address 0 8 and Timer 0 low byte 110 Address 0x8A For Timer 1 they are Timer 1 high byte Address 0x8D and Timer 1 low byte Address 0 8 These SFRs can be used as indepe
16. 5 0 Power supply restored interrupt flag Set when the power supply has been restored This occurs when the source of Vswour changes from to 6 OxFE FPSM 0 PSM interrupt flag Set when an enabled PSM interrupt condition occurs 5 OxFD FSAG 0 Voltage SAG interrupt flag Set when an ADE energy measurement SAG condition occurs 4 OxFC Reserved 0 This bit must be kept at 0 for proper operation 3 OxFB FVADC 0 VocwADC monitor interrupt flag Set when changes by VDCIN_DIFF or when the Voc measurement is ready 2 OxFA FBAT 0 monitor interrupt flag Set when falls below or when measurement is ready 1 OxF9 FBSO 0 Battery switchover interrupt flag Set when Vswour switches from to 0 OxF8 FVDCIN 0 monitor interrupt flag Set when falls below 1 2 V Table 19 Battery Switchover Configuration SFR BATPR Address 0 5 Bit Mnemonic Default Description 7 2 Reserved 0 These bits must be kept at 0 for proper operation 1 0 BATPRG 0 Control bits for battery switchover BATPRG Result 00 Battery switchover enabled on low 01 Battery switchover enabled on low and low 1X Battery switchover disabled 1X don t care Table 20 Peripheral Configuration SFR PERIPH Address 0 4 Bit Mnemonic Default Description 7 RX2FLAG 0 If set indicates that
17. JEDEC STANDARDS MS 026 BCD Figure 119 64 Lead Low Profile Quad Flat Package LQFP ST 64 2 Dimensions shown in millimeters ORDERING GUIDE di dt Sensor Flash Temperature Package Package Model 2 Antitamper Interface Var kB Range Description Option ADE5166ASTZF62 Yes No No 62 40 C to 85 C 64 Lead LOFP ST 64 2 ADES5166ASTZF62 RL Yes No No 62 40 C to 85 64 Lead LOFP 13 Tape amp Reel ST 64 2 ADE5169ASTZF62 Yes Yes Yes 62 40 C to 85 C 64 Lead LOFP ST 64 2 ADE5169ASTZF62 RL Yes Yes Yes 62 40 C to 85 64 Lead 13 Tape amp Reel ST 64 2 5566 5 2 62 62 40 to 85 C 64 Lead LOFP ST 64 2 ADE5566ASTZF62 RL No No No 62 40 C to 85 C 64 Lead LOFP 13 Tape amp Reel ST 64 2 5569 5 7 62 Yes Yes 62 40 C to 85 C 64 Lead LOFP ST 64 2 ADE5569ASTZF62 RL No Yes Yes 62 40 C to 85 C 64 Lead LOFP 13 Tape amp Reel ST 64 2 ADE8052Z PRG1 ADE Programmer ADE8052Z DWDL1 ADE Downloader ADE8052Z EMUL1 ADE Emulator 1 All models have W VA rms 5 V LCD RTC 27 RoHS Compliant Part Rev C Page 153 of 156 ADE5166 ADE5169 ADE5566 ADE5569 NOTES Rev C Page 154 of 156 ADE5166 ADE5169 ADE5566 ADE5569 NOTES Rev C Page 155 of 156 ADE5166 ADE5169 ADE5566 ADE5569 NOTES PC refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors 2008 2010 Analog D
18. WP WP WP WP OxF7EF 56 59 52 55 RP RP RP RP RP RP 28 31 24 27 20 23 16 19 12 15 8 11 4 7 OxF7EB PROTECTION KEY OxF600 07411 124 Figure 96 Flash Protection in Page 124 Rev Page 111 of 156 ADE5166 ADE5169 ADE5566 ADE5569 Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use the reserved emulator commands available only in download mode These commands write directly to the SFRs and can be used to duplicate the operation described in the Enabling Flash Protection by Code section When these flash bytes are written the part can exit emulation mode by reset and the protections are effective This method can be used in production and implemented after downloading the program The commands used for this opera tion are an extension of the commands listed in Application Note uC004 Understanding the Serial Download Protocol available at www analog com Command with ASCII Code I or 0x49 writes the data into RO Command with ASCII Code or 0x46 writes RO into the SFR address defined in the data of this command Omitting the protocol defined in the uC004 Application Note the sequence to load protections is similar to the sequence men tioned in the Enabling Flash Protection by Code section except that two emulator commands are necessary to replace one assembly command For e
19. Parameter Description Min Typ Max Unit tz SS to SCLK edge 145 ns tsi SCLK low pulse width 6 x tcore ns tsH SCLK high pulse width 6 x tore ns Data output valid after SCLK edge 25 ns tosu Data input setup time before SCLK edge 0 ns Data input hold time after SCLK edge 2 X tcore 0 5 Hs tor Data output fall time 19 ns tor Data output rise time 19 ns tsr SCLK rise time 19 ns tsF SCLK fall time 19 ns tooss Data output valid after SS edge 0 ns 1566 SS high after SCLK edge 0 ns 1 depends on the clock divider or the CD bits of the POWCON SFR Address 0xC5 2 0 see Table 26 2 lt 2 4 096 MHz SCLK SPICPOL 0 SCLK SPICPOL 1 MISO MOSI tosu tpup Figure 8 SPI Slave Mode Timing SPICPHA 0 Rev C Page 14 of 156 tsrs BITS 6 1 X LSB 07411 007 ADE5166 ADE5169 ADE5566 ADE5569 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress Table 11 rating only functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational Voo to 0 3 V to 37 V section of this specification is not implied Exposure to absolute Vsar to DGND 0 3 V to 3 7 V maximum rating conditions for extended periods may affect to 0 3 V
20. 0 04 SAG FLAG IS RESET SAG FLAG 3 LINE CYCLES 07411 033 Figure 57 SAG Detection Figure 57 shows the line voltage falling below a threshold that is set in the SAG level register SAGLVL Address 0x14 15 0 for three line cycles The quantities 0 and 1 are not valid for the SAGCYC register and the contents represent one more than the desired number of full line cycles For example when the SAG cycle register SAGCYC Address 0x13 7 0 contains 0x04 FSAG Bit 5 in the power management interrupt flag SFR IPSME Address OxF8 is set at the end of the third line cycle after the line voltage falls below the threshold If the SAG enable bit ESAG Bit 5 in the power management interrupt enable SFR IPSME Address is set 8052 core has a pending power supply management interrupt The PSM interrupt stays active until the ESAG bit is cleared see the Power Supply Management PSM Interrupt section In Figure 57 the SAG flag FSAG is set on the fifth line cycle after the signal on the voltage channel first drops below the threshold level SAG Level Set The 2 byte contents of the SAG level register SAGLVL Address 0x14 are compared to the absolute value of the output from LPF1 Therefore when LPF1 is enabled writing 0x2038 to the SAG level register puts the SAG detection level at full scale see Figure 57 Writing 0x00 or 0x01 puts the SAG detection level at 0 The SAG level register is compared to the inpu
21. ADE5166 ADE5169 ADE5566 ADE5569 Table 135 RTC Calibration Configuration Register RTC_CAL Address 0x0F Bit Mnemonic Default Description 7 CAL_EN_PSM2 0 When this bit is set and the CAL EN bit is set the RTC output is present on 5 50 2 PSM2 mode The RTC output is disabled on all other pins in PSM2 mode 6 CAL EN 0 RTC calibration enable output CAL EN Result 0 The RTC calibration output signal is disabled 1 The RTC calibration output signal is enabled and present on the pins selected by the P2P3 P1P2 RTC POP7 and 5 bits Bits 3 0 5 4 FSEL 1 0 00 RTC calibration output frequency selection FSEL Frequency Calibration Window 00 1Hz 30 5 sec 01 512Hz 30 5 sec 10 500 Hz 0 244 sec 11 16 kHz 0 244 sec 3 P2P3 0 When this bit is set and the CAL EN bit is set the RTC output is present on the P2 3 SDEN TxD2 pin 2 1 2 0 When this bit is set and the bit is set the RTC output is present on the P1 2 FP25 ZX pin 1 RTC_POP7 0 When this bit is set and the CAL_EN bit is set the RTC output is present on the P0 7 SS T1 RxD2 pin 0 5 0 When this bit is set and the EN bit is set the RTC output is present the P0 5 MISO ZX pin RTC CALENDAR The RTC has a full calendar taking into account leap years The rollover of the date to increment the month is implemented according to the parameters shown
22. Erase Page Erase the page containing Flash Memory Byte 0x3C00 MOV EADRH 3Ch Select page through byte address MOV EADRL 00h MOV FLSHKY 3Bh Write flash security key MOV ECON 02H Erase Page Erase All Erase all of the 62 kB flash memory MOV FLSHKY 3Bh Write flash security key MOV ECON 03H Erase all Read Byte Read Flash Memory Byte 0x3C00 MOV EADRH 3Ch Set up byte address MOV EADRL 00h MOV FLSHKY 3Bh Write flash security key MOV ECON 04H Read byte Data is ready in EDATA register Note that the read byte command can be used to view the status of the protection bytes located in the upper 21 bytes Page 123 The write byte command is not valid for this area PROTECTING THE FLASH MEMORY Two forms of protection are offered for this flash memory read protection and write erase protection The read protection ensures that any pages that are read protected cannot be read by the end user The write protection ensures that the flash memory cannot be erased or written over This protects the final product from tampering and can prevent the code from being overwritten in the event of a runaway program Write erase protection is individually selectable for all 124 pages Read protection is selected in groups of four pages see Figure 95 for the groupings The protection bits are stored in the last flash memory locations Address 0xF7EB through Address OxF7FF see Figure 96 Sixteen
23. The discrete time sample period T for the accumulation register in the ADE5169 ADE5569 is 1 22 us 5 MCLK As well as calculating the energy this integration removes any sinusoidal components that may be in the active power signal Figure 72 shows this discrete time integration or accumulation The reactive power signal in the waveform register is continuously added to the internal reactive energy register The reactive energy accumulation depends on the setting of SAVARM Bit 2 and ABSVARM Bit 3 in the ACCMODE register Address OxOF When both bits are cleared the addition is signed and therefore negative energy is subtracted from the reactive energy contents When both bits are set the ADE5169 ADE5569 are set to the more restrictive mode which is the absolute accumulation mode When the SAVARM bit Bit 2 in the ACCMODE register Address OxOF is set the reactive power is accumulated depending on the sign of the active power When active power is positive the reactive power is added as it is to the reactive energy register When active power is negative the reactive power is subtracted from the reactive energy accumulator see the Var Antitamper Accumulation Mode section When the ABSVARM bit Bit 3 in the ACCMODE register Address OxOF is set the absolute reactive power is used for the reactive energy accumulation see the Var Absolute Accumulation Mode section FOR WAVEFORM SAMPLING 23 VARHR 23 0 UD BASE
24. bits in the SPI interrupt status SFR SPISTAT Address 0xEA does not cancel a pending I C SPI interrupt These interrupts remain pending until the I C SPI interrupt vectors are enabled Their respective interrupt service routines are entered shortly thereafter The RTC interrupts are driven by the alarm and interval flags Pending RTC interrupts can be cleared without entering the interrupt service routine by clearing the corresponding flag in software Entering the interrupt service routine alone does not clear the RTC interrupt Figure 89 shows how the interrupts are cleared when the inter rupt service routines are entered Some interrupts with multiple interrupt sources are not automatically cleared specifically the PSM ADE UART UART2 and Timer 2 interrupt vectors Note that the INTO and INTI interrupts are cleared only if the external interrupt is configured to be triggered by a falling edge by setting ITO Bit 0 and IT1 Bit 2 in the Timer Counter 0 and Timer Counter 1 control SFR TCON Address 0x88 If INTO or INTI is configured to interrupt on a low level the interrupt service routine is reentered until the respective pin goes high Rev C Page 94 of 156 ADES166 ADE5169 ADE5566 ADE5569 IE IEIP2 REGISTERS 2 REGISTERS PRIORITY LEVEL LOW HIGH HIGHEST 5 PSM IPSMF 6 INTERVAL lt ALARM gt I m Nm MIRGENH MIRGENM
25. or low Vpp enabled Finally the transition between and Vsar and the different power supply modes see the Operating Modes section are represented in Figure 37 and Figure 38 VOLTAGE SUPERVISORY 07411 013 Figure 34 Power Supply Management for Energy Meter Application Table 27 Power Supply Event Timing Operating Modes Parameter Time Description ti 10 ns min Time between when goes below 1 2 V and when FVDCIN is raised t 10 ns min Time between when falls below 2 75 V and when battery switchover occurs 30 ms typ Time between when falls below 1 2 V and when battery switchover occurs if Vocin is enabled to cause battery switchover ta 130mstyp Time between when power supply restore conditions are met gt 1 2 V and Voo gt 2 75 V if the BATPRG bits 0601 or Voo gt 2 75 V if the BATPRG bits 0600 and when Vswour switches to Rev C Page 32 of 156 ADE5166 ADE5169 ADE5566 ADE5569 Vp VN SAG LEVEL TRIP POINT SAGCYC 1 VpciN bomo Vpp 2 75V SAG EVENT EVENT IF SWITCHOVER ON LOW Vpp IS ENABLED FSAG 1 FVDCIN 1 AUTOMATIC BATTERY SWITCHOVER OCCURS Vswour IS CONNECTED TO Vgar BSO EVENT FBSO 1 07411 014 Figure 35 Power Supply Management Interrupts and Battery Switchover with Only Vpp Enabled for Battery Switchover Vp VN SAG LEVEL TRIP POINT SAGCYC 1
26. Address OxF4 is set to indicate that Vswour is connected Interval Maskable ITFLAG TIMECON 2 IRTC The ADE5166 ADE5169 ADE5566 ADE5569 wake up after the programmable time interval has elapsed The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode Alarm Maskable ALFLAG 6 be set to wake the ADE5166 ADE5169 ADE5566 ADE5569 after the desired amount of time The RTC alarm is enabled by setting the ALxxx_EN bits in the RTC Configuration 2 SFR 2 Address 2 The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode Ports INTO INTOPRG 1 INTPR O N A IEO The edge of the interrupt is selected by the ITO bit Bit 0 in the TCON SFR TCON Address 0x88 The IEO flag Bit 1 in the TCON SFR is not affected The Interrupt 0 interrupt needs to be serviced and acknowledged prior to entering PSM2 mode INT1PRG 11x INTPR 3 1 N A IE The edge of the interrupt is selected by the IT1 bit Bit 2 in the TCON SFR TCON Address 0x88 The IE1 flag Bit 3 in the TCON SFR is not affected The Interrupt 1 interrupt needs to be serviced and acknowledged prior to entering PSM2 mode 2 edge RXPROG 11 PERIPH 1 0 RX2FLAG PERIPH 7 N A An Rx edge event occurs if a rising or falling edge is detected on the RxD2
27. Figure 64 Active Power Calculation Because LPF2 does not have an ideal brick wall frequency response see Figure 65 the active power signal has some ripple due to the instantaneous power signal This ripple is sinusoidal and has a frequency equal to 2x the line frequency Because of its sinu soidal nature the ripple is removed when the active power signal is integrated to calculate energy see the Active Energy Calculation section 8 ATTENUATION dB 1 e 1 3 10 30 100 FREQUENCY Hz 07411 040 Figure 65 Frequency Response of LPF2 Rev C Page 59 of 156 ADE5166 ADE5169 ADE5566 ADE5569 Active Power Gain Calibration Figure 66 shows the signal processing chain for the active power calculation in the ADE5166 ADE5169 ADE5566 ADE5569 As explained previously the active power is calculated by filtering the output of the multiplier with a low pass filter Note that when reading the waveform samples from the output of LPF2 the gain of the active energy can be adjusted by using the multiplier and writing a twos complement 12 bit word to the the watt gain reg ister WGAIN Address Ox1D 11 0 Equation 10 shows how the gain adjustment is related to the contents of the watt gain register Output WGAIN Acte Powerx E 10 For example when 0x7FF is written to watt gain register power output is scaled up by 50 0x7FF 20474 2047 2 0 5 Similarly 0x800
28. Two SFRs the enhanced serial baud rate control SFR SBAUDT Address 0x9E and UART timer fractional divider SFR SBAUDE Address 0x9D are used to control the UART timer SBAUDT is the baud rate control SFR it sets up the integer divider the DIV bits Bits 2 0 and the extended divider the SBTH bits Bits 4 3 for the UART timer The appropriate value to write to the DIV bits and the SBTH bits can be calculated using the following formula where is defined in the POWCON SFR see Table 26 Note that the DIV value must be rounded down to the nearest integer log 16 log 2 DIV SBTH TIMER 1 OVERFLOW CONTROL T2 PIN P1 4 T2 FP23 NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT T2EX PIN P1 3 T2EX FP24 CONTROL TRANSITION DETECTOR EXEN2 8 BITS TL2 TH2 ze TIMER 2 OVERFLOW Rx CLOCK Tx CLOCK TIMER 2 INTERRUPT P1 4 T2 FP23 07411 080 Figure 107 Timer 2 Baud Rates Rev C Page 132 of 156 ADE5166 ADE5169 ADE5566 ADE5569 SBAUDF is the fractional divider ratio required to achieve the required baud rate The appropriate value for SBAUDF can be calculated with the following formula SBAUDF 64 x 1 x Baud Rate Note that SBAUDF should be rounded to the nearest integer After the values for DIV and SBAUDF are calculated the actual baud rate can be calculated with the foll
29. and CF2 enable bit Bit 7 in the Interrupt Enable 2 SFR MIRQENM Address OxDA are set the 8052 core has a pending ADE interrupt The ADE interrupt stays active until the CF1 or CF2 status bit is cleared see the Energy Measurement Interrupts section Pulse Output Configuration The two pulse output circuits have separate configuration bits in the MODE2 register Address 0 0 Setting the CFxSEL bits to 0500 0501 or Ob1X configures DFC to create a pulse output proportional to active power reactive power or apparent power or respectively The selection between Irms and apparent power is done by VARMSCFCON bit Bit 3 MODE2 register Address 0 0 With this selection CF2 cannot be proportional to apparent power if CF1 is proportional to La and CF1 cannot be proportional to apparent power if CF2 is proportional to Pulse Output Characteristic The pulse output for both DFCs stays low for 90 ms if the pulse period is longer than 180 ms 5 56 Hz If the pulse period is shorter than 180 ms the duty cycle of the pulse output is 5096 The pulse output is active low and should preferably be connected to an LED as shown in Figure 80 Vpp cr Figure 80 Pulse Output The maximum output frequency with ac input signals at full scale and CFxNUM 0x00 and CFxDEN 0x00 is approximately 21 1 kHz The ADE5166 ADE5169 A DE5566 ADE5569 incorporate two registers per DFC CFXNUM 15 0 an
30. below 60 Hz and a time delay in ZX detection is acceptable it is recommended that LPF1 be enabled Enabling LPF1 limits the variability in the ZX detection by eliminating the high frequency components Figure 55 shows how the zero crossing signal is generated The zero crossing signal ZX is generated from the output of LPF1 bypassed or not LPF1 has a single pole at 63 7 Hz at 4 096 MHz As a result there is a phase lag between the analog input signal V2 and the output of LPF1 The phase lag response of LPF1 results in a time delay of approximately 2 ms at 60 Hz between the zero crossing on the analog inputs ofthe voltage channel and ZX detection 1 2 4 REFERENCE 8 16 GAIN 7 5 HPF vo lt ance 2 CROSSING 7X LPF1 f 63 7Hz 07411 031 Figure 55 Zero Crossing Detection on the Voltage Channel The zero crossing detection also drives the ZX flag in the Inter rupt Status 3 SFR MIRQSTH Address OxDE If the ZX bit Bit 0 in the Interrupt Enable 3 SFR MIRQENH Address OxDB is set the 8052 core has a pending ADE interrupt The ADE interrupt stays active until the ZX status bit is cleared see the Energy Measurement Interrupts section Zero Crossing Timeout The zero crossing detection also has an assoc