Home

FREESCALE MC9S08AW60 MC9S08AW48 MC9S08AW32 MC9S08AW16 handbook

Contents

1. 5 E P Tm DOCUMENT 98ASB42844B e ELM E semiconductor RESERVED i i i i G gt 8 4 0 M EN e Wr COT Santen Pr M D 5 L 1 5 D R W I R E B NOTES 1 DIMENSIONING AND TOLERANCING PER ASME 14 5 1994 2 CONTROLLING DIMENSION MILLIMETER 3 DATUM PLANE 1 LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 4 DATUMS AND 0 TO BE DETERMINED AT DATUM PLANE H BN DIMENSIONS TO BE DETERMINED AT SEATING PLANE C DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25mm PER SIDE DIMENSIONS DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE ZX DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08mm TOTAL IN EXCESS OF THE DIMENSION AT MAXIMUM MATERIA CONDICTION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT TIE CASE NUMBER 8408 01 64LD QFP 14 X 14 STANDARD NON JEDEC PACKAGE CODE 6057 SHEET 3 4
2. T MECHANICAL OUTLINES DOCUMENT NO 98ASS23234W FREESCALE SEMICONDUCTOR semiconductor RESERVED eun PACE sid VERSIONS Es CONT ROLLED Seer NE D 5 s L E 1 5 D R W I N G R E V D NOTES 1 DIMENSIONS ARE IN MILLIMETERS 2 DIMENSIONING AND TOLERANCING PER ASME Y14 5 1994 3 DATUMS A B AND D TO BE DETERMINED AT DATUM PLANE H DIMENSIONS TO BE DETERMINED AT SEATING PLANE C THIS DIMENSION DOES CLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHA OT CAUSE THE LEAD WIDTH TO EXCEED THE UPPER LIMIT BY MORE THAN 0 mm AT MAXIM ATERIAL CONDITION DAMBAR CANNOT BE OCATED O E LOWER RADIUS OR THE FOOT MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHA OT BE LESS THAN 0 07 THIS DIMENSION DOES NO CLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 mm PER SIDE THIS DIMENSION IS MAXIMUM PLASTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATC IN EXACT SHAPE OF EACH CORNER IS OPTIONAL HESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 1 mm AND 0 25 mm FROM THE LEAD TITLE 6410 LQFP CASE NUMBER 840 02 10 X 10 X 1 4 PKG STANDARD JEDEC MS 026 BCD 2 C ASE OUT
3. ME PLANE sesope 0 12 2 VIEW AA TITLE 64LD LQFP CASE NUMBER 840F 02 10 X 10 X 1 4 PKG STANDARD 5 026 BCD PITCH CASE OUTLINE PACKAGE CODE 8426 SHEET 1 OF 4 freescale semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED COPY IN RED MECHANICAL OUTLINES DOCUMENT NO 98ASS23234W DICTIONARY m BAOF DO NOT SCALE THIS DRAWING REV D 0 22 BASE METAL B B 0 20 d 09 0 09 8 S PLATING 3 023 p 28 8N OR D SECTION VIEW Y MIN 1 45 0 15 555 0 05 RO 08 73 10 i M 1 00 VIEW AA TITLE Bat b E CASE NUMBER 840F 02 10 X 1O X 1 4 STANDARD 5 026 BCD enc Wr CONO SDN TE PACKAGE CODE 8426 SHEE
4. 0 mc 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor 4 5 4 6 24 5 2 23 5 4 II 5 6 2 7 5 8 5 9 Prosa and Erase TIMES bea eu m bns 50 4 4 3 Program and Erase Command Execution gt cunt P9 In Ra RENI PR M Ede tpa EAS 21 44 Burst Program E remeron reon a E E A A 52 AAS Access BET oot 54 445 FLASH Block Protection Eu tiia e esa Reve S aiu de 54 Vector ooo o cc 55 SCU aed E 23 FLASH and Control 57 401 FLASH Clock Divider Register FODIV 57 462 FLASH Options Register and NVOPT 58 4 6 3 FLASH Configuration Register FCNFG 59 464 FLASH Protection Register FPROT and NVPROT 60 4 6 5 FLASH 1 60 406 FLASH Command Register sarsari a r E 62 Chapter 5 Resets Interrupts and System Configuration IEDERE IOLE ATOI n Mert 63 63 SMe ec testes 63 Computer Operating Properly Watchdog
5. 33 39 Resets Interrupts and System Configuration 63 Parallel Input Output 5 terrre kh nah hene y aw Ro een a nnmnnn 79 Central Processor Unit S08CPUV2 107 Internal Clock Generator SO8ICGVA 127 Keyboard Interrupt 508 1 155 Timer PWM 508 2 22 12 163 Serial Communications Interface S08SCIV2 179 Serial Peripheral Interface SO8SPIV3 197 Inter Integrated Circuit SO8IICV1 215 Analog to Digital Converter S08ADCH10Vf1l 231 Development Support siseniuins in XX xS SEXXXXRRXXRRC M EEIEFKKAK E nnmnnn nnmn 257 Electrical Characteristics and Timing Specifications 279 Ordering Information and Mechanical Drawings 305 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor 7 1 1 1 2 13 21 2 2 2 5 3d 3 2 3 9 34 3 5 3 6 41 42 43 4 4 Chapter 1 Introduction NN DUM MM NE L EMO dii cui eem Systemi Clock Chapter 2 Pins and Connections Introduction
6. How to Reach Us USA Europe Locations not listed Freescale Semiconductor Literature Distribution P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 Japan Freescale Semiconductor Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 Asia Pacific Freescale Semiconductor H K Ltd 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Learn More For more information about Freescale Semiconductor products please visit http www freescale com 9508 60 Rev 1 0 1 2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which
7. 132 JEMEN C o o d inu M 132 53 1 gave RUFUS bv Qu 133 8 3 2 ICG Control Register 2 12602 1355 Cox ICG Status Resister L ICOS T Mr E 136 Bae ICG 137 boa ICG Filter Registers ICGFLTU ICGELTL 137 5 3 5 ICG Trim Resister ICG TRIM 138 54 Pumetiomal iu sua MR DM M ORUM 138 139 B4 Sel Ciucked Modeq9C aquai masia utis e 139 8 43 FLL Engaged Internal Clock FED Mode 140 FLL Engaged Internal Unlocked a Prope Gad pti 141 545 FLL Engaged Internal Locked 141 846 FLL Bypassed External Clock FBE Mode 141 8 4 7 FLL Engaged External Clock FEE Mode 141 8 4 8 FLL Lock and Loss of Lock Detection 142 549 FLA Detection 143 B Clock Mode ener 144 BAIT Fixed Fregueney Clock esmee E EA E E Fi DER gaudes 145 9412 High Gam TUS 145 9508 60 Data Sheet Rev 1 0 12 Freescale Semiconductor 8 5 9 1 92 95 9 4 9
8. PTE1 RxD1 3 PTEO TxD1 SERIAL COMMUNICATIONS INTERFACE MODULE SCI1 lt PTF7 gt 6 PTF5 TPM2CH1 PTFA TPM2CHO VOLTAGE REGULATOR 2 CHANNEL TIMER PWM MODULE 2 TPM2CH1 TPM2CHO PORTF gt 5 gt 2 r PTF1 TPM1CH3 PTFO TPM1CH2 7 5 8 KEYBOARD INTERRUPT MODULE 4 PTG6 EXTAL NOTES PTG5 XTAL 1 Port pins are software configurable with pullup device if input port PTG4 KBI1P4 2 Pin contains software configurable pullup pulldown device if IRQ is enabled PTG3 KBI1P3 IRQPE 1 Pulldown is enabled if rising edge detect is selected IRQEDG 1 PTG2 KBI1P2 3 IRQ does not have a clamp diode to Vpp IRQ should not be driven above Vpp 4 Pin contains integrated pullup device 5 Pins PTD7 PTD2 and PTG4 contain both pullup and pulldown devices Pulldown enabled when is enabled KBIPEn 1 and rising edge is selected KBEDGn lt 1 Figure 8 2 Block Diagram Highlighting ICG Module 9508 60 Data Sheet Rev 1 0 128 Freescale Semiconductor Internal Clock Generator SO8ICGV4 8 1 Introduction Figure 8 3 15 a top level diagram that shows the functional organization of the internal clock generation IC
9. 64 ete secre cusses te ect 64 65 22 2 External Regu st IRQ PIN 66 33 3 Interrupt Vectors Sources and Local Masks dad 67 Low Voltage Detect LV rims on 69 25 1 Poser On Reset Operation pus doi 69 50 2 LVD Reset Operation P 69 250 TV DD i UP Operation 69 26 4 Low Voltage Warning CLV 69 69 Po M 70 Reset Interrupt and System Control Registers and Control Bits 70 5 9 1 Interrupt Pin Request Status and Control Register 71 2592 System Status Resister 72 59 5 System Background Debug Force Reset Register SBDDPR urere ete 73 5 9 4 Options Register SOPT 19 5 95 System MCLE Control Register 5 74 39 0 System Device Identification Register SDIDH SDIDL 4 antitrust nce 13 5 9 7 System Real Time Interrupt Status and Control Register SRTISC 76 5 9 8 System Power Management Status and Control 1 Register SPMSC1
10. IRIS RAE 1101717 M RITO Recommended System Connections Dd p tn aoe nate ride 2 3 1 Power Vpp 2x VDDAD VssAD 22 Osella CCDAL ES DAD 2 52 RESET 2 3 4 Backeround Mode Select BKGD MS 2393 ADC Relerence Pins V piss V REPE Ext rnal Interr pt IRQ e 217 General Purpose I O and Peripheral denis Chapter 3 Modes of Operation I NE OD n R n uoo aM Active Backorownd PM V Wait Mode Me StoP trc bu t I Mode n M 202 STOPI e ERN 3 6 3 Active BDM Enabled m Stop Mode 254 LVD Enabledin Stop Mode 3 6 5 On Chip Peripheral Modules in Stop Modes Chapter 4 Memory MC9S08AW60 485 32 16 Memory 4 1 1 Reset and Interrupt Vector Assignments 2 Register Addresses and Bit Assignments
11. 1 Port pins are software configurable with pullup device if input port 2 Pin contains software configurable pullup pulldown device if IRQ is enabled IRQPE 1 Pulldown is enabled if rising edge detect is selected IRQEDG 1 IRQ does not have a clamp diode to Vpp IRQ should not be driven above Vpp Pin contains integrated pullup device Pins PTD7 PTD3 PTD2 and 4 contain both pullup and pulldown devices PORT lt gt PTG6 EXTAL gt PTG5 XTAL PT G4 KBI1P4 gt PTG2 KBI1P2 H 3 PTG1 KBITP1 gt PTGO KBI PO Pulldown enabled when is enabled KBIPEn 1 and rising edge is selected KBEDGn 1 Figure 1 1 MC9SO8AW60 48 32 16 Block Diagram MC9S08AW60 Data Sheet Rev 1 0 20 Freescale Semiconductor Chapter 1 Introduction Table 1 3 lists the functional versions of the on chip modules Table 1 3 Versions of On Chip Modules Analog to Digital Converter ADC Internal Clock Generator ICG Aaj Inter Integrated Circuit IIC Keyboard Interrupt KBI Serial Communications Interface SCI Serial Peripheral Interface SPI Timer Pulse Width Modulator TPM Debug Module DBG a NIN 1 3 System Clock Distribution FIXED FREQ CLOCK XCLK ICGOUT BUSCLK 5 ICGLCLK FLASH
12. MAR 09 FFFC FFFD Vswi FFFE FFFF Vreset MC9S08AW60 Data Sheet Rev 1 0 42 Freescale Semiconductor Chapter 4 Memory 4 2 Register Addresses and Bit Assignments The registers in the 9508 60 48 32 16 are divided into these three groups e Direct page registers are located in the first 112 locations in the memory map so they are accessible with efficient direct addressing mode instructions High page registers used much less often so they are located above 1800 in the memory map This leaves more room in the direct page for more frequently used registers and variables nonvolatile register area consists of a block of 16 locations in FLASH memory at SFFBO SFFBF Nonvolatile register locations include Three values which are loaded into working registers at reset An 8 byte backdoor comparison key which optionally allows a user to gain controlled access to secure memory Because the nonvolatile register locations are FLASH memory they must be erased and programmed like other FLASH memory locations Direct page registers can be accessed with efficient direct addressing mode instructions Bit manipulation instructions can be used to access any bit in any direct page register Table 4 2 is a summary of all user accessible direct page registers and control bits The direct page registers in Table 4 2 can use the more efficient direct addressing mode which only requires the lower
13. freescale DICTIONARY TUE mM semiconductor FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED VERSIONS ARE UNCDWIROLLED Except wien SCALE THIS DRAWING REV IN RED NOTES 1 DIMENSIONS AND TOLERANCING PER ASME 14 5 1994 2 CONTROLLING DIMENSION MILLIMETER 5 DATUM PLANE IS LOCATED AT BOTTOM GF LEAD AND IS COINCIDENT WITH THE EAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING NE 4 DATUMS L AND N TO BE DETERMINED DATUM PLANE H AN DI ENSIONS BE DETERMINED AT SEATING PLANE PROTRUSION 15 0 25 PER TERMINED AT DATUM ANDI ENSIONS DO NOT INCLUDE MOLD PROTRUSION ALLOWABL SIDE DIMENSIONS DO INCLUDE MOLD MISMATCH AND ARE D PLANE H FRO ENSION DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE DIMENSION EXCEED 0 55 MINIMUM SPACE BETWEEN PROTRUSION AND EAD OR PROTRUSION 0 07 ADJACE CAS IT 27 lt 52 TITL ER 8240 02 44 LD TQFP STANDARD JEDEC 026 TO X
14. 77 5 9 9 System Power Management Status and Control 2 Register SPMSC2 78 MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor Chapter 6 Parallel Input Output ON MEE o AO E 79 Dub FEES I E E E A 79 po Pu TSS Ci OR 80 BUE 80 B 80 BROC t odio MUR Ma PU DO NR 81 Port D e E 81 OM EMEN 82 AE DUE 83 TEI NER 83 SIN E 84 EM Je 85 Go Jutecnal Pullup EDS eaa 85 6 5 2 Output Slew Rate Control Enable 85 639 85 66 Bebayior m Stop A TEA umen EEE RER 86 6 7 Parallel I O and Pin Control 86 671 Port A Registers PTAD and PTADD 86 6 7 2 Port A Pin Control Registers PTAPE PTADS 87 Oj Port B 7 Registers PTB D and PTBDD 89 6 7 4 Port B Pin Control Registers PTBPE PTBSE PTBDS 22 22222 44 1 90 6 7 3 PTCD and PTCDD 92 6 7 6 Port C Pin Control Registers PTCPB P
15. This is set when the TPM counter changes to 0x0000 after reaching the modulo TOF value programmed in the TPM counter modulo registers When the TPM is configured for CPWM TOF is set after the counter has reached the value in the modulo register at the transition to the next lower count value Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF If another TPM overflow occurs before the clearing sequence is complete the sequence is reset so TOF would remain set after the clear sequence was completed for the earlier TOF Reset clears TOF Writing a 1 to TOF has no effect 0 TPM counter has not reached modulo value or overflow 1 TPM counter has overflowed 6 Timer Overflow Interrupt Enable This read write bit enables TPM overflow interrupts If TOIE is set an TOIE interrupt is generated when TOF equals 1 Reset clears TOIE 0 TOF interrupts inhibited use software polling 1 TOF interrupts enabled 5 Center Aligned PWM Select This read write bit selects CPWM operating mode Reset clears this bit so the CPWMS TPM operates in up counting mode for input capture output compare and edge aligned PWM functions Setting CPWMS reconfigures the TPM to operate in up down counting mode for CPWM functions Reset clears CPWMS 0 All TPMx channels operate as input capture output compare or edge aligned PWM mode as selected by the MSnB MSnA control bits in each channel s status and co
16. 208 er NE EO m 209 12 5 2 211 9508 60 Data Sheet Rev 1 0 14 Freescale Semiconductor 1243 Mode Fault Detect oN 212 12 5 Initialization Application Information PME dei ues ates is 212 1251 SPI Modu l Initialization BEample Jae a qase Dis afa acus 242 Chapter 13 Inter Integrated Circuit SO8IICV1 13 1 Introduction naa eee 215 217 151 2 Modes OF O E S 217 MT E M EROS EE 218 13 2 External Sicnal IDSs Cr Oe 218 132231 Seral Clock Lie etian 218 1322 SDA o MDC Wee T 218 13 3 Register P cie eT 218 13 3 1 MC Address Resistor 219 13 3 2 HC Frequency Divider Register UC I 219 13 33 MC Control Resister E E E 222 1334 MC Status Resister MCTS TA TE 223 133 9 MC Data VO Resister ICID 224 225 13 41 REL coU 225 c eec 228 228 vii 229 13 02 sende tuii eps tetuer 229 13 6 3 Arbit
17. 1 External Reference Clock Status The ERCS bit is an indication of whether or not the external reference ERCS clock ICGERCLK meets the minimum frequency requirement 0 External reference clock is not stable frequency requirement is not met 1 External reference clock is stable frequency requirement is met 0 ICG Interrupt Flag The ICGIF read write flag is set when an ICG interrupt request is pending It is cleared by ICGIF a reset or by reading the ICG status register when ICGIF is set and then writing a logic 1 to ICGIF If another ICG interrupt occurs before the clearing sequence is complete the sequence is reset so ICGIF would remain set after the clear sequence was completed for the earlier interrupt Writing a logic O to ICGIF has no effect 0 No ICG interrupt request is pending 1 An ICG interrupt request is pending MC9S08AW60 Data Sheet Rev 1 0 136 Freescale Semiconductor Internal Clock Generator SO8ICGV4 8 3 4 ICG Status Register 2 ICGS2 7 6 R 0 0 Ww Reset 0 0 Unimplemented or Reserved Figure 8 9 ICG Status Register 2 ICGS2 Table 8 5 ICGS2 Register Field Descriptions Field Description 0 DCO Clock Stable The DCOS bit is set when the DCO clock ICG2DCLK is stable meaning the count error DCOS has not changed by more than for two consecutive samples and the DCO clock is not static This bit is used when exiting off state if CLKS X1 to determine when t
18. CLOCK INPUT Figure 8 4 External Clock Connections 8 2 4 External Crystal Resonator Connections If an external crystal resonator frequency reference is used then the pins are connected as shown below Recommended component values are listed in the Electrical Characteristics chapter CRYSTAL OR RESONATOR Figure 8 5 External Frequency Reference Connection 8 3 Register Definition Refer to the direct page register summary in the Memory chapter of this data sheet for the absolute address assignments for all ICG registers This section refers to registers and control bits only by their names A Freescale provided equate or header file is used to translate these names into the appropriate absolute addresses Table 8 1 is a summary of ICG registers 9508 60 Data Sheet Rev 1 0 132 Freescale Semiconductor Internal Clock Generator SO8ICGV4 Table 8 1 ICG Register Summary Name 7 6 5 4 3 0 R 0 ICGC1 W HGO RANGE REFS CLKS OSCSTEN R R CLKST REFST LOLS LOCK LOCS ERCS ICGIF ICGS1 1 0 0 0 0 0 0 0 DCOS ICGS2 ICGFLTU FLT ICGFLTL FLT W ICGTRM TRIM Unimplemented or Reserved 8 3 1 ICG Control Register 1 ICGC1 7 6 5 4 3 2 1 0 W Reset 0 1 0 0 0 1 0 0 Unimplemented or Reserved Figure 8 6 ICG Control Register 1 ICGC1 This bit can be written only once after reset Additional writes are ignored
19. 5 PTESE4 PTESE2 PTESE1 PTESEO PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDSO PTFPE7 6 5 PTFPE4 PTFPES PTFPE2 PTFPE1 PTFPEO PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSEO PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDSO 0 PTGPE6 5 PTGPE4 PTGPE2 PTGPE1 PTGPEO 0 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSEO 0 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDSO This reserved bit must always be written to O Nonvolatile FLASH registers shown in Table 4 4 are located in the FLASH memory These registers include an 8 byte backdoor key which optionally can be used to gain access to secure memory resources During reset events the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high page registers to control security and block protection options Address SFFBO FFB7 FFB8 FFBC FFBD FFBE FFBF Register Name NVBACKKEY Reserved NVPROT Reserved NVOPT Table 4 4 Nonvolatile Register Summary Bit 7 6 5 4 3 2 1 Bit 0 8 Byte Comparison Key FPS7 FPS6 FPS5 54 FPS3 FPS2 FPS1 FPDIS KEYEN FNORED 0 0 0 0 SECO1 SECOO This location can be used to store the factory trim val
20. Figure 6 19 Port C Data Register PTCD Table 6 12 PTCD Register Field Descriptions Field Description 6 0 Port C Data Register Bits For port C pins that are inputs reads return the logic level on the pin For port C PTCD 6 0 pins that are configured as outputs reads return the last value written to this register Writes are latched into all bits of this register For port C pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTCD to all Os but these Os are not driven out the corresponding pins because reset also configures all port pins as high impedance inputs with pullups disabled 7 6 5 4 3 2 1 0 R PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDDO W Reset 0 0 0 0 0 0 0 0 Figure 6 20 Data Direction for Port C PTCDD Table 6 13 PTCDD Register Field Descriptions Field Description 6 0 Data Direction for Port C Bits These read write bits control the direction of port C pins and what is read for PTCDDJ6 0 PTCD reads 0 Input output driver disabled and reads return the pin value 1 Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn MC9S08AW60 Data Sheet Rev 1 0 92 Freescale Semiconductor Chapter 6 Parallel Input Output 6 7 6 Port C Pin Control Registers PTCSE PTCDS In addition to the I O control port C pins are controlled by the registers listed below 7
21. J 10 05 A B Ie 17 45 A 2 16 95 0 2040 2 45 2 40 2 15 2 00 SEATING PLANE Y C 0 25 MAX EE wp 40 80 TITLE CASE NUMBER 8408 01 64LD QFP 14 X 14 STANDARD NON JEDEC PACKAGE CODE 605 SHEET 1 OF 4 WEBER DOCUMENT NO 98ASB42844B freescale DICTIONARY semiconductor PAGE FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED 8408 DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED D N VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED CUPY IN RED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED S C L E T H S D N G V 555 02 0 40 CA CAI Cre lee _ CA N BASE METAI 0 50 m 0 02 V 4 mE 23 ROTATED 90 CLOCKWIS DETAIL A S B B gt DATUM PLANE 0 55 DETAL C TITLE CASE NUMBER 840B 01 64LD QFP 14 X 14 STANDARD NON JEDEC PACKAGE 605 SHEET e UF 4
22. E START CALLING ADDRESS READ ACK DATA BYTE NO STOP SIGNAL WRITE BIT ACK SIGNAL MSB LSB MSB LSB 1 1 1 1 1 SDA AD7 AD6 ADS AD4 AD3 AD2 AD1 R W XX AD7 AD6 ADS AD4 AD3 AD1 RAV lt gt lt gt START CALLING ADDRESS READ ACK REPEATED NEW CALLING ADDRESS READ NO STOP SIGNAL WRITE BIT START WRITE ACK SIGNAL Figure 13 8 IIC Bus Transmission Signals MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 225 Inter Integrated Circuit SO8IICV1 13 4 1 1 START Signal When the bus is free 1 no master device is engaging the bus both SCL and SDA lines are at logical high a master may initiate communication by sending a START signal As shown in Figure 13 8 a START signal is defined as a high to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer may contain several bytes of data and brings all slaves out of their idle states 13 4 1 2 Slave Address Transmission The first byte of data transferred immediately after the START signal is the slave address transmitted by the master This is a seven bit calling address followed by a R W bit The R W bit tells the slave the desired direction of data transfer 1 Read transfer the sl
23. LVD 8 USER FLASH AW60 63 280 BYTES AW48 49 152 BYTES AD1P7 AD1P0 8 AD1P15 AD1P8 ANALOG TO DIGITAL CONVERTER ADC1 PTA7 PTAO PTB7 AD1P7 PTBO AD1PO PTC6 PTC5 RxD2 PTC4 PTC3 TxD2 PTC2 MCLK PTC1 SDA1 PTCO SCL1 gt PTD7 AD1P15 KBI1P7 PTD6 AD1P14 TPM1CLK n PTD5 AD1P13 PTD4 AD1P12 TPM2CLK lt gt PTD3 AD1P11 KBI1P6 PTD2 AD1P10 KBI1P5 AW32 32 768 BYTES AW16 16 384 BYTES SERIAL PERIPHERAL INTERFACE MODULE SPI1 USER RAM AW60 48 32 2048 BYTES AW16 1024 BYTES 6 CHANNEL TIMER PWM MODULE 1 TPMICHS INTERNAL CLOCK TPM1CHO 35 PTD1 AD1P9 4 gt PTDO AD1P8 lt gt PTE7 SPSCK1 lt gt PTE6 MOSI PTES MISO1 PTE4 SST PTES TPM1CH1 lt gt PTE2 TPM1CHO GENERATOR ICG PTE1 RxD1 SERIAL COMMUNICATIONS PTEO TxD1 LOW POWER OSCILLATOR INTERFACE MODULE 5 1 lt PTF7 PTF6 VOLTAGE REGULATOR 2 CHANNEL TIMER PWM MODULE 2 TPM2CH1 TPM2CHO NOTES Port pins are software configurable with pullup device if input port Pin contains software configurable pullup pulldown device if IRQ is enabled IRQPE 1 Pulldown is enabled if rising edge detect is selected IRQEDG 1 IRQ does not have a clamp diode to Vpp IRQ should not be driven above Vpp Pi
24. MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 133 Internal Clock Generator SO8ICGV4 Table 8 2 ICGC1 Register Field Descriptions Field Description 7 High Gain Oscillator Select The HGO bit is used to select between low power operation and high gain HGO operation for improved noise immunity This bit is write once after reset 0 Oscillator configured for low power operation 1 Oscillator configured for high gain operation 6 Frequency Range Select The RANGE bit controls the oscillator reference divider and FLL loop prescaler RANGE multiplication factor P It selects one of two reference frequency ranges for the ICG The RANGE bit is write once after a reset The RANGE bit only has an effect in FLL engaged external and FLL bypassed external modes Oscillator configured for low frequency range FLL loop prescale factor P is 64 1 Oscillator configured for high frequency range FLL loop prescale factor P is 1 5 External Reference Select The REFS bit controls the external reference clock source for ICGERCLK The REFS REFS bit is write once after a reset 0 External clock requested 1 Oscillator using crystal or resonator requested 4 3 Clock Mode Select The CLKS bits control the clock mode as described below If FLL bypassed external is CLKS requested it will not be selected until ERCS 1 If the ICG enters off mode the CLKS bits will remain unchanged Writes to the CLKS bits will not take eff
25. less than the minimum as required by the lock detector to detect the unlock condition The ICG will remain in this state while the count error An is greater than the maximum or less than the minimum as required by the lock detector to detect the lock condition In this state the pulse counter subtractor digital loop filter and DCO form a closed loop and attempt to lock it according to their operational descriptions later in this section Upon entering this state and until the FLL becomes locked the output clock signal ICGOUT frequency is given by 2 This extra divide by two prevents frequency overshoots during the initial locking process from exceeding chip level maximum frequency specifications After the FLL has locked if an unexpected loss of lock causes it to re enter the unlocked state while the ICG remains in FEE mode the output clock signal ICGOUT frequency is given by 8 4 7 2 FLL Engaged External Locked FEE locked is entered from FEE unlocked when the count error An is less than njock max and greater than min for a given number of samples as required by the lock detector to detect the lock condition The output clock signal ICGOUT frequency is given by In FLL engaged external locked the filter value is updated only once every four comparison cycles The update made is an average of the error measurements taken in the four previous co
26. 18 0 3 16 0 3 14 0 3 12 0 3 10 0 3 8 0 3 6 0 3 4 0 3 2 0 3 000 0 3 Figure A 2 Typical High Drive vs at Vpp 3 V MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 285 Appendix A Electrical Characteristics and Timing Specifications Average 7 0 3 6 0 3 5 0 3 4 0 3 3 0 3 2 0 3 1 0 3 000 0 0 00 0 30 Vsuppy Figure A 3 Typical Low Drive vs at Vpp 5 V Average of loy V 30 0 3 25 0 3 20 0 3 15 0 3 10 0 3 5 0 3 000 0E 3 0 30 0 50 0 00 0 80 1 00 1 30 2 00 Figure A 4 Typical High Drive vs at Vpp 5 V MC9S08AW60 Data Sheet Rev 1 0 286 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications A 7 Supply Current Characteristics Table A 8 Supply Current Characteristics Vpp 1 Parameter Symbol V Typ Max Unit C Run supply current measured at 5 9 959 1 P RI mA 40 to 125 C CPU clock 2 MHz fa 1 MHz 0 570 0 770 Run supply current measured at 2 mA 40 to 125 C CPU clock 16 MHz fg 8 MHz 3 3 5 3 70 Stop2 mode supply current 7 5 4
27. 193 11 34 Interr pts and Status PIdES a EEEE 194 ILA Additonal 195 154 1 Data Modes 195 AZ Stop Mode 196 og Eno 196 LIS Single Wite iiio 196 Chapter 12 Serial Peripheral Interface SO8SPIV3 199 200 124 2 Block UIDEMUS EEUU ADI MM MM E EEUU DES 200 I2 L 3 SPI Baud Rate Gener ain 202 12 2 External Signal P eio ris RP 203 21 SPSCK SPI CIOOE 203 12 2 2 MOSI Master Data Out Slave Data nennen 203 12 2 3 MISO Master Data In Slave Data Out eee nennen enne 203 1224 58 Slave Select inscia a RAM td n oV RE o Eten a PIRA 203 euet dud Nec 204 P23 SPI Control Register 1 CSPIDIG D ti desdi ta reso mdi 204 12 3 2 SPI Control Regtster 2 205 12 3 3 JOP Baud Rate R gister 206 SPILS Resister SPILS NN 207 123 3 SPI Data Register Hanae atom Dead 208 12 4 Functional Description MR
28. 9 08 60 9 08 48 MC9S08AW32 MC9S08AW16 Advance Information Data Sheet MC9S08AW60 Rev 1 0 1 2006 freescale com fr eescale semicon ductor MC9S08AW60 48 32 16 Features 8 Bit HCS08 Central Processor Unit CPU e 40 MHz 508 CPU central processor unit e 20 2 internal bus frequency e HCO08 instruction set with added BAND instruction e Single wire background debug mode interface e Breakpoint capability to allow single breakpoint setting during in circuit debugging plus two more breakpoints in on chip debug module e On chip real time in circuit emulation ICE with two comparators plus one in BDM nine trigger modes and on chip bus capture buffer Typically shows approximately 50 instructions before or after the trigger point e Support for up to 32 interrupt reset sources Memory Options e Up to 60 KB of on chip in circuit programmable FLASH memory with block protection and security options Up to 2 KB of on chip RAM Clock Source Options e Clock source options include crystal resonator external clock or internally generated clock with precision NVM trimming System Protection e Optional computer operating properly COP reset e Low voltage detection with reset or interrupt illegal opcode detection with reset e Illegal address detection with reset some devices don t have illegal addresses Power Saving Modes e Wait plus two stops Peripherals e ADC 16 channel
29. N 163 lj jj MM M M 163 ouest 165 External 166 10 3 1 External TPM Clock SOUFGOS 166 10 3 2 TPMxCH IPMx Channel n TO PINS 166 Resister R O ixi 166 10 4 1 Timer x Status and Control Register TPMXSC 167 10 4 2 Timer x Counter Registers TPMxCNTH TPMXxCNTL 168 10 4 3 Timer x Counter Modulo Registers 169 10 4 4 Timer x Channel n Status and Control Register 5 170 1044 5 Timer x Channel Value Registers TPMxCnVH TPMNXCDV L 171 Puticbonor DESCHEDON aestum piov totus mp mE OU 172 IOS A E 172 10 5 2 Channel Mode Selection Laco ce up c uM ARE 173 105 5 Center Alisned PWM Mod 173 TPM Mi ag 176 Pass 176 106 2 Timer Overflow Interrupt DeSCEIDUOR edt 176 Channel Eyent Uis pan 177 10 6 4 PWM End of Duty Cycle Events ii aceite vivesccesattteti e prin reta da En ao RH aun pnl eed Geo 177
30. PRESCALER CLOCK RATE DIVIDER DIVIDE BY DIVIDE BY MASTER 1 2 8 4 5 6 7 8 2 4 8 16 32 64 128 or 256 SPI BIT RATE SPPR2 SPPR1 SPPRO SPR2 SPR1 SPRO Figure 12 5 SPI Baud Rate Generation 12 2 External Signal Description The SPI optionally shares four port pins The function of these pins depends on the settings of SPI control bits When the SPI is disabled SPE 0 these four pins revert to being general purpose port I O pins that are not controlled by the SPI 12 2 1 SPSCK SPI Serial Clock When the SPI is enabled as a slave this pin is the serial clock input When the SPI is enabled as a master this pin is the serial clock output 12 2 2 MOSI Master Data Out Slave Data In When the SPI is enabled as a master and SPI pin control zero SPCO is 0 not bidirectional mode this pin is the serial data output When the SPI is enabled as a slave and SPCO 0 this pin is the serial data input If SPCO 1 to select single wire bidirectional mode and master mode is selected this pin becomes the bidirectional data I O pin MOMI Also the bidirectional mode output enable bit determines whether the pin acts as an input BIDIROE 0 or an output BIDIROE 1 If SPCO 1 and slave mode is selected this pin is not used by the SPI and reverts to being a general purpose port I O pin 12 2 3 MISO Master Data In Slave Data Out When the SPI is enabled as a master and SPI pin
31. When LOOPS 1 the RSRC bit in the same register chooses between loop mode RSRC 0 or single wire mode RSRC 1 Loop mode is sometimes used to check software independent of connections in the external system to help isolate system problems In this mode the transmitter output is internally connected to the receiver input and the RxD1 pin is not used by the SCI so it reverts to a general purpose port I O pin 11 4 4 Single Wire Operation When LOOPS 1 the RSRC bit in the same register chooses between loop mode RSRC 0 or single wire mode RSRC 1 Single wire mode is used to implement a half duplex serial connection The receiver is internally connected to the transmitter output and to the TxD1 pin The RxD1 pin is not used and reverts to a general purpose port I O pin In single wire mode the TXDIR bit in SCIxC3 controls the direction of serial data on the TxD1 pin When TXDIR 0 TxD1 pin is an input to the SCI receiver and the transmitter is temporarily disconnected from TxD1 pin so an external device can send serial data to the receiver When TXDIR 1 the TxD1 pin is an output driven by the transmitter In single wire mode the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter 9508 60 Data Sheet Rev 1 0 196 Freescale Semiconductor 12 Serial Peripheral Interface SOBSPIV3 The 950
32. baud rate baud rate bus speed Hz mul SCL divider SDA hold time is the delay from the falling edge of the SCL IIC clock to the changing of SDA IIC data The ICR is used to determine the SDA hold value SDA hold time bus period s SDA hold value Table 13 3 provides the SCL divider and SDA hold values for corresponding values of the ICR These values can be used to baud rate and SDA hold time For example Bus speed 8 MHz MULT is set to 01 mul 2 Desired baud rate 100 kbps baud rate bus speed Hz mul SCL divider 100000 8000000 2 SCL divider SCL divider 40 Table 13 3 shows that ICR must be set to OB to provide an SCL divider of 40 and that this will result in an SDA hold value of 9 SDA hold time bus period s SDA hold value SDA hold time 1 8000000 9 1 125 us If the generated SDA hold value is not acceptable the MULT bits can be used to change the ICR This will result in a different SDA hold value MC9S08AW60 Data Sheet Rev 1 0 220 Freescale Semiconductor Inter Integrated Circuit SO8IICV1 Table 13 3 IIC Divider and Hold Values ICR zz SDA Hold ICR sid SDA Hold hex SCL Divider Value hex SCL Divider Value 00 20 7 20 160 17 01 22 7 21 192 17 02 24 8 22 224 33 03 26 8 23 256 33 04 28 9 24 288 49 05 30 9 25 320 49 06 34 10 26 384 65
33. 1 Clock supplied from ATE has 500 usec duty period 2 ICG configured for internal reference with 4 MHz bus START TRIM PROCEDURE ICGTRM 80 1 MEASURE INCOMING CLOCK WIDTH COUNT OF BUS CLOCKS 4 COUNT EXPECTED 500 RUNNING TOO SLOW COUNT EXPECTED 500 COUNT EXPECTED 500 RUNNING TOO FAST Y ICGTRM ICGTRM ICGTRM 128 2 n ICGTRM 128 2 n DECREASING ICGTRM INCREASING ICGTRM INCREASES THE FREQUENCY DECREASES THE FREQUENCY STORE ICGTRM VALUE IN NON VOLATILE MEMORY CONTINUE NO Figure 8 17 Trim Procedure In this particular case the MCU has been attached to a PCB and the entire assembly is undergoing final test with automated test equipment A separate signal or message is provided to the MCU operating under user provided software control The MCU initiates a trim procedure as outlined in Figure 8 17 while the tester supplies a precision reference signal If the intended bus frequency is near the maximum allowed for the device it is recommended to trim using a reduction divisor R twice the final value After the trim procedure is complete the reduction divisor can be restored This will prevent accidental overshoot of the maximum clock frequency MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 153 Internal Clock Generator SO8ICGV4 9508 60 Data Sheet Rev 1 0 154 Freescale Semiconductor
34. 1 Internal pullup device enabled for port B bit n 7 6 5 4 3 2 1 0 PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSEO 1 1 1 1 1 1 1 1 Figure 6 17 Output Slew Rate Control Enable PTBSE Table 6 10 PTBSE Register Field Descriptions Field Description 7 0 Output Slew Rate Control Enable for Port B Bits Each of these control bits determine whether output slew PTBSE 7 0 rate control is enabled for the associated PTB pin For port B pins that are configured as inputs these bits have no effect O Output slew rate control disabled for port B bit n 1 Output slew rate control enabled for port B bit n MC9S08AW60 Data Sheet Rev 1 0 90 Freescale Semiconductor Chapter 6 Parallel Input Output PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDSO Reset 0 0 0 0 0 0 0 0 Figure 6 18 Output Drive Strength Selection for Port B PTBDS Table 6 11 PTBDS Register Field Descriptions Field Description 7 0 Output Drive Strength Selection for Port B Bits Each of these control bits selects between low and high PTBDS 7 0 output drive for the associated PTB pin 0 Low output drive enabled for port B bit n 1 High output drive enabled for port B bit n MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 91 Chapter 6 Parallel Input Output 6 7 5 Port C Registers PTCD and PTCDD Port C parallel I O function is controlled by the registers listed below
35. 12 om X m oor PTC2 MCLK MODULE FIT lt PTCO SCL1 IRQ LVD AD1P7 AD1PO 8 8 AD1P15 AD1P8 ANALOG TO DIGITAL CONVERTER ADC1 PTD7 AD1P15 KBI1P7 PTD6 AD1P14 TPM1CLK USER FLASH E m eros prer T on aa A PTD4 AD1P12 TPM2CLK 60 63 280 AW48 49 152 BYTES ERE 5 jt PTD3 AD1P11 KBI1 P6 32 32 768 BYTES lt gt 5 AW16 16 384 BYTES lt gt PT PTDO AD1P8 lt lt gt PTE7 SPSCK1 PTE6 MOSI1 lt gt PTE5 MISO1 lt gt PTEA SS1 SPSCK1 MOSI1 USER RAM SERIAL PERIPHERAL uS AW60 48 32 2048 BYTES INTERFACE MODULE SP11 x AW16 1024 BYTES EX S mimi gt TPM1CLK 5 PTE3 TPM1CH1 6 CHANNEL TIMER PWM MODULE 1 TPM1CH5 5 PTE2 TPM1CHO INTERNAL CLOCK 1 6 E GENERATOR ICG oe lt gt 1 SERIAL COMMUNICATIONS TxD1 gt LOW POWER OSCILLATOR INTERFACE MODULE 1 lt PTF7 lt gt PTF6 Vos TPM2CLK lt gt VOLTAGE 2 CHANNEL TIMER PWM L a gt PTFA TPM2CHO Vsg REGULATOR MODULE TPM2 TPM2CH1 TPM2CH0 T 2 _ 7 5 3 8 BIT KEYBOARD gt INTERRUPT MODULE KBI1 4 5 a PTFO TPMICH2 a PTG6 EXT
36. 8 X oprx 16 SP oprx8 SP Operation Compare X Index Register Low with Memory Description X M CCR Updated But Operands Not Changed Effect on CCR Mode DBNZ opr8a rel DBNZA rel DBNZX rel DBNZ oprx8 X rel DBNZ DBNZ DEC DECA DECX DEC Oprx8 X DEC X SP Decimal Adjust Accumulator After ADD or ADC of BCD Values Decrement and Branch if Not Zero Decrement A 10 Decrement A X or M Branch if result 0 2 Affects X Not H opr 6a Oprx16 X Oprx8 X X oprxi 6 SP Oprx8 SP INC oprx8 X INC X INC oprx8 SP 1 16 8 X 1 16 8 X Divide Exclusive OR Memory with Accumulator Increment Jump to Subroutine M lt 0x01 lt A 0x01 lt X 0x01 lt M 0x01 lt 0x01 M lt M 0x01 PC lt Jump Address PC lt n n 1 2 or 3 Push PCL SP lt SP 0x0001 Push PCH SP lt SP 0x0001 PC lt Unconditional Address 1 oprx16 X 8 X 1 6 SP LDA oprx8 SP opr16i opr16a X 16 8 oprx8 SP Load Accumulator from Memory Load Index Register H X from Memory H X
37. Field Description 7 0 Output Slew Rate Control Enable for Port D Bits Each of these control bits determine whether output slew PTDSE 7 0 rate control is enabled for the associated PTD pin For port D pins that are configured as inputs these bits have no effect 0 Output slew rate control disabled for port D bit n 1 Output slew rate control enabled for port D bit n 9508 60 Data Sheet Rev 1 0 96 Freescale Semiconductor Chapter 6 Parallel Input Output 7 6 5 4 3 2 1 0 R PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDSO W Reset 0 0 0 0 0 0 0 0 Figure 6 28 Output Drive Strength Selection for Port D PTDDS Table 6 21 PTDDS Register Field Descriptions Field Description 7 0 Output Drive Strength Selection for Port D Bits Each of these control bits selects between low and high PTDDS T7 0 output drive for the associated PTD pin 0 Low output drive enabled for port D bit n 1 High output drive enabled for port D bit n MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 97 Chapter 6 Parallel Input Output 6 7 9 Port E Registers PTED and PTEDD Port E parallel I O function is controlled by the registers listed below Figure 6 29 Port E Data Register PTED Table 6 22 PTED Register Field Descriptions Field Description 7 0 Port E Data Register Bits For port E pins that are inputs reads return the logic level on the pin For por
38. READ A Active BDM 68 d RD Read accumulator A READ CCR Active BDM 69 d RD Read condition code register CCR READ PC Active BDM 6B d RD16 Read program counter PC READ HX Active BDM 6C d RD16 Read H and X register pair H X READ SP Active BDM 6F d RD16 Read stack pointer SP READ NEXT Active BDM 70 d RD Increment HX by one then read memory byte located at H X Increment by then read memory byte READ Active BDM located at H X Report status and data WRITE A Active BDM 48 WD d Write accumulator A WRITE CCR Active BDM 49 WD d Write condition code register CCR WRITE PC Active BDM 4B WD16 d Write program counter PC WRITE_HX Active BDM 4C WD16 d Write H and X register pair H X WRITE_SP Active BDM 4F WD16 d Write stack pointer SP WRITE NEXT Active BDM 50 WD d Increment by one then write memory byte located at H X WRITE NEXT WS Active BDM 51 WD d SS Increment H X by one then write memory byte located at H X Also report status The SYNC command is a special operation that does not have a command code MC9S08AW60 Data Sheet Rev 1 0 264 Freescale Semiconductor Chapter 15 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command To issue a SYNC command the host Drives the BKGD pin low for at
39. SBRI SBRO 003A SCIHC1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0038 2 toe RE We TE RE RW SBK 003C SCI1S1 TDRE TC RDRF IDLE OR NF FE PF 00309 SCI1S2 o o o o o 0 003E SCI1C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 003F SCHD B7 5 4 2 1 0040 SCI2BDH 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 0041 SCI2BDL SBR7 6 5 SBR4 SBR3 SBR2 SBRI SBRO 0042 SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0043 SCI2C2 TE TOE RE We TE RE RW SK 0044 SCI2S1 TDRE TC RDRF IDLE OR NF FE PF 0045 5 1252 o o su o RAF 0046 SCI2C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0047 SCI2D Bt7 6 5 4 3 2 1 BtO 0048 ICGC1 HGO RANGE REFS CLKS OSCSTEN LOCD 0 0049 ICGC2 LOLRE MFD LOCE RFD 004A ICGS1 CLKST REFST LOLS LOCK LOCS ERCS ICGIF 004B ICGS2 Dcos 004 ICGFLTU 0 0 0 0 FLT 004D ICGFLTL FLT 004E ICGTRM TRIM 004F Reserved 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor 45 Chapter 4 Memory Table 4 2 Direct Page Register Summary Sheet 3 of 3 Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0050 SPI1C1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0051 SPI1C2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPCO 0052 SPITBR 0 SPPR2 SPPR1 SPPRO 0 SPR2 SPR1 SP
40. This write only bit is used to acknowledge real time interrupt request RTIACK write 1 to clear RTIF Writing 0 has no meaning or effect Reads always return logic 0 5 Real Time Interrupt Clock Select This read write bit selects the clock source for the real time interrupt RTICLKS 0 Real time interrupt request clock source is internal 1 kHz oscillator 1 Real time interrupt request clock source is external clock 4 Real Time Interrupt Enable This read write bit enables real time interrupts RTIE O Real time interrupts disabled 1 Real time interrupts enabled 2 0 Real Time Interrupt Delay Selects These read write bits select the wakeup delay for the RTI The clock RTIS 2 0 source for the real time interrupt is a self clocked source which oscillates at about 1 kHz is independent of other MCU clock sources Using external clock source the delays will be crystal frequency divided by value in RTIS2 RTIS1 RTISO See Table 5 10 Table 5 10 Real Time Interrupt Frequency RTIS2 RTIS1 RTISO 1 kHz Clock Source Delay Using External Glock Source Delay Crystal Frequency 0 0 0 Disable periodic wakeup timer Disable periodic wakeup timer 0 0 1 8 ms divide by 256 0 1 0 32 ms divide by 1024 0 1 1 64 ms divide by 2048 1 0 0 128 ms divide by 4096 1 0 1 256 ms divide by 8192 1 1 0 512 ms divide by 16384 1 1 1 1 024 s divide by 32768 1 Normal values are shown in this column based on faq 1 kHz See Appendix A Electrical Characte
41. for more information about using port E pins as SCI pins Refer to Chapter 12 Serial Peripheral Interface SOSSPIV3 for more information about using port E pins as SPI pins Refer to Chapter 10 SOSTPMV2 for more information about using port E pins as TPM channel pins MC9S08AW60 Data Sheet Rev 1 0 82 Freescale Semiconductor Chapter 6 Parallel Input Output 6 3 6 Port F Port F Bit 7 6 5 4 3 2 1 Bit 0 PTF5 PTF4 PTF3 PTF2 PTFi PTFO TPM2CH1 TPM2CHO 5 4 TPMICH3 TPMICH Figure 6 6 Port F Pin Names MCU Pin 7 PTF6 Port F pins are general purpose I O pins Parallel I O function is controlled by the port F data PTFD and data direction PTFDD registers which are located in page zero register space The pin control registers pullup enable PTFPE slew rate control PTFSE and drive strength select PTFDS are located in the high page registers Refer to Section 6 4 Parallel I O Control for more information about general purpose I O control and Section 6 5 Pin Control for more information about pin control Port general purpose I O is shared with TPM1 and 2 timer channels When any of these shared functions is enabled the direction input or output is controlled by the shared function and not by the data direction register of the parallel I O port Also for pins which are configured as outputs by the shared function the output dat
42. 0 BDM active user application program running 1 BDM active and waiting for serial commands 5 BDC Breakpoint Enable If this bit is clear the BDC breakpoint is disabled and the FTS force tag select control bit and BDCBKPT match register are ignored 0 breakpoint disabled 1 BDC breakpoint enabled 4 Force Tag Select When FTS 1 a breakpoint is requested whenever the CPU address bus matches the FTS BDCBKPT match register When FTS 0 match between the CPU address bus and the BDCBKPT register causes the fetched opcode to be tagged If this tagged opcode ever reaches the end of the instruction queue the CPU enters active background mode rather than executing the tagged opcode O Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that instruction 1 Breakpoint match forces active background mode at next instruction boundary address need not be an opcode 3 Select Source for Communications Clock CLKSW defaults to 0 which selects the alternate CLKSW clock source O Alternate BDC clock source 1 MCU bus clock MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 271 Chapter 15 Development Support Table 15 2 BDCSCR Register Field Descriptions continued Field Description 2 Wait or Stop Status When the target CPU is in wait or stop mode most BDC commands cannot function WS However the BACKGROUND command can
43. 0x0001 2 Push H Index Register High m Stack Push SP SP 0x0001 i Push X Index Register Low onto Stack Push X SP lt SP 0x0001 2 Pull A lator f Ec ve MORILO SP lt SP 0x0001 Pull A 3 Pull H Index Register High ous SP SP 0x0001 Pull Pull X Index Register Low from Stack SP lt SP 0x0001 Pull X 3 ROL opr8a 5 ROLA 1 Rok Rotate Left through Carry H ROL X 4 ROL oprx8 SP 6 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor 121 Chapter 7 Central Processor Unit S08CPUV2 Table 7 2 08 Instruction Set Summary Sheet 6 of 7 Source Form ROR opr8a ROR oprx8 X ROR X ROR oprx8 SP Operation Rotate Right through Carry Reset Stack Pointer Return from Interrupt Description SP lt OxFF High Byte Not Affected SP lt SP 0x0001 Pull CCR SP SP 0 0001 Pull A SP lt SP 0x0001 Pull X SP lt SP 0x0001 Pull PCH SP SP 0x0001 Pull PCL Effect on CCR Opcode Operand 16 Oprx8 X X oprx16 SP SBC oprx8 SP Return from Subroutine Subtract with Carry Set Carry Bit SP lt SP 0x0001 Pull PCH SP lt SP 0x0001 Pull PCL Set Interrupt Mask Bit opr 6a oprx16 X oprx8 X X 16 5 STA oprx8 SP Store Accumulator
44. 10 bit analog to digital converter with automatic compare function e Two serial communications interface modules with optional 13 bit break e SPI Serial peripheral interface module e Inter integrated circuit bus module to operate at up to 100 kbps with maximum bus loading capable of higher baudrates with reduced loading e Timers One 2 channel and one 6 channel 16 bit timer pulse width modulator TPM module Selectable input capture output compare and edge aligned PWM capability on each channel Each timer module may be configured for buffered centered PWM CPWM on all channels e 8 pin keyboard interrupt module Input Output Up to 54 general purpose input output I O pins e Software selectable pullups on ports when used as inputs e Software selectable slew rate control on ports when used as outputs e Software selectable drive strength on ports when used as outputs e Master reset pin and power on reset POR e Internal pullup on RESET IRQ and BKGD MS pins to reduce customer system cost Package Options MC9S08AW60 48 32 e 64 pin quad flat package QFP e 64 pin low profile quad flat package LQFP e 48 pin low profile quad flat package QFN e 44 pin low profile quad flat package LQFP MC9S08AW16 e 48 pin low profile quad flat package QFN e 44 low profile quad flat package LQFP 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor MC9S08AW
45. 2 REL 2 DIR 3 EXT 2 2 X1 1 X 04 5 14 5 24 34 44 1 54 1 64 5 74 4 84 1 94 4 4 4 4 4 4 3 4 3 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR TAP TXS AND AND AND AND AND AND 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 1 1 1 1 1 2 2 DIR 3 EXT 2 2 X1 1 X 05 5115 5 25 3 35 4 45 3 55 4 65 3 75 85 1 195 2 2 5 3 5 4 05 4 5 3 F5 3 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT 3 DIR 2 DIR 2 REL 2 DIR 3 IMM 2 DIR 3 2 DIR 1 NH 1 INH 2 MM 2 DIR 3 EXT 3 2 2 X1 1 x 06 5 16 5 26 36 46 1 66 5 76 86 96 5 2 6 C6 6 4 6 3 6 3 ROR RORA RORX ROR ROR PULA STHX LDA LDA LDA LDA LDA LDA 3 DIR 2 DIR 2 REL 2 DIR 1 NH 1 NH 2 X1 1 X 1 3 EXT MM 2 DIR 3 EXT 3 X2 2 X1 1 X 07 5 17 5 27 3 37 5 47 1 57 1 67 5 77 4 87 2 97 1 7 2 7 3 4 07 4 7 3 2 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR PSHA TAX AIS STA STA STA STA STA 3 DIR 2 DIR 2 REL 2 DIR 1 NH 1 NH 2 X1 1 1 1 2 2 DIR 3 EXT 3 2 2 X1 1 x 08 5 18 5 28 3 38 48 1 58 1 68 5 78 4 88 98 1 8 C8 8 4 3 F8 3 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR 3 DIR 2 DIR 2 REL 2 DIR 1 NH 1 NH 2 X1 1 X 1 NH 1 INH MM 2 DIR 3 EXT 3 2 2 X1 1 X 09 5 19 5 29 3 39 5 49 1 59 1 169 5 79 4 89 2 99 1 A9 2 9 3 9 4 09 4
46. 508 2 TPM1CHO PTE1 PTEO RxD1 TxD1 Chapter 11 Serial Communications Interface SO8SCIV2 5 4 2 1 Chapter 10 Timer PWM 508 2 TPM2CHO TPM1CH5 Chapter 10 Timer PWM 508 2 TPM1CH2 PTG4 PTGO KBl1P4 KBl1PO Chapter 9 Keyboard Interrupt SO8KBIV1 PTG6 PTG5 EXTAL XTAL Chapter 8 Internal Clock Generator SO8ICGV4 See the listed chapter for information about modules that share these pins MC9S08AW60 Data Sheet Rev 1 0 30 Freescale Semiconductor Chapter 2 Pins and Connections When an on chip peripheral system is controlling a pin data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin s output buffer See the Chapter 6 Parallel Input Output chapter for more details Pullup enable bits for each input pin control whether on chip pullup devices are enabled whenever the pin is acting as an input even if it is being controlled by an on chip peripheral module When the PTD7 PTD3 PTD2 and 4 pins are controlled by the KBI module and are configured for rising edge high level sensitivity the pullup enable control bits enable pulldown devices rather than pullup devices NOTE When an alternative function is first enabled it is possible to get a spurious edge to the module user software should clear out
47. 5V 3V Output low current Max total for all ports 5V 3V Max Unit Input high voltage all digital inputs 0 65 Input low voltage all digital inputs 10 35 x v mV 0741 0 Input hysteresis all digital inputs 0 06 x Vpp Input leakage current input only pins 0 01 9 High Impedance off state leakage current Internal pullup resistors v Low voltage detection threshold high range Vpp falling Vpp rising Low voltage detection threshold low range Vpp falling Vpp rising Low voltage warning threshold high range Vpp falling Vpp rising Low voltage warning threshold low range Vpp falling Vpp rising Low voltage inhibit reset recover hysteresis 3V Measured with Vi Vpp or Vas Measured with Vi Vss Measured with Vi A OO N MC9S08AW60 Data Sheet Rev 1 0 Typical values are based on characterization data at 25 C unless otherwise stated 284 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications V Average of lop 6 0 3 5 0 3 4 0 3 3 0E 3 2 0 3 1 0 3 000 0 0 0 3 0 5 0 8 0 9 1 2 1 5 Vsuppy VoH Figure A 1 Typical Low Drive vs at Vpp 3 V Average of lop V 20 0 3
48. FFD6 FFD7 Vsci2rx SCI2 IDLE ILIE SCI2 receive RDRF RIE 19 FFD8 FFD9 Vsci2err SCI2 OR ORIE SCI2 error NF NFIE FE FEIE PF PFIE 18 FFDA FFDB Vsciltx 5 TDRE TIE transmit TC TCIE 17 FFDC FFDD Vscil rx SCI1 IDLE ILIE RDRF RIE 16 FFDE FFDF Vscilerr 5 OR ORIE SCI1 error NF NFIE FE FEIE PF PFIE 15 FFEO FFE1 SPIF SPIE MODF SPIE SPTEF SPTIE 14 FFE2 FFE3 Vtpm2ovf TPM2 TOF TOIE 13 FFEA FFES Vtpm2ch1 TPM2 CH1F CH1IE 2 channel 1 12 FFE6 FFE7 Vtpm2chO TPM2 CHOF CHOIE 2 channel 0 11 FFE8 FFE9 Vtpm1ovf 1 TOIE 1 overflow 10 FFEA FFEB Vtpm1ch5 1 CH5F 1 5 9 FFEC FFED Vtpm1ch4 TPM1 CH4F CHAIE 1 channel 4 8 FFEE FFEF Vtpm1ch3 1 CHSIE TPM1 channel 3 7 FFFO FFF1 Vtpmich2 TPM1 CH2F 1 channel 2 6 FFF2 FFF3 Vtpm1ch1 1 CH1F CH1IE 5 FFF4 FFF5 Vtpm1chO 1 CHOF CHOIE 4 FFF6 FFF7 Vicg ICG ICGIF LOLRE LOCRE LOLS LOCS 3 FFF8 FFF9 Vivd System LVDF LVDIE control 2 FFFA FFFB IRQIE 1 FFFC FFFD Vswi Core SWI ES Software interrupt Instruction Y 0 FFFE FFFF Vreset System COP COPE Watchdog timer control LVD LVDRE Low voltage detect Higher RESET pin External pin Illegal opcode 9508 60 Data Sheet Rev 1 0 68 Freescale Semiconductor Chapter 5 Resets Interrupts and System Configuration 5 6 Low Voltage Detect LVD Sy
49. Important configuration information is repeated here for reference Table 8 12 ICGOUT Frequency Calculation Options Clock Scheme P Note SCM self clocked mode FLL bypassed NA Typical ficgout 8 MHz internal immediately after reset FBE FLL bypassed external fext R NA FLL engaged internal fina 7 64 N R 64 Typical 243 kHz FEE FLL engaged external P N R Range 0 P 64 Range 1 P 1 1 Ensure that which is equal to ficsour does not exceed ficapci kmax Table 8 13 MFD and RFD Decode Table MFD Value Multiplication Factor N RFD Division Factor R 000 4 000 x1 001 6 001 2 010 8 010 4 011 10 011 8 100 12 100 16 9508 60 Data Sheet Rev 1 0 146 Freescale Semiconductor Internal Clock Generator SO8ICGV4 Table 8 13 MFD and RFD Decode Table 101 14 101 32 8 5 2 Example 1 External Crystal 32 kHz Bus Frequency 4 19 MHz In this example the FLL will be used in FEE mode to multiply the external 32 kHz oscillator up to 8 38 to achieve 4 19 MHz bus frequency After the MCU is released from reset the ICG is in self clocked mode SCM and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency fp The clock scheme will be FLL engaged external FEE So ficcour P N R 264 fext 32 kHz Eqn 8 1 Solving for N R gives 8 38 MHz 32 kH
50. MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 13 Chapter 11 Serial Communications Interface 5085 2 S d Reus 179 PEAKE S mete A 181 IVI SOT Operation pea otia tuta 181 BOCE 182 11 2 Register Der IOI ida 184 11 2 1 SCI Baud Rate Registers SCIxBDH SCIXBHL rein etes tne 184 11 2 2 SCI Control Register 1 SCRC D 185 11 23 SCL Control Register 186 N24 OC statis Register 1 90 1 aste nsns ihe 187 SCI Situs Resister 2 189 11 20 SCi Conmol Register 3 5C Deo hd ask qoM SA 189 112 7 SCI Data Register SOIR adiac eda 190 LES F nctonal Description 2 dio indo De 191 11 3 1 Baud R te UH MUR MAU 191 13 2 Description 191 Receiver Functional Description ausa noodles
51. TPM interrupt flags are cleared by a 2 step process that includes a read of the flag bit while it is set 1 followed by a write of 0 to the bit If a new event is detected between these two steps the sequence is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new event 10 6 2 Timer Overflow Interrupt Description The conditions that cause TOF to become set depend on the counting mode up or up down In up counting mode the 16 bit timer counter counts from 0x0000 through and overflows to 0x0000 on the next counting clock TOF becomes set at the transition from OxFFFF to 0x0000 When a modulus limit is set TOF becomes set at the transition from the value set in the modulus register to 0 0000 When the counter is operating in up down counting mode the TOF flag gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value This corresponds to the end of a PWM period The 0x0000 count value corresponds to the center of a period 9508 60 Data Sheet Rev 1 0 176 Freescale Semiconductor Timer Pulse Width Modulator 508 2 10 6 3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel input capture output compare edge aligned PWM or center aligned PWM When a channel is configured as an input capture channel the ELSnB ELSnA
52. The A comparator is always associated with the 16 bit CPU address The B comparator compares to the CPU address or the 8 bit CPU data bus depending on the trigger mode selected Because the CPU data bus is separated into a read data bus and a write data bus the RWAEN and RWA control bits have an additional purpose in full address plus data comparisons they are used to decide which of these buses to use in the comparator B data bus comparisons If RWAEN 1 enabled and RWA 0 write the CPU s write data bus is used Otherwise the CPU s read data bus 1s used The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match condition A match can cause Generation of a breakpoint to the CPU e Storage of data bus values into the FIFO e Starting to store change of flow addresses into the FIFO begin type trace Stopping the storage of change of flow addresses into the FIFO end type trace 15 3 2 Bus Capture Information and FIFO Operation The usual way to use the FIFO is to setup the trigger mode and other control options then arm the debugger When the FIFO has filled or the debugger has stopped storing data into the FIFO you would read the information out of it in the order it was stored into the FIFO Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it If a trace run is manually halted by writing 0 to ARM before the FIFO
53. control bit in the IRQSC register must be 1 in order for the IRQ pin to act as the interrupt request IRQ input As an IRQ input the user can choose the polarity of edges or levels detected IRQEDG whether the pin detects edges only or edges and levels and whether event causes an interrupt or only sets the IRQF flag which can be polled by software When the IRQ pin is configured to detect rising edges an optional pulldown resistor is available rather than a pullup resistor BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act as the IRQ input MC9S08AW60 Data Sheet Rev 1 0 66 Freescale Semiconductor Chapter 5 Resets Interrupts and System Configuration NOTE The voltage measured on the pulled up IRQ pin may be as low as 0 7 V The internal gates connected to this pin are pulled all the way to Vpp All other pins with enabled pullup resistors will have an unloaded measurement of Vpp 5 5 2 2 gt Edge and Level Sensitivity The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels In this edge detection mode the IRQF status flag becomes set when an edge is detected when the IRQ pin changes from the deasserted to the asserted level but the flag is continuously set and cannot be cleared as long as the IRQ pin remains at the asserted level 5 5 3 Interrupt Vectors Sources and Local Masks Table 5 1 provi
54. gt C INH 57 1 ASR oprx8 X Arithmetic Shift Right m 67 ff 5 ASR IX 77 4 ASR oprx8 SP SP1 9E67 ff 6 BCC rel Branch if Carry Bit Clear Branch if C 0 24 3 MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 117 Chapter 7 Central Processor Unit S08CPUV2 Table 7 2 08 Instruction Set Summary Sheet 2 of 7 Source Form BCLR n opr8a Operation Clear Bit n in Memory Description Effect on CCR V H IIN Z Opcode Branch if Carry Bit Set Same as BLO Branch if Greater Than or Equal To Signed Operands Branch if C 1 Branch if Z 1 Branch if N V Enter Active Background if 1 Waits For and Processes BDM Commands Until GO TRACE1 or TAGGO Branch if Greater Than Signed Operands Branch if Z N V Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if H 0 Branch if H 1 Branch if Higher Branch if C Z Branch if Higher or Same Same as BCC BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low Branch if IRQ pin OpIX 16 5 oprx8 SP Branch if C Branch if IRQ pin 1 A amp M CCR Updated but Operands Not Changed BLE rel Branch if Less Than or Equal To Signed Operands Branch if Lower Same as BCS Branch if Z N 6 V 1 Branch if C 1 Branch if Lower o
55. 07 40 10 27 480 65 08 28 7 28 320 33 09 32 7 29 384 33 36 9 2A 448 65 OB 40 9 2B 512 65 44 11 2 576 97 00 48 11 20 640 97 56 13 2 768 129 68 13 2 960 129 10 48 9 30 640 65 11 56 9 31 768 65 12 64 13 32 896 129 13 72 13 33 1024 129 14 80 17 34 1152 193 15 88 17 35 1280 193 16 104 21 36 1536 257 17 128 21 37 1920 257 18 80 9 38 1280 129 19 96 9 39 1536 129 112 17 1792 257 1 128 17 2048 257 1C 144 25 3C 2304 385 1D 160 25 3D 2560 385 1E 192 33 3E 3072 513 1F 240 33 3F 3840 513 MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 221 Inter Integrated Circuit SO8IICV1 13 3 3 IIC Control Register IIC1C 7 6 R IICIE Reset 0 0 Unimplemented or Reserved Figure 13 5 IIC Control Register IIC1C Table 13 4 IIC1C Register Field Descriptions Field Description 7 Enable The bit determines whether the module is enabled 0 is not enabled 1 is enabled 6 Interrupt Enable The bit determines whether an interrupt is requested IICIE 0 interrupt request not enabled 1 interrupt request enabled 5 Master Mode Select The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus MST and master mode is selected When this bit changes from a 1 to a 0 a STOP signal is generated and the mode of operation changes from ma
56. 1 0 24 Freescale Semiconductor PTFO TPM1CH2 PTF1 TPM1CH3 Chapter 2 Pins and Connections 47 PTC3 TxD2 46 PTC2 MCLK 45 PTC1 SDA1 42 PTG6 EXTAL PTGS XTAL 37 PTG4 KB1IP4 PTGS KBH P3 O 48 PTC5 RxD2 IRQ PTD3 KBI1P6 AD1P11 RESET PTD2 KBI1P5 AD1P10 Vssap PTFA TPM2CHO 48 Pin QFN PTD1 AD1P9 PTF5 TPM2CH1 PTEO TxD1 PTE1 RxD1 PTE2 TPM1CHO PTES TPM1CH1 PTDO AD1P8 PTF6 PTB3 AD1P3 PTB2 AD1P2 PTB1 AD1P1 PTBO AD1PO PTA7 PTE4 SS1 PTES MISO1 PTE6 MOSI1 PTE7 SPSCK1 PTGO KBH PO 19 PTG1 KBHP1 20 PTG2 KBH P2 21 Figure 2 2 MC9808AW60 48 32 16 in 48 QFN Package MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 25 Chapter 2 Pins and Connections 2 3 PTC5 RxD2 PTC3 TxD2 PTC2 MCLK PTC1 SDA1 PTCO SCL1 PTG6 EXTAL PTG5 XTAL BKGD MS Vss VREFL PTC4 IRa 2 RESET PTFO TPM1CH2 4 PTFI TPMICH3 5 PTF4 TPM2CHO 6 2 7 PTEO TxD1 PTE1 RxD1 PTE2 TPM1CHO PTES TPM1CH1 2 44 Pin LQFP PTE4 SS1 PTES MISO1 PTE6 MOSI1 PTE7 SPSCK1 PTGO KBI1PO PTG1 KBI1P1 PTG2 KBI1P2 m i gt 34 PTG3 KBI1P3 PTD3 KBI1P6 AD1P11 PTD2 KBI1P5 AD1P10 Vssap Vppap PTD1 AD1P9 PTDO AD1P8 PTB3 AD1P3 PTB2 AD1P2 PTB1 AD1P1 PTBO AD1PO Figure 2 3 MC9SO8AW60 48 32 16 in 44 Pin LQFP Package Recommended System Connections Figure 2 4 shows pin connections that are common to
57. 1 2 GND NO CONNECT 3 4 RESET NO CONNECT 5 6 Vpp Figure 15 1 BDM Tool Connector 15 2 1 BKGD Pin Description BKGD is single wire background debug interface pin The primary function of this pin is for bidirectional serial communication of active background mode commands and data During reset this pin is used to select between starting in active background mode or starting the user s application program This pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers This protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate All communication is initiated and controlled by the host that drives a high to low edge to signal the beginning of each bit time Commands and data are sent most significant bit MC9S08AW60 Data Sheet Rev 1 0 258 Freescale Semiconductor Chapter 15 Development Support first MSB first For a detailed description of the communications protocol refer to Section 15 2 2 Communication Details If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication
58. 186 Freescale Semiconductor Serial Communications Interface SO8SCIV3 Table 11 4 5 2 Register Field Descriptions continued Field Description 2 Receiver Enable When the SCI receiver is off the RxD pin reverts to being a general purpose port I O pin RE 0 Receiver off 1 Receiver on 1 Receiver Wakeup Control This bit can be written to 1 to place the SCI receiver in a standby state where it RWU waits for automatic hardware detection of a selected wakeup condition The wakeup condition is either an idle line between messages WAKE 0 idle line wakeup or a logic 1 in the most significant data bit in a character WAKE 1 address mark wakeup Application software sets RWU and normally a selected hardware condition automatically clears RWU Refer to Section 11 3 3 2 Receiver Wakeup Operation for more details 0 Normal SCI receiver operation 1 receiver in standby waiting for wakeup condition 0 Send Break Writing a 1 and then a 0 to SBK queues break character in the transmit data stream Additional SBK break characters of 10 or 11 bit times of logic 0 are queued as long as SBK 1 Depending on the timing of the set and clear of SBK relative to the information currently being transmitted a second break character may be queued before software clears SBK Refer to Section 11 3 2 1 Send Break and Queued Idle for more details 0 Normal transmitter operation 1 Queue break character s to be
59. 1M 16 MHz 1 MO Series resistor Low range Low Gain HGO 0 0 High Gain 1 100 High range Low Gain 0 Rs 0 idm High Gain 1 28MHz 0 4 MHz 10 1 MHz 20 Typical values are based on characterization data at Vpp 5 0V 25 C or is typical recommended value See crystal or resonator manufacturer s recommendation MC9S08AW60 Data Sheet Rev 1 0 292 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications 9 1 ICG Frequency Specifications Table A 12 ICG Frequency Specifications Vppa min to max Temperature Range 40 to 125 C Ambient Oscillator crystal or resonator REFS 1 Fundamental mode crystal or ceramic ee Low range 32 100 kHz 1 I High range High Gain FBE lt 1 CLKS lt 10 1 16 MHz High Gain FEE lt 1 CLKS lt 11 2 10 MHz Low Power 0 CLKS 10 1 8 MHz Low Power FEE 0 CLKS 11 2 8 MHz Input clock frequency CLKS 11 REFS 0 2 T Low range 32 100 kHz High range i 2 10 MHz 3 Input clock frequency CLKS 10 REFS 0 MHz 4 P Internal reference frequency untrimmed Bux 182 25 303 75 kHz 5 P Duty cycle of input clock REFS 0 96 Output clock ICGOUT frequency CLKS 10 REFS 0 max 6 fi T min x All other cases t tmin ficabCcLKmax MHz d ma
60. 4 3 2 1 0 SBR12 SBR11 SBR10 SBR9 SBR8 w ES Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 11 4 SCI Baud Rate Register SCIXBDH Table 11 1 SCIXBDH Register Field Descriptions Field Description 4 0 Baud Rate Modulo Divisor These 13 bits are referred to collectively as BR and they set the modulo divide SBR 12 8 rate for the SCI baud rate generator When BR 0 the SCI baud rate generator is disabled to reduce supply current When BR 1 to 8191 the SCI baud rate BUSCLK 16xBR See also BR bits in Table 11 2 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBRO 0 0 0 0 0 1 0 0 Figure 11 5 SCI Baud Rate Register SCIxBDL 9508 60 Data Sheet Rev 1 0 184 Freescale Semiconductor Serial Communications Interface SO8SCIV3 Table 11 2 SCIxBDL Register Field Descriptions Field Description 7 0 Baud Rate Modulo Divisor These 13 bits are referred to collectively as BR and they set the modulo divide SBR 7 0 rate for the SCI baud rate generator When BR 0 the SCI baud rate generator is disabled to reduce supply current When BR 1 to 8191 the SCI baud rate BUSCLK 16xBR See also BR bits in Table 11 1 11 2 2 SCI Control Register 1 SCIxC1 This read write register is used to control various optional features of the SCI system 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Figure 11 6 SCI Control Register 1 SCIxC1 Table 11 3 SCIxC1 Register Field Descriptio
61. 4 Memory 4 4 1 Features Features of the FLASH memory include FLASH Size 9508 60 63280 bytes 124 pages of 512 bytes each MCO9S08AWAS8 49152 bytes 96 pages of 512 bytes each MC9S08AW32 32768 bytes 64 pages of 512 bytes each e Single power supply program and erase Command interface for fast program and erase operation e Upto 100 000 progranverase cycles at typical voltage and temperature e Flexible block protection e Security feature for FLASH and RAM e Auto power down for low frequency read accesses 4 4 2 Program and Erase Times Before any program or erase command can be accepted the FLASH clock divider register FCDIV must be written to set the internal clock for the FLASH module to a frequency fpc between 150 kHz and 200 kHz see Section 4 6 1 FLASH Clock Divider Register FCDIV This register can be written only once so normally this write is done during reset initialization FCDIV cannot be written if the access error flag FACCERR in FSTAT is set The user must ensure that FACCERR is not set before writing to the FCDIV register One period of the resulting clock 1 is used by the command processor to time program and erase pulses An integer number of these timing pulses are used by the command processor to complete a program or erase command Table 4 5 shows program and erase times The bus clock frequency and FCDIV determine the frequency of FCLK fpc The
62. 5 2 0 SPI Baud Rate Divisor This 3 bit field selects one of eight divisors for the SPI baud rate divider as shown in SPR 2 0 Table 12 6 The inputto this divider comes from the SPI baud rate prescaler see Figure 12 5 The output of this divider is the SPI bit rate clock for master mode Table 12 5 SPI Baud Rate Prescaler Divisor SPPR2 SPPR1 SPPRO 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Prescaler Divisor CO NI OD oa 9508 60 Data Sheet Rev 1 0 206 Freescale Semiconductor Serial Peripheral Interface 5085 Table 12 6 SPI Baud Rate Divisor SPR2 SPR1 SPRO Rate Divisor 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 12 3 4 SPI Status Register SPI1S This register has three read only status bits Bits 6 3 2 1 and 0 are not implemented and always read 0 Writes no meaning or effect 7 6 5 4 3 2 1 0 R SPRF 0 SPTEF MODF 0 0 0 0 Ww Reset 0 0 1 0 0 0 0 0 Unimplemented or Reserved Figure 12 9 SPI Status Register SPI1S Table 12 7 SPI1S Register Field Descriptions Field Description 7 SPI Read Buffer Full Flag SPRF is set at the completion of an SPI transfer to indicate that received data SPRF be read from the SPI data register SPI1D SPRF is cleared by reading SPRF while it is set then reading the SPI data register O No data availab
63. 6 5 4 3 2 1 0 6 5 4 2 PTCPE1 PTCPEO 0 0 0 0 0 0 0 0 Figure 6 21 Internal Pullup Enable for Port C Table 6 14 PTCPE Register Field Descriptions Field Description 6 0 Internal Pullup Enable for Port C Bits Each of these control bits determines if the internal pullup device is PTCPE 6 0 enabled for the associated PTC pin For port C pins that are configured as outputs these bits have no effect and the internal pullup devices are disabled O Internal pullup device disabled for port C bit n 1 Internal pullup device enabled for port C bit n 7 6 5 4 3 2 1 0 R PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSEO W Reset 0 1 1 1 1 1 1 1 Figure 6 22 Output Slew Rate Control Enable for Port C PTCSE Table 6 15 PTCSE Register Field Descriptions Field Description 6 0 Output Slew Rate Control Enable for Port C Bits Each of these control bits determine whether output slew PTCSE 6 0 rate control is enabled for the associated PTC pin For port pins that are configured as inputs these bits have no effect O Output slew rate control disabled for port C bit n 1 Output slew rate control enabled for port C bit n MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 93 Chapter 6 Parallel Input Output 7 6 5 4 3 2 1 0 R PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDSO Ww Reset 0 0 0 0 0 0 0 0 Figu
64. 7 6 5 4 3 2 1 Bit 0 PTD7 6 PTD4 _ PTD3 2 MCUPin ADIPis apiptay 1 1 Apri AD1P13 AD1P9 AD1P8 KBHP7 TPM2CLK 1 6 KBH P5 Figure 6 4 Port D Pin Names Port D pins are general purpose I O pins Parallel I O function is controlled by the port D data PTDD and data direction PTDDD registers which are located in page zero register space The pin control registers 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor 81 Chapter 6 Parallel Input Output pullup enable PTDPE slew rate control PTDSE and drive strength select PTDDS are located in the high page registers Refer to Section 6 4 Parallel I O Control for more information about general purpose I O control and Section 6 5 Pin Control for more information about pin control Port D general purpose I O are shared with the ADC KBI and TPM1 and TPM2 external clock inputs When any of these shared functions is enabled the direction input or output is controlled by the shared function and not by the data direction register of the parallel I O port When a pin is shared with both the ADC and a digital peripheral function the ADC has higher priority For example in the case that both the ADC and the KBI are configured to use PTD7 then the pin is controlled by the ADC module Refer to Chapter 10 SOSTPMV2 for more information about using port D pins as TPM external
65. 8 Input Clock Select ADICLK Selected Clock Source 00 Bus clock 01 Bus clock divided by 2 10 Alternate clock ALTCLK 11 Asynchronous clock ADACK 14 4 8 Pin Control 1 Register APCTL1 The pin control registers are used to disable the I O port control of MCU pins used as analog inputs is used to control the pins associated with channels 0 7 of the ADC module 7 6 5 4 3 2 1 0 ADPC7 ADPC6 ADPC5 ADPCA ADPC3 ADPC2 ADPC1 ADPCO Reset 0 0 0 0 0 0 0 0 Figure 14 11 Pin Control 1 Register APCTL1 Table 14 9 APCTL1 Register Field Descriptions Field Description 7 ADC Pin Control 7 is used to control the pin associated with channel AD7 ADPC7 0 AD7 control enabled 1 ADT pin control disabled 6 ADC Pin Control 6 ADPC6 is used to control the pin associated with channel AD6 ADPC6 0 AD6 pin control enabled 1 AD6 pin control disabled 5 ADC Pin Control 5 ADPC5 is used to control the pin associated with channel 5 ADPC5 0 AD5 control enabled 1 AD5 pin control disabled 4 ADC Pin Control 4 ADPCA is used to control the pin associated with channel 4 ADPC4 0 AD4 pin control enabled 1 AD4 control disabled 3 ADC Pin Control 3 is used to control the pin associated with channel 0 AD3 pin control enabled 1 pin I O control disabled 2 ADC Pin
66. 9 3 9 3 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC 3 DIR 2 DIR 2 REL 2 DIR 1 NH 1 NH 2 X1 1 X 1 2 2 DIR 3 EXT 3 2 2 X1 1 x 0A 5 1A 5 2A 3A 4 1 5 1 6 5 7 4 8 9A 1 BA CA 4 DA 4 FA 3 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA 3 DIR 2 DIR 2 REL 2 DIR 1 NH 1 NH 2 X1 1 X 1 NH 1 INH 2 MM 2 DIR 3 EXT 3 2 2 X1 1 X 5 5 2 3 3B 7 5 4 6 7 6 9 1 3 4 DB 4 3 3 BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD 3 DIR 2 DIR 2 REL 3 DIR 2 INH 2 NH 3 X1 2 1 1 INH 2 2 DIR 3 EXT 2 2 X1 1 x 5 1C 5 2 3C 4C 1 5 1 6 5 7 4 8 1 9 1 C 4 EC 3 FC 3 BRSET6 BSET6 BMC INC INCA INCX INC INC CLRH RSP JMP JMP JMP JMP JMP 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 NH 2 X1 1 X 1 NH 1 INH 2 DIR 3 EXT 3 2 2 X1 1 X 00 5 1D 5 2D 3 30 4140 1 5 1160 4 70 3 9D 1 AD BD 5 6 00 6 ED 5 FD 5 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR SR JSR JSR JSR JSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 NH 2 X1 1 x 1 INH 2 REL 2 DIR 3 EXT 2 2 X1 1 x 0 5 1 5 2 3 6 4 5 5 5 6 4 7 5 8 2 9 2 3 4 0 4 3 FE 3 BRSET7 BSET7 BIL CPHX MOV MOV MOV MOV STOP Page2 LDX LDX LDX LDX LDX LDX 3 DIR 2 DIR 2 REL 3 EXT 3 DD 2 3 IMD 2 1 IN
67. ADC operation the MCU s voltage regulator must remain active during stop3 mode Consult the module introduction for configuration information for this MCU If a conversion is in progress when the MCU enters stop3 mode it continues until completion Conversions can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled AIEN 1 NOTE It is possible for the ADC module to wake the system from low power stop and cause the MCU to begin consuming run level currents without generating a system level interrupt To prevent this scenario software should ensure that the data transfer blocking mechanism discussed in Section 14 5 4 2 Completing Conversions is cleared when entering stop3 and continuing ADC conversions 14 5 8 Stop1 and Stop2 Mode Operation The ADC module is automatically disabled when the MCU enters either stopl or stop2 mode All module registers contain their reset values following exit from stopl or stop2 Therefore the module must be re enabled and re configured following exit from stopl or stop2 14 6 Initialization Information This section gives an example which provides some basic direction on how a user would initialize and configure the ADC module The user has the flexibility of choosing between configuring the
68. BYTES AW32 32 768 BYTES AW16 16 384 BYTES USER RAM AW60 48 32 2048 BYTES AW16 1024 BYTES INTERNAL CLOCK GENERATOR ICG LOW POWER OSCILLATOR VOLTAGE REGULATOR NOTES CONVERTER ADC1 SERIAL PERIPHERAL INTERFACE MODULE SPI1 6 CHANNEL TIMER PWM MODULE TPM1 TPM1CH5 1 4 gt PTD7 AD1P15 KBI1P7 lt gt PTD6 AD1P14 TPM1CLK 4 35 5 1 1 lt gt PTD2 AD1P10 KBI1P5 lt gt PTD1 AD1P9 lt PTDO AD1P8 lt gt PTE7 SPSCK1 lt gt PTE6 MOSI1 PTES MISO1 PTE4 SST PTES TPM1CH1 PTE2 TPM1CHO PTE1 RxD1 SERIAL COMMUNICATIONS INTERFACE MODULE SCI1 2 CHANNEL TIMER PWM MODULE TPM2 8 BIT KEYBOARD INTERRUPT MODULE TPM2CH1 TPM2CHO 7 5 4 lt lt EXTAL Port pins are software configurable with pullup device if input port Pin contains integrated pullup device Pin contains software configurable pullup pulldown device if IRQ is enabled IRQPE 1 Pulldown is enabled if rising edge detect is selected IRQEDG 1 IRQ does not have a clamp diode to Vpp IRQ should not be driven above Vpp PTEO TxD1 PTF7 PTF6 PTFS TPM2CH1 PTFA TPM2CHO PTF3 TPM1CH5 PTF2 TPM1CH4 PTF1 TPM1CH3 PTFO TPM1CH2 F n PTG6 EXTAL PTG5 XTAL lt gt PTGA KBH P
69. FU 98ASB42844B 9508 60 Data Sheet Rev 1 0 Freescale Semiconductor 305 MECHANICAL OUTLINES DOCUMENT 98ASS2e322e5W FREESCALE SEMICONDUCTOR semiconductor RESERVED i i i a 2 m cu SCALE THIS DRAWING RE C NIIS L MIN 4X 11 TIPS 0 2 T L MIN 44 34 i i zo i me PC 1 a 12 00 EW Y 5 00 BSC 6 00 i BSC i5 3 PE 22 500 BSC 6 00 BSC 10 00 BSC 1200 BSC 4X REF 1 60 a SNO H e N 0 1 T na SEATING J X Ne i PLANE x 4 12 REP
70. HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS PTC6 MODES OF OPERATION gt PTCS RXD2 a aa SERIAL COMMUNICATIONS ay IRQ INTERFACE MODULE SCI2 PTC3 TxD2 E PTC2 MCLK MODULE PISA PTCO SCL1 IRQ LVD 10 BIT ANALOG TO DIGITAL CONVERTER ADC1 PTD7 AD1P15 KBI1P7 lt PTDG ADIPIA TPMICLK lt lt 5 1 13 254 USER FLASH A gt PTDA AD1P12 TPM2CLK 4 PTD3 AD1P11 KBI1PG BYTES RM A gt PTb2ADIPIOKBIPS AW16 16 384 BYTES lt 4 gt PTD1 AD1P9 9 PTDO ADIPS T USER RAM SERIAL PERIPHERAL 60 lt gt AW60 48 32 2048 BYTES INTERFACE MODULE SPI1 SET P 5 01 4 gt 551 AW16 1024 BYTES PTES TPM1CH1 5 lt gt PTE2 TPM1CHO TPM1CLK TPM1CH5 TPM1CHO RxD1 SERIAL COMMUNICATIONS TxD1 INTERFACE MODULE SCI1 6 CHANNEL TIMER PWM INTERNAL CLOCK MODULE 1 GENERATOR ICG gt PTE1 RxD1 3 PTEO TxD1 LOW POWER OSCILLATOR a gt PTF7 lt gt PTF6 TPM2CLK lt gt PTFS TPM2CH1 lt gt PTFAITPM2CHO VOLTAGE REGULATOR 2 CHANNEL TIMER PWM MODULE TPM2 TPM2CH1 TPM2CHO 2 PORT PTF3 TPM1CH5 gt 2 4 F PTF1 TPM1CH3 5 PTFO TPM1CH2 1P7 KBHP5 8 BIT KEYBOAR
71. I O control enabled 1 AD16 pin I O control disabled 14 5 Functional Description The ADC module is disabled during reset or when the ADCH bits are all high The module is idle when a conversion has completed and another conversion has not been initiated When idle the module is in its lowest power state The ADC can perform an analog to digital conversion on any of the software selectable channels The selected channel voltage is converted by a successive approximation algorithm into an 11 bit digital result In 8 bit mode the selected channel voltage is converted by a successive approximation algorithm into a 9 bit digital result When the conversion is completed the result is placed in the data registers ADCIRH and ADCIRL In 10 bit mode the result is rounded to 10 bits and placed in ADCIRH and ADCIRL In 8 bit mode the result is rounded to 8 bits and placed in ADCIRL The conversion complete flag COCO is then set and an interrupt is generated if the conversion complete interrupt has been enabled AIEN 1 The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers The compare function is enabled by setting the ACFE bit and operates in conjunction with any of the conversion modes and configurations 14 5 1 Clock Select and Divide Control One of four clock sources can be selected as the clock source for the ADC module This clock source is then divid
72. POstutes cansino ext SUR RU E E R E 257 15 2 Background Debus Controller BDC 258 15241 BKGD Pin De sera 258 15 2 2 Comm nication Details sui 259 523 BDC COMMANAS mcm 263 BDC Hardware Breakpoint 265 15 3 Debiie System DBG Y E UNE EERENS EET 266 12 51 Comparators Aand B Louise ioa ipte temdi nbn tul dE pa UA 266 15 3 2 Bus Capture Information and FIFO Operation 266 15 3 3 267 15 34 Tag vs Force Breakporate and 267 Treger Modes Rm 268 1530 425 epi eei 270 154 270 154 1 BDC Revisters and C ntrol Bits 270 15 4 2 System Background Debug Force Reset Register 272 1544 DBG Registers and Control Bits 213 MC9S08AW60 Data Sheet Rev 1 0 16 Freescale Semiconductor Electrical Characteristics and Timing Specifications Ad Introduction E 279 wu cu SNL ici URP 279 A
73. Please see the ICG registers 3 6 5 On Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode system clocks to the internal peripheral modules are stopped Even in the exception case ENBDM 1 where clocks to the background debug logic continue to operate clocks to the peripheral systems are halted to reduce power consumption Refer to Section 3 6 1 Stop2 Mode and Section 3 6 2 Stop3 for specific information on system behavior in stop modes Table 3 4 Stop Mode Behavior Mode Peripheral Stop2 Stop3 CPU Off Standby RAM Standby Standby FLASH Off Standby Parallel Port Registers Off Standby ADC1 Off Optionally Optionally On Standby MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 37 Chapter 3 Modes of Operation Table 3 4 Stop Mode Behavior continued Mode Peripheral Stop2 Stop3 Off Optionally On Optionally 4 Optionally 4 Off Standby Off Standby TPM Off Standby Standby Standby States Held States Held Requires the asynchronous ADC clock and LVD to be enabled else in standby 2 OSCSTEN set in ICSC1 else in standby For high frequency range RANGE in ICSC2 set requires the LVD to also be enabled in stop3 During stop3 KBI pins that are enabled continue to function as interrupt sources that are capable of waking the MCU from stop3 This RTI can be enabled to run in stop2 or stop
74. Reset 0 0 Unimplemented or Reserved Figure 8 8 ICG Status Register 1 ICGS1 Table 8 4 ICGS1 Register Field Descriptions Field Description 7 6 Clock Mode Status CLKST bits indicate the current clock mode The CLKST bits don t update CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains 00 Self clocked 01 FLL engaged internal reference 10 FLL bypassed external reference 11 FLL engaged external reference 5 Reference Clock Status The REFST bit indicates which clock reference is currently selected by the REFST Reference Select circuit O External Clock selected 1 Crystal Resonator selected 4 FLL Loss of Lock Status The LOLS bit is a sticky indication of FLL lock status LOLS O FLL has not unexpectedly lost lock since LOLS was last cleared 1 FLL has unexpectedly lost lock since LOLS was last cleared LOLRE determines action taken FLL has unexpectedly lost lock since LOLS was last cleared LOLRE determines action taken 3 FLL Lock Status The LOCK bit indicates whether the FLL has acquired lock The LOCK bit is cleared in off LOCK self clocked and FLL bypassed modes 0 FLL is currently unlocked 1 FLLis currently locked 2 Loss Of Clock Status The LOCS bit is an indication of ICG loss of clock status LOCS 0 ICG has not lost clock since LOCS was last cleared 1 ICG has lost clock since LOCS was last cleared LOCRE determines action taken
75. Reset not caused by ICG module 1 Reset caused by ICG module 1 Low Voltage Detect If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage LVD an LVD reset will occur This bit is also set by POR 0 Reset not caused by LVD trip or POR 1 Reset caused by LVD trip or POR 5 9 3 System Background Debug Force Reset Register SBDFR This register contains a single write only control bit A serial background command such as WRITE_BYTE must be used to write to SBDFR Attempts to write this register from a user program are ignored Reads always return 00 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved 1 is writable only through serial background debug commands not from user programs Figure 5 4 System Background Debug Force Reset Register SBDFR Table 5 4 SBDFR Register Field Descriptions Field Description 0 Background Debug Force Reset A serial background command such as WRITE BYTE may be used to BDFR allow an external debug host to force a target system reset Writing logic 1 to this bit forces an MCU reset This bit cannot be written from a user program 5 9 4 System Options Register This register may be read at any time Bits 3 and 2 are unimplemented and always read 0 This is a write once register so only the first write after reset is honored Any subsequent attempt to wri
76. SPI device When the SPI shift register is available this byte of data is moved from the transmit data buffer to the shifter SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired and the SPI serial transfer starts MC9S08AW60 Data Sheet Rev 1 0 208 Freescale Semiconductor Serial Peripheral Interface SO8SPIV3 During the SPI transfer data is sampled read on the MISO pin at one SPSCK edge and shifted changing the bit value on the MOSI pin one half SPSCK cycle later After eight SPSCK cycles the data that was in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data were shifted in the MISO pin into the master s shift register At the end of this transfer the received data byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read by reading SPIID If another byte of data is waiting in the transmit buffer at the end of a transfer it is moved into shifter SPTEF 15 set and a new transfer is started Normally SPI data is transferred most significant bit MSB first If the least significant bit first enable LSBFE bit is set SPI data is shifted LSB first When the SPI is configured as a slave its SS pin must be driven low before a transfer starts and SS must stay low throughout the transfer If a clock format where CPHA 0 is selected SS must be driven to a logic 1 between success
77. TPM1CLK PTD7 AD1P15 KBI1P7 PTEO TxD1 PTE1 RxD1 PTE2 TPM1CHO PTES TPM1CH1 PTE4 SS1 01 PTE6 MOSI1 PTE7 SPSCK1 Freescale Semiconductor 27 Chapter 2 Pins and Connections 2 31 Power Vpp 2 X Vss Vssap Vpp and are the primary power supply pins for the MCU This voltage source supplies power to all I O buffer circuitry and to an internal voltage regulator The internal voltage regulator provides regulated lower voltage source to the CPU and other internal circuitry of the MCU Typically application systems have two separate capacitors across the power pins In this case there should be a bulk electrolytic capacitor such as a 10 uF tantalum capacitor to provide bulk charge storage for the overall system and a 0 1 uF ceramic bypass capacitor located as near to the paired Vpp and Vss power pins as practical to suppress high frequency noise MC9SO8AW60 has a second pin This pin should be connected to the system ground plane or to the primary Vss pin through a low impedance connection Vppap and VssAp are the analog power supply pins for MCU This voltage source supplies power to the ADC module A 0 1 ceramic bypass capacitor should be located as near to the analog power pins as practical to suppress high frequency noise 2 3 2 Oscillator XTAL EXTAL Out of reset the MCU uses an internally generated clock self clocked mode reset equivalent to about 8 MHz
78. Table 4 14 Table 4 14 FLASH Commands Blank check Byte program 20 mByteProg Byte program burst mode 25 mBurstProg Page erase 512 bytes page 40 mPageErase Mass erase all FLASH 41 mMassErase other command codes are illegal and generate an access error It is not necessary to perform a blank check command after a mass erase operation Only blank check is required as part of the security unlocking mechanism MC9S08AW60 Data Sheet Rev 1 0 62 Freescale Semiconductor Chapter 5 Resets Interrupts and System Configuration 5 1 Introduction This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the 9508 60 48 32 16 Some interrupt sources from peripheral modules are discussed in greater detail within other chapters of this data manual This chapter gathers basic information about all reset and interrupt sources in one place for easy reference A few reset and interrupt sources including the computer operating properly COP watchdog and real time interrupt are not part of on chip peripheral systems with their own sections but are part of the system control logic 5 2 Features Reset and interrupt features include Multiple sources of reset for flexible system configuration and reliable operation Power on detection POR Low voltage detection LVD with enable External RESET pin COP watchdog with enabl
79. UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED VERSIONS DO NOT SCALE THIS DRAWING REV ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED COPY IN RED NOTES 1 DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME 14 5 1994 5 THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE 15 COPLANARITY APPLIES TO LEADS CORNER LEADS AND DIE ATTACH PAD 5 MIN METAL SHOULD BE 0 2 freescale MECHANICAL OUTLINES DOCUMENT NO 98ASS23234W FREESCALE SEMICONDUCTOR RESERVED L id PAGE amp 8AOF VERSIONS ARE EXCEPT HEN DO SCALE THIS DRAWING REV D 0 1 H A B D 4X 16 0 2 0 PIN 1 64 ds VIEW lt 0 IDEEN
80. Writes to the ICGFLTU register will not affect FLT if a previous latch sequence is not complete The filter registers show the filter value FLT 8 3 6 ICG Trim Register ICGTRM 7 6 5 4 3 2 1 0 R TRIM 1 0 0 0 0 0 0 0 Reset U U U U U U U U U Unaffected by MCU reset Figure 8 12 ICG Trim Register ICGTRM Table 8 8 ICGTRM Register Field Descriptions Field Description 7 ICG Trim Setting The TRIM bits control the internal reference generator frequency They allow 25 TRIM adjustment of the nominal POR period The bit s effect on period is binary weighted i e bit 1 will adjust twice as much as changing bit O Increasing the binary value in TRIM will increase the period and decreasing the value will decrease the period 8 4 Functional Description This section provides a functional description of each of the five operating modes of the ICG Also discussed are the loss of clock and loss of lock errors and requirements for entry into each mode The ICG is very flexible and in some configurations it is possible to exceed certain clock specifications When using the FLL configure ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation MC9S08AW60 Data Sheet Rev 1 0 138 Freescale Semiconductor Internal Clock Generator SO8ICGV4 8 4 1 Mode Normally when CPU enters stop mode the ICG will cease all clock activ
81. a hardware interrupt request to the CPU KBIE 1 0 No KBI interrupt pending 1 KBl interrupt pending 2 Keyboard Interrupt Acknowledge This write only bit reads always return O is used to clear the KBF status KBACK flag by writing a 1 to KBACK When KBIMOD 1 to select edge and level operation and any enabled port pin remains at the asserted level KBF is being continuously set so writing 1 to KBACK does not clear the KBF flag 1 Keyboard Interrupt Enable This read write control bit determines whether hardware interrupts are generated KBIE when the KBF status flag equals 1 When KBIE 0 no hardware interrupts are generated but KBF can still be used for software polling 0 KBF does not generate hardware interrupts use polling 1 KBI hardware interrupt requested when KBF 1 KBIMOD Keyboard Detection Mode This read write control bit selects either edge only detection or edge and level detection KBI port bits 3 through 0 can detect falling edges only or falling edges and low levels KBI port bits 7 through 4 can be configured to detect either Rising edges only or rising edges and high levels KBEDGn 1 Falling edges only or falling edges and low levels 0 O Edge only detection 1 Edge and level detection MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 159 Keyboard Interrupt SO8KBIV1 9 4 2 KBI Pin Enable Register KBI1PE 7 6 5 4 3 2 1 0 KBIP
82. active low input the pullup associated with the IRQ pin is not automatically enabled Therefore if an external pullup is not used the internal pullup must be enabled by setting IRQPE in IRQSC Upon wake up from stop2 mode the MCU will start up as from a power on reset POR except pin states remain latched The CPU will take the reset vector The system and all peripherals will be in their default reset states and must be initialized MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 35 Chapter 3 Modes of Operation After waking up from stop2 the PPDF bit in SPMSC2 is set This flag may be used to direct user code to to a stop2 recovery routine PPDF remains set and the I O pin states remain latched until a logic 1 is written to PDACK in SPMSC2 To maintain I O state for pins that were configured as general purpose I O the user must restore the contents of the I O port registers which have been saved in RAM to the port registers before writing to the PPDACK bit If the port registers are not restored from RAM before writing to PPDACK then the register bits will assume their reset states when the I O pin latches are opened and the I O pins will switch to their reset states For pins that were configured as peripheral I O the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit If the peripheral module is not enabled before writing to PPDACK the pins will be controlled
83. amplitude mode as selected by HGO Internal reference generator The internal reference generator consists of two controlled clock sources One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU This provides a highly reliable low cost clock source e Frequency locked loop A frequency locked loop FLL stage takes either the internal or external clock source and multiplies it to a higher frequency Status bits provide information when the circuit has achieved lock and when it falls out of lock Additionally this block can monitor the external reference clock and signals whether the clock is valid or not MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 129 Internal Clock Generator SO8ICGV4 e Clock select block The clock select block provides several switch options for connecting different clock sources to the system clock tree ICGDCLK is the multiplied clock frequency out of the FLL ICGERCLK is the reference clock frequency from the crystal or external clock source and FFE fixed frequency enable is a control signal used to control the system fixed frequency clock XCLK ICGLCLK is the clock source for the background debug controller 8 1 1 Features The module is intended to be very
84. an error indicating that the MCU is in either stop or wait mode The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set After entering background debug mode all background commands are available Table 3 2 summarizes the behavior of the MCU in stop when entry into the background debug mode is enabled MC9S08AW60 Data Sheet Rev 1 0 36 Freescale Semiconductor Chapter 3 Modes of Operation Table 3 2 BDM Enabled Stop Mode Behavior CPU Digital Mode PPDC Peripherals RAM ICG ADC1 Regulator Pins RTI FLASH Stop3 0 Standby Standby Active Optionally on Active States Optionally on held 3 6 4 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage If the LVD is enabled in stop by setting the LVDE and LVDSE bits then the voltage regulator remains active during stop mode If the user attempts to enter stop2 with the LVD enabled for stop the MCU will instead enter stop3 Table 3 3 summarizes the behavior of the MCU in stop when the LVD is enabled Table 3 3 LVD Enabled Stop Mode Behavior CPU Digital Mode PPDC Peripherals RAM ICG ADC1 Regulator Pins RTI FLASH Stop3 0 Standby Standby off Optionally on Active States Optionally on held 1 Crystal oscillator can be configured to run stop3
85. an input in single wire mode 1 TxD pin is an output in single wire mode 4 Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output TXINV 0 Transmit data not inverted 1 Transmit data inverted 3 Overrun Interrupt Enable This bit enables the overrun flag OR to generate hardware interrupt requests ORIE 0 OR interrupts disabled use polling 1 Hardware interrupt requested when OR 1 2 Noise Error Interrupt Enable This bit enables the noise flag NF to generate hardware interrupt requests NEIE 0 NF interrupts disabled use polling 1 Hardware interrupt requested when NF 1 1 Framing Error Interrupt Enable This bit enables the framing error flag FE to generate hardware interrupt FEIE requests 0 FE interrupts disabled use polling 1 Hardware interrupt requested when FE 1 0 Parity Error Interrupt Enable This bit enables the parity error flag PF to generate hardware interrupt PEIE requests 0 PF interrupts disabled use polling 1 Hardware interrupt requested when PF 1 1 Setting TXINV inverts the TxD output for all cases data bits start and stop bits break and idle 11 2 7 SCI Data Register SCIxD This register is actually two separate registers Reads return the contents of the read only receive data buffer and writes go to the write only transmit data buffer Reads and writes of this register are also involved in the automatic flag clearing mechanisms fo
86. and Control 2 Register SPMSC2 Table 5 12 SPMSC2 Register Field Descriptions Field Description 7 Low Voltage Warning Flag The LVWF bit indicates the low voltage warning status LVWF 0 Low voltage warning not present 1 Low voltage warning is present or was present 6 Low Voltage Warning Acknowledge The LVWACK bit is the low voltage warning acknowledge LVWACK Writing a 1 to LYWACK clears LVWF to a 0 low voltage warning is not present 5 Low Voltage Detect Voltage Select The LVDV bit selects the trip point voltage LVDV Low trip point selected lt 1 High trip point selected Vi yp Vi ypij 4 Low Voltage Warning Voltage Select The LVWV bit selects the LVW trip point voltage V yw LVWV 0 Low trip point selected Vi yw Vi yw 1 High trip point selected Vi yw Vi yw 3 Partial Power Down Flag The bit indicates that the MCU has exited the stop2 mode PPDF 0 Not stop2 mode recovery 1 Stop2 mode recovery 2 Partial Power Down Acknowledge Writing a 1 to PPDACK clears the PPDF bit PPDACK 0 Partial Power Down Control The write once PPDC bit controls whether stop2 or stop3 mode is selected PPDC 0 Stop3 mode enabled 1 Stop2 partial power down mode enabled MC9S08AW60 Data Sheet Rev 1 0 78 Freescale Semiconductor Chapter 6 Parallel Input Output 6 1 Introduction This chapter explains software controls rela
87. and width The width is defined as the delta between the transition points to one code and the next The ideal code width for an N bit converter in this case N can be 8 or 10 defined as ILSB is 1LSB VREFH VnerL 2 14 1 There is an inherent quantization error due to the digitization of result For 8 bit or 10 bit conversions the code will transition when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function Therefore the quantization error will be 1 2LSB in 8 10 bit mode As a consequence however the code width of the first 000 conversion is only 1 2LSB and the code width of the last SFF or 3FF is 1 5LSB 14 7 2 5 Linearity Errors The ADC may also exhibit non linearity of several forms Every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy These errors are Zero scale error Ezg sometimes called offset This error is defined as the difference between the actual code width of the first conversion and the ideal code width 1 2LSB Note if the first conversion is 001 then the difference between the actual 001 code width and its ideal 1LSB is used Full scale error Egg This error is defined as the difference between the actual code width of the last conversion and the ideal code width 1 5LSB Note if the last conver
88. are compared to the upper two bits of the result following a conversion in 10 bit mode when the compare function is enabled In 8 bit operation ADCICVH is not used during compare 7 6 5 4 3 2 1 0 ADCV9 ADCV8 6 0 0 0 0 0 0 0 Reset 0 Unimplemented or Reserved Figure 14 8 Compare Value High Register ADC1CVH 14 4 6 Compare Value Low Register ADC1CVL This register holds the lower 8 bits of the 10 bit compare value or all 8 bits of the 8 bit compare value Bits ADCV7 ADCVO are compared to the lower 8 bits of the result following a conversion in either 10 bit or 8 bit mode 7 6 5 4 3 2 1 0 R ADCV7 ADCV6 ADCV5 ADCVA ADCV3 ADCV2 ADCV1 ADCVO Reset 0 0 0 0 0 0 0 0 Figure 14 9 Compare Value Low Register ADC1CVL 14 4 Configuration Register ADC1CFG is used to select the mode of operation clock source clock divide and configure for low power or long sample time MC9S08AW60 Data Sheet Rev 1 0 240 Freescale Semiconductor Analog to Digital Converter SO8ADC10V1 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK Reset 0 0 0 0 0 0 0 0 Figure 14 10 Configuration Register ADC1CFG Table 14 5 ADC1CFG Register Field Descriptions Field Description 7 Low Power Configuration ADLPC controls the speed and power configuration of the successive ADLPC approximation converter This is used to optimize power consumption when high
89. are not used and each always reads as 0 This register may be read at any time but user program writes have no meaning or effect Background debug commands can write to FPROT R 7 6 5 4 3 2 1 0 Reset This register is loaded from nonvolatile location NVPROT during reset Ww d Background commands be used to change the contents of these bits in FPROT Figure 4 9 FLASH Protection Register FPROT Table 4 11 FPROT Register Field Descriptions Field Description 7 1 FLASH Protect Select Bits When FPDIS 0 this 7 bit field determines the ending address of unprotected FPS 7 1 FLASH locations at the high address end of the FLASH Protected FLASH locations cannot be erased or programmed 0 FLASH Protection Disable FPDIS 0 FLASH block specified by FPS 7 1 is block protected program and erase not allowed 1 No FLASH block is protected 4 6 5 FLASH Status Register FSTAT Bits 3 1 and 0 always read 0 and writes have no meaning or effect The remaining five bits are status bits that can be read at any time Writes to these bits have special meanings that are discussed in the bit descriptions 7 6 5 4 3 2 1 0 0 FBLANK 0 0 FCBEF FPVIOL FACCERR 1 1 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 10 FLASH Status Register FSTAT MC9S08AW60 Data Sheet Rev 1 0 60 Freescale Semiconductor Chapter 4 Memory Table 4 12 FSTAT Register Field Des
90. attempting to lock The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference 8 2 External Signal Description The oscillator pins are used to provide an external clock source for the MCU 8 2 1 EXTAL External Reference Clock Oscillator Input If upon the first write to ICGC1 either the FEE mode or FBE mode is selected this pin functions as either the external clock input or the input of the oscillator circuit as determined by REFS If upon the first write to ICGCI either the FEI mode or SCM mode is selected this pin is not used by the ICG 8 2 2 Oscillator Output If upon the first write to ICGC1 either the FEE mode mode is selected this pin functions as the output of the oscillator circuit If upon the first write to ICGCI either the FEI mode or SCM mode is selected this pin is not used by the ICG The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity This mode of operation is selected by 1 8 2 3 External Clock Connections If an external clock is used then the pins are connected as shown Figure 8 4 MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 131 Internal Clock Generator SO8ICGV4 ICG EXTAL Wag XTAL 12
91. background mode Features of the ICE system include Two trigger comparators Two address read write R W or one full address data R W Flexible 8 word by 16 bit FIFO first in first out buffer for capture information Change of flow addresses Event only data Two types of breakpoints breakpoints for instruction opcodes Force breakpoints for any address access Nine trigger modes Basic A only AOR B Sequence A then B Full A AND B data A AND NOT B data Event store data Event only B A then event only B Range Inside range A lt address lt B outside range address lt A or address gt MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 257 Chapter 15 Development Support 15 2 Background Debug Controller BDC MCUs in the 08 Family contain a single wire background debug interface that supports in circuit programming of on chip nonvolatile memory and sophisticated non intrusive debug capabilities Unlike debug interfaces on earlier 8 bit MCUS this system does not interfere with normal application resources It does not use any user memory or locations in the memory map and does not share any on chip peripherals BDC commands are divided into two groups e Active background mode commands require that the target MCU is in active background mode the user program is not running Active background mode commands allow the CPU registers to b
92. be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work Whenever the host forces the target MCU into active background mode the host should issue a READ STATUS command to check that BDMACT 1 before attempting other BDC commands O Target CPU is running user application code or in active background mode was not in wait or stop mode when background became active 1 Target CPU is in wait or stop mode or a BACKGROUND command was used to change from wait or stop to active background mode 1 Wait or Stop Failure Status This status bit is set if a memory access command failed due to the target CPU WSF executing a wait or stop instruction at or about the same time The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode repeat the command that failed then return to the user program Typically the host would restore CPU registers and stack values and re execute the wait or stop instruction 0 Memory access did not conflict with a wait or stop instruction 1 Memory access command failed because the CPU entered wait or stop mode 0 Data Valid Failure Status This status bit is not used in the MC9SO8AW60 48 32 16 because it does not have DVF any slow access memory 0 Memory access did not conflict with a slow memory access 1 Memory access command failed because CPU was not finished with a slow memory access 1
93. bit 15 set the duty cycle will be 096 If TPMxCnVH TPMXxCnVL is a positive value bit 15 clear and is greater than the nonzero modulus setting the duty cycle will be 100 because the duty cycle compare will never occur This implies the usable range of periods set by the modulus register is 0x0001 through Ox7FFE Ox7FFF if generation of 10046 duty cycle is not necessary This is not a significant limitation because the resulting period is much longer than required for normal applications TPMxMODH TPMxMODL 0x0000 is a special case that should not be used with center aligned PWM mode When CPWMS 0 this case corresponds to the counter running free from 0x0000 through OxFFFF but when CPWMS the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up counting to down counting Figure 10 12 shows the output compare value in the TPM channel registers multiplied by 2 which determines the pulse width duty cycle of the CPWM signal If ELSnA 0 the compare match while counting up forces the CPWM output signal low and a compare match while counting down forces the output high The counter counts up until it reaches the modulo setting in TPMxMODH TPMxMODL then counts down until it reaches zero This sets the period equal to two times TPMxMODH TPMxMODL COUNT 0 OUTPUT UTPUT TPMxMODH TPMx COUNT DOWN COUNT UP TPMxMODH TPMx Y Y 1 Y Y PULSEWIDTH __ 2
94. bus 4 000 05 3 500 05 lt 3 000 05 8 2 500 05 lt 2 000 05 o 2 1 500 05 1 000E 05 CPU SEN ENIM D QN 0 000 00 4 5 5 1 8 2 2 5 3 3 5 Vpp V Figure A 6 Typical Stop 2 Ipp 4 MC9S08AW60 Data Sheet Rev 1 0 288 Freescale Semiconductor Appendix A Electrical Characteristics and Timing Specifications Stop3 Ipp A Average of Meas lpp 50 0E 6 45 0E 6 40 0E 6 35 0 6 ES 30 0E 6 25 0E 6 20 0E 6 15 0E 6 10 0E 6 5 0 6 000 0E 0 A 1 8 2 2 5 3 3 5 4 4 5 5 Vpp V Figure A 7 Typical Stop3 A 8 ADC Characteristics Table A 9 5 Volt 10 bit ADC Operating Conditions Supply voltage Delta to Vpp Ground voltage Delta to Vss Vas Vssap Ref voltage high Ref voltage low Input voltage Input capacitance Input resistance Analog source resistance 10 bit mode External to MCU fapck gt 4MHz fapck lt 4MHz 8 bit mode all valid fADCK ADC conversion clock frequency High speed ADLPC 0 Low power ADLPC 1 Typical values assume Vppap 5 0 V Temp 25 1 0MHz unless otherwise stated Typical values are for reference only and are not tested in production gc potential difference MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 28
95. byte of the address Because of this the lower byte of the address in column one is shown in bold text In Table 4 3 and Table 4 4 the whole address in column one is shown in bold In Table 4 2 Table 4 3 and Table 4 4 the register names in column two are shown in bold to set them apart from the bit names to the right Cells that are not associated with named bits are shaded A shaded cell with 0 indicates this unused bit always reads as a 0 Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or Os MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 43 Chapter 4 Memory Table 4 2 Direct Page Register Summary Sheet 1 of 3 Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0000 PTAD PTAD7 PTAD6 4 PTAD2 PTAD1 PTADO 0001 PTADD PTADD7 PTADD6 PTADDS PTADD4 PTADD3 PTADD2 PTADD1 PTADDO 0002 PTBD PTBD7 PTBD6 5 4 PTBD2 PTBD1 PTBDO 0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDDO 0004 PTCD 0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCDO 0005 PTCDD 0 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDDO 0006 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDDO 0007 PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDDO 0008 PTED PTED7 PTED6 5 4 2 PTED1 P
96. control bits select rising edges falling edges any edge or no edge off as the edge that triggers an input capture event When the selected edge is detected the interrupt flag is set The flag is cleared by the 2 step sequence described in Section 10 6 1 Clearing Timer Interrupt Flags When a channel is configured as an output compare channel the interrupt flag is set each time the main timer counter matches the 16 bit value in the channel value register The flag is cleared by the 2 step sequence described in Section 10 6 1 Clearing Timer Interrupt Flags 10 6 4 PWM End of Duty Cycle Events For channels that are configured for PWM operation there are two possibilities When the channel is configured for edge aligned PWM the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period When the channel is configured for center aligned PWM the timer count matches the channel value register twice during each PWM cycle In this CPWM case the channel flag is set at the start and at the end of the active duty cycle which are the times when the timer counter matches the channel value register The flag is cleared by the 2 step sequence described in Section 10 6 1 Clearing Timer Interrupt Flags MC9S08AW60 Data Sheet Rev 1 0 Freescale Semiconductor 177 Timer Pulse Width Modulator 508 2 9508 60 Data Sheet Rev 1 0 178 Fre