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CIRRUS LOGIC - CS7401xx Energy Measurement SoC handbook

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1. gt mu _ CS7401xx 7 PACKAGE INFORMATION 64L LQFP PACKAGE DRAWING a E gt E1 gt HBERBSHHERBEHBBH A A DO LE D DI EX ELI Lr LE co O m Y 1 Y iL gt pa gt lt e B 1 KU DI x Al L INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A 0 55 0 063 1 40 1 60 A1 0 002 0 004 0 006 0 05 0 10 0 15 B 0 007 0 008 0 011 0 17 0 20 0 27 D 0 461 0 472 BSC 0 484 11 70 12 0 BSC 12 30 D1 0 390 0 393 BSC 0 398 9 90 10 0 BSC 10 10 E 0 461 0 472 BSC 0 484 11 70 12 0 BSC 12 30 E1 0 390 0 393 BSC 0 398 9 90 10 0 BSC 10 10 e 0 016 0 020 BSC 0 024 0 40 0 50 BSC 0 60 L 0 018 0 024 0 030 0 45 0 60 0 75 oc 0 000 4 7 000 0 00 4 7 00 Nominal pin pitch is 0 50 mm Controlling dimension is mm JEDEC Designation MS026 DS728PP3 39 j CIRRUS LOGIC 8 ORDERING INFORMATION CS7401xx CS740131 IQZ 128 kB Flash Model Package Temperature CS740111 IQZ 32 kB Flash CS740121 IQZ 64 kB Flash 64 pin LOFP 40 to 85 C 9 ENVIRONMENTAL MANUFAC
2. 35 Figure 20 Typical Connection Diagram 38 Foure riveli ey ee eae renale 38 LIST OF TABLES Table 1 CS7401xx Pin Functions 6 Table 2 GPIO Pin Multiplexing 8 Table 3 Typical Brownout and POR Threshold Voltages 18 Table 4 Channel PGA Configuration 19 Table 5 Power Modes 21 Table 6 Memory Types and SIZES 25 Table 7 ModesofOperation 33 DS728PP3 3 _e O A A gt CIRRUS LOGIC CS7401xx 1 HARDWARE DESCRIPTION The CS7401xx is part of a family of energy measurement system on a chip SoC products that provides the ability to implement Metrol ogy Register and Communication MRC functions all in the same device Building on our high quality line of Delta Sigma A2 ana log to digital converters ADCs Cirrus Logic has added a very powerful but economical 32 bit processing sub system along with a targeted set of peripherals to provide a very powerful yet cost effective energy measurement solution The CS740111 CS740121 CS740131 are identical except for the amount of flash memory which i
3. Parameter Symbol Min Typ Max Unit Temperature Channel Temperature Accuracy Note 5 T 5 C Power Supplies Supply Current Active Mode VH 3 3 V Note 6 Note 7 Note 8 MCLK 256 kHz DCLK 4 096 MHz 5 MCLK 512 kHz DCLK 4 096 MHz 6 MCLK 256 kHz DCLK 32 768 MHz i 16 ii MCLK 512 kHz DCLK 32 768 MHz 17 Supply Current Standby Mode VH 2 7 V Note 6 Note 7 Note 8 Internal OSC OFF DCLK 2 048 kHz 24 Internal OSC OFF DCLK 32 kHz ix 27 ES Supply Current Sleep Mode VH 2 7 V Note 6 Note 7 Note 8 Internal OSC OFF DCLK Off Crystal OSC ON PC 23 HA Supply Current OFF Mode VH 2 7 V Note 7 Note 7 Note 8 Internal OSC OFF Crystal OSC OFF PC 16 HA Power Supply Rejection Ratio 50 Hz 60 Hz Note 9 PSRR 85 dB Notes After temperature sensor calibration MCLK is sourced by the on chip oscillator DCLK is the CPU clock All outputs unloaded All inputs CMOS level All gains 1 34x Definition for PSRR VH 3 3 V a 150 mV peak to peak 60 Hz sinewave is imposed onto the 3 3 V DC supply voltage at VH pins The 4 and input pins of both input channels are shorted to AGND Then the CS7401xx is commanded to continuous conversion acquisition mode and digital sampled data is collected for the channel under test The zero to peak value of the digital sinusoidal output signal is determined and this value is converted into the zero t
4. 33 5 4 5 Timers and Counters o 34 5 46 GPIOS ond tha hea aa ea de A i a 34 6 Using a CS7401xx based power meter rin 35 6 1 Calibration sradicare ei 35 6 1 1 AC DC Offset and Gain Calibration 35 6 1 1 1 Offset Calibration ii gusce i Oe eee meee P EGG RE AREE a 35 6 1 1 2 Gar Galibratiom zi he eur ead on e mee eei eee dea re eee der bed oae 35 6 1 1 3 CaliBration Order iii ee s en taht yaad Oe d prec edat dunt 36 6 1 2 Temperature Sensor Calibration 36 6 1 2 1 Temperature Gain Calibration 36 6 1 2 2 Temperature Offset Calibration 36 6 L 3 RTC Calibration eeu da X EXE T ERG RARE NE ERU XR da 36 6 1 4 Power Offset Calibration 37 6 1 5 Phase Compensation Calibration 37 6 2 Energy Pulse and 1 Hz RTC OUtpUt ooococococc eee 37 2 DS728PP3 CS7401xx gt CIRRUS LOGIC 6 3 Typical Application Circuit nunannan 38 7 Package Information lt lt lt criar AA E a 39 8 Ordering Information suse sura ka rr A RARA nn 40 9 Environmental Manufacturing amp Handling Information 40 9 REVISION History air e AR AAA AAA 41 Figure 1 CS7401xx Fe
5. CS7401xx Ww s ROM olta H 1 M ge sense High speed Profile E Interface al o Current Sense Buttons LEDs x LAVA gt Switches Ps Mayor Tamper Detect or Other Input gt IRDA or RFComm Power Mgmt Hardware Abstraction 3 6V Power Layer HAL O Supply Battery h Xtal Hardware Solution Software Solution Md Frodi CIRRUS LOGIC Copyright Cirrus Logic Inc 2008 AUG 08 http www cirrus com All Rights Reserved DS728F1 CIRRUS LOGIC CS7401xx TABLE OF CONTENTS 1 Hardware Description iii i a heus 4 2 Firmware API Description 00 ooocooooooooo ooo eo noooananaasass 5 3 Pin Description i2 nsu id ii 6 3 1 GPIO Pin Mutiplexing x asserire REESE REE eR ERE REE ERE REE Oe ee RS 8 4 Characteristics Specifications eee 9 5 Functional Description 0 eee eee seen iaia 19 5 1 Analog Front End veses rebasa a E Eae e de deis 19 5 1 1 Analog Channels 19 5 1 2 ADC Measurements iii DEE ELA RR EA RATER 20 5 1 3 Voltage Reference hh hh 20 5 1 4 Temperature SensSol i iii cR A RA 20 5 2 Power Supervisor and Power Modes sse nn nnn 21 5 2 1 On chip Voltage Regulators 21 5 2 2 Power On Reset and Brown out Detection 22 5 2 3 Low battery Detection 23 5 3 Central Processor Unit
6. External E7PROM Mode Timing Serial Clock SPICLKO Pulse Width Low tg 8 Pulse Width High tjo 8 us MODE setup time to RESET Rising ty 50 m RESET rising to CS falling tio 48 ns SPICSO falling to SPICLKO rising tis 100 8 ns SPICLKO falling to SPICSO rising t14 16 ns SPICSO rising to driving MODE low tis 50 ns SPITXD setup time to SPICLKO rising tig 100 ns Notes 15 Specified using 10 and 90 points on waveform of interest Output loaded with 50 pF 16 Oscillator start up time varies with crystal parameters This specification does not apply when using an external clock source 14 DS728PP3 lt e ERE _ lt c C CS7401xx IRRUS LOGIC SWITCHING CHARACTERISTICS Continued Parameter Symbol Min Typ Max Unit EPOUT Timing Note 17 17and 19 Period tperiod 0 5 230 1 us Pulse Width tow 0 25 230 2 us Rising Time ton 20 ns Falling Time tort 20 ns CLK1HZ Timing Period tperiod 1 S Pulse Width tow 0 5 ms Rising Time ton 20 ns Falling Time tort 20 ns Notes 17 Pulse output timing is specified at DCLK 4 096 MHz Both period and pulse width are user programmable 18 Output pin has the driving load of 30 pF 19 Timing is proportional to the frequency of DCLK toff ton ipw EPOUT tperiod
7. The CS7401xx provides DC offset and gain calibration that are applied to the voltage and current measurement and AC offset calibration which is applied to the voltage and current RMS calculations Since all ADC channels have independent offset and gain calibration values users can perform offset and gain calibration on any path independently In power meter applications with high pass filters enabled DC offset is optional For most applications AC offset calibration is not required Figure 19 demonstrates the algorithms within the calibration data flow The value in the APR Accumulation Period Register which is passed during component initialization determines the number N of samples averaged during calibration DC offset and gain calibrations take N Tserte samples As N is increased the accuracy of calibration results also increases Cirrus Logic recommends setting N and Tsertre to at least 4000 samples Modulator APE N Reference and Eu r Input a Software x X S gt 2 s gt SINC Filter I Filter s dili iw o i a e uu iam Q g 5 Me gt O O o D A A A N legate X N Negate A A 0 6 a X Figure 19 DC AC Offset and Gain Data Flow 6 1 1 1 Offset Calibration During offset calibrations no line voltage or current should be applied to the power meter DC Offset Calibration
8. lt e ERE _ lt c gt CIRRUS LOGIC CS7401xx 5 4 4 LCD Controller Driver The LCD controller generates the timing signals that drive a static or multiplexed LCD panel with support for up to 30 segments multiplexed with up to four common signals The LCD controller consists of a control register 3 display memory registers and 3 buffer registers The control register defines the mux mode number of segments LCD frequency and blinking control etc Dis play memory registers defines the pixels display on or off Display memory registers are written through buffer registers To drive a LCD panel the corresponding segment and common pins have to be configured as LCD driver enabled LCD controller features include display buffer blink capability configurable frame frequency and blink frequency number of segments programmable support for four types of LCDs static 2 mux 3 mux and 4 mux 5 4 4 1 Operation The number of pixels that an LCD can drive is given by the mux mode times the number of segment pins The voltage applied across a particular pixel is the voltage on the COM pin minus the voltage on the SEG pin If the resulting voltage is above the Von threshold voltage the pixel is visible If the voltage is below the Vg threshold voltage the pixel will not be visible In multiplexed LCD applications the segment data for the second third and fourth column of the display memory are time multiplexed
9. T mn gt CIRRUS LOGIC CS7401xx E 5 4 2 UART IRDAS Each of the two UARTs is a serial communication controller with full infrared support which is also compatible to industry standard 16C550 UART devices These intelligent peripherals support the RS 232 and Infrared Data Association IDAS SIR physical lay er standards Modem control signals CTS DCD DSR and RI are supported DTR and RTS signals are not supported and could be implemented using GPIOs The controllers have a 16 byte FIFO which frees the CPU of excessive software overhead Interrupt support for all operations has been included in this architecture The controllers offer programmable registers for routing interrupts and handshake signals The UARTS incorporate an IrDA SIR ENDEC encoder decoder The IrDA physical layer specification is intended to define a half duplex infrared communication link for exchanging data over a distance of up to 1 meter The full standard includes data rates up to 115 kbps UARTO is the dedicated communication interface to a host PC when the CS7401xx is running in ROM EDM Profile Optional Signals CS7401xx DTRO r gt ls RTSO Isolation DSRO j and gt PC DCDO l RS232 MODEM RIO J Receiver TXDO m RXDO _ Figure 15 Typical UART Connections CS7401xx TXD1 RXD1r GPIO J Shutdown IrDa Transceiver
10. 1 After reset and by default pin 14 through pin 34 and pin 36 through pin 43 are configured as LCD functionality 2 After reset and by default pin 35 and pin 44 through pin 55 are input GPIOs that need to be pulled to a high low CMOS level externally 3 Pin 52 TXD1 has special factory test functionality and has to be pulled down at reset 4 Pin 55 TXDO acts as a Flash lock request at reset if it is high so normally this pin should be pulled down at reset Flash lock can be done by software 5 Pin 50 is the BOOT pin and normally pulled high at reset in order to boot from ROM 6 Pin 35 is the EM pin and normally pulled up at reset in order to run the application code after the booting from ROM A pull down option through a button switch should also be provided to be able to run the ROM EDM Profile after reset 34 DS728PP3 lt e ERE _ lt c CIRRUS LOGIC CS7401xx M 6 USING A CS7401xx BASED POWER METER 6 1 Calibration 6 1 1 AC DC Offset and Gain Calibration To ensure power measurement accuracy a CS7401xx based power meter requires calibration prior to field use When calibration completes the calibration results are saved to Flash memory for subsequent use Factory embedded Energy Monitor firmware provides all the power measurement calibration functions through calibration components This section discusses the technical details and steps for calibrating a CS7401xx power meter
11. Figure 16 Typical IIDA Connections DS728PP3 31 i gt CIRRUS LOGIC CS7401xx 5 4 3 Synchronous Serial Communication Port The synchronous serial communication port SSP provides a convenient method of serial interaction for high speed communi cation between similar shift register type devices The SSP is a programmable serial port that is an AMBA APB intelligent pe ripheral The SSP port supports Motorola SPI format TI synchronous serial format and National Semiconductor MicrowireTM format The SSP is a high speed synchronous serial input output port that allows a serial bit stream of programmed length 4 to 16 bits to be shifted into and out of the device at a programmed bit transfer rate The SSP is normally used for communication between the CPU and external peripherals or another microcontroller Typical applications include interface to external I O or peripheral expansion via devices such as nonvolatile memory display drivers and digital to analog converters The SSP is equipped with four communication interface signals The pins SPICLKO SPIRXD and SPITXD are used in all SSP pin modes The pin SPCSO is optional and may be used if the pin is configured CS7401xx SPICS M SPICLK SSP Compliant SPITXD Device SPIRXD 4 amp 4 Figure 17 CS7401xx SSP Port Connections in Master Mode 32 DS728PP3
12. Read Write Time No Wait State 30 ns FLASH Program Time per Word 20 40 us Read Time No Wait State 30 ns Page Erase 2 kB 20 40 ms Mass Erase 20 40 ms Maximum number of Write Cycles 20 k Notes 25 Minimum supply voltage when the data in the RAM remain unchanged No program execution should take place POWER ON RESET POR AND BROWNOUT DETECTION TIMING Parameter Symbol Min Typ Max Unit VH Vt1 to RESET pin high to 2 ms VH Vt1 to POR_3 3V rising ty 50 us POR_3 3V rising to Bandgap_on rising to 2 ns Bandgap_on rising to Bandgap_rdy rising t3 50 us Bandgap_rdy rising to 65 536 MHz OSC_on rising t4 20 ns 65 536 MHz OSC_on rising to Regulator_on rising t5 1 us Buck Regulator on to ARM Reset rising tg 4 us VH vt2 to PSUP_INT 1 high t z 60 us 26 POR timing parameters and timing are shown in Figure 6 on page 18 DS728PP3 17 i Vt4 18 C vti VH 3 3V RESET Pin POR_3 3V Bandgap_on Bandgap_rdy 65 536MHz OSC_on Buck Regulator_on ARM_Reset vt2 VH 3 3V IRRUS LOGIC CS7401xx Figure 6 POR and Reset Timing Vt3 t7 PSUP INT 1 Figure 7 Brownout Timing Table 3 Typical Brownout and POR Threshold Voltages Voltage Threshold VH Voltage Threshold Vy 1 95 V Voltage Threshold Vi 2 66 V Voltage Threshold V4 2 6V Vol
13. The DC offset calibration function measures and averages DC values on the specified ADC channel with zero input and returns the inverse result This result is passed to the AFE device driver during initialization and added to instantaneous measurements in subsequent conversions removing the DC offset Prior to performing DC offset calibration the gain of the channel should be set to 1 0 AC Offset Calibration The AC offset calibration function measures the residual RMS value on the specified ADC channel with zero input and returns the inverse result This result is passed to the power utilities component during initialization and added to RMS measurements in subsequent conversions removing the AC offset 6 1 1 2 Gain Calibration During gain calibration reference voltage and current must be applied to the power meter or optionally apply scaled low level signals to the AIN1 and AIN2 pins of the CS7401xx Either AC or DC low level reference signals can be used on the AIN1 DS728PP3 35 i gt CIRRUS LOGIC CS7401xx and AIN2 pins for AC gain calibration If a DC signal is used the associated high pass filter HPF must be disabled Using a reference that is too large or too small can cause an out of range condition and should be avoided Refer to the 5 1 1 Analog Channels on page 19 for the maximum input voltages on AIN1 and AIN2 pins AC Gain Calibration Normally the maximum current Imax and reference voltage Un
14. d x oo E gue O40 S858 8h ca 0 oo 25888 E 55 3 OB Lu Boc C n mm QU o ala v o o 090999290909 aO rozuoczasn GX0 0000 aa gt gt gt Olx FFF E 000000 64 63 62 VA i GPIO34 SPITXD SEG26 AIN1P 2 GPIO33 SPCLK SEG25 AIN1N 3 GPIO32 SPCS SEG24 RI AIN2P 4 GPIO31 SPIRXD SEG23 AIN2N 5 EPOUT GPIO30 TE1 SEG22 CLK1HZ VBAT 6 LCDV3 GPIO29 AIN3P 7 LCDV2 GPIO28 AIN3N 8 LCDV1 GPIO27 GNDA 9 CS7401xx LCDVO GPIO26 XIN LCDBP3 GPIO25 VREF LCDBP2GPIO24 XOUT LCDBP1 GPIO23 VBG LCDBPO GPIO22 SEGO GPIOO SEG21 GPIO21 EM SEG1 GPIO1 SEG20 GPIO20 SEG2 GPIO2 SEG19 GPIO19 5 36 ed 0 IIS a a a a aaa 20000000Q MR EE SS OOO o o oo 5 o Ww Ww Ww Ww Ww Ww Ww ad d d d ad a asi d a 9999990099 Qo oo ood t Table 1 CS7401xx Pin Functions Name Pin IO Function VA 1 External Analog supply 1 8 V AIN1P 2 Differential analog input pin for analog channel 1 AIN1N 3 Differential analog input pin for analog channel 1 AIN2P 4 Differential analog input pin for analog channel 2 AIN2N 5 Differential analog input pin for analog channel 2 VBAT 6 Battery voltage monitor AIN3P 7 Differential analog input pin for analog channel 3 AIN3N 8 Differential analog input pin for analog channel 3 GNDA 9 Analog ground XIN 10 Input of inverting amplifier for crystal oscillator Connect to one side of 32 768k Hz crystal or to crystal oscillator source When using an external 32 768 kHz clock the input level requir
15. pod Software Interrupt 0x00000008 0x00000020 P 0x0000001F Undefined Instructions 0x00000004 Exception Interrupt and Reset Vectors Reset 0x00000000 22 _ __eE 0x00000000 Figure 12 CS7401xx Memory Map C language programs expect to have access to a fixed area of program memory where the application image resides and to support two data areas that grow dynamically and where the compiler often cannot work out an optimum size These dynamic areas are The stack Whenever a non trivial function is called a new activation frame is created When a function returns its stack space is automatically recovered and will be reused for the next function call The heap The heap is an area of memory used to satisfy program request for more memory for new data structures A program which continues to request memory over a long period of time should be careful to free up all sections that are no longer needed otherwise the heap will grow until memory is full Due to the limitations of the SRAM in a small embedded system such as the CS7401xx minimal stand alone run time libraries should be ported to the target environment which allows basic C programs to run This library therefore reflects the minimal re quirements of a C program 5 3 2 4 ROM ROM provides single cycle read only memory and is factory programmed with a Boot Monitor and the Energy Monitor firmware image At power up and wit
16. pp _____ fs Jerross mm Pll Down Flash Lock DS728PP3 lt e ERE _ lt c C IRRUS LOGIC CS7401xx 4 CHARACTERISTICS amp SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Positive Supply Voltage Note 1 Active Mode VH 2 6 3 3 3 6 V Power Saving Modes 2 4 2 7 3 6 V Internal Supply Voltage VSC 1 8 V Digital Supply Voltage Note 2 VD 1 7 1 8 1 9 V Analog Supply Voltage Note 2 VA 1 7 1 8 1 9 V Internal Voltage Reference VREF 1 8 V Internal or External Bandgap Reference VBG 1 27 V System Clock DCLK 1 953 4096 32768 kHz Real Time Clock Crystal Frequency RTCLK 32 768 kHz Operating Temperature Range TA 40 85 C Notes 1 See diagram below for typical power supply connection See section 5 1 5 for the definition of power modes 2 Supplied by VSC 3 3 V Operation Internal VREF and VBG Figure 3 DC Supply and Reference Connections DS728PP3 9 cti co A A CIRRUS LOGIC CS7401xx ANALOG CHARACTERISTICS Min Max characteristics and specifications are guaranteed over all Recommended Operating Conditions Typical characteristics and specifications are measured at nominal supply voltages and TA 25 C VH 3 3 V 596 GNDA GND 0 V VREF 1 8 V All voltages with respect to 0 V MCLK modulator clock 256 kHz DCLK CPU Clock 4 09
17. CPU cius acuuurRka Seed Ra MEER RR EE ewes 24 5 3 1 ARM7TDMI CORE 24 SILI TRUMD MO iii ER RR A NIE A GR NR pa 24 5 3 1 2 Long Multiply ut eode a tok quad ahaa 24 5 3 1 3 EmbeddediICE Module ii wawa Wa een deed EX pda eig eR ea PR b a a 24 5 3 1 4 EXCOeDlIODS iii alal x ida da RE 24 5 3 1 5 ARM REGISIErS ug a A ERE ERRARE wala nt 25 5 3 2 Memory SYSIOM sisas ara a Eee ada dads ACE GORGE 25 5 9 2 1 Memory REMAP iii a rs des odds asi em ausu 25 5 3 2 2 I O peripheralsovervieW 25 5 3 2 3 Memory Map utere a Pere eee eund e teo la d ead 26 5 39 24 ROM soso Work LA VAL eel wales e LR RR rg ate p AR a vus ae ee dee ate 26 5 9 2 5 SRAM ii AA basi dab hae eee ee Pb 27 5 3 2 6 FLASH and FLASH Interface 27 5 3 3 Interrupt Controller 27 5 3 3 1 Interrupt Latency usu sica rafael A Rae 27 5 3 4 Boot Monitor LL 28 5 3 5 JTAG Debug Interface 29 5 4 Embedded Peripherals raise a hoec Ra n 30 5 4 1 Clock Generation Real Time Clock RTC 30 5 4 2 UART IRDAS x pipi pr eee piana PESA Wena wea bees 31 5 4 3 Synchronous Serial Communication Port 32 5 4 4 LCD Controller Driver RR Rh m he 33 54 41 Operation ei pale aa e ina ot 33 5 4 4 2 LCD Operating Frequencies Example
18. battery volt age may differ considerably with or without a load an internal 8 Kohms resistive load can be enabled on VBAT pin to implement more practical low battery detection CS7401xx 8 KOhms BrownoutVbat load enable Y Voltage Threshold BrownoutVbat_cntrl 4 0 VBAT lt Vbat_low Figure 11 Low Battery Detection DS728PP3 23 i gt CIRRUS LOGIC CS7401xx 5 3 Central Processor Unit CPU The CPU offers a high performance processor utilizing the high speed 16 32 bit ARM7TDMI core resulting in a high instruction throughput while maintaining high code efficiency The processor core views ROM SRAM Flash and memory mapped registers MMRs as a single linear array ICE debugging is supported via the JTAG interface 5 3 1 ARM7TDMI CORE The ARM7TDM core is a 32 bit reduced instruction set computer RISC It uses a single 32 bit bus for instruction and data The length of the data can be 8 16 or 32 bits and the length of the instruction word is 32 bits The ARM7TDMI is an ARM7 core with 4 additional features Thumb 16 bit compressed instruction set JTAG Debug support on chip enabling the processor to halt in response to a debug request Multiplier enhanced with higher performance yielding a full 64 bit result EmbeddedICE included within the core hardware to support embedded system debugging 5 3 1 1 Thumb Mode An ARM instruction is 32 bits long The ARM7TDMI pro
19. internally to step down the single power supply VH to1 8V for the analog and the digital circuitry Refer to figure 2 on page 8 for recommended power supply connections Buck Regulator o 34 I Buck_enable 3 L l Linear Regulator o me Figure 9 On chip Voltage Regulators The buck regulator can supply the maximum load current of 80mA and is used in active power mode The operation of the buck regulator needs the internal 65 536 MHz oscillator and bandgap to be ready The linear regulator can supply a load current up to 2 mA and be used in power saving modes If the linear regulator is enabled the Flash operation read or write must be avoided and software code should be running from either ROM or RAM The internal Buck_enable signal controls which regulator is en abled DS728PP3 21 i gt CIRRUS LOGIC CS7401xx 5 2 2 Power On Reset and Brown out Detection Proper operation of the POR system requires that the external reset pin be connected to a RC with a time constant greater than 2 ms This reset input pin is AND ed with an internal signal indicating that the voltage is above 1 95 V to start the power on se quence within the device This signal will then enable the band gap internal 65 536MHz oscillator buck regulator and finally release the reset to the ARM processor This comparator has hysteresis such that when the voltage drops b
20. pin When using the internal reference a 10 uF capacitor must be connected from the VREF pin to AGND to filter the output stage noise and ensure stability during conversions Also a 1uF capacitor must be connected from VBG pin to AGND to filter the band gap noise The reference can be used as a reference for other circuits in the system However an external buffer would be re quired because of the low drive capability of the VREF output The VREF pin also provides a means of connecting an external reference 5 1 4 Temperature Sensor The CS7401xx contains an on chip temperature sensor which is designed to assist in characterizing the measurement elements over a desired temperature range Once a temperature characterization is performed the temperature sensor can then be utilized to assist in compensating for temperature drift By setting the appropriate bits in temperature sensor configuration register CONFIG TS the temperature sensor can be pow ered up and routed to an ADC channel ADC channel 2 or 3 The ADC output can then be calculated to the real temperature value by the firmware The calibration component in ROM also provides temperature calibrations After the calibrations the on chip temperature sensor can reach to an accuracy of 5 C 20 DS728PP3 CIRRUS LOGIC CS7401xx EE 5 2 Power Supervisor and Power Modes The CS7401xx power supervisor circuitry provides battery mode detection power on reset and prog
21. the analog front end AFE subsystem and the digital core The AFE subsystem has its own clock divider needed to set the sampling rate of the ADC The digital core is clocked by the output of a clock divider which can provide 4 MHz 8 MHz 16 MHz or 32 MHz oper ational speed The default DCLK is 4 096 MHz During brownout conditions the system clock can be switched to 32 kHz operation This is a low power standby mode where the RTC RAM and CPU are still operational The AFE is not powered during standby mode In standby mode Flash is operational only in read mode Interrupts can be used to bring the system out of standby mode or the power management can detect that power has been restored and software will bring the device out of standby mode DCLK is also used to drive the timing for the SPP and UART peripherals Care must be taken to ensure these clock dividers are changed when the DCLK speed is changed A Div by MCLK Analog Fast Clock Front Generation N End gt XIN 1 22pF e O LO 32 768 O wo kHz El i 8 X UART wu 3 Clock Divider 09 0 22pF N 1024 a N 1 AGND xcik SSP i Clock Divider XCLK Switch 16 777216 MHz CLK RTC Slow CIKEn cuan Calibration Timers a Watchdog i RTC DCLK Counter To ARM Memory amp Other Peripherals Figure 14 Clock Generation Diagram 30 DS728PP3 lt e ERE
22. with COM1 COM2 and COM3 respectively 5 4 4 2 LCD Operating Frequencies Example When DCLK 4 096MHz f cp is programmable among 1 kHz 512 Hz 256 Hz 128 Hz 64Hz 32Hz and 16Hz ficp 2 Muxmode firame When DCLK 4 096MHz the blink frequency is programmable among 0 03Hz 0 06Hz 0 12Hz 0 25 Hz 0 5 Hz 1 Hz and 2 Hz Table 7 Modes of Operation Voltage Across Voltage Across Mode On Pixel Off Pixel Static Vdd Vdd 0 2 mux Vdd Vdd Vdd 2 Vdd 2 3 mux 2Vdd 3 2Vdd 3 Vdd 3 Vdd 3 4 mux 2Vdd 3 2Vdd 3 Vdd 3 Vdd 3 CS7401xx SEG lt 0 29 gt LCD Panel LCDBP 0 3 LCD LCDLVL 0 3 Level Figure 18 CS7401xx LCD Connections DS728PP3 33 gt CIRRUS LOGIC CS7401xx 5 4 5 Timers and Counters In CS7401xx two 32 bit and two 16 bit timers counters are available and can be used for a wide range of functions frequency measurement event counting interval measurement pulse generation delay timing Watchdog timer etc The timers are driven by a system clock and can be initialized by writing a count value through the APB Each timer is a down counter with selectable pre scale The pre scaler allows either the system clock to be used directly or the clock frequency di vided by 16 or 256 may be used This functionality is provided by 0 4 or 8 stages of pre scale Each timer may be configu
23. with a battery monitor and brown out detection which allows the software the flexibility to control the power mode AFE 2 Timers 42 GPIOs Epulse 4x30 Segments 2 Lines Muxed 1 Line 39 Lines Temperature RAM ROM INTO 8kB 32kB see 32 64 128 kB s AIN3 1 AIN3 Embedded Peripherals VRef BG Power Supervisor DC RC 1Hz 1SSPort EM BM FL 2 UARTS 3 Lines 4 Lines 3 Lines 8 Lines Battery Monitor Pin Control z x XOUT 4 DS728PP3 lll ERE A gt CIRRUS LOGIC CS7401xx 2 FIRMWARE API DESCRIPTION Development of user Metrology Register and Communications MRC code is accelerated with the availability of many high level APIs in both ROM based firmware and library function calls The product is supported with application examples many develop ment notes and library of functions which are available in the CS7401xx Software Development Kit SDK C code based devel opment platforms for the ARM7 can be provided by several vendors such as Keil One of the key firmware APIs is Cirrus Logic s wavelet based algorithm for power calculation This algorithm coupled with the high performance Delta Sigma AX ADCs produces data linearity accuracy of 0 1 over 3000 1 dynamic range for active pow er measurement In addition to active power it also provides for measurement of reactive and apparent power for both total and fundamental power A key feature of this algorithm is the accu
24. 6MHz Accuracy measurements are based upon using ROM based metrology code provided by Cirrus Logic Parameter Symbol Min Typ Max Unit Accuracy Active Power Accuracy Note 3 P Input Range 0 03 100 0 1 Reactive Power Accuracy Note 3 Input Range 0 2 100 Q 0 1 Input Range 0 1 0 2 0 5 Voltage amp Current RMS Accuracy Note 3 Input Range 0 2 100 RMS 0 1 Input Range 0 1 0 2 0 5 Apparent Power Accuracy Note 3 Input Range 0 2 100 S 0 1 96 Input Range 0 1 0 296 0 5 Power Factor Accuracy Note 3 Input Range 0 2 100 PF 0 1 Input Range 0 1 0 2 0 5 Analog Inputs Differential Input Range 1 34x 400 3x 200 ex IN s x19 Y 12x 50 Single Ended Input Range 1 34X 200 mV 3X IIN 100 6X 50 12X 25 Input Capacitance IC 35 pF Effective Input Impedance EII 400 kQ Channel to Channel Crosstalk 50 60 Hz Note 4 120 dB Common Mode Rejection 50 60 HzZ CMRR 60 dB Gain Error GE 0 3 Gain Drift GD 20 ppm C Notes 3 Applies when the HPF option is enabled input frequency 50 Hz 5 and fundamental harmonics measurement 4 Full scale input to the driven channel and measured channel input grounded 10 DS728PP3 ANALOG CHARACTERISTICS continued CS7401xx
25. 728PP3 25 i gt CIRRUS LOGIC CS7401xx 5 3 2 3 Memory Map The CS7401xx has its memory arranged as a linear set of logical addresses The ARM7 core sees memory as a linear array of 232 byte locations The different blocks of memory are mapped as outlined in Figure 12 The memory organization is configured in little endian format the least significant byte is located in the lowest byte address and the most significant byte in the high est byte address Register addresses are all word aligned The exception vectors are all mapped at the bottom of the memory array from address 0x0000 0000 to 0x0000 0020 OxFFFFFFFF P di Clock Sys Ox1D000000 i AFE 0x1C000000 Oscillator 0x18A00000 LCD 0x18800000 OXLFEFEFEE GPIO 0x18700000 RTC 0x18600000 System Registers UART1 0x18500000 0x10000000 UARTO 0x18400000 p Timer 0x18300000 SSP 0x18100000 APB 0x18000000 0x08007FFF Su 7 Memory Configuration 0x11000000 30K ROM 0x08000800 0x080007FF 2K FLASH 0x08000000 Ox04001FFF 8K RAM ee 0x040000D0 M di Reserved EM and BM OxO40000CF Ex dcs ME 7 Ox04000000 uu _ _ A OxO0D1FEFF Ra Reserved for EM 0x1100001F 0x0001F800 eee Calibrations 0x1100000C Ox0001F7FF 0x00000018 126K FLASH E FIQ 0x00000016 EC IRQ 0x00000014 Reserved d Data Abort 0x0000000C 0x00000800 Pd Prefetch Abort Boot Monitor BM
26. Dynamic Core Frequency from 4 MHz to 32 MHz 32kB 64kB or 128kB On chip Flash Memory Flash Locking Mechanism to Protect User s Program 8kB On chip RAM 32kB On chip ROM Single 32 kHz Crystal with FLL to Internal Oscillator Internal Oscillator Robust Operation with EFT Events On chip Crystal Capacitors for Frequency Stability JTAG Interface On chip Peripherals LCD Driver with up to 120 Segments 30 x 4 RTC with Auto Calibration and 1Hz Output Two UART Communications Ports Configurable Sync Serial Port with SPI Mode Programmable GPIOs Timers and Watchdog Timer Dedicated Energy Pulse Output ROM Profile Factory ready Communications using UARTO Automated Fast Calibration of Gain Offset and Phase Power Measurement Access for Evaluation Power Management for Low power Operation General purpose Device Drivers Program Loader for Flash Code Download Advanced Power Management On chip Switching Buck Converter for Internal 1 8V 5 mA 4 MHz 17 mA 32MHz Low power Mode 25 uA 16kHz Power Supervisor with Power On Reset POR Programmable Battery Monitoring Programmable Brown out Other Single Power Supply VH 2 6 to 3 6 V 64 lead LQFP Package Temperature Range 40 C to 85 C Supports ARM7 Industry standard Tools Supports Shunts amp Current Transformers CTS Customer Development Board CDB Available ORDERING INFORMATION See page 40 for details
27. Figure 4 EPOUT Timing toff ton ipw gt CLK1HZ tperiod Figure 5 CLK1HZ Timing DS728PP3 15 lt e ERE _ lt c gt CIRRUS LOGIC CS7401xx ABSOLUTE MAXIMUM RATINGS WARNING Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes Parameter Symbol Min Typ Max Unit DC Power Supplies Notes 20 and 21 VH 0 3 3 63 V Digital VD 0 3 1 98 V Analog VA 0 3 1 98 V Input Current Any Pin Except Supplies Notes 22 23 24 lin 10 mA Output Current louT 100 mA Output Current Sourced or Sunk by Any I O Pin 5 mA Analog Input Voltage All Analog Pins Vina 0 3 VA 0 3 V Digital Input Voltage AllDigitalPins Vip 03 VD 03 V Ambient Operating Temperature TA 40 85 C Storage Temperature Tstg 65 150 C Notes 20 VA and GNDA must satisfy VA AGND 1 98 V 21 VD and GNDA must satisfy VD AGND lt 1 98 V 22 Applies to all pins including continuous over voltage conditions at the analog input pins 23 Transient current of up to 100 mA will not cause SCR latch up 24 Maximum DC input current for a power supply pin is 50 mA 16 DS728PP3 lt e ERE _ lt c gt CIRRUS LOGIC CS7401xx MEMORY Parameter Symbol Min Typ Max Unit RAM
28. G Port RESET 60 Active low reset GND 61 Ground VSC 62 Internal Voltage regulator output VH 63 External 3 3 V supply VD 64 External Digital supply 1 8 V See Section 5 4 6 GPIOs on page 34 for details on special functionality of some GPIO pins 3 1 GPIO Pin Multiplexing The GPIO pins can be multiplexed with various other functions such as SSP port serial ports timer input energy pulse output clock I Os and various pull ups and pull downs that control initialization The following provide a reference for the pin multiplexing options Table 2 GPIO Pin Multiplexing Pin LCD Function GPIO Pins SSPPort Seria Port Timers EPulse Clock Init PurPD 14 34 LCD sego 20 aPvoo20 AA _____ 35 icDseg21 cevoz22 TT Pull Up Energy Meter jjeolcbgeo3 J cevo2227 J T o y 4043 CDvotageo3 cP O2020 T 44 LcDSeg22 eposo r4EnablelEpuse imzot 45 icDseg23 cPvoO31 sPIRceve o To y 4b Ecbsegza cPUOSR series 1 To o T T y O 47 LCD Seg25 GPWO33 sPiCiok_ S T 48 CDSeg26 GPYO34 sPiTransmit Riso T Too j 49 CDSeg27 cP O3SS sro TT T ST 50 LCbSeg28 cgevox bebo Pullup BootMode 51 icDseg29 cPvos Jerso Re kn 52 jeevos moi T3Enabe DcikoOut PullDown Tes ss poo jeevs wa jsp Jjeevo rx _
29. RSTOOD TO BE FULLY AT THE CUSTOMER S RISK AND CIR RUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS CUSTOMER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY INCLUD ING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic Inc All other brand and product names in this document may be trademarks or service marks of their respective owners IrDA is a registered trademark of Infrared Data Association Corporation SPI is a trademark of Motorola Inc Motorola is a registered trademark of Motorola Inc ARM AMBA Primecell and Thumb are registered trademarks of ARM Limited ARM7 ARM7TDMI TDMI and EmbeddediCE are trademarks of ARM Limited Microwire is a trademark of National Semiconductor Corporation Tl is a registered trademark of Texas Instruments Incorporated 42 DS728PP3
30. TURING amp HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating Max Floor Life CS740111 1QZ CS740121 IQZ CS740131 IQZ 250 C 7 Days MSL Moisture Sensitivity Level as specified by IPC JEDEC J STD 020 40 DS728PP3 t ll ERE T mn CIRRUS LOGIC liti ii ii ii so REVISION HISTORY Revision Date Changes A1 October 2007 Advance Release PP1 April 2008 Initial Preliminary Release PP2 April 2008 Preliminary Release PP3 August 2008 Initial Public Release F1 August 2008 Final Release DS728PP3 41 i gt CIRRUS LOGIC CS7401xx Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products a
31. The temperature calibration process involves the software re porting a temperature and then the user manually calculating the Gain and Offset using the external temperature reference 6 1 2 1 Temperature Gain Calibration To calibrate temperature gain use two temperature points far enough apart to give reasonable accuracy for example 25 C and 85 C Divide the actual temperature difference by the software measured difference for the two temperatures resulting in a gain correction factor Save this value as the Temperature Gain and it will be multiplied as shown above 6 1 2 2 Temperature Offset Calibration Even though users can perform offset calibration at any temperature Cirrus Logic recommends a temperature of mid scale if any gain error exists Subtract the software measured temperature from the actual temperature to determine the offset error Save this value as the Temperature Offset and it will be added as shown above 6 1 3 RTC Calibration RTC calibration requires a very stable and accurate 16 777216 MHz clock source connected to the CS7401xx RCLK pin 51 The RTC device driver in Energy Monitor firmware provides RTC calibration software functions Both hardware and software con trols the RTC calibration process The calibration duration is 1 2 or 4 seconds configurable After calibration completes software stores the calibrated value in the RTCINCR register 36 DS728PP3 gt CIRRUS LOGIC CS7401xx 6 1 4 Power Off
32. ack below 1 7 V the part will be held in reset Refer to Power On Reset POR and Brownout Detection Timing on page 17 and Figure 6 on page 18 for detail on timing There are two conditions that can generate an interrupt to the ARM processor as an indication of a potential brown out condition The first is a comparator between VH and the battery If VH falls below the battery voltage the internal PSUP INT O0 interrupt will trigger if enabled The second is a comparator between VH and an internal programmable comparator This comparator can be programmed from 2 75 V to 3 05 V in 0 1 V steps If VH falls below the programmed threshold the internal PSUP INT 1 in terrupt will trigger if enabled At the point the interrupts occur it is the responsibility of the software to manage the power state See the power manager soft ware development note for more details on the software operation during this condition VH Startug 3 6V PSUP INT 1 Brownout3p3 cntrl 2 75 to 3 05V PSUP INT 0 Figure 10 POR and Brownout Functional Diagram 22 DS728PP3 gt CIRRUS LOGIC CS7401xx pum M I M M M M M 5 2 3 Low battery Detection The CS7401xx contains a voltage comparator for low battery detection When the comparator is enabled and the battery voltage is lower than the pre programmed threshold the Vbat low bit in the power supervisory register will be set Because
33. are used for AC gain calibration and Irms Vrms will be calibrat ed to 60 of the full scale register value During AC gain calibration the RMS level of the applied reference is measured with the preset gain then divided into 0 6 and the quotient is returned as the gain calibration value DC Gain Calibration With a DC reference applied the DC gain calibration function measures and averages DC values on the specified voltage or current paths and returns the reciprocal result as the gain calibration value For power energy measurement applications DC gain calibration is not applicable 6 1 1 3 Calibration Order 1 DC Offset if needed 2 AC Gain 3 AC Offset if needed If both AC gain and offset calibrations were performed it is possible to repeat both to obtain additional accuracy as AC gain and offset may interact 6 1 2 Temperature Sensor Calibration By setting the appropriate bits in the CONFIG TS register the internal temperature sensor can be routed to ADC channel 2 or channel 3 Temperature calculation and calibration functions are provided through the components in Energy Monitor firmware Temperature sensor calibration involves the adjustment of two internal parameters Temperature Gain and Temperature Offset These parameters are applied to measured temperature in the following way TemperatureReported TemperatureRead TemperatureGain TemperatureOffset By default Temperature Gain is 1 and Temperature Offset is 0
34. ature Diagram 4 Figure 2 Firmware Architecture 5 Figure 3 DC Supply and Reference Connections 9 Figure 4 EPOUT TIMING kb rif chee See SS ita Ra AA 15 Figure 5 CLKTHZ Timing ee sairastuneen x ea Ea 15 Figure 6 POR and Reset Timing 18 Figure 7 Brownout Timing 18 Figure 8 Typical Fully Differential Connection for Current Channel 20 Figure 9 On chip Voltage Regulators 21 Figure 10 POR and Brownout Functional Diagram 22 Figure 11 Low Battery Detection 23 Figure 12 CS7401xx Memory Map cs usd eds eds eee i eee aaa 26 Figure 13 CS7401xx Boot Sequence 28 Figure 14 Clock Generation Diagram 30 Figure 15 Typical UART Connections 31 Figure 16 Typical IrDA Connections 31 Figure 17 CS7401xx SSP Port Connections in Master Mode 32 Figure 18 CS7401xx LCD Connections 33 Figure 19 DC AC Offset and Gain Data Flow
35. can Architecture Refer to this standard for an explanation of the terms and for a description of the Test Access Port TAP controller states The CPU contains hardware extensions for advanced debugging features These make it easier to develop ap plication software monitors BSL and the hardware itself The EmbeddedICE module provides integrated on chip support for the core A JTAG debug probe e g Multi ICE and Em beddedICE are a JTAG based debugging system for the CS7401xx SoC providing the interface between a debugger and the ARM core embedded within the ASSP This system provides real time address dependent and data dependent breakpoints watchpoint registers single stepping full access to and control of the ARM core full access to the SOC full memory access read and write Once the Flash is locked access to Flash is prohibited full 1 0 system access read and write enable the embedded microprocessor to access services of the host system DS728PP3 29 CIRRUS LOGIC CS7401xx ris _ __r_r__r ____zi 5 4 Embedded Peripherals The CS7401xx SoC incorporates a collection of intelligent peripherals that are required in applications specific to energy meter ing All embedded peripherals are fully compliant with the widely used SoC bus protocol the Advanced Microcontroller Bus Ar chitecture AMBAS protocol from ARM The embedded peripherals utilize the AMBA Advanced Peripheral Bu
36. cessor supports a second instruction set that has been compressed into 16 bits the Thumb instruction set Greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set which makes the ARM7TDMI core particularly suitable for embedded applications However the Thumb mode has two limitations Thumb code usually uses more instructions for the same job so ARM code is usually best for maximizing the performance of any time critical code The Thumb instruction set does not include some instructions that are needed for exception handling so the core will automatically switch to ARM code for exception handling Since the CS7401xx program memory Flash is on chip up to 3096 code density can be achieved by utilizing Thumb instructions Thumb and ARM instructions both reside in 32 bit Flash memory Therefore one fetch will retrieve two Thumb instructions from the 32 bit memory 5 3 1 2 Long Multiply The Energy Monitor EM requires efficient digital signal processing DSP routines to calculate power energy measurements The ARM7TDMI instruction set includes four extra instructions which perform 32 bit by 32 bit multiplication with 64 bit product and 32 bit by 32 bit multiplication accumulation MAC with 64 bit result These calculations are achieved in a reduced number of cycles compared to a standard ARM7 core 5 3 1 3 EmbeddedIlCE Module The EmbeddedICE module provides integrated on chi
37. e ments for the XIN pin are O to 1 8V 6 DS728PP3 Table 1 CS7401xx Pin Functions Continued CS7401xx VREF 11 O Internal reference voltage output 1 8V XOUT 12 O Output of inverting amplifier for crystal oscillator Connect to one side of 32 768k Hz crystal VBG 13 O Output of band gap 1 2V SEGO GPIOO 14 I O LCD segment output O General purpose digital I O O SEG1 GPIO1 15 I O LCD segment output 1 General purpose digital I O 1 SEG2 GPIO2 16 I O LCD segment output 2 General purpose digital I O 2 SEG3 GPIO3 17 I O LCD segment output 3 General purpose digital I O 3 SEG4 GPIO4 18 I O LCD segment output 4 General purpose digital I O 4 SEG5 GPIO5 19 IO LCD segment output 5 General purpose digital I O 5 SEG6 GPIO6 20 I O LCD segment output 6 General purpose digital I O 6 SEG7 GPIO7 21 I O LCD segment output 7 General purpose digital I O 7 SEG8 GPIO8 22 IO LCD segment output 8 General purpose digital I O 8 SEG9 GPIO9 23 I O LCD segment output 9 General purpose digital I O 9 SEG10 GPIO10 24 I O LCD segment output 10 General purpose digital I O 10 SEG11 GPIO11 25 IO LCD segment output 11 General purpose digital 1 0 11 SEG12 GPIO12 26 I O LCD segment output 12 General purpose digital I O 12 SEG13 GPIO13 27 I O LCD segment output 13 General purpose digital I O 13 SEG14 GPI014 28 IO LCD segment o
38. e precisely based on different MCLK OWR and line frequencies For the phase shift beyond the ranges in Table 7 the application code needs to calculate phase shift and set the delay by itself to make the phase compensation The maximum phase shift ranges that could be compensated are listed in table 8 Energy Monitor requires the OWR to be 4KHz with BR filter disabled or 8KHz with BR filter enabled Table 8 Phase Compensation Calibration Range 50 Hz 60 Hz MCLK OWR Range Step Size Range Step Size 256 kHz 4KHz 6 75 8 96 0 0703 8 10 10 76 0 0844 512 kHz 8KHz 6 703 8 854 0 0352 8 019 10 567 0 0422 Table 9 Maximum Phase Compensation Range 50 Hz 60 Hz MCLK OWR Range Range 256 kHz 4KHz 13 5 17 93 16 2 21 516 512 kHz 8KHz 6 703 8 854 8 019 10 567 6 2 Energy Pulse and 1 Hz RTC Output To support accuracy verification of energy measurement and RTC the CS7401xx I O pin 44 can be configured to provide the EPOUT or CLK1Hz signal When configured as EPOUT pin 44 generates pulses of variable frequency that directly corresponds to the power values mea sured by the power utilities component in Energy Monitor firmware EPOUT can output active reactive or apparent energy puls es The energy type polarity the maximum pulse rate and pulse width are configurable through the power utilities component in the Energy Mo
39. ents for the XIN pin are O to 1 8V 13 MCLK is sourced by the on chip oscillator DCLK is the CPU clock 14 Citizen CM415 or equivalent crystal DS728PP3 13 CS7401xx SWITCHING CHARACTERISTICS Min Max characteristics and specifications are guaranteed over all Recommended Operating Conditions e Typical characteristics and specifications are measured at nominal supply voltages and TA 25 C e VA 1 8 V 1 V VD 1 8 V 0 1 V GNDA GND 0 V All voltages with respect to O V Logic Levels Logic 0 0 V Logic 1 VD Parameter Symbol Min Typ Max Unit Rise Times tiise 1 0 us Note 15 Any Digital Output 50 ns Fall Times tall 1 0 us Note 15 Any Digital Output 50 ns Start up RTCLK Start up Time XTAL 32 768 kHz Note 16 tricos 0 3 S MCLK and DCLK Start up Time See Figure 6 tsysos 1 S Serial Port SSP Timing Serial Clock Frequency SPICLKO 2 MHz Serial Clock Pulse Widths Pulse Width High ty 200 ns Pulse Width Low to 200 ns SPIRXD Timing SPICSO Falling to SPICLKO Rising ts 50 T ms Data Setup Time Prior to SPICLKORising u so m Data Hold Time After SPICLKO Rising t5 100 ns SPITXD Timing ISPICSOFalingto SPITXD Driving t 20 50 ms SPICLKO Falling to New Data Bit hold time t 20 50 ns SPICS0 Rising to SPITXD Hi Z i tg 2 50 ns
40. g the ADCs FIFO interface filters power calcu lations algorithms and power management to detect brownout condition and manage low power operation The device driver layer contains a set of modules that implements the higher level functionality needed for managing a hardware block including reading and writing the flash memory the interrupt controller UARTS calibration settings partition energy partition analog front end AFE core RTC timers SSP and LCD In addition to the APIs the ROM code contains a full application profile allowing Evaluation Development and Manufacturing EDM capabilities over a UART port This ROM EDM profile allows access to the firmware metrology algorithms and device cal ibration during initial evaluation and also supports code download to the flash during development and manufacturing Early eval uation is available using the CDB7401xx LV customer demonstration board This coupled with a Windows based software tool CapturePlus II allows the user to calibrate and test the CS7401xx Please refer to the CDB7401xx LV data sheet for details on the CDB7410xx LV and the CapturePlus Il software Application zh Ext Flash SP Browno Compo nent Device Driver ROM Based Flash Based Figure 2 Firmware Architecture DS728PP3 5 gt CIRRUS LOGIC CS7401xx 3 PIN DESCRIPTION GPIO41 TXDO SIROUTO FLASH_LOCK n E x 538 og 2 cuiu Dn at Z E Oo 2288 2o29 9S S
41. h the BOOT pin high the SoC is in remapped state See Figure 12 ROM aliases Flash at 0x0000_0000 and Boot Monitor initiates the SoC boot sequence See 5 3 4 Boot Monitor on page 28 for detailed boot sequence 26 DS728PP3 CIRRUS LOGIC CANTA sz 5 3 2 5 SRAM Synchronous SRAM is used to provide single cycle read write memory The SRAM region is organized as 2k x 32 bits and is chosen to represent temporary data memory SRAM is used for temporary power calculation storage and for the dynamic stack heap areas The memory controller provides the interface between SRAM and the AHB Advanced High speed Bus The SRAM is located at ad dress 0x0400_0000 SRAM locations from 0x0400_0000 to 0x0400_00CF are reserved for Boot Monitor and Energy Monitor firmware Free SRAM for custom applications starts from 0x0400_00DO 5 3 2 6 FLASH and FLASH Interface The Flash memory is organized into pages of 2 kB The total Flash size is up to 128 kB and is connected to the ARM7 core via the Memory Controller and Flash Interface and the AHB Address data along with clock and control signals are passed to the Flash from the AHB Programming and erase function are configured and controlled via the internal Memory Controller and Flash Interface regis ters The Flash locations from 0x0001F800 to 0x0001FFF are reserved for calibration functions of Energy Monitor All other locations can be used to store user s a
42. hich is EM pin pin 35 The latched state of the EM pin is in bit 2 of the MEM_PROT register If the pin is high the process branches to the Flash based MRC user application If the pin is low then branches to the embedded ROM EDM profile Check for Signature This step checks if the custom application code loaded at Flash address 0x00000800 con tains a valid data signature of CRUS If the signature exists then the process steps to the next address location 0x00000804 and executes the loaded application code If the signature does not exist then the process re mains a loop Initialize Internal Oscillator This step initializes the internal 65 536 MHz oscillator This step must occur before using the UART Failure to perform this step causes the CS7401xx UART baud rate to deviate more than 5 from acceptable levels As a result the CS7401xx will be unable to communicate with other devices through the UART Initial UART Initialize the UARTO to 9600 baud 8 bits no parity and no stop bit Send Out Prompt Sends out a gt prompt so that a host computer can initiate ROM EDM profile commands through RS232 port ROM EDM Profile This step branches to the main routine in ROM EDM Profile DS728PP3 t ll ERE T mn CIRRUS LOGIC CS7401xx 5 3 5 JTAG Debug Interface The ARM7TDMI processor debug interface is based on IEEE std 1149 1 1990 Standard Test Access Port and Bound ary s
43. i gt CIRRUS LOGIC CS7401xx Energy Measurement SoC Description The CS7401xx energy measurement system on chip SoC de vice reduces the cost to implement advanced digital power meters for electrical utilities as well as enabling many other energy conser vation applications The 24 bit Delta Sigma AZ ADCs coupled with the on chip metrology code enable the highest quality power measurement available The 32 bit processor and targeted periph erals have the power to implement metrology advanced data man agement standards and communication protocols all in the same device The extensive software library enables quick and easy pro gram development Features Analog to Digital Converter Three Independent 24 bit Delta Sigma ADCs Selectable Sampling Rate 1 kHz 8 kHz FIFO for Buffered Data Collection Voltage and Current Sampled Simultaneously Third ADC can be used for Tamper Detection On chip Temperature Sensor Analog Front End Single ended or Differential Inputs Programmable Gain 1x 3x 6x 12x Supports 50 uQ Shunts 1 8V Reference Compensated to 10 ppm C Measurement ANSI C12 20 IEC 62053 22 Class 0 2 Accuracy Active Power Accuracy 0 1 Over 3000 1 Range Fast Phase Calibration up to 18 Range Wide Frequency Range 45 Hz to 70 Hz Supports Total and Fundamental Measurements for Active Reactive and Apparent Power e Microcontroller Subsystem ARM7TDMI 16 32 bit RISC CPU
44. l Recommended Operating Conditions Typical characteristics and specifications are measured at nominal supply voltages and TA 25 C VH 3 3 V 596 AGND DGND 0 V All voltages with respect to O V MCLK 256 kHz DCLK 4 096MHz Parameter Symbol Min Typ Max Unit Clock Characteristics XIN Frequency Tolerance Ty 25 C 20 ppm Digital Clock Frequency Note 13 DCLK 1 953 4096 32768 kHz Modulator Clock Frequency Note 13 MCLK 256 256 512 kHz XIN Crystal Characteristics Note 14 Frequency Temperature Coefficient frc 0 034 ppm C Motional Series Resistance O T4 25 C Ru 70 kQ Drive Level Ta 25 C DL 1 uw Shunt Capacitance Co 1 pF Load Capacitance C 12 5 pF Quality Factor Q 53000 EM Characteristics Using ROM based energy monitor metrology code Phase Compensation Range 9 9 d Output Word Rate OWR 1 8 kHz High pass Filter Corner Frequency 3 dB 0 5 Hz Input Output Characteristics High level Input Voltage VH 3 3V Vi VH 0 5 V Low level Input Voltage VH 3 3 V Vi 0 5 V High level Output Voltage VH 3 3V lout 2 mA Voy VH 1 0 V Low level Output Voltage VH 3 3V lut 2MA VoL 0 4 V Input Leakage Current lin 1 10 HA 3 state Leakage Current loz 10 HA Digital Output Pin Capacitance Cout 5 pF Notes 12 When using an external 32 768 kHz clock the input level requirem
45. lication code can be downloaded to the on chip flash memory which provides a Flash lock feature that ensures code will remain secure The ROM and flash programs are supported by 8 kB of on chip SRAM that is intended for temporary data storage but can also be used to execute code A special feature of the SoC is having a FIFO interface from the ADC to the processing subsystem reducing the interrupt overhead in acquiring data The CS7401xx s integrated peripherals reduce the overall system cost The 120 segment LCD interface eliminates the need for an exter nal LCD controller The synchronous serial port SSP allows the device to interface to many different high speed peripherals including non volatile memory SRAM etc Two UART ports allow communication to RS485 Infrared IR or other subsystems The internal real time clock RTC eliminates the need for an external RTC chip Other features include several timer counters a dedicated HW Energy Pulse output and GPIOs to interface with buttons switches and control signals Flexible control allows multiple functionality for each GPIO pin enabling custom configuration for different applications Power management is key in any system s design The device integrates a switching buck converter that efficiently provides a 1 8V internal supply from the external power supply that is very well regulated This provides a high level of immunity to power supply noise The device has an option for a battery mode
46. mum Input Range RMS Gain 400 mV 282 8 MVRMS 1 34x 200 mV 141 4 mVgys 3x Fully Differential 100 mV 70 7 MVRMS 6x 50 MVp 35 4 MVRMS 12x 200 mV 141 4 mVgys 1 34x 100 mV 70 7 MVRMS 3x Single Ended 50 mV 35 4 MVpms 6x For example the channel s PGA gain is set to 1 34x If the input signal is fully differential and pure sinusoid the maximum signal level will be 400 mVp or 282 8 mVrms which generates full scale ADC data output If the input signal is single ended the maxi mum signal level will be 200 mVp or 141 4 mVrms which generates half the full scale ADC data output To achieve the maximum input impedance the ADCs should be configured as single ended or differential mode according to the actual signal input con nection Figure 9 shows a typical fully differential connection for the current channel with a current transformer CT In this diagram Rit 470 ohms and Ci 33nF act as the simple RC anti alias filter that has about 30 dB attenuation at the sampling rate MCLK 256KHz DS728PP3 19 i CS7401xx CIRRUS LOGIC Line Current Ri 470 Current Transformer CT XXXI Y Y LL WODODLOODU LXX Figure 8 Typical Fully Differential Connection for Current Channel 5 1 2 ADC Measurements The CS7401xx AFE incorporates three oversampling delta sigma AX analog to digital converters ADCs The high fidelity 24 bit ADCs are identical The ADCs opera
47. ne the source of the interrupt It also reduces the interrupt latency because the extra banked registers that are available for FIQ interrupts may be used to maximum efficiency by preventing the need for a context save The IRQ interrupt controller uses a bit position for each interrupt source Bit positions are defined for software programmed interrupts communication channels timers counters real time clock and analog front end Bit O is unassigned in the IRQ controller so that it may share the same interrupt source as the FIQ controller All IRQ interrupt source inputs are active high and level sensitive A programmed interrupt register is provided to generate an interrupt under software control 5 3 3 1 Interrupt Latency The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer plus the time for the longest instruction to complete the longest instruction is an LDM which loads all the registers including the program counter PC plus the time for the data abort entry plus the time for FIQ entry At the end of this time the ARM7TDMI will be executing the instruction at Ox1C FIQ interrupt vector address The maximum total time is 50 processor cycles which is just over 1 5 uSec in a system using a continuous 32 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine f
48. nitor When configured as CLK1Hz pin 44 generates a fixed RTC 1 Hz reference clock This 1Hz clock can used to measure or verify the accuracy of the CS7401xx RTC DS728PP3 37 CIRRUS LOGIC 6 3 Typical Application Circuit Figure 20 below show a typical CS7401xx based single phase tampering detection CS7401xx power meter application circuit with the AIN3 channel used for ii MBRO520L MBRO520L 3 6 V d Power 0 1uF 10uF 3 0 V Supply VH VW VBAT VSC BE E AIN1P 10uH ps CS7401xx VD 32UF Ry Y QO 5 A LL ANN AIN1N VA 1uF 32 768 kHz XOUT VREF DI 10uF XIN VBG 4 1uF NL R Zo amp NW AIN2P RXDOM EE g SR PCI Ye Reurden Ri TXDO 29 E Modem po Y Y Reurden LC AMM AIN2N RXDlle 338 R SEE E TXD1 82 n R AN Te AIN3N SPICS gt gt i SPIRXD le SE Lh Serial 38 Device ey SPITXD 35 gt Ro ij SPICLK gt MN L AIN3P vH LCDBPO 3 Push ae it E Y SEGO SEG20 LCD Displa L gt play 7 VH LCDLVLO K LCD l LODLVL3 Level dal EPOUT AAN Y A rm x GNDA GNDD Y Figure 20 38 Typical Connection Diagram Single phase 2 wire direct connection power meter DS728PP3 lt e ERE _ lt c
49. o peak value of the sinusoidal voltage measured in mV that would need to be applied at the channel s inputs in order to cause the same digital sinusoidal output This voltage is then defined as Veq PSRR is then in dB PSRR 20 og 72 DS728PP3 150 Veq 5 6 7 See section 5 1 5 for a description of Active Standby Sleep and OFF modes 8 9 11 lt e ERE _ lt c C IRRUS LOGIC CS7401xx VOLTAGE REFERENCE Parameter Symbol Min Typ Max Unit Internal Reference Voltage VREF 1 7 1 8 1 9 V VREF Temperature Coefficient Note 10 Uncalibrated TCyrer 60 ppm C Factory Calibrated 20 ppm C External Reference Input Input Voltage Range VREF 1 8 V Input Capacitance 4 pF Input CVF Current 33 HA External Bandgap Reference Input Input Voltage Range VBG 1 27 V Input Capacitance 4 pF 2 HA Input Current Notes 10 The voltage at VREF is measured across the temperature range Device Flash has not been written From these measurements the following formula is used to calculate the VREF Temperature Coefficient ogee Pa Mr 1 2 0 10 VREF VREFAyG Tuax TMI 11 Specified at maximum recommended output of 1 yA source or sink 12 DS728PP3 NEN CS7401xx DIGITAL CHARACTERISTICS Min Max characteristics and specifications are guaranteed over al
50. or an arbitrary length of time This time can be reduced to 42 cycles if the LDM command is not used some compilers have an option to compile without using this command Another option is to run that part of the code in Thumb mode where the time is reduced to 22 cycles The minimum latency for FIQ or IRQ interrupts is five cycles which consists of the shortest time the request can take through the syn chronizer plus the time to enter the exception mode Note The ARM7TDMI will always be run in ARM 32 bit mode when in privileged modes i e when executing interrupt service routines DS728PP3 27 i gt CIRRUS LOGIC CS7401xx 5 3 4 Boot Monitor The Boot Monitor is part of the factory embedded firmware in ROM After the SoC comes out of reset with BOOT pin high the Boot Monitor starts to run and guide the boot sequence as follows 4 5 6 7 28 Reset Initialize ARM Vectors EM Pin High MRC Application EM Pin Low Check for RT Signature Initialize Internal Oscilator N di Com Jump to Flash Initailze P X 0x00000804 UART Send out Boot prompt s i ROM EDM Profile CEO Figure 13 CS7401xx Boot Sequence Initialize ARM Vectors All exception vectors except for reset jump to RAM This step initializes the exception vector table by initializing the code in RAM to the b instruction Check EM Pin Check Pin 35 w
51. p support for the core The EmbeddedICE module contains the break point and watchpoint registers which allow code to be halted for debugging purposes These registers are controlled through the JTAG test port When a breakpoint or watchpoint is encountered the processor halts and enters the debug state Once in the debug state the processor registers may be inspected as well as the embedded Flash SRAM and MMRs 5 3 1 4 Exceptions ARM supports five types of exceptions and a privileged processing mode for each type The five type of exceptions are normal interrupt or IRQ provided to service general purpose interrupt handling of internal and external events fast interrupt or FIQ provided to service data transfer or communication with low latency FIQ has priority over IRQ memory abort attempted execution of an undefined instruction software interrupt SWI instruction which can be used to make a call to an operating system Typically the programmer will define interrupts as IRQ but for a higher priority interrupt the programmer can define the interrupt as FIQ for faster response time 24 DS728PP3 i gt CIRRUS LOGIC CS7401xx NN 5 3 1 5 ARM Registers The ARM7TDMI processor has a total of 37 registers of which 31 are general purpose registers and six are status registers Each operating mode has dedicated banked registers When writing user level programs 15 general purpose 32 bit registers rO to r14
52. pplication code and data To protect the customer s application code the Flash memory can be locked either by hardware pin55 Flash Lock or by software Once the flash is locked the Flash memory can not be read through JTAG Only a mass erase can clear the Flash lock state Refer to the MEMORY table on page 17 for the timing specifications for the Flash memory 5 3 3 Interrupt Controller The interrupt controller provides a simple software interface to the interrupt system The interrupt controller is compliant with the ARM Reference Peripheral Specification RPS The mapping of the interrupt controller registers conforms to the RPS with a base address of Ox1890 0000 In the CS7401xx system two levels of interrupts are available FIQ Fast Interrupt Request for fast low latency interrupt handling IRQ Interrupt Request for more general interrupts Separate interrupt controllers are used for FIQ and IRQ The difference is that only a single bit position is defined for FIQ which is in tended for use by a single interrupt source while 32 bits are available in the IRQ controller A number of methods may be used to extend the IRQ interrupt controller if more than 32 interrupt sources are required The CPU utilizes a single source FIQ which is driven by the AFE circuit This provides a true low latency interrupt because a single source ensures that the interrupt service routine may be executed directly without the need to determi
53. racy of the fundamental reactive power measurement which mea sures the fundamental line frequency 45 Hz to 70 Hz applies an extremely narrow band filter to the voltage and current then calculates the phase angle all with accuracy similar to that of the active power calculations Being available in firmware this algorithm allows for quick and accurate application development with proven metrology code While the Cirrus Logic power measurement algorithm is always available in ROM it can be partially or totally customized with flash based code This open approach to metrology is one of the unique features that is enabled by having a single 32 bit RISC processing element In addition to the metrology the processor has enough power to implement standards based data management and secure com munications protocols Metrology typically requires much less than 4 MHz of processor bandwidth The capabilities of the pro cessing systems to dynamically change processor frequency allows the application to boost the processing power upon demand For example when a communication event occurs the processor can change the system to 32 MHz operation service the com munication request and go back to 4MHz operation minimizing the average power consumption The APIs are layered into a component layer device driver layer and Hardware Abstraction Layer HAL The component layer provides support for saving restoring system settings rapid calibration handlin
54. rammable brown out detec tion and low battery detection The supervisory circuit guarantee the RESET assertion to protect the SoC during power up and power down The battery mode detection brown out detection and low battery detection generate interrupts which can be used by software to initiate specific power down sequence to put the SoC into different power modes for power saving and proper op eration Typically power modes for the CS7401xx include Active Standby Sleep and Off Each mode is defined in Table 5 Table 5 Power Modes Power Mode Description Active All circuitry is operational The Buck regulator is enabled Standby The linear regulator is enabled The internal oscillator bandgap ADCs and temperature sensor are powered down The digital sections including the ARM7 are running using a slow clock from RTC oscillator The speed of the digital clock is dependent upon the settings of the Clock Divider Control and Enable register Sleep The linear regulator is enabled All circuits are shut down or disabled except the RTC This mode can only be exited by applying a low to high transition on GPIO30 pin 44 or by a chip reset Off RAM retention only The linear regulator is enabled All circuits are shut down or disabled including internal oscillator and RTC oscillator This mode can only be exited by a chip reset 5 2 1 On chip Voltage Regulators The CS7401xx has two voltage regulators
55. re sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information including use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROP ERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITI CAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDE
56. red as either a free running or a periodic timer The timer is loaded by writing to the load register and then if enabled the timer will begin counting down After reaching a zero count an interrupt will be generated The interrupt is cleared by writing to the clear register If the timer is operating in free running mode it continues to count down from its maximum value after reaching a zero count If the timer is operating in periodic mode then the timer will reload from the load register after reaching a zero count and continue to count down In this mode the timer will effectively generate a periodic interrupt The timer mode is selected by a bit in the control register In addition to the enable bit in the control register the two 32 bit timers can also be enabled disabled by pin inputs TEO and TE1 One of the 32 bit timers can be used as a watchdog timer 5 4 6 GPIOS Pin14 to pin 55 of CS7401xx are functionality multiplexed input output pins They can be configured individually as the input out put interfaces for the embedded peripherals such as LCD driver SSP port and UARTS etc or as general purpose digital in put outputs GPIOs When configured as input GPIOs these pins also have interrupt generation capability The interrupt properties of each GPIO pin are individually configurable Because some of the I O pins have special functionality after reset and by default the following concerns must be taken carefully when using CS7401xx
57. s Bank size and cycle times are fixed for the ROM and SRAM but can be configured for Flash The memory types are described later 5 3 2 1 Memory Remap The CS7401xx is a small embedded implementation with memory constraints However a hardware solution is provided which allows a portion of ROM that overlays Flash to be remapped As on all ARM based processors the boot strap loader BSL image starts execution at address 0x0000 0000 The first instruction executed loads the program counter with the reset vector address stored at an initial offset of usually OX0000 0020 Execution then continues at the reset vector address The memory map has two states Normal selected when BOOT pin pin 50 is low at reset Remapped selected when the BOOT pin pin 50 is high at reset For energy meter applications pin 50 BOOT should be pulled high 5 3 2 2 I O peripherals overview The CPU utilizes a standard memory mapped I O approach to perform I O functions The base address of all I O memory mapped registers MMRs is factory defined starting at address 0x1800 0000 The SoC architecture supports embedded peripherals in two areas Advanced Peripheral Bus APB Advanced High speed Bus AHB The AHB peripherals implement a Clock Generator and System Controller which are connected to the AMBA AHB Other em bedded peripherals such as interrupt controller timers counters LCD driver RTC UART SSP and GPIOs are connected to the APB DS
58. s APB which is optimized for minimal power consumption and reduced interface complexity to support peripheral functions APB is used in con junction with the standard AMBA AHB version of the on chip system bus for high system performance 5 4 1 Clock Generation amp Real Time Clock RTC All clocks on the CS7401xx are generated from a single low cost 32 768 kHz crystal To further reduce cost the 22 pF capacitors typically needed for crystal operation are integrated into the device This oscillator circuit drives the fast clock generation RTC subsystem and can drive the ARM process for ultra low power operation The real time clock RTC subsystem is driven from the 32 kHz oscillator This clock is then divided down to a 1 Hz clock to op erate a digital counter that can be used to generate time and date information In many cases the low cost 32 768 kHz crystal oscillator may not meet the accuracy requirements of the application In this case an external 16 77721 MHz clock can be used to calibrate the RTC to produce a highly accurate 1 Hz clock Once calibrated the RTC block will always generate an accurate clock with the crystal Other than counting on the 1 Hz clock the RTC can also generate an interrupt The real time clock portion of the circuit operates whenever power is applied and the 32 kHz input clock is running On on chip relaxation oscillator is used to generate a 65 536 MHz internal high speed clock This clock feeds both
59. s 32 kB 64 kB 128 kB respectively Basic to all energy measurement applications is the ability to acquire the voltage and current data with a high degree of precision The CS7401xx family of products is built around three independent high precision ADCs that concurrently acquire both voltage and current information at a data rate high enough to measure up to the 30 harmonic A third channel is available for 3 wire measurement neutral current measurement and for anti tampering applications The sampled data is processed through a pipeline of computations which re sults in a 24 bit quantity available at 1 2 4 or 8 kHz The power behind this advanced system is a high performance 32 bit embedded ARM7 based subsystem capable of executing the most demanding standards The large logical address space allows ease of code development The ARM7TDMI core features a hard ware multiplier 31 registers a JTAG debug port EmbeddedICE module flexible interrupt mechanism and an optional 16 bit Thumb instruction set The CPU can run from Flash ROM or RAM The device includes on chip debug circuitry that provides non intrusive full speed in circuit debugging of the device installed in the end application The 32 bit processing subsystem includes the ROM RAM on chip flash memory and FIFO interface to the ADC The 32 kB of ROM contains a profile for initial code download along with many APIs see the Firmware API Description for more details App
60. set Calibration Power offset calibration compensates for erroneous power sources resident in the metering system not originating from the power line Residual power offsets occur due to crosstalk between current and voltage channels ADC channels 1 2 and 3 or due to ripple within the power meter or the CS7401xx SoC power supply Positive or negative offsets indicate crosstalk coupling either in phase or out of phase with the applied voltage input Power offset calibration is performed without a load connected current channel Power offset calibration is one of the calibration components provided by the Energy Monitor firmware 6 1 5 Phase Compensation Calibration Phase compensation calibration is implemented by setting the different time delays on both voltage and current ADC paths CS7401xx ADC hardware provides up to 63 samples delay 1 hardware sample delay 1 MCLK on voltage channel Energy Monitor can provides a software delay of up to 3 samples 1 software sample delay 1 OWR on both voltage and current chan nel The phase calibration component calculates the phase shift between the voltage channel and the current channel using wavelet technology and translates the phase shift into the number of samples of delay needed on the voltage and current ADC paths The actual compensated phase shift in degrees is also depended on the line frequency Table 7 lists the phase ranges and step sizes that the phase calibration component can calibrat
61. tage Threshold V4 1 7V DS728PP3 CIRRUS LOGIC CS7401xx 5 FUNCTIONAL DESCRIPTION 5 1 Analog Front End The CS7401xx Analog Front End AFE incorporates three fully differential analog input channels Inputs AINx are designed for voltage and or current channel inputs Each channel has a highly integrated 24 bit ADC designed using multi bit delta sigma techniques The ADCs operate at an over sample rate of programmable 32 64 128 or 256 times the system output word rate OWR The different clock rates maximize power savings while maintaining high performance The multiple ADC structure samples the voltage and current inputs simulta neously The ADC operates in one of two clock rates 256 kHz and 512 kHz The output word rates supported can be from 1 kHz to 8 kHz For power meter applications the typical output word rate is 4 kHz The AFE is tightly integrated within the SoC with configuration registers status registers and ADC data interface mapped into the CPU 1 0 memory 5 1 1 Analog Channels To accommodate different sensing elements each channel incorporates a Programmable Gain Amplifier PGA with four pro grammable input gains Table3 illustrates the ADC channels four gain selections and corresponding maximum input signal level The maximum level of single ended signal is half of that of fully differential signal Table 4 Channel PGA Configuration Input Connection Type Maxi
62. tal I O 31 SPI Receive Data LCD segment output 23 GPIO32 SPICS SEG24 46 IO General purpose digital I O 32 SPI Chip Select LCD segment output 24 RI GPIO33 SPICLK SEG25 47 I O General purpose digital I O 33 SPI Clock LCD segment output 25 GPIO34 SPITXD SEG26 48 I O General purpose digital I O 34 SPI Transmit Data LCD segment output 26 DS728PP3 CS7401xx Table 1 CS7401xx Pin Functions Continued GPIO35 SEG27 DSRO 49 I O General purpose digital I O 35 LCD segment output 27 DSR 0 DSR 1 DSR1 GPIO36 SEG28 DCDO0 50 I O General purpose digital I O 36 LCD segment output 28 DCD 0 DCD 1 Boot mode select from DCD1 BOOT FLASH or ROM Should be pulled high for energy meter applications GPIO37 SEG29 CTSO 51 IO General purpose digital I O 37 LCD segment output 29 CTS 0 CTS 1 RCLK XTAL Calibration CTS1 RCLK clock GPIO38 TXD1 TEO 52 IO General purpose digital I O 38 TXD 1 Timer Enable O DCLK Output SIROUT1 DCLK SIROUT1 GPIO39 RXD1 SIRIN1 53 I O General purpose digital I O 39 RXD 1 SIRIN1 GPIOA40 RXDO SIRINO 54 I O General purpose digital I O 40 RXD O SIRINO GPIO41 TXDO SIROUTO 55 I O General purpose digital I O 41 TXD 0 SIROUTO FLASH LOCK TDO 56 O Test data output of Test Debug JTAG Port TDI 57 Test data input of Test Debug JTAG Port TMS 58 Test mode signal input of Test Debug JTAG Port TCK 59 Test clock input of Test Debug JTA
63. te with analog supply voltage VA of 1 8V and provide an output word rate of up to 8k samples per second The AFE ADCs can be powered down individually to save power consumption A 3 d order feed forward multi bit delta sigma modulator is the core of the AFE A D converters The multi bit modulator archi tecture facilitates ultra low power operation The decimation ratio DR of the ADCs is 32 64 128 256 programmable The ADCS perform instantaneous measurements at an output word rate OWR of MCLK OWR DR Therefore with MCLK 256KHz and DR 64 the maximum OWR is 4k samples per second and the ADC frequency bandwidth is 2 kHz At each instantaneous measurement the 24 bit sample is stored in the AFE FIFO When the data in the FIFO reaches a user determined level an interrupt is generated to the CPU Handling this AFE interrupt is the main responsibility of the meter pre pro cess component in Energy Monitor firmware The meter pre process component offers a variety of filters and other services to manipulate the samples acquired by the AFE After the meter pre process the power utilities component in the Energy Monitor firmware provides functions to calculate both basic and advanced power parameters such as RMS voltage current active power apparent power reactive power power fac tor etc 5 1 3 Voltage Reference A high precision low drift 1 8 V bandgap reference is provided on chip The internal reference also appears on the VREF
64. the program counter r15 and the current pro gram status register CPSR are usable The remaining registers are used only for system level programming and for exception handling When an exception occurs some of the standard registers are replaced with registers specific to the exception mode All excep tion modes have replacement banked registers for the stack pointer r13 and the link register r14 as represented in Figure 12 The fast interrupt mode has more registers 8 to 12 for fast interrupt processing so that the interrupt processing can begin with out the need to save or restore these registers and thus save critical time in the interrupt handling process 5 3 2 Memory System The CS7401xx SoC is constructed so that the complete memory system is on chip On chip memory can support zero wait state access speeds and provides better power efficiency and reduced electromagnetic interference The CS7401xx on chip SRAM is preferred to cache memory for a number of reasons it is simpler cheaper uses less power and has a more deterministic be havior The memory controller and Flash interface enable the ARM7 to access RAM Flash and ROM via the AHB Advanced High speed Bus The CPU is configured with the types of memory shown in Table 6 Memory Types and Sizes Memory Type Size Address ROM 32 kB 0x0800 0000 SRAM 8 kB Ox0400 0000 FLASH 32 kB 64 kB or 128 kB Ox0000 0000 Table 6 Memory Types and Size
65. utput 14 General purpose digital I O 14 SEG15 GPIO15 29 I O LCD segment output 15 General purpose digital I O 15 SEG16 GPIO16 30 I O LCD segment output 16 General purpose digital I O 16 SEG17 GPIO17 31 I O LCD segment output 17 General purpose digital I O 17 SEG18 GPIO18 32 I O LCD segment output 18 General purpose digital I O 18 SEG19 GPIO19 33 I O LCD segment output 19 General purpose digital I O 19 SEG20 GPIO20 34 I O LCD segment output 20 General purpose digital I O 20 SEG21 GPIO21 35 I O LCD segment output 21 General purpose digital I O 21 Energy Meter EM mode select LCDBPO GPIO22 36 I O LCD backplane output O General purpose digital I O 22 LCDBP1 GPIO23 37 I O LCD backplane output 1 General purpose digital I O 23 LCDBP2 GPIO24 38 I O LCD backplane output 2 General purpose digital I O 24 LCDBP3 GPIO25 39 I O LCD backplane output 3 General purpose digital I O 25 LCDLVO GPIO26 40 IO Analog LCD voltage Level 0 lowest General purpose digital I O 26 LCDLV1 GPIO27 41 I O Analog LCD voltage level 1 General purpose digital I O 27 LCDLV2 GPIO28 42 I O Analog LCD voltage level 2 General purpose digital I O 28 LCDLV3 GPIO29 43 I O Analog LCD voltage level 3 highest General purpose digital I O 29 EPOUT GPIO30 TE1 44 I O Energy Pulse output General purpose digital I O 30 Timer Enable 1 LCD segment output SEG22 22 RTC generated reference clock CLK1HZ Sleep Recovery GPIO31 SPIRXD SEG23 45 IO General purpose digi

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