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MICROCHIP dsPIC30F1010/202X Data Sheet

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1. dsPIC30F2020 S AN5S CMP2D CMP3B CN7 RB5 PWMSL RE4 Vss 21 PWMS3H RE5 AN6 CMP3C CMP4A OSC1 CLKI RB6 20 VDD AN7 CMP3D CMP4B OSC2 CLKO RB7 10 19 Vss PGD1 EMUD1 PWM4H T2CK U1ATX CN1 RE7 11 18 PGC EMUC SDI1 SDA U1RX RF7 PGC1 EMUC1 EXTREF PWMAL T1CK U1ARX CNO RE6 12 17 PGD EMUD SDO 1 SCL U1TX RF8 VDD 13 16 SFLT2 INTO OCFLTA RA9 PGD2 EMUD2 SCK1 SFLT3 OC2 INT2 RF6 14 15 PGC2 EMUC2 0C1 SFLT1 IC1 INT1 RDO 28 Pin QFN S AN1 CMP1B CN3 RB1 ANO CMP1A CN2 RBO MCLR AVDD AVSS PWM1L REO PWM1H RE1 28 27 26 25 242322 AN2 CMP1C CMP2A CN4 RB2 e PWM2L RE2 AN3 CMP1D CMP2B CN5 RB3 PWM2H RE3 AN4 CMP2C CMP3A CN6 RB4 19 PWM3L RE4 AN5 CMP2D CMP3B CN7 RB5 dsPIC30F2020 PWM3H RE5 Vss VDD AN6 CMP3C CMP4A OSC1 CLKI RB6 Vss AN7 CMP3D CMP4B OSC2 CLKO RB7 PGC EMUC SDI1 SDA U1RX RF7 1 9 1011121314 PGD1 EMUD1 PWMAH T2CK U1ATX CN1 RE7 VDD PGD2 EMUD2 SCK1 SFLT3 OC2 INT2 RF6 PGC2 EMUC2 OC1 SFLT1 IC1 INT1 RDO SFLT2 INTO OCFLTA RA9 PGD EMUD SDO1 SCL U1TX RF8 PGC1 EMUC1 EXTREF PWMAL T1CK U1ARX CNO RE6 DS70178C page 4 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X Pin Diagrams 44 PIN QFN PGC EMUC SDMH RF7 SYNCO SS1 RF15 SFLT3 RA10 SFLT4 RA11 SDA RG3 Vss VDD PWM3H RE5 PWMSL RE4 PWM2H RE3 PWM2L RE2 1 2 3 4 5 6 7 8 9 E A PGC1 EMUC1 PWMAL T1CK U1ARX CNO RE6 PGD1 EMUD1 PWMAH T2C
2. Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated AC CHARACTERISTICS ae temperature aie lt TA lt 85 for Industrial 40 C lt TA 125 C for Extended Symbol Characteristic 1 Max Units Conditions IM10 TLO SCL Clock Low Time 100 kHz mode Tcv 2 BRG 1 us 400 kHz mode Tcv 2 BRG 1 us 1 MHz mode Tcv 2 BRG 1 us IM11 THI SCL Clock High Time 100 kHz mode Tcv 2 BRG 1 us 400 kHz mode Tcv 2 BRG 1 us 1 MHz mode Tcv 2 BRG 1 us IM20 TF scL SDA and 100 kHz mode 300 ns CB is specified to be Fall Time 400 kHz mode 20 0 1 300 ns from 10 to 400 pF 1 MHz mode 100 ns IM21 TR scL SDA 100 kHz mode 1000 ns CB is specified to be Rise Time 400 kHz mode 20 0 1 300 ns 10 to 400 pF 1 MHz mode 300 ns IM25 Tsu bpAT Data Input 100 kHz mode 250 ns Setup Time 400 kHz mode 100 ns 1 MHz mode TBD ns IM26 THD DAT Data Input 100 kHz mode 0 ns Hold Time 400 kHz mode 0 0 9 Hs 1 MHz mode TBD ns IM30 TSU STA Start Condition 100 kHz mode Tcv 2 BRG 1 us Only relevant for Setup Time 400 kHz mode Tcv 2 BRG 1 m us repeated Start 1 MHz mode Tcv 2 BRG 1 ree 1 THD STA Start Condition 100 kHz mode Tcy 2 BRG
3. TABLE 17 1 ANALOG COMPARATOR CONTROL REGISTER MAP FileName ADR Biti5 Biti4 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit 2 Bit 1 Bito All Resets CMPCON1 04C0 CMPON CMPSIDL INSEL lt 1 0 gt EXTREF cMPSTAT CMPPOL RANGE 0000 CMPDAC1 04C2 CMREF lt 9 0 gt 0000 CMPCON2 04C4 CMPON CMPSIDL INSEL lt 1 0 gt EXTREF CMPSTAT CMPPOL RANGE 0000 CMPDAC2 04C6 CMREF lt 9 0 gt 0000 CMPCON3 04C8 CMPON CMPSIDL INSEL lt 1 0 gt EXTREF CMPPOL RANGE 0000 CMPDAC3 04CA CMREF lt 9 0 gt 0000 CMPCON4 04CC CMPON CMPSIDL INSEL lt 1 0 gt EXTREF CMPSTAT CMPPOL RANGE 0000 CMPDAC4 04 CMREF lt 9 0 gt 0000 0 0101 3062145 dsPIC30F1010 202X NOTES LE M O S X s J H M dn H n S DS70178C page 196 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X 18 0 SYSTEM INTEGRATION Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descrip
4. REGISTER 5 7 IEC1 INTERRUPT ENABLE CONTROL REGISTER 1 R W 0 R W 0 R W 0 U 0 R W 0 U 0 U 0 U 0 ACSIE AC2IE 1 bit 15 bit 8 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PWMAIE PWMSIE PWM2IE PWM tIE PSEMIE INT2IE INT1IE bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Analog Comparator 3 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled AC2IE Analog Comparator 2 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled Analog Comparator 1 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled Unimplemented Read as 0 CNIE Input Change Notification Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled Unimplemented Read as 0 PWMAIE Pulse Width Modulation Generator 4 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled PWMSIE Pulse Width Modulation Generator 3 Interrupt Enable bit 1 Interrupt request enabled 0 Interrupt request not enabled PWM2IE Pulse Width Modulation Generator 2 Interrupt En
5. 171 A D Convert Pair Control Register 0 ADCPCO p A D Convert Pair Control Register 1 ADCPCH1 A D Convert Pair Control Register 2 ADCPC2 A D Port Configuration Register ADPCFG A D Status Register AC Characteristics essen Load Conditions x AC Temperature and Voltage Specifications 240 ADC Register Address Generator Units Alternate Vector Table Analog Comparator Control Register Map 195 Assembler MPASM Assembler 228 Automatic Clock Stretch sess 156 During 10 bit Addressing STREN 1 During 7 bit Addressing STREN 1 Receive Transmit Mode eene 156 B Band Gap Start up Time 248 Timing Characteristics 24 44222 248 Barrel Shifter Baud Rate Error Calculation BRGH 0 162 Bit Reversed Addressing 45 Example 10 nnne nnne nnne 45 Implementation 40440 45 Modifier Values
6. Gig Symbol Characteristic Min Typ Max Units Conditions TC10 TtxH TxCK High Time Synchronous 0 5 20 ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous 0 5 20 ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous Tcv 10 ns N prescale no prescaler value 1 8 64 Synchronous Greater of 256 with prescaler 20 ns or Tcv 40 N TC20 TCKEXTMRL Delay from External TxCK Clock 0 5 1 5 Edge to Timer Increment TCY DS70178C page 250 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 21 7 INPUT CAPTURE CAPx TIMING CHARACTERISTICS ei 5 Note Refer to Figure 21 1 for load conditions TABLE 21 23 INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated Operating temperature 40 C lt TA lt 85 C for Industrial 40 C lt TA 125 C for Extended AC CHARACTERISTICS ta Symbol Characteristic Min Max Units Conditions IC10 TccL Input Low Time No Prescaler 0 5 Tcv 20 ns With Prescaler 10 ns IC11 TccH ICx Input High Time No Prescaler 0 5 Tcv 20 ns With Prescaler 10 ns 15 TccP ICx Input Period 2 TCY 40 ns N prescale value 1 4 16 Note 1 These parameters are
7. TABLE 1 3 PINOUT I O DESCRIPTIONS FOR dsPIC30F2023 CONTINUED Pin Name pin Butter Description Type Type PGD ST In Circuit Serial Programming data input output pin PGC ST In Circuit Serial Programming clock input pin PGD1 ST In Circuit Serial Programming data input output pin 1 PGC1 5 In Circuit Serial Programming clock input pin 1 PGD2 ST In Circuit Serial Programming data input output pin 2 PGC2 5 In Circuit Serial Programming clock input pin 2 RA8 RA11 ST PORTA is a bidirectional I O port RBO RB11 ST PORTB is a bidirectional I O port RDO RD1 ST PORTD is a bidirectional port REO RE7 y o ST PORTE is a bidirectional port RF2 RF3 ST PORTF is a bidirectional I O port RF6 RF8 RF14 RF15 RG2 RG3 ST PORTG is a bidirectional I O port SCK1 y o ST Synchronous serial clock input output for SPI 1 5011 ST SPI 1 Data In 5001 SPI 1 Data Out SS1 5 SPI 1 Slave Synchronization SCL y o ST Synchronous serial clock input output for 2 y o ST Synchronous serial data input output for PG T1CK 5 Timer1 external clock input T2CK 5 Timer2 external clock input U1RX ST UART1 Receive U1TX UART1 Transmit U1ARX 5 Alternate UART1 Receive U1ATX Alternate UART1 Transmit CMP1A Analog Comparator 1 Channel A CMP1B Analog 1 Channel CMP1C Analog
8. 262 Bus Start Stop Bits Timing Characteristics Master Mode nenne Slave MOdGe err eer rends General Call Address Support 2 47 4 47 A IPMI Support te tt e retener ea Master Operation esee Master Support 4 0 Operating Function Description 55 Operation During CPU Sleep and Idle Modes 158 Pin Configuration sese 153 Programmer s Model 153 Registers 153 Sl pe Control ec er ar e nore tun 157 Software Controlled Clock Stretching STREN 1 156 2 Register Idle Current IIDLE In Circuit In Circuit Serial Programming ICSP Initialization Condition for RCON Register Case 1 Initialization Condition for RCON Register Case 2 213 Input Capture CAPX Timing Characteristics 251 Input Capture 1 Input Capture Simple Capture Event Mode zi Sleep and Idle Input Capture Register
9. 105 Output Compare Sleep Mode Operation 103 P Packaging Information Marking iere esee eon 267 PICSTART Plus Development Programmer 230 Pinout Descriptions s PLL Clock Timing Specifications 242 POR See Power on Reset Port Register Map dsPIC30F1010 2020 79 Port Register Map dsPIC30F20293 suse 80 Port Write Read Example 78 Power Supply PWM sese 107 Power Supply PWM Module Timing Requirements see 253 Power Supply PWM Register Map 142 Power Down Current IPD 237 Power on Reset POR 4197 Oscillator Start up Timer OST 197 Power up Timer PWRT 197 ce a e ete Sleep Power Saving Modes Sleep and Idle 197 Power up Timer Timing Characteristics 420422221 22 246 Timing Requirements 247 Primary Time Base Register PTPER 111 Product Identification System 283 Program Address Space 29 CONSIUCTION uerit ione rri et P exeo re ted 30 Data Access from Program Memory Us
10. 273 Customer 273 D Data Access from Program Memory Using Program Space Visibility esses 32 Data Accumulators and Adder Subtracter ds Data Space Write 27 Overflow and Saturation 25 Round Logic 2 26 Write Back 26 Data Address Space 93 Alignment 2 36 Alignment Figure sse 2 36 MCU and DSP Class Instructions Memory Map Near Data Software Stack Width e e ed DC Characteristics Pin Input Specifications 238 Pin Output Specifications 239 idle Current IDEE oen c rte 235 Operating Current I 2006 Microchip Technology Inc Preliminary DS70178C page 277 dsPIC30F1010 202X E Electrical 231 Relationship Between Device and SPI Clock Speed 5 trenes 148 UART Baud Rate with BRGH 0 162 UART Baud Rate with BRGH 1 162 cuc 8 Extern
11. FIGURE 3 1 PROGRAM SPACE MEMORY MAP FOR dsPIC30F1010 202X Reset GOTO Instruction 000000 Reset Target Address 000002 A Reserved 000004 Ext Osc Fail Trap Address Error Trap Stack Error Trap Arithmetic Warn Trap Reserved Vector Tables Reserved Reserved Vector 0 000014 Vector 1 Vector 52 Vector 53 00007E Alternate Vector Table 000080 Y 0000FE 5 g 000100 User Flash 9 2 4K instructions 001FFE 002000 Reserved Read o s Y 7FFFFE 800000 Reserved gt gt 8005 5 9 8005C0 UNITID 32 instr 8005FE 800600 8 Reserved F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE FF0000 DEVID 5 FFFFFE 2006 Microchip Technology Inc Preliminary DS70178C page 29 dsPIC30F1010 202X TABLE 3 1 PROGRAM SPACE ADDRESS CONSTRUCTION Access Type Access Program Space Address Space lt 23 gt lt 22 16 gt lt 15 gt lt 14 1 gt lt 0 gt Instruction Access User 0 lt 22 1 gt 0 TBLRD TBLW User TBLPAG lt 7 0 gt Data EA lt 15 0 gt TBLPAG lt 7 gt 0 TBLRD TBLW Configuration TBLPAG lt 7 0 gt Data EA lt 15 0 gt TBLPAG lt 7 gt 1 User 0 PSVPAG lt 7 0 gt Data EA lt 14 0 gt Program Space Visibility FIGURE 3 2 DATA AC
12. REGISTER 5 2 INTCON2 INTERRUPT CONTROL REGISTER 2 R W 0 R 0 U 0 U 0 U 0 U 0 U 0 U 0 ALTIVT DISI bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 INT2EP bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 ALTIVT Enable Alternate Interrupt Vector Table bit 1 Use alternate vector table 0 Use standard default vector table bit 14 DISI DISI Instruction Status bit 1 DIST instruction is active 0 DIST instruction is not active bit 13 3 Unimplemented Read as 0 bit 2 INT2EP External Interrupt 2 Edge Detect Polarity Select bit 1 Interrupt on negative edge 0 Interrupt on positive edge bit 1 INT1EP External Interrupt 1 Edge Detect Polarity Select bit 1 Interrupt on negative edge 0 Interrupt on positive edge bit O INTOEP External Interrupt 0 Edge Detect Polarity Select bit 1 Interrupt on negative edge 0 Interrupt on positive edge DS70178C page 54 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X REGISTER 5 3 IFS0 INTERRUPT FLAG STATUS REGISTER 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPHIF bit 15 bit 8 R W 0 R W 0 R W 0 U 0 R W 0 R W 0 R
13. 163 Transmitting 8 bit Data 163 9 bit Data Mode 5 rot re een 163 Break and Sync 163 UART1 Mode Register U1MODE UART1 Register Map esee UART1 Status and Control Register U1STA 166 Unit IB EOCaliOris 515 riri nre tener ere 197 Universal Asynchronous Receiver Transmitter See UART W Wake up from 197 Wake up from Sleep and 51 Watchdog Timer Timing Characteristics 44 222241 246 Timing Requirements eene 247 Watchdog Timer WDT Enabling and 214 Operation WWW Address WWW On Line 8 2006 Microchip Technology Inc Preliminary DS70178C page 281 dsPIC30F1010 202X NOTES SL E a M HY a DS70178C page 282 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office dsPIC30F2020AT 30 1 SO ES Jl IL IL ILI l ILI Ju Custom ID 3 digits or Trademark Engineering Sample ES
14. m Typical Max Units Conditions Operating Current Ipp 2 DC28a 96 116 mA 25 C 3 3V DC28b 97 116 mA 85 C DC28d 157 188 mA 25 C EC 20 MIPS PLL enabled DC28e 158 189 mA 85 C 5V DE28f 159 191 mA 125 C DC29d 227 273 mA 25 C 5V EC 30 MIPS PLL bled DC29e 228 273 mA 85 C E Note 1 Data Typical column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements are as follows All I O pins are configured as Outputs and pulled to Vss MCLR VDD WDT and FSCM are disabled CPU SRAM Program Memory and Data Memory are operational No peripheral modules are operating DS70178C page 234 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X TABLE 21 6 DC CHARACTERISTICS IDLE CURRENT Standard Operating Conditions 3 3V and 5 0V 10 unless otherwise stated DO CHARACTERISTICS obti temperature Vo lt TA lt 85 C for Industrial 40 C lt TA lt 125 C for Extended Typical Max Units Conditi
15. 1 Channel C CMP1D Analog 1 Channel D CMP2A Analog Comparator 2 Channel A CMP2B Analog Comparator 2 Channel CMP2C Analog Comparator 2 Channel C CMP2D Analog Comparator 2 Channel D CMP3A Analog Comparator 3 Channel A CMP3B Analog Comparator Channel CMP3C Analog Comparator 3 Channel C CMP3D Analog Comparator 3 Channel D CMP4A Analog Comparator 4 Channel A CMP4B Analog Comparator 4 Channel CMP4C Analog Comparator 4 Channel C CMP4D Analog Comparator 4 Channel D CNO CN7 5 Input Change notification inputs Can be software programmed for internal weak pull ups on all inputs VDD P Positive supply for logic and pins Vss P Ground reference for logic and pins EXTREF Analog External reference to Comparator DAC Legend CMOS CMOS compatible input or output Analog Analog input ST Schmitt Trigger input with CMOS levels O Output Input P Power DS70178C page 18 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 2 0 CPU ARCHITECTURE OVERVIEW Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual 0570046 For more information on the devi
16. Typically in the converter application an energy stor age inductor is charged with current while the PWM signal is asserted and the inductor current is dis charged by the load when the PWM signal is deas serted In this application of current reset PWM an external current measurement circuit determines when the inductor is discharged and then generates a signal that the PWM module uses to reset the time base counter In Current Reset mode complementary outputs are available 12 4 9 INDEPENDENT TIME BASE PWM Independent Time Base PWM as shown in Figure 12 11 is often used when the dsPIC DSC is controlling different power converter subcircuits such as the Power Factor Correction circuit which may use 100 kHz PWM and the full bridge forward converter section may use 250 kHz PWM FIGURE 12 11 INDEPENDENT TIME BASE PWM Duty Cycle e s PWM1H P Period 1 PWM2H Duty Cycle o 2 PWM3H Duty Cycle i Period 3 PWMA4H Duty Cycle M Period 4 4 gt Note With independent time bases PWM signals are no longer phase related to each other 2006 Microchip Technology Inc Preliminary DS70178C page 123 dsPIC30F1010 202X 12 5 Primary PWM Time Base There is a Primary Time Base PTMR counter for the entire PWM module In addition each PWM generator ha
17. eene 229 MPLAB Integrated Development Environment Software 227 MPLAB Device Programmer 229 MPLAB REAL ICE In Circuit Emulator System 229 MPLINK Object Linker MPLIB Object Librarian 228 N NVM Register 85 OC PWM Module Timing 252 Operating Current 233 Oscillator System Overview eese Oscillator Configurations esses Fail Safe Clock Initial Clock Source Selection ni Phase Locked Loop Start up Timer OST Oscillator Control Register OSCCON E Oscillator Selection eene Oscillator Selection Configuration Bits FOSC 204 Oscillator Selection Configuration Bits FOSCSEL 203 Oscillator Start up Timer Timing Characteristics 246 Timing Requirements bs Oscillator Tuning Register OSCTUN 201 Oscillator Tuning Register 2 OSCTUN 202 Output Compare Interrupts vd Output Compare Timing Characteristics 4 40 22 251 Timing Requirements ns Output Compare Operation During CPU Idle Mode 103 Output Compare Register
18. Reset Sequence eene nenne 49 Reset Sources Reset Timing Characteristics 246 Reset Timing 247 Resets icin POR with Long Crystal Start up Time POR Operating without FSCM and PWRT RTSP Operation rentre t nen S Salos 44 282 Serial Peripheral Interface 145 Simple Capture Event Mode Capture Buffer 98 Capture 98 Hall Sensor Mode six Input Capture in CPU Idle Timer2 and Timer3 Selection Mode Simple OC PWM Mode Timing Requirements we Simple Output Compare Match Mode Simple PWM Period ER Software Simulator MPLAB SIM Software Stack Pointer Frame Pointer CALL Stack Frame x Special Event Compare Register SEVTCMP 111 SPI Master Frame Master Connection 147 Master Slave 147 Slave Frame Master Connection
19. 148 Slave Frame Slave Connection 148 SPI Mode SPI1 Register 152 SPI Module Timing Characteristics Master Mode CKE 0 Master Mode CKE 1 Slave Mode 1 Timing Requirements Master Mode 0 Master Mode 1 Slave Mode CKE 0 42 Slave Mode 1 SPI1 Register STATUS Register Symbols used Opcode Descriptions 220 System 197 System Integration Register Map dsPIC30F202X 218 T Temperature and Voltage Specifications Timer Module rice eene Hoe 16 bit Asynchronous Counter Mode 16 bit Synchronous Counter 16 bit Timer Gate Operation s Interr pt eet tere ette Operation During Sleep Mode Prescaler Timer1 Register Map essen Timer2 and Timer3 Selection Timer2 3 Module 16 bit Timer 32 bit Synchronous Counter 32 bit Timer Mode ai ADC Event 4 40000 1
20. Architecture Package MM QFN Flash PT TQFP SP SPDIP Memory Size in Bytes SO SOIC 0 ROMIess S Die Waffle Pack 1 1K to 6K W Die Wafers 2 7K to 12K 3 13K to 24K 4 25K to 48K Temperature 5 225 to Rp Industrial 40 C to 85 C to i E 2 aaa Extended High Temp 40 C to 125 8 385K to 768K 9 769K and Up Speed Ld 20 20 MIPS Device ID T Tape and Reel A B C Revision Level Example dsPIC30F2020AT 301 SO 30 MIPS Industrial temp SOIC package Rev 2006 Microchip Technology Inc Preliminary DS70178C page 283 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Alpharetta GA Tel 770 640 0034 Fax 770 640 0307 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara
21. TGATE FIGURE 9 3 ADC Event Trigger T3IF Event Flag Note 1 TCS 1 2006 Microchip Technology Inc TCKPS lt 1 0 gt 2 Prescaler 1 8 64 256 16 BIT TIMER3 BLOCK DIAGRAM PR3 Y Equal Comparator x 16 f TMR3 Q ode TGATE amp e x RET 5 lt 1 0 gt 2 Jr gt Sync e 1 X B Prescaler 1 64 256 b 0 dsPIC30F202X does not have an external pin input to The following modes should not be used 2 TCS 0 and TGATE 1 gated time accumulation Preliminary DS70178C page 93 dsPIC30F1010 202X 9 1 Timer Gate Operation The 32 bit timer can be placed in the Gated Time Accu mulation mode This mode allows the internal to increment the respective timer when the gate input sig nal T2CK pin is asserted high Control bit TGATE T2CON 6 must be set to enable this mode When in this mode Timer2 is the originating clock source The TGATE setting is ignored for Timer3 The timer must be enabled TON 1 and the timer clock source set to internal TCS 0 The falling edge of the external signal terminates the count operation but does not reset the timer The user must reset the timer in order to start counting from zero 9 2 ADC Event Trigger When a match occurs between
22. TABLE 4 3 BIT REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size Words XB lt 14 0 gt Bit Reversed Address Modifier Value 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 Note 1 Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010 202X device DS70178C page 46 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X 5 0 INTERRUPTS Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual 0570046 For more information on the device instruction set and programming refer to the dsPIC30F 33F Programmer s Reference Manual 0570157 The dsPIC30F1010 202X device has up to 35 interrupt Sources and 4 processor exceptions traps which must be arbitrated based on a priority scheme The CPU is responsible for reading the Interrupt Vec tor Table IVT and transferring the address contained in the interrupt vector to the Program Counter PC The interrupt vector is transferred from the program data bus into the Program Counter via a 24 bit wide
23. gt AN3 CMP1D CMP2B CN5 RB3 Program Memory AN4 CMP2C CMP3A CN6 RB4 12 Kbytes gt AN5 CMP2D CMP3B CN7 RB5 6 Effective Address OSC1 CLKI RB6 Data Latch 16 x AN7 CMP3D CMP4B OSC2 CLKO RB7 ROM Latch He 24 V IR 16 1 16 Y 16 16 Decode W Reg Array Instruction Decode amp Control Control Signals to Various Blocks Powerup Timer Oscillator Dx PGC2 EMUC2 OC1 SFLT1 IC1 Start up Timer INT1 RDO POR PORTD Reset Watchdog Timer Input Output Comparator 10 5 ADC Capture Compare PWM1L REO lt PWM1H RE1 ha PWM2L RE2 2 i lt PWM2H RE3 PWM3L RE4 1 1 PWM3H RE5 Input SKIPS PGC1 EMUC1 EXTREF PWM4L PI Ti Change ART1 T1CK U1 ARX CNO RE6 PWM E x PGD1 EMUD1 PWM4H T2CK U1ATX CN1 RE7 PORTE gt PGD2 EMUD2 SCK1 SFLT3 OC2 INT2 RF6 as eX PGC EMUC SDI1 SDA U1RX RF7 X PGD EMUD SD01 SCL U1TX RF8 PORTF O 2006 Microchip Technology Inc Preliminary DS70178C page 13 dsPIC30F1010 202X Table 1 2 provides a brief description of device I O pinouts for the dsPIC30F2020 and the functions that may be multiplexed to
24. diuoo4olN 9002 TABLE 8 1 TIMER1 REGISTER MAP SFR Name Addr Bit15 Bit 14 Bit13 Bit 12 Bit11 Bit10 Bit9 Bits Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State TMR1 0100 Timer 1 Register uuuu uuuu uuuu uuuu PR1 0102 Period Register 1 14220 1444 0104 TSIDL TGATE TCKPS lt 1 0 gt TSYNC TCS 0000 0000 0000 0000 Legend u uninitialized bit Note Refer to the dsPIC30F Family Reference Manual DS70046 for descriptions of register bit fields 06 0101 3062145 dsPIC30F1010 202X 9 0 TIMER2 3 MODULE Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046 This section describes the 32 bit General Purpose Timer module Timer2 3 and associated operational modes Figure 9 1 depicts the simplified block diagram of the 32 bit Timer2 3 module Figure 9 2 and Figure 9 3 show Timer2 3 configured as two independent 16 bit timers Timer2 and Timer3 respectively Note The dsPIC30F1010 device does not fea ture Timer3 Timer2 is a Type B timer and Timer3 is a Type C timer Please refer to the appropriate timer type in Section
25. F Units INCHES MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch 031 0 80 Pins per Side ni 11 11 Overall Height A 039 043 047 1 00 1 10 1 20 Molded Package Thickness A2 037 039 041 0 95 1 00 1 05 Standoff A1 002 004 006 0 05 0 10 0 15 Foot Length L 018 024 030 0 45 0 60 0 75 Footprint Reference F 039 REF 1 00 REF Foot Angle 0 3 5 T 0 3 5 7 Overall Width E 463 472 482 11 75 12 00 12 25 Overall Length D 463 472 482 11 75 12 00 12 25 Molded Package Width E1 390 394 398 9 90 10 00 10 10 Molded Package Length D1 390 394 398 9 90 10 00 10 10 Lead Thickness 004 006 008 0 09 0 15 0 20 Lead Width B 012 015 017 0 30 0 38 0 44 Pin 1 Corner Chamfer CH 025 035 045 0 64 0 89 1 14 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 Controlling Parameter Notes Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 0 254mm per side REF Reference Dimension usually without tolerance for information purposes only See ASME Y14 5M JEDEC Equivalent MS 026 Drawing No C04 076 Revised 07 22 05 O 2006 Microchip Technology Inc Preliminary DS70178C page 271 dsPIC30F1010 202X 44 Lead Plastic Quad Flat No Lead Package ML 8x8 mm Body QFN Note http www microchip com packaging For the most current package drawings please see the Microchip Packaging Speci
26. 2006 Microchip Technology Inc Preliminary DS70178C page 199 dsPIC30F1010 202X REGISTER 18 1 OSCCON OSCILLATOR CONTROL REGISTER CONTINUED bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LOCK PLL Lock Status bit read only 1 Indicates that PLL is in lock 0 Indicates that PLL is out of lock or disabled This bit is Reset upon Reset on POR Reset when a valid clock switching sequence is initiated by the clock switch state machine Set when PLL lock is achieved after a PLL start Reset when lock is lost Read zero when PLL is not selected as a Group 1 system clock PRCDEN Pseudo Random Clock Dither Enable bit 1 Pseudo random clock dither is enabled 0 Pseudo random clock dither is disabled CF Clock Fail Detect bit read clearable by application 1 FSOM has detected clock failure FSCM has NOT detected clock failure This bit is Reset upon Reset on POR Reset when a valid clock switching sequence is initiated by the clock switch state machine Set when clock fail detected TSEQEN FRC Tune Sequencer Enable bit 1 The TUN lt 3 0 gt TSEQ1 3 05 TSEQ7 lt 3 0 gt bits in the OSCTUN and the OSCTUN regis ters sequentialy tune the FRC oscillator Each field being sequential selected via the ROLL 2 0 signals from the PWM module 0 TUN lt 3 0 gt bits in OSCTUN register tunes the FRC oscillator Unimplemented Read as 0 OSWEN Oscillator Switch Enable bit 1 Request o
27. Ein Symbol Characteristic Min Typ Max Units Conditions OC15 TFD Fault Input to PWM I O 25 ns VDD 3 3V 40 C to 85 C Change TBD ns VDD 5V OC20 TFLT Fault Input Pulse Width 50 ns VDD 33V 40 C to 85 C TBD ns VDD 5V Legend TBD To Be Determined Note 1 These parameters are characterized but not tested in manufacturing 2 Datain Typ column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested DS70178C page 252 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 21 10 POWER SUPPLY PWM MODULE FAULT TIMING CHARACTERISTICS FLTA B Y PWMx y MP30 gt 4 20 FIGURE 21 11 POWER SUPPLY PWM MODULE TIMING CHARACTERISTICS 11 MP10 gt lt 1 PWMx m Note Refer to Figure 21 1 for load conditions TABLE 21 26 POWER SUPPLY PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions 3 3V and 5 0V 11096 unless otherwise stated Ae CHARACTERISTICS Sc m temperature dt lt TA 85 C for Industrial 40 lt TA 125 for Extended jk Symbol Characteristic Min Typ Max Units Conditions MP10 PWM Output Fall Time 10 25 ns VDD 5V MP11 TRPWM PWM Output Rise Time 10 25 ns VDD 5V MP12
28. 274 Register Map ADG Register irren nnne nentes 190 Analog Comparator Control Register 195 Core Registers i Device Configuration Register 218 I C Hegister s esent ten ed a 159 Input Capture Registers 100 Input Change Notification Registers 80 Interrupt Controller Registers eat LO NVM Registers 85 Output Compare Registers 105 Port Registers dsPICS3O0F 1010 2020 wi 79 Port Registers 45 0 2023 80 Power Supply PWM Registers 142 SPI1 Register oe derer tret 152 System Integration Register dsPIC30F202X 218 Timer 1 Registers Timer2 3 Registers Sets UART1 Register eene 2006 Microchip Technology Inc Preliminary DS70178C page 279 dsPIC30F1010 202X Registers du eR t 171 ADS TET nii ctetu qns 173 EDEN OM IM PE 115 INTCONI m INTOONO 2 ccrte eerie oerte eter 54 INIEDHEGS emt e 74 PHASEX 114 PTGON Y 110 PWMGONK tote e e d attt 112 SEVIGCMB et se ug 111 SPIXCON1 SPIx Control 1 150 SPIXCON2 SPIx Control 2 151 SPIxSTAT SPIx Status and Control
29. Timer L Phase 16 bit Data Bus PDC3 MUX PWM GEN 3 v mm Latch Sak AGE Comparator v Channel 3 Dead time Generator x PWM3L Fault CLMT Override Logic Timer Eee SEES Ly Phase PWM User Current Limit and Fault Override and Routing Logic gt PDC4 PWM GEN 4 Latch Y Comparator A Timer Lp Phase 4 t x PWM4H Dead time Generator x PWM4L Fault Control X SFLTx t PTPER Master Time Base Logic X IFLTX PTMR k External Time Base SYNCO Synchronization 54 SYNCI Comparator Special Event Special Event Postscaler gt Trigger Timer Period gt Special event SEVTCMP comparison value 1 9 IOCONx Pin override control lt FLTCONx Fault mode and pin control DS70178C page 108 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 12 2 Phase Offset Timer Counter v TMR PDC 05 PWM Dead Override Time Logic Logic PARTITIONED OUTPUT PAIR COMPLEMENTARY PWM MODE X PWMxH xcz Duty Cycle Co
30. DS70178C page 156 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 14 8 Slope Control The 2 standard requires slope control on the SDA and SCL signals for Fast mode 400 kHz The control bit DISSLW enables the user to disable slew rate con trol if desired It is necessary to disable the slew rate control for 1 MHz mode 14 9 Support The control bit IPMIEN enables the module to support Intelligent Peripheral Management Interface IPMI When this bit is set the module accepts and acts upon all addresses 14 10 General Call Address Support The general call address can address all devices When this address is used all devices should in theory respond with an acknowledgement The general call address is one of eight addresses reserved for specific purposes by the protocol It consists of all o s with R_W The general call address is recognized when the Gen eral Call Enable GCEN bit is set IZCCON lt 7 gt 1 Following a Start bit detection 8 bits are shifted into I2CRSR and the address is compared with I2CADD and is also compared with the general call address which is fixed in hardware If a general call address match occurs the I2CRSR is transferred to the I2CRCV after the eighth clock the RBF flag is set and on the falling edge of the ninth bit ACK bit the master event interrupt flag MI2CIF is set When the interrupt is serviced the source fo
31. FIGURE 1 1 dsPIC30F1010 BLOCK DIAGRAM X Data Bus 24 E 24 e 3 16 24 PCU PCH PCL Program Counter Address Latch Program Memory AN4 CMP2C CN6 RB4 12 Kbytes gt IX AN5 CMP2D CN7 RB5 Data Latch gt 24 V IR 16 Instruction Decode amp Control Power up Timer Timing Oscillator Dx POR ALU lt 16 gt Reset MCLR Watchdog Timer a e Output Comparator 40 bit ADC Compare PWM1L REO Module PWMTH RE1 I PWM2L RE2 4p 2 eme lt RE4 IC lL SMPs PGC1 EMUC1 EXTREF T1CK SPI1 Timers PWM UART1 DS70178C page 10 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X Table 1 1 provides a brief description of device I O pinouts for the dsPIC30F1010 and the functions that may be multiplexed to a port pin Multiple functions may exist on one port pin When multiplexing occurs the peripheral module s functional requirements may force an override of the data direction of the port pin TABLE 1 1 PINOUT I O DESCRIPTIONS FOR dsPIC30F1010 Pin Name En Buiter Description Type Type ANO AN5 Analog Analog input channels AVDD P P Positive supply for analog module 55 Ground reference for analog module CLKI ST CMOS External clock source input Always associated with OSC1 pin function CLKO O Oscillato
32. LSB Address 0x0000 0x07FE 0x0800 Ox08FE 0x0900 Ox09FE 0 0 00 0 8000 gt 2560 bytes Near Data Space OxFFFE DS70178C page 34 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 3 7 DATA SPACE FOR MCU AND DSP MAC CLASS INSTRUCTIONS SFR SPACE SFR SPACE O UNUSED Y SPACE Y SPACE UNUSED lt De freee c rer ese aT 42 JY UNUSED lt Vy s mum a ee m d LL Lu Non MAC Class Ops Read Write MAC Class Ops Read Only AC Class Ops Write Indirect EA using any W Indirect EA using W10 W11 Indirect EA using W8 W9 2006 Microchip Technology Inc Preliminary DS70178C page 35 dsPIC30F1010 202X 3 2 2 DATA SPACES The X data space is used by all instructions and sup ports all Addressing modes There are separate read and write data buses The X read data bus is the return data path for all instructions that view data space as combined X and Y address space It is also the X address space data path for the dual operand read instructions MAC class The X write data bus is the only write path to data space for all instructions The X data space also supports modulo addressing for all instructions subject to Addressing mode restric tions Bit Reversed Addressing is only supported for writes to X data spac
33. 40 C lt Ta lt 85 VoD 3 0 3 6 1 1 40 C lt Ta lt 85 C VDD 4 5 5 5V 1 1 40 C TA 125 VoD 4 5 5 5V Note 1 Frequency calibrated at 25 C and 5V TUN bits can be used to compensate for temperature drift DS70178C page 244 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 21 3 CLKO AND I O TIMING CHARACTERISTICS Pin Input Pin Output Old Value New Value Note Refer to Figure 21 1 for load conditions TABLE 21 17 CLKO AND I O TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated Operating temperature 40 C x TA 85 C for Industrial 40 lt TA 125 for Extended ii Symbol Characteristic 2 Min Typ Max Units Conditions DO31 TIOR Port output rise time 10 25 ns DO32 TIOF Port output fall time 10 25 ns DI35 TINP INTx pin high or low time output 20 ns D140 TRBP CNx high or low time input 2 Tcv ns Note 1 These parameters are asynchronous events not related to any internal clock edges 2 These parameters are characterized but not tested in manufacturing 3 Data in Typ column is at 5V 25 C unless otherwise stated 2006 Microchip Technology Inc Preliminary DS70178C page 245 d
34. A 4 bit wide multiplexer with eight sets of inputs selects the tuning value from the TUN and the TSEQx bit fields The multiplexer is controled by the ROLL lt 5 3 gt counter in the PWM module The ROLL lt 5 3 gt counter increments every time the primary time base rolls over after reaching the period value 18 6 6 PSEUDO RANDOM CLOCK DITHERING MODE The Pseudo Random Clock Dither PRCD logic is implemented with a 15 bit LFSR Linear Feedback Shift Register which is a shift register with a few exclusive OR gates The lower four bits of the LFSR provides the FRC TUNE bits The PRCD feature is enabled by setting the PRCDEN bit in the OSCCON register The LSFR is clocked enabled to clock once every time the ROLL lt 3 gt bit changes state which occurs once every 8 PWM cycles 18 6 7 FAIL SAFE CLOCK MONITOR The Fail Safe Clock Monitor FSCM allows the device to continue to operate even in the event of an oscillator failure The FSCM function is enabled by appropriately programming the FCKSM Configuration bits Clock Switch and Monitor Selection bits in the FOSC Configuration register In the event of an oscillator failure the FSCM will generate a clock failure trap event and will switch the system clock over to the FRC oscillator The user will then have the option to either attempt to restart the oscillator or execute a controlled shutdown The user may decide to treat the trap as a warm Reset by sim DS70178C page
35. FIGURE 12 6 MULTI PHASE PWM PTMR 0 Y i Phase2 1 4 gt 1 PWM2H Duty Cycle 1 1 EMSS Duty Cycle i Phase4 Eat Duty Cycle Period 12 4 5 VARIABLE PHASE PWM MODE Figure 12 7 shows the waveforms for Variable Phase Shift PWM Power converter circuits constantly change the phase shift among PWM channels as a means to control the flow of power in contrast to most PWM cir cuits that vary the duty cycle of PWM signals to control power flow Often in variable phase applications the PWM duty cycle is maintained at 50 The phase shift value should be updated when the PWM signal is not asserted Complementary outputs are available in Vari able Phase Shift mode FIGURE 12 7 VARIABLE PHASE PWM 12 4 6 CURRENT LIMIT MODE Figure 12 8 shows Cycle by Cycle Current Limit mode This mode truncates the asserted PWM signal when the selected external Fault signal is asserted The PWM output values are specified by the Fault override bits FLTDAT lt 1 0 gt in the IOCONx register The override output remains in effect until the begin ning of the next PWM cycle This mode is sometimes used in Power Factor Correction PFC circuits where the inductor current controls the PWM on time This is a constant frequency PWM mode CYCLE BY CYCLE CURRENT LIMIT PWM MODE FIGURE 12 8 DS70178C page 122 Preliminary
36. 0 5 1 VINL AVss OV AVDD 5V AD22A DNL Differential Nonlinearity 0 5 lt 1 LSb VINL 55 OV AVDD 3 3V AD23 GERR Gain Error 0 75 14 0 LSb VINL 55 AVDD 5V AD23A GERR Gain Error 0 75 13 0 LSb VINL 55 AVDD 3 3V Note 1 Because the sample caps will eventually lose charge clock rates below 10 kHz can affect linearity performance especially at elevated temperatures 2 The A D conversion result never decreases with an increase in the input voltage and has no missing codes 2006 Microchip Technology Inc Preliminary DS70178C page 263 dsPIC30F1010 202X TABLE 21 33 10 BIT HIGH SPEED A D MODULE SPECIFICATIONS CONTINUED Standard Operating Conditions 3 3V and 5 0V 10 unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt TA 85 C for Industrial 40 C lt TA 125 C for Extended Symbol Characteristic Min Typ Max Units Conditions AD24 Offset Error 50 75 lt 2 0 LSb VINL AVSs Vss OV AVDD VDD 5V AD24A Offset Error 10 75 lt 2 0 LSb AVSs Vss OV AVDD VDD 3 3V AD25 Monotonicity2 Guaranteed Dynamic Performance AD30 Total Harmonic Distortion 77 73 68 dB AD31 SINAD Signal to Noise and 58 E dB Distortion AD32 SFDR Spurious
37. 46 Sequence Table 16 46 Block Diagrams 16 bit Timer1 Module esee 88 DSP Engine dsPIC30F1010 dsPIC30F2020 dsPIC30F2023 External Power on Reset 212 Input Capture Mode 97 Oscillator System eene 198 Output Compare Mode T Reset System iniiai ie ridae 210 Shared Port Structure 77 C Compilers MPLAB C18 hene db redde dre sd 228 MPEAB 30 npe dete t ends 228 CLKO and I O Timing Characteristics eese 245 Req irements 5 eterni haere rnnt nns 245 Code Examples Erasing a Row of Program Initiating a Programming Sequence Loading Write Latches Code Protection Comparator Control Register CMPCONX 193 Comparator DAC Control Registerx CMPDAQCYX 194 Configuring Analog Port 78 Control Registers NVMADRi e yee etes NVMADRU NVMCON ux NVMKEY 82 Core Architecture QVOIVIOW7 5 datu ERRORI 19 Core Register 37 38 Customer Change Notification 273 Customer Notification Service
38. The 17x17 bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1 31 fractional Q31 or 32 bit integer results Unsigned operands are zero extended into the 17th bit of the multiplier input value Signed operands are sign extended into the 17th bit of the mul tiplier input value The output of the 17x17 bit multiplier scaler is a 33 bit value which is sign extended to 40 bits Integer data is inherently represented as a signed two s complement value where the MSB is defined as a sign bit Generally speaking the range of an N bit two s complement integer is 2 2N 1 1 For a 16 bit integer the data range is 32768 0x8000 to 32767 Ox7FFF including 0 For a 32 bit integer the data range is 2 147 483 648 0 8000 0000 to 2 147 483 645 Ox7FFF FFFF When the multiplier is configured for fractional multipli cation the data is represented as a two s complement fraction where the MSB is defined as a sign bit and the radix point is implied to lie just after the sign bit QX for mat The range of an N bit two s complement fraction with this implied radix point is 1 0 to 1 21 For a 16 bit fraction the Q15 data range is 1 0 0x8000 to 0 999969482 0x7FFF including 0 and has a preci sion of 3 01518x10 In Fractional mode a 16x16 mul tiply operation generates a 1 31 product which has a precision of 4 65661 10 10 The same multiplier is used to
39. 0 8 1 0 us Low or Watchdog Timer Reset SY20 1 Watchdog Timer Time out Period 1 4 2 1 2 8 ms VDD 5V 40 C to No Prescaler 125 C TWDT2 1 4 2 1 2 8 ms VDD 3 3 40 C to 125 C SY30 Oscillation Start up Timer Period 1024 Tosc OSC1 period SY35 TFSCM Fail Safe Clock Monitor Delay 500 us 40 C to 125 C Note 1 These parameters are characterized but not tested in manufacturing 2 Data in Typ column is at 5V 25 C unless otherwise stated 2006 Microchip Technology Inc Preliminary DS70178C page 247 dsPIC30F1010 202X FIGURE 21 5 BAND GAP START UP TIME CHARACTERISTICS f VBGAP OV Enable Band Gap see Note SY40 Stable TABLE 21 19 BAND GAP START UP TIME REQUIREMENTS Standard Operating Conditions 3 3V and 5 0V 11096 unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for Industrial 40 C lt TA 125 for Extended Symbol Characteristic Min Typ Max Units Conditions SY40 TBGAP Band Gap Start up Time 40 65 us Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable lt 13 gt status bit Note 1 These parameters are characterized but not tested in manufacturing 2 Data in Typ column is at 5V 25 C unless otherwise stat
40. 1 us After this period the Hold Time 400 kHz mode Tcv 2 BRG 1 EN us first clock pulse is 1 MHz mode Tcv 2 BRG 1 TEE IM33 Tsu srTO Stop Condition 100 kHz mode Tcv 2 BRG 1 us Setup Time 400 kHz mode Tcv 2 BRG 1 us 1 MHz mode Tcv 2 BRG 1 us IM34 Stop Condition 100 kHz mode Tcv 2 BRG 1 ns Hold Time 400 kHz mode Tcv 2 BRG 1 ns 1 MHz mode Tcv 2 BRG 1 ns IM40 TAA SCL Output Valid 100 kHz mode 3500 ns From Clock 400 kHz mode 1000 ns 1 MHz mode ns IM45 TBF SDA Bus Free Time 100 kHz mode 4 7 us Time the bus must be 400 kHz mode 1 3 us _ free before a new 1 MHZ mode TBD us transmission can start Legend TBD To Be Determined Note 1 BRG is the value of the IC Baud Rate Generator Refer to the Inter Integrated Circuit I2C section in the dsPIC30F Family Reference Manual DS70046 2 Maximum pin capacitance 10 pF for all 2 pins for 1 MHz mode only DS70178C page 260 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X TABLE 21 31 BUS DATA TIMING REQUIREMENTS MASTER MODE CONTINUED Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated AG CHARACTERISTICS Operating temperature 40 lt TA 85 for Industrial 40 C lt TA 125 C for Extended Symbol Characteristic Min Max Units
41. Clear the IRQ flag in the ADC BRA ADC PAIR1 PROC Actual Pair 1 Conversion Interrupt Handler BCLR ADSTAT 2 Clear the IRQ flag in the ADC BRA ADC PAIR2 PROC Actual Pair 2 Conversion Interrupt Handler BCLR ADSTAT 3 Clear the IRQ flag in the ADC BRA ADC PAIR3 PROC Actual Pair 3 Conversion Interrupt Handler BCLR ADSTAT 4 Clear the IRQ flag in the ADC BRA PAIRA PROC Actual Pair 4 Conversion Interrupt Handler DS70178C page 184 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X EXAMPLE 16 1 BASE REGISTER CODE CONTINUED The actual pair conversion interrupt handler Don t forget to pop the stack when done and return from interrupt ADC PAIRO PROC m The ADC pair 0 conversion complete POP S Restore WO W3 and SR registers RETFIE Return from Interrupt 1 PROC T The ADC pair 1 conversion complete handler POP S Restore WO W3 and SR registers RETFII Return from Interrupt ADC PAIR2 PROC p The ADC pair 2 conversion complete handler POP S Restore WO W3 and SR registers RETFI Return from Interrupt ADC PAIR3 PROC o The ADC pair 3 conversion complete POP S Restore WO W3 and SR registers RETFII Return from Interrupt The ADC pair 4 conversion complete handler POP S Restore WO W3 and SR registers RETFI Return from Interrupt PAIRS PROC The ADC pair 5 conv
42. H cO s DS70178C page 96 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 10 0 INPUT CAPTURE MODULE Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual 0570046 This section describes the Input Capture module and associated operational modes The features provided by this module are useful in applications requiring Fre quency Period and Pulse measurement Figure 10 1 depicts a block diagram of the Input Capture module Input capture is useful for such modes as Frequency Period Pulse Measurements Additional sources of External Interrupts The key operational features of the Input Capture module are Simple Capture Event mode Timer2 and Timer3 mode selection Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register where x 1 2 N The dsPIC DSC devices contain up to 8 capture channels i e the maximum value of N is 8 The dsPIC30F1010 devices does not fea ture a Input Capture module The dsPIC30F202X devices have one capture input IC1 The naming of this capture channel is intentional and preserves soft ware compatibility with other
43. Input Capture Timing Requirements Input Change Notification esee Input Change Notification Register Map Instruction Addressing Modes File Register Instructions Fundamental Modes Supported MAC Instructions MCU Instructions m Move and Accumulator Instructions Other Instruction Set 2 Instruction Set Overview 2 Inter Integrated Circuit See Internal Clock Timing Examples Internet Address Interrupt Control and Status Register INTTREG T Interrupt Control Register 1 INTCON1 Interrupt Control Register 2 INTCON2 Interrupt Controller Register Map Interrupt Enable Control Register 1 IEC1 Interrupt Enable Control Register 2 IEC2 E Interrupt Flag Status Register 0 IFSO Interrupt Flag Status Register 1 IFS1 Interrupt Flag Status Register 2 IFS2 Interrupt 2 20242222 Interrupt Priority Control Register 0 IPCO 2 Interrupt Priority Control Register 1 IPC1 Interrupt Priority Control Register 10 IPC10 Interrupt Priori
44. Internal Reset 2006 Microchip Technology Inc Preliminary DS70178C page 211 dsPIC30F1010 202X FIGURE 18 10 TIME OUT SEQUENCE ON POWER UP MCLR NOT TIED VDD CASE 2 VDD y MCLR d Internal POR el OST Time out PWRT Time out Internal Reset 18 7 1 1 POR with Long Crystal Start up Time with FSCM Enabled The oscillator start up circuitry is not linked to the POR circuitry Some crystal circuits especially low frequency crystals will have a relatively long start up time Therefore one or more of the following conditions is possible after the POR timer and the PWRT have expired The oscillator circuit has not begun to oscillate The Oscillator Start up Timer has NOT expired if a crystal oscillator is used The PLL has not achieved a LOCK if PLL is used If the FSCM is enabled and one of the above conditions is true then a clock failure trap will occur The device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the trap ISR 18 7 1 2 Operating without FSCM and PWRT If the FSCM is disabled and the Power up Timer PWRT is also disabled then the device will exit rap idly from Reset on power up If the clock source is FRC or EC it will be active immediately If the FSCM is disabled and the system clock has not started the device will be in a frozen state at t
45. lit10 C 1 1 C DC N OV Z SUBB Wb Ws Wd Wd Wb Ws C 1 1 C DC N OV Z SUBB Wb 1it5 Wd Wd Wb lit5 C 1 1 C DC N OV Z 74 SUBR SUBR f f WREG f 1 1 C DC N OV Z SUBR f WREG WREG WREG f 1 1 C DC N OV Z SUBR Wb Ws Wd Wd Ws Wb 1 1 C DC N OV Z SUBR Wb 1it5 Wd Wd lits Wb 1 1 C DC N OV Z 75 SUBBR SUBBR f f WREG f C 1 1 C DC N OVZ SUBBR f WREG WREG WREG f C 1 1 C DC N OV Z SUBBR Wb Ws Wd Wd Ws Wb C 1 1 C DC N OV Z SUBBR Wb 1it5 Wd Wd lit5 Wb C 1 1 C DC N OV Z 76 SWAP SWAP b Wn Wn nibble swap Wn 1 1 None SWAP Wn Wn byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws Wd Read Prog lt 23 16 gt to Wd lt 7 0 gt 1 2 None 78 TBLRDL TBLRDL Ws Wd Read Prog lt 15 0 gt to Wd 1 2 None 79 TBLWTH TBLWTH Ws Wd Write Ws lt 7 0 gt to Prog lt 23 16 gt 1 2 None 80 TBLWTL TBLWTL Ws Write Ws to Prog lt 15 0 gt 1 2 81 ULNK ULNK Unlink frame pointer 1 1 None 82 XOR XOR f f f XOR WREG 1 1 N Z XOR f WREG WREG f XOR WREG 1 1 N Z XOR 1it10 Wn Wd lit10 XOR Wd 1 1 N Z XOR Wb Ws Wd Wd Wb XOR Ws 1 1 NZ XOR Wb 1it5 Wd Wd Wb XOR lit5 1 1 NZ 83 ZE ZE Ws Wnd Wnd Zero Extend Ws 1 1 2 DS70178C page 226 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 20 0 DEVELOPMENT SUPPORT The PIC9 microcontrollers are supported with a full range of hardware and software development tools Integrated Development Environment MPLAB
46. 1 ADCPC1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PEND3 SWTRG3 TRGSRC3 lt 4 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 IRQEN2 PEND2 SWTRG2 TRGSRC2 lt 4 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 IRQENG Interrupt Request Enable 3 bit 1 Enable IRQ generation when requested conversion of channels AN7 and AN6 is completed 0 IRQ is not generated bit 14 PEND3 Pending Conversion Status 3 bit 1 Conversion of channels AN7 and AN6 is pending Set when selected trigger is asserted 0 Conversion is complete bit 13 SWTRG3 Software Trigger 3 bit 1 Start conversion of AN7 and AN6 if selected by TRGSRC bits If other conversions are in progress then conversion will be performed when the conversion resources are available This bit will be reset when the PEND bit is set bit 12 8 TRGSRC3 lt 4 0 gt Trigger 3 Source Selection bits Selects trigger source for conversion of analog channels A7 and A6 00000 No conversion enabled 00001 Individual software trigger selected 00010 Global software trigger selected 00011 PWM Special Event Trigger selected 00100 PWM generator 1 trigger selected 00101 PWM generator 2 trigger selected 00110 PWM generator 8 trigger selected 00111 PWM generato
47. 11096 unless otherwise stated Operating temperature 40 C x TA 85 C for Industrial 40 C x TA 125 C for Extended ah ie Typical Max Units Conditions Idle Current IDLE Core OFF Clock ON Base Current DC48a 65 78 mA 25 C 3 3V DC48b 66 79 mA 85 C DC48d 105 127 mA 25 C EC 20 MIPS PLL enabled DC48e 107 128 mA 85 C 5V DC48f 108 130 mA 125 C DC49d 155 186 mA 25 C 5V EC 30 MIPS PLL enabled DC49e 156 187 mA 85 C Note 1 Data Typical column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 2 Base current is measured with Core off Clock on and all modules turned off All I Os are configured as inputs and pulled high WDT etc are all switched off DS70178C page 236 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X TABLE 21 7 DC CHARACTERISTICS Max 2 4 2 4 2 6 4 2 4 2 4 6 30 30 30 60 60 60 DC CHARACTERISTICS POWER DOWN CURRENT Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated Operating temperature 40 lt Ta lt 85 C for Industrial 40 C x TA 125 C for Extended Units Conditions mA 25 C mA 85 C 3 3V A 125 C Base Power Down Current mA 25 C mA 85 C 5V mA 125 C uA 25 C 85 C 3 3V A 125 C Watchdog Timer Current 9 uA 25 C uA 85 C 5V uA 125
48. 211 MHz max bit 4 3 Unimplemented Read as 0 bit 3 OSCIOFNC OSC2 Pin I O Enable bit 1 CLKO output signal active on the OSCO pin 0 CLKO output disabled bit 1 0 POSCMD lt 1 0 gt Primary Oscillator Mode 11 Primary Oscillator Disabled 10 HS oscillator mode selected 01 Reserved 00 External clock mode selected DS70178C page 204 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 18 2 1 ACCIDENTAL WRITE PROTECTION Because the OSCCON register allows clock switching and clock scaling a write to OSCCON is intentionally made difficult To write to the OSCCON low byte this exact sequence must be executed without any other instructions in between Byte Write 46h to OSCCON low Byte Write 57h to OSCCON low Byte Write is allowed for one instruction cycle mov b 0 05 To write to the OSCCON high byte this exact sequence must be executed without any other instruc tions in between Byte Write 78h to OSCCON high Byte Write 9Ah to OSCCON high Byte Write is allowed for one instruction cycle mov b W0 OSCCON 1 18 3 Oscillator Configurations Figure 18 2 shows the derivation of the system clock Fcv The PLL in Figure 18 1 outputs a maximum fre quency of 480MHz high range FRC option for industrial temperature parts with PLL and TUN lt 3 0 gt 0111 bit settings This signal is used by the Power Supply PWM module and is 32 times the input PLL fre
49. An example program memory address i Perform the TBLWT instructions to write the latches Oth program word MOV WORD 0 W2 MOV HHIGH BYTE 0 W3 TBLWTL W2 WO BLWTH W3 WO 4 lst program word MOV LOW WORD 1 W2 MOV HHIGH BYTE 1 W3 TBLWTL W2 WO TBLWTH W3 WO 2nd_program_word MOV LOW WORD 2 W2 MOV HHIGH BYTE 2 W3 TBLWTL W2 wo BLWTH 0 1 31st program word MOV HLOW WORD 31 W2 MOV HHIGH BYTE 31 W3 7 TBLWTL W2 WO TBLWTH W3 WO Note In Example 7 2 the contents of the upper byte of W3 have no effect Write PM low word into program latch Write PM high byte into program latch Write PM low word into program latch Write PM high byte into program latch Write PM low word into program latch Write PM high byte into program latch Write PM low word into program latch Write PM high byte into program latch 7 6 4 SEQUENCE INITIATING THE PROGRAMMING For protection the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed After the programming command has been executed the user must wait for the programming time until programming is complete The two instructions following the start of the programming sequence should be NOPs EXAMPLE 7 3 INITIATING A PROGRAMMING SEQUENCE DISI 5 Block all interrupts with priority lt 7 for next 5 instructions MOV 0x
50. Analog 1 Channel D CMP2A Analog Comparator 2 Channel A CMP2B Analog Comparator 2 Channel CMP2C Analog Comparator 2 Channel C CMP2D Analog Comparator 2 Channel D CNO CN7 5 Input Change notification inputs Can be software programmed for internal weak pull ups on all inputs VDD P Positive supply for logic and pins Vss P Ground reference for logic and pins EXTREF Analog External reference to Comparator DAC Legend CMOS CMOS compatible input or output Analog Analog input ST Schmitt Trigger input with CMOS levels Output Input P DS70178C page 12 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 1 2 dsPIC30F2020 BLOCK DIAGRAM Y Data Bus X Data Bus Ji te Me he Je 16 Interrupt Data Latch Data Latch PSV amp Table a Controller Data Access T M 54 Control Block 256 bytes 256 bytes gt x SFLT2 INTO OCFLTA RAQ Address Address 24 Latch Latch PORTA 16 16 116 Za X RAGU Y AGU PCU PCH PCL X WAGU a ANO CMP1A CN2 RBO Z Program Counter Ix AN1 CMP1B CN3 RB1 Address Latch Stack Loop lt gt lt AN2 CMP1C CMP2A CN4 RB2
51. C Data in the Typical column is at 5V 25 C unless otherwise stated Parameters are for design guidance Base IPD is measured with all peripherals and clocks shutdown All I Os are configured as inputs and pulled high WDT etc are all switched off iis Typical Power Down Current IPD DC60a 1 2 DC60b 1 2 DC60c 1 3 DC60e 2 1 DC60f 2 1 DC60g 2 3 DC61a 15 DC61b 14 DC61c 14 DC61e 30 DC61f 29 DC61g 30 Note 1 only and are not tested 2 3 TheA 2006 Microchip Technology Inc Preliminary DS70178C page 237 dsPIC30F1010 202X TABLE 21 8 DC CHARACTERISTICS I O PIN INPUT SPECIFICATIONS Standard Operating Conditions 3 3V and 5 0V 11096 unless otherwise stated DC CHARACTERISTICS i temperature e lt Ta lt 85 C for Industrial 40 C lt Ta lt 125 C for Extended iw Symbol Characteristic Min Units Conditions VIL Input Low Voltage DI10 I O pins with Schmitt Trigger buffer Vss 0 2VbD V DI15 MCLR Vss 02VpD V DI16 OSC1 in HS mode Vss O2VpD V 0118 SDA SCL Vss 0 3VpD V SMbus disabled 0119 SDA SCL Vss 0 2 0 V SMbus enabled VIH Input High Voltage DI20 I O pins with Schmitt Trigger buffer 0 8VDD VDD V DI25 MCLR 0 8 VDD V 0126 OSC1 in HS mode 07VbpD VDD V 0128 SDA SCL 0 7VDD VDD V SMbus disabled 0129 SDA SCL 0 8VbDD VDD V SMbus enabled liL Input Leakage Current 30 DI50 I O ports 0 01
52. Fault Interrupt Enable bit 1 Fault interrupt enabled 0 Fault interrupt disabled and FLTSTAT bit is cleared DS70178C page 112 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X REGISTER 12 5 PWMCONx PWM CONTROL REGISTER CONTINUED bit 11 CLIEN Current Limit Interrupt Enable bit 1 Current limit interrupt enabled 0 Current limit interrupt disabled and CLSTAT bit is cleared bit 10 TRGIEN Trigger Interrupt Enable bit 1 trigger event generates an interrupt request 0 Trigger event interrupts are disabled and TRGSTAT bit is cleared bit 9 ITB Independent Time Base Mode bit 1 Phasex register provides time base period for this PWM generator 0 Primary time base provides timing for this PWM generator bit 8 MDCS Master Duty Cycle Register Select bit 1 MDC register provides duty cycle information for this PWM generator 0 DCx register provides duty cycle information for this PWM generator bit 7 6 DTC lt 1 0 gt Dead time Control bits 00 Positive dead time actively applied for all output modes 01 Negative dead time actively applied for all output modes 10 Dead time function is disabled 11 Reserved bit 5 2 Unimplemented Read as 0 bit 1 XPRES External PWM Reset Control bit 1 Current limit source resets time base for this PWM generator if it is in independent time base mode 0 External pins do not affect PWM time base bit 0 IUE Immediate Update Enable bit 1 Updates to the ac
53. PWM Output Fall Time TBD TBD ns VDD 3 3V MP13 TRPWM_ PWM Output Rise Time TBD TBD ns VDD 3 3V MP20 TFD Fault Input to PWM TBD ns VDD 3 3V Change 25 ns VDD 5V TFH Minimum Pulse Width TBD ns VDD 3 3V MP30 50 ns VDD 5V Legend TBD To Be Determined Note 1 These parameters are characterized but not tested in manufacturing 2 Data Typ column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 2006 Microchip Technology Inc Preliminary DS70178C page 253 dsPIC30F1010 202X FIGURE 21 12 SPI MODULE MASTER MODE CKE 0 TIMING CHARACTERISTICS 1 gt 4 SPIT SP10 21 SP20 ms E UON CE CKP 1 i f esl 14 SP35 3 SP20 5 21 SCKx CKP 0 SDOx SDIx SP40 SP41 lt Note Refer to Figure 21 1 for load conditions TABLE 21 27 SPI MASTER MODE CKE 0 TIMING REQUIREMENTS Standard Operating Conditions 3 3V and 5 0V 21096 unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt Ta lt 85 C for Industrial 40 C lt TA 125 C for Extended Para m Symbol Characteristic Min Typ Max Units Conditions No SP10 TscL SCKx Output Low Time Tcv 2 ns SP11 TscH SCKx Output High Time Tcv 2 ns EN SP20 TscF SCKx Output Fall Time ns See parameter D
54. Preliminary 2006 Microchip Technology Inc MICROCHIP dsPIC30F1010 202X 28 44 Pin dsPIC30F1010 202X Enhanced Flash SMPS 16 Bit Digital Signal Controller Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046 For more information on the device instruction set and programming refer to the dsPIC30F 33F Programmer s Reference Manual 0570157 High Performance Modified RISC CPU Modified Harvard architecture C compiler optimized instruction set architecture 83 base instructions with flexible addressing modes 24 bit wide instructions 16 bit wide data path 12 Kbytes on chip Flash program space 512 bytes on chip data RAM 16 x 16 bit working register array Up to 30 MIPS operation Dual Internal RC 9 7 and 14 55 MHz 1 Industrial Temp 6 4 and 9 7 MHz 1 Extended Temp 32X PLL with 480 MHz VCO PLL inputs 3 External EC clock 6 0 to 14 55 MHz HS Crystal mode 6 0 to 14 55 MHz 32 interrupt sources Three external interrupt sources 8 user selectable priority levels for each interrupt 4 processor exceptions and software traps DSP Engine Features Modulo and Bit Reversed modes Two 40 bit wide accumulators with optional saturation
55. RTSP RTSP is accomplished using TBLRD table read and TBLWT table write instructions With RTSP the user may erase program memory 32 instructions 96 bytes at a time and can write program memory data 32 instructions 96 bytes at a time 7 3 Table Instruction Operation Summary The TBLRDL and the TBLWTL instructions are used to read or write to bits lt 15 0 gt of program memory TBLRDL and TBLWTL can access program memory in Word or Byte mode The TBLRDH and TBLWTH instructions are used to read or write to bits lt 23 16 gt of program memory TBLRDH and TBLWTH can access program memory in Word or Byte mode A 24 bit program memory address is formed using bits lt 7 0 gt of the TBLPAG register and the Effective Address EA from a W register specified in the table instruction as shown in Figure 7 1 ADDRESSING FOR TABLE AND NVM REGISTERS 24 bits Using Program 0 Program Counter 0 Counter NVMADR Reg EA Using NVMADR 1 0 NVMADRU Reg Addressing gt 8 bits 16 bits Working Reg EA Using 1 0 TBLPAG Re Table 9 Instruction 8 bits i 16 bits A User Configuration Select Space Select 24 bit EA 2006 Microchip Technology Inc Preliminary DS70178C page 81 dsPIC30F1010 202X 7 4 RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels Each row consists of 32
56. SP40 Note Refer to Figure 21 1 for load conditions TABLE 21 29 SPI MODULE SLAVE MODE CKE 0 TIMING REQUIREMENTS Standard Operating Conditions 3 3V and 5 0V 11096 unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt Ta lt 85 C for Industrial 40 C lt TA 125 C for Extended Symbol Characteristic Min Typ Max Units Conditions SP70 TscL SCKx Input Low Time 30 ns SP71 TscH SCKx Input High Time 30 ns SP72 TscF SCKx Input Fall Time 9 10 25 ns SP73 TscR SCKx Input Rise Time 10 25 ns SP30 TdoF SDOx Data Output Fall Time ns See parameter D032 SP31 TdoR SDOx Data Output Rise Time ns See parameter D031 SP35 TscH2doV SDOx Data Output Valid after 30 ns TscL2doV 5 Edge SP40 TdiV2scH Setup Time of SDIx Data Input 20 ns TdiV2scL 40 SCKx Edge SP41 TscH2diL Hold Time of SDIx Data Input 20 ns TscL2diL to SCKx Edge SP50 TssL2scH SSXL to SCKxT or SCKXJ Input 120 ns TssL2scL SP51 TssH2doZ 55 to SDOx Output 10 50 ns High impedance SP52 TscH2ssH SSx after SCK Edge 1 5 ns TscL2ssH 40 Note 1 These parameters are characterized but not tested in manufacturing 2 Data in Typ column is at 5V 25 C unless otherwise stated Parameters are for de
57. TA20 TCKEXTMRL Delay from External TxCK Clock 0 5 Tcv 1 5 Edge to Timer Increment 2006 Microchip Technology Inc Preliminary DS70178C page 249 dsPIC30F1010 202X TABLE 21 21 TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS 40 C x TA 85 C for Industrial 40 C lt TA 125 for Extended Standard Operating Conditions 3 3V and 5 0V 11096 unless otherwise stated Operating temperature ire Symbol Characteristic Min Typ Max Units Conditions TB10 TtxH TxCK High Time Synchronous 0 5 20 ns Must also meet no prescaler parameter TB15 Synchronous 10 ns with prescaler TB11 TtxL TxCK Low Time 0 5 Tcv 20 ns Must also meet no prescaler parameter TB15 Synchronous 10 ns with prescaler TB15 TxCK Input Period Synchronous Tcv 10 ns N no prescaler value 1 8 64 256 Synchronous Greater of with prescaler 20 ns or Tcv 40 N TB20 Delay from External TxCK Clock 0 5 Tcv 1 5 Edge to Timer Increment TABLE 21 22 TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated 40 C lt TA 85 C for Industrial 40 C lt TA 125 C for Extended Operating temperature
58. Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 bit 14 bit 13 bit 12 7 bit 6 bit 5 2 bit 1 bit 0 SPIEN SPIx Enable bit 1 Enables module and configures SCKx SDOx SDIx and SSx as serial port pins 0 Disables module Unimplemented Read as 0 SPISIDL Stop in Idle Mode bit 1 Discontinue module operation when device enters Idle mode 0 Continue module operation in Idle mode Unimplemented Read as 0 SPIROV Receive Overflow Flag bit 1 Anew byte word is completely received and discarded The user software has not read the previous data in the SPIxBUF register 0 No overflow has occurred Unimplemented Read as 0 SPITBF SPIx Transmit Buffer Full Status bit 1 Transmit not yet started SPIXTXB is full 0 Transmit started SPIXTXB is empty Automatically set in hardware when CPU writes SPIxBUF location loading SPIxTXB Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR SPIRBF SPIx Receive Buffer Full Status bit 1 Receive complete SPIxRXB is full 0 Receive is not complete SPIXRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location reading SPIxRXB 2006 Microchip Technology Inc Preliminary DS70178C page 149 dsPIC30F1010 202X REGISTER
59. are not applicable in this mode 10 2 2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality In the CPU Idle mode the Inter rupt mode selected by the ICI 1 0 bits are applicable as well as the 4 1 and 16 1 capture prescale settings which are defined by control bits ICM lt 2 0 gt This mode requires the selected timer to be enabled Moreover the ICSIDL bit must be asserted to a logic o If the input capture module is defined as ICM lt 2 0 gt 111 in CPU Idle mode the input capture pin will serve only as an external interrupt pin 10 3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt based upon the selected number of cap ture events The selection number is set by control bits lt 1 0 gt lt 6 5 gt Each channel provides an interrupt flag ICxIF bit The respective capture channel interrupt flag is located in the corresponding IFSx STATUS register Enabling an interrupt is accomplished via the respec tive capture channel interrupt enable ICxIE bit The capture interrupt enable bit is located in the corresponding IEC Control register 2006 Microchip Technology Inc Preliminary DS70178C page 99 001 08 10 5 Aseuiwijaid diuoo4olN 9002 TABLE 10 1 INPUT CAPT
60. assume 15 MHz external clock as clock source 111 FADC 18 0 83 MHz 7 5 MIPS 110 FADC 16 0 93 MHz 7 5 MIPS 101 FADC 14 1 07 MHz 7 5 MIPS 100 FADC 12 1 25 MHz 7 5 MIPS 011 FADC 10 1 5 MHz 7 5 MIPS 010 FADC 8 1 87 MHz 7 5 MIPS 001 FADC 6 2 5 MHz 7 5 MIPS 000 FADC 4 3 75 MHz 7 5 MIPS Note See Figure 18 2 for ADC clock derivation DS70178C page 172 Preliminary 2006 Microchip Technology Inc REGISTER 16 2 dsPIC30F1010 202X A D STATUS REGISTER ADSTAT C Clear in software H S Set by hardware U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 bit 15 bit 8 U 0 U 0 R C 0 R C 0 R C 0 R C 0 R C 0 R C 0 H S H S H S H S H S H S P5RDY PARDY P3RDY P2RDY P1RDY PORDY bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown bit 15 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented Read as 0 P5RDY Conversion Data for Pair 5 Ready bit Bit set when data is ready in buffer cleared when a PARDY Conversion Data for Pair 44 Ready bit Bit set when data is ready in buffer cleared when a P3RDY Conversion Data for Pair 3 Ready bit Bit set when data is ready in buffer cleared when a P2RDY Conversion Data for Pair 42 Ready bit Bit set when data is ready in buffer clea
61. bit 11 Unimplemented Read as 0 bit 10 8 lt 2 0 gt Output Compare Channel 1 Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 7 Unimplemented Read as 0 bit 6 4 lt 2 0 gt Input Capture Channel 1 Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3 Unimplemented Read as 0 bit 2 0 INTOIP lt 2 0 gt External Interrupt O Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled 2006 Microchip Technology Inc Preliminary DS70178C page 63 dsPIC30F1010 202X REGISTER 5 10 IPC1 INTERRUPT PRIORITY CONTROL REGISTER 1 U 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 lt 2 0 gt 21 lt 2 0 gt bit 15 bit 8 U 0 R W 1 R W 0 R W 0 U 0 U 0 U 0 U 0 21 lt 2 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 Unimplemented Read as 0 bit 14 12 T3IP lt 2 0 gt Timer3 Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 In
62. interrupt enable bit and interrupt priority bits associated with it The Fault pins are also readable through the PORT I O logic when the PWM module is enabled This allows the user to poll the state of the Fault pins in software FIGURE 12 21 PWM CURRENT LIMIT CONTROL LOGIC DIAGRAM PWMXxH L Signals P PWMx PWM Period Generator Reset D PWMxH L CLDAT lt 1 0 gt Analog Comparator SEMOD CLSTAT odule Analog Comparator 1 gt CMP Analog Comparator 2 gt Analog Comparator 3 0010 Analog 4 5 Shared Fault 1 1000 MUX SFLT2X Shared Fault 2 106 Shared Fault 3 211010 SFLT4AX Shared Fault 4 1101 IFLT2 Independent Fault 2 IFLTA Independent Fault 4 gt DS70178C page 134 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 12 25 Simultaneous PWM Faults and Current Limits The current limit override function if enabled and active forces the PWMxH L pins to the values speci fied by the CLDAT lt 1 0 gt bits in the IOCONXx registers UNLESS the Fault function is enabled and active If the selected Fault input is active the PWMxH L outputs assume the values specified by the FLTDAT lt 1 0 gt bits in the IOCONx registers 12 26 PWM Fault and Current Limit TRG Outputs To ADC The
63. literal instruction where literal is an unimplemented program memory address 6 Executing instructions after modifying the PC to point to unimplemented program memory addresses The PC may be modified by loading a value into the stack and executing a RETURN instruction Stack Error Trap This trap is initiated under the following conditions 1 The Stack Pointer is loaded with a value which is greater than the user programmable limit value written into the SPLIM register stack overflow 2 The Stack Pointer is loaded with a value which is less than 0x0800 simple stack underflow Oscillator Fail Trap This trap is initiated if the external oscillator fails and operation becomes reliant on an internal RC backup 5 3 2 HARD AND SOFT TRAPS It is possible that multiple traps can become active within the same cycle e g a misaligned word stack write to an overflowed address In such a case the fixed priority shown in Figure 5 1 is implemented which may require the user to check if other traps are pending in order to completely correct the fault Soft traps include exceptions of priority level 8 through level 11 inclusive The arithmetic error trap level 11 falls into this category of traps Hard traps include exceptions of priority level 12 through level 15 inclusive The address error level 12 stack error level 13 and oscillator error level 14 traps fall into this category Each hard trap tha
64. prefetch MOV instructions MOV D instructions All other instructions will require two instruction cycles in addition to the specified execution time of the instruction For instructions that use PSV which are executed inside a REPEAT loop The following instances will require two instruction cycles in addition to the specified execution time of the instruction Execution in the first iteration Execution in the last iteration Execution prior to exiting the loop due to an interrupt Execution upon re entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data using PSV to execute in a single cycle DS70178C page 32 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 3 5 DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION 15 5 lt 15 gt 0 Data Space a EA 15 23 15 0 lt 15 gt 1 gt 3 2 Data Address Space The core has two data spaces The data spaces can be considered either separate for some DSP instruc tions or as one unified linear address range for MCU instructions The data spaces are accessed using two Address Generation Units AGUs and separate data paths 3 2 1 DATA SPACE MEMORY MAP The data space memory is split into two blocks X and Y data space A key element of this architecture is that Y space is a s
65. saturation and provides protection against erro neous data or unexpected algorithm problems e g gain calculations 2 Bit 31 Overflow and Saturation When bit 31 overflow and saturation occurs the saturation logic then loads the maximally positive 1 31 value 0x007FFFFFFF or maximally nega tive 1 31 value 0x0080000000 into the target accumulator The SA or SB bit is set and remains set until cleared by the user When this Saturation mode is in effect the guard bits are not used so the OA OB or OAB bits are never set 3 Bit 39 Catastrophic Overflow The bit 39 overflow Status bit from the adder is used to set the SA or SB bit which remain set until cleared by the user No saturation operation is performed and the accumulator is allowed to overflow destroying its sign If tne COVTE bit in the INTCON1 register is set a catastrophic overflow can initiate a trap exception 2 4 2 2 Accumulator Write Back The class of instructions with the exception of MPY MPY N ED and EDAC can optionally write a rounded version of the high word bits 31 through 16 of the accumulator that is not targeted by the instruction into data space memory The write is performed across the X bus into combined X and Y address space The following addressing modes are supported 1 W413 Register Direct The rounded contents of the non target accumulator are written into W13 as a 1 15 fraction 2 W13 2 Register Indirect with P
66. the PWM outputs are restored immediately when the Fault input pin is deasserted AND the FSTAT bit has been cleared in software 12 23 7 FAULT PIN SOFTWARE CONTROL The Fault pin can be controlled manually in software Since the Fault input is shared with a PORT I O pin the PORT pin can be configured as an output by clearing the corresponding TRIS bit When the PORT bit for the pin is cleared the Fault input will be activated Note user should use caution when control ling the Fault inputs in software If the TRIS bit for the Fault pin is cleared and the PORT bit is set high then the Fault input cannot be driven externally 2006 Microchip Technology Inc Preliminary DS70178C page 133 dsPIC30F1010 202X 12 24 PWM Current Limit Pins Each PWM generator can select its own current limit input source from up to12 current limit Fault pins In the FCLCONXx registers each PWM generator has control bits CLSRC lt 3 0 gt that specify the source for its cur rent limit input signal Additionally each PWM genera tor has a CLIEN bit in the PWMCONX register that enables the generation of current limit interrupt requests Each PWM generator has an associated Fault polarity bit CLPOL in the FCLCONx register Figure 12 21 is a diagram of the PWM Current Limit control logic The current limit pins actually serve two different pur poses They can be used to implement either Current Limit PWM mode or Curre
67. using IE bit and meets the prevailing priority level will be able to wake up the processor The processor will process the interrupt and branch to the ISR The Idle status bit in RCON register is set upon wake up Any Reset other than POR will set the Idle status bit On a POR the Idle bit is cleared If Watchdog Timer is enabled then the processor will wake up from Idle mode upon WDT time out The ldle and WDTO status bits are both set Unlike wake up from Sleep there are no time delays involved in wake up from Idle 18 10 Device Configuration Registers The Configuration bits in each device Configuration register specify some of the device modes and are programmed by a device programmer or by using the In Circuit Serial Programming ICSP feature of the device Each device Configuration register is a 24 bit register but only the lower 16 bits of each register are used to hold configuration data There are six Configuration registers available to the user 1 FBS 0xF80000 Boot Code Segment Configuration Register 2 FGS 0xF80004 General Code Segment Configuration Register 3 FOSCEL 0xF80006 Oscillator Selection Configuration Register 4 FOSC 0xF80008 Oscillator Configuration Register 5 FWDT 0xF8000A Watchdog Timer Configuration Register 6 FPOR 0 8000 Power On Reset Configuration Register The placement of the Configuration bits is automati cally handled when you select the device in your dev
68. 0000 0000 0000 0000 LATE 02DC LATE7 LATE6 LATES LATE4 LATES LATE2 LATE1 LATEO 0000 0000 0000 0000 TRISF 02DE TRISF8 TRISF7 TRISF6 0000 0001 1100 0000 PORTF 02E0 RF8 RF7 RF6 0000 0000 0000 0000 LATF 02 2 LATF8 LATF7 LATF6 0000 0000 0000 0000 Note Refer to the dsP C30F Family Reference Manual 0570046 for descriptions of register bit fields 0 0101 3062145 08 eDed 5g 10 sd ABojouyoe diuoo4olN 9002 TABLE 6 2 dsPIC30F2023 PORT REGISTER uiid Addr Bit 15 Bit 14 Bit 13 82 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State TRISA 02 0 TRISA11 TRISA10 TRIS9 TRISA8 0000 1111 0000 0000 PORTA 02C2 RA11 RA10 RA9 RA8 0000 0000 0000 0000 LATA 02C4 LATA11 LATA10 LATA9 LATA8 0000 0000 0000 0000 TRISB 02C6 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRIS6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISBO 0000 1111 1111 1111 PORTB 02C8 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO 0000 0000 0000 0000 LATB 02CA LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2
69. 1 1 1 C DC N OV Z NC Ws Wd Wd Ws 1 1 1 C DC N OV Z 40 INC2 NC2 f f f 2 1 1 C DC N OV Z NC2 f WREG WREG f 2 1 1 C DC N OV Z NC2 Ws Wd Wd Ws 2 1 1 C DC N OV Z 41 IOR OR f f WREG 1 1 N Z OR f WREG WREG f WREG 1 1 N Z OR 1it10 Wn Wd lit10 Wd 1 1 NZ OR Wb Ws Wd Wd Wb IOR Ws 1 1 NZ OR Wb 1it5 Wd Wd Wb lit5 1 1 N Z 42 LAC LAC Wso S1it4 Acc Load Accumulator 1 1 OA OB OAB SA SB SAB 43 LNK LN 1it14 Link frame pointer 1 1 None 44 LSR LSR f f Logical Right Shift f 1 1 C N OVZ LSR f WREG WREG Logical Right Shift f 1 1 C N OV Z LSR Ws Wd Wd Logical Right Shift Ws 1 1 C N OV Z LSR Wb Wns Wnd Wnd Logical Right Shift Wb by Wns 1 1 N Z LSR Wb 1it5 Wnd Wnd Logical Right Shift Wb by lit5 1 1 NZ 45 MAC MAC Wm Multiply and Accumulate 1 1 OA OB OAB Wn Acc Wx Wxd Wy Wyd SA SB SAB AWB Wm Square and Accumulate 1 1 OA OB OAB Wm Acc Wx Wxd Wy Wyd SA SB SAB 46 MOV OV f Wn Move f to Wn 1 1 None OV Move f to f 1 1 N Z OV f WREG Move f to WREG 1 1 N Z OV 1it16 Wn Move 16 bit literal to Wn 1 1 None OV b 1it8 Wn Move 8 bit literal to Wn 1 1 None OV Wn Move Wn to f 1 1 None OV Wso Wdo Move Ws to Wd 1 1 None OV WREG f Move WREG to f 1 1 N Z OV D Wns Wd Move Double from W ns W ns 1 to Wd 1 2 None OV D Ws Wnd Move Double from Ws to W nd 1 W nd 1 2 None 47 MOVSAC MOVSAC Acc Wx Wxd Wy Wyd AWB Prefetch and store accumulator 1 1 None 48 MPY PY Wm Multiply Wm by Wn to
70. 1111 Independent Fault 44 IFLT4 bit 8 CLPOL Current Limit Polarity for PWM Generator X bit 1 The selected current limit source is low active 0 The selected current limit source is high active bit 7 CLMODE Current Limit Mode Enable for PWM Generator X bit 1 Current limit function is enabled 0 Current limit function is disabled O 2006 Microchip Technology Inc Preliminary DS70178C page 117 dsPIC30F1010 202X REGISTER 12 12 FCLCONx PWM FAULT CURRENT LIMIT CONTROL REGISTER CONTINUED bit 6 3 FLTSRC lt 3 0 gt Fault Control Signal Source Select for PWM Generator X bits 0000 Analog Comparator 1 0001 Analog Comparator 2 0010 Analog Comparator 3 0011 Analog Comparator 4 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Shared Fault 1 SFLT1 1001 Shared Fault 2 SFLT2 1020 Shared Fault 3 SFLT3 1011 Shared Fault 4 SFLT4 1100 Reserved 1101 2 Independent Fault 2 IFLT2 1110 2 Reserved 1111 Independent Fault 4 IFLT4 bit 2 FLTPOL Fault Polarity for PWM Generator X bit 1 The selected Fault source is low active 0 The selected Fault source is high active bit 1 0 FLTMOD lt 1 0 gt Fault Mode for PWM Generator x bits 00 The selected Fault source forces PWMxH PWMXxL pins to FLTDAT values latched condition 01 The selected Fault source forces PWMxH PWMXxL pins to FLTDAT values cycle 10 Reserved 11 Fault input is disabled DS70178C page 118
71. 2006 Microchip Technology Inc dsPIC30F1010 202X 12 4 7 CONSTANT OFF TIME PWM Constant Off Time mode is shown in Figure 12 9 Constant Off Time PWM is a variable frequency mode where the actual PWM period is less than or equal to the specified period value The PWM time base is externally reset some time after the PWM signal duty cycle value has been reached and the PWM signal has been deasserted This mode is implemented by enabling the On Time PWM mode Current Reset mode and using the complementary output FIGURE 12 9 CONSTANT OFF TIME PWM Programmed Period External Timer Reset External Timer Reset Period Value PWML Duty Cycle Duty Cycle i Actual Period Note Duty Cycle represents off time 12 4 8 CURRENT RESET PWM MODE Current Reset PWM is shown in Figure 12 10 Current Reset PWM uses a Variable Frequency mode where the actual PWM period is less than or equal to the spec ified period value The PWM time base is externally reset some time after the PWM signal duty cycle value has been reached and the PWM signal has been deas serted Current Reset PWM is a constant on time PWM mode FIGURE 12 10 CURRENT RESET PWM Programmed Period External Timer Reset External Timer Reset PWMH Duty Cycle Duty Cycle Lj i LLL e 4 Actual Period i j Programmed Period 14
72. 4 5 5 5V 1 1 40 C lt 85 C VDD 3 0 3 6V 1 1 40 C lt Ta 85 C VDD 4 5 5 5V 1 1 40 C TA 125 C VDD 4 5 5 5V Note 1 Frequency calibrated at 25 C and 5V TUN bits can be used to compensate for temperature drift 2006 Microchip Technology Inc Preliminary DS70178C page 243 dsPIC30F1010 202X TABLE 21 16 AC CHARACTERISTICS INTERNAL RC JITTER AC CHARACTERISTICS Standard Operating Conditions 3 3V 5 0V 410 unless otherwise stated Operating temperature 40 C TA 85 C for industrial 40 C TA 4125 C for Extended Ed Characteristic Min Typ Max Units Conditions Internal FRC Jitter FRC Freq 6 4 MHz FRC 1 1 25 VDD 3 0 3 6V 4 1 96 25 C VDD 4 5 5 5V 1 1 40 C lt Ta lt 85 VoD 3 0 3 6 1 1 40 C lt Ta lt 85 4 5 5 5 1 1 40 C TA 125 VoD 4 5 5 5V Internal FRC Jitter FRC Freq 9 7 MHz FRC 1 1 25 VDD 3 0 3 6V 1 1 25 C VDD 4 5 5 5V 1 1 40 C lt Ta lt 85 VoD 3 0 3 6V 1 1 40 C lt Ta lt 85 VoD 4 5 5 5V 1 1 40 Ta lt 125 C VpD 4 5 5 5V Internal FRC Jitter FRC Freq 14 55 MHz FRC 1 1 25 C VDD 3 0 3 6V 1 1 25 VDD 4 5 5 5V 1 1
73. 646 5086 Philippines Manila Tel 63 2 634 9065 Fax 63 2 634 9069 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Hsin Chu Tel 886 3 572 9526 Fax 886 3 572 6459 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Thailand Bangkok Tel 66 2 694 1351 Fax 66 2 694 1350 EUROPE Austria Wels Tel 43 7242 2244 39 Fax 43 7242 2244 393 Denmark Copenhagen Tel 45 4450 2828 Fax 45 4485 2829 France Paris Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 10 19 06 Preliminary DS70178C page 284 2006 Microchip Technology Inc
74. 7 V loH 3 0 mA VDD 5V TBD V 2 0 mA VDD 3 3V DO26 OSC2 CLKO VDD 0 7 0 1 3 mA VDD 5V RC or EC Osc mode TBD V 2 0 mA VDD 3 3V Capacitive Loading Specs on Output Pins DO50 2 OSC2 pin 15 pF In HS mode when external clock is used to drive OSC1 DO56 All I O pins and OSC2 50 pF or EC Osc mode DO58 CB SCL SDA 400 pF 12 mode Legend TBD To Be Determined Note 1 Data Typ column is at 5V 25 C unless otherwise stated Parameters for design guidance only are not tested 2 These parameters are characterized but not tested in manufacturing TABLE 21 10 DC CHARACTERISTICS PROGRAM AND EEPROM Standard Operating Conditions 3 3V and 5 0V 410 unless otherwise stated DE CHARACTERISTICS US temperature Dit lt TA 85 C for Industrial 40 C lt TA 125 C for Extended en Symbol Characteristic Min Typ Max Units Conditions Program Flash Memory D130 EP Cell Endurance 10K 100K EAN D131 VPR VDD for Read VMIN 5 5 V VMIN Minimum operating voltage D132 VEB VDD for Bulk Erase 4 5 5 5 V D133 VPEW VDD for Erase Write 3 0 5 5 V D134 TPEW Erase Write Cycle Time 2 ms D135 TRETD Characteristic Retention 40 100 Year Provided no other specifications are violated D136 TEB ICSP Block Erase Time 4 ms D137 IPEW ID
75. 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 7 Unimplemented Read as 0 bit 6 4 U1RXIP lt 2 0 gt UART1 Receiver Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 3 Unimplemented Read as 0 bit 2 0 SPI1IP lt 2 0 gt SPI1 Event Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled 2006 Microchip Technology Inc Preliminary DS70178C page 65 dsPIC30F1010 202X REGISTER 5 12 IPC3 INTERRUPT PRIORITY CONTROL REGISTER 3 U 0 U 0 U 0 U 0 U 0 R W 1 R W 0 R W 0 MI2CIP lt 2 0 gt bit 15 bit 8 U 0 R W 1 R W 0 R W 0 U 0 R W 1 R W 0 R W 0 lt 2 0 gt NVMIP lt 2 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 11 Unimplemented Read as 0 bit 10 8 MI2CIP lt 2 0 gt 2 Master Events Interrupt Priority bits 111 Interrupt is priority 7 highest priority interrupt 001 Interrupt is priority 1 000 Interrupt source is disabled bit 7 Unimplemented Read as 0 bit 6 4 512 1 lt 2 0 gt IC Slave Events Interrupt Priority bits 111
76. 7 or 10 bit address See the 2 programmer s model in Figure 14 1 14 1 2 PIN CONFIGURATION IN 2 MODE 2 has a 2 pin interface pin SCL is clock and pin SDA is data FIGURE 14 1 PROGRAMMER S MODEL I2CRCV 8 bits bit 7 bit 0 I2CTRN 8 bits bit 7 bit 0 I2CBRG 9 bits bit 8 bit 0 I2CCON 16 bits bit 15 bit 0 I2CSTAT 16 bits bit 15 bit 0 I2CADD 10 bits bit 9 bit 0 1413 2 REGISTERS 2 and I2CSTAT are Control and Status regis ters respectively The I2CCON register is readable and writable The lower 6 bits of I2CSTAT are read only The remaining bits of the I2CSTAT are read write I2CRSR is the shift register used for shifting data whereas I2CRCV is the buffer register to which data bytes are written or from which data bytes are read I2CRCV is the receive buffer as shown in Figure 16 1 I2CTRN is the transmit register to which bytes are writ ten during a transmit operation as shown in Figure 16 2 The I2CADD register holds the slave address A status bit ADD10 indicates 10 bit Address mode The I2CBRG acts as the Baud Rate Generator BRG reload value In receive operations I2CRSR and I2CRCV together form a double buffered receiver When I2CRSR receives a complete byte it is transferred to I2CRCV and an interrupt pulse is generated During transmission the I2CTRN is not double buffered Note Following a Restart condi
77. ADCBUF lt 11 0 gt The registers are 10 bits wide but are read into differ ent format 16 bit words The buffers are read only Each analog input has a corresponding data output register This module DOES NOT include a circular data buffer or FIFO Because the conversion results may be produced in any order such schemes will not work since there would be no means to determine which data is in a specific location The SAR write to the buffers is synchronous to the ADC clock Reads from the buffers will always have valid data assuming that the data ready interrupt has been processed If a buffer location has not been read by the software and the SAR needs to overwrite that location the previous data is lost Reads from the result buffer pass through the data for matter The 10 bits of the result data are formatted into a 16 bit word FIGURE 16 2 Critical Edge PWM b ee Desired sample point e Late sample yields zero data Measuring peak inductor current is very important 16 5 Application Information The ADC module implements a concept based on Conversion Pairs In power conversion applications there is a need to measure voltages and currents for each PWM control loop The ADC module enables the sample and conversion process of each conversion pair to be precisely timed relative to the PWM signals In a user s application circuit the PWM signal enables atransistor which allows an inductor
78. Accumulator 1 1 OA OB OAB Wn Wx Wxd Wy Wyd SA SB SAB PY Wm Square Wm to Accumulator 1 1 OA OB OAB Wm Acc Wx Wxd Wy Wyd SA SB SAB 49 MPY N MPY N Wm Multiply Wm by Wn to Accumulator 1 1 None Wn Acc Wx Wxd Wy Wyd 50 MSC MSC Wm Multiply and Subtract from Accumulator 1 1 OA OB OAB Wm Acc Wx Wxd Wy Wyd SA SB SAB AWB 51 MUL MUL SS Wb Ws Wnd Wnd 1 Wnd signed Wb signed Ws 1 1 None UL SU Wb Ws Wnd Wnd 1 Wnd signed Wb unsigned Ws 1 1 None UL US Wb Ws Wnd Wnd 1 Wnd unsigned Wb signed Ws 1 1 None 01 00 Wb Ws Wnd Wnd 1 Wnd unsigned Wb 1 1 None unsigned Ws UL SU Wb 1it5 Wnd Wnd 1 Wnd signed Wb unsigned lit5 1 1 None UL UU Whb 1it5 Wnd Wnd 1 Wnd unsigned Wb 1 1 None unsigned lit5 UL f W3 W2 f WREG 1 1 None DS70178C page 224 Preliminary 2006 Microchip Technology Inc TABLE 19 2 dsPIC30F1010 202X INSTRUCTION SET OVERVIEW CONTINUED B of Maia Assembly Syntax Description 52 Negate Accumulator 1 1 OA OB OAB SA SB SAB NEG f f f 1 1 1 C DC N OV Z NEG f WREG WREG f 1 1 1 C DC N OV Z NEG Ws Wd Wd Ws 1 1 1 C DC N OV Z 53 NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None
79. Analog Comparator Module Analog Comparator 1 gt CMP1x X 0000 CMP2x Analog Comparator 2 m Analog Comparator 2 oie Analog Comparator 4 ja Shared Fault 1 EU SFLT2Dg Shared Fault 2 SFLT3Dg Shared Fault 3 SFLTAQ Shared Fault 4 101 IFLT2 Independent Fault 2 TE IFLT4 Independent Fault 5a FLTSRC lt 3 0 gt Fault Mode Selection Logic FLTMOD lt 1 0 gt FLTMOD 1 0 00 FLTSTAT signal is latched until Reset in software FLTMOD lt 1 0 gt 01 FLTSTAT signal is Reset by PTMR every PWM cycle FLTMOD lt 1 0 gt 11 FLTSTAT signal is disabled DS70178C page 132 Preli minary PWMXxH L 2006 Microchip Technology Inc dsPIC30F1010 202X 12 23 1 FAULT INTERRUPTS The FLTIENx bits in the PWMCONx registers deter mine if an interrupt will be generated when the FLTx input is asserted high The FLTMOD bits in the FCLCONXx register determines how the PWM genera tor and its outputs respond to the selected Fault input The FLTDAT lt 1 0 gt bits in the IOCONx registers supply the data values to be assigned to the PWMxH L pins in the advent of a Fault The Fault pin logic can operate separately from the PWM logic as an external interrupt pin If the faults are disabled from affecting the PWM generators in the FCLCONx register then the Fault pin can be used as a gene
80. Bit 4 Bit 3 Bit 2 Bit 1 BitO All Resets ADCON 0300 ADON ADSIDL GSWTRG FORM EIE ORDER SEQSAMP ADCS lt 2 0 gt 0009 ADPCFG 0302 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFGO 0000 Reserved 0304 0000 ADSTAT 0306 P5RDY P4RDY P3RDY P2RDY P1RDY PORDY 0000 ADBASE 0308 ADBASE 15 1 0000 ADCPCO 030A IRQEN1 PEND1 SWTRG1 TRGSRC1 lt 4 0 gt IRQENO PENDO SWTRGO TRGSRCO 4 0 0000 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3 lt 4 0 gt IRQEN2 PEND2 SWTRG2 TRGSRC2 lt 4 0 gt 0000 ADCPC2 030E 5 PEND5 SWTRG5 TRGSRC5 lt 4 0 gt IRQEN4 PEND4 SWTRG4 TRGSRC4 lt 4 0 gt 0000 Reserved 0310 3 0000 031E ADCBUFO 0320 ADC Data Buffer 0 XXXX ADCBUF1 0322 Data Buffer 1 XXXX ADCBUF2 0324 ADC Data Buffer 2 XXXX ADCBUF3 0326 ADC Data Buffer 3 XXXX ADCBUF4 0328 ADC Data Buffer 4 ADCBUF5 032A cx ADC Data Buffer 5 XXXX ADCBUF6 032C ADC Data Buffer 6 XXXX ADCBUF7 032E ADC Data Buffer 7 XXXX ADCBUF8 0330 ADC Data Buffer 8 XXXX ADCBUF9 0332 ADC Data Buffer 9 XXXX ADCBUF10 0334 Data Buffer 10 ADCBUF11 0336 ADC Data Buffer 11 XXXX Reserved 0338 0000 037E 06 0101 3062145 dsPIC30F1010 202X 17 0 SMPS COMPARATOR MODULE Note This data sheet summarizes features of this group of
81. CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Habour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 2401 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shanghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Shunde Tel 86 757 2839 5507 Fax 86 757 2839 5571 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xian Tel 86 29 8833 7250 Fax 86 29 8833 7256 ASIA PACIFIC India Bangalore Tel 91 80 4182 8400 Fax 91 80 4182 8422 India New Delhi Tel 91 11 4160 8631 Fax 91 11 4160 8632 India Pune Tel 91 20 2566 1512 Fax 91 20 2566 1513 Japan Yokohama Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Gumi Tel 82 54 473 4301 Fax 82 54 473 4302 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Malaysia Penang Tel 60 4 646 8870 Fax 60 4
82. CB Bus Capacitive 400 pF Loading Note 1 Maximum pin capacitance 10 pF for all 2 pins for 1 MHz mode only DS70178C page 262 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X TABLE 21 33 10 BIT HIGH SPEED A D MODULE SPECIFICATIONS Standard Operating Conditions 3 3V and 5 0V 11096 unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt Ta lt 85 C for Industrial 40 C lt TA 125 C for Extended oda Symbol Characteristic Min Typ Max Units Conditions Device Supply ADO1 AVDD Module VDD Supply Greater of Lesser of V 0 3 VDD 0 3 or 2 7 or 5 5 ADO2 55 Module Vss Supply Vss 0 3 VSS 0 3 V Analog Input AD10 Full Scale Input Span Vss VDD V AD11 VIN Absolute Input Voltage AVss 0 3 0 3 V AD12 Leakage Current 0 001 0 244 VINL AVSS OV AVDD 5V Source Impedance 1 kQ AD13 Leakage Current 0 001 0 244 AVSS OV AVDD 3 3V Source Impedance 1 kQ AD17 RIN Recommended Impedance 1K Q Of Analog Voltage Source DC Accuracy AD20 Resolution 10 data bits bits AD21 Integral Nonlinearity 0 5 lt 1 56 VINL 55 OV AVDD 5V AD21A Integral Nonlinearity 0 5 lt 1 LSb VINL 55 OV AVDD 3 3V AD22 Differential Nonlinearity
83. Conditions 50 Bus Capacitive Loading 400 pF Legend TBD To Be Determined Note 1 BRG is the value of the IC Baud Rate Generator Refer to the Inter Integrated Circuit I2C section in the dsPIC30F Family Reference Manual DS70046 2 Maximum pin capacitance 10 pF for all 2 pins for 1 MHz mode only FIGURE 21 18 IC BUS START STOP BITS TIMING CHARACTERISTICS SLAVE MODE SCL Stop Start Condition Condition FIGURE 21 19 IC BUS DATA TIMING CHARACTERISTICS SLAVE MODE 1820 1611 ee 1821 2006 Microchip Technology Inc Preliminary DS70178C page 261 dsPIC30F1010 202X TABLE 21 32 2 BUS DATA TIMING REQUIREMENTS SLAVE MODE Standard Operating Conditions 3 3V and 5 0V 10 unless otherwise stated Ae GNARACTEBISTIGS eer temperature ae lt TA lt 85 C for Industrial 40 C lt TA 125 for Extended E Symbol Characteristic Min Max Units Conditions 1510 TLO SCL Low Time 100 kHz mode 4 7 us Device must operate at a minimum of 1 5 MHz 400 kHz mode 1 3 us Device must operate at a minimum of 10 MHz 1 MHz mode 0 5 us 1511 THI SCL High Time 100 kHz mode 4 0 us Device must operate at a minimum of 1 5 MHz 400 kHz mod
84. DC N OVZ DEC2 Ws Wd Wd Ws 2 1 1 C DC N OV Z 28 DISI DISI 11614 Disable Interrupts for instruction cycles 1 1 None 29 DIV S Wm Wn Signed 16 16 bit Integer Divide 1 18 N Z C OV DIV SD Wm Wn Signed 32 16 bit Integer Divide 1 18 N Z C OV DIV U Wm Wn Unsigned 16 16 bit Integer Divide 1 18 N Z C OV DIV UD Wm Wn Unsigned 32 16 bit Integer Divide 1 18 N Z C OV 30 DIVF DIVF Wm Wn Signed 16 16 bit Fractional Divide 1 18 N Z C OV 31 DO DO lit14 Expr Do code to PC Expr lit14 1 times 2 2 None DO Wn Expr Do code to PC Expr Wn 1 times 2 2 None 32 ED ED Wm Wm Acc Wx Wy Wxd Euclidean Distance no accumulate 1 1 OA OB OAB SA SB SAB 33 EDAC EDAC Wm Wm Wx Wy Wxd Euclidean Distance 1 1 OA OB OAB SA SB SAB 2006 Microchip Technology Inc Preliminary DS70178C page 223 dsPIC30F1010 202X TABLE 19 2 INSTRUCTION SET OVERVIEW CONTINUED B of Assembly Syntax Description RS Siamas rags 34 EXCH EXCH Wns Wnd Swap Wns with Wnd 1 1 35 FBCL FBCL Ws Wnd Find Bit Change from Left MSb Side 1 1 36 FF1L FF1L Ws Wnd Find First One from Left MSb Side 1 1 C 37 FF1R FF1R Ws Wnd Find First One from Right LSb Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None 39 INC NC f f f 1 1 1 C DC N OV Z NC f WREG WREG f
85. F EN Receive Register 0000 0000 0000 0000 I2CTRN 0202 Transmit Register 0000 0000 1111 1111 I2CBRG 0204 pus Baud Rate Generator 0000 0000 0000 0000 2 0206 2 m l2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT PEN SEN 0001 0000 0000 0000 l2CSTAT 0208 ACKSTAT TRSTAT BCL GCSTAT ADD10 IWCOL l2COV DA P S RW RBF TBF 0000 0000 0000 0000 I2CADD 020A Address Register 0000 0000 0000 0000 Note Refer to the dsP C30F Family Reference Manual 0570046 for descriptions of register bit fields 0 0101 3062145 dsPIC30F1010 202X NOTES RECS C M B H HH JH HJ DS70178C page 160 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X 15 0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER UART MODULE Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046 The Universal Asynchronous Receiver Transmitter UART module is one of the serial I O modules available in the dsPIC30F1010 202X device family The UART is a full duplex asynchronous sys
86. Fault and current limit source selection fields in the FCLCONXx registers FLTSRC lt 3 0 gt and CLSRC lt 3 0 gt control multiplexers in each PWM generator module The control multiplexers select the desired Fault and current limit signals for their respective modules The selected Fault and current limit signals are also avail able to the ADC module as trigger signals that initiate ADC sampling and conversion operations 12 27 PWM Output Override Priority If the PWM module is enabled the priority of PWMx pin ownership is PWM Generator lowest priority Output Override Current Limit Override Fault Override PENx GPIO PWM ownership highest priority If the PWM module is disabled the GPIO module controls the PWMx pins o RON 12 28 Fault and Current Limit Override Issues with Dead Time Logic The PWMxH and PWMXxL outputs are immediately driven low deasserted as specified by the CLDAT lt 1 0 gt and the FLTDAT lt 1 0 gt bits when a current limit or a Fault event occurs The override data is gated with the PWM signals going into the dead time logic block and at the output of the PWM module just ahead of the PWM pin output buffers Many applications require fast response to current shutdown for accurate current control and or to limit circuitry damage to Fault currents Some applications will set the complementary PWM outputs high in synchronous rectifier designs when a Fault or current limit event occurs If
87. Free Dynamic m 73 dB Range AD33 FNYQ Input Signal Bandwidth 0 5 MHz AD34 Effective Number of Bits 9 4 bits Note 1 Because the sample caps will eventually lose charge clock rates below 10 kHz can affect linearity performance especially at elevated temperatures 2 The A D conversion result never decreases with an increase in the input voltage and has no missing codes FIGURE 21 20 A D CONVERSION TIMING PER INPUT Trigger Pulse Tconv TAD NAAU A D Clock A D Data ADBUFx OdDaa 2 NewDaa CONV DS70178C page 264 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X TABLE 21 34 COMPARATOR OPERATING CONDITIONS Symbol Characteristic Min Typ Max Units Comments VDD Voltage Range 3 0 3 6 V Operating range of 3 0 V 3 6V VDD Voltage Range 4 5 5 5 V Operating range of 4 5 V 5 5 V TEMP Temperature Range 40 105 that junction temperature exceed 125 C under these ambient conditions TABLE 21 35 COMPARATOR AC AND DC SPECIFICATIONS Standard Operating Conditions unless otherwise stated Operating temperature 40 C lt TA 105 Symbol Characteristic Min Typ Max Units Comments VIOFF Input offset
88. Gate Interrupt Es Operation During Sleep Mode Timer Prescaler aa Timer2 3 Register Map DS70178C page 280 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X Timing Characteristics A D Conversion 10 Bit High speed CHPS 01 SIMSAM 0 ASAM 0 SSRC 000 264 Band Gap Start up Time 248 CLKO and I O External nete 240 Bus Data Master 259 Slave Mode Bus Start Stop Bits Master 259 Slave Mode 261 Input Capture CAPX 251 Motor Control PWM Module 258 SPI Module Master Mode 0 254 Master Mode 1 255 Slave Mode 0 256 Slave Mode 1 257 Type A B and C Timer External Clock 249 Watchdog Timer eene 246 Timing Diagrams PWM 104 Time out Sequence on Power up MCLR Not Tied to VDD Case 1 211 Time out Sequence on Power up MCLR Not Tied to VDD Case 2 212 Ti
89. IPL3 bit CORCON 3 is always clear when interrupts are being pro cessed It is set only during execution of traps The RETFIE Return from Interrupt instruction will unstack the Program Counter and status registers to return the processor to its state prior to the interrupt sequence 5 5 Alternate Vector Table In Program Memory the IVT is followed by the AIVT as shown in Figure 5 1 Access to the Alternate Vector Table is provided by the ALTIVT bit in the INTCON2 register If the ALTIVT bit is set all interrupt and excep tion processes will use the alternate vectors instead of the default vectors The alternate vectors are organized in the same manner as the default vectors The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a sup port environment without requiring the interrupt vec tors to be reprogrammed This feature also enables switching between applications for evaluation of different software algorithms at run time If the AIVT is not required the program memory allo cated to the AIVT may be used for other purposes AIVT is not a protected section and may be freely programmed by the user 5 6 Fast Context Saving A context saving option is available using shadow reg isters Shadow registers are provided for the DC N OV Z and C bits in SR and the registers WO through W3 The shadows are only one level deep The shadow registers are accessible
90. IRQ is indicated by the flag bit being equal to a 1 in an IFSx register The IRQ will cause an interrupt to occur if the corresponding bit in the interrupt enable IECx register is set For the remainder of the instruction cycle the priorities of all pending interrupt requests are evaluated If there is a pending IRQ with a priority level greater than the current processor priority level in the IPL bits the processor will be interrupted The processor then stacks the current Program Counter and the low byte of the processor STATUS Register SRL as shown in Figure 5 2 The low byte of the STATUS register contains the processor priority level at the time prior to the beginning of the interrupt cycle The processor then loads the priority level for this interrupt into the STATUS register This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine ISR FIGURE 5 2 INTERRUPT STACK FRAME 0x0000 15 0 PC lt 15 0 gt SRL PC lt 22 16 Free Word amp W15 after CALL W15 before CALL Stack Grows Towards Higher Address POP W15 PUSH W15 Note 1 The user can always lower the priority level by writing a new value into SR The Interrupt Service Routine must clear the interrupt flag bits in the IFSx register before lowering the processor interrupt priority in order to avoid recursive interrupts 2 The
91. Microchip Technology Inc Preliminary DS70178C page 181 dsPIC30F1010 202X 16 6 Reverse Conversion Order The ORDER control bit in the ADCON register when set reverses the order of the input pair conversion pro cess Normally ORDER 0 the even numbered input of an input pair is converted first and then the odd numbered input is converted If ORDER 1 the odd numbered input pin of an input pair is converted first followed by the even numbered pin This feature is useful when using voltage control modes and using the early interrupt capability EIE 1 These features enable the user to minimize the time period from actual acquisition of the feedback ADC data to the update of the control output PWM This time from input to output of the control system determines the overall stability of the control system 16 7 Simultaneous and Sequential Sampling in a pair The inputs that have dedicated Sample and Hold S amp H circuits are sampled when their specified trigger events occur The inputs that share the common sam ple and hold circuit are sampled in the following manner 1 If the SEQSAMP bit and the common shared sample and hold circuit is NOT busy then the shared S amp H will sample their specified input at the same time as the dedicated S amp H This action provides Simultaneous sample and hold functionality 2 If the SEQSAMP bit and the shared S amp H is currently busy with a conversi
92. Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X REGISTER 12 13 TRIGx PWM TRIGGER COMPARE VALUE REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 TRGCMP lt 15 8 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 U 0 U 0 TRGCMP lt 7 3 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 3 TRGCMP lt 15 3 gt Trigger Control Value bits Register contains the compare value for PWMx time base for generating a trigger to the ADC module for initiating a sample and conversion process or generating a trigger interrupt bit 2 0 Unimplemented Read as 0 Note 1 The minimum usable value for this register is 0x0008 A value of 0x0000 does not produce a trigger If the TRIGx value is being calculated based on duty cycle value you must ensure that a minimum TRIGx value is written into the register at all times 2006 Microchip Technology Inc Preliminary DS70178C page 119 dsPIC30F1010 202X REGISTER 12 14 LEBCONx LEADING EDGE BLANKING CONTROL REGISTER R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB lt 9 8 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 U 0 U 0 U 0 LEB lt 7 3 gt bit 7 bit 0 Legend
93. R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 15 PHR PWMH Rising Edge Trigger Enable bit 1 Rising edge of PWMH will trigger LEB counter 0 LEB ignores rising edge of PWMH bit 14 PHL PWMH Falling Edge Trigger Enable bit 1 Falling edge of PWMH will trigger LEB counter 0 LEB ignores falling edge of PWMH bit 13 PLR PWML Rising Edge Trigger Enable bit 1 Rising edge of PWML will trigger LEB counter 0 LEB ignores rising edge of PWML bit 12 PLF PWML Falling Edge Trigger Enable bit 1 Falling edge of PWML will trigger LEB counter 0 LEB ignores falling edge of PWML bit 11 FLTLEBEN Fault Input Leading Edge Blanking Enable bit 1 Leading Edge Blanking is applied to selected Fault Input 0 Leading Edge Blanking is not applied to selected Fault Input bit 10 CLLEBEN Current Limit Leading Edge Blanking Enable bit 1 Leading Edge Blanking is applied to selected Current Limit Input 0 Leading Edge Blanking is not applied to selected Current Limit Input bit 9 3 LEB Leading Edge Blanking for Current Limit and Fault Inputs bits Value is 8 nsec increments bit 2 0 Unimplemented Read as 0 DS70178C page 120 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X 12 4 Module Functionality The PS PWM module is a very high speed design that provides capabilities not found in other PWM genera tors The modu
94. R W 0 HC R W 0 R W 0 HC R W 0 R W 0 R W 0 R W 0 R W 0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSELO STSEL bit 7 bit 0 Legend U Unimplemented bit read as 0 R Readable bit n Value at POR W Writable bit 1 Bit is set HC Hardware Cleared 0 Bit is cleared HS Hardware Select x Bit is unknown bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 8 bit 7 bit 6 bit 5 bit 4 bit 3 UARTEN UART1 Enable bit 1 UART1 enabled all UART1 pins are controlled by UART1 as defined by UEN lt 1 0 gt 0 UART1 disabled all UART1 pins are controlled by PORT latches UART1 power consumption minimal Unimplemented Read as 0 USIDL Stop in Idle Mode bit 1 Discontinue module operation when device enters Idle mode 0 Continue module operation in Idle mode IREN IrDA Encoder and Decoder Enable bit 1 IrDA encoder and decoder enabled 0 IrDA encoder and decoder disabled Note This feature is only available for the 16x BRG mode BRGH Unimplemented Read as 0 ALTIO UART Alternate I O Selection bit 1 UART communicates using U1ATX and U1ARX I O pins 0 UART communicates using U1TX and U1RX I O pins Unimplemented Read as 0 WAKE Wake up on Start bit Detect During Sleep Mode Enable bit 1 UART1 will continue to sample the U1RX pin interrupt generated on falling edge bit cleared in hardware on following rising edge 0 No wake up enabled
95. TdiV2scL SCKx Edge SP41 TscH2diL Hold Time of SDIx Data Input 20 ns TscL2diL to SCKx Edge SP50 TssL2scH SSxJ to SCKxl or SCKxT input 120 ns TssL2scL SP51 TssH2doZ SST to SDOx Output 10 50 ns SP52 2 SSxT after SCKx Edge 1 5 m ns TscL2ssH 4 40 SP60 TssL2doV SDOx Data Output Valid after 50 ns SSx Edge Note 1 These parameters are characterized but not tested in manufacturing 2 Datain Typ column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 3 The minimum clock period for SCK is 100 ns Therefore the clock generated in Master mode must not violate this specification 4 Assumes 50 pF load on all SPI pins DS70178C page 258 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X FIGURE 21 16 2 BUS START STOP BITS TIMING CHARACTERISTICS MASTER MODE SCL Start Stop Condition Condition Note Refer to Figure 21 1 for load conditions FIGURE 21 17 IC BUS DATA TIMING CHARACTERISTICS MASTER MODE IM20 ia MT ad Note Refer to Figure 21 1 for load conditions 2006 Microchip Technology Inc Preliminary DS70178C page 259 dsPIC30F1010 202X TABLE 21 31 2 BUS DATA TIMING REQUIREMENTS MASTER MODE
96. Technology Low power high speed Flash technology 3 3V 5 0V operation 10 Industrial and Extended temperature ranges Low power consumption o c lt at aw 0 2 86622 5 5 4 n a 5 Product 4 E gt gt 5 E lt 2 5 lt 2 56 e o E a o dsPIC30F1010 28 SDIP 6K 256 2 0 1 1 1 1 2 1 3 6 ch 2 21 dsPIC30F1010 28 SOIC 6K 256 210 1 1 1 1 2x2 1 3 6 ch 2 21 dsPIC30F1010 28 QFN S 6K 256 210 1 1 1 1 2x2 1 3 6 ch 2 21 dsPIC30F2020 28 SDIP 12K 512 3 1 2 1 1 1 4x2 1 5 8ch 4 21 dsPIC30F2020 28 SOIC 12K 512 3 1 2 1 1 1 4x2 1 5 8 ch 4 21 dsPIC30F2020 28 QFN S 12K 512 3 1 2 1 1 1 4x2 1 5 8 ch 4 21 dsPIC30F2023 44 QFN 12K 512 3 1 2 1 1 1 4x2 1 5 12ch 4 35 dsPIC30F2023 44 TQFP 12K 512 3 1 2 1 1 1 4x2 1 5 12 ch 4 35 DS70178C page 2 Preliminary 2006 Microchip Technology Inc dsPIC30F1010 202X Pin Diagrams 28 Pin SDIP and SOIC MCLR 28H ANO CMP1A CN2 RBO 2 27 AVss AN1 CMP1B CN3 RB1 3 26H PWMI1L REO AN2 CMP1C CMP2A CN4 RB2 14 25 PWM1H RE1 AN3 CMP1
97. The UART module includes a dedicated 16 bit Baud Rate Generator The U1BRG register controls the period of a free running 16 bit timer Equation 15 1 shows the formula for computation of the baud rate with BRGH 0 EQUATION 15 1 UART BAUD RATE WITH BRGH 0 1 2 3 Baud Rate 2 16 UIBRG 1 986 16 Baud Rate Note 1 denotes the instruction cycle clock frequency Fosc 2 2 Assuming external oscillator with fre quency of 15 MHz and PLL disabled is 7 5 MHz 3 Assuming external oscillator with fre quency of 15 MHz and PLL enabled Fcy is 30 MHz Example 15 1 shows the calculation of the baud rate error for the following conditions Foy 7 5 MHz Desired Baud Rate 9600 The maximum baud rate BRGH 0 possible is 16 for UTBRG 0 and the minimum baud rate possible is Fcy 16 65536 Equation 15 2 shows the formula for computation of the baud rate with BRGH 1 EQUATION 15 2 UART BAUD RATE WITH BRGH 14 23 Fcv Baud Rate 4 UIBRG 1 Fcv IBRG2 G 4 Baud Rate Note 1 Fcy denotes the instruction cycle clock frequency 2 Assuming external oscillator with fre quency of 15 MHz and PLL disabled is 7 5 MHz 3 Assuming external oscillator with fre quency of 15 MHz and PLL enabled is 30 MHz The maximum baud rate BRGH 1 possibl
98. U 0 U 0 R 0 R 0 R 0 R 0 ILR lt 3 0 gt bit 15 bit 8 U 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 VECNUM lt 6 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 12 Unimplemented Read as 0 bit 11 8 ILR New CPU Interrupt Priority Level bits 1111 CPU Interrupt Priority Level is 15 0001 CPU Interrupt Priority Level is 1 0000 CPU Interrupt Priority Level is 0 bit 7 Unimplemented Read as 0 bit 6 0 VECNUM Vector Number of Pending Interrupt bits 0111111 Interrupt Vector pending is number 135 0000001 Interrupt Vector pending is number 9 0000000 Interrupt Vector pending is number 8 DS70178C page 74 Preliminary 2006 Microchip Technology Inc diuoo49lN 9002 Aseuiwijaid 9 eDed 59 L07Sd TABLE 5 2 INTERRUPT CONTROLLER REGISTER MAP uid ADR Bit 15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit 8 Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit1 BitO Reset State NTCON 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIVOERR MATHERR ADDRERR STKERR OSCFAIL 0000 000
99. WAGU modulo address ing will be disabled However modulo addressing will continue to function in the X RAGU If Bit Reversed Addressing has already been enabled by setting the BREN XBREV lt 15 gt bit then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit reversed pointer FIGURE 4 2 BIT REVERSED ADDRESS EXAMPLE Sequential Address 15 14 13 12 b11 b10 b9 b8 b7 bs b4 ba b2 b1 0 Bit Locations Swapped Left to Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 bs b7 b6 b5 bt 2 b3 b4 0 A Pivot Point Bit Reversed Address XB 0x0008 for a 16 word Bit Reversed Buffer 2006 Microchip Technology Inc Preliminary DS70178C page 45 dsPIC30F1010 202X TABLE 4 2 BIT REVERSED ADDRESS SEQUENCE 16 ENTRY Normal Bit Reversed Address Address A3 A2 A1 0 Decimal A3 A2 A1 0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 I 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 i 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 T 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 i 1 0 al 13 1 1 0 0 12 0 0 1 1 3 1 1 0 T 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15
100. __ RAW PWMH RAW PWML E PWMH OUTPUT PWML OUTPUT DS70178C page 128 Preliminary O 2006 Microchip Technology Inc dsPIC30F1010 202X 12 15 Configuring a PWM Channel Example 12 1 is a code example for configuring PWM channel 1 to operate in complementary mode at 400 kHz with a dead time value of approximately 64 nsec It is assumed that the dsPIC30F1010 202X is operating on the internal fast RC oscillator with PLL in the high frequency range 14 55 MHz input to the PLL assuming industrial temperature rated part 12 16 Speed Limits of PWM Output Circuitry The PWM output I O buffers and any attached circuits such as FET drivers and power FETs have limited slew rate capability For very small PWM duty cycles the PWM output signal is low pass filtered no pulse makes it through all of the circuitry A similar effect happens for duty cycle values near 100 Before 100 duty cycle is reached the output PWM signal appears to saturate at 100 Users need to take such behavior into account in their applications In normal power conversion applications duty cycle values near 0 or 100 are avoided because to reach these values is to operate in a Dis continuous mode or a Saturated mode where the control loop may be non functional 12 17 PWM Special Event Trigger The PWM module has a Special Event Trigger that allows A D conversions to be synchronized to the PWM time base The A D s
101. be used to wake up