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FREESCALE SEMICONDUCTOR MC13211/212/213/214 Manual

1. Analog p gt VODA 2nd IF Mixer Decimation Baseband Matched Regulator gt VBATT E Filter Mixer Filter 1st IF Mixer 1 MHz PMA j Power Up Digital LNA IF 65 MHz D 2 amp 2 m Control Regulator L VDDINT Y S a Packet j Logic DDH z eka igital CCA TE sl Processor j Digital S BEI j Regulator H VDDD j2 amp J t H amp KA TN j C ystal i j Regulator RFIN P j T ji VCO ji VDDVCO PAO_P Tik Receive Receive RAM j Regulator gt RFIN_M EIN Packet RAM j Arbiter PAO M AGC CT Bias Sequence f RATAEN Manager um Programmable Control Logic VDDLO2 gt l 4 Prescaler gt 24 Bit Event Timer k CE 1 MOSI gt MISO 4 Programmable zu je SPICLK Timer Comparators z z K ATTN ries ka Uu RST Crystal a Oscillator XTAL1 o XTAL2 k 16 MHz 7 po CPOL Synthesizer Transmit GPIO2 gt Packet RAM 2 MK GPIO3 GPIO4 GPIO5 1 Transmit Pu GPIO6 Packet RAM 1 l gt GPIO7 2 45 GHz VDDLO1 VCO A IRQ Transmit RAM Symbol j gt RO Arbiter gt Generation Arbiter FAO Pe PA Ph mm dul T DAE PAOM ase Shift Modulator 2 FCS Header Generation Generation Figure
2. Characteristic Symbol Min Typ Max Unit Power Spectral Density 40 to 85 C Absolute limit 47 dBm Power Spectral Density 40 to 85 C Relative limit 47 Nominal Output Power Pout 4 1 2 dBm Maximum Output Power 3 dBm Error Vector Magnitude EVM 18 35 Ouput Power Control Range 30 dB Over the Air Data Rate 250 kbps 2nd Harmonic 43 dBc 3rd Harmonic j 45 dBc 1 SPI Register 12 is default value of OxOOBC which sets output power to nominal 1 dBm typical Z SPI Register 12 programmed to OxOOFC which sets output power to maximum 3 Measurements taken at output of evaluation circuit set for maximum power out VDDA L10 4 4 nH Z4 3 1 011 2 5 U4 1 0pF 4 PICI L11 IC2 aan LDB212G4005C 001 GUT Von h PAO_M OUT1 5 f PAO P ake IN Seli GND If zi 10pF 4 10pF 2 BERIT L13 ved Tys RE S UPG20127K E2 4 SMA edge Recep Blas 3 3nH z5 L12 2615 5 3 1 2 2nH 1 8pF j MC1321x deas 2 j e 1 8pF za a elem 4 L14 HA LDB212G4005C 001 3 3nH Figure 26 RF Parametric Evaluation Circuit MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 49 6 3 MCU Electrical Characteristics 6 3 1 MCU DC Characteristics Table 11 MCU DC Characteristics Temperature Range 40 to 85 C Amb
3. Figure 22 SCI Transmitter MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 39 FROM RxD1 PIN INTERNAL BUS 16 Y BAUD RATE CLOCK DIVIDE BY 16 READ ONLY SCID Rx BUFFER DATA RECOVERY Cu T RECEIVE SHIFT REGISTER LSB T START 7 J 6 J 5 J 4 J 31211 SHIFT DIRECTION Rx INTERRUPT REQUEST ERROR INTERRUPT REQUEST 2 4 4 di Y LOOPS gt sINGLE WIRE WAKE gt WAKEUP EWI RSRG LOOP CONTROL LT A LOGIC FROM TRANSMITTER p RDRF RIE IDLE ILIE M ORIE 5 DD gt FE j FEIE Uwe I Y Y NEIE PE PARITY BE A CHECKING PEIE 1 Figure 23 SCI Receiver MC13211 212 213 214 Technical Data Rev 0 0 40 Freescale Semiconductor 5 7 6 Inter Integrated Circuit IIC Module The HCS08 microcontroller provides one inter integrated circuit IIC module for communication with other integrated circuits The two pins associated with this module SDA and SCL share port C pins 2 and 3 respectively All functionality as described in this section is available on HCS08 When the IIC i
4. PTEO TxD1 PORT F See Note 1 PORT G See Note 1 X PTG2 EXTAL PTG1 XTAL PTGO BKGD MS MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 25 5 2 MCU Modes of Operation The MCU has multiple operational modes to facilitate maximum system performance while also providing low power modes In the MC1321x the MCU can use the following modes e Run Wait e Stop2 e Stop3 NOTE The MCU can also be programmed for Stop1 mode but this mode IS NOT USABLE The reset to the modem function is controlled by an MCU GPIO and the GPIO state must be maintained during the MCU stop condition Stop1 mode does not control I O states as required during modem power down condition 5 2 1 Run Mode This is the normal operating mode for the HCS08 This mode is selected when the BKGD MS pin is high at the rising edge of reset In this mode the CPU executes code from internal memory with execution beginning at the address fetched from memory at FFFE FFFF after reset 5 2 2 Wait Mode Wait Mode is entered by executing a WAIT instruction Upon execution of the WAIT instruction the CPU enters a low power state in which it is not clocked The I bit in CCR is cleared when the CPU enters the wait mode enabling interrupts When an interrupt request occurs the CPU exits the wait mode and resumes processing beginning with the stacking operations leading to the i
5. 100 90 80 70 60 50 Input Pow er dBm Figure 8 Reported Power Level versus Input Power in Clear Channel Assessment Mode 15 25 35 45 55 65 802 15 4 Accuracy and Range Requirements Reported Power Level dBm 75 85 85 75 65 55 45 35 25 15 Input Power Level dBm Figure 9 Reported Power Level Versus Input Power for Energy Detect or Link Ouality Indicator 45 Transmit Path Description For the transmit path the TX data that was previously written to the internal RAM is retrieved packet mode or the TX data is clocked in via the SPI stream mode formed into packets per the 802 15 4 PHY spread and then up converted to the transmit freguency If the 802 15 4 modem is in packet mode data is processed as an entire packet The data is first loaded into the TX buffer The MCU then reguests that the modem transmit the data The MCU is notified via an interrupt when the whole packet has successfully been transmitted MC13211 212 213 214 Technical Data Rev 0 0 18 Freescale Semiconductor In streaming mode the data is fed to the 802 15 4 modem on a word by word basis with an interrupt serving as a notification that the 802 15 4 modem is ready for more data This continues until the whole packet is transmitted In both modes a two byte FCS is calculated in hardware from the payload data and appended to the packet This done without
6. The HCS08 includes two independent serial communications interface SCI modules sometimes called universal asynchronous receiver transmitters UARTS Typically these systems are used to connect to the RS232 serial input output I O port of a personal computer or workstation and they can also be used to communicate with other embedded controllers A flexible 13 bit modulo based baud rate generator supports a broad range of standard baud rates beyond 115 2 kbaud Transmit and receive within the same SCI use a common baud rate and each SCI module has a separate baud rate generator This SCI system offers many advanced features not commonly found on other asynchronous serial I O peripherals on other embedded controllers The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection Hardware parity receiver wakeup and double buffering on transmit and receive are also included MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 37 5 7 5 1 SCI Features Features of SCI module include Full duplex standard non return to zero NRZ format Double buffered transmitter and receiver with separate enables Programmable baud rates 13 bit modulo divider Interrupt driven or polled operation Transmit data register empty and transmission complete Receive data register full Receive overrun parity error framing error and noise error Idle receiver
7. 0 or STOP 3 Differential supply voltage Vpp Vppap lVpp rl 100 my 4 Differential ground voltage Vss VssAp VspiT 100 mV 5 Reference potential low IVREFLI E VSSAD Reference potential high 2 08V lt VppAp VREFH 2 08 VDDAD 3 6V 1 80V lt Vppap lt VDDAD VDDAD 2 08V 6 Reference supply current Enabled IREF 200 300 HA V to V VREFH to VREFL Disabled leer 0 01 0 02 ATDPU 0 or STOP 7 Analog input voltage ViNDC VSSAD 0 3 VDDAD 0 3 V 1 Vbpap must be at same potential as Vpp Maximum electrical operating range not valid conversion range MC13211 212 213 214 Technical Data Rev 0 0 54 Freescale Semiconductor Table 14 ATD Timing Performance Characteristics Num Characteristic Symbol Condition Min Typ Max Unit 1 ATD conversion clock ATDCLK 2 08V Vppap lt 3 6V 0 5 2 0 MHz TEHMency 1 80V lt Vppap lt 2 08V 0 5 1 0 2 Conversion cycles CCP 28 28 30 ATDCLK continuous convert cycles 3 Conversion time Tconv 2 08V lt Vppap 3 6V 14 0 60 0 uS 1 80V lt Vppap 2 08V 28 0 60 0 4 Source impedance at RAS 10 ko input 5 Analog Input Voltage MAIN VREFL VREFH V 6 Ideal resolution 1 LSB RES 2 08V lt Vppap 3 6V 2 031 3 516 mV 1 80V lt Vppap lt 2 08V 1 758 2 031 7 Differential non linearity DNL 1 80V lt Vppap lt
8. 6566676869 2 345 0 1 c CI 4 341 0 1 a 6 57 0 15 a o 1 A B C I modi G C I 71 70 UU C48 n 49 71X 65X 71X 0 25 0 1 0 5 0 35 0 1 0 1 JA B CI paon 225 BOTTOM VIEW Figure 38 Bottom View Mechanical 2 of 2 MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 813 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 303 675 2140 Fax 303 67
9. VDDD VDDINT GPIO5 GPIO6 GPIO7 XTAL1 XTAL2 VDDLO2 VDDLO1 VDDVCO VBATT REDA CT_Bias RFIN_M Digital Input Output Digital Input Output Digital Input Output Digital Input Output Power Output Power Input Digital Input Output Digital Input Output Digital Input Output Input Input Output Power Input Power Input Power Output Power Input R wep utput Output RF Control Output RF Input Output MCU Port C Bit 6 MCU Port C Bit 7 MCU Port E Bit 0 SCI1 TX data out MCU Port E Bit 1 SCI1 RX data in Modem regulated output supply voltage Modem digital interface supply Modem General Purpose Input Output 5 Modem General Purpose Input Output 6 Modem General Purpose Input Output 7 Modem crystal reference oscillator input Modem crystal reference oscillator output Modem LO2 VDD supply Modem LO1 VDD supply Modem VCO regulated supply bypass Modem voltage regulators input Modem R falogu ouilpt d APCS WET sc350 82 189 55IRIP55 2 1343013561088 45 1950 82 043 386 BTI 0 0 9 353 82 Modem bias voltage control signal for RF external components Modem RF input output negative Decouple to ground 2 0 to 3 4 V Decouple to ground Connect to Battery Connect to 16 MHz crystal and load capacitor Connect to 16 MHz crystal and load capacitor Do not load this pin by using it as a 16 MHz source Measure 16 MHz output at CLKO progra
10. Keyboard Input Bit 5 4 PTAG KBI1P6 Digital MCU Port A Bit 6 Input Output Keyboard Input Bit 6 5 PTATIKBI1P7 Digital MCU Port A Bit 7 Input Output Keyboard Input Bit 7 6 VDDAD Power Input MCU power supply to ATD Decouple to ground 7 PTGO BKGND MS Digital MCU Port G Bit 0 PTGO is output only Pin is I O when used as BDM Input Output Background Mode Select function 8 PTG1 XTAL Digital MCU Port G Bit 1 Crystal Full I O when not used as clock source Input Output oscillator output Output 9 PTG2 EXTAL Digital MCU Port G Bit 2 Crystal Full I O when not used as clock source Input Output oscillator input Input 10 CLKO Digital Output Modem Clock Output Programmable frequencies of 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 62 5 kHz 32 786 kHz default and 16 393 kHz 11 RESET Digital MCU reset Active low Input Output 12 PTCO TXD2 Digital MCU Port C Bit 0 SCI2 Input Output TX data out 13 PTC1 RXD2 Digital MCU Port C Bit 1 SCI2 RX Input Output data in 14 PTC2 SDA1 Digital MCU Port C Bit 1 IIC bus Input Output data 15 PTC3 SCL1 Digital MCU Port C Bit 1 IIC bus Input Output clock 16 PTC4 Digital MCU Port C Bit 4 Input Output 17 PTC5 Digital MCU Port C Bit 5 Input Output MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 83 34 35 PTC6 PTC7 PTEO TXD1 PTE1 RXD1
11. 213 214 Technical Data Rev 0 0 Freescale Semiconductor 29 Uses external or internal clock as reference freguency Automatic lockout of non running clock sources Resetor interrupt on loss of clock or loss of FLL lock Digitally controlled oscillator DCO preserves previous frequency settings allowing fast frequency lock when recovering from stop3 mode DCO will maintain operating frequency during a loss or removal of reference clock When FLL is engaged FEE or FET loss of lock or loss of clock adds a divide by 2 to ICG to prevent over clocking of the system e Post FLL divider selects 1 of 8 bus rate divisors 1 through 128 Separate self clocked source for real time interrupt e Trimmable internal clock source supports SCI communications without additional external components Automatic FLL engagement after lock is acquired e Selectable low power high gain oscillator modes 5 4 2 Modes of Operation This section provides a high level description only e Mode 1 Off The output clock ICGOUT is static This mode may be entered when the STOP instruction is executed e Mode 2 Self clocked SCM Default mode of operation that is entered out of reset The ICG s FLL is open loop and the digitally controlled oscillator DCO is free running at a frequency set by the filter bits e Mode 3 FLL engaged internal tio 000Spera 00039may be eno 2 sm i the digitall 3 d Tj p5 thc1 Ttstatic MC13211 212 213
12. 214 Technical Data Rev 0 0 30 Freescale Semiconductor FLL engaged external locked is a state which occurs when the FLL detects that the DCO is locked to a multiple of the internal reference Figure 17 is a top level diagram that shows the functional organization of the internal clock generation ICG module EXTAL d T ICG OSCILLATOR OSC CLOCK WITH EXTERNAL REF SELECT T i SELECT ICGERCLK t nA OUTPUT ICGDCLK CLOCK R bm i FREQUENCY pco_ SELECT IGGBUE LOCKED REF LOOP FLL SELECT voo X i LOSS OF LOCK vss x AND CLOCK DETECTOR FIXED CLOCK r gt SELECT EFE IRG TYP 243 kHz ICGIRCLK INTERNAL E saam REFERENCE 8 MHz GENERATORS R LOCAL CLOCK FOR OPTIONAL USE WITH BDC TUT ICGLCLK Figure 17 ICG Block Diagram 5 5 Central Processing Unit CPU The HCS08 CPU is fully source and object code compatible with the M68HC08 CPU Several instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers MCU 5 5 1 CPU Features Features of the CPU include e Object code fully upward compatible with M68HC05 and M68HC08 Families e Allregisters and
13. 3 uA 55 Stop3 mode supply current S3l 3 675 nA 7 2 nA 70 er 17 0 uA 85 1 Typicals are measured at 25 C Values given here are preliminary estimates prior to completing characterization 3 All modules except ATD active ICG configured for FBE and does not include any dc loads on port pins Values are characterized but not tested on every part MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 53 Wait mode typical is 560 pA at 3 V and 422 pA at 2V with fgus 1 MHz 8 9 Typicals are measured at 25 C Values given here are preliminary estimates prior to completing characterization All modules except ATD active ICG configured for FBE and does not include any dc loads on port pins 10 Values are characterized but not tested on every part 1 Every unit tested to this parameter All other values in the Max column are guaranteed by characterization Every unit tested to this parameter All other values in the Max column are guaranteed by characterization Most customers are expected to find that auto wakeup from stop2 or stop3 can be used instead of the higher current wait mode 6 3 3 MCU ATD Characteristics Table 13 MCU ATD Electrical Characteristics Operating Num Characteristic Condition Symbol Min Typical Max Unit 1 ATD supply VDDAD 1 80 3 6 V 2 ATD supply current Enabled IppADrun 0 7 1 2 mA Disabled IDDADstop 0 02 0 6 uA ATDPU
14. 8 MHz 5 8 mA 55 2 4 8 mA 5 8 mA 70 5 8 mA 85 0 6 uA 55 3 25 nA 1 8 pA 70 4 0 nA 85 Stop1 mode supply current 91l 500 na 55 2 20 nA 1 5 pA 70 3 3 uA 4 85 3 0 uA 55 3 550 nA 5 5 pA 70 Stop2 mode supply current S2l b 2 4 uA 55 2 400 nA 5 0 uA 70 9 5 uA 9 85 4 3 pA 55 3 675 nA 7 2 pA 70 17 0 uA 85 Stop3 mode supply current S3l 5 3 5 uA 55 2 500 nA 6 2 pA 70 15 0 uA 85 55 3 300 nA 70 85 RTI adder to stop2 or stop3 2 300 nA 70 85 MC13211 212 213 214 Technical Data Rev 0 0 52 Freescale Semiconductor Table 12 MCU Supply Current Characteristics continued Temperature Range 40 to 85 C Ambient Parameter symbol Vpp V Typical Max Temp C 55 3 70 uA 70 LVI adder to stop3 85 LVDSE LVDE 1 55 2 60 uA 70 85 Parameter Symbol Vpp V Typical Max Temp C 2 1 ma19 55 3 1 1 mA 2 4 mA 70 9 2 1 mA 85 Run supply current measured at Ripp CPU clock 2 MHZ fgus 1 MHZ 1 8 mA 55 2 0 8 mA 1 8 ma 70 1 8 mA 85 7 5 mA 55 3 6 5 mA 7 5 mA 70 3 7 5 mA 85 Run supply current measured at RI DD CPU clock 16 MHz fg 8 MHz 5 8 mA 55 2 4 8 mA 5 8 mA 70 5 8 mA 85 0 6 pA 55 3 25 nA 1 8 pA 70 4 0 nA 85 Stop1 mode supply current S11 DD 500 na 55 2 20 nA 1 5 pA 70 3 3 uA 9 85 3 0 pA 55 3 550 nA 5 5 pA 70 Stop2 mode supply current S2I DD 2 4 A Aw 55 2 400 nA 5 0 uA 70 9 5 uA 85 4
15. LNA and PA designs Figure 14 shows three possible configurations for the transceiver radio RF usage 1 Figure 14A shows a single antenna configuration in which the MC1321x internal T R switch is used The balun converts the single ended antenna to differential signals that interface to the RFIN x PAO x pins of the radio The CT Bias pin provides the proper bias point to the balun depending on operation that is CT Bias is at VDDA voltage for transmit and is at ground for receive The internal T R switch enables the signal to an onboard LNA for receive and enables the onboard PAs for transmit 2 Figure 14B shows a single antenna configuration with an external low noise amplifier LNA for greater range An external antenna switch is used to multiplex the antenna between receive and transmit An LNA is in the receive path to add gain for greater receive sensitivity Two external baluns are required to convert the single ended antenna switch signals to the differential signals required by the radio Separate RFIN and PAO signals are provided for connection with the baluns and the CT Bias signal is programmed to provide the external switch control The polarity of the external switch control is selectable MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 23 3 Figure 14C shows a dual antenna configuration where there is a RX antenna and a TX antenna For the receive side the RX antenna is ac coupled to the diffe
16. T T F T T T INDEX REGISTER HIGH INDEX REGISTER LOW X 15 8 7 0 T T ET T T STACKPOINTER SP T T T TTT T T PROGRAM COUNTER PC 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF CARRY FROM BIT 3 TWO S COMPLEMENT OVERFLOW Figure 18 CPU Registers MC13211 212 213 214 Technical Data Rev 0 0 32 Freescale Semiconductor 5 6 Parallel Input Output The MC1321x HCSO08 has seven I O ports which include a total of 56 general purpose I O signals one of these pins PTGO is output only The MC1321x family does not use all the these signals as denoted in Figure 15 Port F and part of port G are not utilized The MC1321x family makes use of the remaining I O as pinned out I O or as internally dedicated signal for communication with the 802 15 4 modem As stated above port F and part of port G are not utilized These signals and any unused IO should be programmed as outputs during initialization for lowest power operation Many of these pins are shared with on chip peripherals such as timer systems various communication ports or keyboard interrupts When these other modules are not controlling the port pins they revert to general purpose I O control For each I O pin a port data bit provides access to input read and output write data a data direction bit controls the direction of the
17. intervention from the user 4 6 Functional Description 4 6 1 802 15 4 Modem Operational Modes The 802 15 4 modem has a number of operational modes that allow for low current operation Transition from the Off to Idle mode occurs when M_RST is negated Once in Idle the SPI is active and is used to control the IC Transition to Hibernate and Doze modes is enabled via the SPI These modes are summarized along with the transition times in Table 5 Current drain in the various modes is listed in Table 8 DC Electrical Characteristics Table 5 802 15 4 Modem Mode Definitions and Transition Times Transition Time Mode Definition To or From idle Off All IC functions Off Leakage only M_RST asserted Digital outputs are tri stated 10 25 ms to Idle including IRQ Hibernate Crystal Reference Oscillator Off SPI not functional IC Responds to ATTN Data 7 20 ms to Idle is retained Doze Crystal Reference Oscillator On but CLKO output available only if Register 7 Bit 9 300 1 CLKO us to Idle 1 for frequencies of 1 MHz or less SPI not functional Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator Idle Crystal Reference Oscillator On with CLKO output available SPI active Receive Crystal Reference Oscillator On Receiver On 144 us from Idle Transmit Crystal Reference Oscillator On Transmitter On 144 us from Idle 4 6 2 Serial Peripheral In
18. memory are mapped to a single 64 Kbyte address space e 16 bit stack pointer any size stack anywhere in 64 Kbyte address space 16 bit index register H X with powerful indexed addressing modes e 8 bit accumulator A Many instructions treat X as a second general purpose 8 bit register e Seven addressing modes MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 31 5 5 2 Inherent Operands in internal registers Relative 8 bit signed offset to branch destination Immediate Operand in next object code byte s Direct Operand in memory at 0x0000 0x00FF Extended Operand anywhere in 64 Kbyte address space Indexed relative to H X Five submodes including auto increment Indexed relative to SP Improves C efficiency dramatically Memory to memory data move instructions with four address mode combinations Overflow half carry negative zero and carry condition codes support conditional branching on the results of signed unsigned and binary coded decimal BCD operations Efficient bit manipulation instructions Fast 8 bit by 8 bit multiply and 16 bit by 8 bit divide instructions STOP and WAIT instructions to invoke low power operating modes Programmer s Model and CPU Registers Figure 18 shows the five CPU registers CPU registers are not part of the memory map 7 0 16 BIT INDEX REGISTER H X T T T T T r ACCUMULATOR A I T T T T T T T T
19. power supply going out of regulation Ensure external Vpp load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power Examples are if no system clock is present or if the clock rate is very low which would reduce overall power consumption 6 2 802 15 4 Modem Electrical Characteristics 6 2 1 Modem Recommended Operating Conditions Table 7 Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Power Supply Voltage VBATT VDDINT VBATT 2 0 2 7 3 4 Vdc VDDINT Input Freguency fn 2 405 2 480 GHz Operating Temperature Range TA 40 25 85 C Logic Input Voltage Low ViL 0 3096 V VDDINT Logic Input Voltage High Vin 70 VDDINT V VppiNT SPI Clock Rate fspi 8 0 MHz RF Input Power Pmax 10 dBm Crystal Reference Oscillator Frequency 40 ppm over operating fref 16 MHz Only conditions to meet the 802 15 4 standard MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 47 6 2 2 Modem DC Electrical Characteristics Table 8 DC Electrical Characteristics VBATT VDDINT 2 7 V TA 25 C unless otherwise noted Characteristic Symbol Min Typ Max Unit Power Supply Current VgaTr VDDINT Off lleakage 0 2 1 0 HA Hibernate IccH 1 0 6 0 HA Doze No CLKO lccp 35 102 HA Idle lcci 500 800 HA Transmit Mode ICCT 30 35 MA Receive Mode ICCR 37 4
20. the I O latches are opened A separate self clocked source approximately 1 kHz for the real time interrupt allows a walk up from Stop2 or Stop3 Modes with no external components When RTIS2 RTIS1 RTISO 0 0 0 the real time interrupt function and this 1 kHz source are disabled Power consumption is lower when the 1 kHz source is disabled but in that case the real time interrupt cannot wake the MCU from stop 5 2 4 Stop3 Upon entering the Stop3 Mode all of the clocks in the MCU including the oscillator itself are halted The ICG is turned off the ATD is disabled and the voltage regulator is put in standby The states of all of the internal registers and logic as well as the RAM content are maintained The I O pin states are not latched at the pin as in Stop2 Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained Exit from Stop3 is performed by asserting RESET an asynchronous interrupt pin or through the real time interrupt The asynchronous interrupt pins are the IRO or KBI pins If Stop3 is exited by means of the RESET pin then the MCU will be reset and operation will resume after taking the reset vector Exit by means of an asynchronous interrupt or the real time interrupt will result in the MCU taking the appropriate interrupt vector MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 27 A separate self clocked source approximately1 kHz for th
21. tri teye 25 ns Output tto 25 ns MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 61 cyc ss OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT Figure 33 SPI Master Timing CPHA 0 6 4 4 FLASH Specifications This section provides details about program erase times and program erase endurance for the FLASH memory Program and erase operations do not reguire any special power sources other than the normal Vpp supply Table 20 FLASH Characteristics Characteristic Symbol Min Typical Max Unit Supply voltage for program erase Vprog erase 2 1 3 6 V Supply voltage for read operation VRead V 0 lt fgus lt 8 MHz 1 8 3 6 0 lt fgus lt 20 MHz 2 08 3 6 Internal FCLK frequency fFCLK 150 200 kHz Internal FCLK period 1 FCLK tEcyc 5 6 67 us Byte program time random location torog 9 tEcyc Byte program time burst mode tBurst 4 tEcyc Page erase time tpage 4000 tEcyc Mass erase time tMass 20 000 tEcyc Program erase endurance cycles T to Ty 40 C to 85 C 10 000 T 25 C 100 000 Data retention tb ret 15 100 years 1 The frequency of this clock is controlled by a software setting These values are hardware state machine controlled User code does not need to count cycles This information supplied for calculating approximate time
22. well as beaconed networks The MC13213 contains 60K of flash and 4KB of RAM and is also intended for use with the Freescale fully compliant 802 15 4 MAC where larger memory is required In addition this device can support ZigBee applications that use a stack from 3rd party vendors The MC13214 is a fully compliant ZigBee platform The MC13214 contains 60K of flash and 4KB of RAM and uses the Figure 8 Wireless ZigBee Stack Z stack software Applications can be added to develop fully certified ZigBee products Applications include but are not limited to the following Residential and commercial automation Lighting control Security Access control Heating ventilation air conditioning HVAC Automated meter reading AMR Industrial Control Asset tracking and monitoring Homeland security Process management Environmental monitoring and control HVAC Automated meter reading Health Care Patient monitoring Fitness monitoring MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 1 1 Ordering Information Table 1 provides additional details about the MC1321x family Table 1 Orderable Parts Details Operating Memor Device Temp Range Package ld Description Options TA MC13211 40 to 85 C LGA 1KB RAM Intended for proprietary applications and Freescale 16KB Flash Simple MAC SMAC MC13211R2 40
23. 2 mA Input Current Vin 0 V or VppinT All digital inputs liN 1 HA Input Low Voltage AII digital inputs VIL 0 30 V VDDINT Input High Voltage all digital inputs Vin 70 VDDINT V VDDINT Output High Voltage lop 1 mA All digital outputs Vou 8096 VDDINT V VDDINT Output Low Voltage lo 1 MA All digital outputs VoL 0 2096 V VpDINT 6 2 3 Modem AC Electrical Characteristics NOTE All AC parameters measured with SPI Registers at default settings except where noted Table 9 Receiver AC Electrical Characteristics VBATT VDDINT 2 7 V TA 25 C friet 16 MHZ unless otherwise noted Characteristic Symbol Min Typ Max Unit Sensitivity for 1 Packet Error Rate PER 40 to 85 C SENSper 92 dBm Sensitivity for 196 Packet Error Rate PER 25 C 92 87 dBm Saturation maximum input level SENSmax 10 dBm Channel Rejection for 1 PER desired signal 82 dBm 5 MHZ adjacent channel 34 dB 5 MHz adjacent channel 29 dB 10 MHz alternate channel 44 dB 10 MHz alternate channel 44 dB gt 15 MHZ 46 dB Frequency Error Tolerance 200 kHz Symbol Rate Error Tolerance 80 ppm MC13211 212 213 214 Technical Data Rev 0 0 48 Freescale Semiconductor Table 10 Transmitter AC Electrical Characteristics VBATT VDDINT 2 7 V Ta 25 C fret 16 MHz unless otherwise noted
24. 3 6V 0 5 1 0 LSB 8 Integral non linearity INL 1 80 V lt Vppap 3 6V 0 5 1 0 LSB 9 Zero scale error Ezs 1 80V lt Vppap lt 3 6V 0 4 1 0 LSB 10 Full scale error Ers 1 80V lt VppAp lt 3 6V 0 4 1 0 LSB 11 Input leakage error 19 EL 1 80V lt Vppap 3 6V 0 05 5 LSB 12 dotar vyda Stee ETU 1 80V lt Vppap lt 3 6V 1 1 2 5 LSB error All ACCURACY numbers are based on processor and system being in WAIT state very little activity and no IO switching and that adequate low pass filtering is present on analog input pins filter with 0 01 uF to 0 1 uF capacitor between analog input and VREF Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which Will vary based on board layout and the type and magnitude of the activity This is the conversion time for subsequent conversions in continuous convert mode Actual conversion time for single conversions or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting the conversion and setting the CCF flag The total conversion time in Bus Cycles for a conversion is SC Bus Cycles PRS 1 2 28 1 2 CC Bus Cycles PRS 1 2 28 Ras is the real portion of the impedance of the network driving the analog input pin Values greater than this amount may not fully charge the input circuitry of the ATD resulting in accuracy err
25. 5 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MC1321x Rev 0 0 03 2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body o
26. 6 802 15 4 Modem Block Diagram MC13211 212 213 214 Technical Data Rev 0 0 16 Freescale Semiconductor 4 2 Data Transfer Modes The 802 15 4 modem has two data transfer modes 1 Packet Mode Data is buffered in on chip RAM 2 Streaming Mode Data is processed word by word The Freescale 802 15 4 MAC software only supports the streaming mode of data transfer For proprietary applications packet mode can be used to conserve MCU resources 4 3 Packet Structure Figure 7 shows the packet structure of the 802 15 4 modem Payloads of up to 125 bytes are supported The 802 15 4 modem adds a four byte preamble a one byte Start of Frame Delimiter SFD and a one byte Frame Length Indicator FLI before the data A Frame Check Sequence FCS is calculated and appended to the end of the data 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes Preamble SFD FLI Payload Data FCS Figure 7 802 15 4 modem Packet Structure 4 4 Receive Path Description In the receive signal path the RF input is converted to low IF In phase and Quadrature I amp Q signals through two down conversion stages A Clear Channel Assessment CCA can be performed based upon the baseband energy integrated over a specific time interval The digital back end performs Differential Chip Detection DCD the correlator de spreads the Direct Sequence Spread Spectrum DSSS Offset QPSK O QPSK signal determines the symbols and packets and detects the data
27. BUFFER READ SPCO IDIROE gt BERGE MODEM LSBFE l_ gt SHIFT SHIFT x BUFFER BORT DIRECTIONCLOCK FUL EMPTY MASTER CLOCK BUS RATE SPIBR CLOCK gt M SPSCK CLOCK CLIOCK GENERATOR LOGIC SLAVE CLOCK S L9 SPICLK MSTR MASTER SLAVE MASTER MODE SELECT SLAVE MOD MODE FAUL SSOE SS CE DETECTION Y Y Connected onboard SiP SPRF SPTEF SPTIE SPI aj O p INTERRUPT Ec l1 REQUEST Figure 19 Modem Dedicated SPI Block Diagram MC13211 212 213 214 Technical Data Rev 0 0 34 Freescale Semiconductor 5 7 2 Keyboard Interrupt KBI Module The HCS08 has one KBI module with eight keyboard interrupt inputs that share port A pins The KBI module allows up to eight pins to act as additional interrupt sources Four of these pins allow falling edge sensing while the other four can be configured for either rising edge sensing or falling edge sensing The sensing mode for all eight pins can also be modified to detect edges and levels instead of only edges This on chip peripheral module is called a keyboard interrupt KBI module because originally it was designed to simplify the connection and use of row column matrices of keyboard switches However these inputs are also useful as extra external interrupt inputs and as an external means of waking up the MCU fr
28. DD ye VSS y VOLTAGE REGULATOR Notes 1 All Port F and Port G signals are present on the MCU KT INTERNAL BUS DEBUG MODULE DBG K 8 BIT KEYBOARD INTERRUPT MODULE Kol IIC MODULE IIC K GEMA COMMUNICATIONS INTERFACE MODULE SCI1 K SER AL COMMUNICATIONS INTERFACE MODULE SCI2 K 1 CHANNEL TIMER PWM MODULE TPM1 4 CHANNEL TIMER PWM MODULE TPM2 DEDICATED SERIAL PERIPHERAL INTERFACE MODULE SPI but only the signals used by the MC1321x are designated For lowest power operation all unused I O should be programmed as outputs during initialization internal signals 2 Timer channels are limited as noted due to use of Port D I O for gt Figure 15 MCU Block Diagram KO PORT A PTA7 KBILP7 PTAO KBI1PO KT PORT B 8 lt gt PTB7 AD1P7 PTBO AD1PO K gt PORT C lt PTC r 39 PTC6 1T PTC5 j lt lt PTCA Ltd PTC3 SCL1 rt PTC2 SDA1 red PTC1 RxD2 rt PTCO TxD2 K gt PORT D P PTD7 TPM2CH4 PTD6 TPM2CH3 PTD5 TPM2CH2 PTDA TPM2CH1 X PTD3 9 PTD2 TPM1CH2 PTD1 P PTDO PORTE la PTE7 PTE6 PTE5 SPSCK 3 PTEA MOSI 3 PTE3 MISO gt PTE2 SS PTE1 RxD1
29. F Drive level 10 uW 2 uW Shunt capacitance 2 pF max Mode of oscillation fundamental 1 With this crystal the oscillator freguency reguires trimming in production 2 This crystal is not recommended for applications that employ Doze mode over the entire temperature range Table 22 Toyocom TSX 10A 16MHZ TN4 26139 Crystal Specifications 12 Parameter Value Unit Condition Type TSX 10A surface mount Freguency 16 MHZ Frequency tolerance t 10 ppm at 25 C 3 eC Equivalent series resistance 40 Q max Temperature drift 16 ppm 40 C to 85 C Load capacitance 9 pF Drive level 100 uW max Shunt capacitance 1 2 pF typical Mode of oscillation fundamental 1 with this crystal oscillator frequency trimming is NOT required in production 2 This crystal not recommended for applications that employ Doze mode over the entire temperature range Table 23 NDK EXS00A 03311 Crystal Specifications 1 2 Parameter Value Unit Condition Type NX3225 surface mount Frequency 16 MHz Frequency tolerance t 10 ppm at25 C 3 C Equivalent series resistance 80 Q max 42 typ Temperature drift 15 ppm 40 C to 85 C Load capacitance 7 2 pF Drive level 100 uW max Shunt capacitance 0 8 pF typical Mode of oscillation fundamental MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 65 1 with this crystal oscillator freguency trimmin
30. Freescale Semiconductor Document Number MC1321x Technical Data Rev 0 0 03 2006 MC1321x Package Information MC13211 212 213 214 71 pin LGA 9x9 mr TM ZigBee Compliant Platform Ordering Information 2 4 GHz Low Power Transceiver iiid aah daye a ic MC132111 13211 LGA for the IEEE 802 15 4 Standard 11 T L plus Microcontroller MC13213 13213 LGA MC13214 13214 LGA 1 See Table 1 for more details 1 Introduction Potente 1 Introduction ccc kk kk kk eee 1 The MC1321x family is Freescale s second generation 2 MC1321x Pin Assignment and Connections 8 ZigBee platform which incorporates a low power 2 4 3 MC1321x Serial Peripheral Interface SPI 14 GHz radio frequency transceiver and an 8 bit 4 IEEE 802 15 4 Modem 16 microcontroller into a single 9x9x1 mm 71 pin LGA 5 MCU ZE DR MM DpDp III 25 package The MC1321x solution can be used for wireless 6 System Electrical Specification 46 applications from simple proprietary point to point 7 Application Considerations 63 8 Mechanical Diagrams 68 connectivity to a complete ZigBee mesh network The combination of the radio and a microcontroller in a small footprint package allows for a cost effective solution The MC1321x contains an RF transceiver which is an IEEE 802 15 4 compliant radio that operates in the 2 4 GHz ISM frequency band The transceiver includes a low noise amplifie
31. G AD1P6 Input Output MCU Port B Bit 6 ATD analog Channel 6 59 PTBZ AD1P7 Input Output MCU Port B Bit 7 ATD analog Channel 7 60 VREFH Input MCU high reference voltage for ATD 61 VREFL Input MCU low reference voltage for ATD 62 PTAO KBI1PO Digital MCU Port A Bit 0 Input Output Keyboard Input Bit O 63 PTA1 KBI1P1 Digital MCU Port A Bit 1 Input Output Keyboard Input Bit 1 64 PTA2 KBI1P2 Digital MCU Port A Bit 2 Input Output Keyboard Input Bit 2 65 TEST Test Point For factory test Do not connect 66 TEST Test Point For factory test Do not connect 67 TEST Test Point For factory test Do not connect 68 TEST Test Point For factory test Do not connect 69 TEST Test Point For factory test Do not connect 70 TEST Test Point For factory test Do not connect 71 TEST Test Point For factory test Do not connect FLAG VSS Power input External package flag Connect to ground Common VSS MC13211 212 213 214 Technical Data Rev 0 0 12 Freescale Semiconductor 2 2 Internal Functional Interconnects The MCU provides control for the 802 15 4 modem The reguired interconnects between the devices are routed onboard the SiP In addition the signals are brought out to external pads primarily for use as test points These signals can be useful when writing and debugging software Table 3 Internal Functional Interconnects Pin MCU Signal Modem Signal Description 43 PTE6 G
32. H R2 OR m a Ci Not Mounted ANT1 mat LDB21264005C 001 39nH 1 0pF F Antenna 10pF 2 3 1 4 SMA edge Recepta 5 Figure 35 RF Single Port Application with an F Antenna 7 3 RF Dual Port Application with an F Antenna Figure 36 shows a typical dual port application topology which also uses a printed copper F antenna Both the RFIN and PAO ports are used and the internal T R switch is bypassed Matching is provided for both differential ports by L5 L6 L7 and L9 and C4 and C7 A balun is used for both receive and transmit paths which are provided by the external T R switch IC1 This implementation while more complicated gives MC13211 212 213 214 Technical Data Rev 0 0 66 Freescale Semiconductor better performance due to the reduced loss of the external T R switch and the more optimum match provided to the PAO and RFIN ports The switch control is connected to the CT Bias pin which serves as its control signal The CT Bias signal can be programmed to be active high or active low depending on TX versus RX and will switch appropriately based on the radio operation No interaction with the MCU on an operation by operation basis is required NOTE Passive component values can vary as a function of circuit board layout as required to obtain best matching and RF performance The VDD voltage to the antenna switch is connected to GPIO1 This is a useful feature when GPIO1 is prog
33. Internal Clock Generator ICG The ICG provides multiple options for MCU clock sources This block along with the ability to provide the MCU clock form the modem offers a user great flexibility when making choices between cost precision current draw and performance As seen in Figure 17 the ICG consists of four functional blocks Oscillator Block The Oscillator Block provides means for connecting an external crystal or resonator Two freguency ranges are software selectable to allow optimal start up and stability Alternatively the oscillator block can be used to route an external sguare wave to the MCU system clock External sources such as the modem CLKO output can provide a low cost source or a very precise clock source The oscillator is capable of being configured for low power mode or high amplitude mode as selected by HGO Internal Reference Generator The Internal Reference Generator consists of two controlled clock sources One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU This provides a highly reliable low cost clock source Frequency Locked Loop A Frequency Locked Loop FLL stage takes either the internal or external clock source and multiplies it to a higher frequency Status bits provide informati
34. MCU Up to 32 GPIO Ea DE ee Lav K teme d 17 pesas Lm Figure 1 MC1321x System Level Block Diagram MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 1 7 System Clock Configuration The MC321x device allows for a wide array of system clock configurations Pins are provided for a separate external clock source for the CPU The external clock source can by derived from a crystal oscillator or from an external clock source Pins are provided for a 16 MHz crystal for the modem clock source required e The modem crystal oscillator frequency can be trimmed through programming to maintain the tight tolerances required by IEEE 802 15 4 The modem provides a CLKO programmable frequency clock output that can be used as an external source to the CPU As a result a single crystal system clock solution is possible e Out of reset the MCU uses an internally generated clock approximately 8 MHz for start up This allows recovery from stop or reset without a long crystal start up delay The MCU contains an internal clock generator which can be trimmed that can be used to run the MCU for low power operation This internal reference is approximately 243 kHz 1 MC1321X I 802 15 4 MODEM HCS08 MCU i l XTAL1 XTAL2 CLKO EXTAL XTAL J 27 I 28 10 9 8 16MHz Figure 2 MC1321x Single Crystal System Clock Struc
35. PIO2 Modem GPIO2 output acts as CRC Valid status indicator for Stream Data Mode to MCU 44 PTE7 GPIO1 Modem GPIO1 output acts as Out of Idle status indicator for Stream Data Mode to MCU 46 PTDO ATTN MCU Port D Bit O drives the attention ATTN input of the modem to wake modem from Hibernate or Doze Mode PTE5 SPSCK1 SPICLK MCU SPI master SPI clock output drives modem SPICLK slave clock input PTE4 MOSI1 MOSI MCU SPI master MOSI output drives modem slave MOSI input PTE3 MISO1 MISO Modem SPI slave MISO output drives MCU master MISO input PTE2 SS1 CE MCU SPI master SS output drives modem slave CE input IRO M_IRO Modem interrupt reguest M_IRO output drives MCU IRO input PTD1 RXTXEN MCU Port D Bit 1 drives the RXTXEN input to the modem to enable TX or RX or CCA operations PTD3 M_RST MCU Port D Bit 3 drives the reset M_RST input to the modem NOTE To use the MCU and modem signals as described in Table 3 the MCU needs to be programmed appropriately for the stated function MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 13 3 MC1321x Serial Peripheral Interface SPI The MC1321x modem and CPU communicate primarily through the onboard SPI command channel Figure 4 shows the SiP internal interconnects with the SPI bus highlighted The MCU has a single SPI module that is dedicated to the modem SPI interface The modem is a slave only and the MCU SPI must be programmed and used as a master only Furthe
36. The preamble SFD and FLI are parsed and used to detect the payload data and FCS which are stored in RAM in Packet Mode A two byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data which generates a Cyclical Redundancy Check CRC result A parameter of received energy during the reception called the Link Quality Indicator is measured over a 64 us period after the packet preamble and stored in an SPI register If the 802 15 4 modem is in Packet Mode the data is stored in RAM and processed as an entire packet The MCU is notified that an entire packet has been received via an interrupt If the 802 15 4 modem is in streaming mode the MCU is notified by a recurring interrupt on a word by word basis Figure 8 shows CCA reported power level versus input power Note that CCA reported power saturates at about 57 dBm input power which is well above IEEE 802 15 4 Standard requirements Figure 9 shows energy detection LOI reported level versus input power MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 17 NOTE For both graphs the reguired IEEE 802 15 4 Standard accuracy and range limits are shown A 3 5 dBm offset has been programmed into the CCA reporting level to center the level over temperature in the graphs 50 60 70 802 15 4 Accuracy c and range Requirements 80 Reported Power Level dBm 90
37. ant temperature Vpp 3 0 VS ri ic 24v6JTj 22G7 109 800986 AC Tuv UT Z R 05 00 3030 8642 4 Tm088067 Tin 8ar 6 4 MCU AC Peripheral Characteristics This section describes ac timing characteristics for each peripheral system 6 4 1 MCU Control Timing MC13211 212 213 214 Technical Data Rev 0 0 58 Freescale Semiconductor RESET PIN Figure 28 Control Reset Timing tmssu gt Figure 29 Control Active Background Debug Mode Latch Timing IRO Figure 30 Control IRO Timing 6 4 2 MCU Timer PWM TPM Module Timing tiin gt gt This is the shortest pulse that is guaranteed to be recognized as a reset pin reguest Shorter pulses are not guaranteed to override reset reguests from internal sources When any reset is initiated internal circuitry drives the reset pin low for about 34 cycles of fser reset and then samples the level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry Shorter pulses may or may not be recognized In stop mode the synchronizer is bypassed so shorter pulses can be recognized in that case Timing is shown with respect to 2096 Vpp and 80 Vpp levels Temperature range 40 C to 85 C Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional exte
38. ce operation or dual crystal operation Support for SMAC IEEE 802 15 4 and ZigBee software e 9mm x 9mm x Imm 71 pin LGA MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 1 3 Microcontroller Features Low voltage MCU with 40 MHz low power HCS08 CPU core e Up to 60K flash memory with block protection and security and 4K RAM MC13211 16KB Flash 1KB RAM MC13212 32KB Flash 2KB RAM MC13213 60KB Flash AKB RAM MC13214 60KB Flash 4KB RAM with ZigBee Z stack Low power modes Wait plus Stop2 and Stop3 modes Dedicated serial peripheral interface SPT connected internally to 802 15 4 modem One 4 channel and one 1 channel 16 bit timer pulse width modulator TPM module with selectable input capture output capture and PWM capability e 8 bit port keyboard interrupt KBI e 8 channel 8 10 bit ADC Two independent serial communication interfaces SCI Multiple clock source options Internal clock generator ICG with 243 kHz oscillator that has 0 2 trimming resolution and 0 5 deviation across voltage Startup oscillator of approximately 8 MHz External crystal or resonator External source from modem clock for very high accuracy source or system low cost option e Inter integrated circuit IIC interface n circuit debug and flash programming available via on chip background debug module BDM Two comparator and 9 trigger modes Eight deep FIFO for st
39. debug features such as CPU register modify breakpoints and single instruction trace commands Address and data bus signals are not available on external pins not even in test modes Debug is done through commands fed into the MCU via the single wire background debug interface The debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the MCU on a cycle by cycle basis without having external access to the address and data signals The alternate BDC clock source for HCS08 is the ICGLCLK 5 7 8 1 Development Support Features Features of the background debug controller BDC include Single pin for mode selection and background communications BDC registers are not located in the memory map SYNC command to determine target communications rate e Non intrusive commands for memory access Active background mode commands for CPU register access e GO and TRACE1 commands BACKGROUND command can wake CPU from stop or wait modes One hardware address breakpoint built into BDC e Oscillator runs in stop mode if BDC enabled e COP watchdog disabled while in active background mode Features of the debug module DBG include Two trigger comparators Two address read write R W or One full address data R W Flexible 8 word by 16 bit FIFO first in first out buffer for capture information Change of flow addresses or Even
40. detect Hardware parity generation and checking Programmable 8 bit or 9 bit character length Receiver walk up by idle line or address mark MC13211 212 213 214 Technical Data Rev 0 0 38 Freescale Semiconductor 5 7 5 2 SCI Block Diagrams The SCI allows full duplex asynchronous NRZ serial communication among the MCU and remote devices including other MCUs The SCI comprises a baud rate generator transmitter and receiver block The transmitter and receiver operate independently although they use the same baud rate generator During normal operation the MCU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 22 and Figure 23 show the SCI transmitter and receiver block diagrams INTERNAL BUS WRITE ONLY SCID Tx BUFFER U icd TO RECEIVE ke tue E CONTROL ATAJN O lt jm l5 11 BIT TRANSMIT SHIFT REGISTER TO TxD1 PIN 1 BAWD H 8 l7 6 5 l4 lg l2 l o l l RATE CLOCK A A m SHIFT DIRECTION _ gt U A A A A 3 uj 8 Ji 5l 2 W Bl vf E g Ei T lt E PARITY 0 u 5 a __ GENERATION i SCI CONTROLS TxD1 ENABLE Kan ao TRANSMIT CONTROL TO TxD1 m TXD1 DIRECTION PIN LOGIC gt LL gt
41. e Features Freescale provides a wide range of software functionality to complement the MC1321x hardware There are three levels of application solutions 1 Simple proprietary wireless connectivity 2 User networks built on the IEEE 802 15 4 MAC standard 3 ZigBee compliant network stack 1 5 1 1 5 2 Simple MAC SMAC Small memory footprint about 3 Kbytes typical Supports point to point and star network configurations Proprietary networks Source code and application examples provided IEEE 802 15 4 Compliant MAC Supports star mesh and cluster tree topologies Supports beaconed networks Supports GTS for low latency MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 1 5 3 ZigBee Compliant Network Stack Supports ZigBee 1 0 specification e Supports star mesh and tree networks Advanced Encryption Standard AES 128 bit security 1 6 System Block Diagram Figure 1 shows a simplified block diagram of the MC1321x solution Analog Receiver gt Background Debug Module RFIC Timers 16 60 KB 8 Channel RIN P PAO P Transmit Receive Frequency 2 3 Flash Memory 10 Bit ADC lt gt 99 Switch Generator a8 m RIN MPAO M ES oge 14 KB RAM 2x SCI PAO P lt PAO M Buffer RAM 1 Chama amp 4 Low Voltage Detect Channel 16 bit Timers IRQ Arbiter RAM Arbiter Key board Interrupt COP Power Management Voltage Regulators 802 15 4 Modem HCS08
42. e real time interrupt allows a wake up from Stop2 or Stop3 Modes with no external components When RTIS2 RTIS1 RTISO 0 0 0 the real time interrupt function and this 1 kHz source are disabled Power consumption is lower when the 1 kHz source is disabled but in that case the real time interrupt cannot wake the MCU from stop 5 3 MCU Memory As shown in Figure 16 on chip memory in the MC1321x series of MCUs consists of RAM FLASH program memory for non volatile data storage plus I O and control status registers The registers are divided into three groups Direct page registers 0000 through 007F e High page registers 1800 through 182B e Nonvolatile registers SFFBO through FFBF DIRECT PAGE REGISTERS 9 0000 0090 n DIRECT PAGE REGISTERS 097F DIRECT PAGE REGISTERS Mrs La RAM 1024 BYTES jum RAM 047F 0480 RAM 2048 BYTES 4096 BYTES 0880 UNIMPLEMENTED T UNIMPLEMENTED 1080 4992 BYTES 3968 BYTES 1920 BYTES 17FF 17FF 17FF 1800 1800 1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS HIGH PAGE REGISTERS 182B 182B 182B 182C 182C 182C UNIMPLEMENTED 26580 BYTES S7FFF UNIMPLEMENTED 8000 FLASH 42964 BYTES 59348 BYTES FLASH BFFF 32768 BYTES C000 FLASH 16384 BYTES FFFF FFFF FFFF MC13213 214 MC13212 MC13211 Figure 16 MC1321X Memory Maps MC13211 212 213 214 Technical Data Rev 0 0 28 Freescale Semiconductor 5 4 MCU
43. functions are based on a separate 16 bit counter with prescaler and modulo features to control frequency and range period between overflows of the time reference This timing system is ideally suited for a wide range of control applications and the center aligned PWM capability on the 3 channel TPM extends the field of applications to motor control in small appliances The use of the fixed system clock XCLK as the clock source for either of the TPM modules allows the TPM prescaler to run using the oscillator rate divided by two ICGERCLK 2 This clock source must be selected only if the ICG is configured in either FBE or FEE mode In FBE mode this selection is redundant because the BUSCLK frequency is the same as XCLK In FEE mode the proper conditions must be met for XCLK to equal ICGERCLK 2 Selecting XCLK as the clock source with the ICG in either FEI or SCM mode will result in the TPM being non functional 5 7 4 1 TPM Features The timer system in the MC1321x family MCU includes a 1 channel TPM1 and a separate 4 channel TPM2 Timer system features include e A total of 5 channels Each channel may be input capture output compare or buffered edge aligned PWM Rising edge falling edge or any edge input capture trigger Set clear or toggle output compare action Selectable polarity on PWM outputs Each TPM may be configured for buffered center aligned pulse width modulation CPWM on all channels e Clock source to p
44. g is NOT reguired in production 2 This crystal recommended for applications that employ Doze mode NOTE Crystal suppliers freguently specify the crystal package separately form the desired crystal parameters Care should be taken that desired crystal specifications can be obtained in the desired package 7 2 RF Single Port Application with an F Antenna Figure 35 shows a typical single port RF application topology in which part count is minimized and a printed copper F antenna is used for low cost Only the RFIN port of the MC1321x is required because the differential port is bi directional and uses the on chip T R switch Matching to near 50 Ohms is accomplished with L1 L2 L3 and the traces on the PCB A balun transforms the differential signal to single ended to interface with the F antenna The proper DC bias to the RFIN x PAO x pins is provided through the balun The CT Bias pin provides the proper bias voltage point to the balun depending on operation that is CT Bias is at VDDA voltage for transmit and is at ground for receive CT Bias is switched between these two voltages based on the operation Capacitor C2 provides some high frequency bypass to the dc bias point The L3 C1 network provides a simple bandpass filter to limit out of band harmonics from the transmitter NOTE Passive component values can vary as a function of circuit board layout as required to obtain best matching and RF performance L2 34 3 9n
45. he initial or make tolerance of the crystal resonant frequency itself 2 The variation of the crystal resonant frequency with temperature 3 The variation of the crystal resonant frequency with time also commonly known as aging 4 The variation of the crystal resonant frequency with load capacitance also commonly known as pulling This is affected by a The external load capacitor values initial tolerance and variation with temperature b The internal trim capacitor values initial tolerance and variation with temperature C Stray capacitance on the crystal pin nodes including stray on chip capacitance stray package capacitance and stray board capacitance and its initial tolerance and variation with temperature Freescale has specified that a 16 MHz crystal with a 9 pF load capacitance is required The 802 15 4 modem does not contain a reference divider so 16 MHz is the only frequency that can be used A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal The oscillator amplifier configuration used in the 802 15 4 modem requires two balanced load capacitors from each terminal of the crystal to ground As such the capacitors are seen to be in series by the crystal so each must be 18 pF for proper loading The m
46. he power down state MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 43 5 7 7 3 ATD Block Diagram Figure 25 shows the functional structure of the ATD module CONTROL INTERRUPT SAR_REG Pe DATA lt 9 0 gt ADDRESS CONTROL AND JUSTIFICATION RESULT REGISTERS STATUS R W DATA REGISTERS VDD CTL E PRESCALER STATUS VSS Y CTL e BUSCLK Sl dek CONVERSION MODE STATE n gt PRESCALER CONTROL BLOCK MACHINE CONVERSION CLOCK DIGITAL ANALOG POWERDOWN CTL SUCCESSIVE APPROXIMATION REGISTER Y ANALOG TO DIGITAL CONVERTER ATD BLOCK CONVERSION REGISTER INPUT m 014 MUX AD1P7 INTERNAL PINS CHIP PADS Figure 25 ATD Block Diagram MC13211 212 213 214 Technical Data Rev 0 0 44 Freescale Semiconductor 5 7 8 Development Support Development support systems in the include the background debug controller BDC and the on chip debug module DBG The BDC provides a single wire debug interface to the target MCU that provides a convenient interface for programming the on chip FLASH and other non volatile memories The BDC is also the primary debug interface for development and allows non intrusive access to memory data and traditional
47. he programmable pull up resistor associated with the pin is enabled Table 6 shows the maximum ratings for the 71 Pin LGA package Table 6 LGA Package Maximum Ratings Rating Symbol Value Unit Maximum Junction Temperature Tj 125 C Storage Temperature Range Tstg 55 to 125 sC Power Supply Voltage VBATT VDDINT 3 6 Vdc RF Input Power P max 10 dBm Maximum Current into Vpp Ipp 120 mA Instantaneous Maximum Current Single Pin Limit 2 3 Ip 25 mA Note Maximum Ratings are those values beyond which damage to the device may occur Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables Note Meets Human Body Model HBM 2 kV RF input output pins have no ESD protection MC13211 212 213 214 Technical Data Rev 0 0 46 Freescale Semiconductor 1 Input must be current limited to the value specified To determine the value of the reguired current limiting resistor calculate resistance values for positive Vpp and negative Vss clamp voltages then use the larger of the two resistance values All functional non supply pins are internally clamped to Vss and Vpp Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current conditions If positive injection current Vi gt Vpp is greater than Ipp the injection current may flow out of Vpp and could result in external
48. he various MCU modes is given here Run mode This is the basic mode of operation To conserve power in this mode disable the module Wait mode The module will continue to operate while the MCU is in wait mode and can provide a wake up interrupt Stop mode The IIC is inactive in Stop3 Mode for reduced power consumption The STOP instruction does not affect IIC register states Stop1 and Stop2 will reset the register contents MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 41 5 7 6 3 IC Block Diagram Figure 24 shows a block diagram of the IIC module ADDRESS i ADDR_DECODE DATA BUS INTERRUPT A A DATA_MUX CTRL_REG FREO_REG ADDR_REG STATUS_REG DATA_REG A A INPUT x SYNC IN OUT START DATA STOP SHIFT x ARBITRATION REGISTER CONTROL CLOCK lt CONTROL d EU COMPARE y Y SCL SDA Figure 24 IIC Functional Block Diagram MC13211 212 213 214 Technical Data Rev 0 0 42 Freescale Semiconductor 5 7 7 Analog to Digital ATD Module The HCS08 provides one 8 channel analog to digital ATD module The eight ATD channels share Port B Each channel individually can be configured for general purpose I O or for ATD functionality 5 7 7 1 ATD Features e 8 10 bit reso
49. ient Parameter Symbol Min Typical Max Unit Supply voltage run wait and stop modes VpD V 0 lt fBus lt 8 MHz 1 8 3 6 0 lt fgus lt 20 MHz 2 08 3 6 Minimum RAM retention supply voltage applied to Vpp VRAM 1 0 Low voltage detection threshold high range VivpH Vpp falling 2 08 2 1 2 2 Vpp rising 2 16 2 19 2 27 Low voltage detection threshold low range VLVDL V Vpp falling 1 80 1 82 1 91 Vpp rising 1 88 1 90 1 99 Low voltage warning threshold high range VivwH 2 5 V Vpp falling 2 35 2 40 Vpp rising 2 35 2 40 Low voltage warning threshold low range VivwL V Vpp falling 2 08 2 1 2 2 Vpp rising 2 16 2 19 2 27 Power on reset POR re arm voltage VRearm Mode stop 0 20 0 30 0 40 V Mode run and Wait 0 50 0 80 1 2 Input high voltage Vpp 2 2 3 V all digital inputs Vin 0 70 x Vpp V Input high voltage 1 8 V x Vpp x 2 3 V Vin 0 85 x Vpp V all digital inputs Input low voltage Vpp gt 2 3 V all digital inputs ViL 0 35 x Vpp V Input low voltage 1 8 V Vpp x 2 3 V ViL 0 30 x Vpp V all digital inputs Input hysteresis all digital inputs Vhys 0 06 x Vpp V Input leakage current per pin Ilin 0 025 1 0 A Vin Vpp or Vss all input only pins H High impedance off state leakage current per pin lozl _ 0 025 1 0 A Vin Vpp OF Vss all input output z Internal pullup and pulldown resistors Rpu 17 5 52 5 Kohm all port pi
50. imum of 2 bytes and can extend to a larger number depending on the type of access After the final SPI burst CE is negated to high to signal the end of the transaction An example SPI read transaction with a 2 byte payload is shown in Figure 11 CE Clock Burst D EZ TEE I ZAWA SPICLK MISO Valid Valid MOSI Valid Header Read data Figure 11 SPI Read Transaction Diagram 4 7 Modem Crystal Oscillator The modem crystal oscillator uses the following external pins as shown in Figure 12 1 XTAL1 reference oscillator input 2 XTAL2 reference oscillator output Note that this pin should not be loaded as a reference source or to measure frequency instead use CLKO to measure or supply 16 MHz MC1321X 802 15 4 MODEM XTAL1 XTAL2 CLKO 27 28 10 16MHz Figure 12 Modem Crystal Oscillator MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 21 The IEEE 802 15 4 Standard requires that several frequency tolerances be kept within 40 ppm accuracy This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency A number of factors can contribute to this tolerance and a crystal specification will quantify each of them 1 T
51. its with most significant bit MSB first The master MCU can send a byte to the slave transceiver on the MOSI line and the slave can send a byte to the master on the MISO line Although an 802 15 4 modem transaction is three or more SPI bursts long the timing of a single SPI burst is shown in Figure 10 The maximum SPI clock rate is 8 Mhz from the MCU because the modem is limited by this number Figure 10 SPI Single Burst Timing Diagram MC13211 212 213 214 Technical Data Rev 0 0 20 Freescale Semiconductor 4 6 2 2 SPI Transaction Operation Although the SPI port of the MCU transfers data in bursts of 8 bits the 802 15 4 modem reguires that a complete SPI transaction be framed by CE and there will be three 3 or more bursts per transaction The assertion of CE to low signals the start of a transaction The first SPI burst is a write of an 8 bit header to the transceiver MOSI is valid that defines a 6 bit address of the internal resource being accessed and identifies the access as being a read or write operation In this context a write is data written to the 802 15 4 modem and a read is data written to the SPI master The following SPI bursts will be either the write data MOSI is valid to the transceiver or read data from the transceiver MISO is valid Although the SPI bus is capable of sending data simultaneously between master and slave the 802 15 4 modem never uses this mode The number of data bytes payload will be a min
52. itten to PPDACK in SPMSC2 Exit from Stop2 is performed by asserting either of the wake up pins RESET or IRQ or by an RTI interrupt IRO is always an active low input when the MCU is in Stop2 regardless of how it was configured before entering Stop2 Upon wake up from Stop2 Mode the MCU will start up as from a power on reset POR except pin states remain latched The CPU will take the reset vector The system and all peripherals will be in their default reset states and must be initialized After waking up from Stop2 the PPDF bit in SPMSC2 is set This flag may be used to direct user code to go to a Stop2 recovery routine PPDF remains set and the I O pin states remain latched until a 1 is written to PPDACK in SPMSC2 To maintain I O state for pins that were configured as general purpose I O the user must restore the contents of the I O port registers which have been saved in RAM to the port registers before writing to the PPDACK bit If the port registers are not restored from RAM before writing to PPDACK then the register bits will assume their reset states when the I O pin latches are opened and the I O pins will switch to their reset states For pins that were configured as peripheral I O the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit If the peripheral module is not enabled before writing to PPDACK the pins will be controlled by their associated port control registers when
53. lution 14 0 usec 10 bit single conversion time at a conversion frequency of 2 MHz e Left right justified result data e Left justified signed data mode Conversion complete flag or conversion complete interrupt generation Analog input multiplexer for up to eight analog input channels Single or continuous conversion mode 5 7 7 2 ATD Modes of Operation The ATD has two modes for low power 1 Stop mode 2 Power down mode 5 7 7 2 1 ATD Stop Mode When the MCU goes into Stop Mode the MCU stops the clocks and the ATD analog circuitry is turned off placing the module into a low power state Once in stop mode the ATD module aborts any single or continuous conversion in progress Upon exiting stop mode no conversions occur and the registers have their previous values As long as the ATDPU bit is set prior to entering stop mode the module is reactivated coming out of stop 5 7 7 2 2 ATD Power Down Mode Clearing the ATDPU bit in register ATD1C also places the ATD module in a low power state The ATD conversion clock is disabled and the analog circuitry is turned off placing the module in power down mode This mode does not remove power to the ATD module Once in power down mode the ATD module aborts any conversion in progress Upon setting the ATDPU bit the module is reactivated During power down mode the ATD registers are still accessible NOTE The reset state of the ATDPU bit is zero Therefore the module is reset into t
54. mmed for 16 MHz Connect to VDDA externally Connect to VDDA externally Decouple to ground Decouple to ground Connect to Battery Decouple to ground Connect to directly VDDLO1 PAO M through a bias network When used with internal T R switch provides ground reference for RX and VDDA reference for TX Can also be used as a control signal with external LNA antenna switch and or PA When used with internal T R switch this is a biO TctioanRF ted nted Li MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor Table 2 Pin Function Description continued analog Channel 4 Pin Pin Name Type Description Functionality 37 NC Not used May be grounded or left open 38 PAOP RF Output Modem power amplifier Open drain Connect to VDDA through a bias RF output positive network when used with external balun Not used when internal T R switch is used 39 PAOM RF Output Modem power amplifier Open drain Connect to VDDA through a bias RF output negative network when used with external balun Not used when internal T R switch is used 40 SM Input Test Mode pin Must be grounded for normal operation 41 GPIOA Digital Modem General Purpose Input Output Input Output 4 42 GPIOS3 Digital Modem General Purpose Input Output Input Output 3 43 GPIO2 Test Point MCU Port E Bit 6 Modem Internally connected pins When gpio alt en General Pu
55. nction This measure of error includes inherent quantization error 1 2LSB and circuit error differential integral zero scale and full scale error The specified value of Er assumes zero E no leakage or zero real source impedance 6 3 4 MCU Internal Clock Generation Module Characteristics ICG EXTAL XTAL Re Rs IN Crystal or Resonator See Note 7 ook Il TG NOTE Use fundamental mode crystal or ceramic resonator only Figure 27 ICG Clock Basic Schematic Table 15 MCU ICG DC Electrical Specifications Temperature Range 40 to 85 C Ambient Characteristic Symbol Min Typ Max Unit Load capacitors Ci 2 C2 Feedback resistor RE Low range 32k to 100 kHz 10 MO High range 1M 16 MHz 1 MW Series Resistor Rs 0 Q 1 Data in Typical column was characterized at 3 0 V 25 C or is typical recommended value 2 See crystal or resonator manufacturer s recommendation MC13211 212 213 214 Technical Data Rev 0 0 56 Freescale Semiconductor 6 3 5 MCU ICG Freguency Specifications Table 16 MCU ICG Freguency Specifications VppA Vppa min to Vppa max Temperature Range 40 to 85 C Ambient Characteristic Symbol Min Typical Max Unit Oscillator crystal or resonator REFS 1 Fundamental mode crystal or ceramic resonator Low range f o 32 100 kHz High
56. ns If positive injection current Vi gt Vpp is greater than Ipp the injection current may flow out of Vpp and could result in external power supply going out of regulation Ensure external Vpp load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power Examples are if no system clock is present or if clock rate is very low which would reduce overall power consumption 5 All functional non supply pins are internally clamped to Vss and Vpp Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values This parameter is characterized and not tested on each device IRQ does not have a clamp diode to Vpp Do not drive IRQ above Vpp MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 51 6 3 2 MCU Supply Current Characteristics Table 12 MCU Supply Current Characteristics Temperature Range 40 to 85 C Ambient Parameter Symbol Vpp V Typical Max Temp C 2 1 mA 55 3 1 1 MA 2 1 mA 70 3 2 1 mA 85 Run supply current measured at Ripp CPU clock 2 MHZ fgus 1 MHZ 1 8 ma 55 2 0 8 mA 1 8 ma 70 1 8 mA 85 7 5 mA 55 3 6 5 mA 7 5 mA 70 5 85 Run supply current 3 measured at RI 7 5 mA M DD CPU clock 16 MHZ fgus
57. ns and IRO Internal pulldown resistors Port A4 A7 and IRQ Rpp 17 5 52 5 kohm MC13211 212 213 214 Technical Data Rev 0 0 50 Freescale Semiconductor Table 11 MCU DC Characteristics continued Temperature Range 40 to 85 C Ambient Parameter Symbol Min Typical Max Unit Output high voltage Vpp 2 1 8 V lop 2 mA ports A B D E and G Vou Vpp 0 5 Output high voltage ports C and F Vpp 0 5 loH 10 mA Vpp gt 2 7 V V log 6 mA Vpp gt 2 3 V loH 3 MA Vpp gt 1 8 V Dx Maximum total lop for all port pins llourl 60 mA Output low voltage Vpp 2 1 8 V VoL loL 2 0 mA ports A B D E and G 0 5 Output low voltage ports C and F loL 10 0 mA Vpp gt 2 7 V 0 5 V lo 6 mA Vpp gt 2 3 V 0 5 lo 3 mA Vpp gt 1 8 V 0 5 Maximum total lo for all port pins lot 60 mA dc injection current gt 6 7 8 lc Vin lt Vss Vin Vpp Single pin limit 0 2 mA Total MCU limit includes sum of all stressed pins 5 mA Input capacitance all non supply pins 2 Cin 7 pF Typicals are measured at 25 C 1 2 3 4 This parameter is characterized and not tested on each device Measurement condition for pull resistors Vi Vss for pullup and Vin Vpp for pulldown Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current conditio
58. nterrupt service routine While the MCU is in Wait Mode there are some restrictions on which background debug commands can be used Only the BACKGROUND command and memory access with status commands are available when the MCU is in wait mode The memory access with status commands do not allow memory access but they report an error indicating that the MCU is in either stop or wait mode The BACKGROUND command can be used to wake the MCU from Wait Mode and enter active background mode 5 2 3 Stop 2 The Stop2 Mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I O pins Stop2 can be entered only if the LVD circuit is not enabled in Stop Modes either LVDE or LVDSE not set Before entering Stop2 Mode the user must save the contents of the I O port registers as well as any other memory mapped registers they want to restore after exit of Stop2 to locations in RAM Upon exit of Stop2 these values can be restored by user software before pin latches are opened MC13211 212 213 214 Technical Data Rev 0 0 26 Freescale Semiconductor When the MCU is in Stop2 Mode all internal circuits that are powered from the voltage regulator are turned off except for the RAM The voltage regulator is in a low power standby state as is the ATD Upon entry into Stop2 the states of the I O pins are latched The states are held while in Stop2 Mode and after exiting Stop2 Mode until a 1 is wr
59. nts MCU control bits Slave select programmed to meet modem protocol 3 3 SPI System Block Diagram Figure 5 shows the SPI system level diagram MCU MASTER MODEM SLAVE MOS1 MOSI gt SPI SHIFTER SPI SHIFTER 7 65 4 3 2 1 0 MISO1 MISO 7 6 5 4 3 2 1 0 lt Ba a A A SPSCK1 SPICLK gt O Dr CLOCK GENERATOR PTE2 SS1 CE Figure 5 SPI System Block Diagram Figure 5 shows the SPI modules of the MCU and modem in the master slave arrangement The MCU master initiates all SPI transfers During a transfer the master shifts data out on the MOSI pin to the slave while simultaneously shifting data in on the MISO pin from the slave Although the SPI interface supports simultaneous data exchange between master and slave the modem SPI protocol only uses data exchange in one direction at a time The SPSCK signal is a clock output from the master and an input to the slave The slave device must be selected by a low level on the slave select input SS1 pin MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 15 4 IEEE 802 15 4 Modem 4 1 Block Diagram
60. odem uses the 16 MHz crystal oscillator as the reference oscillator for the system and a programmable warp capability is provided It is controlled by programming CLKO Ctl Register 0A Bits 15 8 xtal trim 7 0 The trimming procedure varies the frequency by a few hertz per step depending on the type of crystal The high end of the frequency spectrum is set when xtal trim 7 0 is set to zero As xtal trim 7 0 is increased the frequency is decreased Accuracy of this feature can be observed by varying xtal trim 7 0 and using a spectrum analyzer or frequency counter to track the change in frequency of the crystal signal The reference oscillator frequency can be measured at the CLKO contact by programming CLKO Ctl Register 0A Bits 2 0 to value 000 MC13211 212 213 214 Technical Data Rev 0 0 22 Freescale Semiconductor Frequency Decrease Hz xtal trim 7 0 decimal Figure 13 Crystal Frequency Variation vs xtal trim 7 0 Figure 13 shows typical oscillator frequency decrease versus the value programmed in xtal trim 7 0 4 8 Radio Usage The MC1321x RF analog interface has been designed to provide maximum flexibility as well as low external part count and cost An on chip transmit receive T R switch with bias switch CT Bias can be used for a simple single antenna interface with a balun Alternately separate full differential RFIN and PAO outputs can be utilized for separate RX and TX antennae or external
61. om stop or wait low power modes 5 7 3 KBI Features The keyboard interrupt KBI module features include e Keyboard interrupts selectable on eight port pins Four falling edge low level sensitive Four falling edge low level or rising edge high level sensitive Choice of edge only or edge and level sensitivity Common interrupt flag and interrupt enable control Capable of waking up the MCU from stop3 or wait mode 5 7 3 1 KBI Block Diagram Figure 20 shows the block diagram for the KBI module KBIPO o KBIPEO KBIP3 A SPASE SEANA KEIBES VDD RESET DCLRO LI SYNCHRONIZER KBIP4 5 KBIPE4 STOP BYPASS 1 KEYBOARD STOP KEYBOARD INTERRUPT FF KBEDG4 INTERRUPT REQUEST KBIMOD mr KBIPn l4 mE 0 KBIPEn V KBEDGn Figure 20 KBI Block Diagram MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 35 5 7 4 Timer PWM TPM Module Introduction The HCS08 includes two independent Timer PWM TPM modules which support traditional input capture output compare or buffered edge aligned pulse width modulation PWM on each channel A control bit in each TPM configures all channels in that timer to operate as center aligned PWM functions In each of these two TPMs timing
62. on when the circuit has achieved lock and when it falls out of lock Additionally this block can monitor the external reference clock and signals whether the clock is valid or not Clock Select Block The Clock Select Block provides several switch options for connecting different clock sources to the system clock tree ICGDCLK is the multiplied clock frequency out of the FLL ICGERCLK is the reference clock frequency from the crystal or external clock source and FFE fixed frequency enable is a control signal used to control the system fixed frequency clock XCLK ICGLCLK is the clock source for the background debug controller BDC The module is intended to be very user friendly with many of the features occurring automatically without user intervention 5 4 1 Features Features of the ICG and clock distribution system Several options for the MCU primary clock source allow a wide range of cost frequency and precision choices 32 kHz 100 kHz crystal or resonator 1 MHz 16 MHz crystal or resonator External clock supplied by modem CLKO or other source Internal reference generator Defaults to self clocked mode to minimize startup delays Frequency locked loop FLL generates 8 MHz to 40 MHz for bus rates up to 20 MHz When using modem CLKO as external source maximum FLL frequency is 32 MHz 16 MHz bus rate with CLKO 16 MHz or maximum FLL frequency is 40 MHz 20 MHz bus rate with CLKO 4 MHz MC13211 212
63. or Analog input must be between Vper and VREFH for valid conversion Values greater than VREFH will convert to 3FF less the full scale error Egs 5 The resolution is the ideal step size or 1LSB VREFH VREFL 1024 Differential non linearity is the difference between the current code width and the ideal code width 1L SB The current code width is the difference in the transition voltages to and from the current code Integral non linearity is the difference between the transition voltage to the current code and the adjusted ideal transition voltage for the current code The adjusted ideal transition voltage is Current Code 1 2 1A VREFH Ers VREFLTEzs Zero scale error is the difference between the transition to the first valid code and the ideal transition to that code The Ideal transition voltage to a given code is Code 1 2 1 VREFH VREFL Full scale error is the difference between the transition to the last valid code and the ideal transition to that code The ideal transition voltage to a given code is Code 1 2 1 Vgggu Vngr B Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin Reducing the impedance of the network reduces this error MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 55 11 Total unadjusted error is the difference between the transition voltage to the current code and the ideal straight line transfer fu
64. oring change of flow addresses and event only data Tag and force breakpoints In circuit debugging with single breakpoint System protection features Programmable low voltage interrupt LVI Optional watchdog timer COP Illegal opcode detection e Up to 32 MCU GPIO with programmable pullups MC13211 212 213 214 Technical Data Rev 0 0 4 Freescale Semiconductor 1 4 1 5 RF Modem Features Fully compliant IEEE 802 15 4 transceiver supports 250 kbps O QPSK data in 5 0 MHz channels and full spread spectrum encode and decode Operates on one of 16 selectable channels in the 2 4 GHz ISM band 1 dBm to 0 dBm nominal output power programmable from 27 dBm to 3 dBm typical Receive sensitivity of 92 dBm typical at 196 PER 20 byte packet much better than the IEEE 802 15 4 specification of 85 dBm Integrated transmit receive switch Dual PA ouput pairs which can be programmed for full differential single port or dual port operation that supports an external LNA and or PA Three low power modes for increased battery life Programmable frequency clock output for use by MCU Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration Four internal timer comparators available to supplement MCU timer resources Supports both packet data mode and streaming data mode Seven GPIO to supplement MCU GPIO Softwar
65. pin and a pullup enable bit enables an internal pullup device provided the pin is configured as an input and a slew rate control bit controls the rise and fall times of the pins Parallel I O features include e A total of 32 general purpose I O pins in seven ports PTGO is output only High current drivers on port C Hysteresis input buffers e Software controlled pullups on each input pin e Software controlled slew rate output buffers Eight port A pins shared with KBI1 Eight port B pins shared with ATD1 e Eight high current port C pins shared with SCI2 and IIC1 Eight port D pins shared with TPM1 and TPM2 Eight port E pins shared with SCI1 and SPI1 Eight port G pins shared with EXTAL XTAL and BKGD MS NOTE Not all port G signals and no port F signals are bonded out but are present in the MCU hardware see Figure 15 These port I O signals should be programmed as outputs set to the low state 5 7 MCU Peripherals 5 7 1 Modem Dedicated Serial Peripheral Interface SPI Module The HCS08 provides one serial peripheral interface SPI module which is connected within the SiP to the modem SPI port The four pins associated with SPI functionality are shared with port E pins 2 5 When the SPI is enabled the direction of pins is controlled by module configuration The MCU SPI port is used only in master mode on the MC1321x family The user must program the SPI module for the proper characteristics as listed in the feat
66. quency with temperature 3 The variation of the crystal resonant frequency with time also commonly known as aging 4 The variation of the crystal resonant frequency with load capacitance also commonly known as pulling This is affected by a The external load capacitor values initial tolerance and variation with temperature b The internal trim capacitor values initial tolerance and variation with temperature C Stray capacitance on the crystal pin nodes including stray on chip capacitance stray package capacitance and stray board capacitance and its initial tolerance and variation with temperature 5 Whether or not a frequency trim step will be performed in production 7 1 1 Crystal Oscillator Design Considerations Freescale requires that a 16 MHz crystal with a 9 pF load capacitance is used The MC1321x does not contain a reference divider so 16 MHz is the only frequency that can be used A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal The oscillator amplifier configuration used in the MC1321x requires two balanced load capacitors from each terminal of the crystal to ground As such the capacitors are seen to be in series by the crystal so each must be 18 pF for proper loading In the Figure 34 crystal
67. r 1mW nominal output power PA with internal voltage controlled oscillator V CO integrated transmit receive switch on board power supply regulation and full spread spectrum encoding and decoding The MC1321x also contains a microcontroller based on the HCS08 Family of Microcontroller Units MCU and can provide up to 60KB of flash memory and 4KB of RAM The onboard MCU allows the communications Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products O Freescale Semiconductor Inc 2005 2006 All rights reserved S z freescale semiconductor stack and also the application to reside on the same system in package SIP The MC1321x family is organized as follows The MC13211 has 16KB of flash and 1KB of RAM and is an ideal solution for low cost proprietary applications that reguire wireless point to point or star network connectivity The MC13211 combined with the Freescale Simple MAC SMAC provides the foundation for proprietary applications by supplying the necessary source code and application examples to get users started on implementing wireless connectivity The MC13212 contains 32K of flash and 2KB of RAM and is intended for use with the Freescale fully compliant 802 15 4 MAC Custom networks based on the 802 15 4 standard MAC can be implemented to fit user needs The 802 15 4 standard supports star mesh and cluster tree topologies as
68. r the SPI performance is limited by the modem constraints of 8 MHz SPI clock frequency and use of the SPI must be programmed to meet the modem SPI protocol 3 1 SIP Level SPI Pin Connections The SiP level SPI pin connections are all internal to the device Figure 4 shows the SiP interconnections with the SPI bus highlighted MC1321x ee ee ee eee A N ee ee D ee TT M RST lt PTD3 la AA RESET M_IRQ IRQ T ATTN PTDO RXTXEN la PTD1 MODEM GPIO1 Out_of_Idle PTE7 Meo GPIO2 CRC Valid PTE6 MOSI 14 PTE4IMOSI1 MISO PTE3 MISO1 SPICLK PTESISPSCK1 CE 4 PTE2 SS1 DI Figure 4 MC1321x Internal Interconnects Highlighting SPI Bus Table 4 MC1321x Internal SPI Connections MCU Signal Modem Signal Description PTE5 SPSCK1 SPICLK MCU SPI master SPI clock output drives modem SPICLK slave clock input PTE4 MOSI1 MOSI MCU SPI master MOSI output drives modem slave MOSI input PTE3 MISO1 MISO Modem SPI slave MISO output drives MCU master MISO input PTE2 SS1 CE MCU SPI master SS output drives modem slave CE input MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 3 2 SPI Features e MCU bus master Modem bus slave Programmable SPI clock rate maximum rate is 8 MHz e Double buffered transmit and receive at MCU Serial clock phase and polarity must meet modem requireme
69. r other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 2006 All rights reserved z freescale semiconductor
70. rammed as an Out of Idle status indicator When the radio is out of Idle or active the antenna switch is powered In this manner the antenna switch only consuina 1urr ent when it needs to be active The GPIO1 can only be used as a VDD source for a very low 1urrent load L6 A IC1 OUT2 VDD OUT1 5 IN 3 1 2 Tuer Di Wel E uPG2012TK E2 le els 10pF OBL 2 2nH F Antenna R Not Mounted 18 PP R4 ANT2 LDB212G4005C 001 27 E SMA edge Receptacle Female 5 Figure 36 RF Dual Port Application with an F Antenna MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 67 8 Mechanical Diagrams Figure 37 and Figure 38 show the MC1321x mechanical information 9 B 64 49 LJ LU J 14J1 J tJ o JlJ T1J EJ 1 C M peus 171 70 D 1O0 2 S SI Ej AEE E a 4 XJ o E 3 p r a En Ji n radan U ca Lo a a 3 i a i s LC LL J g D XI Ee 65666768869 n za 1 16 D a D Ll lli iT T T T ILi C Li f1 Li E1 L L 7 0 1 1 MAX Figure 37 Top View Mechanical 1 of 2 MC13211 212 213 214 Technical Data Rev 0 0 68 Freescale Semiconductor 6 71310 15 10 11AIB C 3 10910 1 TY 32 UUUTVVU JE n a
71. range FLL bypassed external CLKS 10 fhi_byp 2 16 MHz High range FLL engaged external CLKS 11 hi eng 2 10 MHz Input clock frequency CLKS 11 REFS 0 Low range flo 32 100 kHz High range fni eng 2 10 MHz Input clock frequency CLKS 10 REFS 0 fExtal 0 40 MHz Internal reference frequency untrimmed fICGIRCLK 182 25 243 303 75 kHz Duty cycle of input clock 2 REFS 0 tac 40 60 Output clock ICGOUT freguency fICGOUT CLKS 10 REFS 0 fexta min fexta max MHz All other cases fig min fICGDCLKma x max Minimum DCO clock ICGDCLK freguency ficGDCLKmin 8 MHz Maximum DCO clock ICGDCLK frequency flcGDCLKma 40 MHz x Self clock mode ICGOUT frequency 1 fself f CGDCLKmin fICGDCLKma MHz x Self clock mode reset ICGOUT frequency selt reset 5 5 8 10 5 MHz Loss of reference frequency f OR Low range 5 25 kHz High range 50 500 Loss of DCO frequency fim 0 5 1 5 MHz Crystal start up time 5 Low range tes TL 430 ms High range CSTH 4 FLL lock time 6 ms Low range ti ockd 2 High range li ockh 2 FLL frequency unlock range Unlock 4 N 4 N counts FLL frequency lock range Lock 2 N 2 N counts MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 57 ICGOUT period jitter 7 measured at f ccour Max Conr Long term jitter averaged over 2 ms interval 96 fica Internal oscillator deviation from trimmed frequency Vpp 1 8 3 6 V const
72. reference schematic the external load capacitors are shown as 6 8 pF each used in conjunction with a crystal that requires an 8 pF load capacitance The default internal trim capacitor value 2 4 pF and stray capacitance total value 6 8 pF sum up to 9 2 pF giving a total of 16 pF The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout A different board layout may require a different external load capacitor value MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 63 The on chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the freguency at CLKO Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps Initial tolerance for the internal trim capacitance is approximately 15 Since the MC1321x contains an on chip reference frequency trim capability it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0 12 ppm on a board by board basis Individual trimming of each board in a production environment allows use of the lowest cost crystal but requires that each board go through a trimming procedure This step can be avoided by using specifying a crystal with a tighter stability tolerance but the crystal will be slightly higher in cost A tolerance analysis budget may be created
73. rential RFIN inputs and these capacitors along with inductor L1 form a matching network Inductors L2 and L3 are ac coupled to ground to form a freguency trap For the transmit side the TX antenna is connected to the differential PAO outputs and inductors L4 and L5 provide dc biasing to VDDA but are ac isolated MC1321x 14A Using Onboard T R Switch RX Antenna L1 Ant Sw LNA RFIN P PAO P Balun L1 RFIN_M PAO_M Bypass li MC1321x CT Bias Ant Sw Ctl PAO P VDDA Balun PAO_M Bypass 14B Using External Antenna Switch With LNA TX Antenna RFIN P PAO P RFIN M PAO M MC1321x CT Bias PAO P PAO M 14C Using Dual Antennae Figure 14 Using the MC1321x with External RF Components MC13211 212 213 214 Technical Data Rev 0 0 24 Freescale Semiconductor 5 5 1 MCU MCU Block Diagram MCU CORE BDC CPU RESET IRQ MCU SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH 61 268 BYTES MAX K USER RAM 4096 BYTES MAX VDDAD VSSAD VREFH VREFL 10 BIT ANALOG TO DIGITAL CONVERTER ATD1 INTERNAL CLOCK GENERATOR ICG LOW POWER OSCILLATOR V
74. rescaler for each TPM is independently selectable as bus clock fixed system clock or an external pin e Prescale taps for divide by 1 2 4 8 16 32 64 or 128 e 16 bit free running or up down CPWM count operation e 16 bit modulus register to control counter range Timer system enable Oneinterrupt per channel plus terminal count interrupt MC13211 212 213 214 Technical Data Rev 0 0 36 Freescale Semiconductor 5 7 4 2 TPM Block Diagram The TPM uses one input output 1 O pin per channel TPMxCHn where x is the TPM number for example 1 or 2 and n is the channel number for example 1 4 The TPM shares its I O pins with general purpose I O port pins Figure 21 shows the structure of a TPM Some MCUs include more than one TPM with various numbers of channels BUSCLK CLOCK SOURCE PRESCALE AND SELECT SELECT DIVIDE BY XCLK 3 sync OFF BUS XCLK EXT 1 2 4 8 16 32 64 or 128 TPM1 EXT CLK CLKSB CLKSA PS2 PS1 PSO CPWMS MAIN 16 BIT COUNTER TOF INTERRUPT TFIE COUNTER RESET 16 BIT COMPARATOR TPMIMODH TPMIMODL ELS1B ELS1A CHANNEL 1 TPM1C1VH TPM1C1VL DEM CHIF e MS1B MS1A CH1IE INTERRUPT LOGIC 16 BIT LATCH Figure 21 TPM Block Diagram 5 7 5 Serial Communications Interface SCI Module
75. rnal source to the timer counter These synchronizers operate from the current bus rate clock Table 18 TPM Input Timing MC13211 212 213 214 Technical Data Rev 0 0 Function Symbol Min Max Unit External clock frequency frPMext dc Bus 4 MHz External clock period trPMext 4 teyc External clock high time telkh 1 5 teye External clock low time telki 1 5 teye Input capture pulse width ticpw 1 5 teye Freescale Semiconductor 59 TPMXCHn Figure 31 Timer External Clock lt licpw TPMxCHn TPMxCHn lt cpw gt Figure 32 Timer Input Capture Pulse MC13211 212 213 214 Technical Data Rev 0 0 60 Freescale Semiconductor 6 4 3 Table 19 describes the timing reguirements for the SPI system Table 19 SPI Timing System SPI Timing No Function Symbol Min Max Unit Operating frequency fop Hz Master fpus 2048 fgus 2 8 MHz 1 SCK period tsck Master 2 2048 t 2 Enable lead time tLead Master 1 2 tsck 3 Enable lag time t ag Master 1 2 tsck 4 Clock SCK high or low time tWSCK Master 62 5 1024 teyc ns 5 Data setup time inputs tsu Master 15 ns 6 Data hold time inputs tu Master 0 ns 7 Data valid after SCK edge ty Master 25 ns 8 Data hold time outputs tHo Master 0 ns 9 Rise time Input try lcyc 25 ns Output tro 25 ns 10 Fall time Input
76. rpose Register 9 Bit 7 1 GPIO2 functions as a CRC Input Output 2 Valid indicator 44 GPIO1 Test Point MCU Port E Bit 7 Modem Internally connected pins When gpio_alt_en General Purpose Register 9 Bit 7 1 GPIO1 functions as an Out of Input Output 1 Idle indicator 45 VDD Power Input MCU main power supply Decouple to ground 46 ATTN Test Point MCU Port D Bit 0 Modem Internally connected pins attention input 47 PTD2 TPM1CH2 Digital MCU Port D Bit 2 TPM1 Input Output Channel 2 48 PTD4 TPM2CH1 Digital MCU Port D Bit 4 TPM2 Input Output Channel 1 49 PTD5 TPM2CH2 Digital MCU Port D Bit 5 TPM2 Input Output Channel 2 50 PTDG TPM2CH3 Digital MCU Port D Bit 6 TPM2 Input Output Channel 3 51 PTD7 TPM2CHA Digital MCU Port D Bit 7 TPM2 Input Output Channel 4 52 PTBO AD1PO Input Output MCU Port B Bit O ATD analogChannel 0 53 PTB1 AD1P1 Input Output MCU Port B Bit 1 ATD analog Channel 1 54 PTB2 AD1P2 Input Output MCU Port B Bit 2 ATD analog Channel 2 55 PTB3 AD1P3 Input Output MCU Port B Bit 3 ATD analog Channel 3 56 PTB4 AD1P4 Input Output MCU Port B Bit 4 ATD MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 11 Table 2 Pin Function Description continued Pin Pin Name Type Description Functionality 57 PTBS5 AD1P5 Input Output MCU Port B Bit 5 ATD analog Channel 5 58 PTB
77. s enabled the direction of pins is controlled by module configuration If the IIC is disabled both pins can be used as general purpose I O The inter integrated circuit IIC provides a method of communication between a number of devices statement The interface is designed to operate up to 100 kbps with maximum bus loading and timing The device is capable of operating at higher baud rates up to a maximum of clock 20 with reduced bus loading The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF 5 7 6 1 IC Features The IIC includes these features e P bus V2 0 compliant Compatible with IIC bus standard e Multi master operation statement e Software programmable for one of 64 different serial clock frequencies iic prescale asm e Software selectable acknowledge bit iic ack asm e Interrupt driven byte by byte data transfer iic int asmj e Arbitration lost interrupt with automatic mode switching from master to slave iic int asm e Calling address identification interrupt iic int asm START and STOP signal generation detection fiic transmit asm iic receive asm iic receive addon asm e Repeated START signal generation iic transmit asmj e Acknowledge bit generation detection iic ack asm e Bus busy detection iic bus busy asm 5 7 6 2 IC Modes of Operation The IIC functions the same in normal and monitor modes A brief description of the IIC in t
78. t only data Two types of breakpoints Tag breakpoints for instruction opcodes Force breakpoints for any address access Nine trigger modes MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 45 A only AORB Athen B A AND B data full mode A AND NOT B data full mode Event only B store data A then event only B store data Inside range A lt address lt B Outside range address lt A or address gt B 6 System Electrical Specification This section details maximum ratings for the 71 pin LGA package and recommended operating conditions DC characteristics and AC characteristics for the modem and the MCU 6 1 SiP LGA Package Maximum Ratings Absolute maximum ratings are stress ratings only and functional operation at the maximum rating is not guaranteed Stress beyond the limits specified in Table 6 may affect device reliability or cause permanent damage to the device For functional operating conditions refer to the remaining tables in this section This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for instance either Vss or Vnn or t
79. terface SPI The MCU directs the 802 15 4 modem checks its status and reads writes data to the device through the 4 wire SPI port The transceiver operates as a SPI slave device only A transaction between the host and the 802 15 4 modem occurs as multiple 8 bit bursts on the SPI The modem SPI signals are 1 Chip Enable CE A transaction on the SPI port is framed by the active low CE input signal A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts 2 SPI Clock SPICLK The host drives the SPICLK input to the 802 15 4 modem Data is clocked into the master or slave on the leading rising edge of the return to zero SPICLK and data out changes state on the trailing falling edge of SPICLK MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 19 NOTE For the MCU the SPI clock format is the clock phase control bit CPHA 0 and the clock polarity control bit CPOL 0 3 Master Out Slave In MOSI Incoming data from the host is presented on the MOSI input 4 Master In Slave Out MISO The 802 15 4 modem presents data to the master on the MISO output Although the SPI port is fully static internal memory timer and interrupt arbiters require an internal clock CLK ore derived from the crystal reference oscillator to communicate from the SPI registers to internal registers and memory 4 6 2 1 SPI Burst Operation The SPI port of the MCU transfers data in bursts of 8 b
80. to 85 C LGA 1KB RAM Intended for proprietary applications and Freescale Tape and Reel 16KB Flash Simple MAC SMAC MC13212 40 to 85 C LGA 2KB RAM Intended for IEEE 802 15 4 compliant applications and 32KB Flash Freescale 802 15 4 MAC MC13212R2 40 to 85 C LGA 2KB RAM Intended for IEEE 802 15 4 compliant applications and Tape and Reel 32KB Flash Freescale 802 15 4 MAC MC13213 40 to 85 C LGA 4KB RAM Intended for IEEE 802 15 4 compliant applications and 60KB Flash Freescale 802 15 4 MAC Also supports ZigBee applications that use a stack from a 3rd party vendor MC13213R2 40 to 85 C LGA 4KB RAM Intended for IEEE 802 15 4 compliant applications and Tape and Reel 60KB Flash Freescale 802 15 4 MAC Also supports ZigBee applications that use a stack from a 3rd party vendor MC13214 40 to 85 C LGA 4KB RAM Intended for full ZigBee compliant applications using the 60KB Flash F8 Wireless Z Stack MC13214R2 40 to 85 C LGA 4KB RAM Intended for full ZigBee compliant applications using the Tape and Reel 60KB Flash F8 Wireless Z Stack 1 2 General Platform Features e IEEE 802 15 4 standard compliant on chip transceiver modem 2 4GHz 16 selectable channels Programmable output power e Multiple power saving modes 2V to 3 4V operating voltage with on chip voltage regulators e 40 C to 85 C temperature range Low external component count Supports single 16 MHz crystal clock sour
81. to program and erase MC13211 212 213 214 Technical Data Rev 0 0 62 Freescale Semiconductor 3 Typical endurance for FLASH was evaluated for this product family on the 9812Dx64 For additional information on how Freescale Semiconductor defines typical endurance please refer to Engineering Bulletin EB619 D Typical Endurance for Nonvolatile Memory 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de rated to 25 C using the Arrhenius equation For additional information on how Freescale Semiconductor defines typical data retention please refer to Engineering Bulletin EB618 D Typical Data Retention for Non volatile Memory 7 Application Considerations 7 1 Crystal Oscillator Reference Frequency The IEEE 802 15 4 Standard requires that several frequency tolerances be kept within 40 ppm accuracy This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance The MC1321x transceiver provides onboard crystal trim capacitors to assist in meeting this performance The primary determining factor in meeting the 802 15 4 standard is the tolerance of the crystal oscillator reference frequency A number of factors can contribute to this tolerance and a crystal specification will quantify each of them 1 The initial or make tolerance of the crystal resonant frequency itself 2 The variation of the crystal resonant fre
82. ture MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 7 2 MC1321x Pin Assignment and Connections Figure 3 shows the MC1321x pinout N Ay g N lt E Au e4 PTA1 KBI1P1 PTAO KBI1PO PTB5 ADIP5 PTB4 AD1P4 PTB3 AD1P3 PTB2 AD1P2 PTBI ADIP1 PTBO AD1PO PTD7 TPM2CH4 PTD6 TPM2CH3 PTD5 TPM2CH2 VREFH PTA3 KBIIP3 e PTDA TPM2CHI PTA4 KBI1P4 _ PTD2 TPMICH2 PTA5S KBI1P5 5 PTAG KBIIP6 4 PTAZ KBIIP7 5 VDDAD 6 GPIO2 PTGO0 BKGD MS Flag opening PTG1 XTAL PTG2 EXTAL L SM CLKO 1 PAO M RESET lu PAO P PTCO TXD2 NC PTC1 RXD2 L1 TEST REIN P PTC2 SDA1 53 RFIN M PTC3 SCLI CT Bias PTC4 VDDA PI LJ TL LIU L L LIT L L L L LU gg d d tz lt x M lt sazu SSS RRS sss Hom Sa Soe B b s 3 x O R Mer U O A 2 g m o e n Figure 3 Preliminary MC1321x Pinout MC13211 212 213 214 Technical Data Rev 0 0 8 Freescale Semiconductor 2 1 Pin Definitions Table 2 details the MC1321x pinout and functionality Table 2 Pin Function Description Pin Pin Name Type Description Functionality 1 PTAS3 KBI1P3 Digital MCU Port A Bit 3 Input Output Keyboard Input Bit 3 2 PTA4 KBI1P4 Digital MCU Port A Bit 4 Input Output Keyboard Input Bit 4 3 PTAS KBI1P5 Digital MCU Port A Bit 5 Input Output
83. ures below and also program the SS signal to have the proper use to support the modem transaction protocol for the modem CE signal MC13211 212 213 214 Technical Data Rev 0 0 Freescale Semiconductor 33 5 7 1 1 SPI Features Features of the SPI module use include e Used in master mode only Programmable transmit bit rate maximum usable rate is 8 MHz with modem e Double buffered transmit and receive Serial clock phase and polarity option must be programmed to CPHA 0 and CPOL 0 e Programmable slave select output to support modem SPI protocol e MSB first data transfer 5 7 1 2 SPI Module Block Diagram Figure 19 is a block diagram of the SPI module The central element of the SPI is the SPI shift register Data is written to the double buffered transmitter write to SPI1D and gets transferred to the SPI shift register at the start of a data transfer After shifting in a byte of data the data is transferred into the double buffered receiver where it can be read read from SPI1D Pin multiplexing logic controls connections between MCU pins and the SPI module When the SPI is configured as a master the clock output is routed to the SPSCK pin the shifter output is routed to MOSI and the shifter input is routed from the MISO pin PIN CONTROL M MOSI SPE s 4 mosi Tx BUFFER WRITE ENABLE M rar EE SHIFT SHIFT ER s OUT SPI SHIFT REGISTER IN Rx
84. using all the previously stated factors It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS Root Sum Square analysis The aging factor is usually specified in ppm year and the product designer can determine how many years are to be assumed for the product lifetime Taking all of the factors into account the product designer can determine the needed specifications for the crystal and external load capacitors to meet the IEEE 802 15 4 specification C10 6 8pF MC1321x C11 1 6 8pF Y1 Daishinku KDS DSX321G ZD00882 Figure 34 MC1321x Modem Crystal Circuit 7 1 2 Suggested Crystals Three suggested crystal types are shown in Table 21 Table 22 and Table 23 These variations are given because the crystals have different trade offs between cost and usage Table 21 Daishinku KDS DSX321G ZD00882 Crystal Specifications 2 Parameter Value Unit Condition Type DSX321G surface mount Freguency 16 MHz Frequency tolerance 20 ppm at 25 C 3 C Equivalent series resistance 100 Q max MC13211 212 213 214 Technical Data Rev 0 0 64 Freescale Semiconductor Table 21 Daishinku KDS DSX321G ZD00882 Crystal Specifications continued Parameter Value Unit Condition Temperature drift 20 ppm 10 C to 60 C Load capacitance 8 0 p

FREESCALE SEMICONDUCTOR MC13211/212/213/214 Manual

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