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MICROCHIP dsPIC30F5015/5016 Data Sheet

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1. FIGURE 20 2 A D CONVERTER VOLTAGE REFERENCE SCHEMATIC gt 82 Pais dsPIC30F vss 4 7 7 la tLe 20 7 1 1 Msps CONFIGURATION 20 7 1 2 Multiple Analog Inputs GUIDELINE The configuration for 1 Msps operation is dependent on whether a single input pin is to be sampled or whether multiple pins will be sampled 20 7 1 1 For conversions at 1 Msps for a single analog input at least two sample and hold channels must be enabled The analog input multiplexer must be configured so that the same input pin is connected to both sample and hold channels The A D converts the value held on one S H channel while the second S H channel acquires a new input sample Single Analog Input The A D converter can also be used to sample multiple analog inputs using multiple sample and hold channels In this case the total 1 Msps conversion rate is divided among the different input signals For example four inputs can be sampled at a rate of 250 ksps for each signal or two inputs could be sampled at a rate of 500 ksps for each signal Sequential sampling must be used in this configuration to allow adequate sampling time on each input DS70149A page 138 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 20 7 1 3 1 Msps C
2. Spley 19481691 jo suonduosep 10 970045 J0 2IdSp 19 94 peziemuun 0000 0000 0000 0000 01559 11850 21559 61550 FISSO 91559 91559 21550 81550 61559 011552 1582 211550 611550 11550 911550 20 1SS00V 0000 0000 0000 0000 09 DADd 69 04 69 04 VOADd SOdOd 99 24 29404 80 244 69dOd 01959 24 619 024 LOdOd 79 024 19 04 8 20 0000 0000 0000 0000 lt 0 gt VSOHO VNOHO VS CLHO 0 L2VNECLHO lt 0 gt GSOHO 6562 lt O I gt aNECIHO 9vcO SHOGV 0000 0000 0000 0000 lt 0 4 gt 5 0 ouav lt 0 7 gt 0NVS 14444 NOOQV 0000 0000 0000 0000 SLIV W4Ng lt 0 gt Id INS sind lt 0 1 gt SdHO VNOSO lt 0 2 gt D4 0A ALA 2 0000 0000 0000 0000 INOQ dWVS NYSY INVSWIS lt 0 2 gt OUSS lt 0 L gt INYOS Tdisaqv NOQV 0V lt 0 LNODOV nnnn nnnn nnoo 0000 91 Jeyxng 1600 J4ngaoav nnnn nnnn 00 0000 1eyng 9620 nnnn 00 0000 I J9yng ereg 6 danaoav nnnn nnnn nnoo 0000 ZL Jeyng eieg 86c0 nnnn nnnn 10100 0000 LL Jeyng 9620 nnnn nnnn nn
3. TABLE 20 1 10 CONVERSION RATE PARAMETERS dsPIC30F 10 bit A D Converter Conversion Rates A D Speed TAD Sampling Rs Max VDD Temperature A D Channels Configuration Minimum Time Min Up to 83 33 ns 12 TAD 5000 4 5Vto 5 5V 40 C to 85 C PES 1 Msps anx Dx 2 or CH3 S H ez CHO ADC 95 24 2 5000 4 5V to 5 5V 40 C to 85 C 750 ksps re a Dq pete ADC Up to 138 89 12TAD 5000 3 0Vto5 5V 40 C to 125 C 600 ANx gt CH1 CH2 or CH3 OK CHO 7 Abe S H Up to 153 85 ns 1 TAD 5 0 4 5V to 5 5V 40 C to 125 C 500 ksps Xx Dd sm se ADC Up to 256 41 ns 1 TAD 5 0 kQ 3 0V to 5 5V 40 C to 125 C 900 ksps EE yell ADC Note 1 External VREF and VREF pins must be used for correct operation See Figure 20 2 for recommended circuit 2005 Microchip Technology Inc Preliminary DS70149A page 137 dsPIC30F5015 5016 The configuration guidelines give the required setup values for the conversion speeds above 500 ksps since they require external VREF pins usage and there are some differences in the configuration procedure Configuration details that are not critical to the conversion speed have been omitted The following figure depicts the recommended circuit for the conversion rates above 500 ksps
4. DS700149A page 40 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 5 0 INTERRUPTS Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046 For more information on the device instruction set and pro gramming refer to the dsPIC30F Programmer s Reference Manual DS70030 The dsPIC30F5015 5016 has 36 interrupt sources and 4 processor exceptions traps which must be arbitrated based on a priority scheme The CPU is responsible for reading the Interrupt Vector Table IVT and transferring the address con tained in the interrupt vector to the program counter The interrupt vector is transferred from the program data bus into the program counter via a 24 bit wide multiplexer on the input of the program counter The Interrupt Vector Table IVT and Alternate Inter rupt Vector Table AIVT are placed near the beginning of program memory 0x000004 The IVT and AIVT are shown in Figure 5 1 The interrupt controller is responsible for pre processing the interrupts and processor exceptions prior to their being presented to the processor core The peripheral interrupts and traps are
5. Access Program Space Address lt 23 gt lt 22 16 gt lt 15 gt lt 14 1 gt lt 0 gt Instruction Access User 0 PC lt 22 1 gt 0 TBLRD TBLW User TBLPAG lt 7 0 gt Data EA lt 15 0 gt TBLPAG lt 7 gt 0 TBLRD TBLW Configuration TBLPAG lt 7 0 gt Data EA lt 15 0 gt TBLPAG lt 7 gt 1 Program Space Visibility User 0 PSVPAG lt 7 0 gt Data EA lt 14 0 gt FIGURE 3 2 DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION 23 bits Using Program 0 Program Counter 0 Counter ae EA Using Program 0 PSVPAG Reg Space a lt gt Visibility 8 bits 15 bits l EA Using 1 0 TBLPAG Reg Table sta x Instruction 8 bits 16 bits S 2 User Configuration 24 bit EA Byte Space Select Select Note Program Space Visibility cannot be used to access bits lt 23 16 gt of a word in program memory DS70149A page 24 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 3 1 1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24 bit wide program memory Consequently instructions are always aligned How ever as the architecture is modified Harvard data can also be present in program space There are two methods by which program space can be accessed via special table instructions or through the remapping of a 16K word program space page into the upper half of
6. 20 28 OCA Output Compare 4 21 29 T4 Timer4 22 30 T5 Timer5 23 31 INT2 External Interrupt 2 24 32 Reserved 25 33 Reserved 26 34 SPI2 27 35 C1 Combined IRQ for CAN1 28 36 IC3 Input Capture 3 29 37 IC4 Input Capture 4 30 38 Reserved 31 39 Reserved 32 40 OC5 Output Compare 5 33 41 OC6 Output Compare 6 34 42 OC7 Output Compare 7 35 43 OC8 Output Compare 8 36 44 INT3 External Interrupt 3 37 45 INT4 External Interrupt 4 38 46 Reserved 39 47 PWM PWM Period Match 40 48 Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA PWM Fault A 44 52 FLTB PWM Fault B 45 53 53 61 Reserved Lowest Natural Order Priority DS700149A page 42 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 5 2 Reset Sequence A Reset is not a true exception because the interrupt controller is not involved in the Reset process The processor initializes its registers in response to a Reset which forces the PC to zero The processor then begins program execution at location 0x000000 A instruction is stored in the first program memory loca tion immediately followed by the address target for the GOTO instruction The processor executes the GOTO to the specified address and then begins operation at the specified target start address 5 2 1 RESET
7. PORTE t C1RX RFO C1TX RF1 SCL RG2 U1RX RF2 SDA RG3 U1TX RF3 lt gt SCK2 CN8 RG6 X CN17 RF4 re SDI2 CN9 RG7 CN18 RF5 SDO2 CN10 RG8 EMUC3 SCK1 INTO RF6 J94 SDI1 RF7 2 CN11 R SS2 CN11 RG9 EMUD3 SDO1 RF8 RGO RG1 ER ER PORTG PORTF 2005 Microchip Technology Inc Preliminary DS70149A page 11 dsPIC30F5015 5016 Table 1 1 provides a brief description of the device I O pinout and the functions that are multiplexed to the port pins on the dsPIC30F5016 Multiple functions may exist on one port pin When multiplexing occurs the peripheral module s functional requirements may force an override of the data direction of the port pin TABLE 1 2 PIN DESCRIPTIONS For dsPIC30F5016 Pin Name Pin Buffer Description Type Type ANO AN15 Analog Analog input channels ANO and AN1 are also used for device programming data and clock inputs respectively AVDD P P Positive supply for analog module AVss P P Ground reference for analog module CLKIN ST CMOS External clock source input Always associated with OSC1 pin function CLKO Oscillator crystal output Connects to crystal or resonator in Crystal Oscillator mode Optionally functions as CLKO in RC and EC modes Always associated with OSC2 pin funct
8. AN9 RB Data EEPROM NOBEL 0 1 Kbyte L Effective Address NN AN11 RB11 Data Latch 16 AN12 RB12 AN13 RB13 AN14 RB14 AN15 CN12 RB15 ROM Latch 46 24 T2CK RC1 T4CK RC3 16 Fe EMUD1 SOSCI CN1 RC13 25 EMUC1 SOSCO T1CK CNO RC14 OSC2 CLKO RC15 Y 16 x 16 W Reg Array Decode PORTC Decode amp 6 16 Control EMUC2 0C1 RDO EMUD2 OC2 RD1 OC3 RD2 OC4 RD3 CN13 RD4 CN14 RD5 CN15 RD6 CN16 UPDN RD7 IC1 RD8 IC2 RD9 ICS RD10 IC4 RD11 RD12 Control Signals DSP to Various Blocks Power up Engine Unit Timer OSCI CLKIN Timing o Oscillator Generation Start up Timer 4 POR BOR NL ALUCt6 Reset MCLR Watchdog 16 16 Timer Low Voltage CN19 RD13 9 CN20 RD14 DD VSS Detect gt FX CN21 RD15 DD AVSS PORTD lt lt A PWM1L REO PWM1H RE1 PWM2L RE2 PWM2H RE3 PWMSL RE4 PWMSH RE5 PWM4L RE6 PWM4H RE7 FLTA INT1 RE8 FLTB INT2 RE9 Input Output CAN1 10 bit ADC Capture Compare Module Module V V Motor Control SPI Timers BWN UART1
9. 142 Conversion Operation 185 Effects of a Reset 141 Operation During CPU Idle Mode s 141 Operation During CPU Sleep Mode 141 Output Formats 0 804 141 Power Down Modes 141 Programming the Start of Conversion Trigger 136 Register Map issues 143 Result BUffer iier erede ere 135 Selecting the Conversion Clock 136 Selecting the Conversion Sequence 135 AC Temperature and Voltage Specifications 185 AC Characteristics 185 Internal FRC Jitter Accuracy and Drift 189 Internal LPRC Accuracy s Load Conditions PEL A sent Muse 187 Address Generator Units 2 44022221 35 Alternate Vector Table 45 Alternate 16 bit Timer Counter 89 Assembler MPASM Assembler Automatic Clock Stretch During 10 bit Addressing STREN 1 During 7 bit Addressing STREN 1 T Receive Mode Transmit Mode essere B Barrel Shifter s i eene 22 Bit Reversed Addressing 2 38 A 38 Impleme
10. Note 1 OSC2 pin function is determined by FPR lt 4 0 gt 2 OSC1 pin cannot be used as an pin even if the secondary oscillator or an internal clock source is selected at all times DS70149A page 148 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 21 2 2 OSCILLATOR START UP TIMER OST In order to ensure that a crystal oscillator or ceramic resonator has started and stabilized an Oscillator Start up Timer is included It is a simple 10 bit counter that counts 1024 Tosc cycles before releasing the oscillator clock to the rest of the system The time out period is designated as TOST The TOST time is involved every time the oscillator has to restart i e POR BOR and wake up from Sleep The Oscillator Start up Timer is applied to the LP XT XTL and HS Oscillator modes upon wake up from Sleep POR and BOR for the primary oscillator 21 2 3 LP OSCILLATOR CONTROL Enabling the LP oscillator is controlled with two elements 1 The current oscillator group bits COSC lt 2 0 gt 2 The LPOSCEN bit OSCON register The LP oscillator is ON even during Sleep mode if LPOSCEN 1 The LP oscillator is the device clock if e COSC lt 2 0 gt 000 LP selected as main oscillator and e LPOSCEN 1 Keeping the LP oscillator ON at all times allows for a fast switch to the 32 kHz system clock for lower power operation Returning to the faster main oscillator will still require a s
11. 170 530222252 A 170 Baud Rate Setting 128 Bit Timing ennt itr ree rre 128 Message 126 Acceptance Filter Masks 126 Acceptance Filters 126 Receive Buffers 126 Receive Errors 126 Receive Interrupts 126 Receive Overrun 126 Message Transmission Aborting A Errors usse uas Interrupts Sequence Lo Transmit Buffers eee 127 Transmit Priority 127 Modes of Operation s 125 Disable 125 Error Recognition 125 Initialization tnn 125 Listen Only 125 Loopback 125 Normal 2 125 Phase Segments 129 Prescaler Setting 129 Propagation Segment 129 Sample Point 129 Synchronization 129 CAN Module 123 CAN1 Register 130 Frame Types neo teen nei 123 II 123 Code Examples Data EEPROM Block Erase 56 Data EEPROM Block Write Data EEPROM Read Data EEPROM Word Erase D
12. 182 O Pin Output Specifications 183 Idle Current IIDLE Operating Current IDD Operating MIPS vs Voltage dsPIC30FB0O15 sese 174 dsPIC30F5016 174 Power Down Current IPD 181 Program and EEPROM 184 Temperature and Voltage Specifications 175 Thermal Operating Conditions 174 Development Support 169 Device Configuration Register 0 8 159 Device Configuration Registers 157 FBORPOR 157 FGS 157 FOSC 157 EWBT 5 teet eme 157 Device Overview 7 Divide Support 18 DSP Engine cette ren trs 18 Data Accumulators and Adder Subtractor 20 Accumulator Write Back 21 Data Space Write Saturation 22 Overflow and Saturation 20 Round Logic 2 21 M ltipligi s sec une 20 dsPIC30F5015 PORT Register Map ss 61 dsPIC30F5016 PORT Register Map wesc i ed na 62 Dual Output Compare Match Mode 84 Continuous Pulse Mode 84 Single Pulse Mode
13. S DS70149A page 14 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 2 0 CPU ARCHITECTURE OVERVIEW Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046 For more information on the device instruction set and pro gramming refer to the dsPIC30F Programmers Reference Manual DS70030 This document provides a summary of the dsPIC30F5015 5016 CPU and peripheral function For a complete description of this functionality please refer to the dsPIC30F Family Reference Manual DS70046 2 1 Core Overview The core has a 24 bit instruction word The Program Counter PC is 23 bits wide with the Least Significant bit LSb always clear see Section 3 1 Program Address Space and the Most Significant bit MSb is ignored during normal program execution except for certain specialized instructions Thus the PC can address up to 4M instruction words of user program space An instruction pre fetch mechanism is used to help maintain throughput Program loop constructs free from loop count management overhead are supported using the DO and REPEAT instructions both of which are interruptible at any point The working register array consi
14. 0 lt gt 0 2960 aI30XLLO nnnn nnnn goon nnnn HHS lt 0 6 gt PJEPUEJS Jeying 9 0L24eynuep PIEPUEIS 0 Jeyng HUSUEIL 0950 GISOXLLO 0000 0000 0000 0000 lt 0 gt 14dXL Em OJHXL YYAXL 44VIXL LEVXL F 3580 NODIXLIO nnnn 9 914g HLUSUEJ 2560 vVaLXLILO nnnn nnnn nnnn nnnn eig HLUSUEJ S eig HUISUEIL VSE0 nnnn nnnn nnnn nnnn Jeyng 914g Jeyng 8560 alXLLO 9 5 Jose 018 s 1g v 1g xa 81g 61g vrug Sl 1g HdS GSNNILNOD 53151999 LNVO 1 61 31971 0570149 131 iminary Prel 2005 Microchip Technology Inc dsPIC30F5015 5016 NOTES i i DS70149A page 132 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 20 0 10 BIT HIGH SPEED ANALOG TO DIGITAL CONVERTER A D MODULE Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046
15. 170 N NVM Register ss 538 Oscillator Operating Modes Table System Overview Oscillator Configurations seen Fail Safe Clock Monitor Fast RC FRC m Initial Clock Source Selection 148 Low Power RC LPRC 150 LP Oscillator Control 149 Phase Locked Loop PLL 149 Start up Timer OST 2 0 2222222 149 Oscillator Selection 145 Output Compare Module 83 Interrupts 85 Operation During CPU Idle Mode 85 Operation During CPU Sleep Mode 85 Register 0 0 86 Timer2 Timer3 Selection Mode 84 P Packaging ree RE 217 Marking orae tn die 217 Peripheral Module Disable PMD Registers 158 PICSTART Plus Development Programmer 172 Pinout Descriptions dsPICS30F5015 itr rtr Rete 9 dsPIC30E50196 5 erre trece 12 POR See Power on Reset Port Write Read Example 60 Position Measurement Mode 88 Power on Reset 145 Oscillator Start up Timer OST 145 Power up Timer PWRT
16. see 84 E Electrical Characteristics 2 4 2 4 173 Equations A D Conversion Clock 136 Baud Rate 2 PWM Period rar ttp Re pref 96 PWM Resolution eee 96 Serial Clock Rate 112 Time Quantum for Clock Generation 129 Errata M 5 F Fast Context Saving seen 45 Flash Program Memory sese 49 Erasing a ROW ronem mh eri eres 51 Initiating Programming Sequence 52 Loading Write Latches 52 Operations 2551 Programming Algorithm 51 Table Instruction Operation Summary 49 Ports 59 Parallel I O PIO 2 59 In Circuit Debugger ss 158 In Circuit Serial Programming ICSP 49 145 Initialization Condition for RCON Register Case 1 RE 155 Initialization Condition for RCON Register Input Capture Module Interrupts wats wha ia aie A Operation During Sleep and Idle Modes 80 Register Map Simple Capture Event Mode 79 Input Change Notification Module 63 Register Map Bits 15 8 for dsPIC30F5015 63 Register Map Bits 15 8 for dsPIC30F5016 63 Register Map Bits 7
17. 2005 Microchip Technology Inc Preliminary DS70149A page 177 dsPIC30F5015 5016 TABLE 24 6 DC CHARACTERISTICS OPERATING CURRENT 150 CONTINUED Standard Operating Conditions 2 5V to 5 5V unless otherwise stated DE CHARACTERISTICS Operating temperature 40 C lt TA lt 85 for Industrial 40 C lt lt 125 C for Extended Typical Max Units Conditions Operating Current 100 2 DC29 mA 40 C DC29a TBD mA 25 C 5V MIP DC29b mA 85 C DC29c mA 125 C Legend TBD To Be Determined Note 1 Data in Typical column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 2 The supply current is mainly a function of the operating voltage and frequency Other factors such as I O pin loading and switching rate oscillator type internal code execution pattern and temperature also have an impact on the current consumption The test conditions for all IDD measurements as follows OSC1 driven with external square wave from rail to rail All pins are configured as inputs and pulled to VDD MCLR VDD WDT FSCM and BOR are disabled CPU SRAM program memory and data memory are operational No peripheral modules are operating DS70149A page 178 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 TABLE 24 7 DC CHARACTERISTICS IDLE CURRENT IIDL
18. Lug zug ena sug 914 a vLug HAS d3lsi93u S CHAMNI L LOL FIAVL DS700149A page 73 iminary Prel 2005 Microchip Technology Inc dsPIC30F5015 5016 NOTES LD 2 eee eee DS700149A page 74 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 11 0 TIMER4 5 MODULE Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source For more information on the CPU peripherals register descriptions and general device functionality refer to the dsPIC30F Family Reference Manual DS70046 This section describes the second 32 bit General Purpose GP timer module Timer4 5 and associated operational modes Figure 11 1 depicts the simplified block diagram of the 32 bit Timer4 5 module Figure 11 2 and Figure 11 3 show Timer4 5 configured as two independent 16 bit timers Timer4 and Timer5 respectively Note 4 is a Type timer and Timer5 is Type C timer Please refer to the appropri ate timer type in Section 24 0 Electrical Characteristics of this document FIGURE 11 1 The Timer4 5 module is similar in operation to the Timer2 3 module However there are some differences which are listed below e The Timer4 5 module does
19. MCLR Reset during Sleep 0 000000 0 0 1 0 0 0 1 0 0 MCLR Reset during Idle 0x000000 0 0 1 0 0 1 0 0 0 WDT Time out Reset 0x000000 0 0 0 0 1 0 0 0 0 WDT Wake up PC 2 0 0 0 0 1 0 1 0 0 Interrupt Wake up from PC 201 0 0 0 0 0 0 1 0 0 Sleep Clock Failure Trap 0x000004 0 0 0 0 0 0 0 0 0 Trap Reset 0x000000 a 0 0 0 0 0 0 0 0 Illegal Operation Trap 0x000000 0 1 0 0 0 0 0 0 0 Legend u unchanged x unknown unimplemented bit read as 0 Note 1 When the wake up is due to an enabled interrupt the PC is loaded with the corresponding interrupt vector Table 21 6 shows a second example of the bit conditions for the RCON register In this case it is not assumed the user has set cleared specific bits prior to action specified in the condition column TABLE 21 6 INITIALIZATION CONDITION FOR RCON REGISTER CASE 2 Condition a TRAPR IOPUWR EXTR SWR IDLE SLEEP BOR Power on Reset 0x000000 0 0 0 0 0 0 0 1 1 Brown out Reset 0x000000 u u u u u u u MCLR Reset during normal 0x000000 u u 1 0 0 0 0 u u operation Software Reset during 0x000000 u u 0 1 0 0 0 u u normal operation MCLR Reset during Sleep 0x000000 u u 1 u 0 0 1 u u MCLR Reset during Idle 0x000000 u u 1 u 0 1 0 u u WDT Time out Reset 0x000000 u u 0 0 1 0 0 u u WDT Wake up PC 2 u u u u 1 u l u u Interrupt Wake up from PC 201 u u u u u u 1 u u Sleep Cloc
20. 44 U UART Address Detect Mode Auto Baud Support Baud Rate Generator Disabling Enabling Loopback Mode m Module Overview 2 Operation During CPU Sleep and Idle Modes 120 Receiving Data ss In 8 bit or 9 bit Data Mode Interrupt Receive Buffer UXRXB Reception Error Handling 118 Framing Error FERR Bit 119 Idle Status 119 Parity Error PERR Bit 119 Receive Break 119 Receive Buffer Overrun Error OERR Bit 118 Setting Up Data Parity and Stop Bit Selections niia Transmitting Data In 8 bit Data Mode In 9 bit Data Mode Interr pt rte Transmit Buffer UXTXB 117 UART1 Register Map 121 Unit ID Locations 145 Universal Asynchronous Receiver Transmitter Module UART 115 Wake up from Sleep 145 Wake up from Sleep and 45 Watchdog Timer 145 156 Enabling an
21. Note that many of these trap conditions can only be detected when they occur Consequently the question able instruction is allowed to complete prior to trap exception processing If the user chooses to recover from the error the result of the erroneous action that caused the trap may have to be corrected There are 8 fixed priority levels for traps Level 8 through Level 15 which implies that IPL3 is always set during processing of a trap If the user is not currently executing a trap and he sets the IPL lt 3 0 gt bits to a value of 0111 Level 7 then all interrupts are disabled but traps can still be processed 5 3 1 TRAP SOURCES The following traps are provided with increasing priority However since all traps can be nested priority has little effect Math Error Trap The math error trap executes under the following three circumstances 1 Should an attempt be made to divide by zero the divide operation will be aborted on a cycle boundary and the trap taken 2 f enabled a math error trap will be taken when an arithmetic operation on either Accumulator A or B causes an overflow from bit 31 and the Accumulator Guard bits are not utilized 3 If enabled a math error trap will be taken when an arithmetic operation on either Accumulator A or B causes a catastrophic overflow from bit 39 and all saturation is disabled 4 Ifthe shift amount specified in a shift instruction is greater than the maximum
22. The10 bit high speed analog to digital converter A D allows conversion of an analog input signal to a 10 bit digital number This module is based on a Successive Approximation Register SAR architecture and pro vides a maximum sampling rate of 1 Msps The A D module has 16 analog inputs which are multiplexed into four sample and hold amplifiers The output of the sample and hold is the input into the converter which generates the result The analog reference voltages are software selectable to either the device supply volt age AVDD AVSS or the voltage level on the VREF VREF pin The A D converter has a unique feature of being able to operate while the device is in Sleep mode The A D module has six 16 bit registers A D Control Register ADCON1 A D Control Register2 ADCON2 A D Control Register3 ADCONS3 A D Input Select Register ADCHS A D Port Configuration Register ADPCFG A D Input Scan Selection Register ADCSSL The ADCON1 ADCON2 and ADCONS registers control the operation of the A D module The ADCHS register selects the input channels to be converted The ADPCFG register configures the port pins as analog inputs or as digital The ADCSSL register selects inputs for scanning Note SSRC lt 2 0 gt ASAM SIMSAM SMPI lt 3 0 gt BUFM and ALTS bits as well as the ADCON3 and ADCSSL registers must not be written to while ADON 1 This would lead to indeterminate results
23. lt lt AVDD AVss ALU lt 16 gt 16 16 PORTC CAN1 10 bit ADC Input Capture Module Output Compare Module V Timers GEI Motor Control PWM UARTI SCK2 CN8 RG6 SDI2 CN9 RG7 SDO2 CN10 RG8 SS2 CN11 RG9 SCL RG2 SDA RG3 ER PORTG PORTD PORTE PORTF ANO VREF CN2 RBO AN1 VREF CN3 RB1 AN2 SS1 CN4 RB2 AN3 INDX CN5 RB3 AN4 QEA CN6 RB4 AN5 QEB CN7 RB5 PGC EMUC AN6 OCFA RB6 PGD EMUD AN7 RB7 AN8 RB8 AN9 RB9 AN10 RB10 AN11 RB11 AN12 RB12 AN13 RB13 AN14 RB14 AN15 CN12 RB15 EMUD1 SOSCI TACK CN1 RC13 EMUC1 SOSCO T1CK CNO RC14 OSC2 CLKO RC15 EMUC2 0C1 RDO EMUD2 OC2 RD1 OC3 RD2 OC4 RD3 IC5 CN13 RD4 IC6 CN14 RD5 CN15 RD6 UPDN CN16 RD7 IC1 FLTA INT1 RD8 IC2 FLTB INT2 RD9 ICS INTS RD10 IC4 INT4 RD11 PWM1L REO PWM1H RE1 PWM2L RE2 PWM2H RE3 PWMSL RE4 PWMSH RE5 PWM4L RE6 PWM4H RE7 C1RX RFO C1TX RF1 U1RX SDI1 RF2 EMUD3 U1TX SDO1 RF3 CN17 RF4 CN18 RF5 EMUC3 SCK1 INTO RF6 DS70149A page 8 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 Table 1 1 provides a brief description of the device I O pinout and the func
24. 145 Power Saving Modes 156 Idle 157 Ele 156 Power Saving Modes Sleep and Idle 145 Program Address Space Construction Data Access from Program Memory Using Program Space Visibility 26 Data Access from Program Memory Using Table Instructions 25 Data Access from Address Generation 24 Memory 23 Table Instructions TBLRDH TBLRDL 2 ea TBEWTIE RE Gen ni Program Counter Program Data Table Access MSB Program Space Visibility Window into Program Space Operation 27 Programmable 145 Programmable Digital Noise Filters 89 Programmer s Model 16 Protection Against Accidental Writes to OSCCON 151 PWM Center Aligned ss Complementary Operation 5 Dead Time Generators ASSignment 2 nd Ranges Selection Bits Duty Cycle Comparison Units es Immediate Updates 97 Register Buffers sese 97 Edge Aligned 96 Fault Pins 100 Enable Bits 100 Fault States uen anses 100 Input Modes 4
25. mA 85 C DC49c mA 125 C Legend TBD To Be Determined Note 1 Data in Typical column is at 5V 25 C unless otherwise stated Parameters are for design guidance only and are not tested 2 Base lIDLE current is measured with core off clock on and all modules turned off DS70149A page 180 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 TABLE 24 8 DC CHARACTERISTICS POWER DOWN CURRENT IPD Standard Operating Conditions 2 5V to 5 5V unless otherwise stated DC CHARACTERISTICS Operating temperature 40 C lt Ta lt 85 C for Industrial 40 C lt lt 125 C for Extended ete Typical Max Units Conditions Power Down Current IPD 2 DC60 40 C DC60a TBD A 25 C 3 3V DC60b 85 DC60c A 125 C Base Power Down Current DC60d 40 C DC60e TBD 25 C DC60f 85 DC60g 125 C DC61 40 C DC61a TBD 25 C 3 3V DC61b 85 DC61c A 125 C Watchdog Timer Current AIWDT DC61d 40 C DC61e TBD 25 C BV DC61f 85 DC61g uA 125 C DC62 40 C DC62a TBD 25 C 3 3V DC62b 85 DC62c A 125 C w 32 kHz Crystal
26. Receiver error passive The RXEP bit indicates that the Receive Error Counter has exceeded the error passive limit of 127 and the module has gone into Error Passive state 19 5 Message Transmission 19 5 1 TRANSMIT BUFFERS The CAN module has three transmit buffers Each of the three buffers occupies 14 bytes of data Eight of the bytes are the maximum 8 bytes of the transmitted mes sage Five bytes hold the standard and extended identifiers and other message arbitration information 19 5 2 TRANSMIT MESSAGE PRIORITY Transmit priority is a prioritization within each node of the pending transmittable messages There are 4 levels of transmit priority If TXPRI 1 0 CiTXnCON lt 1 0 gt where 0 1 or 2 represents a particular transmit buffer for a particular message buffer is set to 11 that buffer has the highest priority If TXPRI lt 1 0 gt for a particular message buffer is set to 10 or 01 that buffer has an intermediate priority If TXPRI lt 1 0 gt for a particular message buffer is 00 that buffer has the lowest priority 19 5 3 TRANSMISSION SEQUENCE To initiate transmission of the message the TXREQ bit CiTXnCON lt 3 gt must be set The CAN bus module resolves any timing conflicts between setting of the TXREQ bit and the Start of Frame SOF ensuring that if the priority was changed it is resolved correctly before the SOF occurs When TXREQ is set the CiTXnCON lt 6 gt TX
27. 0 3V to 5 5V Voltage on MCLR with respect to 55 OV to 13 25V Maximum current out of VSS PIN d se I EE ER la ra ri hava larva aa 300 mA Maximum current into VDD Note 2 iii 250 mA Input clamp current VI lt or VI gt 0 20 mA Output clamp current IOK VO lt 0 or VO gt VDD nennen nnn 20 mA Maximum output current sunk by any I O pin ss 25 mA Maximum output current sourced by any I O pin sise 25 mA Maximum current sunk by all ports sise 200 mA Maximum current sourced by all ports Note 2 200 mA Note 1 Voltage spikes below Vss at the MCLR VPP pin inducing currents greater than 80 mA may cause latch up Thus a series resistor of 50 100Q should be used when applying a low level to the MCLR VPP pin rather than pulling this pin directly to Vss 2 Maximum allowable current is a function of device maximum power dissipation See Table 24 6 TNOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliabi
28. The block diagram of the A D module is shown in Figure 20 1 2005 Microchip Technology Inc Preliminary DS70149A page 133 dsPIC30F5015 5016 FIGURE 20 1 10 BIT HIGH SPEED A D FUNCTIONAL BLOCK DIAGRAM AVSS VREF Note 1 lt VREF Note 2 Y Y ANO e ANO x 0 70 S H gt CHI ADC oo 0 AN9 o lt s oo 10 bit Result Conversion Logic lt gt AM s sH gt CM AN105 16 word 10 bit 19 6 o Dual Port AS Buffer AN2 9 x ANS ae S H 3 AN8 CH1 CH2 CH3 CHO Sample Seguence a 5 7 e sample Control input AN2 switches Input MUX AN3 SZ 4 AN3 Control SZ AM AN5 e ANS AN6 e ooo e ooo sd AN9 AN9 AN10 S 10 AN11 ANII e AN12 SZ 12 5 e AN13 13 lt AN14 14 AN15 X 15 o e 0 sm gt LL oq AN 5 Note 1 VREF is multip
29. TxCK Input Period Synchronous 10 ns N prescaler value Synchronous Greater of 1 8 64 256 with prescaler 20 ns or Tcy 40 N TC20 TCKEXTMRL Delay from External TxCK Clock 0 5 15 Edge to Timer Increment DS70149A page 194 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 FIGURE 24 8 TIMERQ MODULE EXTERNAL CLOCK TIMING CHARACTERISTICS POSCNT gt 1 Y A TQ20 TABLE 24 26 MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions 2 5V to 5 5V unless otherwise stated AC CHARACTERISTICS Operating temperature 40 C lt TA lt 85 C for Industrial 40 C lt TA lt 125 C for Extended Symbol Characteristic Min Typ Max Units Conditions TQ10 TQCK High Time Tcy 20 ns Must also meet with prescaler parameter TQ15 TQ11 TQCK Low Time Synchronous 20 ns Must also meet with prescaler parameter TQ15 15 TQCP Input Period Synchronous 2 TCY 40 ns with prescaler TQ20 TCKEXTMRL Delay from External TxCK Clock 0 5 Tcy 1 5 TcY ns Edge to Timer Increment Note 1 These parameters are characterized but not tested in manufacturing 2005 Microchip Technology Inc Prelimina
30. lt lt Stretching Write q I2CTRN Eu Shift LSB V Read Reload T gt gt Control Write TK lt BRGDown K I2CBRG N Counter pay Read DS70149A page 108 Preliminary 2005 Microchip Technology Inc dsPIC30F5015 5016 17 2 Module Addresses The I2CADD register contains the Slave mode addresses The register is a 10 bit register If the A10M bit 2 lt 10 gt is 0 the address is interpreted by the module as a 7 bit address When an address is received it is compared to the 7 LSbs of the I2CADD register If the A10M bit is 1 the address is assumed to be a 10 bit address When an address is received it will be compared with the binary value 1 1 1 1 0 A9 A8 where 9 8 are two Most Significant bits of I2CADD If that value matches the next address will be compared with the Least Significant 8 bits of I2CADD as specified in the 10 bit addressing protocol 7 bit C Slave Addresses supported by dsPIC30F 0x00 General call address or start byte 0x01 0x03 Reserved 0x04 0x77 Valid 7 bit addresses 0x78 0x7b Valid 10 bit addresses lower 7 bits Ox7c Ox7f Reserved 17 3 7 bit Slave Mode Operation Once enabled I2CEN 1 the slave module will wait for a Start bit to occur i e the IPC
31. 16 5 SPI Operation During CPU Idle Mode When the device enters Idle mode all clock sources remain functional The SPISIDL bit SPIXSTAT lt 13 gt selects if the SPI module will stop or continue on Idle If SPISIDL 0 the module will continue to operate when the CPU enters Idle mode If SPISIDL 1 the module will stop when the CPU enters Idle mode 2005 Microchip Technology Inc Preliminary DS70149A page 105 dsPIC30F5015 5016 Spley 4q 191sIBoJ Jo suonduosep 10 970045 jenuejy JO OIdSD 01 1 8JON peziemiuun 0000 0000 0000 0000 Jeyng 8118984 pue HUSUEJ Veco 5309198 0000 0000 0000 0000 L3Hdd O3HdS 13995 5 N3ISW N3SS 3MO ans 9 43GOW 1 asdids NAWH4 8220 NOOZIdS 0000 0000 0000 0000 A8HidS 44LI4S NOHIdS 1415195 9220 IVLSZIdS 9 EJS v ng a erua HAS 93151999 2145 2 91 379 4q 19481691 jo suonduosep 10 970045 4001950 01 1 0 0N peziemiuun pus 697 0000 0000 0000 0000 Jeyng
32. In order to erase a block of data EEPROM the NVMADRU and NVMADR registers must ini