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INFINEON PMA7110 Manual

1. T3Mask 4 Figure 26 Timer mode 1 Preliminary Data Sheet 98 V0 9 2008 04 28 Cinfineon em Functional Description Timer mode 2 Comprises 8 bit timer with reload 8 bit timer with reload and bitrate strobe signal for RF Transmitter Timer 2 sets up a reloadable 8 bit timer holding the start value SFR TLO timer reload value SFR THO timer run bit SFR bit TCON2 0 TORun and timer elapsed indicator SFR bit TCON2 1 TOFull Timer 3 sets up a reloadable 8 bit timer holding the start value SFR TL1 timer reload value SFR TH1 timer run bit SFR bit TCON2 4 T1Run and timer elapsed indicator SFR bit TCON2 5 T1Full IE 7 EA IE 6 EID amp Interrupt Timer 2 2 2 T2Mask gt T2Full T2Run Timer 2 Timer 2 Reload Reload Baudrate strobe T3Run Timer 3 Timer 3 Reload T3Full gt IE 7 EA U I Fe EA amp bo Interrupt TL3 TH3 IE 6 EID Timer 3 T3Mask Figure 27 Timer mode 2 Preliminary Data Sheet 99 V0 9 2008 04 28 Cinfineon em Functional Description Timer mode 3 Comprises 8 bit timer without reload 1 8 bit timer without reload 2 8 bit timer with reload and bitrate strobe signal for RF Transmitter Timer 2 1 utilizes SFR TLO as starting value and TOFull as timer elapsed flag Setting SFR bit TCO
2. Cinfineon eae Reference Table 133 SFR Address 5 FCSS Flash Control Register for Single Step Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SelRefCell1 SelRefCell0 VPPCh VProgPCh 55 5 SSALE SSWRB rw 1 1 rw 1 1 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 Bit 7 SelRefCell1 Selects RefCells 3 and 2 Bit 6 SelRefCellO Selects RefCells 1 and 0 Bit 5 VPPCh Charge pump charging indicator for VPP Bit 4 VProgPCh Charge pump charging indicator for VProgP Bit 3 VProgNCh Charge pump charging indicator for VProgN Bit 2 SSCSB Single Step Chip Select Bar Bit 1 SSALE Single Step Address Latch Enable Bit 0 SSWRB Single Step Write Read Bar Table 134 SFR Address LBD Low Battery Detector Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u n u LBD2V1 LBDF LBDEn LBDMen 0 0 0 0 0 0 0 0 rw 1 1 0 0 rw 1 1 rw 1 1 Bit 3 LBD2V1 Low Battery Voltage Switch 1 2 1V VEXT 0 2 4V VDDC Bit 2 LBDF Low Battery Detector Flag 1 Supply Voltage below threshold Bit 1 LBDEn Low Battery Detector enable Bit 0 LBDMen Low Battery Detector measurement enable Preliminary Data Sheet 154 V0 9 2008 04 28 Cinfin eon PMA7110 Reference Table 135 SFR Address D6 OSCCONF RC HF Oscillator Configuration Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi
3. 250 GND vant gum N 500 JF 5 GND LE 7 gt 22 MSE Mode Select Enable VBat MSE 500 MSE i D 250k Preliminary Data Sheet 22 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Pin PAD name Equivalent I O Schematic Function No 23 Test Mode Enable VBat TME EB TME i ER o Ej E 250k 24 XTALCAP Crystal oscillator 10 output XTALCAP L L 25 KTAL SCLK Crystal oscillator input pa SCLK Tb XTAL 4 0 9Vdo 500 XGND OR ii d Preliminary Data Sheet 23 V0 9 2008 04 28 Cinfineon 5 Functional Description Pin PAD name Equivalent I O Schematic Function No 26 KGND Crystal oscillator PGND gt ground e L ZN 1 27 AMUX1 Additional pol differential ADC standard input1 for LJ external sensor Analog Testsignal 509 E H EN i 1 7 FE 7 GND GND esessssesessesen asa 28 AMUX2 Additional PC differential ADC gr Stan
4. SFR Abbr Addr Access Default Value Register THO BCh rw 004 00 Timer 0 Register Upper Byte rw 00 00 Timer 0 Register Lower Byte TH1 eD rw 00 00 Timer 1 Register Upper Byte TL1 eB rw 00 00 Timer 1 Register Lower Byte TH2 CD rw 00 00 Timer 2 Register Upper Byte TL2 CC rw 00 00 Timer 2 Register Lower Byte TH3 rw 00 00 Timer 3 Register Upper Byte TL3 CA rw 00 00 Timer 3 Register Lower Byte SFR TCON and SFR TCON2 are used for starting and stopping timers and for status indication of all timers Note The purpose of this bits depends on the selected timer mode Table 44 SFR Address 88 TCON Timer Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TF1 TR1 TRO IE1 IT1 IEO ITO rw 0 0 rw 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 TF1 Timer 1 Overflow Flag TR1 Timer 1 Run control Bit Timer 0 Overflow Flag TRO Timer 0 Run control Bit IE1 Interrupt 1 Edge Flag IT1 Interrupt 1 Type control bit IEO Interrupt O Edge Flag ITO Interrupt O Type control bit Setting the SFR bit TCON 4 TRO respectively SFR bit TCON 6 TR1 starts Timer 0 resp Timer 1 It counts using the selected clock see SFR TMOD until the timer is elapsed SFR bit TCON 5 TFO resp SFR bit TCON 7 TF 1 is set If the selected timer mode used timer reload then the timer is automatically reloaded and res
5. 4 40 Watchdog Timer 21224222212 029290 4 1k pe basket ekke ke 40 Detector ee 40 FLASH Memory Checksum 40 ADC Measurement Overflow amp Underflow 40 IMAX Detectof deeds cae Ere bek add T 40 Functional Block Description 41 Sensor Interfaces and Data Acquisition 41 Sensor Interface p bn 41 Two differential high sensitive interfaces to external Sensors 43 Interface to other signals 44 Reference voltages 44 Temperature Sensor sesi kes 44 0 ae ER E gee ade an 46 Battery Voltage 46 Memory Organization and Special Function Registers SFR 47 ROM GT 48 FLASH bd Sob torsade a vine dad eere ute bods 49 EE 51 Special Function Registers 51 Microcontroller Sse oes Sans smed e kk RA 57 System Configuration Registers 58 General Purpose Registers 61 System Controller sa 95 ld
6. 2 5 17 PROGRAMMING mode Operation In PROGRAMMING mode the PMA7 110 is accessible as a slave using the Interface The device is operating using the 12 MHz RC HF Oscillator as clock source To avoid programming failures all PROGRAMMING mode commands are protected by a 16 bit CRC at the end of each command 16Bit CRC Cyclic Redundancy Check Generator Checker on Page 86 shows details about the used CRC polynom The checksum has to be calculated over all bytes in the command excluding the 7110 device address PROGRAMMING mode commands FLASH Write Line FLASH Erase FLASH Check Erase Status FLASH Read Line FLASH Set Lockbyte 3 ReadStatus 2 5 17 1 FLASH Write Line The FLASH Write Line command writes 32 bytes to the FLASH start address is a multiple of 20 1 If transferring the start address the lower 5 bits are cleared automatically Ifless than 32 data bytes are received the contents of the previous write access are written into the FLASH Preliminary Data Sheet 117 V0 9 2008 04 28 Cinfineon Functional Description If an already written section in the FLASH gets re written without being erased before the resulting data is undefined Note After the Stop condition P is received the data is programmed into the FLASH During the programming time incoming IC commands are not acknowledged See Rats gt ERCH
7. PA V2P T 3 Microcontroller 2 Amp PGND a V2N 5 Reference Wit 8081 Diff standard input E voltage amp S g Crystal XTAL 3 offset DAC 53 2 i AMUX1 Interrupt controller XTALC AMUX2 2 ALCAP ADC state 2 ASK FSK mm B machine System controller modulator modulator XGND AD 5 EX 5 LF receiver Bandgap and 5 18 21 18 125kHz PTAT 8 815 Digital Carrier Receiver 212 8 Receiver detector Vmin and Voltage Regulators Brownout 2 2 RC Special CRC Watch TMAX Tm law PRNG detector LP function generator dog Timer Oscillator registers SFR ti detector power dropout Reset MSE V reg V reg o a 8 9 lt Ihe gt gt 79 gt gt Figure 2 PMA7110 Block Diagram Preliminary Data Sheet 28 V0 9 2008 04 28 Cinfineon em Functional Description 2 3 Operating Modes and States The PMA7110 can be operated in four different operating modes NORMAL mode PROGRAMMING mode DEBUG mode internal production TEST mode 2 3 1 Operating mode selection SYSTEM RESET POR xReset Software reset Brown out even SCAN Test Mode Mode Select 1 110 1 1 01 Lockbyte set MSE 1 1 PP1 0 Lockbyte II not set Lockbyte II not set Note If Lockbyte I and or Il is set only a reduced Test command set is available Note Whenever TME is set
8. we ue 62 Wakeup Logie 62 Interval Timer 455256 Uer ace vl dum 68 Preliminary Data Sheet 6 V0 9 2008 04 28 Cinfineon 2 5 6 3 2 5 7 2 5 7 1 2 5 7 2 2592719 2 5 8 2 59 2 5 9 1 2 5 9 2 2 5 9 3 2 5 9 4 2 5 9 5 2 5 10 2 5 11 2 5 12 2 5 13 2 5 13 1 2 5 13 2 2 5 13 3 2 5 14 2 5 14 1 2 5 14 2 2 5 14 3 2 5 14 4 2 5 15 2 5 15 1 2 5 15 2 2 5 15 3 2 5 16 2 5 17 2 5 17 1 2 5 17 2 2 5 17 3 2 5 17 4 2 5 17 5 2 5 17 6 2 5 17 7 Interval Timer Calibration 69 Clock Controller ae ee head Y db es day 70 2 kHz RC LP Oscillator Low Power 71 12 MHz RC HF Oscillator High Frequency 71 Crystal Oscillator hmc ada C EEG veret 71 Interrupt Sources on the Dev NameShort1 gt 74 315 434 868 915 MHz FSK ASK Transmitter 78 Phase Locked Loop PLL 1 I 79 Power 80 ASK Modulator 2 sea gar c c ped Sx pice ud EC 80 Voltage Controlled Oscillator 80 Manchester BiPhase Encoder with bit Rate 81 LE ReGetvet ev ud es 85 16Bit CRC Cyclic Red
9. Preliminary Data Sheet 145 V0 9 2008 04 28 Infineon 5 Reference Table 99 SFR Address D3 ADCS ADC Startus Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SARSATL SARSATH 1000 n u SAMPLE BUSY 0 0 0 0 0 0 0 0 r 0 0 0 0 0 0 0 0 SARSATL negative saturation of SAR SARSATH positive saturation of SAR CL000 0x000 saturation of c net control word CG3FF Dx3FF saturation of c net control word SAMPLE Sample Hold BUSY Busy Table 100 SFR Address ADWBC AD WBC Wire Bond Check Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u STAT3 2 DREF WBEF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STAT3 reserved STAT2 reserved DREF Diagnostic Resistor Error Flag BUSY Wire Bond Error Flagl Table 101 SFR Address 9 FCSP Flash Control Register Sector Protection Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ECCLeft WLO WLE SingleStep rc 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rmw u 0 rmw u 0 ECCErr ECC Error Detected Bit 0 no error 1 error detected ECCLeft vector selection for read write 0 select lower 8 bit 1 selects LEFT 4 bits ECCOff Bypass ECC WLO Selects all odd wordlines WLE Selects all even wordlines SingleStep Flash Single Step Mode CodeLCK C
10. ADCD 0 Preliminary Data Sheet 144 V0 9 2008 04 28 Cinfin eon PMA7110 Reference Table 96 SFR Address D5 ADCCH ADC Configuration Register high byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u n u n u ADCD 9 ADCD 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCD 9 Bit 9 ADCD 8 Bit 8 Table 97 SFR Address D2 ADCM ADC Mode Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCStart RV2 RV1 RVO WBCStart 52 CS1 CS0 rcw 0 0 rw 1 1 rw 1 1 rw 1 1 rcw 0 0 rw 1 1 rw 1 1 rw 1 1 ADCStart ADC conversion start RV2 Reference voltage select bit 2 RV1 Reference voltage select bit 1 RVO Reference voltage select bit 0 WBCStart BC start CS2 Analog channel select bit 2 CS1 Analog channel select bit 1 CSO Analog channel select bit 0 Table 98 SFR Address ADCOFF ADC Input Offset c network configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OFF5 OFF5 5 RVO WBCStart 52 CS1 CS0 r 0 0 r 0 0 rw 0 0 rw 1 1 rcw 0 0 rw 1 1 rw 1 1 rw 1 1 OFF5 Bit 5 extended OFF5 Bit 5 extended OFF5 Input of Offset c network Bit 5 OFF4 Input of Offset c network Bit 4 OFF3 Input of Offset c network Bit 3 OFF2 Input of Offset c network Bit 2 OFF1 Input of Offset c network Bit 1 OFFO Input of Offset c network Bit 0
11. Functional Description FR Abbr Addr Register description POWER SUPPLY Description VDDD VDDC Note Page DBCLO 0x94 CPU Debug Compare Register 0 low n Page 152 DBCHO 0x95 CPU Debug Compare Register 0 high n Page 152 DBTLO 0x96 CPU Debug Target Register 0 low n Page 152 DBTHO 0x97 CPU Debug Target Register 0 high n Page 152 DBCL1 0 9 CPU Debug Compare Register 1 low n Page 152 DBCH1 0x9D CPU Debug Compare Register 1 high n Page 152 DBTL1 0 9 CPU Debug Target Register 1 low n Page 153 DBTH1 0 9 CPU Debug Target Register 1 high n Page 153 DIVIC 0xB9 Internal Clock Divider n Page 71 DPL 0x82 Data Pointer low n Page 57 DPH 0x83 Data Pointer high n Page 57 DSR 0 09 Diagnosis and Status Register n Page 60 ExtWUF OxF1 Wakeup Flag Register 2 n Page 65 ExtWUM OxF2 Wakeup Mask Register 2 n Page 65 FCSP 0 9 Flash Control Register Sector Protection Control n Page 146 FCS OxEA Flash Control Register Status Mode n Page 147 FCPPO 0 1 Flash Charge Pumps Power Control Register 0 n Page 147 FCPP1 0 2 Flash Charge Pumps Power Control Register 1 n Page 147 FCSERM 0 Flash Sector Erase and Read Margin Select Register n Page 148 FCTKAS 0 4 Flash Tkill and Analog Output Select Register n Page 153 55 0 5 Flash Control Register for Single Step Mode n Page 154 I2CB 0xB1 I2C Baudrat
12. Preliminary Data Sheet 9 V0 9 2008 04 28 Cinfineon em Product Description 1 2 Features Supply voltage range from 1 9 V up to 3 6 V Operating temperature range 40 to 85 C Low supply current Temperature sensor Battery voltage measurement Integrated RF transmitter for ISM band 315 434 868 915 MHz Selectable transmit power 5 8 10 dBm into 50 Ohm load Transmit data rates up to 32kbit s or 64kchips s in manchester code FSK ASK modulation capability Frequency deviation up to 100 kHz in FSK mode Fully integrated VCO and PLL synthesizer Crystal oscillator tuning on chip LFreceiver with input signal amplitude of min 0 25 mVpp LFreceiver data rate from 2000 bit up to 4000 bit Manchester BiPhase coded 8051 instruction set compatible microcontroller cycle optimized 6 kbyte Flash Code and 2x128 bytes flash data memory for user application like EEPROM emulation 12 kbyte ROM for ROM library functions 256 bytes RAM 128 bytes configurable to keep content in Power Down mode 16 bytes XData memory supplied in PowerDown 2 bus interface SPI bus interface e 10 free programmable bidirectional GPIO pins with on chip pull up down resistors 4independent 16 bit timers 10bit ADC with pair differential channels e g as IO for external sensors Wakeup from POWER DOWN state using the Interval Timer the LF receiver external wakeup sources connected via a GP
13. Preliminary Data Sheet 18 V0 9 2008 04 28 Cinfineon 5 Functional Description Pin PAD name Equivalent I O Schematic Function No 12 PP1 GPIO port WUO I2C SDA WUO OPMode2 2 2 SDA I Putdown i OPMode2 Tristate 50k 77 GND VBat E VBat BBI PPO1 ml H E I 2cen pt 500 GND n PP 13 2 SCL GPIO port OPMode1 2 SCL OPMode1 Ru Tristate 50k GND VBat D VBat T F p 7 dams 3 os MAC 8 Im 2cen 500 L GND 5 PPio Preliminary Data Sheet 19 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Pin No PAD name Equivalent I O Schematic Function 14 PP3 SPI_CS IWU2 VBat Tristate 250 GND rv Pulldown Pros Core DMUX2 Pros em DMUX3 tmd2 wucdet imd2 imd2 bitbounddet imd2 decerr GPIO port WU2 SPI CS 15 PP4 wu3 SPI_MISO VBat Pullup Pulldown Tristate lt 54 GND VBat VBat na H lt 3 PPO4 s Data Data Brem Tristate gum SP
14. Q1 Measurement Terror 3 3 20 70 C error Voat 2 1 3 6V Q2 Measurement 5 5 C T 40 85 C error Voat 2 1 3 6V Table 77 Battery Sensor Characteristics Parameter Symbol Limit Values Unit Test Conditions Remarks min typ max P1 Measurement Verror 100 100 mV error Table 78 Supply Currents Parameter Symbol Limit Values Unit Test Conditions Remarks min typ max C1a Supply Current lesksabm 89 9 mA 5 8 104 Vga 3V RF Transmission lrsksabm 11 12 mA 40 FSK modulation lt 12 15 mA DIVIC 0x03 f 315MHz C1b Supply Current lesksdbm 92 0 5 mA Pout 5 8 10dBm V amp 4 73V RF Transmission lrsksabm 11 5 12 mA 40 FSK modulation leski0dbm 12 9 15 mA DIVIC 0x03 f 434MHz C2a Supply Current lesksabm 9 7 10 mA gPout 5 8 10dBm Vga 3V RF Transmission 12 22 14 mA T 25 C FSK modulation lt 12 8 18 mA SFRDIVIC 0x03 f 315MHz Preliminary Data Sheet 128 V0 9 2008 04 28 Cinfineon Reference Parameter Symbol Limit Values Unit Test Conditions Remarks min typ max C2b Supply Current 99 10 mA 5 8 104 Vg 3V RF Transmission lrsksabm 12 3 14 mA 25 FSK modulation lt 13 8 18 mA 0x03 f 434MHz C3a Supply Current tbd mA 5 8 104 Vg
15. d mm seien rs soo GPIO port WU3 MISO 16 PP5 SPI MOSI VBat Pullup Pulldown Tristate GND lt 55 PPOS ie PPD5 I m 5 mm sPIEn gt EH Pris GPIO port SPI MOSI Preliminary Data Sheet 20 V0 9 2008 04 28 Cinfineon 5 Functional Description Pin PAD name Equivalent I O Schematic Function No 17 PP6 WUA GPIO port SPI_Clk WU4 SPI DMUXS 18 xReset Reset input VBat 50k 500 xReset Wt WP Reset 19 PP7 WUS5 GPIO port Ext Int1 veg WU5 cam pes Ext Int1 Tristate PPO7 aE GND DMUXA o Hm _ _ Len DMUX6 per T lt tmd4_chipvalid e 1 state i ri deg Preliminary Data Sheet 21 V0 9 2008 04 28 Cinfineon 5 Functional Description Pin PAD name Equivalent Schematic Function No 20 PP8 WU6 s WUG won Io H DL 2 Cae HiRG Clock H RE tmd6 tr so PP8 flash digo 21 PP9 WU7 GPIO port Ext IntO ven WU7 Tr uer Ext IntO
16. 88 TCON 89 TMOD 8 TLO 8B TL1 8c THO 8D TH1 8E RFD 8F IRQFR 80 PO 81 SP 82 DPL 83 DPH 84 MMRO 85 MMR1 86 MMR2 87 PCON reserved The following tabe shows which SFRs keep their content in POWER DOWN state and THERMAL SHUTDOWN state and gives a reference to the page within this document where a detailed description can be found Table 8 Status of SFR Registers in POWER DOWN state ISFR Abbr Register description Description VDDC Note Page 0 0 Accumulator n Page 57 ADCCO 0xDB ADC Configuration Register 0 n Page 144 ADCC1 OxDC Configuration Register 1 n Page 144 ADCDL 0 4 Result Register low byte n Page 151 ADCDH 0xD5 Result Register high byte n Page 151 ADCM 0xD2 Mode Register n Page 145 ADCOFF OxDA ADC Input Offset c network configuration n Page 145 ADCS 0xD3 ADC Status Register n Page 146 ADWBC 0xDD AD WBC Wire Bond Check n Page 146 B OxFO Register B n Page 57 OxF8 Configuration Register 0 n Page 58 CFG1 0 8 Configuration Register 1 n Page 59 2 0xD8 Configuration Register 2 n Page 60 OxA9 CRC Control Register n Page 87 CRCD OxAA CRC Data Register n Page 151 0 OxAC CRC Shift Register low byte n Page 151 ICRC1 OxAD CRC Shift Register high byte n Page 152 Preliminary Data Sheet 53 V0 9 2008 04 28 Infineon 5
17. Figure 39 I C Commands Legend Preliminary Data Sheet 122 not acknowledge acknowledge V0 9 2008 04 28 Cinfineon em Functional Description 2 5 18 DEBUG mode Operation 2 5 18 1 Debug Special Function Registers Table 73 DEBUG mode SFRs alue DBCLO rw 004 004 Debug Compare Register O low DBCHO 95n rw 004 004 Debug Compare Register 0 high DBTLO rw 004 004 Debug Target Register 0 low DBTHO 7 rw 004 004 Debug Target Register 0 high DBCL1 Cu rw 004 004 Debug Compare Register 1 low DBCH1 OD rw 004 004 Debug Compare Register 1 high DBTL1 rw 004 001 Debug Target Register 1 low DBTH1 rw 004 004 Debug Target Register 1 high 2 5 18 2 Debugging Facility During program execution the Program Counter PC of the microcontroller is continuously compared with the contents of the DBCHx DBCLx registers The DBCHx DBCLx registers can be set to addresses in the FLASH or the ROM code area In case of a match the PC is automatically set to the address given in DBTHx DBTLx and program execution is continued The x in the upper content is O or 1 ROM Debug Function The debug function mainly consists of a debug handler and a single stepper The debug handler processes the 12 communication and debug command interpretation The debug commands SetSFR ReadSFR SetData ReadData and SetPC ReadPC are executed directly by the debug handler The d
18. Frequency Synthesizer VCO Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCOCC3 VCOCC2 VCOCC1 VCOCCO NCOF3 2 VCOF1 NCOFO rw u 1 rw u 0 rw u 0 rw u 1 rw u 0 rw u 0 rw u 0 rw u 0 Bit 7 Bit VCOCC3 Core Current Select bit 3 bit 0 0 COCCO Bit 6 COCC2 CO Core Current Select bit 2 Bit 5 COCC1 CO Core Current Select bit 1 Bit 4 COCCO CO Core Current Select bit 0 Bit 3 COF3 Tuning Curve Select bit 3 bit 0 Bit 2 COF2 CO Tuning Curve Select bit 2 Bit 1 COF1 CO Tuning Curve Select bit 1 Bit 0 COFO CO Tuning Curve Select bit 0 Table 138 SFR Address DF RFFSLD RF Frequency Synthesizer Lock Detector Configuration Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 n u NOLOCK ENLOCKDET LL3 LL2 LL1 LLO 0 0 0 0 0 0 jw 0 w 1 jw 0 0 jw 0 Bit 5 NOLOCK PLL Lock Indicator Bit 4 ENLOCKDET Enable Lock Detector Bit 3 LL3 LLO Lock Limit Select bit 3 bit 0 Bit 0 Table 139 SFR Address TMAX TMAX Detector Control Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PD TMAX nm u TMTR5 TMTR4 TMTR3 TMTR2 TMTR1 TMTRO rw u 1 0 0 rw u 0 rw u 0 rw u 0 rw u 0 rw u 0 rw u 0 Bit 7 PD TMAX Power down TMAX Detector in RUN state if set Please note TMAX Detector is always active in THERMAL SHUTDOWN state Bit 5 Bit0 TMTR5 Detector Shut Down Trigger Release Tempr Trimming TMTRO LSB 1 C nonlinear charcteristic 000000b min temp threshold 90 C 111111b max te
19. PP3 lalso used for SSDI lt 4 gt and DMux lt 3 gt and LongEval PP2 lalso used for SSDI lt 3 gt and DMux lt 2 gt PP1 lalso used for SSDI lt 2 gt and DMux lt 1 gt VPPO lalso used for SSDI lt 1 gt and DMux lt 0 gt VPPen falso used for SSDI 0 Table 104 SFR Address E2 FCPP1 Flash Charge Pumps Power Control Register 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VReadHi IBiasHi MProgPBit4 MProgPBit2 VProgPEn rw 0 0 rw 0 0 0 0 rw0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 ReadHi increases CG voltage from 1 8 V to 2 5 V during read IBiasHi increases bias currents by 66 from 5 uA to 8 33 uA ProgPBit4 ProgPBit3 ProgPBit2 also used for SSDI lt 11 gt Preliminary Data Sheet 147 V0 9 2008 04 28 Cinfineon Reference ProgPBit1 also used for SSDI lt 10 gt ProgPBitO also used for SSDI lt 9 gt ProgPEn also used for SSDI 8 Table 105 SFR Address E3 FCSERM Flash Sector Erase and Read Margin Select Registerl Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UseVEXT REFCURMAG1 REFCURMAGO ERSELREF ERSELCONF ERSELS2 ERSELS1 ERSELSO rw 0 0 rw 0 0 rw 1 1 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 UseVEXT uses voltage at VEXT to increase VProgP current REFCUR Reference current magnitude bit 1 MAG1 REFCUR Reference current magnitude bit 0 MAGO ERSELR Select
20. SFR Address 8 IE Interrupt Enable Register on Page 76 and Table 31 SFR Address 8 IP Interrupt Priority Register on Page 77 2 5 16 Serial Peripheral Interface SPI The PMA7110 supports a 2 3 or 4 wires bus protocol High speed synchronous data transfer up to 1 125 Mbit 18 MHz clock Four programmable bit rates through prescaler 2 wire bus for half duplex transmission a serial clock line SPI and concatenated data line SPI MISO SPI MOSI e 3 wire bus for full duplex transmission a serial clock line SPI and two serial data lines SPI MISO SPI MOSI A 4 wire bus for full duplex transmission plus handshaking can be implemented by utilizing also the Chip Select SPI CS This pin can be used for indicating the beginning of a new byte sequence Master or Slave Operation Preliminary Data Sheet 114 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Clock Control Polarity idle low high and Phase sample data with rising falling clock edge are programmable Bit Width 1 to 8 bits and Bit Order MSB or LSB first are configurable Compatible to SSC High Speed Synchronous Serial Interface and standard SPI interfaces Protocol is defined by software The Serial Peripherial Interface also known as SPI is a very simple synchronous interface to transfer data on a serial bus connecting an intelligent master controller with general purpose slave circuits like slave control
21. The encoding selection can be changed everytime before data byte is written to the SFR RFD by adjusting SFR bits RFENC 2 0 RFMode2 0 The SFR bit RFENC 3 TXDD defines the data value assigned to Manchester BiPhase encoder output when no data is available in the SFR RFD Note If SFR bit RFC 1 O ENFSYN EnPA is set the SFR bit RFENC 3 TXDD controls directly the transmitter state By using this feature the user has full control of the transmit data without any restrictions in timing or protocol Table 35 SFR Address E7 RFENC RF Encoder Tx Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RFDLen2 IRFDLen1 RFDLen0 RFMASK TXDD RFMode2 RFMode1 0 rw 1 1 rw 1 4 rw 1 1 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 RFDLen2 0 RF Data Length Number of bits to be transmitted from SFR RFD TXDD Transmit data if SFR bit RFC 1 0 ENFSYN is set RFMASK RF Interrupt Mask Flag RFMode2 0 RF Encoder Mode 000b Manchester 0 is encoded as Low to High 1 High to Low transition 0016 Inverted Manchester 0 is encoded as High to Low 1 as Low to High transition 0106 Differential Manchester 0 is encoded as transition 011b BiPhase 0 is encoded transition 100b BiPhase 1 is encoded transition 101b Data bits are interpreted as chips 110b reserved 111b reserved By writing a databyte to the SFR RFD the data transmission is invoked automa
22. The wakeup source except the Watchdog is available during the whole RUN state If an additional Wakeup event occurs during Run State the appropriate flag will be set but the device won t be forced through Init state It won t be cleared until POWER DOWN state is entered again Preliminary Data Sheet 63 V0 9 2008 04 28 Cinfineon 5 Functional Description Table 16 SFR Address C1 WUM Wakeup Mask RegisterM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MWDOG MTMAX MLFCD MLFSY MLFPM1 MLFPMO MITIM rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 MWDOG Mask Watchdog Wakeup Watchdog Wakeup is not maskable in NORMAL mode This bit is only used for internal production test mode Debug and Prog mode don t care for application MTMAX Mask TMAX Wakeup MAX Wakeup is not maskable in NORMAL mode This bit is only used for internal production test mode Debug and Prog mode don t care for application MLFCD Mask LF receiver Carrier detect 0 no Mask enable wakeup source 1 Mask disable wakeup source MLFSY Mask LF receiver Sync match 0 no Mask enable wakeup source 1 Mask disable wakeup source MLFPM1 Mask LF receiver Pattern 1 match 0 no Mask enable wakeup source 1 Mask disable wakeup source MLFPMO Mask LF receiver Pattern 0 match 0 no Mask enable wakeup source 1 Mask disable wakeup source Mask Interval Timer Wakeup Interval Tim
23. This bit is only used for PROGRAMMING mode 0 No write access to FLASH program memory 1 Write access to FLASH program memory is allowed Note This bit is under control of ROM library functions Don t care for application 2 Enable 1 PC behavior on PINs PP1 SCL and PP2 SDA is enabled 0 Keeps standard functionality RfTXPEn Transmitter Data Port Out Enable 1 The transmission data is strobed on port PP2 TXData 0 GPIO port functionality is provided ADWBEn Conversion ENable his is under control of ROM library functions Don t change this bit by the application manually ITInit Interval Timer Initialization active This bit is 1 as long as the Interval Timer is configured with the content of the ITPR register This bit is automatically cleared after initialization completes ITEn Intervaltimer ENable Test Debug Progmode only Preliminary Data Sheet 59 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Table 13 SFR Address D8 CFG2 Configuration Register 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EnHFBYP PDLMB PDADC n u WDRES RESET rw 0 0 r 0 0 r 0 0 rw u 1 rw 1 1 r 0 0 jew 0 0 ew 0 0 EnHFBYP Enable RF Vreg HF bypass PDLMB Power down RAM lower Memory Block 004 7F 1 the lower 128 byte RAM is powered down in POWER DOWN state or THERMAL SHUTDOWN state 0 the lower memory block is always powered PDADC
24. automatically cleared after a resume event The resume event source is available in SFR REF The Idle State will be left in case an interrupt event occurrs After completion of the Interrupt service the Idle State will be re entered in case no resume event is pending Table 20 SFR Address D1 REF Resume Event Flag Register Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 REXTG n u READC RELFO RERFU RERFF RERC RET2 rc 0 0 0 0 rc 0 0 0 0 0 0 0 0 0 0 0 0 REXTG Systemclock changed to crystal PMA7110 be put into IDLE state during crystal startup After expiring of the crystal delay time the REXTG Flag is set see also SFR XTCFG 2 0 Bit XTDLY 2 0 in Table 26 SFR Address 2 XTCFG Crystal Config Register on Page 72 READC conversion complete this bit is under control of ROM Library functions RELFO LF receiver buffer full RERFU RF transmit buffer empty RERFF RF transmission finished RERC 2 kHz RC LP Oscillator calibration complete RET2 Timer 2 underflow Preliminary Data Sheet 67 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 6 2 Interval Timer Interval Timer 2kHz RC LP Oscillator Precounter Postcounter Interval Wakeup uncalibrated gt ITFSH 11 8 gt gt ITFSL 7 0 ITPR 7 0 Figure 12 Interval Timer Block Diagram Th
25. era Figure 33 FLASH Write Line Command AdrHi MSB of the FLASH address to write to AdrLo LSB of the FLASH address to write to has to be multiple of 20 1 Data0 Data31 This data is written into the FLASH memory starting at the specified address Data0 is written at the lowest specified address CRCH MSB of the CRC sum CRCL LSB of the CRC sum 2 5 17 2 FLASH Erase The FLASH Erase command erases 1 to 5 sectors of the FLASH Note After the Stop condition P is received the selected FLASH sectors are being erased During the erase time incoming I C commands are not acknowledged SJ oxec A oxA2 A Sect ATCRCH ATCRCL Figure 34 FLASH Erase Command Table 69 Parameter Sect Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u Sector4 3 Sector2 Sector1 0 Sector4 protected area don t care Sector3 protected area don t care Sector2 protected area don t care Preliminary Data Sheet 118 V0 9 2008 04 28 Cinfineon Functional Description Sector1 1 erase User Data Sector 0 don t erase User Data Sector SectorO 1 erase Code sector 0 don t erase Code sector CRCH MSB of the CRC sum CRCL LSB of the CRC sum Preliminary Data Sheet 119 V0 9 2008 04 28 Infineon 5 Functional Description 2 5 17 3 FLASH Check Erase Status This function returns the status of the selected FLA
26. internal SPI External wakeup source pullup pulldown switchable Preliminary Data Sheet 12 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Table 1 Pin Description Pin Name Type Description Comments 18 xReset Digital External reset low active 19 PP7 WU5 Digital GPIO External wakeup source internal Ext Int1 pullup pulldown Switchable 20 PP8 WU6 Digital GPIO External wakeup source internal pullup pulldown switchable 21 PP9 WU7 Digital GPIO External wakeup source internal Ext Int1 External Interrupt source pullup pulldown Switchable 22 MSE Digital Mode select enable high active set to GND in normal mode 23 TME Digital Test mode enable high active set to GND in normal mode 24 XTALCAP Analog Crystal oscillator load capacitance 25 XTAL SCLK Analog Crystal oscillator input External reference clock 26 XGND Supply Crystal oscillator ground 27 AMUX1 Analog additional differential ADC standard connect to GND if not input1 for external sensor use 28 AMUX2 Analog additional differential ADC standard connect to GND if not input2 for external sensor use 29 XLF Analog Differential LF receiver Input2 30 LF Analog Differential LF receiver Input1 31 VReg Supply Internal voltage regulator output connect to decoupling capacitor Czcap 100nF 32 VDDD Supply Digital supply 33 VDDA Supply Analog supply 34 GNDC Supply Ground 35 RD sens Analog
27. 0 0 0 rw 0 0 PDWN POWER DOWN state If set to 1 by software the POWER DOWN state is entered This bit is automatically reset to 0 by the system controller after wakeup Note Entering POWER DOWN state is handled by a ROM Library function It is recommended to set this bit manually TSHDWN THERMAL SHUTDOWN state If set to 1 by software the THERMAL SHUTDOWN state is entered This bit is automatically reset to 0 by the system controller after wakeup Note Entering THERMAL SHUTDOWN state is handled by ROM Library function It is not recommended to set this bit manually IDLE IDLE state If set to 1 by software the IDLE state is entered This bit is automatically reset to 0 by the system controller after a resume event occurred FTM only used for internal production test mode don t care for application CLKSelO Systemclock Source Select 1 Select crystal oscillator clock 0 Select 12MHz RC HF Oscillator Note Changing the systemclock is handled by a ROM Library function It is not ecommended to set this bit manually Preliminary Data Sheet 58 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Table 12 SFR Address E8 CFG1 Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PMWEn I2CEn ADWBEn ITInit ITEn rw 0 0 rw 0 0 r 0 0 rw u 0 rw 0 0 rw 0 0 r 0 0 r u 1 PMWEn Program Memory Write Enable
28. 2 75 Iregpp 40uA 7 M4 voltage in POWER DOWN THERMAL SHUT DOWN 1 The voltage regulator is designed to supply only the internal blocks of the PMA7110 and not designed to drive any external 100nF decoupling cap is recommended for proper operation thus only the decoupling cap may be connected to the pin Table 87 VMIN detector Parameter Symbol Limit Values Unit Test Conditions min typ max Remarks N1 Low battery threshold THea 20 21 2 2 used by warning level ROM Library functions only Preliminary Data Sheet 139 V0 9 2008 04 28 Cinfineon Reference Table 88 6k FLASH Code memory data H Parameter Symbol Limit Values Unit Test Conditions min typ max Remarks O1 Temperature 0 0 35 Erase program 2 Erase Program 23 0 5 Supply voltage ga 2 5 range regulated Qpad VDDD Qpad VBat Endurance 400k 1 cycles programming erase cycles sector or P 40 yrs O4 Erase time 102 ms RC HF Oscillator 912MHz O5 Write time line 2 2 ms RC HF Oscillator 12MHz Line 32byte 1 This is only valid for storage temperature from 40 C to 125 C for max 1000 hours Table 89 2 times 128 byte FLASH User Data memory Paramete
29. Description V Vreg THR POR RESET internal PPO PP1 t MODE Figure 5 Power On Reset operating mode selection During the time the levels of PPO PP1 and MSE are read and being determined the operation mode of the device according to Table 3 Operating mode selection after Reset on Page 30 The levels on these pins must be stable during the whole Period The PMA7110 s Power On Reset circuit is activated if Vreg rises above internal blocks are held in Reset state until Vreg has risen above When this Reset state is released a further time of tope is needed for reading the levels PP1 and MSE After has elapsed the device starts operation in the selected mode Note See Power On Reset on Page 138 for details on Power On Reset characteristics 2 3 2 State Description 2 3 2 1 INIT State This is a transient state which is entered when the settings of PP1 MSE TSE the Lockbyte lead to Normal Mode please refer to Table 3 Operating mode selection after Reset on Page 30 In this state the SFRs which are not located in the System controller get reset and the ROM routines initializes the system to its default Preliminary Data Sheet 32 V0 9 2008 04 28 Cinfineon em Functional Description values Then the application Program in Flash is started at 4000h and the device enters RUN state 2 3 2 2 RUN
30. MHz D2 Output power Psapm 5 6 dBm 25 transformed to 50 7 8 9 dBm Ohm Pio n P 10 11 dBm Low temp output 1 dB Vgat 3V 40 power change nominal output power D4 High temp output 71 5 dB 85 nominal output power D5 Supply voltage 5 5 dB Vgat 1 9V 25 ependent output nominal output power power change D6 Supply voltage OP vvs 1 8 dB Vgat 2 5V 25 ependent output nominal output power power change P548m D7 Supply voltage OPyavs 1 8 dB Vgat 3 6V T 25 C ependent output nominal output power power change D8 Data rate 32 kBps 64kChips s D9 Carrier to spurious 28 dBc FCC 15 231a e ratio incl harmonics RBW 100kHz D1 315 915MHz 2nd 10th harmonic D10 carrier to noise ratio 20 dBc FCC 15 231a e D1 315 915MHz RBW 100kHz measured at frequency dge 0 25 for 315MHz 0 596 fc for 915MHz c carrier frequency Preliminary Data Sheet 131 V0 9 2008 04 28 Cinfineon Reference D11 SSB Phase Noise RBW 100kHz 25 C D1 315MHz 95 tbd dBc Hz 10kHz offset 93 tbd dBc Hz 100kHz offset 97 tbd dBc Hz 250kHz offset 120 tbd dBc Hz 1MHz offset 136 tbd dBc Hz 10MHz offset D12 SSB Phase Noise RBW 100kHz 25 C QD 1 434MHz 93 tbd dBc Hz 10kHz offset 90 tbd dBc Hz 100kHz offset 91 tbd dBc Hz 250kHz offset 113 tbd dBc Hz 1
31. Power down ADC 1 no supply 0 ADC active ote This bit is handled by the ROM Library functions automatically It is not ecommended to change this bit manually Reset Watchdog counter to 0 RESET Reset System Software Reset Table 14 SFR Address D9 DSR Diagnosis and System Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCLK TMAX OpMODE1 OpMODEO FlashCP1 FlaschCPO WUP FlashLCK r 0 0 xix u x ulx 0 0 0 0 0 rmw u 0 SCLK Status Flag indicating the current systemclock 1 Crystal Oscillator clock 0 12 MHz RC HF Oscillator Detector Status Bit 1 Temperature lt TMAX 0 Temperature gt TMAX This bit should be polled by the application before entering THERMAL SHUTDOWN state Note Entering THERMAL SHUTDOWN state is handled by a IROM Library function It is not needed to evaluate this bit manually OpMODEO 1 These bits indicate the current operation mode 11b NORMAL mode 10b PROGRAMMING mode 1b DEBUG mode Ob internal productionTEST mode FLASHCP1 Only used for internal production test mode don t care for application FLASHCPO Only used for internal production test mode don t care for application WUP Wakeup pending FLASHLCK Flash Lock 0 full Flash SFR access 1 restricted write access It is set to 1 by SW if Config Magic Number is detected Self holding when 1 Preliminary Data Sh
32. SFR bit I2CC 6 GCEn has to be set Once the interface has been enabled the PMA7110 waits for a start condition to occur After the PMA7110 received a start condition the following received 7 bits are compared to the device address When the address matches the hardware automatically generates an acknowledge and sets SFR bit I2CS 7 AM and SFR bit I2CS 3 RnW Depending on SFR bit I2CS 3 RnW the following two different actions are executed Receive I C data If SFR bit I2CS O RBF is set one byte has been shifted to SFR I2CD An acknowledge is automatically set by hardware as long as no receive buffer overflow SFR bit I2CS 5 OV has occurred If SFR bit I2CS 4 S is set a stop condition has occurred the transmission is closed by the master device If SFR bit I2CS 7 AM is set a restart condition has been set and a matching address has been received in case of a write access a branch to the transmit data subroutine has to be performed Transmit I C data Data to be transmitted has to be written to SFR I2CD SFR bit I2CS 1 TBF is reset if data is taken over by the shift register and new data may be written to SFR I2CD If no data is provided the IC interface automatically sets line SCL to low until data is written to SFR I2CD slave device gains access over line SCL If SFR bit I2CS 4 S is set the transmission process has been terminated by the master and the transmission subroutine can be left Preliminary D
33. SFRITPR Timer Baudrate G t LF On Off Timer ee Precounter ONO SFR LFOOTP sr General Purpose Timer for Baudrate Calibration Figure 13 PMA7110 Clock Concept Preliminary Data Sheet 70 V0 9 2008 04 28 Cinfineon em Functional Description PMA7110 Internal Clock Divider For power saving it is possible to enable the internal clock divider to reduce the systemclock by a prescaled factor If SFR is set to 00 default the divider is disabled Table 24 SFR Address B9 Internal Clock Divider Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 n u n u n u n u n u DIVIC1 DIVICO 0 0 0 0 0 0 0 0 0 0 0 0 rw 0 rw 0 DIVIC1 0 Internal Clock Divider 11b Divide by 64 10b Divide by 16 016 Divide by 4 006 Divide by 1 2 5 7 1 2kHzRC LP Oscillator Low Power The 2 kHz RC LP Oscillator stays active even in POWER DOWN state The typical frequency of the oscillator is 2kHz 2 5 7 2 12 MHz RC HF Oscillator High Frequency The 12 MHz RC HF Oscillator runs at typ 12MHz It is used as the default clock source for the PMA7110 in RUN state and is calibrated in the Infineon production site 2 5 7 3 Crystal Oscillator The crystal oscillator is a Negative Impedance Converter NIC oscillator with a crystal operating in series resonance The nominal crystal operating frequencies are between 18MHz and 20M
34. content otherwise it can be used as battery buffered storage beyond a POWER DOWN period Note The RAM is not reset at a System Reset After a Brown Out Reset this feature can be used to possibly recover data from RAM After Power On Reset the RAM is not initialized thus it contains random data The application has to initialize the RAM if needed 2 5 2 4 Special Function Registers Special Function Registers are used to control and monitor the state of the PMA7110 and its peripherals The following table shows the naming convention for the SFR descriptions that are used throughout this document R C W 0 0 Value after Power On Reset Value after wakeup from POWER DOWN THERMAL SHUTDOWN state X unknown u unchanged 1 high 0 low Access Readable C Cleared after Read automatically cleared W Writeable Figure 10 Naming convention for Register descriptions Note If a single bit or the whole byte value is declared as unchanged it keeps its state even during POWER DOWN state or THERMAL SHUTDOWN state Table 7 SFR Special Function Register Address Overview on Page 53 shows all available registers of the PMA7110 Note All SFRs that are listed in Table 7 SFR Special Function Register Address Overview on 53 but not in Table 8 Status of SFR Registers Preliminary Data Sheet 51 V0 9 2008 04 28 Cinfineon Functional Description POWER DOWN state on Page 53 should not be chan
35. from the 12 MHz RC HF Oscillator to the crystal e g for RF Transmisssion is performed automatically by a ROM library function see 1 Reference Documents on Page 157 If the crystal is selected as systemclock the 12 MHz RC HF Oscillator is automatically powered down Note Since the external crystal needs some startup time a 3 bit delay timer is integrated to delay the clock switching Dependent on the used crystal the SFR bits XTCFG 2 0 XTDL Y2 0 can be set to delay from typ Ous up to 1750us in 250us steps see Table 26 SFR Address C2 XTCFG Crystal Config Register on Page 72 The following figure shows which clocks are used for which PMA7110 blocks Details about the individual blocks can be found in the appropriate chapters of this document LF Baudrate Generator SFR LFDIV Data Recovery Synconizer 12 MHz RC HF i Microcontroller z lt Oscillator SFR CFGO gt SFIEDIVIG Generator CIkS i 64 16 4 1 Checker co Crystal Oscillator 2 20 Peude andam 19 6875 MHz Number Generator 18 080 MHz 18 08958 MHz 19 0625 MHz RF Transmitter PLL VCO gt NO 2 kHz RC LP 8 Oscillator S SFR gt TMOD PP2 Event Interval Timer Precounter Postcounter 1 SFR ITFSL H
36. h H 500 L 4 i L H T H is i Preliminary Data Sheet 26 V0 9 2008 04 28 Cinfineon 5 Functional Description Pin PAD name Equivalent I O Schematic Function No 37 MM2 sens Channel 2 VDDA Negative Supply a 2 4 TI ba 38 2 sens Channel 2 VDDA Negative Signal oe H c VING ND 2 2 Preliminary Data Sheet 27 V0 9 2008 04 28 infineon Functional Description 2 2 Functional Block Diagram 12MHz RC 256 B 6 kB 12 General Purpose PP1 HF Oscillator RAM Flash ROM Input Output Diff high sensitive input1 GPIO 12 SPI PP2 WU PP9 VIN V RF transmitter Diff high sensitive input2
37. least one bit is set in the sector 0 sector is erased or untested Preliminary Data Sheet 120 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 17 4 FLASH Read Line The contents of the FLASH memory be read out via the I C interface If Lockbyte 2 is set reading of code sector will only yield but the Lockbyte 2 itself can still be read for validating the result S 60 A Adi ito ASRS O60 DabicRCR AICRCL AP Figure 36 FLASH Read Line Command AdrHi MSB of the address to start the read access AdrLo LSB of the read address Data0 Value that has been read from the specifed address Data31 Value that has been read from the specified address 31 CRCH MSB of the CRC sum CRCL LSB of the CRC sum 2 5 17 5 FLASH Set Lockbyte 2 Lockbyte 2 protect the Code sector After the Lockbyte 2 is set by the Keil programmer a startup in DEBUG mode or PROGRAMMING mode is not possible any more 2 5 17 6 FLASH Set Lockbyte 3 This command sets the Lockbyte 3 protecting the FLASH User Configuration Sector Sector 1 After the Lockbyte 3 is set a startup in DEBUG mode or PROGRAMMING mode is not possible any more see on Page 121 for details Note It is required to set Lockbyte 2 Code Sector to enable Lockbyte 3 to become effective SJ oss AT mata 924 ATP Figure 37 FLASH Set Lockbyte 3 Command Preliminary Data Sheet 121 V0 9 2008 04 28 Cinfin
38. n Page 73 XTCFG OxC2 XTAL Configuration Register n Page 72 Note Power Supply VDDC switched off during POWER DOWN state Register value will be lost Preliminary Data Sheet 56 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 3 Microcontroller Central part of the PMA7110 is an CPU8051 instruction set compatible microcontroller The CPU8051 offers an 8 bit datapath an interrupt controller several addressing modes direct register register indirect bit direct and accesses peripheral components using Special Function Registers SFR The architecture of the CPU8051 is well known and not part of this discription However some of the features are not needed or adapted to special product requirements These features are described herein in detail The CPU8051 incorporates basic core internal registers Accumulator ACC Register B B and Program Status Word PSW are bitaddressable registers used to perform arithmetical and logical operations Stack Pointer SP and Data Pointer DPL DPH are included to allow basic programming structures Table 9 8051 basic SFRs SFR Abbr Addr Access Default Value Register ACC EO rw 0400 Accumulator B FO rw 00400 Register B DPL 82 rw 0400 Data Pointer low DPH 83 rw 00 00 Data Pointer high PSW DO rw 00400 Program Status Word SP B1 rw 00 00 Stack Pointer SFR PSW holds the result of basic arithmetic
39. not explicity noted this applies also to Timer 1 2 5 13 1 Basic Timer Configuration Timer 0 Timer 3 comprise four fully programmable 16 bit timers which can be used for time measurements as well as generating time delays The clock source is selectable in order to enlarge the timer runtime SFR TMOD and SFR 2 are used to select the clock source and the desired timer mode Table 41 SFR Address 89 TMOD Timer Mode Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1Gate T1CIT 1 1 T1M0 TOGate TOC T TOM1 rw 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 T1Gate Timer 1 Gate Control bit gating input PP8 T1C T Timer 1 Counter not Timer count input PP9 T1M1 0 Timer 1 Mode 00b Mode 0 8 bit timer with a divided by 32 prescaler 1b Mode 1 16 bit timer 10b Mode 2 8 bit timer with 8 bit auto reload 11b Mode 3 Timer 1 hold its count The effect is the same like setting TR1 0 TOGate Timer 0 Gate Control bit gating input Preliminary Data Sheet 90 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Timer 0 Counter not Timer count input PP1 OM1 0 Timer 0 Mode 006 Mode 0 8 bit timer with a divided by 32 prescaler 016 Mode 1 16 bit timer 105 Mode 2 8 bit timer with 8 bit auto reload 116 Mode 3 Two 8 bit timers Table 42 SFR Address C9 TMOD2 Timer Mode Reg
40. operations Table 10 SFR Address 0 PSW Program Status Word Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CY FO RS1 RSO OV F1 P rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 0 0 CY Carry Bit set to 1 if accumulator changes signed number range through 0x00 0xFF unsigned range overflow AC Carry Bit carry out for BCD operations FO General Purpose Bit 0 may be freely used by the application RS1 Register Bank Select bit 1 RSO Register Bank Select bit 0 Overflow Bit set to 1 if accu changes signed number range through 0x80 0x7F with arithmetic operations signed range overflow F1 Gereral Purpose Bit 1 may be freely used by the application P reflects the number of 15 in the accumulator set to 1 if contains an odd number of 15 Preliminary Data Sheet 57 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description 2 5 4 System Configuration Registers The system configuration registers can be used for Initiating state transitions System software reset Enabling or disabling peripherals Monitoring the operation mode the system state and peripherals Table 11 SFR Address F8 Configuration Register 0 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 PDWN TSHDWN IDLE n u FTM n u n u ICLKSel0 rw 0 0 rw 0 0 rw 0 0 0 0 rw 0 0
41. purposes or are fixed assigned to one peripheral Alternative Port Functionality on Page 109 When used as GPIO pins they can be accessed directly by the processor Pullup and pulldown resistors are configurable on demand to allow wired AND and wired OR functions All peripheral port pins are configured as input with the pullup resistor which will be enabled after a Power On Reset Pin status will be kept during Powerdown 2 5 14 1 Peripheral Port Basic Configuration Table 46 Peripheral I O Port Registers alue P1DIR rwuu PPO 7 Data Direction Register P1IN s r 7 Data Input Register P1OUT 90 rw u FF PPO 7 Data OUT Register P1SENS 93 rw lu 00 7 Sensitivity Register P3DIR EB rw PP8 9 Data Direction Register P3IN EC r 8 9 Data Input Register P3OUT rw PP8 9 Data OUT Register P3SENS ED rw PP8 9 Sensitivity Register The following table shows the different possible configurations for the GPIO Port Table 47 GPIO Port Configuration PPDx pullup omment pulldown 0 0 Output LOW sink 0 1 H Output HIGH source 1 0 H Input no high Z Tri State Bidirectional 1 1 0 Input pullup Weak High Quasi Bidirectional 1 1 1 Input pulldown Weak Low Quasi Bidirectional Note In addition SFR bit PPSx defines the wakeup sensitivity for the external wakeup source see External Wakeup on PP1 P
42. to deactivate the request before the interrupt service routine is completed or else another interrupt will be generated Each of the External Interrupts has its own interrupt vector Timer Interrupts All four timers on the Dev NameShort1 can be used as interrupt sources While Timer 0 and Timer 1 are fully compatible to the original CPU8051 for a description please refer to Timer counter interrupts on Page 96 Timer2 and Timer interrupts are treated as Extended Interrupts FC Interface Interrupts The data interface transfer on the Module can be controlled via interrupts This module has a separte interrupt vector vector address 23 where the PC is automatically set whenever one of the interrupt flags active and unmasked In Test Debug and Programming Mode the 1 C interface handling is done by polling SPI Interface Interrupts The data transfer on the SPI Interface can be controlled via Interrups This module has a separte interrupt vector vector address 2B where the is automatically set whenever one of the interrupt flags is active and unmasked LF Receiver Interrupts Preliminary Data Sheet 75 V0 9 2008 04 28 Cinfineon em Functional Description While the main target for LF receiver operation is waking up the device itis also possible to receive data via the LF interface in Run Mode The Wake up flags are used as Interrupt event flags and Wake up mask bits are used as Interrupt Mask bi
43. 0 13 Bit Timer Counter 0 Y TL1 TH1 n le ED 4 5 Bits 8Bits TF1 T1Count PP9 xt _ T alo mem IE 7 EA mer CON6 TR1 TMOD7 T1Gate 1 p 8 IESSET1 21 T1Gate PP8 Timer01_Mode0 vsd Figure 22 Timer Counter 1 Mode 0 13 Bit Timer Counter Mode 1 Mode 1 is equal to Mode 0 with the difference that the timer register is running with all 16 bits Mode 2 Mode 2 configures the timer registers as an 8 bit counter in TLO resp TL1 with automatic reload as shown in Figure 23 Timer Counter 0 Mode 2 8 Bit Timer Counter with auto reload on Page 95 Overflow from TLO resp TL1 not only sets TCON 5 resp TCON 7 TF1 but also reloads TLO resp TL1 with the Preliminary Data Sheet 94 V0 9 2008 04 28 Cinfineon 5 Functional Description contents of THO resp 1 which is preset by software The reload leaves THO resp TH1 unchanged OSC 6 IE 7 EA IE 1 ETO ETO Interrupt Timer 0 0 TMOD TOCIT TOCount PP1 B TCON4 TRO TMOD3 TOGate 1 amp 01 Mode2 vsd TOGate PP0 Figure 23 Timer Counter 0 Mode 2 8 Bit Timer Counter with auto reload Mode 3 Mode 3 has different effects on Timer 0 and Timer 1 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TCON
44. 008 04 28 Cinfineon em Functional Description 2 5 1 2 Two differential high sensitive interfaces to external Sensors Differential high sensitive sensor interface 1 Channel 6 V1P V1N is the positve negative differential voltage inputs of the first sensor bridge Differential high sensitive sensor interface 2 Channel 7 V2P V2N is the positve negative differential voltage inputs of the second sensor bridge Channel gain selection The SFR Bit ADCC1 5 4 GAIN1 0 gain factor selection allows the selection of the sensitivity of the analog input channels 6 and 7 The gain is one for all other input channels see Table 6 Table 6 Selection of the gain factor amo m m gain ADCM CS2 0 76 20 11X 60 20 11X 50 20 11X 38 20 11X others others others ajajaja others Sensor Excitation The two sensor bridges have a common positive supply which is always connected When a sensor bridge is to be activated its negative supply is pulled to ground by pad VM1 or VM2 for VMP or VMA Otherwise it is disconnected In this way the power of a connected bridge can be supplied Preliminary Data Sheet 43 V0 9 2008 04 28 Cinfineon em Functional Description These two sensor interfaces are very adapted piezoresistive Wheatstone bridge sensors whose output signal is differential and ratiometric proportional to the bridge excitat
45. 11 1 2 1 3 2 24 2 2 2 3 2 31 2 3 2 2 3 2 1 2 3 2 2 2 3 2 3 2 3 2 4 23 35 2 3 2 6 2 3 2 7 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 22 2 5 1 2 5 1 1 2 5 1 2 2 5 1 3 2 5 1 4 2 5 1 5 2 5 1 6 2 5 2 2 5 2 1 2 5 2 2 2 5 2 3 2 5 2 4 2 5 3 2 5 4 2 33 2 5 6 2 5 6 1 2 5 6 2 Product Description 9 OVEIVIEW edo Se Sahl a oa aad 9 Features ere REDRE ERN ENE ERSEN ee sas 10 Applications bod dm dea Gass kos ee E I E eds 10 Functional Description 11 Pin Description 2 2 ends dane 11 Functional Block 28 Operating Modes and States 29 Operating mode selection 29 State Description desk 32 INIT State zie Rr ume Ime y Stes 32 RUN diced pellere 33 IDLE State sinuta tnih 33 POWER DOWN State 2425 34 THERMAL SHUTDOWN state 34 State Transitions 4 av equo e bebe 35 Status of PMA7110 Blocks in Different States 37 Fault protection
46. 2 SP 1 5 0 0 0 0 0 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 1 1 SP 7 SP 0 IStackpointer Bit 7 Bit 0 Table 110 SFR Address 8C THO Timer 0 Register High Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Bit 7 Bit 0 Bit 7 Bit 0 Table 111 SFR Address 8D TH1 Timer 1Register High Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 0 rw0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Bit 7 Bit 0 Bit 7 Bit 0 Preliminary Data Sheet 149 V0 9 2008 04 28 0 Cinfineon eae Reference Table 112 SFR Address TH2 Timer 2 Register High Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Bit 7 Bit 0 Bit 7 Bit 0 Table 113 SFR Address TH3 Timer 3Register High Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 0 rw0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Bit 7 Bit 0 Bit 7 Bit 0 Table 114 SFR Address 8A TLO Timer 0 Register Low Byte Bit 7 Bit 6 Bit 5 B
47. 3 Data Out Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u P3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 rw u 1 rw u 1 P3 1 PP9 Data Out PullUp enable P3 0 PP8 Data Out PullUp enable Preliminary Data Sheet 106 V0 9 2008 04 28 Infineon 5 Functional Description Table 52 SFR Address 93 P1SENS IO Port1 Sensitivity Register PS1 x I O Port sensitivity 16 Pulldown is enabled if SFR P1DIR x 1 and P1OUT x Ob Pullup is enable if SFR P1DIR x 1 and P1OUT x The x in the table has to be replaced by either of 0 until 7 Table 53 SFR Address ED P3SENS IO Port3 Sensitivity Register PS3 1 PP9 I O Port sensitivity 1b Pulldown b Pullup PS3 0 8 sensitivity 1b Pulldown b Pullup Table 54 SFR Address 92 P1IN IO Port1 Data In Register Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 7 1 6 5 PH 4 3 2 1 0 xix Ir xix x x Ir x x r PI1 7 2 PP7 PP2 data In Testmode DMUX7 DMUX2 in 1 PI1 0 PP 1 PPO data In Table 55 SFR Address EC P3IN IO Port3 Data In Register Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u 1 0 0 0 0 0 0 0 0 0 0 0 0 0 r xix r 1 PP9 data In 0
48. 3 and the timer is restarted automatically SFR bit TCON2 1 TOFull has to be reset by software It is not cleared on read access Note In this mode both SFR bit TCON2 4 T1Run and SFR bit TCON2 5 T1Full are not used IE 7 EA TL2 TH2 IE 6 EID amp gt Interrupt T2Mask Timer 2 1 T2Run Timer 2 T2Full Reload T3Run Timer 2 Reload T3Full 0 TL3 TH3 Figure 25 Timer mode 0 Preliminary Data Sheet 97 V0 9 2008 04 28 Cinfineon em Functional Description Timer mode 1 Comprises e 16 bit timer without reload 8 bit timer with reload and bitrate strobe signal for RF Transmitter Timer 2 operates as 16 bit timer with start value in SFR TL2 and SFR TH2 timer run bit SFR bit TCON2 0 TORun and timer elapses indicator SFR bit TCON2 1 TOFull If the timer elapses it stops sets SFR bit TCON2 1 TOFull and resets the timer run bit SFR bit TCON2 0 TORun Timer 3 sets up a reloadable 8 bit timer holding the startup value in SFR TL3 timer reload value in SFR TH3 timer run bit in SFR bit TCON2 4 T1Run and timer elapses indicator in SFR bit TCON2 5 T1Full IE 7 EA Interrupt amp Timer 2 T2 TH2 IE 6 EID Jl Jl i T2Mask T2Run 4 Timer 2 gt T2Full T3Run Timer 3 Timer 3 Reload T3Full IE 7 EA EA amp Interrupt TL3 TH3 IE 6 EID Timer 3 Baudrate strobe gt
49. 3V RF Transmission lrsksabm mA 85 FSK modulation tbd mA DIVIC 0x03 f 315MHz C3b Supply Current tbd mA Pout 5 8 10dBm Vgai 3V RF Transmission lrsksabm mA 85 FSK modulation tbd mA DIVIC 0x03 f 434MHz C4a Supply Current 11 3 mA 5 8 104 RF Transmission 12 8 mA 40 FSK modulation llesxioanm 16 8 mA DIVIC 0x03 f 868MHz C4b Supply Current 11 3 mA Pout 5 8 10dBm Vg 3V RF Transmission 13 4 mA 40 C FSK modulation 16 7 mA DIVIC 0x03 f 915MHz Supply Current lisa 118 14 mA Pout 5 8 10dBm RF Transmission 12 9 18 mA 25 FSK modulation 169 24 mA DIVIC 0x03 f 868MHz C4d Supply Current 12 6 14 mA QPout 5 8 10dBm Vg RF Transmission 15 3 18 mA 25 FSK modulation llesxioanm 17 1 24 mA DIVIC 0x03 f 915MHz C4e Supply Current tbd mA Pout 5 8 10dBm Vga 3V RF Transmission lt tbd MA 85 FSK modulation tbd mA DIVIC 0x03 f 868MHz Supply Current tbd mA 5 8 104 Vba RF Transmission mA T 85 C FSK modulation lesxioanm tbd mA DIVIC 0x03 f 915MHz Note Matching circuit as used in the 50 Ohm Output
50. 6 TR1 0 Timer 0 establishes TLO and THO as two separate counters Figure 24 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters on Page 96 TLO uses the Timer 0 control bits TMOD 2 TOC T TMOD 3 TOGate TCON 4 TRO TCON 5 TFO and the pin status of PPO THO is locked into a timer function counting machine cycles and takes over the use of TCON 6 TR1 and TCON 7 TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or in fact in any application not requiring an interrupt from Timer 1 itself Preliminary Data Sheet 95 V0 9 2008 04 28 Cinfineon em Functional Description IE 7 EA TCON 6 TR1 IE 3 ET1 Interrupt amp gt _ el Timer 1 THO ITCON 7 1 ose 6 8 Bits TF1 L 0 TLO 5 TMOD 2 T0C T Interrupt TOCount PP1 B amp IE 7 EA Timer 0 TCON4 TRO TMOD3 TOGate 1 pO amp MEET 21 Timer01_Mode3 vsd TOGate PP0 DX Figure 24 Timer Counter 0 Mode 3 Two 8 Bit Timers Counters Interrupt support This module supports interrupt generati
51. 8 04 28 Cinfineon Functional Description 2 5 10 LF Receiver The LF receiver is used for data transmission to the PMA7110 as well as for waking up the PMA7110 from POWER DOWN state It can generate wakeup directly by the carrier detector if the carrier amplitude is above a preset threshold or it can decode the received data and not wake up the microcontoller until predefined sync match pattern or wakeup pattern is detected in the data stream Data recovery using synchronizer and decoder is available for Manchester and BiPhase coded data The synchronizer can also handle Manchester BiPhase code violations Any other coding scheme can be handled by the microcontroller on chip level thus no limitations on data coding schemes apply A LF On Off Timer is implemented to generate periodical On Off switching of the LF receiver in POWER DOWN state This can be done to reduce the current consumption Preliminary Data Sheet 85 V0 9 2008 04 28 Cinfineon Functional Description 2 5 11 16Bit CRC Cyclic Redundancy Check Generator Checker CRC CCITT Polynomial 0x1021 CRC Shiftregister Logic SFR CRCC SFR CRCR1 CRC Result 15 8 MSB SFR CRCRO SFRCRCD CRC Data 8 bit Y SFR CRCS CRCValid CRC Result lt 7 0 gt Figure 19 CRC Cyclic Redundancy Check Generator Checker CRC is a powerful method to detect errors in datapackets that have been transmitted over a distorted con
52. CDFLT tbd E2 LF Baseband 120 mV signal level required to Sensitivity achieve a BER better than Gain setting 2 0 1 100 square modulation Datarate 4000 Bit s SFR LFRXO tbd SFR LFCDM tbd SFR LFCDFLT tbd Datarate 2000 4000 Bit s E4 Datarate error 2 E5 Carrier frequency 120 125 130 kHz E6 LF Current lir 2 3 0V T 25 C LF consumption Input signal smaller than Carrier Detection level 12 MHz RC HF Osc and LF Baseband OFF lir tbd 3 0V T 25 C LF Input signal higher than Carrier Detection level or enabled by SFR Bit LFCDFLT CDFM1 0 11b 12 MHz RC HF Osc and LF Baseband ON E7 dynamic 70 dB Sensitivity Gain setting 1 range 1 enabled E9 AGC attack time 200 900 us Qcontinous wave signal Preliminary Data Sheet 133 V0 9 2008 04 28 Cinfineon Reference H Parameter Symbol Limit Values Unit Test Conditions min typ max Remarks E10 decay slew TAccpec B5 M s SFR bit LFRX0 7 6 AGCTCD1 rate 0 00b 70 V s SFR bit LFRX0 7 6 AGCTCD1 0 01b 140 M s bit LFRX0 7 6 AGCTCD1 10b E11 Settling time ser 4 ms power on settling time of internal nodes x 2 kHz RC Oscillator cycles Min Max Tolerances from Table 83 apply E12 capacitance tb d 0 t b d pF E13 Dif
53. Characteristics on Page 128 for the sensor specification Preliminary Data Sheet 46 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 2 Memory Organization and Special Function Registers SFR Nonvolatile Code Data memory memory Not implemented DEF RAM 0x5900 256 0x80 Reference cells OxS8FF Ox7F Lockbyte 1 0 58 0 byte Optional battery buffered Flash Configuration ID 09935 Data RAM 000 128B 0x587F Indirect Direct User Data Sector II 0x5800 ddressi ddressi FLASH lt ETER addressing addressing 6kB 128B User Data Sector 0 5780 CRC Sum Lockbyte 2 0x577F Xdata 6016B 0x4033 memory Vectors 0x4000 RAM OxOF Ox3FFF Not implemented 16 Battery buffered Data RAM byte 0x00 mete accessible with SFR mapped SRAM 0x3000 Revision number Checksum 2 ROM Mode Handlers 12 lt Library Functions _ 0x007F Vectors 0x0000 Figure 9 Memory map The following memory blocks are implemented 12 kByte ROM Memory 3 Byte SFR mapped Code Memory 6kByte Flash Code Memory e 2x128 Bytes FLASH User Data Memory 128 Bytes Flash Configuration ID and Reference cells e 2 128 Byte Data RAM thereof 128 bytes battery buffered optionally 16 bytes battery buffered XData RAM Preliminary Data Sheet 47 V0 9 2008 04 28 Cinfineon Functional Description 2 5 2 1 ROM A 12 ROM memory is located in addre
54. Crystal oscillator software software inactive inactive selectable selectable power down power down 2kHz RC Oscillator active active active inactive power down 12MHz Software software power down power down RC HF Oscillator selectable selectable Remark can be enabled by LF RX Interval timer active active active inactive LF Receiver Software software software inactive selectable Selectable selectable power down RF Transmitter software software inactive inactive selectable selectable power down power down Preliminary Data Sheet 38 V0 9 2008 04 28 Cinfineon em Functional Description Peripheral unit R DLE state POWER DOWN THERMAL state SHUTDOWN state min Detector software software o supply inactive Selectable selectable power down Note active block is powered is active and keeps its register contents Power consumption is high inactive block is powered cannot be used but keeps its register contents Power consumtion is low no supply block is not powered connot be used and all register content is lost Power consumption is zero Preliminary Data Sheet 39 V0 9 2008 04 28 Cinfineon em Functional Description 2 4 Fault protection The PMA7110 features multiple fault protections which prevent the application from unexpected behavior and deadlocks This chapter gives a brief overview of the available fault protections Detailed explanation of the usage can be found later in this document and in 1
55. EXTWU2 EXTWU1 EXTWUO 0 0 0 0 0 0 0 0 EXTWU7 External Wakeup 7 06 External Wakeup 6 EXTWUS External Wakeup 5 EXTWUA External Wakeup 4 EXTWUS3 External Wakeup 3 Preliminary Data Sheet 65 V0 9 2008 04 28 Cinfineon Functional Description EXTWU2 External Wakeup 2 EXTWU1 External Wakeup 1 EXTWUO External Wakeup 0 Watchdog Wakeup watchdog wakeup occurs after the watchdog timer has elapsed See Watchdog Timer on Page 40 for details about the watchdog timer TMAX Wakeup wakeup occurs only if the device was in THERMAL SHUTDOWN state and the temperature falls below the threshold temperature See Functional Block Description on Page 41 for details about the TMAX wakeup LF Receiver Wakeup Event The LF receiver wakeup can be enabled by setting either SFR bit WUM 5 LFCD or SFR bit WUM 4 LFSY or SFR bit WUM 3 LFPM1 and or SFR bitWUM 2 LFPMO The wakeup source can be read in the SFR WUF Note The LF receiver has to be configured appropriate for the particular wakeup modes See LF Receiver on Page 85 for details External Wakeup Event Port PP1 PP4 and PP6 PP9 can be configured to wakeup the PMA7110 from POWER DOWN state by an external source Note PP1 PP4 and PP6 PP9 have to be configured according to External Wakeup on PP1 PP4 and PP6 PP9 on Page 109 for this fe
56. FR 5 READC SFR ADCM CSI ISARSATL SARSATI CL000 CG3FF EOC SAMPLE BUSY GAIN 1 0 5 ISUBC 2 0 TVC 2 0 SFR ADCCO STC 2 0 SFR ADCS SFR ADCC1 VReg Sensor SFR ADCC1 GAIN 1 01 SFR ADCOFF SFR ADCDH Data 9 8 SFR ADCDL bata 7 0 VDD sens Sl Lo RV 2 0 SFR ADCM CS 2 0 Ch6p Ch6n OV1P sens Channel 6 VIN sens VM sens VDD sens V2P sens TT VM2 sens ORD sens Figure 6 Block diagram Sensor Interface The sensor interface connects to the external sensors and to the internal on chip temperature and battery voltage sensors Preliminary Data Sheet 41 V0 9 2008 04 28 Cinfineon Functional Description All signal channels can be configured for differential or single ended operation Differential operation is only recommended for signals where the common mode voltage is stable while the positive and negative signal voltages vary symmetrically around the common mode voltage The input multiplexer selects one channel for the input signal and one channel for the reference voltage to the ADC Any channel can be selected as reference except channels 6 and 7 which are specially adapted to the low level signals from external sensors Preliminary Data Sheet 42 V0 9 2
57. FR Address 94 DBCLO CPU Debug Compare Register 0 Low Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 DBCL 7 DBCL 6 DBCL 5 DBCL 4 DBCL 3 DBCL 2 DBCL 1 DBCL 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 125 SFR Address 95 CPU Debug Compare Register 0 High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBCH 7 DBCH 6 DBCH 5 DBCH 4 DBCH 3 DBCH 2 DBCH 1 DBCH 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 126 SFR Address 96 DBTLO CPU Debug Target Register 0 Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBTL 7 DBTL 6 DBTL 5 DBTL 4 DBTL 3 DBTL 2 DBTL 1 DBTL 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 127 SFR Address 97 DBTHO CPU Debug Target Register 0 High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBTH 7 DBTH 6 DBTH 5 DBTH 4 DBTH 3 DBTH 2 DBTH 1 DBTH 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 128 SFR Address 9 DBCL1 CPU Debug Compare Register 1 Low Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBCL 7 DBCL 6 DBCL 5 DBCL 4 DBCL 3 DBCL 2 DBCL 1 DBCL 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 129 SFR Address 90 DBCH1 CPU Debug Compare Register 1 High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Preliminary Data She
58. FR bit CRCC 5 CRCSS The following figure shows an example for the usage of SFR bit CRCC 5 CRCSS and SFR bit CRCC 6 CRCSD A Data to be encoded CRCC 6 CRCSD CRCC 5 CRCSS 11111 Figure 20 Example for serial CRC generation checking svevegep Note The serial and byte aligned generation checking mechanism is interchangeable within the same generation checking process E g if a data packet consists of 18 bits then 16 bits can be processed byte aligned via SFR CRCD and the two remaining bits can be processed bit aligned by using SFR bit CRCC 5 CRCSS and SFR bit CRCC 6 CRCSD Preliminary Data Sheet 88 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 12 Pseudo Random Number Generator For many applications a pseudo random number generator is needed e g to vary the interval period between transmissions For this purpose a Maximum Length linear Feedback Shift Register MLFSR is available as a hardware unit Table 40 SFR Address SFR RNGD Random Number Generator Data SFR Abbr Addr Access Default Value Register RNGD rw u 55u Random Number Generator Data Register A user defined start value except 00 can be written to SFR RNGD The default value after startup is 55 1 The generation of a new random number is initiated by setting SFR bit CFG1 5 RNGEn After the random number is generated SF
59. Hz depending on the RF band used Table 25 Formulas for Crystal selection dependent of RF Bands 868 2 915MHz f frr zc 434MHz f p oct Senn xtal RF 48 315MHz f ARRANI xtal RF 48 Preliminary Data Sheet 71 V0 9 2008 04 28 Cinfineon em Functional Description Crystal startup time adjustment for different crystals is possible in steps of 250us by using the SFR bits XTCFG 2 0 XTDL Y2 0 Table 26 SFR Address C2 XTCFG Crystal Config Register Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u n u n u XTDLY2 XTDLY1 XTDLYO bro 0 0 loro rw rw u1 KTDLY2 0 Crystal Delay Timer delay time in steps of 250us typ 2 kHz RC LP Oscillator clcok 2kHz 111b typ 1750us 110b typ 1500us 101b typ 1250us 100b typ 1000us 11b typ 750us 10b typ 500us 01b typ 250us 006 typ Ous Frequency pulling from the nominal crystal frequency can be achieved by the internal capacitor banks This can be used for fine tuning the ASK carrier frequency and the lower and upper modulation frequencies for FSK modulation Thus frequency errors due to crystal or component tolerances can be trimmed away Crystal 18 20 MHz Oscillator FSK Modulator FSK Data SFR XTALO SFR XTAL1 Figure 14 Crystal Oscillator and FSK Modulator Block Diagram The SFRs SFR XTALO and SFR XTAL allow the trimming of the crystal freque
60. IO Manchester BiPhase encoder and decoder Hardware CRC generator Pseudo Random Number Generator Watchdog timer onchip debugging via interface Note In PMA7110 the Thermal Shout down function is not used 1 3 Applications Remote control systems for industrial and consumer applications e Security and Alarm systems Home automation systems Automatic meter reading Active Tagging Preliminary Data Sheet 10 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description 2 Functional Description 2 1 Pin Description VDD sens 1 C 38 VAN sens 2 37 VM1 sens 3 36 V1P sens 4 35 GNDB 5 34 GNDA 6 33 VBat 7 32 PGND 8 31 PA 9 30 GND 40 PMA7110 29 PP2 WU1 TXDATAOut 11 28 PP1 WUO0 I2C SDA OPMode2 12 27 2 SCL OPMode1 13 26 PP3 SPI CS WU2 14 25 PP4 WU3 SPI_MISO 15 24 PP5 SPI MOSI 16 23 PP6 WUA SPI 17 22 xReset 18 21 PP7 Ext Int1 WU5 19 20 Figure 1 Pin out of PMA7110 in TSSOP38 package Preliminary Data Sheet 11 V2N sens VM2 sens V2P sens RD sens GNDC VDDA VDDD VReg LF xLF AMUX2 AMUX1 XGND XTAL SCLK XTALCAP TME MSE PP9 Ext_Int0 WU7 PP8 WU6 V0 9 2008 04 28 Cinfineon PMA7110 Functional Des
61. KDT RSEN SEN 0 0 rw0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 GCEN 2 General Call Enable INP 2 interrupt not polling handling 0 interrupt 1 polling mode ACKDT 2 acknowledge data 0 ACK 1 ACKEN 2 acknowledge sequence enable PEN STOP condition enable Preliminary Data Sheet 111 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description RSEN 2 repeated START condition enable SEN START condition enable Table 60 SFR Address 9 I2CS IC Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICD 5 RnW RAck TBF RBF rc 0 0 rc 0 0 rc 0 0 rc 0 0 0 0 0 0 r 0 0 r 0 0 AM Address match set if device address matches with received address byte CD I2C bus collision detected OV Overflow Bit set if received byte has not been read out before next byte received also Iset if byte has not been transmitted after writing new byte to register I2CD In both ases the old byte value is kept the new byte is rejected The bit is automatically cleared by hardware if I2CS is read S 2 transmission in progress set on occurrance of start condition and reset on of stop condition RnW Read Write Bit Information states the actual state received with device address RAck Received A
62. MHz offset 132 tbd dBc Hz 10MHz offset D13 SSB Phase Noise RBW 100kHz 25 C DD 1 868MHz 87 tbd dBc Hz 10kHz offset 85 tbd dBc Hz 100kHz offset 88 tbd dBc Hz 250kHz offset 110 tbd dBc Hz 1MHz offset 134 tbd dBc Hz 10 2 offset D14 SSB Phase Noise RBW 100kHz 25 C QD 1 915MHz 86 tbd dBc Hz Q 10kHz offset 85 tbd dBc Hz 100kHz offset 87 tbd dBc Hz 250kHz offset 109 tbd dBc Hz 1MHz offset 135 tbd dBc Hz 10MHz offset D15 Spurious and Out 54 dBm EN300220 EUR Band Emission RBW 10kHz QD 1 434 868MHz 47 74MHz 87 5 118MHz 174 230MHz 470 862MHz D16 Spurious and Out 36 dBm EN300220 EUR Band Emission RBW 10kHz QD 1 434 868MHz other lt 1GHz D17 Spurious and Out 30 dBm EN300220 EUR Band Emission RBW 10kHz QD 1 434 868MHz other gt 1GHz Note Matching circuit as used in the 50 Ohm Output Testboard at the specified frequency Tolerances of the passive elements not taken into account Preliminary Data Sheet 132 V0 9 2008 04 28 Cinfineon eae Reference Table 80 LF Receiver V 72 1 3 6V Parameter Symbol Limit Values Unit Test Conditions typ max Remarks E1 LF Baseband 1 2 mV signal level required to Sensitivity achieve a BER better than Gain setting 1 0 1 100 square AM modulation Datarate 4000 Bit s SFR LFRXO tbd SFR LFCDM tbd SFR LF
63. N2 0 TORun starts the timer and SFR bit TCON2 1 TOFull is set when the timer is elapsed SFR bit TCON2 0 TORun is reset automatically if the timer elapses Timer 3 2 utilizes SFR THO as starting value and SFR bit TCON2 5 T1Full as timer elapsed flag Setting SFR bit TCON2 4 TiRun starts the timer SFR bit TCON2 5 T1Full is set when the timer is elapsed SFR bit TCON2 4 T1Run is reset automatically if the timer elapses Timer 3 operates exclusive as 8 bit bitrate timer for Manchester coding Therefore the timer needs neither a run nor an elapsed bit It is started automatically when the timer mode is set IE 7 EA IE 6 EID amp gt Interrupt Timer 2 T2 TH2 T2Mask T2Full T2Run 4 Timer 2 1 Timer 2 2 Baudrate strobe Y T3Run Timer 3 Timer 3 Reload T3Full u SE IETIEA amp Interrupt TL3 TH3 IE 6 EID Timer 3 T3Mask 4 Figure 28 Timer mode 3 Preliminary Data Sheet 100 V0 9 2008 04 28 Cinfineon em Functional Description Timer mode 4 Comprises e 16 bit timer with reload and bitrate strobe signal for RF Transmitter The timer unit is configured as a 16 bit reloadable timer SFR TL1 and SFR TH1 hold the start value SFR bit TCON2 4 TiRun is set the timer starts counting SFR bit TCON2 5 T1Full is set when the timer is elapsed The timer value is reloaded fro
64. P4 and PP6 PP9 on Page 109 The x in the table has to be replaced by any of 0 until 9 PP9 Preliminary Data Sheet 105 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Table 48 SFR Address 91 4 P1DIR IO Port1 Direction Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PD1 7 1 6 PD15 PD1 4 PD1 3 PD1 2 PD1 1 PD1 0 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 PD1 7 PP7 I O Port configuration Testmode DMUX6 DMUX2 direction PD1 6 1 Input port PD1 5 0 Output port PD1 4 PD1 3 PD1 2 2 configuration PD1 1 1 Input port PD1 0 0 Output port Table 49 SFR Address EB P3DIR IO Port3 Direction Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u n u n u PPD9 PPD8 0 0 0 0 0 0 0 0 0 0 0 0 rw u 1 rw u 1 PPD9 8 8 1 configuration 1 Input port 0 Output port T Table 50 SFR Address 904 P1OUT I O Port1 Data Out Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1_7 1_6 1_5 1_4 1_3 1_2 1_1 1_0 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 P1 7 P1 2 7 PP2 Data Out DMUX6 DMUX1 Data Out PullUp enable 1 Input port 0 Output port P1 1 P1 0 PP1 Data Out PullUp enable Table 51 SFR Address P3OUT l O Port
65. PP8 data In Preliminary Data Sheet 107 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 14 2 Spike Suppression on Input Pins To avoid metastabilities when reading the GPIO pins a synchronization stage is included and a two stage spikefilter suppresses spikes thus data is available to be read after a delay of maximum 2 systemclock periods Due to the synchronization stage the following possibilities might occur Signal duration Tsiena lt 1 systemclock period 1 Signal is surpressed 1 lt Tsienat lt 2 undefined if supressed or passed gt 2 Signal is available P1IN register Preliminary Data Sheet 108 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 14 3 External Wakeup on PP1 PP4 and PP6 PP9 PP1 PP4 and PP6 PP9 can additionally be used as external wakeup sources if enabled by the Wakeup Mask SFR bit EXWUM x MEXTWUX and configured as input pin by setting SFR bit P1DIR x PPDx The internal pullup pulldown resistor is enabled if SFR bit P1OUT x PPOx is set SFR bit P1SENS x PPSx selects the sensitivity high active low active Table 56 External Wakeup Configuration SFR Settings Description SFR bit PTDIR x PPDx 7 1 PPx configured as Input pullup enabled Wakeup SFR bit P1OUT x PPOx 1 occurs if PPx is forced to LOW externally SFR bit PISENS x PPSx 0 SFR bit EXWUM x MEXTWUX 0 SFR bit PTDIR x PPDx 7 1
66. PPx configured as Input pulldown enabled SFR bit P1OUT x PPOx 71 Wakeup occurs if PPx is forced to HIGH SFR bit PISENS x PPSx 1 externally SFR bit EXWUM x MEXTWUX 0 The x in the table has to be replaced by either 1 4 or 5 9 PPO PP4 PP6 PP9 2 5 14 4 Alternative Port Functionality In the following table the alternative port functionality is shown which has higher priority than standard port functionality Table 57 I O Port 1 Alternative Functionality Pin Function Description PPO I2C SCL 2 Serial Clock Line Configured to I2C clock pin if SFR bit CFG1 6 I2CEn is set Weak High has to be provided by an external pullup resistor or by the I2C master device Port Pin I O Standard port functionality OPMode1 I O Select operation mode PP1 I2C SDA I O 12 Serial Data Configured to 12 data pin if bit CFG1 6 I2CEn is set Weak High has to be provided either by the internal pullup resistor by an external pullup resistor or by the 2 master device Port Pin I O I O Standard I O port functionality WUO I O up by external wake up source OPMode2 I O Select operation mode Preliminary Data Sheet 109 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Pin Function Description PP2 TX Data Out If bit CFG1 4 RfTXPEn is set
67. Preliminary Data Sheet V0 9 April 2008 vem SG PMA7 1 10 RF Transmitter IC with embedded 8051 Microcontroller LF 125kHz ASK Receiver and FSK ASK 315 434 868 915 MHz Transmitter ni peos gt Sense amp Control Cinfineon Never stop thinking Edition 2008 04 28 Published by Infineon Technologies AG Am Campeon 1 12 85579 Neubiberg Germany O Infineon Technologies AG 2008 04 28 Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as guarantee of characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies Representatives worldwide www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies
68. R bit CFG1 5 RNGEn is reset automatically and the value is available in SFR RNGD Preliminary Data Sheet 89 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 13 Timer Unit Timer 0 Timer 1 Timer 2 Timer 3 The 7110 comprises four independent 16 bit timers Timer 0 1 operate as up counters timer 2 3 operate as down counters Timer counter 0 and 1 are fully compatible with Timer counter 0 and 1 of the Standard 8051 and can be used in the same four operating modes Mode 0 8 bit timer counter with a divide by 32 prescaler Mode 1 16 bit timer counter Mode 2 8 bit timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer counter 1 in this mode holds its count The effect is the same as setting TR1 0 The external inputs PP1 and PP9 can be programmed to function gate for timer counters 0 and 1 to facilitate pulse width measurements Each timer consists of two 8 bit registers THO and TLO for timer counter 0 TH1 and TL1 for timer counter 1 which may be combined to one timer configuration depending on the mode that is established The functions of the timers are controlled by two special function registers TCON and TMOD In the following descriptions the symbols THO and TLO are used to specify the high byte and the low byte of Timer 0 TH1 and TL1 for Timer 1 respectively The operating modes are described and shown for Timer 0 If
69. Reference SFR Registers on Page 144 2 4 1 Watchdog Timer For operation security a watchdog timer is available to avoid application deadlocks The watchdog timer must be reset periodically by the microcontroller otherwise the timer generates a software reset and forces a restart of PMA7110 program execution The watchdog timer duration is fixed to nominal 1 second The accuracy depends on the accuracy of the 2 kHz RC LP Oscillator which is used to clock the watchdog timer Setting SFR bit CFG2 1 WDRES resets the watchdog timer see Table 13 SFR Address D8 CFG2 Configuration Register 2 on Page 60 2 4 2 VMIN Detector This circuit will detect if the supply voltage is below the minimum value required to guarantee the measurement accuracy The ROM library functions which perform measurements will return the VMIN status in a statusbyte with the measurement result 2 4 3 FLASH Memory Checksum A CRC checksum is stored in the FLASH memory and can be recalculated and checked by the application program for verification of program code if needed Flash bit FCSP 7 ECCErr If a single bit error in the Flash memory occurs it is corrected by the Flash internal Error Correction Coder as an indication the FCSP 7 ECCErr bit is set see Table 101 SFR Address E9 FCSP Flash Control Register Sector Protection Control on Page 146 in Reference SFR Registers on Page 144 2 4 4 ADC Measurement Overflow amp Underflow The ROM Library functi
70. SH sector s The time required for the checking of the sectors depends on the selected sectors Note After the first Stop condition P is received the selected FLASH sectors are checked During this time incoming commands are not acknowledged S oxec AT os A seat CRGC AP Pause 35ms S oxeD Status CRCH CRCL nA P Figure 35 FLASH Check Erase Status Command Table 70 Parameter Sect Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sector4 3 Sector2 Sector1 0 Sector4 protected area thus don t care Sector3 protected area thus don t care Sector2 protected area thus don t care Sector1 1 check if User Data Sector is erased 0 don t check User Data Sector SectorO 1 check if Code sector is erased 0 don t check Code sector CRCH MSB of the CRC sum CRCL LSB of the CRC sum Table 71 Return Value Status Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u Sector4 3 Sector2 Sector1 0 Sector4 1 at least one bit is set in the sector 0 sector is erased or untested Sector3 1 at least one bit is set in the sector 0 sector is erased or untested Sector2 1 at least one bit is set in the sector 0 sector is erased or untested Sector1 1 at least one bit is set in the sector 0 sector is erased or untested SectorO 1 at
71. State In RUN state the CPU8051 executes programs stored in ROM or FLASH memory Peripherals are on or off according to the application program The watchdog WD is active and automatically cleared when entering RUN state on Wakeup event The CPU clock frequency is selectable by software All Wakeup events are ignored in RUN state but the corresponding flags get set and can be read and cleared 2 3 2 3 IDLE State In IDLE state the CPU8051 clock is disabled but Peripherals Timers ADC SPI Interface and Manchester Biphase Coder continues normal operation If a resume condition occurs the RUN state is reentered immediatelly The watchdog WD is active and reset automatically when entering IDLE state All wakeups are ignored in IDLE state but the corresponding flags are set if a wakeup occurs and can be evaluated once the device returns to the RUN state In case of a Peripheral requests an interrupt or an External Interrupt occurs the IDLE state is left for RUN state the Interrupt service routine is executed and on the next RETI return from interrupt instruction the IDLE State is re entered in case no Resume event has occured in between Resume events The resume source can be identified by reading REF Resume events may occur on following events RF transmitter buffer empty RF transmission finished LFreceiver buffer full Timer 2 underflow AID conversion finished RC LP Oscillator calibra
72. VDDA Negative Supply VM1 b GND 4 Sens Channel 1 VBA Positive Signal HL 500 1 x HL 5 GNDB Ground PGND amp GNDB S H E Preliminary Data Sheet 16 V0 9 2008 04 28 Cinfineon 5 Functional Description Pin PAD name Equivalent I O Schematic Function No 6 PGND ae I GNDA 7 MBat Power supply gt voltage regulators t VReg 5 e 8 PGND Power amplifier double bond PGND P ground GND gt Preliminary Data Sheet 17 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Pin PAD name Equivalent I O Schematic Function No 9 PA Power amplifier tput st 10 output stage PGND PGND 10 GND 100 PROGRAM7V GE 11 PP2WU1 GPIO port TXDATAOut 5 WU1 da rms Serial output of rn SR Manchester Biphase ECL encoded data Proz Jam T FH iE iH lt M 500 Doce
73. XData area and therefore not reset a System Reset After a Brownout Reset this feature can be used to possibly recover data from RAM After Power On Reset the GPR Registers are not initialzed thus they contain random data The application has to initialize the GPR Registers if needed Preliminary Data Sheet 61 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 6 System Controller While the microcontroller controls PMA7110 in RUN state the system controller takes over control in POWER DOWN state IDLE state and THERMAL SHUTDOWN state The system controller handles the system clock wakeup events and system resets System Controller SFR Registers Port lt T Wakeup Logic 2x high sensitive differential 1x standard differential analog interfaces Sensor Sensor Interface RF Transmitter LF Receiver ON OFF Timer Figure 11 Block diagram of the system controller Timer Calibration Unit LF ON OFF Timer Interval Timer Crystal Oscillator 12MHz Clock Controller Oscillator Clock Divider intern RC LP Oscillator system Clock 2 5 6 1 Wakeup Logic One of the key elements within the system controller is the wakeup logic which is responsible for transitions from POWER DOWN state to RUN state via INIT state The wakeup logic is clocked by the 2 kHz RC LP Oscillator thus the wakeup logic is fully
74. age 148 MMR1 0x85 Memory Mapped Register 1 n Page 148 MMR2 0x86 Memory Mapped Register 2 n Page 150 JOSCCONF 0 RC HF Oscillator Configuration Register n Page 155 reserved 0x80 0 Data Register P1DIR 0x91 1 Direction Register n Page 106 0x92 1 Data IN Register n Page 107 P10UT 0x90 1 Data OUT Register n Page 106 P1SENS 0x93 10 Port 1 Sensitivity Register n Page 107 P3DIR 0 3 Direction Register n Page 106 P3IN 0 3 Data IN Register n Page 107 P3OUT 0 0 3 Data OUT Register n Page 106 P3SENS OxED 3 Sensitivity Register n Page 107 P2 reserved 0 0 2 Data Register n u P2Dir reserved OxA1 2 Direction Register n u PCON reserved 0x87 Power Control Register n u PSW 0 Program Status Word n Page 57 REF 0 1 Resume Event Flag Register n Page 67 RFC 0 RF Transmitter Control Register n Page 79 RFD 0 8 RF Encoder Data Register n Page 82 RFENC 0 7 RF Encoder Control Register n Page 82 RFFSPLL 0 07 RF Frequency Synthesizer PLL Configuration n Page 155 RFS OxE6 RF Encoder Tx Status Register n Page 84 RFFSLD RF Frequency Synthesizer Lock Detector Configuration n Page 151 RFTX 0 RF Transmitter Configuration Register n Page 79 RFVCO OxDE RF Frequency Synthesizer VCO Configuration n Page 151 RNGD 0xAB RNG Data Register n Page 89 SBUF re
75. ata Sheet 113 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 15 2 General call sequence If a general call address is sent and bit I2CC 6 GCEn in control register is set the I2C bus behaves like a slave receiver i e the same procedure may be taken The defined general call protocol has to be done by software 2 5 15 3 Master mode sequence After enabling the bus module and configuration as master device it waits for fur ther actions given by the control register I2CC and simultaneously for a start condition from other master devices in the later case the master behaves like a slave i e the same procedure described above may be taken Control over the I2C bus is only taken if the I2C bus is in idle state and bit I2CC 0 SEN start enable in the control register plus the address of the wanted device including the access direction bit RnW in status register I2CS 3 is set by software The start condition and the following address byte is transmitted immediately on SCL and SDA An existing slave with the according device address responds with an acknowledge whereby bits IE 4 EI2C and I2CS 2 RAck in status register will be set accordingly After that the master may transmit write data to data register or receive read data register after reception data After data reception the master has to set an acknowledge This is done by setting bit I2CC 3 ACKEN and I2CC 4 ACKDT in control register Please see Table 30
76. ata to be transmitted On Off Keying by using RFENC 3 TXDD or the Manchester BiPhase encoder see also Manchester BiPhase Encoder with bit Rate Generator on Page 81 About FSK modulation please see Crystal Oscillator on Page 71 2 5 9 4 Voltage Controlled Oscillator VCO The VCO is using on chip inductors and varactors for tuning and has a nominal center frequency of 1750MHz The tuning range VCO is split up into 16 frequency ranges VCO Frequency Loop Filter Tuning Voltage V Figure 16 VCO tuning characteristic Preliminary Data Sheet 80 V0 9 2008 04 28 Cinfineon em Functional Description automatically by the operating system after power up or a System Reset by using the PLL Lock detector and the PLL Lock detection routine Additionally the VCO is always recalibrated by firmware if the crystal oscillator is selected as clock source by setting CFG0 0 ClkSel Table 118 SFR Address DE RFVCO RF Frequency Synthesizer VCO Config on Page 151 Additionally the PLL Lock Detector for VCO tuning curve selection may be used by the user program code before RF data transmission The PLL Lock Detection routine can be called by the user program for that reason Table 119 SFR Address D4H ADCDL ADC Result Register low Byte on Page 151 A ROM library function is available which selects the tuning curve automatically dependent on environmental conditions temperature Note Recalibration of the tuning curve is
77. ature Interval Timer Wakeup Event When the Interval Timer elapses a wakeup event is generated POWER DOWN state is left The wakeup can be identified by the application software reading SFR bit WUF O ITIM The Interval Timer is reloaded automatically with actual values from register ITPR and immediately restarted so the Interval Timer is even working in RUN state Note The Interval Timer is not maskable so the application will get Interval Timer wakeup events periodically If these Wakeup events occur during Run state they will set the appropriate Flag but not force the device through Init state Preliminary Data Sheet 66 V0 9 2008 04 28 Cinfineon em Functional Description IDLE state and Resume Event Handling If switched to IDLE state by setting SFR bit CFG0 5 IDLE the systemclock to the microcontoller is gated off Note IDLE state will only be entered if one of the units providing a resume event is enabled and active Otherwise the system will continue executing code in RUN state without entering IDLE state Only few peripherial components are still active in IDLE state The watchdog is active and will be initialized automatically before entering IDLE state thus IDLE state has a maximum duration of approx 1 second before a watchdog wakeup occurs The systemclock to the microcontroller is re enabled when a resume event occurs The program code continues working where it was suspended SFR bit CFGO 5 IDLE is
78. ax Remarks G1 Crystal startup time 1 2 ms Testboard with Crystal INX5032SD 500 02825 C 12pF forysta 18 08MHz G2 Crystal oscillator 4p 0 1750 us Progammable 250us Startup delay time Steps SFR G3 Crystal frequency ba 18 20 MHz G4 Paracitic 4 pF determined by PCB Layout G5 Serial resistance of Remax F 60 forysta 19 20MHz the crystal gg 80 Ohm ferystal 18 19MHz G6 Input inductance Losc 2 2 uH XTALOUT G7 Crystal fine tuning Ciyne 40 pF Selectable with 156 fF capacitance resolution 8 bits Table 82 12 MHz RC HF Oscillator Parameter Symbol Limit Values Unit Test Conditions min typ Remarks H1 Operating 11 64 12 00 12 36 MHz 3 0V T 25 frequency H3 Overall drift 5 Table 83 2kHz RC LP Oscillator H Parameter Symbol Limit Values Unit Test Conditions min typ max Remarks J1 Operating 1 3 2 2 8 2 3 0V T 25 C frequency J2 Overall drift 7 Preliminary Data Sheet 136 V0 9 2008 04 28 Cinfineon Table 84 Interval Timer H Parameter Symbol Limit Values Unit Test Conditions min typ max Remarks K1 Wake up interval Twy 0 035 9328 Adjustble with timer range reso
79. cknowledge Level states the actual level of the received acknowledge 0 if acknowledge 1 if not acknowledge received TBF Transmit Buffer Full set by hardware if register I2CD is written cleared automatically if data byte is taken over by the shift register to be transmitted RBF Receive Buffer Full set by hardware if a full data byte is received cleared automatically if register I2CD is read Table 61 SFR Address I2CD I2C Data Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CD 7 I2CD 6 12 0 5 I2CD 4 I2CD 3 I2CD 2 I2CD 1 I2CD 0 rw 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 I2CD 7 0 B bit Read Write Data Access should be done after reading I2CS Bits TBD RBF Table 62 SFR Address B1 2 I2C Bitrate Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIB 7 SPIB 6 5 SPIB 4 SPIB 3 SPIB 2 SPIB 1 SPIB 0 rw 0 0 0 0 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 12 7 0 bit Bitrate Data Preliminary Data Sheet 112 V0 9 2008 04 28 Cinfineon 5 Functional Description Table 63 SFR Address I2CM I2C Mode Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AT 5 4 2 1 rw 0 0 rw 1 1 rw 1 1 rw 0 0 rw 1 1 rw 1 1 rw 0 0 0 0 2 0 7 bit Address Data 2 5 15 1 Slave mode sequence Programming the slave interface To enable the interface the
80. consists of an on chip VCO an asynchronous divider chain with selectable overall division ratio a phase detector with charge pump and an internal loop filter see Table 118 SFR Address RFVCO RF Frequency Synthesizer VCO Config on Page 151 The PLL can be enabled manually by setting SFR bit RFC 1 ENFSYN The PLL lock frequency is determined by the used crystal see Table 25 Formulas for Crystal selection dependent of RF Bands on Page 71 and the appropriate configuration in the SFR bits RFTX 3 2 ISMB1 0 Preliminary Data Sheet 79 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 9 2 Power Amplifier PA The highly efficient power amplifier is enabled automatically if a byte is transmitted RFS 1 RFSE is set to 0 and if TX data are not output on pin PP2 CFG1 4 RfTXPEn Alternatively the power amplifier is enabled immediately by using 0 ENPA The nominal transmit power levels are 5 8 10dBm into 50 Ohm load at a supply voltage of 3 0V The power amplifier operating point must be optimized to the output power 5 8 10dBm regarding current consumption by properly setting the RFTX 1 0 PAOP 1 0 RFFSPLL 3 2 DCC 1 0 and using an optimal sized matching circuit The power amplifier should be enabled at least 100us after enabling the RF frequency synthesizer because of the PLL lock in time 2 5 9 3 ASK Modulator ASK modulation is done by turning on and off the power amplifier dependent on the baseband d
81. cription Table 1 Pin Description Pin Name Type Description Comments 1 VDD sens Supply Sensor positive supply same voltage as chip analog supply 2 V1N sens Analog Channel1 negative sensor input output of wheatstone bridge sensor 3 VM1 sens Supply Sensor negative supply same voltage as chip GND 4 V1P sens Analog Channel positive sensor input output of wheatstone bridge sensor 5 GNDB Supply Ground 6 GNDA Supply Ground 7 VBat Supply Battery supply voltage 8 PGND Supply RF transmitter ground 9 PA Analog RF transmitter output 10 GND Analog Ground 11 PP2 WU1 Digital GPIO External wakeup source internal TXDATAOut Serial output of pullup pulldown Manchester Biphase encoded data switchable 12 PP1 WUO Digital GPIO External wakeup source I2C internal I2C SDA bus interface data Select operation pullup pulldown OPMode2 mode switchable 13 PPO Digital 2 bus interface clock internal I2C SCL Select operation mode pullup pulldown 1 switchable 14 PPS SPI CS Digital GPIO SPI bus interface chip select internal WU2 External wakeup source pullup pulldown switchable 15 PP4 WU3 Digital GPIO SPI bus interface master internal MISO slave out External wakeup source pullup pulldown switchable 16 Digital GPIO SPI bus interface master out internal SPI MOSI slave in pullup pulldown switchable 17 PP6 WU4 Digital GPIO SPI bus interface clock
82. ct the Interrupt source peripheral from this Vector by reading IRQFR and the appropriate source within the peripheral from the various flag registers Timer 2 Interrupt Timer 3 Interrupt LF Receiver Interrupt RF Encoder Interrupt Preliminary Data Sheet 74 V0 9 2008 04 28 Cinfineon em Functional Description External Interrupts 0 and 1 The Dev NameShort1 gt has two external Interrupt sources Ext IntO PP9 and Ext Int1 on PP7 As in the CPU8051 the control bits and interrupt flags can be found in the TCON register please refer to Table 44 on Page 92 When enabled by setting 0 for External Interrupt 0 resp IE 2 EX1 for External Interrupt 1 interrupts can be generated from PP9 resp PP7 The External Interrupts 0 and 1 can be programmed to be level activated or negative transition activated by clearing or setting bit TCON O ITO respectively TCON 2 IT1 If bit ITx 0 the corresponding External Interrupt is triggered by a detected low level at the pin If ITx 1 the corresponding External Interrupt is negative edge triggered In this mode if successive samples of the pin show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx 1 then requests the interrupt If the External Interrupt is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has
83. ctional Description 2 5 6 3 Interval Timer Calibration Calibration is done by counting clock cycles from the crystal oscillator or the 12MHz RC HF Oscillator depending on the current systemclock during one 2kHz RC LP Oscillator period The calibration is performed automatically by a ROM library function see 1 Reference Documents on Page 157 Note If the crystal oscillator should be used for the calibration the crystal frequency has to be stored in the FLASH User Data Sector Table 22 SFR Address BA ITPL Interval Timer Precounter Low Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ITP 7 ITP 6 ITP 5 ITP 4 ITP 3 ITP 2 1 0 rw u 1 rw u 1 rw u 1 rw u 0 rw u 1 rw u 0 rw u 0 rw u 0 Table 23 SFR Address BB ITPH Interal Timer Precounter High Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u n u ITP 11 ITP 10 ITP 9 ITP 8 0 0 0 0 0 0 0 0 rw u 0 rw u 0 rw u 1 rw u 1 Note These SFRs can be modified manually as well for using other uncalibrated precounter values Preliminary Data Sheet 69 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 7 Clock Controller The Clock Controller for internal clock managment is part of the system controller The PMA7110 always starts up using the 12 MHz RC HF Oscillator to provide minimum startup time and minimum current consumption Changing the systemclock
84. ctive active active active CPU8051 active nactive supply no supply Non volatile SFRs active inactive inactive inactive System Controller content not content not lost content not lost lost Peripheral core active inactive supply no supply content SFR s content not content lost lost lost Manchester Biphase software software supply no supply Coder Timer selectable selectable Pheripheral modules software supply supply MFLSR selectable Peripheral modules software software no supply no supply I2C SPI ADC selectable selectable Watchdog active active supply no supply Preliminary Data Sheet 37 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Peripheral unit UN state IDLE state POWER DOWN THERMAL tate HUTDOWN state RAM Lower 128Bytes active nactive selectable selectable power content not power down down content lost lost content lost content inactive not lost content not lost RAM Upper 128Bytes active supply supply content content not content lost lost lost XData 16 bytes active inactive inactive content not content not content not lost lost lost FLASH memory active inactive ho supply no supply content not content notlost content not lost lost ROM active inactive ho supply no supply content not lost content not lost
85. d from 4000h 1 Flash protection is done by hardware In these modes setting the SFR bits FCS 3 PROG and FCS 2 ERASE is not possible 2 Flash programming and erasing is only possible via ROM Library functions 3 Whenever TME is set to high the current mode is left immediately and SCAN Test Mode is entered regardless if there is a reset or not Preliminary Data Sheet 30 V0 9 2008 04 28 Cinfineon em Functional Description States MSE 0 or TSHT Thermal shutdown a o PDWN Powerdown PP1 1 0 1 RUN Run application Lockbyte II set or 1 1 PP1 1 Lockbyte II not set IDLE CPU clock stopped Transitions WU Wakeup PE Powerdown enable TE Thermal shutdown enable WD Watchdog IFLG Idle flag RS Resume IRQ Interrupt request RETI Return from interrupt Figure 4 NORMAL Mode State transistion diagram For low power consumption and safety reasons the PMA7110 supports different operating states RUN state IDLE state and POWER DOWN mode and Thermal shutdown state The device operation in these states is described below Transitions between these states are either application software controlled or managed automatically by the system controller PDWN Powerdown CPU amp Peripherrals stopped IDLE CPU clock stopped peripherals are still running Preliminary Data Sheet 31 V0 9 2008 04 28 Cinfineon em Functional
86. d as a serial clock line SCL 7110 responds 2 Address 6C or to a general call if enabled by addressing slave address 00 General call is enabled by setting SFR bit I2CC 6 GCEn Data transfer up to 100 kbit s in standard mode or 400 kbit s in fast mode To control master slave interface the following registers are implemented Table 58 SFR Control Status und DataRegister SFR Abbr Addr Access perautt Register alue 2 B1 rw 00 0014 2 Bitrate Register I2CC A2 rw 00 00 Control Register I2CS 9B r rc 100 00 4 2 Status Register I2CD rw 00 00 IC Dataln DataOut Register If written data are stored in the internal data transmit register if read data is read from the data receive register Flags TBF and RBF are available in status register 2 A3 pw 6 6 Mode Register The basic I C bus configuration is set for both master and slave mode To allow bitlogic operations this register is readable and writeable The contained bits are partially set by software and reset by hardware resp set and reset by software itself The control register is only applicable in master mode in slave mode all functional steps are done automatically without external control Table 59 SFR Address A2 I2CC Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IGCEn INP AC
87. dard input2 for external sensor Analog Testsignal H 500 AMUX2 4 Port B GND GND amp esssssssssnseese 29 KLF Low Frequency xLF 50 15k xLF i Input gt T lt L GND Preliminary Data Sheet 24 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Pin PAD name Equivalent I O Schematic Function No 30 LF Low Frequency LF 50 15k LF i Input m T I GND 31 VReg Regulated Power VBat t Supply E E VReg a GND dos 4d GND 32 VDDD Digital Supply vene EET 0 Digital L GND 33 VDDA Analog Supply VDDA e H Analog core GND Preliminary Data Sheet 25 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Pin PAD name Equivalent I O Schematic Function No 34 IGNDC Ground PGND t JH GNDC e TH XGND F3 e 35 sens Connect to VODA diagnostic resister on sensor bridge otherwise no HL connection 500 4 RD Dy 36 V2P sens Channel 2 VDDA Positve Signal
88. e Interval Timer is responsible to wakeup the PMA7110 from the POWER DOWN state after predefined time interval It is clocked by the 2kHz RC LP Oscillator and incorporates two dividers Precounter can be calibrated to the systemclock and represents the timebase e Postcounter configures the Interval Timer duration It can be set from 1 256 Timing accuracy can be ensured by using a ROM library function which calibrates the precounter towards the accurate systemclock See 1 Reference Documents on Page 157 The Interval Timer duration is determined by the SFR ITPR This value is calculated by using the following equation recounter Intervaltimeriod s _ postcounter for HzRCLPOSseillator 5 The Postcounter ITPR is 8 bit register The maximum interval duration corresponds to 00x multiplication with 256 014 up to FF corresponds to a multiplication with 14 up to 255 dec Note After writing SFR ITPR some clock cyles are needed to activate the new setting SFR bit CFG1 1 ITInit is cleared automatically when the new setting is activated Table 21 SFR Address BC ITPR Interval Timer Period Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ITPR 7 ITPR 6 ITPR 5 ITPR 4 ITPR 3 ITPR 2 ITPR 1 ITPR O rw u 0 rw u 0 rw u 0 rw u 0 rw u 0 rw u 0 rw u 0 rw u 1 Preliminary Data Sheet 68 V0 9 2008 04 28 Cinfineon Fun
89. e Register n Page 112 2 0 2 I2C Control Register n Page 111 I2CD Ox9A I2C Data Register n Page 112 I2CM OxA3 I2C Mode Register n Page 113 I2CS 0x9B I2C Status Register n Page 112 IE OxA8 Interrupt Enable Register n Page 76 IP 0xB8 Interrupt Priority Register n Page 77 IRQFR Ox8F Interrupt Request Flag Register for extended interrupts n Page 77 ITPL OxBA Interval Timer Precounter Register Low Byte n Page 69 ITPH 0xBB Interval Timer Precounter Register High Byte n Page 69 ITPR OxBC Interval Timer Period Register n Page 68 LBD OxEF Low Battery Detector Control n Page 154 LFCDFIt 0xB2 t b d n t b d LFCDM 0xB5 t b d n t b d LFDIVO 0xB3 tb d n t b d LFDIV1 0xB4 tb d n t b d LFOOT 0 6 tb d n t b d LFOOTP OxC5 t b d n t b d LFPCFG OxC7 t b d n t b d LFPOL OxBE t b d n t b d LFPOH OxBF t b d n t b d LFP1L OxCE t b d n t b d Preliminary Data Sheet 54 V0 9 2008 04 28 Infineon PMA7110 Functional Description FR Abbr Addr Register description POWER SUPPLY Description VDDD Note Page LFP1H OxCF t b d n t b d LFRXO 0xB7 t b d n t b d LFRX1 0xB6 t b d n t b d LFRXC OxF9 LFRXD OxA5 tb d n t b d LFRXS 0 4 t b d n LFSYNCFG OxAF t b d n t b d LFSYNO 0 t b d n t b d LFSYN1 OxA7 t b d n t b d MMRO 0x84 Memory Mapped Register 0 n P
90. ebug commands Single Step Run Interruptible and Run until Breakpoint are executed by the single stepper The single stepper fetches the current opcode and enables opcode execution depending on the debug command To enable single stepping of branch instructions two sets of debug registers are implemented Afterwards the debug handler is entered again Preliminary Data Sheet 123 V0 9 2008 04 28 Infineon 5 Functional Description 2 5 18 3 Debugger Commands Set SFR Set an SFR to a user defined value Exception It is not possible to set the SFRs used by the Debug Function itself GPR3 GPR4 GPR5 DBCxx AT 0x00 aar JA bata ATP Adr represents the address of the SFR to be set Data this value has to be put into the SFR address specified by Aar ReadSFR Read the value of one SFR 9 5 Aer ATP Pause gt us Son A Adr represents the address of the SFR to be read Data this value was read on the SFR address specified by Adr SetData Set one Byte in RAM to user defined value A 0x06 JA adr A Data Adr represents the address of the Internal data memory to be set Data this value that has to be written into the internal data memory byte specified by Adr ReadData Read one Byte of the RAM ATP Pause gt s Adr represents the address of the Internal data memory location to be read Data t
91. eet 60 V0 9 2008 04 28 Cinfineon em Functional Description 2 5 5 General Purpose Registers GPR In PMA7110 XData Memory GPR1 GPRF are used In NORMAL Debug and Programming Mode as 16 GPR General Purpose Register which can be used by the application to store data beyond a POWER DOWN state period They consume low leakage current compared to the whole lower memory block by storing low amounts of data They can also be used as Testmode Registers in Functional Testmode for building blocks and Test Hardware but they are not reseted in these modes to allow data retention even after Brown out Table 15 GPR Registers Sm SSCS 0x00 XDATA General Purpose Register 0 GPR1 0x01 XDATA General Purpose Register 1 GPR2 0x02 XDATA General Purpose Register 2 GPR3 0x03 XDATA General Purpose Register 3 GPR4 0x04 XDATA General Purpose Register 4 GPR5 0x05 XDATA General Purpose Register 5 GPR6 0x06 XDATA General Purpose Register 6 GPR7 0x07 XDATA General Purpose Register 7 GPR8 0x08 XDATA General Purpose Register 8 GPR9 0x09 XDATA General Purpose Register 9 GPRA OxOA XDATA General Purpose Register 10 GPRB 0x0B XDATA General Purpose Register 11 GPRC OxOC XDATA General Purpose Register 12 GPRD XDATA General Purpose Register 13 GPRE OxOE XDATA General Purpose Register 14 GPRF OxOF XDATA General Purpose Register 15 Note GPRs the
92. ents The oper ating voltage range is 1 9 3 6 V 7110 contains 8051 based microcontroller Advanced power control system to minimize power consumption RF transmitter LFreceiver Multifunctional interface for external Sensors and embedded temperature and battery voltage sensor Measurement via embedded temperature and voltage sensor reading signal from analog inputs e g from external analog sensor are performed under software control so that the microcontroller can format and prepare this data for the RF transmission An intelligent power control system enables the build of ultra low power applications by using powersaving modes The integrated microcontroller is instruction set compatible to the standard 8051 processor It is equipped with various peripherals e g a hardware Manchester BiPhase Encoder Decoder and CRC Generator Checker enabling an easy implementation of customer specific applications The low power consumption FSK ASK Transmitter for 315 434 868 915 MHz frequency bands contains a fully integrated VCO a PLL synthesizer an ASK FSK modulator and an efficient power amplifier Fine tuning of the center frequency can be done by an on chip capacitor bank To store the microcontroller application program code and its unique ID Number an on chip FLASH memory is integrated Additional ROM storage is provided for the ROM library functions covering standard tasks required by various applications
93. ents of several sources which are listed below When an interrupt occurs the PC is automatically set to the Vector assigned to the Interrupt source From there the vector is forwarded via LJMP instruction into the Flash area and the offset of 4000 is added When an an unmasked interrupt occurs while the device is in Idle State this state is immediately left and the PC continues operation on the appropriate interrupt vector see Figure 29 After the processing of the Interrupt service routine instruction the device automatically returns into Idle State in case no Resume Event has occured in between If a Resume Event has been detected during the interrupt service routine the RETI instruction returns the PC to the location after the Idle Instruction It is highly recommended that this instruction to be a NOP The priority of the Interrupts can be configured using the IP register Setting a bit in IP to one assigns higher priority to the linked interrupt A high priority interrups can then interrupt a service routine from a low priority interrupt Table 29 Interrupt Vector locations Address Address Vector 0 03 4003 External Interrupt 0 PP9 Vector 1 be 400B Timer 0 Interrupt ector 2 13 40134 External Interrupt 1 PP7 ector 3 1B 401B Timer 1 Interrupt ector 4 23 4023 2 Interface Interrupt ector 5 2B 402B SPI Interface Interrupt ector 6 334 40334 Extended Interrupt the Flash software has to dete
94. eon PMA7110 Functional Description 2 5 17 7 Read Status This function is intended to read out the status of the previous executed functions pass fail It can be called whenever desired to verify if there were errors since the last Read Status call 5 66 AT oxaa x14 99 Pause gt 9us S 0x6D Status A CRCH CRCL fnaf P Figure 38 Read Status Command Table 72 Return Value Status Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CmdCnt3 CmdCnt2 ErrCnt1 ErrCnto InvCmdL CRCFail CmdCnt3 0 Counter indicates the number of executed commands since the first detected error 1111b 15 commands or more 1110b 14 commands b001b 1 command 0000b error occured in last command ErrCnt1 0 Counter of erroneous events since the last Read Status call 116 three or more errors 10b two errors 015 one error 006 no error InvCmdL 1 Invalid command length or execution fail since the last Read Status call 0 no Invalid command length or execution fail occured since the last Read Status call CRCFail 1 CRC Failure detected since the last Read Status call 0 no CRC Error occured since the last Read Status call CRCH MSB of the CRC sum CRCL LSB of the CRC sum from master to slave S start condition n from slave to master P stop condition A SR repeated start condition may be replaced by Stop Start condition
95. er Wakeup is not maskable in NORMAL mode IThis bit is only used for internal production test mode don t care for application Preliminary Data Sheet 64 V0 9 2008 04 28 Cinfineon PMA7110 Functional Description Table 17 SFR Address 2 ExtWUM Wakeup Mask Register 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MEXTWU7 MEXTWU6 MEXTWU5 MEXTWU4 03 MEXTWU2 MEXTWU1 MEXTWUO rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 rw u 1 MEXTWU7 Mask External Wakeup 7 MEXTWUG Mask External Wakeup 6 MEXTWUS Mask External Wakeup 5 MEXTWUA Mask External Wakeup 4 MEXTWUS3 Mask External Wakeup 3 MEXTWU2 Mask External Wakeup 2 MEXTWU1 Mask External Wakeup 1 MEXTWUO Mask External Wakeup 0 Table 18 SFR Address C0 WUF Wakeup Flag Register Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 WDOG TMU LFCD LFSY LFPM1 LFPMO n u ITIM rc x 0 rc x 0 rc x 0 rc x 0 rc x 0 rc x 0 r 0 0 rc x 0 WDOG Watchdog Wakeup TMU Underflow Wakeup LFCD LF receiver Carrier Wakeup LFSY LF receiver Sync match Wakeup LFPM1 LF receiver Pattern 1 match Wakeup LFPMO LF receiver Pattern 0 match Wakeup ITIM Interval Timer Wakeup Table 19 SFR Address F1 ExtWUF Wakeup Flag Register 2 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 EXTWU7 EXTWU6 IEXTWU5 IEXTWU4 EXTWU3
96. et 152 V0 9 2008 04 28 Infineon 5 Reference DBCH 7 DBCH 6 IDBCH 5 DBCH 4 DBCH 3 IDBCH 2 DBCH 1 DBCH 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 130 SFR Address 9 DBTL1 CPU Debug Target Register 1 low Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 DBTL 7 DBTL 6 DBTL 5 DBTL 4 DBTL 3 DBTL 2 DBTL 1 DBTL 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 131 SFR Address 9F DBTH1 CPU Debug Target Register 1 High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBTH 7 DBTH 6 DBTH 5 DBTH 4 DBTH 3 DBTH 2 DBTH 1 DBTH 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 rw 0 0 Table 132 SFR Address 4 FCTKAS Flash Tkill and Analog Output Select Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read0V9 CLKSEL ANSEL3 ANSEL2 ANSEL1 ANSELO TKILL1 TKILLO rw 0 0 rw 0 0 rw 1 1 rw 1 1 rw 1 1 rw 1 1 rw 1 1 rw 1 1 Bit 7 40 9 sets the read voltage to 0 9 V Bit 6 ICLKSEL Read clock select 0 g 1 Bit 5 ANSEL3 Analog Output Select bit 3 Bit 4 ANSEL2 Analog Output Select bit 2 Bit 3 ANSEL1 Analog Output Select bit 1 Bit 2 ANSELO Analog Output Select bit 0 Bit 1 TKILL1 ITkill Time bit 1 Bit 0 TKILLO ITkill Time bit 0 Preliminary Data Sheet 153 V0 9 2008 04 28
97. evaluation board at the specified frequency Tolerances of the passive elements not taken into account C5 Supply Current 500 700 ha 4 3 0 25 POWER DOWN 26 UA 3 0V T 85 C Preliminary Data Sheet 129 V0 9 2008 04 28 Cinfineon PMA7110 Reference Parameter Symbol Limit Values Unit min typ max Test Conditions Remarks C7 Supply Current THERMAL SHUTDOWN N U N U N U C8 Supply Current 0x00 MHz RC Osc IDLE SFR DIVIC systemclock 12 Noe tbd MA 3 0V T 25 tbd MA 3 0V T 85 C9 Supply Current 0x00 MHz RC Osc RUN SFR DIVIC systemclock 12 Ikun tbd MA 3 0V T 25 tbd MA 3 0V T 85 Preliminary Data Sheet 130 V0 9 2008 04 28 Cinfineon PMA7110 Table 79 RF Transmitter Characteristics Reference The RF Transmitter is characterized on the testboard with 50 Ohm matching network for specified frequency Tolerances of the passive elements not taken into accoun Under this condition the application is compliant to standards ETSI EN 300 220 and FCC 15 231 a b e Parameter Symbo Limit Values Unit Test Conditions min typ max Remarks D1 Transmit frequency 300 320 MHz 433 450 MHz 865 870 MHz 902 928
98. ferential Input t b d 420 kOhm disabled resistance E14 Preamble length Tpcambie ae Manchester coded input signal Datarate 4kBit s F1 LF Carrier Detector 0 2 2 5 mV Minimum Carrier Pulse threshold length 1ms Gain setting 1 SFR LFRXO tbd SFR LFCDM tbd SFR LFCDFLT tbd 1 2 B 7 5 Minimum Carrier Pulse length 1ms SFR LFRXO tbd SFR LFCDM tbd SFR LFCDFLT tbd F2 LF Carrier Detector 20 50 120 mV Minimum Carrier Pulse threshold length 1ms Gain setting 2 SFR LFRXO tbd SFR LFCDM tbd SFR LFCDFLT tbd 80 200 480 Minimum Carrier Pulse length 1ms SFR LFRXO tbd SFR LFCDM tbd SFR LFCDFLT tbd Carrier Detector 50 ms worst case 85 Freeze Hold Time if Calibration Freeze Bit SFR bit LFCDM 3 LFENFC is set Preliminary Data Sheet 134 V0 9 2008 04 28 Cinfineon dd Reference Parameter Symbol Limit Values Unit Test Conditions min typ max Remarks F4 Carrier Detector tbd tbd SFR bit LFCDFLT 4 5 CDFT1 Filter time 0 00b tbd us SFR bit LFCDFLT 4 5 CDFT1 0 01b tbd tbd us bit LFCDFLT 4 5 CDFT1 10b tbd us SFR bit LFCDFLT 4 5 CDFT1 0 116 Preliminary Data Sheet 135 V0 9 2008 04 28 Cinfineon Reference Table 81 Crystal Oscillator H Parameter Symbol Limit Values Unit Test Conditions min typ m
99. functional even when all other clock sources 12 MHz RC HF Oscillator and crystal oscillator are switched off Preliminary Data Sheet 62 V0 9 2008 04 28 Cinfineon em Functional Description The difference between Reset and Wakeup Reset Either via Software Reset Brownout or Reset pin the digital circuit is reset Program execution starts at address 0000 to perform reset initialization routines including operation mode selection and will jump to the FLASH at address 4000 in Normal Mode to execute the application program Wakeup Only the program counter of the microcontroller and its peripheral units are reset Program Execution starts at address 0000 to perform wakeup initialization routines for evaluating the wakeup source and jumps to the FLASH at 4000 to execute the application program Wakeup Event Handling Whenever a wakeup event occurs the PMA7110 leaves POWER DOWN state and enters RUN state to execute the application code This transition can be initiated from various sources The wakeup source can be identified by reading SFR WUF and SFR ExtWUF A wakeup source can be enabled or disabled by setting the appropriate bits in SFR WUM and SFR ExtWUM For security reasons the Interval Timer wakeup cannot be masked and the Interval Timer can not be disabled The Watchdog which is only active in RUN and Idle State can not be masked SFR WUF and SFR ExtWUF are read only thus no set clear operations are possible
100. ged by the application since they could be damaged irreversibly These are handled automatically by the ROM Library functions if needed Preliminary Data Sheet 52 V0 9 2008 04 28 infineon Functional Description Table 7 SFR Special Function Register Address Overview Addr Register Addr Register Addr Register Addr Register Addr Register Addr Register Addr Register Addr Register F8 CFGO F9 LFRXC FA FB FC FD FF F1 EXTWUF F2 EXTWUM F3 SPIB F4 SPIC F5 SPID F6 SPIM F7 SPIS E8 CFG1 E9 FCSP EA FCS EB P3DIR EC P3IN ED P3SENS RFC EF LBD 0 Et FCPPO 2 FCPP1 E3 FCSERM 4 E5 55 E6 RFS E7 RFENC D8 CFG2 D9 DSR DA ADCOFF DB ADCCO DC ADCC1 DD ADWBC DE RFVCO DF RFFSLD DO PSW D1 REF 02 ADCM D3 ADCS D4 ADCDL D5 ADCDH D6 OSCCONF D7 RFFSPLL c8 TCON2 c9 TMOD2 CA TL3 cB TH3 cc TL2 CD TH2 CE LFP1L CF LFP1H co WUF C1 WUM c2 XTCFG c3 XTAL1 c4 XTALO c5 LFOOTP c6 LFOOT c7 LFPCFG B8 IP B9 DIVIC BA ITPL BB ITPH BC ITPR BD TMAX BE LFPOL BF LFPOH BO P3Out B1 2 2 LFCDFIt B3 LFDIVO B4 LFDIV1 B5 LFCDM B6 LFRX1 B7 LFRXO A8 IE A9 CRCC AA CRCD AB RNGD AC CRCO AD

INFINEON PMA7110 Manual

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