3ALOGICS - TRH031M Datasheet
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1. r gt 7 00 0 20 lt gt A A Se H 8 8 o N 32 O di Y d 0 70 1 gt lt 0 80 0 30 010 XS amp 0 10 MAX H SAS 7 ba 0 10 0 127 om z 0 8 A 0 50 0 20 PICTURE 13 3 32 PIN LQFP PACKAGE DIMEMSION 4 CN 0 10 MAX 0 05 MIN 72 Confidential www 3ALogics com TRH031M Datasheet 3ALogics 13 56MHz Muti protocol RFID reader IC Data sheet Tel 82 31 715 7117 JO Fax 82 31 719 7551 P L A a Homepage http www 3alogics com Email rfid 3alogics com OF AQZ It s RFID 7 Floor Hyundai office Bldg 9 4 RFID amp Mobile SoC for Ubiquitous Technology Sunae dong Bundang gu Seongnam si Gyeonggi do 463 783 Korea www 3ALogics com Confidential 732. 64 dd AR II EE OE EN ORE HE ER RO EE EE tee 66 12 1 INTRODUCTION see a ODE EE EE EE Eeer 66 12 2 HOW TO USE TEST dE 66 CHAPTER13 ELECTRICAL CHARACTERISTICS sscssssssccsesecceccecscssceeccessecsesescecsesecseceecsecseseseeesess 68 13 1 OPERATING CONDITION TT EE eee eere ser mer eee eere cera rese rare serecereers eee reerserecerserse ese rsersernsers 68 13 2 CURRENT GONSUMEAONSAL l b ent aaa 68 13 3 STANDARB 1 O PIN DC CHARACTERISTICS rires 69 13 4 SCHMN TRIGGER INPUT THRESHOLD ssssssssssssssssssssssessossosssssssssossossossosessesseeosessesatsassassosessssacsassecsossasensesacsacsasees 69 13 5 TIMING MPECIFICATION MEE AAA EE N EE N 70 13 5 1 Timing for Read Write Strobe EE 70 13 5 2 Timing for SPI compatible interface EE 71 13 6 PACKAGE NFORMATION EE NE EE N Aa ia 72 www 3ALogics com Confidential 5 TRHO31M Datasheet C ha pte rl Introduction 1 1 Features Basic information 13 56MHz Multi protocol RFID Reader chip 3 3V operation voltage 32pin LQFP Package Supported Protocols ISO IEC 14443 A B Type ISO IEC 15693 Tag it Texas Instrument Performs Analog and Digital mixed operation as standards indicated Modulation Demodulation Encoding Decoding Framing and Collision Detection for Anti collision Automatic Data integrity check Functions for microprocessor interface 64 bytes FIFO buffer for immed
3. Tag2 UID 74 07 AE 48 95 b Tag UID Binary 0111 0100 0101 1011 0011 0110 8 2 8 0111 0100 0000 0111 1010 1110 2 2 E c Tag UID Received Data il 2 3 4 3 6 7 8 9 A B C D E F 10 11 12 13 14 15 0010111011 4 1 so 1 11011 1101170 011 11011 S A E O o0o 1 0 1 1 1 0 1 1 1100101010 011 1 TO a 5 Y Y Y LSB of 74H MSB of 74H First Collision RxLastBits 2 CollPos B Picture 5 4 Register value during collision occurrence Above picture 5 4 displays an example of two tags collision Picture 5 4 a is UID of two tags First byte has same value of 74 but from second byte each value of 5B and 07 are given Picture 5 4 b is tabularized UID in binary numbers Picture 5 4 c displays actual receiving steps For ISO 14443A LSB is received first and steps as picture 5 4 c occurs When TRHO31M terminates receiving collision occurs in 11 Receiver bit therefore Co Posflag value becomes B and RxLastBits value becomes 0 36 Confidential www 3ALogics com TRHO31M Datasheet If ZrAfColl is set as 1 2 byte is stored to FIFO as 03h and lower level 3 bytes are stored as 00h If ZrAfColl is set to 0 data value after Collision becomes unpredictable value different from original UID 5 5 Bit Level data Transmit Receive Table 5 6 BITFRAME register Add
4. ccccccssccsccsssscssssccsscssssssssssccsssssssssssscesssssssssssseessssssssesees 52 INTRODUGTION ss a ES AE ES mie te md 52 9 2 PRN ERDOWN MODE en 52 9 3 POWERDOWN MODE DIRECTIONS iy sea ARAR ennemi Ee ee een asla sail 53 9 3 1 Hardware PowerDown Mode 53 9 3 2 Software PowerDown Mode 53 4 Confidential www 3ALogics com TRH031M Datasheet CHAPTER10 TIMER U esse see E S ie eers se gees ARB M R Nee et oe se eee RAR RAR tits 54 LO LINTRODUCTIONE on casar aaa maa haste ist nana ie nine nd AE ER 54 10 2 TIMER SETTING yal ee ee es aa Geisa na derriere a een der teinte 54 LOS TIMER FUNCTION edd deed 56 CHAPTERIT ANA eege l ER EES 57 ET TRANSMITER SEE sass ER EE RES A nn Lea SS dae A Um ee Ee 57 11 2 TRANSMITTER STRUCTURE ee n e UL RRL NU NL a eek 57 11 3 TRANSMITTER FUNCTION see ee See s s ER ERGE ee See AR Se ee ee GR EE 57 11 3 1 TX1 and TX2 Function Settings 58 11 3 2 TX1 and TX2 Output Power Settings 60 11 3 3 TX1 and TX2 Modulation Index Acdtustment EEN 61 11 3 4 Recognition Distance and Power Consumpton EE 61 11 4 RECEMER s EE s s Se A VEE ANENE EN 62 11 5 RECEIVER STRUCTURES ese ee EE 62 11 6 RECE MER e el VEE OE EE ane 63 11 6 1 Envelope Detector ari lisses 63 11 6 2 Offset Coll cHOn sis ese rendaient ion 63 11 6 3 Variable Gain Amplifier VGA nee 63 11 64 Comparator EN
5. TRHO31M Datasheet 1 3 Pin Diagrams 30 Jada 29 It 28 aso 27 Toma 25 OZLS3L 4 x N m en AVSS TESTOUT TEST N AVDD wre RST R TRHO31M IRQ XOUT 32 LQFP PALE S XIN ADDR2 DVSS ADDR1 DVDD ADDRO oviva 6 Ivivaf Jor zviva Ir eviva z pviva Ier cviva T oviva st Lviva EN Picture 1 2 TRHO31M Pin Diagrams 8 Confidential www 3ALogics com TRHO31M Datasheet 1 4 Pin Description Table 1 1 TRHO31M Pin Map Number Pin Name Description Direction TESTOUT Test Output for factory test TESTIN Test Input for factory test WRB Write Bar Active low RDB Read Bar Active low Digital Ground Digital Power 3 bit Address Bus Positive Address Latch Enable Active High umsims 00 RST Reset Active High Test Output for factory test Receiver Input Analog Receive Reference Voltage Analog CSB Chip Select Bar Active Low TX1 Transmit Driver 1 Analog Transmit Driver 2 Analog www 3ALogics com Confidential 9 TRHO31M Datasheet 1 5 Special Function Register Group Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D OXOE OXOF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Ox1A Ox1B 0x1C Name Table 1 2 TRHO31M Special Function Register Group 1 Value FIFODATA FIFOData Do SS ss T exe RR RT eer
6. TRH031M Datasheet 3ALogics Datasheet Scope This technical document contains 3ALogics 13 56MHz Multi Protocol Reader IC TRHO31M features and structure Related 3ALogics Document TRHO3XM Cookbook Firmware User Manual Application Access Control Home Network amp Digital Door Lock POS Terminal Public Transportation Electronic Library Intelligent Toys E Parking Product Authentication Distribution Logistics www 3ALogics com Confidential 1 TRHO31M Datasheet Revision history Date Version Content Old version data sheet 2007 01 29 301 m Register initial value and address modification 2008 01 16 31 Nevv version data sheet preliminary release 2008 04 29 33 3 3 version release Notice All referenced brands product names service name and trademarks are the property of their respective owners AnyRead is a trademark of 3ALogics Copyright 2008 3ALogics Inc This draft document is a copyright protected by 3ALogics Except as permitted under the applicable laws of the user s country neither this draft document nor any extract from it may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic photocopying recording or otherwise without prior written permission Disclaimer Contact 3ALogics Inc 3ALogics accepts no liability for the content of this 7 Floor Hyundai office Bldg
7. su T mi Droge we on qe Tune s se ers Lea soa one WEE EIE ff ewe TT H v s KE EI wes TT T m rfT eT rene mr ev TT TT f O RE fT es 0 Deene EE emma o o EC msm S n sn we Bar asses War D amp VEE TEE seer P AS O BR EE tors TT mm ECC SE fm 10 Confidential www 3ALogics com TRHO31M Datasheet 1 6 Special Function Register Group Continue Address Table 1 3 TRHO31M Special Function Register Group 2 Name Value WE TI r a a RXWAIT iy 0 3 ma jeje e EN KAN CRCPresetLSB O RU I MEEN MEE MEE EE m D D Ty a E OE x m T T KAN AK NN ed TRELOADVALUE TReloadValue TT TT T ep t L ad m www 3ALogics com Confidential 11 TRHO31M Datasheet Cha pter2 TRHO31M Functionality 2 1 Introduction This chapter will explain RFID communication process and role of TRHO31M instead of detailed functions of TRH31M 2 2 RFID Reader Microprocessor TRHO3IM Antenna Picture 2 1 RFID Reader Picture 2 1 displays 13 56MHz RFID reader structure using TRHO31M As displayed on picture TRHO31M is placed between antenna and microprocessor TRHO31M from microprocessor receives both command and data per each protocol format to tag through antenna Receiving process works conversely TRHO31M converts data from the antenna by digitizing and microprocess
8. 9 4 Sunae dong document or for the consequences of any actions taken on Bundang gu Seongnam si Gyeonggi do 463 783 Korea the basis of the information provided unless that TEL 82 31 715 7117 FAX 82 31 719 7551 information is subsequently confirmed in vvriting If you are not the intended recipient you are notified that disclosing copying distributing or taking any action in reliance on the homepage http www 3ALogics com E mail rfid 3ALogics com contents of this information is strictly prohibited Printed in the Republic of Korea 2 Confidential www 3ALogics com TRHO31M Datasheet Document Contents CHAPTER1 INTRODUCTION scccsssssssssssosserssssssonsorsarsssonsossarsssensonsessassssonsorsassnsonsonsersassasonsorsassssonsors 6 di EEATURES CD LS ci 6 1 2 BOEK DIAGRAM EE EE sab nb te 7 UE dee 8 1 4 PIN DESCRIPTION isus da s Mes nus 9 1 5 SPECIAL FUNCTION REGISTER GROUP ss AR AR ee ae Aag s f nina editer 10 1 6 SPECIAL FUNCTION REGISTER GROUP CONTINUE 11 CHAPTER2 TRHO31M FUNCTIONALITY esse see see see sesse see see se ee see see ee se se ee Se ee Ge Ge ee ee Ge ee ee 12 EWL Ces ue 12 2 2 REID READER RE a a UB o sa OE nn 12 2 3 ROLE OF TRHOZ EE EE N AE EE EE apa 13 2 3 1 Modulation Demodulation eeste er ee ee eek oek ek Re ee eek oen ek eek oek ek Re eek oek RR Re eek eken Re
9. 001 Constant high 010 Demodulated RX Signal 100 Not modulated TX Signal Picture 13 1 displays transmit receive process Picture 12 1 a is actual signal on antenna Picture 12 1 b is transmitted digital signal from digital block to analog block for alteration Picture 12 1 c is digital signal originally received from tag and demodulated from analog block and sent to digital block User can confirm activation using TESTOUT pin to observe picture 12 1 b and picture 12 1 c signal TESTOUT pin output can be set using estSe flag of TESTOUTSEL 0x00 and if the value is 4 then picture 12 1 b and value is 2 then picture 12 1 c signal output occur www 3ALogics com Confidential 67 TRHO31M Datasheet Cha pter1 3 Electrical Characteristics 13 1 Operating condition range Symbol Parameter MIN TYP MAX UNIT Top Operating temperature range 25 25 85 C DVDD Digital power supply 3 0 3 3 3 6 V AVDD Analog power supply 3 0 33 3 6 V TVDD Transmitter power supply 3 0 33 3 6 V 13 2 Current consumption Symbol Parameter Conditions MIN TYP MAX UNIT NT Idle Command 3 9 4 7 5 6 mA igital Su current di S EE Power Down mode 013 016 022 uA i EE Receiver On 2 15 2 26 2 35 mA nalog Su curren GER Power Down mode 0 047 0 056 0 068 uA Continuous Wave 80 100 120 mA Antenna unconnected TX1 and TX2 unconnected Itvop Transmitter Supply cur
10. PVVM method distinguishes data by pulse length 5 3 Receiver Data Format Select Receiver data format is determined by registers same as Transmit data AxFraming flag of DECODCONTROL Ox1A register performs this activity Table 5 3 displays Receiver data format by RxFraming value Table 5 3 DECODCONTROL register Address Reset Value Ox1A 0x08 g z CJ foto o uni o o DECODCONTROL Number Description 5 ZrAfColl Store received data after Collision as 0 4 2 RxFraming 000 Set decoder to Tag It Protocol mode 01x Set decoder to ISO 14443 A Type mode 10x Set decoder to ISO 15693 mode 11x Set decoder to ISO 14443 B Type mode Picture 5 2 displays Receiver data format by protocol All protocols use sub carrier and they use Manchester coding method except ISO 14443B type ISO 14443A type and ISO 14443B type use 847 KHz subcarrier and ISO 14443B type use BPSK modulation BPSK modulation is a method changing phase 180 when data is changed ISO 15693 use same format with ISO 14443A type and subcarrier speed is half of ISO 14443A 423 KHz For Tag it change subcarrier speed to tabularize data For data 1 subcarrier changes from 484 KHz to 433 KHz and for data 0 changes from 423 KHz to 484 KHz conversely 32 Confidential www 3ALogics com TRHO31M Datasheet ZrAfColl flag of DECODCONTROL Ox1A register used only by ISO 14443A type When ZrAfColl flag is set to 1 after Collision error received data is sa
11. is a received signal from analog part after demodulation As seen on picture 2 5 there is a time delay between ending TX and beginning RX Also TX and RX do not occur normally because it is not possible to receive response when tag is outside of antenna recognition distance Therefore software is developed for normal transmission TRHO31M will idle waiting for receiving signal when no response from tag Consequently timer and interrupt should be used in case failed receiving signal after transmission From above example using receiving interrupt and timer interrupt if completing receiving it activates receiving interrupt If signal is not received in given time timer interrupt occurs For these action to happen set from IEN 0x06 to use timer interrupt and receive interrupt and set TReloadValue to applicable distance Interval Picture 2 5 Lastly set TCONTOL 0x2B register to TStartTxEnd thereafter set the timer to count after signal transmission From microprocessor normal completion of transmitting and receiving can be determined very simply by type of interrupt generated after completion of transmitting and receiving 16 Confidential www 3ALogics com TRH031M Datasheet Cha pte r3 Host Interface 3 1 Introduction Host typically means microprocessor TRHO31M supports 4 types of parallel interface and SPI serial interface to host 3 2 Parallel Interface TRHO31M supports total of 4 types of parallel interface A
12. value to be transmitted from Tag It protocol Table 5 2 Transmit data format by 7xCoding value TxCoding Standard Format o ISO 14443A Modified Miller ISO 15693 1 out of 256 coding Pulse Position Modulation ISO 15693 lout of 4 coding Pulse Position Modulation enin HR 0 1 a 14443A b 14443B I l I I l I l I I l l l I I l I I I I I I l I l I l I I 00 01 10 11 00 01 10 11 l 1 1 I l l I l l I l I I I l I l I I l l I I l I l I I l 00 01 10 11 00 01 10 11 c 15693 1 out of 4 coding I i 1 2 3 4 5 6 7 8 249 250 251 252 253 254 255 256 d 15693 1 out of 256 coding I I d Tag It Picture 5 1 Encoding method by protocol www 3ALogics com Confidential 31 TRHO31M Datasheet Picture 5 1 displays Encoding method by protocol ISO 14443A type Picture 5 1 a encode by Modified Miller form and two data formats to display 0 ISO 14443B type Picture 5 1 b is the most standard encoding method NRZ coding ISO 15693 two forms of PPM Pulse Position Modulation method to indicate data Picture 5 1 c and picture 5 1 d display tvvo Encoding method for ISO 15693 PPM format is a method of data value to tabularize as pulse location Reader can select either one of these two formats and tag responds by both data format Tag It protocol use PVVM Pulse VVidth Modulation method
13. 0 Not transfer TxIRq interrupt signal to IRQ pin 1 Transfer TxIRq interrupt signal to IRQ pin RxlEn 0 Not transfer RxIRq interrupt signal to IRQ pin bu E IdlelEn 0 Not transfer IdleIRq interrupt signal to IRQ pin Hi nr amp gage HiAlertIEn 0 Not transfer HiAlertIRq signal to IRQ pin tr ge LoAlertIEn 0 Not transfer LoAlertiRq interrupt signal to IRQ pin E www 3ALogics com Confidential 49 TRHO31M Datasheet TRHO31M alerts microprocessor through IRQ pin when interrupt occurs in IEN 0x06 register setting Therefore user must select interrupts to be used set in IEN 0x06 register Microprocessor through IRQ pin is alerted of interrupt occurrence but to know which interrupt must confirm by reading from IRQ 0x07 register When microprocessor set the interrupt in IEN 0x06 and verify interrupt occurrence through IRQ pin microprocessor read IRQ 0x07 register IRQ 0x07 register is automatically set to 1 when interrupt occurs but maintains the value until microprocessor change the value to 0 When multiple interrupt occur if not microprocessor initialize interrupt to 0 despite additional interrupt occurrence IRQ pin has no impact thus microprocessor is not aware of interrupt occurrence Therefore interrupt request is recommended to re initialize after occurrence Occurred interrupt request is modified in IRQ 0x07 register and other values to be maintained as previous value IEN Ox06 register and IRQ 0x07 register have d
14. Data Hexadecimal FIFO 58 36 Picture 5 6 Bit Level Receive Picture 5 6 displays bit level Receiver steps When Receiver data On picture 5 6 a RxA ign value is set to 3 data is stored in FIFO as picture 5 6 b beginning 4 bit Picture 5 6 c displays hexadecimal data stored in FIFO 38 Confidential www 3ALogics com TRH031M Datasheet 5 6 Protocol This section describes each protocol and related register functions 5 6 1 ISO IEC 14443A Protocol Setting Decoding Method Decoding function improvement setting is possible with ISO 14443A type 3ALogics highly recommends this function since there are many advantages with virtually no disadvantage To use this function ADcdMd flag of RXCONTROL2 0x1E register must be set to 1 Table 5 7 RXCONTROL2 register Address Reset Value Pn O aand o o o o T o ou 1 ADcdMd Set ISO 14443A decoding method Dcdsrc Use to define input signal of receiver decoder logic 0 Use response signal from card as input 1 Use signal through TESTIN pin as input 7 1 Dedsrc flag of RXCONTROL2 0X1E register is a flag to determine which signal to decode When Dcdscr is 0 signal from receiver is decoded and when it is 1 signal from TEST N pin is decoded Signal received from TESTIN pin is decoding function testing purpose and typically is set to 0 when used for transmit receive purpos
15. High irrelevant of IRQInv value of ICONFIG 0x2D register 26 Confidential www 3ALogics com TRHO31M Datasheet ERR flag of STATUS1 0x03 register becomes High value when any error occurs from ERRFLAG 0x0A register This flag as well as IRQ flag automatically clears when ERRFLAG 0x0A register flags are cleared HiAlert and LoAlert flag are registers to check data size in FIFO For detailed explanations please referred 6 3 3 FIFO buffer related functions Table 4 3 STATUS2 register Name Address Reset Value 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit es ooo ZP eet sie abit abit 2 bit tit obit When timer is running value is 1 When stopped value is 0 LockStatus During operating Tag It protocol LockStatus of Memory Block save in GetBlock Response TerrFlag During operating Tag It protocol Saving ErrorFlag from tag response TadFlag During operating Tag It protocol Saving Address Flag from tag response When using ISO 14443A protocol store valid bit quantity when Collision occurs STATUS2 0x05 register same as STATUS1 0x03 is a register to confirm activating status STATUS2 register displays timer status TRunning flag of STATUS2 register maintains High value even during timer counting RxLastBitflag of STATUS2 register indicates number of valid bits location of last byte received For example if conflict occurs in 6th bit after RECEIVE command RxLastBits become 5 and valid bits
16. Transmitter setting can be divided into signal type selection and output power selection Next chapter explains transmitter setting method www 3ALogics com Confidential 57 TRHO31M Datasheet 11 3 1 TX1 and TX2 Function Setting Transmitter transmit TX_I Transferred digital signal for modulation modulated 13 56MHz carrier signal through TX1 and TX2 Also output signal from TX1 and TX2 for filtering and matching activate antenna through few external elements TX1 and TX2 output signal can be set in various format through TXCONTROL 0x11 register Table 11 1 TXCONTROL register Name Address Reset Value Como ModulatorSource FLOOASK TX2Inv TX2Cw TX2RFEn TXIRFEn ModulatorSource Select the modulator source 00 Constant Low 01 Constant High 10 Internal coder source 11 TESTIN pin source F100ASK 0 ASK modulation depth is determined by ModConductance value 1 Fix ASK modulation depth to 100 TX2Inv 0 TX2 pin and TX1 pin output carrier signals are inphase 1 TX2 pin output carrier signal is 180 phase to TX1 TX2Cw 0 TX2 pin and TX1 pin output signals are modulated 1 TX2 pin output signal is not modulated TX2RFEn 0 TX2 pin not used Output Constant Low value 1 TX2 pin used Output RF signal TX1RFEn 0 TX1 pin not used Output Constant Low value 1 TX1 pin used Output RF signal Table 11 2 TX1 related settings TXIRFEn F100ASK TXI Signal on TX1 EE 13 56MHz carrier
17. and remains idle mode TRANSMIT 1Eh command encodes FIFO stored data and after modulation then transmits through TX1 and TX2 pins When there is no data in FIFO it does not transmit but remains in IDLE 00h mode TRANSMIT 1Eh command sends no response command for test purpose at times RECEIVE 16h command is a command to demodulate decode response signal from antenna then stores in FIFO This command also activates by microprocessor and used mainly for test purpose TRANCEIVE 1Eh command executes TRANSMIT 1Ah and RECEIVE 16h commands continuously TRANCEIVE 1Eh command transmits data in FIFO after encoding modulation and stores response signal after demodulation decoding All these actions are performed continuously and when no response from tags it remains in receiving mode thus using IDLE OOh command to remain in idle status Activating TRANCEIVE 1Eh command when there is no data in FIFO all protocols except ISO IEC 15693 cannot execute commands but for ISO IEC 15693 after transmitting EOF signal then receive www 3ALogics com Confidential 25 TRHO31M Datasheet 4 3 Transmit Receive Status Check Microprocessor checks transmission status by reading TRHO31M register Not only execution of transmit receive status but also error occurrence and other status checks are possible Microprocessor occasionally checks information on TRHO31M transmit receive status and determines next course of action Table 4 2
18. are hovv to designate Read and Write using two pins WRB and RDB In Common mode WRB value being High implies Read and Low value implies Write Also in Common Mode Read Write point is indicated when RDB falls to Low value in either Read Write situation For Separate Mode Read Write is allotted in each pin WRB falling to Low value means Write and RDB falling to Low value means Read 3 2 1 Using Dedicated Address Using Dedicated Address address line constitutes in 3 bits thus not able to designate all TRHO31M memory map having total 6 bits Therefore TRHO31M utilizes low level 3 bits of PAGE 0x00 register to designate upper level 3 bits of address MSB of PAGE 0x00 register is set to 1 when using PAGE 0x00 register low level bit for address PAGE 0x00 register value is to set ADDR pin to all 0 and Write 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit Page Register UsePage PageSelect PageSelect 2 0 ADDR 2 0 Address 5 0 Picture 3 2 Dedicated Address Configuration Picture 3 2 displays Dedicated Address configuration ADDR implies data entered from TRHO31M input pin and Address implies to TRHO31M last used address 18 Confidential www 3ALogics com TRH031M Datasheet Table 3 1 PAGE register Name Address Reset Value X X useage o of of o PageSelect AE BE UsePage 0 The PageSelect is not in use for register address
19. become 5 bits Every bits of last received byte are received normally RxLastBits becomes 0 Please refer to 5 4 Anti Collision Lockstatus TerrFlag and TadFlag are flags to support TI Texas Instruments Tag It protocol In case of Tag It protocol tag response cannot be divided 8 bits evenly Therefore TRHO31M from tag response stores LockStatus TerrFlag and TadFlag data not store by FIFO LockStatus is Lock Status per specification and TerrFlag is Error Flag Lastly TadFlag is Address Flag www 3ALogics com Confidential 27 TRHO31M Datasheet 4 4 Control CONTROL 0x09 register is a register to execute various functions PowerDown of CONTROL 0x09 register leads TRHO31M to Stand by mode using software During power down mode TRHO31M cannot execute transmit receiving but power consumption is minimized For detailed explanations please refer to 9 3 2 TStopNow and TStartNow flag are used to execute timer When writing 1 to TStartNow flag timer begins counting and when writing 1 to 7StopNow flag timer counting stops For detailed explanations please refer to 10 3 FlushFIFO function is to delete data remaining in FIFO buffer When tag is not responding noise can be a cause Sometimes noise can be recognized as data and stored in FIFO When transmit receiving without deleting FIFO data incorrect data caused by noise can be transmitted Therefore before storing transmitted data to FIFO use F ushFIFO to dele
20. collision anti collision algorithm is used For ISO 14443B and ISO 15693 tag collision detection is required for anti collision to function However ISO 14443A requires hardware detection of collision location and collision occurrence to activate anti collision function TRHO31M has ability to detect collision and its location when collision occurs Received Signal Picture 5 3 Collision Detection 5 4 1 Collision Detection Picture 5 3 displays how TRHO31M detects collision Tag A and tag B have different value from 4 bit When tag and tag B have different value as seen on picture 5 3 receiver cannot determine whether Received data is 0 or 1 When TRHO31M receives a signal undetermined whether O or 1 Seen as picture 6 3 location is stored at Co Pos flag of COLLPOS OXOB register and set to 1 on CollErr flag of ERRFLAG OXOA register thus microprocessor can accomplish anti collision functions Parity bit is excluded from Co Pos calculation www 3ALogics com Confidential 35 TRHO31M Datasheet Table 5 5 COLLPOS register Name Address Reset Value X x 7 0 CollPos Indicate a position where first collision occurred When collision is detected ZrAfCo is set and all data after first collision are stored in FIFO as 0 This type of data processing is very convenient to develop software to handle anti collision meeting ISO standard a Tag UID Hexadecimal Tag 1 UID 74 5B 36 40 59
21. ee 13 23 2 Encoding Kl ne D E AA AAA AAA 14 2 3 3 ar Ie AR a ER RE EE EE ER N 15 234 Data Ate CACY oases EE RP EE EA KAR OE HER 15 2 3 5 Timer and Interrupt o a issues 16 CHAPTERS HOST INTERFACE 5Qygessscessesssrsssenconsorsersscensosssssssensenessoessscensonsersesensessrssersesensorsersscesoss 17 E 1 NTRODUCTON a EE EE SEARA Leal SECR 17 3 2 PARALLEL GE EE EE OE N N 17 3 2 1 Using Dedicated Address 18 3 3 PARALLEL INTERFACE HARDWARE CONFIGURATION nee 19 34 SPLSERIAL INTERFACE siistiin EO A E N 20 3 4 1 SPI Serial Interface Hardware Configuration 21 3 4 2 SPI Serial Interface Data Format EEN 22 aal dee ld EER EE AAA EE EE R s s dattes 24 APA INTRODUCTION DE EE ED Ee ee Oe RES 24 e Deel let E 24 4 3 TRANSMIT RECEIVE STATUS CHECK is sa niet Ge reses ans un tente ar ese entente 26 MA CONTROLER EER RE ton DR EE DR EE ID re tn 28 A 5 ERROR CHAE CK Re sbab Zn inin os 29 www 3ALogics com Confidential 3 TRHO31M Datasheet CHAPTERS PROTOCOL wivsccssciccccesccsdecesssctecestectisescSedecessccdssevsevbsiensaedssevseesssuvdaesssunsdessoesecsvevesedssovewoestessusdese 30 S A INTRODUCTION OR EE EE EE EE N N OE dt en N N sas 30 5 2 TRANSMIT DATA FORMAT SELECT Se ne sas aguas hante tn R sa BE Ge ee aad ea Gegee 30 5 3 RECEIVER DATA FORMAT SELECT N EE EE NE OE EN 32 5 3 1 Receive Delay Time cssscccssscsseccsssssceseccssssscaseecsssescaseessnstessussssenseessu
22. setting 1 The PageSelect is in use for register address setting PageSelect If UsePage value is 1 upper level of register address 3 bit PageSelect value is used 3 3 Parallel Interface Hardware Configuration Parallel interface are divided into 4 different types by address allocation methods and control signal use methods However difference in control methods do not impact hardware configuration Whether user selects Separated mode or Common mode hardware configuration is the same and control method is determined using software TRH031M control method is based on first executed write command after reset Basically if Separated mode is used to write after reset then until next reset Separate mode is used continuously Hardware configuration for address delivery method is as below In case of Dedicated Address PALE pin is not used In Multiplexed ADDR pin is not used Table 3 2 displays each value when not using PALE or ADDR Table 3 2 Allocation of signal based on Addressing methods PIN Name Dedicated Address Bus Multiplexed Address Bus PALE HIGH PALE ADDR2 ADDR2 LOVV ADDR1 ADDR1 HIGH ADDRO ADDRO HIGH www 3ALogics com Confidential 19 TRHO31M Datasheet 3 4 SPI Serial Interface TRHO31M also supports SPI serial interface in addition to parallel interface SPI Serial Peripheral Interface can send and receive data through 3 to 4 bus lines TRHO31M is ideal for small quantity bus control or control many TRHO3
23. structure differs based on each protocol and TRHO31M performs framing once user selects protocol type Frame structure is simply divided into SOF Start Of Frame and EOF End of Frame For ISO14443A parity is included after 8 bit data for data integrity 2 3 4 Data integrity Data integrity signifies data error status during transmission To check data integrity ordinary protocols during transmit receiving mode attaches surplus data for error checking CRC is one of the major errors checking method TRHO31M has hardware check capability for CRC parity error status check for data integrity during wireless interface As other features error checking is performed automatically by setting couple of features and result is sent to microprocessor through register www 3ALogics com Confidential 15 TRHO31M Datasheet 2 3 5 Timer and Interrupt a RF Signal il mul nala b Not Modulated TX Signal i I l l e Interval c Demodulated RX Signal Picture 2 5 Status of Tx Rx signal nterrupt and timer instruction is not fixed User can improve program efficiency by using timer and interrupt The following is an example of program using interrupt and timer Picture 2 5 is end of TX and beginning of RX in RFID communication Picture 2 5 a is analog signal waveform from antenna and picture 2 5 b is a signal transmitting from digital part to analog part for modulation after encoding Picture 2 5 c
24. the SOF to length of 11 ETU Lovv 3 ETU High www 3ALogics com Confidential 41 TRHO31M Datasheet a Frame format Picture 5 8 displays SOF and EOF used in ISO 14443B type Picture 5 8 a is frame b SOF i i architecture of ISO 14443B type Frame begins with SOF and ends with EOF and 751 y characters are located in betvveen Picture in e 5 8 b displays form of SOF SOF is a signal with low section length is 10 11etu c EOF and high section length is 2 3etu This value can be adjusted through SOFWidth LI flag Picture 5 8 c displays EOF signal bi eem EOF length is10 11etu and can be adjusted using FOFWidth flag Picture 5 8 SOF and EOF length Character Format Stop Start LSB i i lt pr EGT l Picture 5 9 EGT length Picture 5 9 explains EGT extra guard time Same as picture 5 8 character comprise of start bit and stop bit with total of 8 binary data Delay time between two characters is called EGT From specification EGT value is 0 57us when transmitting and 0 19us when receiving User can adjust EGT length by 128 fc using CharSpacing flag of BERAMING 0x17 register 42 Confidential www 3ALogics com TRH031M Datasheet Cha pter6 FIFO Buffer 6 1 Introduction TRHO31M has 64 Byte FIFO buffer This HFO buffer stores data temporarily while data transfer between microprocessor and TRH031M When microprocessor sends rece
25. 1M actions are initiated by commands Writing command to address COMMAND 0x01 register TRHO31M functions based on current register setting value and FIFO data value 4 2 Command Explanation Table 4 1 displays commands available in TRH031M Table 4 1 COMMAND register Name Address Reset 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit COMMAND 0x01 Ox3F ENE dare Po xax E Command Command register for operating the TRHO31M INIT 3Fh Initializing system after reset IDLE 00h Remains in IDLE mode Writing 00 to Command register will stop actions TRANSMIT 1Ah Transmit FIFO data then remains IDLE RECEIVE 16h Store received data to FIFO then remains IDLE TRANSCEIVE 1E Transmit FIFO data then store received data to FIFO Then IDLE INIT 3Fh command is executed automatically when TRHO31M is initializing system after reset Therefore this command does not execute by microprocessor INIT 3Fh command automatically stops after set time and becomes IDLE 00h status IDLE OOh command means idle status Basically TRHO31M is not executing any activities However this command can activate by microprocessor unlike INIT 3Fh When IDLE 00h command is activated by microprocessor it means discontinuing of any command in action For 24 Confidential www 3ALogics com TRHO31M Datasheet example when RECEIVE 16h is being executed writing IDLE OOh to command register then TRHO31M stops receiving
26. 1MS with one microprocessor SPI is divided by master and slave Master gives commands from SPI protocol and slave follows the commands TRHO31M functions as slave during communication SPI clock SCK is created by master and use MOSI Master Out Slave In during communication from master to slave and MISO Master Out Slave In during communication from slave to master NSS Negative Slave Select is similar to Chip Select being used during one master controlling multiple slaves and wanting to select specific slave to set command 4 yY y L AN ALKAA Slave Read point I I l l l l l l I l I l I l I I l I N wot lt lt 1 I Start point il lt Data Transition End point e Y y wo Km e x xo x l Picture 3 3 SPI Serial interface operation Picture 3 3 displays 1 byte 8bit delivery process using SPI interface To initiate SPI communication first NSS need to change to Low value MSB of MISO begins output from negative edge of NSS Then MOSI signal transfers from master to slave Slave reads MOSI signal from positive edge of SCK Up to this point is the process of 1 bit data transaction Basically from positive edge of SCK enter 1 bit of data from master to slave and from negative edge of SCK and negative edge of NSS slave outputs 1 bit of data to master This process is repeated 8 times to send and receiv
27. 2 signal integrity Table 4 5 ERRFLAG register Name Address Reset Value Po o fo oom ac o rien corr www 3ALogics com Confidential 29 TRHO31M Datasheet C ha pte r5 Protocol 5 1 Introduction This chapter explains protocols ISO IEC 14443 A B ISO15693 Tag It and use methods supported by TRH031M Changing protocols are done by changing registers related to protocols 5 2 Transmit Data Format Select To choose a protocol user must select Transmit data format Format implies Encoding method and Framing method and do not include Analog Modulation TRHO31M supports total 4 types of protocol and for I O15693 2 Encoding methods are available Therefore user can select up to 5 formats Table 5 1 CODCONTROL register Address Reset Value ed LI Po To T fuma om 3 TLAddr Used to select Address mode type during Tag It protocol Request m ni 2 0 TxCoding Set TX Encoding method 000 Set coder to ISO 14443 B type mode 001 Set coder to ISO 14443 A Type mode 010 Set coder to Tag It Protocol mode 110 Set coder to ISO 15693 standard mode 1 out of 256 coding 111 Set coder to ISO 15693 standard mode 1 out of 4 coding 30 Confidential www 3ALogics com TRH031M Datasheet IxCoding flag of CODCONT 0x14 register is a flag to select Transmit data format Below table is transmitting data format based on xCoding value 7 Addr flag is used to store Address Flag
28. 3 56MHz tag signal through RX pin and sensing envelop to convert to digital signal This process is called demodulation 11 5 Receiver Structure Pwdown gt Power management Rx_enable gt PEER Decoder Voltage reference gt VMID RxThreshold lt 2 0 gt Va Z Envelop Offset i Detector Correction Picture 11 2 Receiver Structure RX RxControll lt 2 gt Receiver configuration is displayed in Picture 11 2 Receiver performs demodulation process through Envelop detector VGA and Comparator VMID informs to comparator signal distinction standard level 62 Confidential www 3ALogics com TRHO31M Datasheet 11 6 Receiver Functions Receiving process can be divided into various levels Next sections will describe each role and possible settings 11 6 1 Envelope Detector Envelop detection is a level to delete carrier from received signal and output envelop changes TRHO31M suggest PMOS diode structure for more stable data receiving 11 6 2 Offset Collection In this level Offset collection for more clear and ideal DC biasing To find this DC bias point standard methods such as Pass Filtering and AC coupling vvere used 11 6 3 Variable Gain Amplifier VGA Demodulated signals are amplified for improved performance VGA Gain can be controlled using VGAGain flag of RXCONTROL1 0x19 register Table 11 9 displays VGA Gain based on VGAGain flag value T
29. LUE TReloadValue 7 0 TReloadValue The timer loads this value when it works From timer start event to timer to have specific timer value can be obtained using below equation 7Re oadValue implies timer start value and 7imerV lue is current timer value T Timer yimercloc X T Re loadValue TimerValue Subsequently T imer value is estimated from 74ns to 40s Table 10 3 TIMERVALUE register Name Address Reset Value X x 08 72 Timevawe 0 TimerValue Number Description 7 0 Shovv the current value of the timer TimerValue flag of TIMERVALUE is a register to display current timer value 7imerV lue flag comprises of 8 bits 7imerValue is made of total 8 bits thus timer can count from 0 to 2 www 3ALogics com Confidential 55 TRHO31M Datasheet 10 3 Timer Function Basically timer can start or stop using 7StartNow and 7StopNow flag of CONTROL 0x09 register Setting 7StartNow to 1 timer load 7Re oadV lue value to TimerValue flag and begin counting as reducing 7 rerVa ue value by 1 When timer is counting user sets 7StartNow to 1 Then timer stops and displays consumed time through 7imerV lue value Other than timer function through CONTROL Ox09 register to utilize timer for transmit receive select TCONTROL 0x2B register TCONTROL Ox2B register controls timer count and it is used when transmit receive begin or end For example if user wants to know the amount of time after tra
30. RHO31M Datasheet Cha pter10 Timer 10 1 Introduction Microprocessor executes various timer operations Using timer related registers timer speed timer control by event and timer interrupt occurrence are possible 10 2 Timer Setting Timer speed is determined by 7PreSca er flag value of TIMERCLK Ox2A register Timer speed implies changes in speed of timer actual value 7PreScaler is divided into total of 5 bits Timer speed is determined by 13 56MHz cycle In below equation Trimerciock implies timer speed T PreScaler T 2 TPrescaler x 73 7ns TimerClock 13 56MHz TPreScaler value can be set from O to 21 therefore possible Trimercock value is from 74ns to 150ms Table 10 1 TIMERCLK register Address Reset Value x x o o TRestart TPreScaler TRestart If this value is 1 timer count is completed to 0 then reload TReloadValue to automatically restart timer TPreScalar Set timer count speed 54 Confidential www 3ALogics com TRH031M Datasheet From TIMERCLK Ox2A register 7Restart is a register to auto re start timer automatically If TRestart is already set do not reduce the timer value to O and when timer value is 1 TReload Value value is reloaded and begins re counting TRHO31M timer begins counting from designated value User can set timer start value using TReload Value flag of TRELOADVALUE 0x2C register Table 10 2 TRELOADVALUE register Address Reset Value TRELOADVA
31. STATUS1 register Name Address Reset Value i ae TE ee 6 4 ModemsState 000 Idle ready status 001 TXSOF transmitting the SOF Start of flame 010 TxData transmitting data of FIFO buffer 011 TXEOF transmitting the EOF End of flame 100 GoToRx starting receive 101 PrepareRx waiting till selected period in the RXWAIT register is expired 110 AwaitingRx waiting for the receiving signal 111 Receiving receiving the signal 3 2 1 0 RQ Displays interrupt occurrence Set interrupt use by utilizing TEN register Shovving an error state VVhen ERRFLAG register value is 0 then ERR value is 0 HiAlert When FIFO stored data size is above certain level then value become 1 LoAlert When FIFO stored data size is below certain level then value become 1 STAUS1 register is a register confirming overall transmit receive status Also current executed transmit receive process can be verified by ModemState of STATUS1 register One transmit Frame is configured by SOF Start of Frame data and EOF End of Flame following ISO standard Through ModemsState flag of STATUS1 register can verify which step of Frame is being transmitted by transmitter Table 4 2 explains definition of ModemState value IRQ flag of STATUS1 0x03 register obtain High value when interrupt occurs by IEN 0x06 register setting When interrupt request completes it automatically changes to Low value IRQ flag of STATUS1 0x03 register perform Active
32. Store received CRC value on FIFO Setting CRC calculation type 0 ISO 14443A Type 1 ISO IEC3309 15014443B Type and ISO 15693 RxCRCEn Processing CRC calculation for received data ParityOdd Setting Parity calculation 14443 A type only 0 Even Parity 1 Odd Parity Setting parity error detecting code 14443 A type only CRCWr flag of REDUNDANCY 0x22 register writes received CRC value to FIFO buffer When CRCWr is set to 1 microprocessor reads CRC value from FIFO and calculates CRC value in software level to confirm signal integrity RxCRCEn and 7xCRCEn are flags to determine to use CRC during Transmit Receive When IxCRCEn is set to 1 CRC is sent with transmit data and when RxCRCEn is set to 1 then data is received and calculates CRC for signal integrity ISO 14443A may not use CRC based on command type thus user should confirm CRC use and may need to set AxCRCEn and 7xCRCEn Table 7 3 CRCPRESETLSB register Address Reset Value CRCPRESETLSE CRCPresetLSB 7 0 CRCPresetLSB Store CRC preset value LSB 8bit www 3ALogics com Confidential 47 TRHO31M Datasheet Table 7 4 CRCPRESETMSB register Address Reset CRCPRESETMSB CRCPresetMSB 7 0 CRCPresetMSB Store CRC preset value MSB 8bit CRCPRESETLSB 0x23 and CRCPRESETMSB 0x24 register are registers determining initial value of CRC calculation CRC preset value are 8 bits each through 2 registers since 16 bit CRC is used This regis
33. able 11 8 RXCONTROL1 register Address Reset Value pon La eee EEE 0 1 Number Name Description 2 0 VGAGain Adjust RX amp gain This value can be changed by protocol type and working environment www 3ALogics com Confidential 63 TRHO31M Datasheet Table 11 9 Gain value by VGA Gain setting VGAGain Gain dB Simulation Results f 11 6 4 Comparator Comparator is a last step to convert output signal through envelop detector and VGA to digital signal If comparator As seen on picture 11 3 a transforms very fast at certain threshold point inaccurate signals will output in noise environment In this type of situation comparator transformation characteristics should be modified Thus TRHO31M allows hysteresis range Picture 12 3 b in comparator Hysteresis range can be modified by HYR of RXTHRESHOLD 0x1C register Table 11 10 RXTHRESHOLD register Address Reset Value tal m ov e Comparator threshold output comparator T L I Picture 11 3 a Ordinary comparator noise impact b Hysteresis added comparator noise impact 64 Confidential www 3ALogics com TRH031M Datasheet Table 11 11 Hysteresis range of comparator based on HYR value HYR Hysteresis Range Hysteresis ranges Vrpp mV Simulation Results Table 11 11 displays hysteresis range based on WYR flag value As seen on above table hysteresis range of comparator can be modifi
34. al for modulation TX2 as well as TX1 output signal only when TX2RFEn is set to 1 and select modulation method by F100ASK value However TX2 has two additional setting compared to TX1 TX2Cw regardless of TXI Transferred digital signal for modulation signal to TX2 is a flag to output as same as when TX I value is 1 Lastly TX2Inv is a flag to output TX1 and TX2 phase in 180 reverse www 3ALogics com Confidential 59 TRHO31M Datasheet 11 3 2 TX1 and TX2 Output Power Setting TX1 and TX2 output drivability change by conductance value As conductance value rise TX1 and TX2 output rise as well TX1 and TX2 driver conductance use CwConductance of CVVCONDUCTANCE 0x12 register and can be adjusted Rp p channel resistance Table 11 4 CWCONDUCTANCE register Address Reset Value GENEE CvvConductance CwConductance This register value defines the output driver conductance of pins TX1 and TX2 Table 11 5 TX1 and TX2 P channel resistance CwConductance Rp Ohm Table 12 3 is a table to display TX1 and TX2 P channel resistance P channel resistance is inverse to driver conductance If CwConductance value is set to 3 P channel resistance value becomes 3 9 with parallel calculated considering when CwConductance 1 value is 10 14 and when CwConductance 2 value is 6 33 60 Confidential www 3ALogics com TRHO31M Datasheet 11 3 3 TX1 and TX2 Modulation Index Adjustment If FZOOASK is not se
35. e www 3ALogics com Confidential 39 TRHO31M Datasheet Modulation VVidth Changes ISO 14443A type protocol communication from reader to tag utilize 10096 ASK Modulation 1 Modified Miller coding method Modified Miller tabularize data value by pulse location and THRO31M allows functionality to adjust pulse width ModWidth flag of MODWIDTH 0x15 register is used for 14443A type pulse width adjustment in transmit signal ModWidth unit is 128 fc Table 5 8 MODWIDTH register Name Address Reset Value x x oe ROM ModWidth Name Description ModWidth Set 100 modulation width for 15014443A Tmoa 2 ModWidth 1 f Modulation l Width Picture 5 7 Modulation Width 40 Confidential www 3ALogics com TRHO31M Datasheet 5 6 2 ISO IEC 14443B Protocol ISO IEC 14443B Type Frame Setting TRHO31M contains functionality for frame adiustment using 14443B type protocol Using ISO 1444B type from frame SOF EOF and EGT length are predetermined Through BFRAMING 0x17 register user can adjust values within specification Table 5 9 BFRAMING register Address Reset Value BFRAMING 0x17 0x00 o o towan charspacing opman 5 EOFVVidth 0 Set the EOF to length of 10 ETU Um RE MEN SOFVVidth 00 Set the SOF to length of 10 ETU Lovv 2 ETU High 01 Set the SOF to length of 10 ETU Lovv 3 ETU High 10 Set the SOF to length of 11 ETU Lovv 2 ETU High 11 Set
36. e 8 bits of data and completes 1 byte transaction To send or receive more than 1 byte of data maintain NSS to low and send and receive by byte After all data is sent NSS returns to High value 20 Confidential www 3ALogics com TRHO31M Datasheet 3 4 1 SPI Serial Interface Hardware Configuration SPI interface unlike parallel interface is determined during reset process Therefore to use SPI modes before sending reset signal assign inputs as belovv table 4 2 Table 3 3 SPI SPI Interface Configuration PIN Name SPI Interface PALE NSS DATAO MISO www 3ALogics com Confidential 21 TRHO31M Datasheet 3 4 2 SPI Serial Interface Data Format Picture 3 4 displays SPI command structure Example Master reading 4 registers When executing Read command master must send to slave the register address wanted to read End byte is dummy thus to read 4 registers 5 bytes are entered Consequently to read n number of registers user must enter n 1 number of bytes Typically dummy uses 8 continuous O values One additional point of caution is that after address input data output occurs when next byte is entered As seen in the picture when addr1 is entered data0 output occur not datal In write command there is not output through MISO but through MOSI address and data types of signal should be entered Entry steps are first byte recognizes as address and before NSS becomes High previously entered b
37. ed from 34mV to 128mV Also comparator can set Input Reference Voltage Input Reference Voltage is standard voltage that comparator can determine whether 0 or 1 To adjust comparator Input Reference Voltage value CRO flag must be set to 1 If CRO is set to 1 Input Reference Voltage value changes by CRV value of RXTHRESHOLD Ox1C register If CRO value is set to 0 Input Reference Voltage is 1 65V irrelevant of CRV value Table 11 12 displays Input Reference Voltage value by CRV value Table 11 12 Comparator Input reference voltage by CRV value CRV Comparator Reference Voltage Reference voltage V Simulation Results em un No 7 kh se www 3ALogics com Confidential 65 TRHO31M Datasheet Chapter12 res 12 1 Introduction TRHO31M supports debugging process after design completion using various test features Using TESTOUT pin for signal output from TRHO31M user can test functionality 12 2 Hovv to use test pin Picture 12 1 is transmit and receiving process a RF Signal iii a n ir dr Tili em FU b Not Modulated TX Signal il 1 me Interval e c Demodulated RX Signal TX End RX Start Picture 12 1 Observable signals using test pin 66 Confidential www 3ALogics com TRH031M Datasheet Table 12 1 TESTOUTSEL register Name Address Reset Value Pelo tops 2 0 TestSel Select send out signal to TESTOUT pin 000 Constant low
38. frequency modulated AEE 13 56MHz carrier frequency 1 1 a 13 56MHz energy carrier 58 Confidential www 3ALogics com TRHO31M Datasheet Table 11 2 displays 7XIRFEn and F100ASK flag of TXCONTROL 0x11 register and TX1 output signal by TXI Transferred digital signal for modulation 7XZRFEn flag of TXCONTROL 0x11 register is a flag for TX1 operation Until 7XZRFEn is set to 1 there is no output signal from TX1 When 7XIRFEn set to 1 transmitter modulates TX I Transferred digital signal for modulation based on FIOOASK value When FIOOASK is set to 1 100 ASK modulation occurs and when FIOOASK is set to 0 user can modify modulation index based on ModConductance value 6 50 ASK Table 11 3 TX2 related settings TX2RFEn F100ASK TX2Cw TX2Inv TXI Signal on TX2 x C O X 13 56MHz carrier frequency modulated HA x A 13 56MHz carrier frequency 13 56MHz carrier frequency modulated 180 phase shift relative to TX1 13 56MHz carrier frequency 180 phase shift relative to TX1 X 13 56MHz carrier frequency 13 56MHz carrier frequency 180 phase shift relative to O HA 13 56MHz carrier frequency HIGH 13 56MHz carrier frequency 180 phase shift relative to TX1 13 56MHz carrier frequency 13 56MHz carrier frequency 180 phase shift relative to x HA Table 11 3 displays flag value of TXCONTROL 0x11 register and TX2 output signal by TXI Transferred digital sign
39. iate data storage 4 types of Parallel interface and SPI Serial interface Configurable interrupt can inform event to microprocessor Configurable and Adjustable timer function can cooperated with transceive state and interrupt Power consumption minimization Hardware Software power down function Minimized leakage and stand by current Other functions Transmit power and modulation index configuration Two Transmit drivers can be configured Adjustable receiver sensitivity depends on noise condition Data rate and pulse width configuration according to protocol standards Test pins for operation check 6 Confidential www 3ALogics com TRHO31M Datasheet 1 2 Block Diagram Picture 1 1 displays TRHO31M block diagram that is divided by digital and analog parts DVSS DVDD RST TVSS TVDD K lt Digital Part gt lt TX gt Special Function Encoder Register Group FIFO 64Byte TX1 ASK Modulator Decoder Manchester Decoder Main State Machine amp Controller Ti CRC Clock Power mer Calculator D r down Ctrl Fil Env l Comparator hon bid RX VGA Detector Parallel amp Serial Interface Clock Ocillator T liLllLlL NM LL WRB RDB DATA PALE ADDR IRQ XIN XOUT TEST20 TEST N TESTOUT VMID AVSS AVDD Test out Selector Picture 1 1 TRH031M Block Diagram www 3ALogics com Confidential 7
40. ifferent read write methods than other registers IEN 0x06 and IRQ 0x07 registers are changeable by bit level Basically user can change specific bit value and keep others as is This function is useful when initializing single interrupt Table 8 2 IRQ register Name Address Reset 7 bit 6 bit 5 bit 4 bit 1 3 bit 2 bit 1 bit 0 bit IR 0x07 0x00 Q SetIR TimerlR TxIR RxIR IdlelR HiAlertIR LoAlertIR q q q q q q q SetIRg 0 Clear Bit From 0 6 set marked bit as 0 1 Set Bit 0 6 set marked bit as 1 TimerlRq 0 TIMERVALUE register is not 0 R H 1 TIMERVALUE register is 0 TxIRq 0 FIFO data not transmitted LEN io memes O RxIRq 0 Receiving not complete AFGEE HiAlertIRq 0 FIFO available space is more than WaterLevel 1 HFO available space is less than WaterLevel LoAlertIRq 0 FIFO data is more than WaterLevel 1 HFO data is less than WaterLevel IdleIRq 0 Not in Idle mode 1 Command execution complete and remains in Idle mode 50 Confidential www 3ALogics com TRHO31M Datasheet a Bit Setting Register Value before VVrite VVrite Data 0x9C Register Value After VVrite b Bit Clear Register Value before VVrite Write Data 0x1C Register Value After Write Picture 8 1 IEN and IRQ register setting method Above pict
41. ive command data is written to FIFO buffer and if transmit command is sent then received data is stored in FIFO FIFO related functions same as other TRHO31M functions are executed through register 6 2 FIFO Buffer Data Input Output FIFO buffer input output is accomplished using FIFODATA Ox02 register Microprocessor write to FIFODATA 0x02 register the data to be transmitted and read data received through FIFODATA 0x02 register FIFODATA Ox02 register outputs first data stored in FIFO Again FIFODATA 0x02 register read data sequentially based on first in first out basis Table 6 1 FIFODATA register Address Reset Value X FIFODATA 0x02 FIFOData Number Description 7 0 FIFOData FIFO buffer input output register FlFOLength flag of FIFOLENGTH 0x04 register is a register expressing FIFO buffer stored data in byte level FIFOLength flag comprises of 7 bits to express up to 64 bytes www 3ALogics com Confidential 43 TRHO31M Datasheet Table 6 2 HFOLENGTH register Address Reset Value ei om FIFOLength Number Description 6 FIFOLength Show the number of bytes stored in the FIFO buffer 6 3 FIFO Buffer Related Functions 6 3 1 FIFO Buffer Data Deletion FIFO buffer data can be deleted by F ushFIFO flag of CONTROL 0x09 register Finally FIFOLENGTH 0x04 becomes 0 and FIFO can store up to 64 bytes AlushAIFO command allows inaccurate data deletion due to noise before tra
42. ll 4 interfaces support 8 bit data bus differentiated by read write execution methods and allotted address methods User can select any one of 4 interfaces that is more convenient and efficient Picture 3 1 displays 4 interface types supported by TRHO31M PALE CSB ST H i WRB I CSB e r _ data read point WRB i RDB l N Lei I DATA address read point __ data read point address read point a Multiplexed Addressing b Dedicated Addressing WB SD RB gt gt gt l Read l Read RDB RDB read point N f read point yy id I WRB WRB N vo __ write point Write RDB i RDB 7 _ write point K v c Common mode d Seperated mode Picture 3 1 Shape of TRHO31M supported microprocessor interface www 3ALogics com Confidential 17 TRHO31M Datasheet There is 2 vvays to delivery address Picture 3 1 a and picture 3 1 b display the difference of Multiplexed Addressing and Dedicated Addressing VVhen using Multiplexed Addressing Picture 3 1 a address is delivered through data bus When address is read is determined by PALE pin Dedicated Addressing is used by dividing data bus and address bus Instead of using PALE pin address is controlled by VVRB and RDB pin Picture 3 1 c and picture 3 1 d are differences of Common Mode control method and Separated Mode control method Differences of tvvo methods
43. nsmit complete 7Start7 gt xEnd of TCONTROL 0x2B register set to 1 Table 10 4 TCONTROL register Name Address Reset Value 7 6 5 4 bit 3 bit 2 bit 1 bit 0 bit TCONTROL x2B 0x06 bit bit bit ofofolo TStopRxEnd TStopRxBe TStartTxEnd TStartTxBe Number Description TStopRxEnd is a flag to stop timer after transmit completion and 7StopRxBe is a flag to start timer when receiver begins 7Running flag of SecondaryStatus register displays current timer status When start event begins timer begins to count and 7Running flag becomes 1 Also when end event begins timer stops counting and 7Running flag returns to 0 Timer is set to create interrupt 7imer Rq flag of IRQ register is an interrupt request when timer value becomes 0 56 Confidential www 3ALogics com TRH031M Datasheet Cha pterl 1 Analog 11 1 Transmitter Analog transmitter comprise of control block ASK Modulator and driver Transmitter transmits modulated 13 56MHz carrier frequency simultaneously controls TX1 and TX2 pin output signals 11 2 Transmitter Structure CwConductance lt 5 0 gt DA ModConductance lt 5 0 gt Modulator Powerdown 13 56MHz Clock TX Controller TX2 TX KNot modulated TX Signal TXCONTROL lt 6 0 gt Picture 11 1 Transmitter Structure Picture 11 1 displays transmitter configuration TRHO31M use two transmitter drivers for antenna signal efficiency 11 3 Transmitter Function
44. nsmit receive function 6 3 2 FIFO Buffer Error When data is full in FIFO buffer error occurs and sets FJFOOvf of ERRFLAG 0x0A register to 1 FFOOvf error can be cleared using FlushFiFO command 6 3 3 FIFO Buffer caused Interrupt There can be interrupts due to TRHO31M FIFO buffer stored data quantity and these interrupts occurs by Waterleve flag of FIFOLEVEL 0x29 register value 44 Confidential www 3ALogics com TRHO31M Datasheet Table 6 3 HFOLEVEL register Name Address Reset Value WaterLevel me nm nem WaterLevel Set HiAlert and LoAlert alert level HiAlert occurs when FIFO available space is below WaterLevel LoAlert occurs when FIFO stored data quantity is below WaterLevel WaterLevel 4 Byte 1 Byte 2 ie LoAlert Interrupt Request Byte 3 Byte 4 mw To LoAlert Threshold Byte 5 Byte 6 No Interrupt Request Byte 59 Byte 60 Byte 61 a LI HiAlert Threshold Byte 62 Byte 63 HiAlert Interrupt Request Byte 64 Picture 6 1 WaterLevel value interrupts Picture 6 1 displays FIFO buffer stored data quantity and interrupt occurrence due to WaterLeve value Total of 64 bytes can be stored in FIFO LoA ert interrupt occurs when FIFO data is less than Waterleve specified value and HiA ert interrupt occurs when less space is available in FIFO then WaterLevel specified value Other occasions interrupt do not
45. occur www 3ALogics com Confidential 45 TRHO31M Datasheet Cha pte r7 Signal Integrity 7 1 Introduction VVireless communication has number of insecure elements Electromagnetic vvaves from other peripherals natural environment changes and other elements impact communication error Therefore all protocols contain methods to detect error and TRHO31M provides error correction methods by hardvvare 7 2 Signal Integrity Setting Method Table 7 1 Signal integrity check method by Protocol and its register setting method Protocol Type Redundancy Check Method CRCB Flag ParityOdd Flag ParityEn Flag ISO 14443A 16 bit CRC ISO 14443A Odd Parity DESSERTE 150144438 rebicecesonecs li 00170 iso 18693 Lesen 1 00 o son cacsonsa Fi Po o Table 7 1 tabularizes signal integrity checking method by protocol and its register setting methods CRCB flag of register REDUNDANCY 0x22 is a flag to activate CRC method ParityEn is a flag to determine parity check use ParityOdd flag determines to use Odd parity or Even Parity As seen on above table all protocols except ISO 14443A type do not use parity error check method and also CRC type use different format for 1SO 14443A type 46 Confidential www 3ALogics com TRHO31M Datasheet Table 7 2 REDUNDANCY register Address Reset Value 7 bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 bit REDUNDANCY 0x22 0x03 bit ERENS IE SIE IE CRCVVr
46. or verifies data received from TRHO31M Therefore microprocessor communicates with RFID tag through TRHO31M In other words TRHO31M provides wireless communication interface between microprocessor and RFID tag 12 Confidential www 3ALogics com TRH031M Datasheet 2 3 Role of TRHO31M 2 3 1 Modulation Demodulation a 13 56MHz carrier frequency modulated signal b Demodulated signal or modulation source Wa Picture 2 2 Modulation Demodulation Key functions of TRHO31M are modulation and demodulation Modulation is sending data through carrier as seen on picture 2 2 from B to A Demodulation is conversely receiving signal such as A on picture 2 2 by removing carrier and converting to B Therefore modulation occurs in transmit mode TX and demodulation occurs in receiving mode RX www 3ALogics com Confidential 13 TRHO31M Datasheet 2 3 2 Encoding Decoding l l Data 0 Subcarrier Modulated 1 Manchester Code l i Picture 2 3 is an example of ISO 14443A type tag and reader encoding decoding signal Encoding decoding process differs by different protocol used therefore detailed information 1 I b Data 0 Manchester Coding l I i should follovv standard specification Encoding is creating vvaveform Seen as picture 2 3 a or 2 3 c for data transmission and decoding is process of distinguishing 55 waveform Seen as
47. picture 2 3 a or picture 2 Manchester Codi ee 3 c as data O or data 1 First decoding process is as follows From analog part demodulation completed signal is d Data 1 Manchester Coding Picture 2 3 Encoding Decoding shaped as picture 2 3 a and picture 2 3 c As seen in picture 2 3 a and picture 2 3 c carrier is eliminated but subcarrier remains Thus eliminate subcarrier From picture 2 3 a to picture 2 3 b transformation process and picture 2 3 c to picture 2 3 d transformation process are subcarrier elimination process Eliminated subcarrier signal Seen as picture 2 3 b and picture 2 3 d will take shape of Manchester Coding TRHO31M digital part in the end finish the data decoding process by distinguishing the signal Picture 2 3 b as data 0 and Picture 2 3 d as data 1 In case of encoding conversely transmit data value stored in FIFO will impact the shape as seen on picture 2 3 a and picture 2 3 c All these processes will be performed automatically when user selects protocol type Confidential www 3ALogics com TRHO31M Datasheet 2 3 3 Framing s bi b2 b3 b4 b b b7 elei bt b2 b3 b4 b b b7 ve P e Start of Frame Data Parity Data End of Frame Picture 2 4 Framing Picture 2 4 displays ISO 14443A frame structure Framing means simply making frame Frame is data transmission unit in communication and word packet is used very frequently Frame
48. rent 7 8 10 uA TX1 2 disable clock on TX1 and TX2 unconnected 0 01 0 011 0 013 uA TX1 2 disable clock off lek Total Leakage current Power Down mode 0 19 0 23 0 3 uA Top Total Operating current Operating mode 86 107 128 mA 68 Confidential www 3ALogics com 13 3 Standard I O Pin DC characteristics TRHO31M Datasheet Conditions SYMBOL PARAMETER MIN MAX VDD Ha Guaranteed Input VIL Low level input voltage 0 5V 0 3 X VDD 2 7V to 3 6V Low Voltage e Guaranteed Input VIH High level input voltage 0 7 X VDD VDD 0 5V 2 7V to 3 6V High Voltage VOL Low level output voltage VSS 0 1V 2 7V VOH High level output voltage VDD 0 1V 2 7V 13 4 Schmitt Trigger Input Threshold VT VT Hysteresis gem ni MIN MAX TYP MIN MAX TYP MIN MAX TYP 1 39 2 06 1 82 0 9 1 46 1 24 0 49 0 6 0 58 V www 3ALogics com Confidential 69 TRHO31M Datasheet 13 5 Timing specification 13 5 1 Timing for Read Write Strobe SYMBOL PARAMETER MIN MAX UNIT tu PALE pulse width 10 ns AVL Multiplexed Address Bus Setup Time 4 ns LLAX Multiplexed Address Bus Hold Time 6 ns tuwi PALE low to WRB RDB low 5 ns taw CSB low to WRB RDB low 0 ns bauen VVRB NVVR high to CSB high 0 ns tripz RDB low to DATA valid 35 ns RHDZ RDB high to DATA high impedance 20 n
49. ress Reset BITFRAME 6 0 RxAlign Align bit for received data 3 TMaskFlag Used for Tag It protocol From SID Request command it is used when using Mask Bit and Mask Length value is stored in TxLastBits then selected Mask value from data stored in FIFO and transmitted to Tag It tag TxLastBits Use when transmitting less than a byte TxLastBits is a bit value for data to be transmitted TRHO31M can Transmit Receive data by bit level For bit level Transmit 7xlastBits flag of BITFRAME OXOF register is used and for bit level receiving RxA ign flag is used a FIFO Data Hexadecimal FIFO Data 74 03 b FIFO Data Binary 0111 0100 0000 0011 c Transmit Data When TxLastBits 3 1 2 3 4 5 6 7 8 9 A B 9 0111011 1 1 1 1 0 Y Y LSB of 74H MSB of 74H 7 End of Transmission Picture 5 5 Bit Level Transmit www 3ALogics com Confidential 37 TRHO31M Datasheet Above picture 5 5 displays bit level Transmit If FIFO stored data is same as picture 5 5 a data is tabularized in binary numbers as seen in picture 5 5 b If IxLastBits is set to 3 and Transmit command carries out then first byte 74 is all transmitted and second data 03 is transmitted up to 3 bits a Received Data Binary 0101011 1 011 0 0 1 1 011 11010 mm Start of Reception c FIFO
50. s bau mu VVRB lovv to DATA valid 35 ns twHDX DATA Bus Hold Time 6 ns twwH WRB RDB pulse width 41 ns AVVVL Separated Address Bus Setup Time 5 ns VVHAX Separated Address Bus Hold Time 6 ns twHwL Period between sequenced R W accesses 150 ns LHLL PALE taw 7 F ban T 13 T7 Diet VVRB hum twLwiT twawr RDB G Caen ees DATA twi DV EWEDX RLDV RHDZ twa Separated Addressbus Picture 13 1 Timing for Separated Read Write Strobe 70 Confidential www 3ALogics com 13 5 2 Timing for SPI compatible interface TRHO31M Datasheet SYMBOL PARAMETER MIN MAX UNIT tsckL SCK low pulse width 100 ns sckH SCK high pulse vvidth 100 ns supx SCK high to data changes 20 ns pxsu data changes to SCK high 20 ns tsLDX SCK low to data changes 15 ns TSLNE SCK low to NSS high 20 ns SCK MOSI MISO tseke tsckL tsckH Lane pxsu LSB sucH Ns a nu PICTURE 13 2 Timing for SPI compatible interface www 3ALogics com Confidential 71 TRHO31M Datasheet 13 6 Package Information
51. seccnnsessesecennsessasescnnsceseseecanseseeneseseaseets 34 5 3 2 Bit Level Receiving nee 34 5 4 ANTI COLLISION a 35 5 4 1 Collision Detection ensten trennsenrt bnn tons tba tenb stonne tnaa nanssre onen nnn 35 5 5 Bir LEVEL DATA TRANSMIT RECEIVE EN 37 5 6 T0 1e 00 AUS PR ee 39 5 6 1 ISO IEC 14443A Protocol a a 39 5 6 2 ISO IEC 14443B d r d S 41 CHAPTERG FIFO BUFFER issie esse ed es Se ee ede ee be ee eg Pe Se a a Mb sede bee dee be dese dees 43 6 1 INTRODUCTION aaa 93 o 43 6 2 FIFO BUFFER DATA INPUT OUTPUT c ccccscscsecessceescsescsucscscscsvscsusuessecscsesvsueasatacaevauessecscavavavssesusssavacseanesecasesecavaess 43 6 3 FIFO BUFFER RELATED FUNCTIONS ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee seasann nase 44 6 3 1 FIFO Buffer Data Deletion De ee ee ee ee ee ee ee ee ee ee ee 44 6 3 2 FIFO Butfer TEE EE ER OE nt 44 6 3 3 FIFO Buffer caused Interrupt Tiens 44 CHAPTER 7 SIGNAL INTEGRITY esse esse ee ees sesse ee ee ee ee ee Ge ee Ge ee Ge Ge ee ee Ge ee ee Gee 46 7 L INTRODU TION EE UR ree n Ge n Ge ER d si 46 7 2 SIGNAL INTEGRITY SETTING METHODEN 46 CHAPTERS INTERRUPT 0 Qggcccsssscsosscsscconscscsccrssscnccsensosenscaconcrsssccecssnscsensesscconssacnecsssscsensessccenssacseosens 49 GN Did elei ugi Of ER RE ER N N abad 49 8 2 INTERRUAT USE METHOD x5 N N AE 49 CHAPTERS POWER MANAGEMENT
52. t to 1 TX1 and TX2 modulation index is impacted by ModConductance of MODCONDUCTANCE 0x13 register value The role of ModConductance is to adjust driver conductance when TX1 and TX2 process modulation and impacts ASK modulation index changes Rj p channel resistance Table 11 6 MODCONDUCTANCE register Address Reset Value WEE ModConductance ModConductance Determine Modulation Conductance value between TX1 pin and TX2 pin Table 11 7 TX1 and TX2 modulation P channel resistance ModConductance R Ohm Table 11 7 is a table displaying TX1 and TX2 modulation P channel resistance Same as CwConductance when two or more bits are set ModConducatance also result in adding each Rp value in parallel Changes in Rp change modulation index but it is impacted by Rp value and matching circuit simultaneously therefore there can be minor changes based on matching methods Changes in modulation index due to ModConducatance value change please refer to TRHO3XM CookBook 11 3 4 Recognition Distance and Povver Consumption Recognition distance and povver consumption have proportional relationship As transmitter povver consumption increase recognition distance also increases Therefore there is a trade off betvveen Recognition distance and povver consumption User should consider this fact vvhen designing www 3ALogics com Confidential 61 TRHO31M Datasheet 11 4 Receiver Receiver execute converting 1
53. te all FIFO data and store data to be transmitted In PowerDown when set as value 1 the value stays the same However FlushFIFO TStopNow and 7StartNow commands clear to 0 automatically Table 4 4 CONTROL register Name Address Reset Value Po o o roveronn o Tsepn s s r n Fusero 4 PowerDown Setting value to 1 internal power consumption is minimized and remains waiting mode 2 TStopNow Setting this value to 1 will initiate timer count This value automatically changes to 0 1 TStartNow Setting this value to 1 will stop timer This value automatically changes to 0 0 FlushFIFO Delete all FIFO stored data This value automatically changes to 0 28 Confidential www 3ALogics com TRH031M Datasheet 4 5 Error Check ERRFLAG 0x0A register is a register to check error during transmit receiving If FIFO buffer data is full than F FOOvf flag changes to value 1 When FFOOvf occurs using FlushFIFO eliminates FIFO buffer data and AlFOOVv error clears automatically CRCErr displays CRC error during transmission and ParityErr displays parity error for ISO14443 type A These two value update automatically when Transceive command restart Co Err flag sets when Collision error occurs CollErr also as ParityErr and CRCErr automatically updates when command start For detailed information on Collision please refer to 5 4 Anti Collision and detailed information on ParityErr and CRCErr please refer to 7
54. ter can change by microprocessor Therefore user can set CRC operation initial value Table 7 5 CRCRESULTLSB register Address Reset Value CRCRESULTLSB 7 0 CRCResultLSB Store CRC calculation result LSB 8bit Table 7 6 CRCRESULTMSB register Address Reset CRCResultMSB CRCPRESETMSB 7 0 CRCResultMSB Store CRC calculation result MSB 8bit CRCRESULTLSB OXOD and CRCRESULTMSB 0x0E register are registers to store CRC calculation result CRCErr flag of ERRFLAG Ox0A register can be confirmed by microprocessor Also microprocessor uses CRCResu tLSB and CRCResultMSB to confirm error occurrence 48 Confidential www 3ALogics com TRH031M Datasheet C h a pte r8 Interrupt 8 1 Introduction TRHO31M supports various types of interrupt Using interrupt benefits for microprocessor to control TRHO31M First processing speed enhancement can be expected and second efficiency in microprocessor calculation If microprocessor controls more than 2 devices benefits of interrupt enhance TRH031M supports total of 6 interrupts and user can select choose to use any interrupt 8 2 Interrupt Use Method Table 8 1 IEN register Name Address Reset Value Senen o meng maer raen ite enter valent SetlEn 0 Clear Bit From 0 6 set marked bit as 0 EF 1 Set Bit 0 6 set marked bit as 1 TimerlEn O Not transfer TimerIRq interrupt signal to IRQ pin 1 Transfer TimerlRq interrupt signal to IRQ pin TxIEn
55. up Below table displays pin status during power down mode For optimum performance of power down mode entry pin must assign different value other than high Z Table 9 1 Pin assignment in power down mode Symbol T O Description a ELITE e T T coma pa of om m of omm Jee TUT m O WEER T m LLE EEN ENE EEN mee N omno SC ff e Dom ERC Do jeter RST ES Input High 52 Confidential www 3ALogics com TRHO31M Datasheet 9 3 Powerdown Mode Directions 9 3 1 Hardware PowerDown Mode Hardware power down mode is a method to minimize power consumption using TRHO31M RST pin TRHO31M activates power down mode when RST pin is 1 During power down mode TRHO31M internal main clock does not oscillate and needs some time after RST is given lovv value and to re activate It s because stopped oscillation to resume clock and to stabilize requires a certain time This required time is less than 500us 9 3 2 Software PowerDown Mode Software power down mode activates when CONTROL 0x09 register sets as PowerDown flag to 1 and during software power down mode all internal current consumption is minimized This process is actually the same as hardware power down mode In software power down mode host interface remains in action mode to release from power down mode Same as hardware power down mode in software power down mode clock does not oscillate www 3ALogics com Confidential 53 T
56. ure 8 1 displays IEN 0x06 register and IRQ 0x07 register setting method Picture 8 1 a displays register setting of bit value 1 and picture 8 1 b displays register bit setting of 0 From picture 8 1 a and b if first byte data is previous data before written 2nd byte is IEN 0x06 or IRQ 0x07 written data Lastly 3 byte changed value after it is written As seen on picture 8 1 when setting IEN Ox6 or IRQ 0x07 register as either 1 or O is determined by MSB then only bit 1 is changed and other bits maintains previous value Table 8 3 IRQCONFIG register Address Reset Value Ro o o o o o raw o Description Set Polarity of IRQ pin 0 Active High 1 when interrupt occurs 1 Active Low 0 when interrupt occurs IRQCONFIG 0x2D register is a register to set polarity of interrupt When RQInv is set to 1 IRQ pin maintains the value 1 during idle and changes to O when interrupt occurs When RQInv is set to 0 conversely IRQ pin maintains 0 value during idle mode and changes to 1 during interrupt occurrence www 3ALogics com Confidential 51 TRHO31M Datasheet Cha pte r9 Povver Management 9 1 Introduction TRHO31M provide power down mode to minimize power consumption User can minimize power consumption during reader chip idle mode using power down mode 9 2 Power down Mode Effect When power down mode is executed TRHO31M stops all devices consuming power and maintain idle until wake
57. ved in FIFO as 0 This function simplifies use of 1SO14443A Anti Collision data 1 data O a 14443A data 1 data O b 14443B data 1 data O c 15693 data 1 l data 0 c Tag It Picture 5 2 Receiver data format by protocol www 3ALogics com Confidential 33 TRHO31M Datasheet 5 3 1 Receive Delay Time RXVVATT 0x21 register is a register to set the delay time between begin receiving after Transmit ends Using RXVVATT 0x21 can block noise after Transmit Hovvever if delay time is set too long than may not able to receive response from tag thus set the proper value through testing Delay time is a value RxWa t multiplied by 128 fc Table 5 4 RXVVATT register Address Reset Value X X RxWait Setting the interval time after transmission before receiving 5 3 2 Bit Level Receiving Collision occurrence from tag during data receiving or if less than 1 byte data is received to display the number of normal received bits from last received bytes AxlastBits of STATUS register is used AxLastBits are in 3 bits and value are O when all bytes are Received normally 34 Confidential www 3ALogics com TRHO31M Datasheet 5 4 Anti Collision If multiple tags are in RF field all tags respond at same time and tag signals are mixed in RF field making it difficult to distinguish data Therefore reader must read tags in RF field sequentially In order to avoid tag
58. ytes are recognized as data From the picture data0 to data3 4bytes are written in address addr0 To execute write to other registers initialize NSS to High then change to Low and re enter address then write data byte 1 byte 2 byte 3 l byte 4 byte 5 Read NSS MOSI MISO Write NSS MOSI MISO Picture 3 4 SPI Command Structure 22 Confidential www 3ALogics com TRHO31M Datasheet In SPI communication determining whether it is Read or Write command depends on first byte of MSB If first byte of MSB is O then it is Write command and if 1 then it is Read command If MSB is bit 7 and LSB is bit 0 then Read Write is determined by MSB then address is located from bit6 bit1 Picture 3 5 is address structure for SPI communication a is first address of Read command Basically it is addrO of Read command in Picture 3 4 As explained above MSB value is 1 b is address format from addr1 to addr3 MSB and LSB are all RFU c is Write command address that is Write command addr0 in Picture 3 4 As explained above MSB value is 0 RFU is meaningless value and user can set it at his ovvn discretion Read a 1 address lt 5 0 gt Reu b RFU address lt 5 0 gt RFU Write EN address lt 5 0 gt RFU Picture 3 5 SPI Address Structure www 3ALogics com Confidential 23 TRHO31M Datasheet C ha pte r4 Command 4 1 Introduction TRHO3
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