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ANALOG DEVICES AD8331/AD8332/AD8334 Manual

1. 5 5 E 2 7 15 gt CLMP 2 E INPUT IS NOT TO SCALE 8 4 3 2 8 30 20 10 0 10 20 30 40 50 60 70 80 50 40 30 20 10 0 10 20 30 40 50 TIME ns TIME ns Figure 47 Clamp Level Pulse Response for 4 Values of Reme Figure 44 Large Signal Pulse Response for Various Capacitive Loads C OpF 10 pF 20 pF 50 pF 03199 048 Figure 48 LNA Overdrive Recovery 0 05 V to 1 V Burst Vean 0 27 V VGA Output Shown 03199 045 Figure 45 Pin GAIN Transient Response Top Vau Bottom Output Voltage Rev E Page 18 of 40 AD8331 AD8332 AD8334 03199 049 03199 052 Figure 49 VGA Overdrive Recovery 4 mV to 70 mV Burst Figure 52 Enable Response Large Signal Vean 1 VVGA Output Shown Attenuated by 24 dB Top Veng Bottom Vour 150 mV VPS1 Vean 0 5V m 2 x o 8 il 8 100 1M 10M 100M FREQUENCY Hz Figure 50 VGA Overdrive Recovery Vnu 4 mV to 275 mV Burst Figure 53 PSRR vs Frequency No Bypass Capacitor Vean 1 V VGA Output Shown Attenuated by 24 dB 140 VGAIN 0 5V 130 lt 90 gt o _ o m TP 9 50 b B o D 5 M 8 30 20 8 40 20 0 20 40 60 80 100 TEMPER
2. 25 Added Figure 71 Figure 72 and Figure 73 2222 26 Updated Outline Dimensions seen 31 2 03 Rev 0 to Rev A Edits to Ordering Guide sse 32 Rev E Page 3 of 40 AD8331 AD8332 AD8334 SPECIFICATIONS Ta 25 C Vs 5 V 500 Q Rs Rn 50 Res 280 Csu 22 f 10 MHz Ramp Cr 1 pin floating 4 5 dB to 43 5 dB gain HILO LO and differential output voltage unless otherwise specified Table 1 Parameter Conditions Min Max Unit LNA CHARACTERISTICS Gain Single ended input to differential output 19 dB Input to output single ended 13 dB Input Voltage Range AC coupled 275 mV Input Resistance Rrs 2800 50 Q Rr 4120 75 Q Rre 5620 100 Q 1 13 200 Q 6 Input Capacitance 13 pF Output Impedance Single ended either output 5 Q 3 dB Small Signal Bandwidth Vout 0 2 V p p 130 MHz Slew Rate 650 V us Input Voltage Noise Rs 0 HI or LO gain eo f 5 MHz 0 74 nV 4Hz Input Current Noise eo or LO gain f 5 MHz 2 5 pA VHz Noise Figure f 10 MHz LOP output Active Termination Match Rs 500 3 7 dB Unterminated Rs 50 2 5 dB Harmonic Distortion LOP1 or LOP2 Vout 0 5 V single ended f 10 MHz HD2 56 dBc HD3 70 dBc Output Short Circuit Current Pin LON Pin LOP 165 mA LNA VGA CHARACTERISTICS 3 dB S
3. 32 32 Optional Input Overload Protection 33 Layout Grounding and 33 Multiple Input Matching 33 Disabling the LNA Sc espe 33 Ultrasound TGC Application sse 34 High Density Quad Layout 34 O tline DimensioTiss eine irte t Reiten 39 Ordering Guide eee bets 40 Rev E Page 2 of 40 AD8331 AD8332 AD8334 REVISION HISTORY 4 06 Rev D to Rev E 833 setenta dte Universal Changes to Figure 1 and Figure 2 sss 1 Changes to Table 1 24 tope rite et o bee 7 Changes to Figure 7 through Figure 9 and Figure 12 12 Changes to Figure 13 Figure 14 Figure 16 and Figure 18 13 Changes to Figure 23 and Figure 24 sss 14 Changes to Figure 25 through Figure 27 sss 15 Changes to Figure 31 and Figure 33 through Figure 36 16 Changes to Figure 37 through 2 17 Changes to Figure 43 Figure 44 and Figure 48 18 Changes to Figure 49 Figure 50 and Figure 54 19 Inserted Figure 56 and Figure 57 20 Inserted Figure 58 Figure 59 and Figure 61 21 Changes to Figure 60 nene 21 Inserted Figure 63 and Figure 65 22 Charges to Figure GA oroesi
4. 5V C31 C22 C21 3 0 1pF d 1nF C2 10uF RE 6 3V AGND AVDD C30 R5 330 VIN A CLK A 120nH FB Vig w VIN SHARED REF 330 4 7kQ C29 AGND SELECT 0 1uF C17 C18 3 3VADDIG C33 0 1HF MERE E AVDD PDWN A V C35 10 12 120nH 0 1 6 5V He lt H cu REFT A OEB A A 10nF T 0 1 TV REFB A OTR A OTR A our a VREF D11_A MSB Di1A VREF c32 tl 12 D 10pF SENSE 010 A D10 A 0 1 Pen 10 L 4 3 REFB B D9 A D9 A amp s Tour D8 A C37 EM 43 3VADDIG 0 1 AVDD DRGND cie_L c15 8 C23 C25 d TET 13 AGND DRVDD D V 7 330 14 DA D7 A ui B gt D6 A D6 A 3 3VCLK AGND DSA D5 A R18 a 52 C63 4990 AVDD d D4A D4 A EXTCLOCK RIE DMA D3 A R17 R19 DCS D2 A 02 DFS 01 Di A Rol mal 5 5 PDWN_B V V Y 43 3 VCLK DNC DNC DNC DNC DNC ADCLK 24 P DNC DRVDD aL ott 05 2 9 25 Ao fnF h 74VHC04 74VHC04 RQ 0 B E DRGND 6 3V 00 3 gt 1 gt 2 1_ 2 p1 OTR B 27 TPA ara D2_B D11_B MSB D11_B U5 U5 O 28 74VHC04 74VHC04 CLK L D10_B D10_B U6 5 6 9 8 3 29 SG 636PCE gt gt Ts o 09 B 09 JP1 D3 B 74VHC04 D8 B D8 B us m D7 B D7 B D6 B D6 B
5. SPARES 3 3VADDIG US C26 C24 74VHC04 0 TuF Vr Figure 92 Converter Schematic TGC Using an AD8332 and AD9238 03199 092 Rev E Page 36 of 40 AD8331 AD8332 AD8334 DATACLKA U10 vcc T m 3 3VDVDD 74 541 C28 0 1 10 6 3V 22 4 H OTR A D11 A 5 010 A 4 1 8 09 A 22 4 2 RP10 08 A 6 gt 15 07 g 4 5 A 06 A c 17 gt z o 3 3VDVDD 5 07 5 G1 5 74VHC541 C8 c10 cre G2 0 1 0 10 A 6 3V DS A 2252 A N IS IN ar jo 1 8 Di A 22x4 2 RP 12 7 DO A AM 3 6 DNC SAM080UPM 4 5 3 3VDVDD 1 92 vocc 41 74VHC541 lco 1 27 ACC pour jour 10pF RP13 6 3V OTR B WW 010 B v 1253 14 ls 2 H 53 2 E 07 B m DeB jan 3 D5 B a 2 o 15 G1 VCC 5 7 541 4 C5 C6 C75 67 gt 4 D2_B Di B 1 22 4 8 Dc ANN 2 RP 16 1 r amp K w SAMO80UPM 8 DATACLK Figure 93 Interface Schematic TGC Using an
6. Rfg 9 SIMULATION 03199 077 50 100 1k Rg Q Figure 77 Noise Figure vs Rs for Various Fixed Values of Ry Actively Matched Rev E Page 26 of 40 AD8331 AD8332 AD8334 The primary purpose of input impedance matching is to improve the system transient response With resistive termination the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the input voltage noise generator With active impedance matching however the contributions of both are smaller than they would be for resistive termination by a factor of 1 1 LNA Gain Figure 76 shows their relative noise figure NF performance In this graph the input impedance was swept with Rs to preserve the match at each point The noise figures for a source impedance of 50 are 7 1 dB 4 1 dB and 2 5 dB respectively for the resistive active and unterminated configurations The noise figures for 200 are 4 6 dB 2 0 dB and 1 0 dB respectively Figure 77 is a plot of the NF vs Rs for various values of Ruy which is helpful for design purposes The plateau in the NF for actively matched inputs mitigates source impedance variations For comparison purposes a preamp with a gain of 19 dB and noise spectral density of 1 0 nV VHz combined with a VGA with 3 75 nV VHz yields a noise figure degradation of approximately 1 5 dB for most input impedances significantly worse than th
7. APPLICATIONS LNA EXTERNAL COMPONENTS The LMD pin connected to the bias circuitry must be bypassed to ground and signal sourced to the INH pin capacitively coupled using 2 2 nF to 0 1 capacitors see Figure 81 The unterminated input impedance of the LNA is 6 The user can synthesize any LNA input resistance between 50 and 6 Res is calculated according to Equation 6 or selected from Table 7 33 kO x Ry EB uxo RS 6 6kQ Table 7 LNA External Component Values for Common Source Impedances Rin Rre Nearest STD 1 Value pF 50 280 22 75 412 12 100 562 8 200 1 13k 1 2 500 3 01k None 6k None When active input termination is used a decoupling capacitor Crs is required to isolate the input and output bias voltages of the LNA The shunt input capacitor reduces gain peaking at higher frequencies where the active termination match is lost due to the gain roll off of the LNA at high frequencies The value of diminishes as Rm increases to 500 at which point no capacitor is required Suggested values for 50 Q lt Rw lt 200 are shown in Table 7 When a long trace to Pin INH is unavoidable or if both LNA outputs drive external circuits a small ferrite bead FB in series with Pin INH preserves circuit stability with negligible effect on noise The bead shown is 75 at 100 MHz Murata BLM21 or equivalent Other values can pro
8. LON2LOP2 VIP2 ENB VCM2 Figure 70 AD8332 Functional Block Diagram 03199 070 SIGNAL PATH 3 5dB 15 5dB INH LMD BIAS AND INTERPOLATOR 03199 072 Figure 72 Simplified Block Diagram Rev E Page 24 of 40 AD8331 AD8332 AD8334 The linear in dB gain control interface is trimmed for slope and absolute accuracy The gain range is 48 dB extending from 4 5 dB to 43 5 dB in HI gain and 7 5 dB to 55 5 dB in LO gain mode The slope of the gain control interface is 50 dB V and the gain control range is 40 mV to 1 V Equation 1 and Equation 2 are the expressions for gain GAIN dB 50 dB V x Vaam 6 5 dB HILO LO 1 or GAIN dB 50 dB V x Vaam 5 5 dB HILO LO 2 The ideal gain characteristics are shown in Figure 73 GAIN dB ASCENDING GAIN MODE DESCENDING GAIN MODE WHERE AVAILABLE 03199 073 0 0 2 0 4 0 6 0 8 1 0 1 1 Vean V Figure 73 Ideal Gain Control Characteristics The gain slope is negative with the MODE pulled high where available GAIN dB 50 dB V x Vean 45 5 dB HILO LO 3 or GAIN dB 50 dB V x 57 5 dB HILO HI 4 The LNA converts a single ended input to a differential output with a voltage gain of 19 dB If only one output is used the gain is 13 dB The inverting output is used for active input impedance termination Each of the LNA outputs is capacitiv
9. Page 12 of 40 AD8331 AD8332 AD8334 60 Vean 1V 1V p p 50 Vear 0 8V T 40 ey Vear 1 0V GAIN U AD8332 Vear 0 7V E SAN 4 Vear 0 4V Vear 0 4 x E lt 20 9 x 5 10 0 e 10 8 8 100k 1M 10M 100M 500M 100M FREQUENCY Hz FREQUENCY Hz Figure 13 Frequency Response for Various Values of Vau HILO Figure 16 Channel to Channel Crosstalk vs Frequency for Various Values of Veain Vean 0 5V gt 8 5 B 2 5 o 100k 1M 10M 100M 500M 10M 100M FREQUENCY Hz FREQUENCY Hz Figure 14 Frequency Response for Various Matched Source Impedances Figure 17 Group Delay vs Frequency for Two Values of AC Coupling Vean 0 5V T 85 C gt g g gt lt gt 9 10 20 u T 85 C 5 T 25 Bl 5 gt T 40 30 8 100 1M 10M 100M 500M 0 01 02 03 04 05 06 07 08 09 10 141 FREQUENCY Hz Vean V Figure 15 Frequency Response Unterminated LNA Rs 50 Figure 18 R
10. 4 5 dB to 43 5 dB gain HILO LO and differential output voltage unless otherwise specified 60 SAMPLE SIZE 80 UNITS 50 40 E N ES 5 2 2 10 A lt HILO LO 1 0 ASCENDING MODE DESCENDING GAIN MODE _ _ _ WHERE AVAILABLE 8 0 0 2 0 4 0 6 0 8 1 0 1 1 0 5 04 0 3 02 0 1 0 01 02 0 3 04 0 5 Vean V GAIN ERROR dB Figure 7 Gain vs Vean and MODE MODE Available on AC Package Figure 10 Gain Error Histogram SAMPLE SIZE 50 UNITS Vean 0 2 z p 5 9 2 lt 0 0 2 0 4 0 6 0 8 10 1 1 O O O O O O O O O O O O O O O O V n CHANNEL TO CHANNEL GAIN MATCH dB Figure 8 Absolute Gain Error vs Vea at Three Temperatures Figure 11 Gain Match Histogram for Vesan 0 2 V and 0 7 V 50 Vean 1V 40 Vean 0 8V 50 Vear 0 6 T GAIN 0 Z x 2 9 Vear 0 4V lt 10 2 Vear 0 2V lt 0 OV 4 10 E 8 20 8 0 0 2 0 4 0 6 0 8 1 0 1 1 100 1M 10M 100M 500M Vear V FREQUENCY Hz Figure 9 Absolute Gain Error vs Various Frequencies Figure 12 Frequency Response for Various Values of Vea Rev E
11. BEAD 120nH 0 1HF 2370 280 2370 280 E 8 8 5 OSCILLOSCOPE Figure 66 Pulse Response Measurements FERRITE BEAD 120nH 0 1 soo 22PF I RF 3 SIGNAL 0 1uF 0 1uF 2550 GENERATOR I TO PIN GAIN OR ENxx PULSE GENERATOR 8 Figure 67 GAIN and Enable Transient Response NETWORK ANALYZER FERRITE BEAD DIFF PROBE 120nH PROBE POWER 500 E SIGNAL 0 1uF I 0 1 2550 GENERATOR 1 03199 068 Figure 68 PSRR vs Frequency Rev E Page 23 of 40 AD8331 AD8332 AD8334 THEORY OF OPERATION OVERVIEW The following discussion applies to all part numbers Figure 69 CLMP12 Figure 70 and Figure 71 are functional block diagrams of the AD8331 AD8332 and AD8334 respectively LON LOP VIP VIN HILO VGA BIAS AND GAIN INTERPOLATOR GAIN12 ATTENUATOR _ 1 03199 069 ATTENUATOR _ 48dB LI LOP4 VINA EN34 VCM4 Figure 71 AD8334 Functional Block Diagram 03199 071 INTERPOLATOR Each channel contains an LNA that provides user adjustable input impedance termination a differential X AMP VGA anda AD8332 RCLMP programmable gain postamplifier with adjustable output voltage limiting Figure 72 shows a simplified block diagram with external components
12. 089 Figure 89 Disabling the LNA Rev E Page 33 of 40 AD8331 AD8332 AD8334 ADG736 1 13 S 4 SELECT Rep C9 03199 090 Figure 90 Accommodating Multiple Sources ULTRASOUND TGC APPLICATION The AD8332 ideally meets the requirements of medical and industrial ultrasound applications The TGC amplifier is a key subsystem in such applications because it provides the means for echolocation of reflected ultrasound energy Figure 91 through Figure 93 are schematics of a dual fully differential system using the AD8332 and the AD9238 12 bit high speed ADC with conversion speeds as high as 65 MSPS Using the EVAL AD8332 AD9238 evaluation board and a high speed ADC FIFO evaluation kit connected to a laptop an FFT can be performed on the AD8332 With the on board clock of 20 MHz minimal low pass filtering and both channels driven with a 1 MHz filtered sine wave the THD is 75 dB noise floor is 93 dB and HD2 is 83 dB HIGH DENSITY QUAD LAYOUT The AD8334 is the ideal solution for applications with limited board space Figure 94 represents four channels routed to and away from this very compact quad VGA Note that none of the signal paths crosses and that all four channels are spaced apart to eliminate crosstalk In this example all of the components shown are 0402 size however the same layout is executable at the expense of slightly more board area The sketch also assumes that both sides of the
13. 1000 E s 1 Rin 2000 2 90 1 SIMULATION 0 1 8 0 8 0 0 2 0 4 0 6 0 8 1 0 50 100 1k Vean V SOURCE RESISTANCE Q Figure 27 Short Circuit Input Referred Noise vs Vau Figure 30 Noise Figure vs Rs for Various Values of Rin Rev E Page 15 of 40 AD8331 AD8332 AD8334 PREAMP LIMITED f 10MHz Rg 500 f 10MHz Vout 1V p p m m a z 5 5 u E 9 u a a HILO LO Rpg lt HILO HI Rin 0 0 1 02 03 04 05 06 07 08 0 9 10 14 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Vean V RLoap Figure 31 Noise Figure vs Figure 34 Harmonic Distortion vs Rioap m m 2 5 u 5 5 a BN serm AN AN 2 9 9 HILO HI HD3 lt 0 10 20 30 40 50 GAIN dB PF Figure 32 Noise Figure vs Gain Figure 35 Harmonic Distortion vs 20 f 10MHz GAIN 30dB m 5 a m z HILO LO HD3 6 HILO LO HD2 z S 7 0 E 5 o o 7 7 o Ke Jj MILOS HU HD HILO HI HD3 o 80 lt 7 4 u 100 8 8 0 1 2 3 4 Vout V FREQUENCY Hz Figure 36 Harmonic Distortion vs Differential Output Voltage Figure 3
14. FREQUENCY Hz 100M 500M 03199 024 15 100k 1M 00M 500M FREQUENCY Hz Figure 24 Frequency Response for Unterminated LNA Single Ended AD8331 AD8332 AD8334 500 1 00 Rs 0 Reg 9 0 95 1V f 10MHz N 400 0 90 gt 0 85 5 300 gt 0 80 2 Losan 2888 HI GAIN 408331 200 070 2 x a Z 0 65 2 E 100 0 60 o 8 0 55 8 0 3 0 50 3 50 Vean V TEMPERATURE C Figure 25 Output Referred Noise vs Vea Figure 28 Short Circuit Input Referred Noise vs Temperature Rs 0 9 Vean 1V 10 HILO LO OR HI f 5MHz Reg Vea 1V N z m gt 9 P 5 2 z 2 77 2 Rg THERMAL NOISE 400k 1M 10M 100M 0 1 8 FREQUENCY Hz 1 10 100 1k Figure 26 Short Circuit Input Referred Noise vs Frequency SOURCE RESISTANCE 0 Figure 29 Input Referred Noise vs Rs 100 Rs 0 Reg 9 HILO LO OR HI f 10MHz INCLUDES NOISE OF VGA 6 E s 500 10 8 IN 4 5 Ry 750 a o ir z u 3 Rin
15. VOL4 LMD3 VOH4 INH3 COM34 f s toc 35539522 885363 gt gt 2 99 8 8 lt Figure 6 64 Lead LFCSP Pin Configuration AD8334 Table 6 64 Lead LFCSP Pin Function Description AD8334 Pin No Mnemonic Description 1 INH2 CH2 LNA Input 2 LMD2 CH2 LNA Vu Bypass AC Coupled to GND 3 COM2X CH2 LNA Ground Shield 4 LON2 CH2 LNA Feedback Output for 5 LOP2 CH2 LNA Output 6 VIP2 CH2 VGA Positive Input 7 VIN2 CH2VGA Negative Input 8 VPS2 CH2 LNA Supply 5 V 9 VPS3 CH3 LNA Supply 5 V 10 VIN3 CH3VGA Negative Input 11 VIP3 CH3 VGA Positive Input 12 LOP3 CH3 LNA Positive Output 13 LON3 CH3 LNA Feedback Output for 14 COM3X CH3 LNA Ground Shield 15 LMD3 CH3 LNA Bypass AC Coupled to GND 16 INH3 CH3 LNA Input 17 COM3 CH3 LNA Ground 18 COM4 CH4 LNA Ground 19 INHA CH4 LNA Input 20 LMD4 CH4 LNA Bypass AC Coupled to GND 21 COM4X CH4 LNA Ground Shield 22 LON4 LNA Feedback Output for 23 LOP4 CH4 LNA Positive Output 24 VIP4 CH4 VGA Positive Input 25 VIN4 CHAVGA Negative Input 26 VPS4 CH4 LNA Supply 5 V 27 GAIN34 Gain Control Voltage for CH3 and CH4 28 CLMP34 Output Clamping Level Input for CH3 and CH4 Rev E Page 10 of 40 AD8331 AD8332 AD8334 Pin No Mnemonic Description 29 HILO Gain Select for Postamp 0 dB 12 dB 30 VCM4 CH4 Common Mode Voltage
16. in Figure 87 summarizes the combinations of input signal and gain that lead to the different types of overload POSTAMP X AMP POSTAMP X AMP OVERLOAD OVERLOAD OVERLOAD OVERLOAD 43 5 15mV 25mV 56 5 4mV 25mV 29dB T 24 598 24 5dB LO GAIN gt GAIN MODE MODE 9 9 74 gt gt lt lt 2 2 4 5 7 5 1 1 10m 0 1 0 275 1 1m 10m 01 0275 1 03199 087 INPUT AMPLITUDE V INPUT AMPLITUDE V Figure 87 Overload Gain and Signal Conditions The previously mentioned clamp interface controls the maximum output swing of the postamp and its overload response When the clamp feature is not used the output level defaults to approximately 4 5 V p p differential centered at 2 5 V common mode When other common mode levels are set through the VCM pin the value of Rcuw should be selected for graceful overload A value of 8 3 or less is recommended for 1 5 V or 3 5 V common mode levels 7 2 for HI gain mode This limits the output swing to just above 2 V p p differential Rev E Page 32 of 40 AD8331 AD8332 AD8334 OPTIONAL INPUT OVERLOAD PROTECTION Applications in which high transients are applied to the LNA input can benefit from the use of clamp diodes A pair of back to back Schottky diodes can reduce these transients to manageable levels Figure 88 illustrates how such a diode protection scheme can be connected OPTIONAL SCHOTTKY OVERLOAD CLAMP r
17. range and output noise for 12 bit or 10 bit converter applications The output can be limited to a user selected clamping level preventing input overload to a subsequent ADC An external resistor adjusts the clamping level The operating temperature range is 40 to 85 C The AD8331 is available in a 20 lead QSOP package the AD8332 is available in 28 lead TSSOP and 32 lead LFCSP packages and the AD8334 is available 64 lead LFCSP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD8331 AD8332 AD8334 TABLE OF CONTENTS Features cnet STD aeRO NR E Ee 1 1 General Description 1 Functional Block Diagram senten 1 RevIiSIOTETITIS 3 SPECI CALI ONS er ua RM EU Rer iut eene eodd 4 Absolute Maximum 7 ESD Caution teretes 7 Pin Configurations and Function Descriptions 8 Typical Performance Characteristics 12 icit 20 Measurement 20 Theory of Operation 24 OVERVIEW 24 Low Noise Amplifier 25 Variable Gain Amplifier 27 Postaniplifiet oce ete Oe e Se 28 Applications a y nu nus 30 LNA External 30 Driving ADCS
18. the differential gain magnitude is 9 the maximum input signal before saturation is 275 mV or 550 mV p p Overload protection ensures quick recovery time from large input voltages Because the inputs are capacitively coupled to a bias voltage near midsupply very large inputs can be handled without interacting with the ESD protection Low value feedback resistors and the current driving capability of the output stage allow the LNA to achieve a low input referred voltage noise of 0 74 nV VHz This is achieved with a current consumption of only 11 mA per channel 55 mW On chip resistor matching results in precise single ended gains of 4 5x 9x differential critical for accurate impedance control The use of a fully differential topology and negative feedback minimizes distortion Low HD2 is particularly important in second harmonic ultrasound imaging applications Differential signaling enables smaller swings at each output further reducing third order distortion Rev E Page 25 of 40 AD8331 AD8332 AD8334 Active Impedance Matching The LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH The input resistance Rm is given by Equation 5 where A is the single ended gain of 4 5 and 6 is unterminated input impedance E 6 6 kO x Ry 5 1 33 Rep is needed in series with Res because the dc levels at Pin LON and Pin INH are unequa
19. 3 Harmonic Distortion vs Frequency Rev E Page 16 of 40 AD8331 AD8332 AD8334 0 Savi Vout 1V COMPOSITE ff f2 Vout 1V 20 INPUT RANGE gt LIMITED WHEN g 0 HILO Lo 5 5 8 O 8 o 80 100 8 i 120 8 8 0 01 0 2 03 04 05 06 07 08 09 1 0 100M Vean V FREQUENCY Hz Figure 37 Harmonic Distortion vs Vean f 1 MHz Figure 40 IMD3 vs Frequency 10MHz HILO HI Vout 1V p p INPUT RANGE LIMITED WHEN m HILO LO 5 5 S 5 5 e 5 8 5 0 01 0 2 03 04 05 06 07 08 09 1 0 0 01 02 03 04 05 06 07 08 09 10 Veain V Vean V Figure 38 Harmonic Distortion vs Vea f 10 MHz Figure 41 Output Third Order Intercept vs m x gt 0 01 02 03 04 05 06 07 08 09 1 0 Vaan V Figure 42 Small Signal Pulse Response 30 Figure 39 Input 1 dB Compression vs Top Input Bottom Output Voltage HILO HI or LO Rev E Page 17 of 40 AD8331 AD8332 AD8334 Vout V 03199 043 03199 046 0 5 10 15 20 25 30 35 40 45 50 Figure 43 Large Signal Pulse Response 30 dB Figure 46 Clamp Level vs Ramp HILO HI or LO Top Input Bottom Output Voltage
20. 334ACPZ REEL7 409 to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP VQ CP 64 1 AD8334 EVAL Evaluation Board with AD8334ACP 17 Pb free part 2006 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners C03199 0 4 06 E s Rev E Page 40 of 40
21. AC Bypass 31 VCM3 CH3 Common Mode Voltage AC Bypass 32 NC No Connect 33 COM34 VGA Ground CH3 and CH4 34 VOH4 Positive VGA Output 35 VOL4 CH4 Negative VGA Output 36 VPS34 VGA Supply 5V CH3 and CH4 37 VOL3 CH3 Negative VGA Output 38 VOH3 Positive VGA Output 39 COM34 VGA ground CH3 and CH4 40 NC No Connect 41 MODE Gain Control SLOPE Logic Input 0 Positive 42 COM12 VGA Ground CH1 and CH2 43 VOH2 CH2 Positive VGA Output 44 VOL2 CH2 Negative VGA Output 45 VPS12 CH2 VGA Supply 5 V CH1 and CH2 46 VOL1 CH1 Negative VGA Output 47 VOH1 CH1 Positive VGA Output 48 COM12 VGA Ground CH1 and CH2 49 VCM2 CH2 Common Mode Voltage AC Bypass 50 VCM1 CH1 Common Mode Voltage AC Bypass 51 EN34 Shared LNA VGA Enable CH3 and CH4 52 EN12 Shared LNA VGA Enable CH1 and CH2 53 CLMP12 Output Clamping Level Input CH1 and CH2 54 GAIN12 Gain Control Voltage CH1 and CH2 55 VPS1 CH1 LNA Supply 5 V 56 VIN1 CH1 VGA Negative Input 57 VIP 1 CH1 Positive Input 58 LOP1 CH1 LNA Positive Output 59 LON1 LNA Feedback Output for 60 COM1X CH1 LNA Ground Shield 61 LMD1 CH1 LNA Bypass AC Coupled to GND 62 INH1 CH1 LNA Input 63 1 CH1 LNA Ground 64 COM2 CH2 LNA Ground Rev E Page 11 of 40 AD8331 AD8332 AD8334 TYPICAL PERFORMANCE CHARACTERISTICS Ta 25 C Vs 5 V 500 Rs Rn 50 Res 280 Csu 22 pE f 10 MHz Ramp Cr 1 pin floating
22. AD8332 and AD9238 Rev Page 37 of 40 AD8331 AD8332 AD8334 AD8334 POWER SUPPLY DECOUPLING LOCATED ON WIRING SIDE Figure 94 Signal Path and Board Layout for AD8334 Rev E Page 38 of 40 CH 1 DIFFERENTIAL OUTPUT 2 DIFFERENTIAL OUTPUT CH 3 DIFFERENTIAL OUTPUT CH 4 DIFFERENTIAL OUTPUT 03199 094 AD8331 AD8332 AD8334 OUTLINE DIMENSIONS 9 80 0 345 6 40 BSC 0 065 0 069 0 049 0 053 gt m o gt e 8 0 010 8 LM gt 0 20 T 245 75 0 004 2 025 0 012 SEATING 0 0 050 COPLANARITY 0 19 SEATING 0 09 BSC 0 008 PLANE 0 010 0 016 0 10 PLANE 0 45 COPLANARITY 0 006 0 004 COMPLIANT TO JEDEC STANDARDS MO 153 AE COMPLIANT TO JEDEC STANDARDS MO 137 AD Figure 95 28 Lead Thin Shrink Small Outline Package TSSOP Figure 96 20 Lead Shrink Small Outline Package QSOP RU 28 RQ 20 Dimensions shown in millimeters Dimensions shown in Inches 0 60 0 60 BINA INDICATOR PIN 1 INDICATOR 0 50 BSC EXPOSED 3 25 PAD 10 SQ BOTTOM VIEW 295 0 50 0 40 0 30 4 0 25 3 50 REF 5 0 65 TYP THE EXPOSE PAD IS NOT CONNECTED INTERNALLY FOR INCREASED RELIABILITY 0 05 MAX OF THE SOLDER JOINTS AND MAXIMUM 1 00 ae T 0 02 NOM THERMAL CAPABILITY IT IS RECOMMENDED TH
23. ANALOG DEVICES Ultralow Noise VGAs with Preamplifier and Programmable Rin AD8331 AD8332 AD8334 FEATURES Ultralow noise preamplifier Voltage noise 0 74 nV VHz Current noise 2 5 pA VHz 3 dB bandwidth AD8331 120 MHz AD8332 AD8334 100 MHz Low power AD8331 125 mW channel AD8332 AD8334 145 mW channel Wide gain range with programmable postamp 4 5 dB to 43 5 dB 7 5 dB to 55 5 dB Low output referred noise 48 nV VHz typical Active input impedance matching Optimized for 10 bit 12 bit ADCs Selectable output clamping level Single 5 V supply operation AD8332 and AD8334 available in lead frame chip scale package APPLICATIONS Ultrasound and sonar time gain controls High performance AGC systems signal processing High speed dual ADC drivers GENERAL DESCRIPTION The AD8331 AD8332 AD8334 are single dual and quad channel ultralow noise linear in dB variable gain amplifiers VGAs Optimized for ultrasound systems they are usable as a low noise variable gain element at frequencies up to 120 MHz Included in each channel are an ultralow noise preamplifier LNA an VGA with 48 dB of gain range and a selectable gain postamplifier with adjustable output limiting The LNA gain is 19 dB with a single ended input and differential outputs Using a single resistor the LNA input impedance can be adjusted to match a signal source without compromising noise performance The 48 dB gain range of the VGA m
24. AT THE PAD BE SOLDERED 245 N P COPLANARITY THE GROUND PLANE 0 8 P 23 0 20 REF 0 08 SEATING PLANE 0 18 041806 A COMPLIANT TO JEDEC STANDARDS MO 220 VHHD 2 Figure 97 32 Lead Lead Frame Chip Scale Package LFCSP_VQ 5mmx5mm Body Very Thin Quad CP 32 2 Dimensions shown in millimeters Rev E Page 39 of 40 AD8331 AD8332 AD8334 PIN 1 INDICATOR 4 70 4 55 BOTTOM VIEW L 7 50 15 INTERNALLY FOR INCREASED RELIABILITY 1 00 12 MAX 550 OF THE SOLDER JOINTS AND MAXIMUM s HE STe HCl TO ENDED 0 80 11 002 THE GROUND PLANE L TIHHHHHHHHHHHHHHHIL 0 02 NOM y SEATING 0 50 Bsc PLANE 0 20 REF lt COMPLIANT JEDEC STANDARDS MO 220 VMMD 4 E EXCEPT FOR EXPOSED PAD DIMENSION 8 Figure 98 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 9 mm x 9 mm Body Very Thin Quad CP 64 1 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8331ARQ 40 to 85 C 20 Lead Shrink Small Outline Package QSOP RQ 20 AD8331ARQ REEL 40 to 85 C 20 Lead Shrink Small Outline Package QSOP RQ 20 AD8331ARQ REEL7 40 to 85 C 20 Lead Shrink Small Outline Package QSOP RQ 20 AD8331ARQZ 40 to 85 C 20 Lead Shrink Small Outline Package QSOP RQ 20 AD8331ARQZ R
25. ATURE C Figure 51 Enable Response Vens Bottom 30 mV Figure 54 Quiescent Supply Current vs Temperature Rev E Page 19 of 40 AD8331 AD8332 AD8334 TEST CIRCUITS MEASUREMENT CONSIDERATIONS Short circuit input noise measurements are made using Figure 62 The input referred noise level is determined by dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer The gain should be measured at each frequency of interest and with low signal levels because a 50 load is driven directly The generator is removed when noise measurements are made Figure 55 through Figure 68 show typical measurement configurations and proper interface values for measurements with 50 conditions NETWORK ANALYZER FERRITE BEAD 120nH 03199 055 Figure 55 Gain and Bandwidth Measurements NETWORK ANALYZER 18nF FERRITE BEAD 2370 10kO 120nH 0 1uF yn t 280 1 1 P3 2370 0 1 l 0 1 L 280 03199 056 Figure 56 Frequency Response for Various Matched Source Impedances NETWORK ANALYZER FERRITE 03199 057 Figure 57 Frequency Response for Unterminated LNA Rs 50 Q Rev E Page 20 of 40 AD8331 AD8332 AD8334 NETWORK ANALYZER 18 10kQ FERRITE 0 1yF BEAD AND 120nH 10 10 280 03199 058 Figure 58 Group Delay vs F
26. Although the LNA noise performance is the same in single ended and differential applications the VGA performance is not The noise of the VGA is significantly higher in single ended usage because the contribution of its bias noise is designed to cancel in the differential signal A transformer can be used with single ended applications when low noise is desired Gain control noise is a concern in very low noise applications Thermal noise in the gain control interface can modulate the channel gain The resultant noise is proportional to the output signal level and usually only evident when a large signal is present Its effect is observable only in LO gain mode where the noise floor is substantially lower The gain interface includes an on chip noise filter which reduces this effect significantly at frequencies above 5 MHz Care should be taken to minimize noise impinging at the GAIN input An external RC filter can be used to remove Vaam source noise The filter bandwidth should be sufficient to accommodate the desired control bandwidth Common Mode Biasing An internal bias network connected to a midsupply voltage establishes common mode voltages in the VGA and postamp An externally bypassed buffer maintains the voltage The bypass capacitors form an important ac ground connection because the VCM network makes a number of important connections internally including the center tap of the differential input attenuator the feedb
27. B steps The input stages of the X AMP are distributed along the ladder and a biasing interpolator controlled by the gain interface determines the input tap point With overlapping bias currents signals from successive taps merge to provide a smooth attenuation range from 0 dB to 48 dB This circuit technique results in excellent linear in dB gain law conformance and low distortion levels and deviates 0 2 dB or less from the ideal The gain slope is monotonic with respect to the control voltage and is stable with variations in process temperature and supply The X AMP inputs are part of a gain of 12 feedback amplifier that completes the VGA Its bandwidth is 150 MHz The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across gain setting see Figure 12 and Figure 13 Gain Control Position along the VGA attenuator is controlled by a single ended analog control voltage Vaam with an input range of 40 mV to 1 0 V The gain control scaling is trimmed to a slope of 50 dB V 20 mV dB Values of Vcam beyond the control range saturate to minimum or maximum gain values Both channels of the AD8332 are controlled from a single gain interface to preserve matching Gain can be calculated using Equation 1 and Equation 2 Gain accuracy is very good because both the scaling factor and absolute gain are factory trimmed The overall accuracy relative to the theoretical gain expres
28. CH2 Common Mode Voltage 14 COMM VGA Ground Both Channels 14 MODE Gain Slope Logic Input 15 VPSV VGA Supply 5 V Both Channels 15 GAIN Gain Control Voltage 16 VOL1 CH1 Inverting VGA Output 16 RCLMP Output Clamping Level Input 17 VOH1 CH1 Noninverting VGA Output 17 COMM VGA Ground 18 ENB Enable VGA LNA 18 VOH2 CH2 Noninverting VGA Output 19 HILO VGA Gain Range Select HI or LO 19 VOL2 CH2 Inverting VGA Output 20 VCM1 CH1 Common Mode Voltage 20 NC No Connect 21 VIN1 CH1 VGA Inverting Input 21 VPSV VGA Supply 5 V 22 VIP 1 CH1 VGA Noninverting Input 22 VOL1 1 Inverting VGA Output 23 1 CH1 LNA Ground 23 VOH1 CH1 Noninverting VGA Output 24 LOP1 CH1 LNA Noninverting Output 24 COMM VGA Ground 25 LON1 CH1 LNA Inverting Output 25 ENBV VGA Enable 26 VPS1 CH1 LNA Supply 5 V 26 ENBL LNA Enable 27 INH1 CH1 LNA Input 27 HILO VGA Gain Range Select HI or LO 28 LMD1 CH1 LNA Signal Ground 28 VCM1 CH1 Common Mode Voltage 29 VIN1 CH1 VGA Inverting Input 30 1 CH1 VGA Noninverting Input 31 1 CH1 LNA Ground 32 LOP1 CH1 LNA Noninverting Output Rev E Page 9 of 40 AD8331 AD8332 AD8334 2 1 INH1 LMD1 COM1X LON1 LOP1 VIP1 VIN1 VPS1 GAIN12 CLMP12 EN12 EN34 VCM1 VCM2 63 62 61 60 INH2 1 12 PIN 1 LMD2 2 INDICATOR VOH1 COM2X 3 LON2 4 VPS12 LOP2 5 VOL2 VIP2 6 VOH2 VIN2 7 COM12 AD8334 VPS2 8 TOP VIEW MODE VPS3 9 Not to Scale NC VIN3 COM34 VIP3 VOH3 LOP3 VOL3 LON3 VPS34 COM3X
29. L 409 to 85 C 20 Lead Shrink Small Outline Package OSOP RQ 20 AD8331ARQZ R7 40 to 85 C 20 Lead Shrink Small Outline Package QSOP RQ 20 AD8331 EVAL Evaluation Board with AD8331ARQ AD8332ACP R2 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD8332ACP REEL 40 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD8332ACP REEL7 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD8332ACPZ R7 40 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD8332ACPZ RL 409 to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 32 2 AD8332ARU 40 to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD8332ARU REEL 40 to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD8332ARU REEL7 40 to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD8332ARUZ 409 to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD8332ARUZ R7 40 to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD8332ARUZ RL 409 to 85 C 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 AD8332 EVAL Evaluation Board with AD8332ARU EVAL AD8332 AD9238 Evaluation Board with AD8332ARU and AD9238 ADC AD8334ACPZ WP 40 to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ 64 1 AD8334ACPZ REEL 409 to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 64 1 AD8
30. RFACE PIN VCMn Input Resistance Current limited to 1 mA 30 Output CM Offset Voltage 2 5 125 25 100 mV Voltage Range Vour 2 0 V 1 5 to 3 5 V Rev E Page 5 of 40 AD8331 AD8332 AD8334 Parameter Conditions Min Typ Max Unit ENABLE INTERFACE PIN ENB PIN ENBL PIN ENBV Logic Level to Enable Power 2 25 5 V Logic Level to Disable Power 0 1 0 V Input Resistance Pin ENB 25 kQ Pin ENBL 40 kQ Pin ENBV 70 kQ Power Up Response Time 30 mV p p 300 us 150 mV p p 4 ms HILO GAIN RANGE INTERFACE PIN HILO Logic Level to Select HI Gain Range 2 25 5 V Logic Level to Select LO Gain Range 0 1 0 V Input Resistance 50 kQ OUTPUT CLAMP INTERFACE PIN RCLMP HI OR LO GAIN Accuracy HILO LO Ramp 2 74 Vout 1 V p p clamped 50 mV HILO HI 2 21 Vout 1 V p p clamped 75 mV MODE INTERFACE PIN MODE Logic Level for Positive Gain Slope 0 1 0 V Logic Level for Negative Gain Slope 2 25 5 V Input Resistance 200 kQ POWER SUPPLY PIN VPS1 PIN VPS2 PIN VPSV PIN VPSL PIN VPOS Supply Voltage 4 5 5 0 5 5 V Quiescent Current per Channel AD8331 20 25 mA AD8332 AD8334 20 29 mA Power Dissipation per channel No signal AD8331 125 mW AD8332 AD8334 145 mW Power Down Current AD8332 VGA and LNA Disabled 50 300 600 AD8331 VGA and LNA Disabled 50 240 400 LNA Current AD8331 ENBL Each channel 75 11 15 mA AD8332 AD8334 ENBL Each
31. V is used a voltage limiting resistor is needed to protect against overload INTERNAL CIRCUITRY lt lt 300 NEW Vow 100pF 0 1 AC GROUNDING FOR INTERNAL CIRCUITRY Figure 83 VCM Interface 03199 083 Logic Inputs ENB MODE and HILO The input impedance of all enable pins is nominally 25 and can be pulled up to 5 V a pull up resistor is recommended or driven by any 3 V or 5 V logic families The enable pin ENB powers down the VGA when pulled low the VGA output voltages are near ground Multiple devices can be driven from a common source Consult Table 3 Table 4 Table 5 and Table 6 for circuit functions controlled by the enable pins Pin HILO is compatible with 3 V or 5 V CMOS logic families It is either connected to ground or pulled up to 5 V depending on the desired gain range and output noise Optional Output Voltage Limiting The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive The peak to peak limited voltage is adjusted by a resistor to ground and Table 8 lists several voltage levels and the corresponding resistor value Unconnected the default limiting level is 4 5 V p p Note that third harmonic distortion increases as waveform amplitudes approach clipping For lowest distortion the clamp level should be set higher than the converter input span A clamp
32. ack network of the VGAs fixed gain amplifier and the feedback network of the postamplifier in both gain settings For best results use a 1 nF and a 0 1 uF capacitor in parallel with the 1 nF nearest to the VCM pin Separate pins are provided for each channel For dc coupling to a 3 V ADC the output common mode voltage is adjusted to 1 5 V by biasing the VCM pin POSTAMPLIFIER The final stage has a selectable gain of 3 5 dB x1 5 or 15 5 dB x6 set by the logic pin HILO Figure 79 is a simplified block diagram 03199 079 Figure 79 Postamplifier Block Diagram Separate feedback attenuators implement the two gain settings These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes 150 MHz The slew rate is 1200 V us in HI gain mode and 300 V us in LO gain mode The feedback networks for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel Rev E Page 28 of 40 AD8331 AD8332 AD8334 Noise The topology of the postamplifier provides constant input referred noise with the two gain settings and variable output referred noise The output referred noise in HI gain mode increases with gain by four This setting is recommended when driving converters with higher noise floors The extra gain boosts the output signal levels and noise floor appropriately When driving circuits with lower input noise flo
33. akes these devices suitable for a variety of applications Excellent bandwidth uniformity is maintained across the entire range The gain control interface provides precise linear in dB scaling of 50 dB V for control voltages between 40 mV and 1 V Factory trim ensures excellent part to part and channel to channel gain matching Rev E Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property their respective owners FUNCTIONAL BLOCK DIAGRAM LON LOP VIP VIN VCM HILO GAIN BIAS AND RCLMP INTERPOLATOR GAIN 03199 001 Figure 1 Signal Path Block Diagram GAIN dB 03199 002 FREQUENCY Hz Figure 2 Frequency Response vs Gain Differential signal paths result in superb second and third order distortion performance and low crosstalk The VGAs low output referred noise is advantageous in driving high speed differential ADCs The gain of the postamplifier can be pin selected to 3 5 dB or 15 5 dB to optimize gain
34. c HD3 85 dBc HD2 10 MHz 62 dBc HD3 66 dBc Input 1 dB Compression Point Vaan 0 25 V Vout 1 V p p f 1 MHz to 10 MHz 1 dBm Two Tone Intermodulation Distortion IMD3 AD8331 Vean 0 72 V 1 V f 1 MHz 80 dBc Vaan 0 5 V Vout 1 V f 10 MHz 72 dBc AD8332 AD8334 Vean 0 72 V Vout 1 V f 1 MHz 78 dBc Vaan 0 5 V 1 V p p f 10 MHz 74 dBc Output Third Order Intercept AD8331 Vaan 0 5 V Vout 1 V p p 1 MHz 38 dBm Vaan 0 5 V Vout 1 V f 10 MHz 33 dBm AD8332 AD8334 Vaan 0 5 V Vout 1 V p p f 1 MHz 35 dBm Vaan 0 5 V 1 V p p f 10 MHz 32 dBm Channel to Channel Crosstalk AD8332 AD8334 Vean 0 5 V 1 V p p f 1 MHz 98 dB Overload Recovery Vaan 1 0 V Vin 50 mV p p 1 V p p f 10 MHz 5 ns Group Delay Variation 5 MHz lt f lt 50 MHz full gain range 2 ns ACCURACY Absolute Gain Error 0 05 V lt Vean lt 0 10 V 1 0 5 2 dB 0 10 V lt Vean lt 0 95 V 0 3 1 dB 0 95 V lt Vean lt 1 0 V 2 1 dB Gain Law Conformance 0 1 V lt Vaan lt 0 95 V 0 2 dB Channel to Channel Gain Matching 0 1 V lt Vaan lt 0 95 V 0 1 dB GAIN CONTROL INTERFACE Pin GAIN Gain Scaling Factor 0 10 lt Vaan lt 0 95 V 48 5 50 51 5 dB V Gain Range LO gain 4 5 to 43 5 dB HI gain 7 5 to 55 5 dB Input Voltage Vean Range Oto 1 0 V Input Impedance 10 MO Response Time 48 dB gain change to 90 full scale 500 ns COMMON MODE INTE
35. can be driven by a common voltage source or DAC Decoupling should take into account any bandwidth considerations of the drive waveform using the total distributed capacitance If gain control noise in LO gain mode becomes a factor maintaining lt 15 nV VHz noise at the GAIN pin ensures satisfactory noise performance Internal noise prevails below 15 nV VHz at the GAIN pin Gain control noise is negligible in HI gain mode VCM Input The common mode voltage of Pin VCM Pin VOL and Pin VOH defaults to 2 5 V dc With output ac coupled applications the pin is unterminated however it must still be bypassed in close proximity for ac grounding of internal circuitry The VGA outputs can be dc connected to a differential load such as an ADC Common mode output voltage levels between 1 5 V and 3 5 V can be realized at Pin VOH and Pin VOL by applying the desired voltage at Pin VCM DC coupled operation is not recommended when driving loads on a separate PC board The voltage on the VCM pin is sourced by an internal buffer with an output impedance of 30 Q and 2 mA default output current see Figure 83 If the VCM pin is driven from an external source its output impedance should be 30 and its current drive capability should be gt gt 2 mA If the VCM pins of several devices are connected in parallel the external buffer should be capable of overcoming their collective output currents When a common mode voltage other than 2 5
36. channel 75 12 15 mA VGA Current AD8331 ENBV 75 14 20 mA AD8332 AD8334 ENBV 75 17 20 mA PSRR Vaan 0 V f 100 kHz 68 dB 1 All dBm values are referred to 50 2 The absolute gain refers to the theoretical gain expression in Equation 1 Best fit to linear in dB curve 4 The current is limited to 1 mA typical Rev E Page 6 of 40 AD8331 AD8332 AD8334 ABSOLUTE MAXIMUM RATINGS Table 2 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device This is a stress Voltage rating only functional operation of the device at these or any Supply Voltage VPSn VPSV VPSL VPOS 55V other conditions above those indicated in the operational Input Voltage INHn Vs 200 mV section of this specification is not implied Exposure to absolute ENB ENBL ENBV HILO Voltage Vs 200 mV maximum rating conditions for extended periods may affect GAIN Voltage 25V device reliability Power Dissipation AR Package 0 96 W CP 20 Package AD8331 1 63 W CP 32 Package AD8332 1 97 W RQ Package 0 78 W CP 64 Package AD8334 0 91 W Temperature Operating Temperature Range 40 to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature Soldering 60 sec 300 C AR Package 68 C W CP 20 Package 40 C W CP 32 Package 33 C W RQ Package 83 C W CP 64 Package 24 2 C W 1 Four layer JEDEC board 2S2P Exposed pad sold
37. e AD8332 performance The equivalent input noise of the LNA is the same for single ended and differential output applications The LNA noise figure improves to 3 5 dB at 50 without VGA noise but this 15 exclusive of noise contributions from other external circuits connected to LOP A series output resistor is usually recommended for stability purposes when driving external circuits on a separate board see the Applications section In low noise applications a ferrite bead is even more desirable VARIABLE GAIN AMPLIFIER The differential X AMP VGA provides precise input attenuation and interpolation It has a low input referred noise of 2 7 nV VHz and excellent gain linearity A simplified block diagram is shown in Figure 78 GAIN INTERPOLATOR BOTH CHANNELS 03199 078 POSTAMP Figure 78 Simplified VGA Schematic X AMP VGA The input of the VGA is a differential R 2R ladder attenuator network with 6 dB steps per stage and a net input impedance of 200 Q differential The ladder is driven by a fully differential input signal from the LNA and is not intended for single ended operation LNA outputs are ac coupled to reduce offset and isolate their common mode voltage The VGA inputs are biased through the ladder s center tap connection to VCM which is typically set to 2 5 V and is bypassed externally to provide a clean ac ground The signal level at successive stages in the input attenuator falls from 0 dB to 48 dB in 6 d
38. ely coupled to a VGA input The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain for a net gain range of 27 dB to 21 dB The X AMP gain interpolation technique results in low gain error and uniform bandwidth and differential signal paths minimize distortion The final stage is a logic programmable amplifier with gains of 3 5 dB or 15 5 dB The LO and HI gain modes are optimized for 12 bit and 10 bit ADC applications in terms of output referred noise and absolute gain range Output voltage limiting can be programmed by the user LOW NOISE AMPLIFIER LNA Good noise performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain which minimizes the noise contribution in the following VGA Active impedance control optimizes noise performance for applications that benefit from input matching A simplified schematic of the LNA is shown in Figure 74 INH is capacitively coupled to the source An on chip bias generator establishes dc input bias voltages of 3 25 V and centers the output common mode levels at 2 5 V A Capacitor Crup of the same value as the Input Coupling Capacitor Cu is connected from the LMD pin to ground m o H 03199 074 Figure 74 Simplified LNA Schematic The LNA supports differential output voltages as high as 5 V p p with positive and negative excursions of 1 25 V about a common mode voltage of 2 5 V Because
39. epresentative Differential Output Offset Voltage vs Vean at Three Temperatures Rev E Page 13 of 40 AD8331 AD8332 AD8334 SAMPLE SIZE 100 0 2V lt Vear lt 0 7V 03199 019 03199 020 d lt 496 497 498 499 50 0 50 1 50 2 50 3 50 4 50 5 GAIN SCALING FACTOR Figure 19 Gain Scaling Factor Histogram 100 SINGLE ENDED PIN VOH OR VOL R o 10 2 lt 2 1 2 0 1 100 1M 10M FREQUENCY Hz Figure 20 Output Impedance vs Frequency 5 1M 10M FREQUENCY Hz Figure 21 LNA Input Impedance vs Frequency for Various Values of Rre and Csu 03199 021 Figure 23 LNA Frequency Response Single Ended for Various Values of Rin Rev E Page 14 of 40 GAIN dB GAIN dB 50 1 1 1 Ya ss sss 7 Rij 500 7 x Rep 2700 1 Rep 5490 i Rin 2000 Y Reg 1 1 50j 03199 022 Figure 22 Smith Chart S11 vs Frequency 0 1 MHz to 200 MHz for Various Values of Rrg 20 15 10 03199 023 15 100k 1M 10M
40. ered to board nine thermal vias in pad JEDEC 4 layer board J STD 51 9 3 Exposed pad soldered to board 25 thermal vias in pad JEDEC 4 layer board J STD 51 9 ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate the human body and test equipment and can discharge without detection Although this product features ART ed lt proprietary ESD protection circuitry permanent damage may occur devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev Page 7 of 40 AD8331 AD8332 AD8334 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 INDICATOR AD8331 TOP VIEW Not to Scale 03199 003 Figure 3 20 Lead QSOP Pin Configuration AD8331 Table 3 20 Lead QSOP Pin Function Description AD8331 Pin No Mnemonic Description 1 LMD LNA Signal Ground 2 INH LNA Input 3 VPSL LNA 5 V Supply 4 LON LNA Inverting Output 5 LOP LNA Noninverting Output 6 COML LNA Ground 7 VIP Noninverting Input 8 VIN VGA Inverting Input 9 MODE Gain Slope Logic Input 10 GAIN Gain Control Voltage 11 VCM Common Mode Voltage 12 RCLMP Output Clamping Level 13 HILO Gain Range Select HI or LO 14 VPOS 5 V Supply 15 VOH Noninverting VGA Output 16 VOL Inverting VGA Output 17 COMM VGA G
41. ferred voltage noise sets an important limit on system performance The short circuit input voltage noise of the LNA is 0 74 nV VHz or 0 82 nV VHz at maximum gain including the VGA noise The open circuit current noise is 2 5 pA VHz These measurements taken without a feedback resistor provide the basis for calculating the input noise and noise figure performance of the configurations in Figure 75 Figure 76 and Figure 77 are simulations extracted from these results and the 4 1 dB NF measurement with the input actively matched to 50 source Unterminated Res operation exhibits the lowest equivalent input noise and noise figure Figure 76 shows the noise figure vs source resistance rising at low Rs where the LNA voltage noise is large compared to the source noise and again at high Rs due to current noise The VGAs input referred voltage noise of 2 7 nV VHz is included in all of the curves UNTERMINATED Vin Vout ACTIVE IMPEDANCE MATCH Rin Rfg Rs Vin Vout Rep 1 4 5 03199 075 Figure 75 Input Configurations INCLUDES NOISE OF VGA RESISTIVE TERMINATION 5 Rg Rin ACTIVE IMPEDANCE MATCH NOISE FIGURE dB SIMULATION UNTERMINATED 03199 076 50 100 1k Rs 0 Figure 76 Noise Figure vs Rs for Resistive Active Matched and Unterminated Inputs INCLUDES NOISE OF VGA Rin 500 Rin 750 3 Rix 1000 NOISE FIGURE dB Riy 2000
42. input referred noise as a function of Vean are plotted in Figure 25 and Figure 27 for the short circuited input conditions The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range The output referred noise is flat over most of the gain range because it is dominated by the fixed output referred noise of the VGA Values are 48 nV VHz in LO gain mode and 178 nV VHz in HI gain mode At the high end of the gain control range the noise of the LNA and source prevail The input referred noise reaches its minimum value near the maximum gain control voltage where the input referred contribution of the VGA becomes very small At lower gains the input referred noise and thus noise figure increases as the gain decreases The instantaneous dynamic range of the system is not lost however because the input capacity increases with it The contribution of the ADC noise floor has the same dependence as well The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC With its low output referred noise levels these devices ideally drive low voltage ADCs The converter noise floor drops 12 dB for every 2 bits of resolution and drops at lower input full scale voltages and higher sampling rates ADC quantization noise is discussed in the Applications section The preceding noise performance discussion applies to a differential VGA output signal
43. is typically used with an ADC Filter requirements are application dependent When the ADC resides on a separate board the majority of filter components should be placed nearby to suppress noise picked up between boards and to mitigate charge kickback from the ADC inputs Any series resistance beyond that required for output stability should be placed on the ADC board Figure 85 shows a second order low pass filter with a bandwidth of 20 MHz The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC OPTIONAL BACKPLANE 1 5uH 1580 1 1 1 1 1 15ugH 1580 1 03199 085 Figure 85 20 MHz Second Order Low Pass Filter DRIVING ADCs The output drive accommodates a wide range of ADCs The noise floor requirements of the VGA depend on a number of application factors including bit resolution sampling rate full scale voltage and the bandwidth of the noise antialias filter The output noise floor and gain range can be adjusted by selecting HI or LO gain mode The relative noise and distortion performance of the two gain modes can be compared in Figure 25 and Figure 31 through Figure 41 The 48 nV VHz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions such as 12 bits Both gain modes can accommodate ADC full scale voltages as high as 4 V p p Because distortion performance remains favorable for output voltages as high as 4 V p
44. l Expressions for choosing Res in terms of Rw and for choosing Crs are found in the Applications section and the ferrite bead enhance stability at higher frequencies where the loop gain is diminished and prevent peaking Frequency response plots of the LNA are shown in Figure 23 and Figure 24 The bandwidth is approximately 130 MHz for matched input impedances of 50 to 200 and declines at higher source impedances The unterminated bandwidth when Res is approximately 80 MHz Each output can drive external loads as low as 100 in addition to the 100 input impedance of the VGA 200 differential Capacitive loading up to 10 pF is permissible All loads should be ac coupled Typically Pin LOP output is used as a single ended driver for auxiliary circuits such as those used for Doppler ultrasound imaging and Pin LON drives Res Alternatively a differential external circuit can be driven from the two outputs in addition to the active feedback termination In both cases important stability considerations discussed in the Applications section should be carefully observed The impedance at each LNA output is 5 A 0 4 dB reduction in open circuit gain results when driving the VGA and 0 8 dB with an additional 100 Q load at the output The differential gain of the LNA is 6 dB higher If the load is less than 200 on either side a compensating load is recommended on the opposite output LNA Noise The input re
45. level of 1 5 V p p is recommended for a 1 V p p linear output range 2 7 for a 2 V range or 1 for a 0 5 V p p operation The best solution is determined experimentally Figure 84 shows third harmonic distortion as a function of the limiting level for a 2 V p p output signal A wider limiting level is desirable in HI gain mode Vean 0 75V HD3 dBc 03199 084 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 CLAMP LIMIT LEVEL V p p Figure 84 HD3 vs Clamping Level for 2 V p p Differential Input Table 8 Clamp Resistor Values Clamp Resistor Value Clamp Level V p p HILO LO HILO HI 0 5 1 21 1 0 2 74 2 21 1 5 4 75 4 02 2 0 75 6 49 2 5 11 9 53 3 0 16 9 14 7 3 5 26 7 23 2 4 0 49 9 39 2 44 100 73 2 Rev E Page 31 of 40 AD8331 AD8332 AD8334 Output Decoupling When driving capacitive loads greater than about 10 pF or long circuit connections on other boards an output network of resistors and or ferrite beads can be useful to ensure stability These components can be incorporated into a Nyquist filter such as the one shown in Figure 81 In Figure 81 the resistor value is 84 5 The AD8332 EVAL incorporates 100 Q in parallel with a 120 nH bead Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB The exact values of these components can be selected empirically An antialiasing noise filter
46. mall Signal Bandwidth Vout 0 2 V p p AD8331 120 MHz AD8332 AD8334 100 MHz 3 dB Large Signal Bandwidth 2 V p p AD8331 110 MHz AD8332 AD8334 90 MHz Slew Rate AD8331 LO gain 300 V us HI gain 1200 V us AD8332 AD8334 LO gain 275 V us HI gain 1100 V us Input Voltage Noise Rs 0 O HI or LO gain eo f 5 MHz 0 82 nV VHz Noise Figure Vean 1 0 V Active Termination Match Rs Rin 50 f 10 MHz measured 4 15 dB Rs Rin 200 O f 5 MHz simulated 2 0 dB Unterminated Rs 50 eo f 10 MHz measured 2 5 dB Rs 200 f 5 MHz simulated 1 0 dB Output Referred Noise AD8331 Vaan 0 5 V LO gain 48 nV VHz Vaan 0 5 V HI gain 178 nV VHz AD8332 AD8334 Vaan 0 5 V LO 40 nV 4Hz Vaan 0 5 V HI gain 150 nV VHz Output Impedance Postamplifier DC to 1 MHz 1 Rev 4 of 40 AD8331 AD8332 AD8334 Parameter Conditions Min Typ Max Unit Output Signal Range Postamplifier gt 500 O unclamped either pin Vem 1 125 V Differential 4 5 V p p Output Offset Voltage Vaan 0 5 V AD8331 Differential 50 5 50 mV Common mode 125 25 100 mV AD8332 AD8334 Differential 20 5 20 mV Common mode 125 25 100 mV Output Short Circuit Current 45 mA Harmonic Distortion Vaan 0 5 V 1 V HI gain AD8331 HD2 1 MHz 88 dBc HD3 85 dBc HD2 10 MHz 68 dBc HD3 65 dBc AD8332 AD8334 HD2 1 MHz 82 dB
47. oen A ER tss 22 Moved Measurement Considerations Section 20 Inserted Figure 67 and Figure 68 23 Inserted Figure 70 and Figure 71 24 Change to Figure 2 24 Changes to Figure 73 and Low Noise Amplifier Section 25 Changes to Postamplifier Section sse 28 Changes to Figure 80 ecd ep a t GEI Re 29 Changes to LNA External Components Section 30 Changes to Logic Inputs ENB MODE and HILO Section 31 Changes to Output Decoupling and Overload Sections 32 Changes to Layout Grounding and Bypassing Section 33 Changes to Ultrasound TGC Application Section 34 Added High Density Quad Layout 34 Inserted Figure tein 38 Updated Outline Dimensions eerte 39 Changes to Ordering Guide 3 06 Rev C to Rev D Updated Format m Ree Universal Changes to Features and General 1 Changes to Table 1 113 Changes to Table usa a na a u a S 6 Changes to Ordering Guide eee 34 11 03 Rev B to Rev C Addition of New Part sse Universal Ch nges to FigUr s annus replies Universal Updated Outline 32 5 03 Rev A to Rev B Edits t Ordering Guide iet eene 32 Edits to Ultrasound TGC Application Section
48. ors the LO gain mode optimizes the output dynamic range Although the quantization noise floor of an ADC depends on a number of factors the 48 nV VHz and 178 nV VHz levels are well suited to the average requirements of most 12 bit and 10 bit converters respectively An additional technique described in the Applications section can extend the noise floor even lower for possible use with 14 bit ADCs Output Clamping Outputs are internally limited to a level of 4 5 V p p differential when operating at a 2 5 V common mode voltage The postamp implements an optional output clamp engaged through a resistor from Rcimp to ground Table 8 shows a list of recommended resistor values Output clamping can be used for ADC input overload protection if needed or postamp overload protection when operating from a lower common mode level such as 1 5 V The user should be aware that distortion products increase as output levels approach the clamping levels and the user should adjust the clamp resistor accordingly For additional information see the Applications section The accuracy of the clamping levels is approximately 5 in LO or HI mode Figure 80 illustrates the output characteristics for a few values of 5 0 4 5 4 0 3 5 3 0 2 5 Vou V 2 0 03199 080 V Figure 80 Output Clamping Characteristics Rev E Page 29 of 40 AD8331 AD8332 AD8334
49. p see Figure 36 it is possible to lower the output referred noise even further by using a resistive attenuator or transformer at the output The circuit in Figure 86 has an output full scale range of 2 V p p a gain range 10 5 dB to 37 5 dB and output noise floor of 24 nV VHz making it suitable for some 14 bit ADC applications 4V DIFF 2V DIFF 48nV VHz 24 2 ADC AD6644 Figure 86 Adjusting the Noise Floor for 14 Bit ADCs OVERLOAD These devices respond gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high Each stage is designed for clean limited overload waveforms and fast recovery when gain setting or input amplitude is reduced 03199 086 Signals larger than 275 mV at the LNA input are clipped to 5 V p p differential prior to the input of the VGA Figure 48 shows the response to a 1 V p p input burst The symmetric overload waveform is important for applications such as CW Doppler ultrasound where the spectrum of the LNA outputs during overload is critical The input stage is also designed to accommodate signals as high as 2 5 V without triggering the slow settling ESD input protection diodes Both stages of the VGA are susceptible to overload Postamp limiting is more common and results in the clean limited output characteristics found in Figure 49 Recovery is fast in all cases The graph
50. p 0 1uF 03199 088 BAS40 04 Figure 88 Input Overload Clamping When selecting overload protection the important parameters are forward and reverse voltages and t The Infineon BAS40 04 series shown in Figure 88 has of 100 ps and Vr of 310 mV at 1 mA Many variations of these specifications can be found in vendor catalogs LAYOUT GROUNDING AND BYPASSING Due to their excellent high frequency characteristics these devices are sensitive to their PCB environment Realizing expected performance requires attention to detail critical to good high speed board design A multilayer board with power and ground planes is recommended with blank areas in the signal layers filled with ground plane Be certain that the power and ground pins provided for robust power distribution to the device are connected Decouple the power supply pins with surface mount capacitors as close as possible to each pin to minimize impedance paths to ground Decouple the LNA power pins from the VGA supply using ferrite beads Together with the capacitors ferrite beads eliminate undesired high frequencies without reducing the headroom Use a larger value capacitor for every 10 chips to 20 chips to decouple residual low frequency noise To minimize voltage drops use a 5 V regulator for the VGA array Several critical LNA areas require special care The LON and LOP output traces must be as short as possible before connecting to the coupling capaci
51. printed circuit board are available for components and that the bypass and power supply decoupling circuitry is located on the wiring side of the board Rev E Page 34 of 40 AD8331 AD8332 AD8334 AD8332ARU 50 0 1pF 1 28 F c49 LMb2 TP6 oft L12 120nH 113 c60 TP3 120nHFB 0 1 REDI M C79 TB1 C80 JP5 JP6 5V CFB2 Z2pF T 1 Int 22 1 18nF L 1 18 22 cas 5VLNA 3 26 00 BLACK Hu C41 C74 1 I 2 0414 74 5VLNA 2740 2740 GND L i e 7 4 25 120nH sVGA 16 24 120nH 65 23 42 59 0 1uF 0 1pF 22 VCM1 2 JP13 l Vem C48 78 01 inF 9 20 C77 C43 1nF T 0 1yF T 5VGA 10 19 7 HIGAIN 2 TP7 GNDO 5 LO GAIN yi 11 18 ENABLE R3 JP16 R ceo ces DISABLE Reime 7 9 tur 12 i 3 8 7 DC2H 1000 1000 JP9 OPTIONAL 4 POLE LOW PASS n OPTIONAL 4 POLE LOW PASS FILTER FILTER 54 L11 16 L9 C58 L15 VintB 0 1 120nH 120nH FB 0 1uF SAT VintA C55 L10 15 18 56 116 0 1 120nH 12017 1 lt 4 gt 45 85 JP10 0 T 1nF T Figure 91 Schematic TGC VGA Section Using an AD8332 and AD9238 03199 091 Rev E Page 35 of 40 AD8331 AD8332 AD8334 VR1 ADP3339AKC 3 3 3 3VAVDD L5 C44 120nH FB
52. requency Two Values of AC Coupling NETWORK ANALYZER FERRITE BEAD 2370 OUT 120nH 280 1 1 500 2370 280 03199 059 Figure 59 LNA Input Impedance vs Frequency Standard and Smith Chart 511 Formats NETWORK ANALYZER FERRITE BEAD 120nH A 03199 060 Figure 60 Frequency Response for Unterminated LNA Single Ended NETWORK ANALYZER FERRITE BEAD 120nH 0 1uF qp fet 22 03199 061 Figure 61 Short Circuit Input Referred Noise Rev E Page 21 of 40 AD8331 AD8332 AD8334 SPECTRUM ANALYZER A GAIN FERRITE BEAD 49 90 0 1uF 420nH ints 500 10 22pF I 0 1 SIGNAL GENERATOR z 0 AuF TO MEASURE GAIN l DISCONNECT FOR NOISE MEASUREMENT 03199 062 Figure 62 Noise Figure SPECTRUM ANALYZER 22pF LMD 0 1 SIGNAL GENERATOR 2 8 d 5 SPECTRUM ANALYZER Figure 63 Harmonic Distortion vs Load Resistance 18nF 2700 AD8332 0 1 2370 22pF LM SIGNAL 0 1 0 1 280 GENERATOR 03199 064 Figure 64 Harmonic Distortion vs Load Capacitance 6dB SPECTRUM 12208 ANALYZER 18nF 2700 FERRITE fon 0 1pF 2370 280 2370 2998 280 SIGNAL GENERATORS 8 s 5 Figure 65 IMD3 vs Frequency Rev E Page 22 of 40 AD8331 AD8332 AD8334 OSCILLOSCOPE 18nF 2700 FERRITE
53. round 18 ENBV VGA Enable 19 ENBL LNA Enable 20 COMM VGA Ground Rev E Page 8 of 40 Table 4 28 Lead TSSOP Pin Function Description AD8332 AD8332 TOP VIEW Not to Scale 03199 004 Figure 4 28 Lead TSSOP Pin Configuration AD8332 LOP1 COM1 31 YSPIN 1 AD8331 AD8332 AD8334 VIP1 VIN1 VCM1 HILO ENBL ENBV 30 INDICATOR BE 08332 TOP VIEW Not to Scale N N N W 2 n 2 8 lt gt d 8 gt gt 9 8 Figure 5 32 Lead LFCSP Pin Configuration AD8332 Table 5 32 Lead LFCSP Pin Function Description AD8332 Pin No Mnemonic Description Pin No Mnemonic Description 1 LMD2 CH2 LNA Signal Ground 1 LON1 CH1 LNA Inverting Output 2 INH2 CH2 LNA Input 2 VPS1 LNA Supply 5 V 3 VPS2 CH2 Supply LNA 5 V 3 INH1 CH1 LNA Input 4 LON2 CH2 LNA Inverting Output 4 LMD1 CH1 LNA Signal Ground 5 LOP2 CH2 LNA Noninverting Output 5 LMD2 CH2 LNA Signal Ground 6 COM2 CH2 LNA Ground 6 INH2 CH2 LNA Input 7 VIP2 2 VGA Noninverting Input 7 VPS2 CH2 LNA Supply 5 V 8 VIN2 2 VGA Inverting Input 8 LON2 CH2 LNA Inverting Output 9 VCM2 CH2 Common Mode Voltage 9 LOP2 CH2 LNA Noninverting Output 10 GAIN Gain Control Voltage 10 COM2 CH2 LNA Ground 11 RCLMP Output Clamping Resistor 11 VIP2 CH2 VGA Noninverting Input 12 VOH2 CH2 Noninverting VGA Output 12 VIN2 CH2 Inverting Input 13 VOL2 CH2 Inverting VGA Output 13 VCM2
54. sion is 1 dB for variations in temperature process supply voltage interpolator gain ripple trim errors and tester limits The gain error relative to a best fit line for a given set of conditions is typically 0 2 dB Gain matching between channels is better than 0 1 dB Figure 11 shows gain errors in the center of the control range When Vaan lt 0 1 or gt 0 95 gain errors are slightly greater Rev E Page 27 of 40 AD8331 AD8332 AD8334 The gain slope can be inverted as shown in Figure 73 available in most versions The gain drops with a slope of 50 dB V across the gain control range from maximum to minimum gain This slope is useful in applications such as automatic gain control where the control voltage is proportional to the measured output signal amplitude The inverse gain mode is selected by setting the MODE pin HI Gain control response time is less than 750 ns to settle within 10 of the final value for a change from minimum to maximum gain VGA Noise In a typical application a VGA compresses a wide dynamic range input signal to within the input span of an ADC While the input referred noise of the LNA limits the minimum resolvable input signal the output referred noise which depends primarily on the VGA limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage This limit is set in accordance with the quantization noise floor of the ADC Output and
55. tors connected to Pin VIN and Pin VIP Res must be placed near the LON pin as well Resistors must be placed as close as possible to the VGA output pins VOL and VOH to mitigate loading effects of connecting traces Values are discussed in the Output Decoupling section Signal traces must be short and direct to avoid parasitic effects Wherever there are complementary signals symmetrical layout should be employed to maintain waveform balance PCB traces should be kept adjacent when running differential signals over a long distance MULTIPLE INPUT MATCHING Matching of multiple sources with dissimilar impedances can be accomplished as shown in Figure 90 A relay and low supply voltage analog switch can be used to select between multiple sources and their associated feedback resistors An ADG736 dual SPDT switch is shown in this example however multiple switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers DISABLING THE LNA Where accessible connection of the LNA enable pin to ground powers down the LNA resulting in a current reduction of about half In this mode the LNA input and output pins can be left unconnected however the power must be connected to all the supply pins for the disabling circuit to function Figure 89 illustrates the connections using an AD8331 as an example e NC LMD COMM AD8331 NC ENBL 0 018pF 5V MODE GAIN O 03199
56. ve useful Figure 82 shows the interconnection details of the LNA output Capacitive coupling between the LNA outputs and the VGA inputs is required because of the differences in their dc levels and the need to eliminate the offset of the LNA Capacitor values of 0 1 are recommended There is 0 4 dB loss in gain between the LNA output and the VGA input due to the 5 Q output resistance Additional loading at the LOP and LON outputs affect LNA gain 03199 081 0 Nx Figure 81 Basic Connections for a Typical Channel AD8332 Shown LNA DECOUPLING TO EXT RESISTOR CIRCUIT 5Q 500 TO EXT LNA DECOUPLING RESISTOR SIRCUIT 03199 082 Figure 82 Interconnections of the LNA and VGA Both LNA outputs are available for driving external circuits Pin LOP should be used in those instances when a single ended LNA output is required The user should be aware of stray capacitance loading of the LNA outputs in particular LON The LNA can drive 100 in parallel with 10 pF If an LNA output is routed to a remote PC board it tolerates a load capacitance up to 100 pF with the addition of a 49 9 series resistor or ferrite 75 0 100 MHz bead Gain Input The GAIN pin is common to both channels of the AD8332 The input impedance is nominally 10 and a bypass capacitor from 100 pF tol nF is recommended Rev E Page 30 of 40 AD8331 AD8332 AD8334 Parallel connected devices

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