Home

lnfineon TLE 6244X Manual

1. Final Data Sheet 7 V4 2 2003 08 29 TLE 6244X technologies 1 5 Function of Pins IN1 to IN16 Control inputs of the power stages Internal pull up current sources exception IN8 with pull down current source FCL Clock for the usec bus pin shared with IN16 FDA Data for the usec bus pin shared with ING SSY Strobe and Synchronisation for the usec bus pin shared with IN7 OUT1 to OUT18 VDD UBatt GND1 to GND8 RST GND ABE SI SO SCK SS Final Data Sheet Outputs of the power switches Short circuit proof Low side switches Limitation of the output voltage by zener diodes Supply voltage 5V Supply voltage Upat Pin must not be left open but has to be connected either to Ugat or to Vpp e g in commercial vehicles Ground pins Ground pins for the power stages see 2 4 Ground reference of all logic signals is GND1 2 Reset Active low Locks all power switches regardless of their input signals except OUT8 Clears the fault registers Resets the usec bus interface registers In Output VDD Monitoring Active low Output pin for the VDD Monitoring Input pin for the shut off signal coming from the supervisor Sense ground VDD Monitoring SPI Interface 8 V4 2 2003 08 29 TLE 6244X technologies 1 6 SPI Interface The serial SPI interface establishes a communication link between TLE6244X and the systems mi
2. gt Uarop Reutl up UBatt UBR Uug TLE6244X Y lag Y OUTi UiresoL Rpull up max UBR min Uarop max 7 UthresOL max Idiag max UBR min is the required minimum battery voltage for diagnostic function of the ECU The drop volt age is composed of the drop voltage of the regulator and the drop voltage of the reverse protec tion circuit of the regulator resp the forward voltage of a reverse protection diode Attention This equation also applies to power switches that are used as signal drivers pull up resistor inside ECU or outside ECU the permissible pull up resistance without a wrong diagnostic infor mation is calculated by the same equation On dimensioning the pull up resistance in combination with the diagnostic current in applications as signal drivers attention must be paid especially to the required high level also for low battery voltage Final Data Sheet 32 V4 2 2003 08 29 e Infineon technologies TLE 6244X 1 9 Timing Diagram of the Power Outputs 1 9 1 Power Stages Uni 4 taon tson taorr tsorr If the output is controlled via SPI the timing starts with the positive slope at SS If the output is controlled by the usec bus the timing starts with the pos slope of SSY With ohmic load UCLi UBatt Final Data Sheet 33 V4 2 2003 08 29 technologies TLE 6244X 1 10 VDD Monitoring Overview The VDD monitori
3. DAES RAGA GMS Aman BAERS e Infineon technologies TLE 6244X 18 Channel Smart Lowside Switch ASSP for Powertrain Final Data Sheet Features Short Circuit Protection Overtemperature Protection Overvoltage Protection 16 bit Serial Data Input and Diagnostic Output 2 bit chan acc SPI Protocol Direct Parallel Control of 16 channels for PWM Applications P MQFM 64 10 Low Quiescent Current Compatible with 3 3V Microcontrollers Ordering Code Q67007 A9613 Electrostatic discharge ESD Protection General description 18 fold Low Side Switch 0 35 Q to 1 Q in Smart Power Technology SPT with a Serial Pe ripheral Interface SPI and 18 open drain DMOS output stages The TLE6244X is protected by embedded protection functions and designed for automotive and industrial applications The output stages are controlled via SPI Interface Additionally 16 of the 18 channels can be controlled direct in parallel for PWM applications Therefore the TLE6244X is particularly suitable for engine management and powertrain systems IN 3 gt p Protection Functions L Has Ch 1 Has Ch 1 LO GIC i L 1 55 Ch 1 OUTI i as Ch 1 Output Stage IN15 Has Ch 1 IN16 L Has Ch 1 pLnnr qr F s 4erial Interface Output Control al Buffer jours CH SPI SO lt L GND Final Data Sheet 1 V4 2 2003 08 29 TLE 6
4. R1 R2 9 S1 Us DC Volt EN DUT meter Uc S3 Y e Uc 2kV R4 100kQ Ro 1 5kQ C 100pF Number of pulses each pin 18 in all Frequency 1Hz Arrangement and performance The requirements of MIL883D Method 3015 latest revision have to be fulfilled Final Data Sheet 68 V4 2 2003 08 29 29 V4 2 2003 08 69 e gt lt lt N O 200 T1S6 T100V 2609Y 590999 ONUOPU3A y Saj8ojouu28 SuoN a3oghiey LL woaujguI peusan 10 97 10 1s _po e dem JNI ILODO 39V 2Vd Ku ONDISVA X3UNI I qoudo 4 10 01 2000 D A 89 e LH Lisesu exu Ed qu E EPMO 1049 api uo2 Auoduo r Tigas a Toa pop Jeta gt S39NVH2 SONIW e68u0u9 g i ok D 69 P 340 NVIS 2 0 AQIS did XVW S20 30 NOISNAlDdd WISW YO OILSV ld 30N TONI LON S3000 IL O EE REIR RTT uus ar em Es onl 2 i E V y a Sl me pis gt gt AMOR H O Ino 156 gt D eg 3009 f M zs i A e EDI LE E i
5. Characteristics of the SPI Interface 1 If the slave select signal at SS is High the SPl logic is set on default condition i e it expects an instruction 2 If the 5V reset RST is active the SPI output SO is switched into tristate The VDD monitoring ABE has no influence on the SPI interface 3 Verification byte Simultaneously to the receipt of an SPI instruction TLE6244X transmits a verification byte via the output SO to the controller This byte indicates regular or irregular operation of the SPI It contains an initial bit pattern and a flag indicating an invalid instruction of the previous access 4 On a read access the databits at the SPI input SI are rejected On a writing access or after the DEL DIA instruction the TLE6244XTLE6244X sets the SPI output SO to low after sending the verification byte If more than 16 bits are received the rest of the frame is rejected 5 Invalid instruction access An instruction is invalid if one of the following conditions is fulfilled an unused instruction code is detected see tables with SPI instructions in case the previous transmission is not completed in terms of internal data processing number of SPI clock pulses counted during active SS differs from exactly 16 clock pulses A write access and the instruction DEL DIA is internally suppressed i e internal _ registers will not be affected in all cases where at the rising inactive edge of SS the number of falling edges
6. 3 6 7 Leakage Cur rent 3 6 8 Clamping 3 6 8 1 Clamping Voltage 3 6 8 2 Maximum Clamping En ergy Te lt 110 C 3 6 8 3 Maximum Clamping En ergy Tc lt 60 C 3 6 8 4 Maximum Clamping En ergy with two Outputs con nected in par allel 3 6 8 5 Maximum Clamping En ergy at Load Dump 3 6 8 6 Jump Start 3 6 8 7 Singlepulse Tc lt 60 C TLE 6244X On Off Measurementwithohmic load Itdon taoril switch on slew rate switch off slew rate Uypp OV Uouts 14 14V leakage current of the DMOS diagnostic current 0 Uvpp OV Uouts 14 24V leakage current of the DMOS diagnostic current 0 louri 0 2A Linear decreasing current fmax 30Hz see diagrams E f I on page 66 louro 14 lt 2 2A louro 14 1 0A Linear decreasing current fmax 30Hz louro 14 lt 2 2A louro 14 lt 1 0A Each output 75 of the values of 3 6 8 2 resp 3 6 8 3 For a maximum of 10 times during ECU life load dump with 400ms and R 20 over the load e g 2W lamp Each output 150 of the values of 3 6 8 3 For a maximum of 10 jump starts of 2 minutes each during ECU life louTe 14 lt 0 6A max 10 000 pulse gt OO 00UUU Uda 40 10 us 5 us 10 us 10 us 5 us 20 V us 25 V us 50 HA 200 HA 45 50 V 14 mJ 30 mJ 17 mJ 36 mJ 50 mJ 50 mJ Final Data Sheet 51 V4 2 2003 08 29 technologies
7. Between 17V x Uypat lt 21V the short circuit shutdown threshold is switched A power stage that is switched off in case of SCB can be switched on again by an off on cycle at the cor responding input pin resp by the change of the state of the corre sponding SPI bit SCONx see page 16 by the usec Bus by a DEL DIA instruction or can be released again by reset If the fault register is cleared before this release by a DEL DIA instruc tion a new fault entry of SCB is immediately carried out even if SCB condition is no longer present See Note 1 11 1 Shutoff delay of the power stages after detection of SCB OUT1 2 5 6 Ty 25 C OUT1 2 5 6 T 150 C OUT1 2 5 6 T 40 C OUT3 4 Ty 25 C OUT3 4 Ty 150 C OUT3 4 T 40 C For Uypatt 10V Ro is increased up to 20 On Off Measurement with ohmic load Itaon 7 taorrd switch on slew rate switch off slew rate UJ P gt gt gt gt gt OO OOUUU UoUT 1 6 tvoff Ron1 2 5 6 Ron1 2 5 6 Ron1 2 5 6 Rona 4 Rona 4 Rona 4 taon lont laor tsoff4 e Ata o 00 Oo Son1 6 Sofft 6 36 60 220 420 180 210 410 170 320 600 250 300 580 240 us ma ma ma ma ma ma us us us us us V us V us Final Data Sheet 47 V4 2 2003 08 29 technologies 3 5 7 Leakage Cur rent 3 5 8 Clamping 3 5 8 1 Clamping Voltage 3 5 8 2 Ma
8. and Reset IN1 IN16 RST 3 4 1 Low Level Reset not active B URSTL 1 0 V Power stage on for i 1 5 5 9 15 B UiNiL 1 0 V i 6 7 16 B UiNiL 1 0 V Power stage off for i 8 UiNiL 1 0 V 3 4 2 High Level Power stage off for B UrstTH 1 7 V i 1 7 9 16 B UiNiH 2 0 V V Power stage on for i 8 B UmiH 2 0 V 3 4 3 Hysteresis AUiNi 0 1 0 6 V AUprst 3 4 4 Input Cur 0 3V lt Uni RsT lt Uypp A B lwiRsr 100 5 HA rents i 1 7 9 16 In RST Uvpp Uni lt 36 V C inl 5 HA i 1 7 9 16 0 3V lt Uing lt Uvpp A B ling 100 100 HA 0 8V lt Uing lt Uvpp pull down A ling 20 40 100 HA Uvpp lt Uing lt 36 V pull down C ling 20 40 100 pA OV lt URst lt Uypp 1 7V pull up A IgsT 20 40 100 pA 0V lt Uni lt Uvpp 1 7V pull up A liyi 5 10 20 HA i 6 7 16 Bit BMUX 1 CONFIG_REG OV Uni lt Uypp 1 7V pull up A liyi 20 40 100 HA i 1 5 9 15 Bit BMUX 0 CONFIG_REG OV lt Uyi lt Uvpp high impedance A liNil 1 HA i 1 5 9 15 Final Data Sheet 45 V4 2 2003 08 29 technologies 3 4 5 Input Protec tion INi 3 5 Power Outputs 2 2A 70V OUT1 6 3 5 1 Nominal Cur rent 3 5 2 Extended Cur rent Range 3 5 3 Maximum Current Short Circuit Shut down Threshold TLE 6244X Input clamping at INi i 1 16 No malfunction during clamping Max clamping current externally limited static dynamic t lt
9. 0 85 x Imax OUTx max OUTy 0 8x Imax OUTx max OUTy Imax OUTz 0 75 x ECI OUTx Ecl OUTy 0 58 x Ecl ouTx t Ecl OUTy ECI OUTZ 0 5 x Ron OUTx y 0 34 x Ron OUTx yz 2 PS with the same nominal current but different clamp ing voltage application with out free wheeling diode see note 3 0 7 x Imax OUTx t Imax OUTy Clamping energy of the PS with the lower clamping voltage Ron OUTx X Ron OUTy Ron OUTx t Ron OUTy 2 PS with the same nominal current but different clamp ing voltage application with free wheeling diode see note 3 0 7 x Imax OUTx Imax OUTy no clamping required Ron OUTx X Ron OUTy Ron Ax Ron OUTy 2 PS with the same clamp ing voltage but different Imax OUTx Te 7 OUR Rang nominal Max les OUTy T CI OUTx aon x aon Y 0 E on OUTx on OUTy current see note 4 CI OUTy 0 75 x Imax OUTx t L u Imax OUTy 2 PS with different nominal Clamping energy current and different clamp of the PS with the lower P lu Imax OUTx Ron OUTx X Ron OUTy ing voltage see note 5 ax d clamping voltage max OUTy Ron OUTx t Ron OUTy Final Data Sheet 40 V4 2 2003 08 29 e Infineon technologies TLE 6244X note 1 For every PS there exists only one symmetrical PS OUT1 and OUT2 are symmetrical PS OUT3 and OUT4 are symmetrical PS OUTI7 and OUT18 are symmetrical PS note 2 PS of the same
10. 1 1 5 Power Stage OUT8 OUTS can be controlled by SPI or by the pin IN8 only When controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3 5V OUTS will not be reset by RST In SPI mode the power stage is fully supervised by the VDD monitor Final Data Sheet 2 V4 2 2003 08 29 TLE 6244X technologies 1 2 Block Diagram fault iagnostics OUT1 IN1 2 2A TOV IN2 2 2A 70V OUT2 IN3 2 2A 70V OUT3 IN4 2 2A 70V OUT4 INS 2 2A 70V OUT5 ING 2 2A 70V OUT6 IN7 OUT7 IN8 1 1A 45V OUT8 IN9 2 2A 45V OUT9 IN10 L 2 2A 1 45V OUT 10 IN11 H 2 2A 45V OUT 11 IN12 M 2 2A 45V OUT 12 IN13 M 2 2A 45V OUT 13 OUT 14 IN15 LI 3 0A 45V OUT15 IN16 LH 3 0A 45V OUT16 1 1A 45V OUT17 1 1A 45V OUT18 e VDD Moni VDD Pan toring ABE SS SO ST GND1 8 GND ABE Final Data Sheet 3 V4 2 2003 08 29 technologies TLE 6244X 1 3 Description of the Power Stages OUT1 OUT6 6 non inverting low side power switches for nominal currents up to 2 2A Control is possible by input pins by the usec bus or via SPI For Ty 25 C the on resistance of the power switches is below 400m4 An integrated zener diode limits the output voltage to 70V typically A protection for inverse current is implemented for OUT1 OUT4 for use as stepper motor con trol OUTS OUT14 6 non inverting low side power switches for nominal currents up to
11. approximately linear characteristic line can be assumed 3 8 3 1 Maximum See Note 1 11 1 C UouT 36 V Battery Volt 17 18 age at Short Circuit to Bat tery 3 8 4 Shutoff Delay Shutoff delay of the power stages B tvort 60 215 us after detection of SCB For the duration of typf current is limited to maximum current Final Data Sheet 55 V4 2 2003 08 29 technologies 3 8 5 On Resis tance 3 8 6 On off Delay Times 3 8 7 Leakage Cur rent 3 8 8 Clamping 3 8 8 1 Clamping Voltage 3 8 8 2 Maximum Clamping En ergy Tc lt 110 C 3 8 8 3 Maximum Clamping En ergy Tc lt 60 C TLE 6244X Ty 25 C A Ronzs 400 620 780 ma 17 18 Ty 150 C A Ronz 780 1200 1500 mQ 17 18 Ty 40 C A Ronzs 290 450 560 ma 17 18 For UyBatt 10V Ron is increased up to 20 condition Uypp gt 4 5 V For OUTS8 only 3 5V Uypp UuBatt lt 4 5V Ty 25 C A Ron 1300 mo T 150 C A Ron 2200 ma Tj 40 C A Ron 1050 mQ On B tdon 10 us B tson 5 us Off B tdoff 10 HS Measurementwithohmicload C tsoff 10 us Itdon taorrl C Atg 5 HS Switch on slew rate C Son 25 V s Switch off slew rate C Soff 40 V s For OUT7 8 OUT1718 Uvpp OV Uouri 14V leakage A louri 50 HA current of the DMOS diagnostic current 0 Uvpp OV Uouri 24V leakage A louri 200 HA current of the DMOS diagnostic current 0 For OUT7 8 OUT17 18 loUTi 0 2A A Uouri 4
12. crocontroller TLE6244X always operates in slave mode whereas the controller provides the mas ter function The maximum baud rate is 5 MBaud EN The TLE6244X is selected by the SPI master by an active slave select signal at SS and by the first two bits of the SPI instruction Sl is the data input Slave In SO the data output Slave Out Via SCK Serial Clock Input the SPI clock is provided by the master In case of inactive slave select signal High the data output SO goes into tristate Block Diagram Power Stages 1 18 Power Stages 1 16 SCON REG1 3 MUX REG1 2 SPI Control State Machine Clock Counter Control Bits SI O Parity Generator STATCON_REG DIA_REG1 5 VDD Monitoring Power Stages 1 18 Final Data Sheet 9 V4 2 2003 08 29 TLE 6244X technologies A SPI communication always starts with a SPI instruction sent from the controller to TLE6244X During a write cycle the controller sends the data after the SPI instruction beginning with the MSB During a reading cycle after having received the SPI instruction TLE6244X sends the correspond ing data to the controller also starting with the MSB SPI Command Format MSB 7 6 5 4 3 2 1 0 0 0 INSTR4 INSTR3 INSTR2 INSTR1 INSTRO INSW Bit Name Description 7 6 CPAD1 0 Chip Address has to be 0 0 5 1 INSTR 4 0 SPI instruction encoding 0 INSW Parity of the instruction
13. 08 29 TLE 6244X technologies 3 9 1 Input SCK SPI clock input 3 9 1 1 Low Level B UsckL 1 0 V 3 9 1 2 High Level B Uscku 20 V 3 9 1 3 Hysteresis C AUsck 0 1 0 6 V 3 9 1 4 Input Capacity C Csck 10 pF 3 9 1 5 Input Current Pull up current source connected A lsck 10 20 50 HA to VDD 3 9 2 Input ss Slave select signal 3 9 2 1 Low Level TLE6244X is selected B UssL 1 0 V 3 9 2 2 High Level B UssH 2 0 V 3 9 2 3 Hysteresis C AUss 0 1 0 6 V 3 9 2 4 Input Capaci C Css 10 pF ty 3 9 2 5 Input Current Pull up current source connected A lss 10 20 50 HA to VDD 3 9 3 Input SI SPI data input 3 9 3 1 Low Level B UsiL 1 0 V 3 9 3 2 High Level B UsiH 2 0 V 3 9 3 3 Hysteresis C AUgi 0 1 0 6 V 3 9 3 4 Input Capaci C Cg 10 pF ty 3 9 3 5 Input Current Pull up current source connected A lsi 10 20 50 HA to VDD 3 9 4 Output SO Tristate output of the TLE6244X SPI output On active reset RST output SO is in tristate 3 9 4 1 Low Level Iso 2mA A UsoL 0 4 V 3 9 4 2 High Level Iso 2mA A UsoH Uvpp V 1 0 3 9 4 3 Capacity Capacity of the pin in tristate C Cso 10 pF 3 9 4 4 Leakage Cur In tristate A Iso 10 10 pA rent Final Data Sheet 59 V4 2 2003 08 29 technologies 3 9 5 Timing 1 Cycle Time B t cyc 200 ns referred to master 2 Enable Lead Time C t lead 100 ns referred to master 3 Enable Lag Time C t lag 150 ns referred to master 4 Data Valid CL 50pF 5 MHz C ty
14. 2 2A Control is possible by input pins by the usec bus or via SPI For Ty 25 C the on resistance of the power switches is below 380m An integrated zener diode limits the output voltage to 45V typically OUT15 OUT16 2 non inverting low side power switches for nominal currents up to 3 0A Control is possible by input pins by the usec bus or via SPI For Ty 25 C the on resistance of the power switches is below 280mQ An integrated zener diode limits the output voltage to 45V typically OUT7 OUT8 OUT17 OUT18 4 low side power switches for nominal currents up to 1100mA Stage 7 is non inverting Stage 8 is inverting IN8 1 gt OUT8 is active For the output OUT7 control is possible by the input pin by the usec bus or via SPI OUT8 is controlled by the input pin IN8 or via SPI for the outputs OUT 17 and OUT18 control is only possible via SPI For Ty 25 C the on resistance of the power switches is below 780mQ An integrated zener diode limits the output voltage to 45V typically In order to increase the switching current or to reduce the power dissipation parallel connection of power stages is possible for additional information see 1 13 The power stages are short circuit proof Power stages OUT1 OUT8 OUT11 14 In case of overload SCB they will be turned off after a given delay time During this delay time the output current is limited by an internal current control loop Power stages OUT9 OUT10 OUT15 OUT1
15. 2ms Max clamping voltage lini 5mA lini 2mA t lt 2ms External current limitation at INi is only provided if usec bus control is used In that case INi are used as digital inputs If usec bus is not used there is no external resistor for current limitation See 2 4 Inputs of the Power Switches SPI Inputs In case of open input parallel con trol or missing power supply the power stage is switched off Paral lel connection of power stages is possible louT1 6 gt 2 2A Accumulated operating time 45V lt Uupatt lt 17V Tj 40 C Tj 150 C UuBatt gt 21V T 40 C T 150 C Above this limit short circuit to UBatt is detected For the duration of the shutoff delay time tyop see 3 5 4 the output current is limited to approximately this value If the short circuit condition is still present after tvorr the output is switched off An error is stored after tpiag see 3 11 4 lOUT1 6 louT1 6 louT1 6 louT1 6 louT1 6 3 40 2 4 2 7 70 2 2 100 4 0 3 7 5 0 4 6 mA mA Final Data Sheet 46 V4 2 2003 08 29 technologies 3 5 3 1 Maximum Battery Volt age at Short Circuit to Bat tery 3 5 4 Shutoff Delay 3 5 5 On Resis tance 3 5 6 On off Delay Times TLE 6244X Between 40 C and 150 C an approximately linear characteristic line can be assumed for the short circuit shutdown threshold
16. Ag Mejdw x pajajap Ayu Belj Lo dsas gos gos jo ases ui UONeJiwWIi JUNI 10 powwesboid abe s amod 81 GL0L GLNO SABEIS amod jo yoda YIS JO 2neuieu s Infineon technologies e 29 V4 2 2003 08 26 Final Data Sheet TLE 6244X technologies Reading Input1 SPI Instruction RD INP1 Register INP REG1 7 6 5 4 3 2 1 0 IN8 Test 0 IN5 INA IN3 IN2 IN1 Bit Name Description 0 4 IN 1 5 Status of the input pins IN1 IN5 5 No function LOW on reading 6 Test usec test bit the bit D8 of the pusec bus is read 7 IN8 Inverted status of the input pin IN8 Low level at pin IN8 Bit 7 1 High level at pin IN8 Bit 7 0 Reading Input2 SPI Instruction RD INP2 Register INP REG2 7 6 5 4 3 2 1 0 0 IN15 IN14 IN13 IN12 IN11 IN10 IN9 Bit Name Description 0 6 IN9 IN15 Status of the input pins IN9 IN15 7 No function LOW on reading The input pins IN1 IN5 and IN8 IN15 can be used as input port expander by reading the status of the input pins using the SPl commands RD INP1 2 If the usec bus interface is enabled BMUX 0 the pull up current sources at the input IN1 5 and IN9 15 are disabled If BMUX 1 the pullup current sources at these pins are enabled The pull up pull down current sources of the other input pins are not effected by the bit BMUX On executing the read instruction on RD I
17. DIA 25 24 Diagnostic Bits of power stage 13 3 2 DIA 27 26 Diagnostic Bits of power stage 14 5 4 DIA 29 28 Diagnostic Bits of power stage 15 7 6 DIA 31 30 Diagnostic Bits of power stage 16 Final Data Sheet 18 V4 2 2003 08 29 TLE 6244X technologies Register DIA REG5 7 6 5 4 3 2 1 0 1 1 1 UBatt DIA35 DIA34 DIA33 DIA32 State of Reset FFH Access by Controller Read only Bit Name Description 1 0 DIA 33 32 Diagnostic Bits of power stage 17 3 2 DIA 35 34 Diagnostic Bits of power stage 18 4 UBatt 0 Voltage Level at Pin UBatt is below 2V typically 1 Voltage Level at Pin UBatt is above 2V typically Diagnosis of UBatt is only possible if Uypp gt 4 5V Status of UBatt is not latched 7 5 No function High on reading Encoding of the Diagnostic Bits of the Power Stages DIA 2 x 1 DIA 2 x 2 State of power stagex x 1 18 1 1 Power stage o k 1 0 Short circuit to Ugatt SCB OT 0 1 Open load OL 0 0 Short circuit to ground SCG Final Data Sheet 19 V4 2 2003 08 29 technologies TLE 6244X 1 6 3 Configuration The psec bus is enabled by this register In addition the shut off at SCB can be configured for the power stages OUT9 OUT10 and OUT15 OUT18 CONFIG Read and write 7 6 5 4 3 2 1 O16 SCB O15 SCB O10 SCB O9 SCB
18. HA IABE 300 HA w oo Final Data Sheet 64 V4 2 2003 08 29 technologies 3 13 4 Undervolt age Thresh old 3 13 5 Test Mode Reducing the Overvoltage Threshold 3 13 6 Test Mode Lifting the Undervoltage Threshold 3 13 7 Suppres sion of Glitches 3 13 8 GND_ABE 3 13 8 1 Permissible Offset be tween__ GND_ABE and GND 3 13 8 2 Bond Lift Solder Crack on GND_ABE Final Data Sheet TLE 6244X Voltage referred to GND_ABE Voltage referred to GND_ABE Voltage referred to GND_ABE Periodical alternating between overvoltage and normal operating voltage with T lt 50us and overvolt age duration gt 5us leads to over voltage detection If the transition from undervoltage to overvoltage is faster than the fil tering time tglitch the filtering time talitch for overvoltage detection is not started again The same is valid for reverse order Pin ABE goes LOW see 3 13 1 1 The power stages are switched off The over and undervoltage thresholds are increased by typi cally 700mV for T4 25 C 65 Vopth_ Vopth_h Voot 1 tglitch AUawp 4 5 4 5 5 3 50 4 7 V 4 7 V 5 5 V 215 us 0 3 V V4 2 2003 08 29 e Infineon technologies TLE 6244X 3 14 Clamping Energy 3 14 1 E f lour1 6 2 24 Power Stages with 70V Clamping A E mJ J Injector Drivers Clamping Voltage 64 76V ag 5 fma
19. MUX REG1 WR MUX2 00 10011 1 write into MUX REG2 WR SCON1 00 10100 0 write into SCON REG1 WR SCON2 00 10101 1 write into SCON REG2 WR SCON3 00 10110 1 write into SCON_REG3 WR_COMFIG 00 10111 0 write into CONFIG RD MUX1 00 00010 1 read MUX REG1 RD MUX2 00 00011 0 read MUX REG2 RD SCON1 00 00100 1 read SCON REG1 RD SCON2 00 00101 0 read SCON_REG2 RD SCON3 00 00110 0 read SCON_REG3 RD STATCON 00 00111 1 read STATCON REG DEL DIA 00 11000 0 resets the 5 diagnostic registers DIA REG RD DIA1 00 01000 1 read DIA REG1 RD DIA2 00 01001 0 read DIA REG2 RD DIA3 00 01010 0 read DIA REG3 RD DIA4 00 01011 1 read DIA REG4 RD DIA5 00 01100 0 read DIA REG5 RD CONFIG 00 01101 1 read CONFIG RD INP1 00 01110 1 read INP REG1 RD INP2 00 01111 0 read INP REG2 all others no function Final Data Sheet 12 V4 2 2003 08 29 technologies TLE 6244X 1 6 1 Serial Parallel Control Serial Parallel Control of the Power Stages 1 16 and Serial Control SPI of the Power Stages 17 and 18 The registers MUX_REG1 2 and the bmux bit prescribe parallel control or serial control SPI or usec bus of the power stages SPl Instructions WR MUX1 2 RD MUX4 2 WR SCONT1 3 RD_SCON1 3 The following table shows the truth table for the control of the power stages 1 18 The registers MUX REG 1 2 prescribe parallel control or serial control of the power stages The registers SCON_REG1 3 prescribe the state of the power stage in
20. O18 SCB O17 SCB BMUX State of Reset FFh Bit Name Description 0 No function HIGH on reading 1 BMUX 1 parallel inputs INx enabled 0 usec Bus Interface enabled 2 O17 SCB 1 The output OUT17 is switched off in case of SCB 0 The output is not switched off in case of SCB 3 O18 SCB 1 The output OUT18 is switched off in case of SCB 0 The output is not switched off in case of SCB 4 O9 SCB 1 The output OUTO9 is switched off in case of SCB 0 The output is not switched off in case of SCB 5 O10 SCB 1 The output OUT10 is switched off in case of SCB 0 The output is not switched off in case of SCB 6 O15 SCB 1 The output OUT15 is switched off in case of SCB 0 The output is not switched off in case of SCB 7 O16 SCB 1 The output OUT 16 s switched off in case of SCB 0 The output is not switched off in case of SCB Description of the usec bus see chapter 1 7 Final Data Sheet 20 V4 2 2003 08 29 TLE 6244X technologies 1 6 4 Other Reading the IC Identifier SPI Instruction RD_IDENT1 IC Identifier1 Device ID 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 IDO Bit Name Description 7 0 ID 7 0 ID No 10101000 Reading the IC revision number SPI Instruction RD IDENT2 IC revision number 7 6 5 4 3 2 1 0 SWR3 SWR2 SWR1 SWRO MSR3 MSR2 MSR1 MSRO Bit Name Description 7 4 SWR 3 0 Revision corresponding
21. TLE 6244X 3 7 Power outputs 3 0A 45V OUT15 OUT16 3 7 1 Nominal Cur rent 3 7 2 Extended Cur rent Range 3 7 3 Maximum Current Short Circuit Shut down threshold 3 7 3 1 Maximum Battery Volt age at Short Circuit to Bat tery 3 7 4 Shuttoff Delay In case of open input parallel con trol or missing power supply the power stage is switched off Paral lel connection of power stages is possible louT15 16 gt 3 0A Accumulated operating time Uupatt gt 4 5V T 2 40 C T 150 C Above this limit short circuit to UBatt is detected For the duration of the shutoff delay time tyop see 3 6 4 the output current is limited to approximately this value If the short circuit condition is still present after tyof the outputs OUT15 16 are switched off if the static current limitation is not enabled An error is stored after tpiag see 3 11 4 Above this limit short circuit to UBatt is detected The output cur rent is limited to approximately this value if the static current limitation is configured An error is stored after tpiag see 3 11 4 If the oper ation leads to an overtemperature condition a second protection level about 170 C will change the output into a low duty cycle PWM selective thermal shutdown with restart to prevent critical chip tem peratures Between 40 C and 150 C an approximately linear characteristic line can be assumed See Note 1 11 1 Shutoff de
22. a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Final Data Sheet 70 V4 2 2003 08 29
23. b E 95 DOO OUO UU OU UU g W E m o u V h la x STOFG G H Im L Q ari c ag viwe oz zm o 8 pOg Z impu presby 2 MU CT HL A O SJ 10 21 o 7 SMS Os a y 82 Do X E o a G ce o 8 Z 9 S n 2 Te Final Data Sheet e Infineon technologies TLE 6244X Edition 2003 08 29 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 M nchen Germany Infineon Technologies AG 11 28 03 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if
24. initialization of TLE6244X Power stage 8 however is not influenced by the reset input if it s controlled by IN8 and Uypp gt 3 5V Alternatively these outputs can be controlled either by the pins IN1 IN16 or by the usec bus interface Exception OUT8 can be controlled by IN8 or by the SPl interface only The bit Bus Multiplex BMUX in the SPI register CONFIG prescribes parallel access IN1 IN7 IN9 IN16 or usec bus control see figure below Exception If BMUX is set to 0 only the power stages OUT1 0UT7 and OUT9 OUT16 are controlled by the usec bus Main features 16 data bits for each data frame at the pin FDA 16 clock pulses for each data frame at the pin FCL clock frequency TLE6244 0 16 MHz one sync input pin SSY to latch the input data stream input level interface same as for IN6 IN7 IN16 no error correction Data Frame SSY T FCL FDA x be DO D1 x D14 D15 X don t care X DO I INx BMUX FDA FCL 16 bit shift register i OUTx Glitch x lt SSY Filter 16 bit usec bus Reg D rH SCON REG gt SPI shift reg MUX REG Principle of the psec bus interface Final Data Sheet 30 V4 2 2003 08 29 TLE 6244X technologies When the bit BMUX in CONFIG is set to Low the power s
25. lout 270 580 980 HA rent incl leakage current Uour1 18 OV A lout 50 130 250 HA UouT1 18 OL Threshold C lout 220 980 HA Uour1 18 SCG Threshold C lour 40 250 pA Final Data Sheet 62 V4 2 2003 08 29 technologies TLE 6244X 3 11 4 Filtering Time from occurrence of one of B tDiag 60 240 us Time Power the errors short to ground open Switches load or short to battery until the fault is entered into the corre sponding diagnostic register Time from occurrence of OT until C tDiatOT 3 30 us the information is entered into the corresponding diagnostic register 3 11 5 Diagnostic Bit Ubatt in DIA REG5 Uth uB 1 9 V Threshold UBatt 3 12 Reverse Cur rents Uypp lt 1V 3 12 1 Reverse Cur Static C doie 3 A rent at C loo 16 3 A OUT1 18 C lors 0 8 A without Sup C lois 0 8 A ply Voltage Dynamic C lore 10 A Test pulse 1 according to ISO C loo 16 10 A 100V R 10W 2ms C loza 1 5 A C lom 18 45 A 3 12 2 Reverse Cur 4 5V Uypp x 5 5V rent at Pulsed power stage OUT1 0UT18 Neighboring stages reset input in Operation signals of the power stages VDD Mode monitoring SPI interface incl reg isters and usec bus must not be disturbed Diagnostics of fault con ditions at neighboring stages is still possible Control bits in the SPI registers serial control of power stages are not disturbed Open load failure at neighboring C lo1 16 1 A stages may be d
26. parallel control of power stage 5 5 MUX5 Serial or parallel control of power stage 6 6 MUX6 Serial or parallel control of power stage 7 7 MUX7 Serial or parallel control of power stage 8 Register MUX REG2 7 6 5 4 3 2 1 0 MUX15 MUX14 MUX13 MUX12 MUX11 MUX10 MUX9 MUX8 State of Reset OOH Access by Controller Read Write Bit Name Description 0 MUX8 Serial or parallel control of power stage 9 1 MUX9 Serial or parallel control of power stage 10 2 MUX10 Serial or parallel control of power stage 11 3 MUX11 Serial or parallel control of power stage 12 4 MUX12 Serial or parallel control of power stage 13 5 MUX13 Serial or parallel control of power stage 14 6 MUX14 Serial or parallel control of power stage 15 7 MUX15 Serial or parallel control of power stage 16 Final Data Sheet 14 V4 2 2003 08 29 TLE 6244X technologies Register SCON_REG1 7 6 5 4 3 2 1 0 SCON7 SCONG SCON5 SCON4 SCON3 SCON2 SCON1 SCONO State of Reset FFH Access by Controller Read Write Bit Name Description 0 SCONO State of serial control of power stage 1 1 SCON1 State of serial control of power stage 2 2 SCON2 State of serial control of power stage 3 3 SCON3 State of serial control of power stage 4 4 SCON4 Sta
27. type have the same nominal current and the same clamping voltage note 3 Parallel connection of PS type 2 2A 45V with type 2 2A 70V note 4 Parallel connection of PS type 2 2A 45V with type 3 0A 45V or Parallel connection of PS type 1 1A 45V with type 2 2A 45V note 5 Parallel connection of PS type 2 2A 70V with type 1 1A 45V or Parallel connection of PS type 2 2A 70V with type 3 0A 45V If the power stages are configured for static current limitation the max current limitation of the parallel connected PS is the summation of the corresponding max values of the PS Isc ourx t lsc outy The following statements apply to Power Stages within different TLE6244X The application has to take into account that all maximum ratings of each TLE6244X are observed Final Data Sheet 41 V4 2 2003 08 29 TLE 6244X technologies 2 Maximum Ratings 2 1 Definition of Test Conditions The integrated circuit must not be destroyed if maximum ratings are reached Every maximum rating is allowed to reach as far as no other maximum rating is exceeded Unless otherwise indicated all voltages are referred to GND GND pins 1 8 connected to each other Positive current flows into the pin 2 2 Test Coverage TC in Series Production In the standard production flow not all parameters can be covered due to technical or economic reasons Therefore the following test coverage was defined A Parameter test B Go NoGo test in the c
28. 0 45 50 V Linear decreasing current fmax 10Hz see diagrams E f l on page 67 louri 0 6A C E 10 mJ louri lt 1 1A C E 7 mJ Linear decreasing current fmax 10Hz louri lt 0 6 C E 12 mJ louti lt 1 1A C E 8 5 mJ Final Data Sheet 56 V4 2 2003 08 29 TLE 6244X technologies 3 8 8 4 Maximum Each output 75 of the values of C Clamping En 3 8 8 2 resp 3 8 8 3 ergy with two Outputs con nected in par allel 3 8 8 5 Maximum For a maximum of 10 times during C E 15 mJ Clamping En ECU life load dump with 400ms ergy atLoad and Ri 20 over the load Dump 3 8 8 6 Jump Start Each output 150 of the values of C 3 8 8 3 For a maximum of 10 jump starts of 2 minutes each during ECU life Final Data Sheet 57 V4 2 2003 08 29 TLE 6244X technologies 3 9 SPI Interface The timing of TLE6244X is defined as follows The change at output SO is forced by the rising edge of the SCK signal The input signal Sl is sampled on the falling edge of the SCK signal The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal if exactly 16 SPI clocks have been counted during SS active Also Only if exactly 16 SPI clocks have been counted the instruction DEL_DIA resets the diagnostic regis ters tristate Final Data Sheet 58 V4 2 2003
29. 100 ns Data Valid CL 200pF 2MHz C ty 150 ns referred to TLE6244X 5 Data Setup Time C t su 50 ns referred to master 6 Data Hold Time C th 20 ns referred to master 7 Disable Time C t dis 100 ns referred to TLE6244X 8 Transfer Delay C tat 150 ns referred to master 9 Select time C t sel 50 nsec referred to master 10 Access time C tcs 8 35 usec referred to master 11 Serial clock high time C teckH 50 ns referred to master 12 Serial clock low time C tsckL 120 ns C 13 Disable Lead Time tala 250 ns C 14 Disable Lag Time taig 250 ns Final Data Sheet 60 V4 2 2003 08 29 TLE 6244X technologies 3 10 usec bus lt Fouts STNO Z N X GM 2 I gt oW tswitch tsetup FDA IN6 I ni tSF I SSY IN7 LA Timing usec bus Notes for the timing Timing definitions are starting or ending at a voltage level of 1V Low Level resp 2V High Level During SSY high the clock at FCL may be interrupted i e there is no need for a clock during SSY high The clock signal may remain on high or low statically during SSY high A rising edge at SSY and a falling edge at FCL must not occur simultaneously On the rising edge of SSY the 16 bits clocked in TLE6244X by the last 16 falling edges at FCL are latched 3 10 1 Input FCL psec bus interface pins FDA SSY 3 10 1 1 Low Level B Urcu 1 0 V UrpAI Ussvi 3 10 1 2 High Level B Urci
30. 2 must not be activated even if slave select is set to low and the first two bits of the third byte of the 32bit transmission are identical to the chip address of TLE6244X During the transmission of CPAD1 and CPADO the data output SO remains in tristate see timing diagram of the SPI in chapter 3 9 SPI access format WRITE access 16bit READ access 16bit 8 bit command 8bit data 8 bit command 8bit data si SPI instruction Data 8bit si SPI instruction XX XX XX XX MSB MSB MSB SO Check byte 00 00 00 00 SO Check byte Data 8bit ZZ 6bit ZZ 6bit MSB Z tristate Verification byte MSB 7 6 5 4 3 2 1 0 z z 1 0 1 0 1 TRANS_F Bit Name Description 0 TRANS_F Bit 1 error detected during previous transfer Bit 0 previous transfer was recognised as valid State after reset 0 1 Fixed to High 2 Fixed to Low 3 Fixed to High 4 Fixed to Low 5 Fixed to High 6 send as high impedance 7 send as high impedance Final Data Sheet 11 V4 2 2003 08 29 TLE 6244X technologies SPI Instructions SPI Instruction Encoding Description bit 7 6 bit 5 4 3 2 1 Parity CPAD1 0 INSTR A 0 RD IDENT1 00 00000 0 read identifier 1 RD IDENT2 00 00001 1 read identifier2 WR STATCON 00 10001 0 write into STATCON REG WR MUX1 00 10010 0 write into
31. 244X technologies 1 Description 1 1 Short Description This circuit is available in MQFP64 package or as chip 1 1 1 Features of the Power Stages Nominal Current Ron max at Ty 25 C static current limita Clamping tion enabled by SPI OUT1 2 5 6 2 2A 400m0 70V OUT3 OUT4 2 2A 380MQ 70V OUT7 OUT8 1 1A 780mQ 45V OUT9 OUT10 2 2A 380mQ X 45V OUT11 0UT14 2 2A 380MQ 45V OUT15 OUT16 3 0A 280mo X 45V OUT17 OUT18 1 1A 780MQ X 45V only serial control possible via SPI Parallel connection of power stages is possible see 1 13 Internal short circuit protection Phase relation non inverting exception IN8 2OUTS8 is inverting 1 1 2 Diagnostic Features The following types of error can be detected Short circuit to Ugatt SCB Short circuit to ground SCG Open load OL Overtemperature OT Individual detection for each output Serial transmission of the error code via SPI 1 1 3 VDD Monitoring Low signal at pin ABE and shut off of the power stages if VDD is out of the permitted range Exception If OUTS is controlled by IN8 OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection The state of VDD can be read out via SPI 1 1 4 psec bus Alternatively to the parallel and SPI control of the power stages a high speed serial bus inter face can be configured as control of the power stages OUT1 OUT7 and OUT9 OUT16
32. 3 6 1 Nominal Cur rent 3 6 2 Extended Cur rent Range 3 6 3 Maximum Current Short Circuit Shut down Threshold In case of open input parallel con trol or missing power supply the power stage is switched off Paral lel connection of power stages is possible louri gt 2 2A Accumulated operating time 4 5V Uypatt 17V for OUT11 14 4 5V Uypatt for OUT9 10 T 40 C T 150 C Uypatt gt 21V for OUT11 14 Tj 40 C T 150 C For OUT11 OUT14 Above this limit short circuit to UBatt is detected For the duration of the shutoff delay time tyop see 3 6 4 the output current is limited to approximately this value If the short circuit condition is still present after tyof the outputs OUT11 OUT14 are switched off An error is stored after tDiag see 3 11 4 The same is true for OUTY OUT 10 if the static current limita tion is not enabled Between 40 C and 150 C an approximately linear characteristic line can be assumed Between 17V x Uypat lt 21V the short circuit shutdown threshold is switched for OUT11 14 louTo 14 louti louti louti louti 2 2 2 7 2 2 A 100 h 3 8 A 3 7 A 5 A 4 6 A Final Data Sheet 49 V4 2 2003 08 29 technologies 3 6 3 1 Maximum Battery Volt age at Short Circuit to Bat tery 3 6 4 Shutoff Delay 3 6 5 On Resis tance TLE 6244X A power stage that is switched off i
33. 5 1 OUT15 1 2 Output 15 2 OUT15 2 3 Output 16 1 OUT16 1 51 Output 16 2 OUT16 2 50 Output 17 OUT17 25 Output 18 OUT18 28 Note OUTxy 1 and OUTxy 2 have to be connected externally Slave Select SS 56 Serial Output SO 53 Serial Input SI 55 SPI Clock SCK 54 Final Data Sheet V4 2 2003 08 29 TLE 6244X technologies Supply Voltage VDD VDD 47 Supply Voltage Upatt Ubatt 23 GND1 GND1 26 GND2 GND2 27 GND3 GND3 58 GND4 GND4 59 GND5 GND5 11 GND6 GND6 12 GND7 GND7 42 GND8 GND8 41 Sense Ground VDD Monitoring GND ABE 29 In Output VDD Monitoring ABE 30 Reset low active RST 31 not connected nc 21 24 32 52 64 O TE 1 IN15 nc 52 2 OUTI5_1 OUTI6 1 51 3 OUTIS5 2 OUTI6 2 50 4 OUTII OUTI2 49 5 IN11 IN12 48 6 INS VDD 47 7 IN IN2 46 8 OUTI OUT2 45 9 OUT3 OUT4 44 10 IN3 IN4 43 11 GNDS HiQUAD64 GND7 42 12 GND6 GND8 41 13 INI3 IN14 40 14 OUTI3 1 OUT14 1 39 15 OUTI3 2 OUT14 2 38 16 OUTS_1 OUT6_1 37 17 OUTS 2 OUT6_2 36 18 OUT9 1 OUT10_1 35 19 OUT9 2 OUT10 2 34 20 IN9 IN10 33 o o
34. 8 In case of SCB these power stages can be configured for a shut down mode or for static current limitation In the shut down mode while SCB they will behave like OUT1 8 or OUT11 14 In case of static current limitation and SCB the current is limited and the corresponding bit com bination is set early warning after a given delay time They will not be turned off If this condition leads to an overtemperature condition the output will be set into a low duty cycle PWM selective thermal shut down with restart to prevent critical chip temperature There are 3 possibilities to turn the power stages on again turn the power stage off and on either via serial control SPI or via parallel control input pin except outputs OUT 17 and OUT18 or by the usec bus except OUT8 OUT17 OUT 18 applying a reset signal sending the instruction del dia by the SPl interface The VDD monitoring locks all power stages except OUT8 for access by the IN8 input OUTS is locked by an internal threshold of 3 5V maximum when controlled by IN8 Otherwise OUT8 is locked by the VDD monitor Final Data Sheet 4 V4 2 2003 08 29 TLE 6244X technologies All low side switches are equipped with fault diagnostic functions short circuit to Ugat SCB can be detected if switches are turned on short circuit to ground SCG can be detected if switches are turned off open load OL can be detected if switches are turned off overtemperatur
35. 80 mO 390 480 mQ 170 210 mQ 10 us 5 us 10 us 10 us 5 us 20 V us 25 V us 50 HA 200 HA 45 50 V 18 mJ 20 mJ 24 mJ 40 mJ 20 mJ 46 mJ Final Data Sheet 53 V4 2 2003 08 29 technologies TLE 6244X 3 7 8 5 Maximum For a maximum of 10 times during E 50 mJ Clamping En ECU life load dump with 400ms ergy atLoad and Rj 20 over the load e g 2W Dump lamp 3 7 8 6 Jump Start Each output 150 of the values of 3 7 8 3 For a maximum of 10 jump starts of 2 minutes each during ECU life 3 7 8 7 Singlepulse lour45 16 lt 0 6A max 10 000 E 50 mJ Tc lt 60 C pulses 3 8 Power Outputs In case of open input parallel con 1 1A 45V trol or missing power supply the OUT7 8 power stage is switched off Paral OUT17 18 lel connection of power stages is possible 3 8 1 Nominal Cur for OUTT 8 17 18 louti 1 1 A rent 3 8 2 Extended Cur loUT7 8 17 18 gt 1 1A rent Range Accumulated operating time 100 h 3 8 3 Maximum 4 5V Uypat 17V for OUT7 8 Current 4 5V Uypat for OUT17 18 Short Circuit Shut down Ty 40 C louri 1 2 2 2 A Threshold Ty 150 C louti 1 1 2 0 A and static current limita tion Uysatt gt 21V only for OUT7 8 Ty 40 C louri 1 5 2 5 A Ty 150 C louti 1 3 2 3 A For OUT7 OUT8 Above this limit short circuit to UBatt is detected For the duration of the shutoff delay time tvor see 3 8 4 the output current is limited to approximately this val
36. NP1 2 the present status not latched of the input pins INx is read back exception bit IN8 represents the inverted status of input pin IN8 Final Data Sheet 27 V4 2 2003 08 29 TLE 6244X technologies Reading the State resp the Configuration SPI Instructions WR_STATCON RD_STATCON Register STATCON_REG 7 6 5 4 3 2 1 0 CONFIG2 CONFIG1 CONFIGO STATUS4 STATUS3 STATUS2 STATUS1 STATUSO Bit Name Description 0 STATUSO Bit 1 No overvoltage at VDD Bit 0 Overvoltage at VDD resp state of overvoltage still stored reset by CONFIGO 0 Access by Controller Read only Overvoltage information bit STATUSO 0 will not be reset by an external reset signal pin RST low Overvoltage will be detected and stored CONFIGO 1 during RST low The information will be deleted when an internal undervoltage reset occurs or when CONFIGO is set to 0 1 STATUS1 Bit 1 No undervoltage at VDD Bit 0 Undervoltage at VDD Access by Controller Read only 2 STATUS2 Reading the voltage level at ABE Access by Controller Read only 3 STATUS3 Common error flag Bit 1 At present no error is entered in one of the 5 diag nostic registers DIA_REG1 5 Bit 0 For at least at one power stage an error has been detected and entered in the corresponding diagnostic register Access by Controller Read only 4 STATUS4 Common overtemperature flag Bit 1 No overtemperature d
37. Np4 2 18 A total ground current of OUT5 6 9 10 17 18 Total current GND3 4 pins 58 59 lenp3 4 lt 20 A total ground current of OUT1 2 7 8 11 12 15 16 Total current GND5 6 pins 11 12 lenps 6 lt 6 A total ground current of OUT3 13 Total current GND7 8 pins 41 42 IGnp7 8 lt 6 A total ground current of OUTA 14 Attention Even if all ground pins are connected with each other on the PCB the total ground currents lenp1 2 and lenp3 4 and lsNps 6 and Ienp7 g must not be exceeded The 4 ground pins GND1 4 are internally connected to the heat sink via an unspecified rivet joint Therefore it is advisable to short circuit the 4 ground pins on the PCB and to connect them with the heat sink In addition the 4 ground pins GND5 8 must be connected to the other ground pins on the PCB Inputs of the Power Switches SPI Inputs Reset and Shut off of the Power Stages Input voltage 0 3V UINi RSTSS SI SCK ABE lt 36V Input currents see 3 4 4 3 9 1 3 9 2 3 9 3 3 13 2 Pin RST Minimum reset duration Power On 15 ms Input currents see 3 4 4 Final Data Sheet 43 V4 2 2003 08 29 technologies TLE 6244X 3 Electrical Characteristics 3 1 Operating Range see also 3 13 VDD monitoring ABE Out of this range the power stages can be shut off by the VDD moni toring except OUT8 Voltage referred to GND_ABE Minimum reset duration Power On Minimum reset duration in operation mode 4 5V Uyp
38. OUT9 and OUT10 and OUT15 OUT18 See characteristics in chapters 3 5 3 3 6 3 3 7 3 and 3 8 3 The restrictions concerning overload of power stages see 3 5 2 3 6 2 3 7 2 and 3 8 2 and per missible clamping energy see 3 5 8 3 6 8 3 7 8 and 3 8 8 are relevant further on 1 11 1 Notes for short circuit limitation The power stages are short circuit protected for the following conditions The max voltage at the output pins are limited to 36V and the TLE6244 is not operating in the booster mode The power stages will be switched on off with a max frequency of 1 kHz Only a 40 msec burst with the 1 kHz on off frequency is allowed with a minimum burst repetition time of 1 sec The maximum number of burst repetition cycles is 25 The number of driving cycles under these conditions is limited to 100 in lifetime The temperature of the slug of the MQFP64 package must not exceed 130 C These limitations are valid for UBatt gt 24 V For Ubatt 24 V the number of driving cycles under these conditions is extended to 1000 in life time Final Data Sheet 37 V4 2 2003 08 29 TLE 6244X technologies 1 12 Notes for the Diagnostics SCB entry in DIA_REGx see diagrams in chapter 1 6 4 In case of overvoltage at pin VDD VDD gt 5 5V the diagnostic information can be wrong In that case the diagnostic information has to be cleared with the DEL_DIA instruction The filtering time restarts when the output voltage passes the dia
39. UTS will not be reseted by RST After reset parallel control by IN8 is active for OUT8 If UVDD 4 5V errors are not stored because of the active RST of the external Regulator Nev ertheless OUTS is protected against overload 1 3 1 4 Input Current The control input IN8 has an internal pull down current source Thus the input currents IN8 are positive flow into the pin 1 3 1 5 On Resistance For OUT8 and 3 5V UVDD lt 4 5V R on increases see 3 8 5 1 3 1 6 Parallel Connection of Power Stages Parallel connection of power stages with OUTS8 and parallel control is prohibited inverting input IN8 Control via SPI is possible See 1 13 Final Data Sheet 5 V4 2 2003 08 29 technologies TLE 6244X 1 4 Pinout Function Pin Pin Number Input 1 IN1 7 Input 2 IN2 46 Input 3 IN3 10 Input 4 INA 43 Input 5 IN5 6 Input 6 or FDA ING 63 Input 7 or SSY IN7 61 Input 8 IN8 22 Input 9 IN9 20 Input 10 IN10 33 Input 11 IN11 5 Input 12 IN12 48 Input 13 IN13 13 Input 14 IN14 40 Input 15 IN15 1 Input 16 or FCL IN16 62 Output 1 OUT1 8 Output 2 OUT2 45 Output 3 OUT3 9 Output 4 OUT4 44 Output 5 1 OUT5 1 16 Output 5 2 OUT5 2 17 Output 6 1 OUT6 1 37 Output 6 2 OUT6 2 36 Output 7 OUT7 60 Output 8 OUT8 57 Output 9 1 OUTO9 1 18 Output 9 2 OUT9 2 19 Output 10 1 OUT10 1 35 Output 10 2 OUT10 2 34 Output 11 OUT11 4 Output 12 OUT12 49 Output 13 1 OUT13 1 14 Output 13 2 OUT13 2 15 Output 14 1 OUT14 1 39 Output 14 2 OUT14 2 38 Output 1
40. Y YO POYoUMS SI x qO 1ndino eBuei jo no s GGA 3gv 24722 dsai josal BAI Oe uo 1s Aue ul s1a siBaJ ne e sejejep VIG 130 uononiu sul dS 241 snq o sr JO 4S BIA 01 e U09 elas JO pijen Aj Huilpsoooe si wesbeig xNI uid ndul Aq pejoujuoo eDejs 1ewod e 10J Auej duiexy uonoe ou v a lt d 8 9 VIG Tad iv 29 V4 2 2003 08 39 Final Data Sheet e Infineon technologies TLE 6244X 1 13 Parallel Connection of Power Stages The power stages PS which are connected in parallel have to be switched on and off simultaneously The corresponding SPI Bits SCONx have to be in the same register see page 15 when the PS are serial controlled via SPI In case of overload the ground current and the power dissipation are increasing The application has to take into account that all maximum ratings are observed e g operating temperature Tj and total ground current lanp see page 36 37 Max number of parallel connections 3 The following statements apply to PS within the same TLE6244X The max short circuit shutdown threshold of the parallel connected PS is the summation of the corre sponding max values of the PS Isc outx lsc outy Max Nominal Current Max Clamping Energy On Resistance 2 symmetrical PS see note 1 0 9 x Imax OUTx Imax OUTy 0 75 x ECI OUTx Ecl OUTy 0 5 x Ron OUTx y 2 PS of the same type see note 2 3 PS of the same type see note 2
41. applied to the SPI input SCK during the access is not equal to 16 A write access is also internally suppressed i e internal registers will not be affected if at the rising inactive edge of SS a 17th bit is submitted SCK 1 After the bits CPAD1 0 and INSTR 4 0 have been sent from the microcontroller TLE6244X is able to check if the instruction code is valid If an invalid instruction is detected any modification on a register of TLE6244X is not allowed and the data byte FFh is transmitted after having sent the verification byte If a valid read instruction is detected the content of the corresponding register is transmitted to the controller after having sent the verification byte even if bit INSW afterwards is wrong If a valid write instruction is Final Data Sheet 10 V4 2 2003 08 29 TLE 6244X technologies detected the data byte 00h is transmitted to the controller after having sent the verification byte even if bit INSW afterwards is wrong but modifications on any register of TLE6244 are not allowed until bit INSW is valid too If an invalid instruction is detected bit TRANS F in the following verification byte is set to High This bit must not be cleared before it has been sent to the microcontroller O If TLE6244X and additional IC s are connected to one common slave select they are distinguished by the chip address CPAD1 CPADO If an IC with 32bit transmission format is selected TLE623
42. as above the upper limit this can be read out by the SPI instruction RD STATCON VDD monitoring has no influence on SCON REGx MUX REGx DIA REGx CONFIG and INP REGx If output stages are switched off by the internal over undervoltage detection or by externally applying a low signal at the ABE pin no failure storage DIAREG1 5 may occur Description in Detail Description of the Register STATCON REG Bit 7 1 Normal operation 0 Test of VDD threshold Access by controller read write State of reset 1 Bit 6 1 Testing the lower threshold if bit 7 0 0 Testing the upper threshold if bit 7 0 Access by controller read write State of reset 1 Bit5 1 ABE latched after overvoltage 0 ABE deactivated immediately after the disappearance of the overvoltage Access by controller read write State of reset 1 Bit 2 Reading out the level at pin ABE Access by controller read only Bit 1 1 no undervoltage at pin VDD 0 undervoltage at pin VDD Access by controller read only Final Data Sheet 34 V4 2 2003 08 29 technologies TLE 6244X Bit 0 1 no overvoltage at pin VDD 0 overvoltage at pin VDD resp state of overvoltage still stored Access by controller read only Testing the VDD Monitoring Upper threshold By writing 000xxxxxp in the register STATCON REG the overvoltage threshold is reduced by 0 8V In STATCON_REG Bit 0 has to be LOW then After writing 110xxxxxp in the register STATCON_REG Bit 0
43. case of SPI serial control BMUX deter mines parallel control or control by usec bus For the power stages 17 and 18 control is exclusively possible via SCON17 18 IN17 18 and MUX17 18 do not exist BMUX has no function for OUT17 18 ABE RST INx BMUX MUXx SCONx psec Output OUTx of Power Stage x REGx x 1 18 0 0 X X X X X OUTx off 0 1 X X X X X OUTx off 1 0 X X X X X OUTx off 1 1 X X 0 0 X SPI Control OUTx on 1 1 X X 0 1 X SPI Control OUTx off 1 1 0 1 1 X X Parallel Control OUTx on 1 1 1 1 1 X X Parallel Control OUTx off 1 1 X 0 1 X 0 usec bus Control OUTx on 1 1 X 0 1 X 1 pusec bus Control OUTx off Exception OUTS is on active if IN8 is set to logic 1 and off if IN8 is set to logic 0 in case of parallel access Note OUT8 cannot be controlled by the usec Bus Refer to section 1 7 Final Data Sheet 13 V4 2 2003 08 29 TLE 6244X technologies Description of the SPI Registers Register MUX_REG1 7 6 5 4 3 2 1 0 MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUXO State of Reset 80H Access by Controller Read Write Bit Name Description 0 MUXO Serial or parallel control of power stage 1 1 MUX1 Serial or parallel control of power stage 2 2 MUX2 Serial or parallel control of power stage 3 3 MUX3 Serial or parallel control of power stage 4 4 MUX4 Serial or
44. e OT will only be detected if switches are turned on The fault conditions SCB SCG OL and OT will not be stored until an integrated filtering time is expired please note for PWM application If at one output several errors occur in a sequence always the last detected error will be stored with filtering time All fault conditions are encoded in two bits per switch and are stored in the corresponding SPI registers Additionally there are two central diagnostic bits one specially for OT and one for fault occurrence at any output The registers can be read out via SPI After each read out cycle the registers have to be cleared by the DEL_DIA command 1 3 1 Power Stage OUT8 Condensed Description 1 3 1 1 Control of OUT8 and VDD Monitoring OUTS can be controlled by SPI or by the pin IN8 only control by us bus is not possible When controlled by IN8 this power stage is functional if the voltage at the pin VDD is above 3 5V In SPI mode the power stage is fully supervised by the VDD monitor If OUT8 is controlled by IN8 OUT8 will only be switched off by the overvoltage detection and not by undervoltage detection 1 3 1 2 Phase Relation IN8 OUT8 The phase relation IN8 gt OUTS is inverting OUTS is active if IN8 is set to logic 1 high level see 3 4 2 in case of parallel access On executing the read instruction on RD INP1 2 the inverted status of IN8 is read back 1 3 1 3 Reset Power Stage Diagnostics If OUT8 is controlled by IN8 O
45. etected as short C loz 0 3 A to ground C lo17 18 0 3 A Open load failure at neighboring C lo4 4 0 5 A stages are not detected as short C los 16 0 25 A to ground C loz 0 3 A Destruction limit C lo1 6 3 A C log 16 3 A C loz 0 8 A Final Data Sheet 63 V4 2 2003 08 29 TLE 6244X technologies 3 13 VDD Monitor Bidirectional open drain output ing ABE input with pull up current source An external current limitation must guarantee IABE lt 5 mA for any UABE 3 13 1 Output Uzee Low after tolitchyfor 2 V lt Uvpp lt 4 5V 4 7V or 5 3V 5 5V lt Uvpp 36V or Testmode see 3 13 5 or 3 13 6 or Pin GND ABE is open 3 13 1 1 Low Level Uypp gt 4 5V IABE lt 5mA A UABE 1 2 V Uypp 27V IABE lt 1mA A UABE 1 0 V in case of less current ohmic behavior can be assumed 1kQu 2400 3 13 1 2 Maximum No current recovery on VDD C UABE 36 V Voltage UBatt and the logical pins SS SCK SI SO INx RST in case of short to battery at ABE up to 36V 3 13 2 Input 3 13 2 1 Low Level B UABEL 0 3 V Uvpp 3 13 2 2 High Level B UABEH 07 V Uvpp 3 13 2 3 Hysteresis C AUsgg 02 1 0 V 3 13 2 4 Input Cur Pull up current source connected rent to VDD 0 25V UABE lt Uvpp 1 IN 0 25V lt UABE lt Uvpp 1 5M 0 3V lt Urge lt 0 25V 3 13 3 Overvoltage Voltage referred to GND ABE Threshold IABE 20 40 100 HA lABE 15 40 100
46. etected since the last reset of diagnostic information by del_dia instruction RST Low or undervoltage at VDD see 3 2 Bit 0 Overtemperature for at least one power stage has been detected since the last reset of the diagnostic information by del_dia instruction RST Low or undervoltage at VDD see 3 2 State of Reset 1 Access by Controller Read only 5 CONFIGO Bit 1 Latch function for overvoltage at VDD is switched on Bit 0 Latch function for overvoltage at VDD is switched off State of Reset 1 Access by Controller Read Write Final Data Sheet 28 V4 2 2003 08 29 technologies TLE 6244X CONFIG1 Bit 1 Lower threshold of VDD monitoring is lifted if bit CONFIG2 0 test of switch off path Bit 0 Upper threshold of VDD monitoring is reduced if bit CONFIG2 0 test of switch off path State of Reset 1 Access by Controller Read Write CONFIG2 Bit 1 Test of VDD threshold is switched off Bit 0 Test of VDD threshold is switched on State of Reset 1 Access by Controller Read Write Final Data Sheet 29 V4 2 2003 08 29 technologies TLE 6244X 1 7 usec Bus Interface The usec bus interface is one of three possibilities to control the power stages OUT1 0UT7 and OUT9 OUT16 are influenced by the reset input RST If RST is set to Low these power stages are switched off After reset they are controlled by the SPI default
47. ey UO KINO uonipuoo AOS technologies poj650 jou sem o431uoo eDejs 1oMod jnq peJeeddesip uonipuoo gos 194e vig 130 Aq pejejep Aue gos gOS jo ases ui jjo 3nys 10 powwesboid eBejs 19od 91767 LINO seBejs amod jo yoda YIS JO 2neuieu s 29 V4 2 2003 08 24 Final Data Sheet TLE 6244X UO UO UO uo o43uoo abejs Jamod Jasay UO 898 gos puewwoos yiq 130 technologies KIJO Vid ul Aqua yne4 UO KINO uonipuoo AOS poj650 jou sem o431uoo eDejs 1oMod jnq pa esaddesip uonipuoo gas Jaye josay Aq pajajap ue gos gos Jo ases ul yo 1nus JO powwesboid eBejs 19od 91767 LL LNO seBejs amod jo yoda YIS JO 2neuieu s 29 V4 2 2003 08 25 Final Data Sheet UO uO uO uO JO1 U09 oDejs Jamod I Jesoy puewwo vid 130 TLE 6244X Bel LO uouuuoo I 934 NOOLVLS Ul gos dds KIJO VIQ U nu yney 898 J Ovid Ovid 9VIOy uo uo uo uO KINO E 10 Vid LO ou 10 LO ou uonipuo9 LO gos ou 898 uonipuoo AOS poj650 sem jojuo3 abe s jamod pue pajeaddesip uonipuoo LO ds i gos Jaye Vid 13d
48. gnostic threshold for short to ground SCG Diagram of the typical diagnostic current A loUTPUT 580 pA 130 pA Short to CND ok A Diagnostic current see 3 11 3 B Bias Voltage Open Load see3 11 2 C Short to GND Threshold see 3 11 1 2 D Open load Threshold see 3 11 1 1 Final Data Sheet 38 V4 2 2003 08 29 er er P HOIH MO1 E XNI Bu l66ol HO KINO Buiounoq q gt 1O OL LLI OTNI io uz ymes l 10 ou amp 10 ou 10 Y 9 gos OL SIH lt MOT Aqua yney Wo yee XN BuB6o y a ai Juano xew uo xino HO xino MO XNI x 89501 o P bc MOT XNI Anua yney a T ee O T INE wi ON 10 oN 90S Hi 92S lO uoneymun yuana ou 9 S LLAO 898 10 S pamsiyuoo sr uoneyrung juoxmo JI X SLAQ SE o ol S10 9 1100 39 ES o 10 0L 89S OL 3 Anu nea Aqu yney 9S9 00 70 LO Aug yney Anua qne o HOS ON gos hs ko c Burounoqeq 9098 SOS ON IOJJUO9 juaJIno Buiounoq q O O Bursunogaq Buiounoq q E x uo XLMO ae HOIH lt MO1 oe fo MOT XNI XNI Buij660 Ho KINO ao uonoy amp gt H9IH XNI ON a HOIH lt MOT XNI Buif6o V bb o yney yney ON o uonov S s5 O oS oN Y MOA lt HOIH XNI BuibBo LO o 810 1deoxe y ejeis ui s eBejs Jamod Se y J9S9J JOL
49. in STATCON_REG must be HIGH again Lower threshold By writing 010xxxxxp in the register STATCON_REG the overvoltage threshold is increased by 0 8V In STATCON REG Bit 1 has to be LOW then After writing 110xxxxxp in the register STATCON REG Bit 1 in STATCON REG must be HIGH again Example of configuration Requirement After overvoltage ABE is to be LOW After overvoltage a self test is carried out by the ECU afterwards ABE is deactivated Register STATCON REG is set to 111 oxxxp during driving cycle When ABE becomes active overvoltage can be detected by reading out STATCON REG After the ECU s self test a reset condition is achieved by writing 110xxxxxp into the register STATCON REG This reset is only possible after disappearance of the overvoltage condition because the set input is dominant The reset signal is withdrawn by writing 111xxxxxp Final Data Sheet 35 V4 2 2003 08 29 TLE 6244X technologies yjnejo X N proysalyL aBeyonlepun sel A plous iu1 SBeyonisao 3S L Q seDeis Jamod 934 NOOLVIS JO uos 1 0 L c v S 9 gt 0 NN yosoy aBeyonapun IND V 3 S Jjav GND GA 18 abeyOAIaAQ T NUN jueuiuop Jas E Jeyy uou DuuojUuOJ A QdG A wejbeiq 19019 r GGA ye abeyonapun 1 29 V4 2 2003 08 36 Fi
50. lay of the power stages after detection of SCB For the duration of tyop current is limited to maximum current loUT15 loUT16 louT15 louT16 UOUT 15 16 tor 3 3 36 60 3 0 215 us Final Data Sheet 52 V4 2 2003 08 29 technologies 3 7 5 On Resis tance 3 7 6 On off Delay Times 3 7 7 Leakage Cur rent 3 7 8 Clamping 3 7 8 1 Clamping Voltage 3 7 8 2 Maximum Clamping En ergy Tc lt 110 C 3 7 8 3 Maximum Clamping En ergy Tc lt 60 C 3 7 8 4 Maximum Clamping En ergy with two Outputs con nected in par allel TLE 6244X Tj 25 C T 150 C Tj 40 C For Uypatt lt 10V Ron is increased up to 20 On Off Measurementwithohmicload Itdon taoril switch on slew rate switch off slew rate Uvpp OV Uout15 16 14V leakage current of the DMOS diagnostic current 0 Uvpp OV Uout15 16 24V leakage current of the DMOS diagnostic current 0 louT15 16 0 2A Linear decreasing current fmax 30Hz see diagrams E f l on page 67 10UT15 16 lt 3 0A lOUT15 16 lt 2 2A 10UT15 16 lt 1 5A loUT15 16 lt 1 0A Linear decreasing current fmax 30Hz 10UT15 16 3 0A louT45 16 1 0A Each output 75 of the values of 3 7 8 2 resp 3 7 8 3 gt OO 00UUU O O O O loUT15 16 loUT15 16 Uouris 16 m m rm rm 150 270 120 40 220 2
51. n 2 0 V UrDAn Ussvn 3 10 1 3 Hysteresis C AUrcL 0 1 0 6 V AUFDA AUssy 3 10 1 4 Input Ca C Ceci 10 pF pacity CrpA Cssv 3 10 1 5 Input Cur Pull up current source connected A lECL 5 10 20 HA rent to VDD lEDA Issy 3 10 2 Timing Cycle Time C tcvc 62 nsec Data setup time C tsetup 10 nsec Data hold time C thold 10 nsec Switching time on FCL C tewitch 30 nsec fec lt 10MHz Final Data Sheet 61 V4 2 2003 08 29 TLE 6244X technologies Switching time on FCL C tewitch 8 nsec frcL gt 10MHz Select hold time C tshold 25 10 nsec FCL Low time C tFCLL 25 nsec FCL High time C tFCLH 25 SSY Low time C tSSYL 25 nsec SSY High time C tSSYH 25 Time between rising edge of SSY C tSF 8 nsec and next falling edge of FCL 3 11 Diagnostics 3 11 1 Diagnostic Thresholds Power Stages 3 11 1 1 Open Load Output turned off B Uour Uvpp Uvpp Uvypp V OL 18 I 0 5V 0 5V 3 11 1 2 Short to Output turned off B Uours 0 54 0 54 0 54 V Ground gt SCG Uvpp Uvpp Uvpp 0 5V 0 5V 3 11 1 3 Short to Bat See 3 5 3 3 6 3 3 7 3 3 8 3 tery SCB 3 11 1 4 Overtem Output turned on B Ty 150 C perature Individually for each stage 3 11 2 Bias Voltage Output turned off lour4 48 0 A Uour 0 6 0 7 0 76 V Open Load 1 Uvpp Uvpp Uvpp Power Stages 3 11 3 Diagnostic 4 5V lt Uypp lt 5 5V output turned Currents off Power Stages UouT1 18 14V diagnostic cur A
52. n case of SCB can be switched on again by an off on cycle at the cor responding input pin resp by the change of the state of the corre sponding bit for SPI or usec bus by a DEL_DIA instruction or can be released again by reset If the fault register is cleared before this release by a DEL_DIA instruc tion a new fault entry of SCB is immediately carried out even if SCB condition is no longer present For OUT9 OUT10 Above this limit short circuit to UBatt is detected The output cur rent is limited to approximately this value if the static current limitation is configured An error is stored after tpiag see 3 11 4 If the oper ation leads to an overtemperature condition a second protection level about 170 C will change the output into a low duty cycle PWM selective thermal shutdown with restart to prevent critical chip tem peratures Between 40 C and 150 C an approximately linear characteristic line can be assumed See Note 1 11 1 Shutoff delay of the power stages after detection of KSUB For the duration of tyog current is limited to maximum current Ty 25 C Tj 150 C T 40 C For Uypatt 10V Ron is increased up to 20 gt gt gt UOUT 9 14 tvoff Rong 14 Rono 14 Rono 14 36 60 200 380 150 300 550 220 215 380 680 280 us ma ma ma Final Data Sheet 50 V4 2 2003 08 29 technologies 3 6 6 On off Delay Times
53. nal Data Sheet TLE 6244X technologies 1 11 Notes for the Application in Commercial Vehicles For electric systems with 24V battery voltage that can even increase to 2 37V in case of load dump some peculiarities have to be observed The static voltage at pin UBatt without destruction is limited to 37V therefore this pin must either be connected to the 5V supply voltage VDD or else the voltage at pin UBatt has to be limited by adequate external circuitry By connecting pin UBatt to VDD the values of Ruas on of the power switches will increase up to 20 The power stages 7 18 are equipped with a 40V active clamping Therefore this power stages must only drive loads with an accordingly high resistance that can be switched on in case of over voltage e g a maximum load dump voltage of 60V and a load resistor of 1kQ result in a power dissipation of 0 8W for each power stage For all of the 12 power stages together there is a power dissipation of 9 6W for the typical duration of a load dump of 500ms The restrictions listed above are no longer relevant in case of a overvoltage protected battery voltage within the 24V electric system that limits the voltage to e g a maximum of 37V The thresholds of the currents on which the power stages are switched off in case of overload are increased by approximately 25 if there is a voltage at pin UBatt higher than19V reason jump start requirements in 12V electric systems Exception
54. ng generates a low signal at the bidirectional pin ABE if the 5V supply volt age at pin VDD is out of the permissible range of 4 5V 5 5V On ABE low the power stages of TLE6244X are switched off Exception OUTS is not switched off in case of parallel control via IN8 by the VDD monitoring undervoltage threshold but by a threshold of 3 5V at VDD On shorting pin ABE to Vpp or UBATT s 36V the power stages will be switched off in case of undervoltage or overvoltage at pin VDD in spite of ABE high The behavior of the ABE level on the return of VDD out of the undervoltage range into the cor rect range is not configurable At the transition from undervoltage to normal voltage the signal at pin ABE goes high after a filtering time is expired The behavior of the ABE level on the return of VDD out of the overvoltage range into the correct range is configurable in EN STATCON REG Bit5 At the transition from overvoltage to normal voltage the signal at pin ABE goes high either after a filtering time OV not latched or after a SPI writing instruction OV latched state after reset EE On undervoltage condition the signal at pin ABE goes high after a filtering time is expired On overvoltage condition pin ABE goes high either after a filtering time or after a SPI writing instruc tion Before this SPI instruction is sent to TLE6244X appropriate tests can be carried out by the controller If the voltage at pin VDD is below the lower limit or is resp w
55. ourse of release qualification characterization parameter test C Guaranteed by design covered by lab tests not considered within the standard production flow 2 3 Thermal Limits Operating temperature TLE6244 continuous 40 C lt Tj lt 150 C additionally only for the power switches 150 C lt Ty x 200 C for 100h accumulated Storage temperature 55 C lt Tc lt 125 C Thermal resistance Rinuc lt 2 5 K W 2 4 Electrical Limits Limits must absolutely not be exceeded By exceeding only one limit the integrated circuit might be destroyed Power Supplies Uypp and Uypatt Static without destruction 0 3V Uypp lt 36V 0 3V lt Uypat lt 37V Dynamic 10psec without destruction 0 5V lt Uypp lt 36V 0 5V lt U patt 40V Dynamic 500 ms 10 x in lifetime without destruction 0 5V x Uypatt x 40V Uypp gt 5 5V is allowed only in case of error conditions Not suitable for continuous operation SPI Output Output voltage 0 3V Ugo lt 36V Final Data Sheet 42 V4 2 2003 08 29 TLE 6244X technologies Output current Iso lt 5mA Outputs Low Side Switches Static voltage without destruction OUT1 6 lt 64V OUT7 18 lt 40V Dynamic voltage without destruction after ISO DIS7637 1 pulses 1 to 4 OUT1 to 6 OUTY to16 via external load e g 2W lamp lt 2ms OUT7 OUT8 OUT17 and OUT18 via external load lt 2ms Ground Current Total current GND1 2 pins 26 27 le
56. p lt 5 5V Uvypp RST min RST min 4 7 15 5 3 ms us 3 2 Validity of Parameters Parameters are valid for 4 5V Uypp lt 5 5V 4 5V Uypatt lt 37V TLE6244 40 C x T x 150 C and 2 power stages in current limitation unless otherwise noted If VDD monitoring is active the power stages are switched off except OUTS see page 28 Positive current flows into the pin negative current flows out of the pin Unless otherwise noted all volt ages are referred to GND GND1 8 connected with each other If the Uypp falls below this trashed the power stages except OUT8 are switched off If Uypp rises above this threshold the power stages work regularly after a delay time of 250 usec Threshold for shut off of OUT8 If Uypp rises above this threshold the power stages work regularly after a delay time of 250 usec Supply voltage Uvpp Uvpp Uvpp 3 5 4 5 4 2 4 5 3 5 5 5 Final Data Sheet 44 V4 2 2003 08 29 TLE 6244X technologies 3 3 Power Con Uvpp lt 5 5V A lvpp 20 mA sumption 5 5 V UVDD 36 V IC is not C lvDD 50 mA destroyed UuBatt 14V A luBatt 3 mA UuBatt 28V A luBatt 4 mA UuBatt UvDD A lUBatt 1 mA Power consumption in standby A lUBatt 200 HA mode in case of missing Uvpp UuBatt lt 14V 3 4 Inputs of the Outputs are switched off if inputs Power Stages are open parallel control
57. tages 1 7 and 9 16 are controlled by the usec bus interface on condition that registers MUX_REG1 2 are configured for serial access The received usec bus bit stream DO D15 is latched into a 16 bit register by the rising edge at SSY Power stages 1 7 and 9 16 are switched according to bits DO D7 and D9 D15 psec bus control of psec bus control of power stage power stage DO OUT14 D8 psec bus Test Bit D1 OUT1 D9 OUT11 D2 OUT2 D10 OUT10 D3 OUT3 D11 OUT9 D4 OUT4 D12 OUT12 D5 OUT5 D13 OUT13 D6 OUT6 D14 OUT16 D7 OUT7 D15 OUT15 Bit Dx 0 Power stage OUTx is switched on Bit Dx 1 Power stage OUTx is switched off State of reset FFFFy Because the power stage 8 is not controlled by the uisec bus interface the corresponding bit D8 can be used as test bit that can be read back by the SPl interface see register RD INP1 If the usec bus interface is used to control the power stages the input pins IN1 IN5 and IN8 IN15 can be used as input port expander by reading the status of the input pins by the SPI commands RD INP1 2 Final Data Sheet 31 V4 2 2003 08 29 TLE 6244X technologies 1 8 Unused Power Stages To avoid an open load fault indication an unused power switch has to be connected to an exter nal pull up resistor connected to Uyg or has to be switched on by the input pin or via SPI or the usec bus interface Uupatt Voltage oD regulator
58. tching of the Clamp ing Voltage 3 5 8 3 Maximum Clamping En ergy Tc lt 110 C 3 5 8 4 Maximum Clamping En ergy Tc lt 60 C 3 5 8 5 Maximum Clamping En ergy with two Outputs con nected in par allel 3 5 8 6 Maximum Clamping En ergy at Load Dump 3 5 8 7 Jump Start 3 5 8 8Singlepulse Tc lt 60 C TLE 6244X Uvpp OV Uout1 6 14V leak age current of the DMOS diag nostic current 0 Uvpp OV UouT1 6 24V leak age current of the DMOS diag nostic current 0 louT1 6 0 2A Between different outputs with identical inductive loads Linear decreasing current fmax 50Hz see diagrams E f I on page 66 louT1 6 22A louT1 6 1 0A louT1 6 0 5A Linear decreasing current fmax 50Hz lout1 6 lt 2 2A louT1 6 1 0A louT1 6 0 5A Each output 75 of the values of 3 5 8 3 resp 3 5 8 4 For a maximum of 10 times during ECU life load dump with 400ms and R 20 over the load e g 2W lamp Each output 15096 of the values of 3 5 8 4 For a maximum of 10 jump starts of 2 minutes each during ECU life louT4 6 lt 0 6A max 10 000 pulse O O O 0 louT1 6 lOUT1 6 UouT1 6 AU 64 50 HA 200 HA 76 V 3 V 8 5 mJ 19 mJ 30 mJ 10 8 mJ 22 mJ 36 mJ 50 mJ 50 mJ Final Data Sheet 48 V4 2 2003 08 29 technologies TLE 6244X 3 6 Power outputs 2 2A 45V OUT9 OUT14
59. te of serial control of power stage 5 5 SCON5 State of serial control of power stage 6 6 SCON6 State of serial control of power stage 7 7 SCON7 State of serial control of power stage 8 Register SCON_REG2 7 6 5 4 3 2 0 SCON15 SCON14 SCON13 SCON12 SCON11 SCON10 SCON9 SCON8 State of Reset FFH Access by Controller Read Write Bit Name Description 0 SCON8 State of serial control of power stage 9 1 SCON9 State of serial control of power stage 10 2 SCON10 State of serial control of power stage 11 3 SCON11 State of serial control of power stage 12 4 SCON12 State of serial control of power stage 13 5 SCON13 State of serial control of power stage 14 6 SCON14 State of serial control of power stage 15 7 SCON15 State of serial control of power stage 16 Final Data Sheet V4 2 2003 08 29 TLE 6244X technologies Register SCON_REG3 7 6 5 4 3 2 1 0 1 1 1 1 1 1 SCON17 SCON16 State of Reset FFH Access by Controller Read Write Bit Name Description 0 SCON16 State of serial control of power stage 17 1 SCON17 State of serial control of power stage 18 7 2 No function HIGH on reading Final Data Sheet 16 V4 2 2003 08 29 technologies TLE 6244X 1 6 2 Diagnostics Encoding of Failures Description of the SPI Registers SPI Instructions RD DIA1 5 Regis
60. ter DIA_REG1 7 6 5 4 3 2 1 0 DIA7 DIAG DIA5 DIA4 DIA3 DIA2 DIA1 DIAO State of Reset FFH Access by Controller Read only Bit Name Description 1 0 DIA 1 0 Diagnostic Bits of power stage 1 3 2 DIA 3 2 Diagnostic Bits of power stage 2 5 4 DIA 5 4 Diagnostic Bits of power stage 3 7 6 DIA 7 6 Diagnostic Bits of power stage 4 Register DIA REG2 7 6 5 4 3 2 1 0 DIA15 DIA14 DIA13 DIA12 DIA11 DIA10 DIA9 DIA8 State of Reset FFH Access by Controller Read only Bit Name Description 1 0 DIA 9 8 Diagnostic Bits of power stage 5 3 2 DIA 11 10 Diagnostic Bits of power stage 6 5 4 DIA 13 12 Diagnostic Bits of power stage 7 7 6 DIA 15 14 Diagnostic Bits of power stage 8 Final Data Sheet 17 V4 2 2003 08 29 TLE 6244X technologies Register DIA_REG3 7 6 5 4 3 2 1 0 DIA23 DIA22 DIA21 DIA20 DIA19 DIA18 DIA17 DIA16 State of Reset FFH Access by Controller Read only Bit Name Description 1 0 DIA 17 16 Diagnostic Bits of power stage 9 3 2 DIA 19 18 Diagnostic Bits of power stage 10 5 4 DIA 21 20 Diagnostic Bits of power stage 11 7 6 DIA 23 22 Diagnostic Bits of power stage 12 Register DIA_REG4 7 6 5 4 3 2 1 0 DIA31 DIA30 DIA29 DIA28 DIA27 DIA26 DIA25 DIA24 State of Reset FFH Access by Controller Read only Bit Name Description 1 0
61. to Software release OHex 3 0 MSR 3 0 Revision corresponding to Maskset OHex Reset of the Diagnostic Information SPI Instruction DEL DIA Resets the 5 diagnostic registers DIA REG41 5 to FFH and the common overtemperature flag in regis ter STATCON REG Bit4 to High These bits are only cleared by the DEL DIA instruction when there is no failure entry at the input of the registers Access is performed like a writing access with any data byte In the case a power stage is shut off because of SCB the output is activated again by the DEL DIA instruction and the filtering time is enabled Therefore in case of SCB the output is activated and shut off after the shutoff delay For a power stage in the current limitation mode the current limitation mode is left if a DEL DIA instruction has been received If there is still the condition for SCB the current limitation mode is entered again On the following pages the conditions for set and reset of the SCB report in DIA REGx is shown in several schematics The signal power stage control is generated as follows INi N PONT ABE not active power stage control ON ew OR AND usec ON Final Data Sheet 21 V4 2 2003 08 29 TLE 6244X
62. uO uO uO uO uO 043u09 oDejs Jamod esos puewwo vid 130 gos lt gos gos KIJA VIG UI nu yney uo uo y UO j M UO uO XLno 9WId 9WId 9WId lt p lt p lt Pp gos ou gos uonipuoo GOS Infineon technologies e poj6503 sem o41uoo eDBejs Jamod pue peJeeddesip uonipuoo gos 194e VIG 130 Aq pejejep Aue gos JJS jo ases ui yo nus 10 powwesboid eBejs 19od 91767 LL LNO seBejs amod jo uodai YIS JO 2neuieu s 29 V4 2 2003 08 22 Final Data Sheet e TLE 6244X Infineon technologies UO UO UO uo UO JO1 U09 abejs Jamod jesoy gOS Abos gos ou gOS puewwoo yiq 130 KIJA Vid ul Anua yney UO KINO uonipuo AOS poj6503 sem j01 U09 aHe s Jamod pue pojseoddesip uonipuoo gas Jaye jasay Aq pajajap ue gos gos Jo ases u Jjo nNYS 10 powwesboid eBejs 1amod 91 6 Z2 LLNO seBejs amod jo yoda YIS JO 2neuieu s 29 V4 2 2003 08 23 Final Data Sheet TLE 6244X uO UO UO uo o43uoo abejs Jamod Jasay gOS Akos UO UO gos ou gOS puewwoos yiq 130 KIJO Vid ul Anua yn
63. ue If the short circuit condition is still present after tyof the outputs OUT7 8 are switched off An error is stored after tDiag see 3 11 4 The same is true for OUT17 OUT 18 if the static current limita tion is not enabled Final Data Sheet 54 V4 2 2003 08 29 TLE 6244X technologies Between 40 C and 150 C an approximately linear characteristic line can be assumed Between 17V x Uypat lt 21V the short circuit shutdown threshold is switched for OUT7 8 A power stage that is switched off in case of SCB can be switched on again by an off on cycle at the cor responding input pin resp by the change of the state of the corre sponding bit for SPI or usec bus by a DEL DIA instruction or can be released again by reset If the fault register is cleared before this release by a DEL DIA instruc tion a new fault entry of SCB is immediately carried out even if SCB condition is no longer present For OUT17 OUT18 Above this limit short circuit to UBatt is detected The output cur rent is limited to approximately this value if the static current limitation is configured An error is stored after tpiag see 3 11 4 If the oper ation leads to an overtemperature condition a second protection level about 170 C will change the output into a low duty cycle PWM selective thermal shutdown with restart to prevent critical chip tem peratures Between 40 C and 150 C an
64. x 50 na Tomax 110 C 20 10 0 HH HH gt 0 0 5 1 0 1 5 2 0 Imax 2A 3 14 2 E f louro a14 2 2A Power Stages with 45V Clamping E mJ n 2 2A Power Stage Clamping Voltage 40 50V 30 L fmax 30 Hz Tomax 110 C 20 10 0 A gt 0 0 5 1 0 1 5 2 0 Imax A Final Data Sheet 66 V4 2 2003 08 29 e Infineon technologies TLE 6244X 3 14 3 E f lourz 8 47 18 1100mA Power Stages with 45V Clamping E mJ A 1 1A Power Stage Clamping Voltage 40 50V PUN fmax 10 Hz Tomax 110 C 10 5 m 0 gt 0 0 25 0 5 0 75 1 0 Imax A 3 14 4 E f lout15 out16 3 0A Power Stages with 45V Clamping E mJ J 3 0A Power Stage Clamping Voltage 40 50V 30 L fmax 30 Hz Tomax 110 C 20 10 0 e y l gt 0 0 5 1 0 15 2 0 25 Imax A Final Data Sheet 67 V4 2 2003 08 29 TLE 6244X technologies 4 ESD All pins of the IC have to be protected against electrostatic discharge ESD by appropriate pro tection components The integrated circuit has to meet the requirements of the Human Body Model with Uc 2kV C 100pF and R2 1 5kQ without any defect or destruction of the IC Appropriate measures to reach the required ESD capability have to be coordinated The ESD capability of the IC has to be verified by the following test circuit S2 1 2 O

Download Pdf Manuals

Related Search

lnfineon TLE 6244X Manual

lnfineon TLE 6244X Manual

Contents

Download Pdf Manuals

Related Search

Related Contents