MAXIM MAX498/MAX499 Manual
Contents
1. SM ALL SIGNAL GAIN GAIN FLATNESS LARGE SIGNAL GAIN vs FREQUENCY vs FREQUENCY vs FREQUENCY 8 3 6 2 s 8 3 7 Vin 20mVp p s si VIN 20mVp p 2 B 6 6 0 6 5 5 9 5 2 4 2 58 2 z z z 4 3 8 57 2 5 6 1 55 2 0 54 1 1 5 3 0 1M 10M 100M 1G 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz LARGE SIGNAL GAIN LARGE SIGNAL GAIN OUTPUT IMPEDANCE vs FREQUENCY vs FREQUENCY vs FREQUENCY 3 0 14 s 1000 2 RL 50Q 8 Vout 2Vp p A 7 Vour 2Vp p A i 0 10 i QuTO OUTI 100 0 06 a a 5 T OUTO OUT3 Bodo o 2 Z 4 Z 0 02 a 3 3 d 0 02 i f 0 1 0 06 OUTO OUT2 0 0 10 0 01 1M 10M 100M 500M 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY Hz FREQUENCY Hz FREQUENCY Hz OFF ISOLATION CROSSTALK POWER SUPPLY REJECTION vs FREQUENCY vs FREQUENCY vs FREQUENCY 20 A 20 g 15 2 H Var M H g 30 OJT lt Vp p on a 40 20 35 ko T g 50 S 40 ALL HOSTILE a 6 E 2 9 60 60 55 ADJACENT m 70 80 65 80 100 75 90 120 85 100 140 95 1M 10M 100M 1G 1M 10M 100M 30k 0 1M 1M 10M 100M FREQUENCY Hz JENCY Hz FREQUENCY Hz A MAXIM SUPPLY CURRENT mA amp 35 30 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Typical Operating Characteristics continued2. Voc 5V VEE 5V RL 100Q Ta 25 C unless otherwise noted MAX498 SUPPLY CURRENT vs TEMPERATURE MAX498 499 10 CURRENT mA 55 35 15 5 25 45 65 8 EMPERATURE C INPUT OFFSET VOLTAGE vs TEMPERATURE 12 10 8 6 4 2 D 4 6 8 10 12 55 35 15 5 25 45 65 8 TEMPERATURE C LARGE SIGNAL PULSE RESPONSE bui MAX4BI499 T0016 z fe SE TIME 10ns div MAXIM DISABLED SUPPLY CURRENT vs TEMPERATURE MAX4SB 499 11 2 0200 N o 75 0150 SUPPLY CURRENT mA DN o GAIN vs TEMPERATURE MAX498499 12 55 35 15 5 2 45 65 85 TEMPERATURE C INPUT BIAS CURRENT vs TEMPERATURE MAX498 499 13 MAXA98 499 14 INPUT BIAS CURRENT uA 0 O A ND OND FD o ae LARGE SIGNAL PULSE RESPONSE CL 47pF TIME 10ns div 55 MAXA98 499 TOC17 ERATURE C LARGE SIGNAL PULSE RESPONSE CL 100pF i i TIME 10ns div MAX498 499 TOC 18 66VXVW S6VXVIN Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Typical Operating Characteristics continued MAX498 MAX499 VOLTAGE mV g SMALL SIGNAL PULSE RESPONSE 100 E IN 0 100 g g 200 aT
3. Ordering Information The four channel MAX498 dissipates 390mW typical from 5VDC power supplies with all output buffers PARI TEMP RANGE PIN PACKAGE enabled Power consumption is reduced to 130mW with MAX498CWI 0 C to 70 C 28 SO all buffers disabled The corresponding dissipation for MAX499CWG 0 C to 70 C 24 SO the three channel MAX499 is 300mW enabled and 100mW disabled 135MHz Full Power 3dB Bandwidth 70MHz 0 1dB Gain Flatness 1250V us Slew Rate 12ns to 0 1 Settling Time 0 03 0 06 Differential Phase Gain Error 2pF Input Capacitance 3ns Channel Switching Time 120mVp p Channel Switching Transient gt o o lt o o Applications Pin Configurations Video Switching and Routing Broadcast Quality Composite Video Multiplexing TOP VIEW Workstations Video Editing Broadcast and High Definition TV Systems Multimedia Products MAXIN MAX499 Medical Imaging SO MAX498 appears at end of data sheet MAXI Maxim Integrated Products 1 For free samples amp the latest literature http www maxim ic com or phone 1 800 998 8800 66VXVW S6VXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC tO VEE 00 Voltage on IN__ to GND VEE 0 3V to Vcc 0 3V Voltage on Digital Inputs LE EN AO CS Voltage on OUT_ disabled Output Short Circuit Duration to 4V
4. and controls the status of switches S1 S2 and S3 of each amplifier in parallel as described in the Digital Interface section S3 is open in the enabled state and if Ch_A is select ed S1 is connected to IN_A and S2 is connected to GND If Ch_B is selected S1 is connected to GND and S2 is connected to IN_B Connecting the deselected GM_ block to GND ensures minimum feedthrough S3 is closed in the disabled state and both S1 and S2 are connected to GND Disconnecting both inputs and connecting the amplifier s inputs to GND significantly improves off isolation Applications Information Power Dissipation The MAX498 MAX499 s maximum output current is limit ed by the package s maximum allowable power dissi pation The maximum junction temperature should not exceed 150 C Power dissipation increases with load and this increase can be approximated by one of the following equations For Vout gt OV Vcc VouT ILoaD OR For Vout lt OV Vee VouT ILoap These devices can drive 100Q loads connected to each of the outputs over the entire rated output swing and temperature range While the output is short circuit protected to 120mA this does not necessarily guaran tee that under all conditions the maximum junction temperature will not be exceeded Do not exceed the derating values given in the Absolute Maximum Ratings section 10 MAX LMI MAX498 MAX499 CHANNEL 0 CHANNEL 1 CHANNEL
5. Disables amplifiers Outputs high Z AO latch channel A 0 0 1 Enables amplifier outputs Selects channel B 13 66PXVWWB86PXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers OUTPUTS LE V Figure 7 Logic Timing Diagram EN AO LE se MAXIM MAXIM MAX498 MAX498 AK9 LE MAX499 SHUTDOWN LE cs MAXIM MAXIM MAX498 MAX498 m MAX499 MAX499 NOTE ISOLATION RESISTORS IF REQUIRED NOT SHOWN a Figure 8 a Simultaneous Shutdown of all MAX498 MAX499s b Enable EN Register Latched by CS 1 MAK Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers MAXIM MAXIM MAX498 MAX499 MAX498 MAX499 Vin 4Vp p f 10MHz N Rg 750 Vin 4Vp p f 10MHz Rs 75Q a ADJACENT CHANNEL b ALL HOSTILE Figure 9 Test Circuits for Measuring Crosstalk a Adjacent Channel b All Hostile 75Q CABLE MAKI MI MAX4 75Q CABLE 2 SOURCE g TEKTRONIX 7 MEASUREMENT 1910 DIGITAL GENERATOR TEKTRONIX VM700 VIDEO MEASUREMENT SET Figure 10 Differential Phase and Gain Error Test Circuit MANKI TII 15 66PXVWW86PXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Pin Configurations continued Chip Information SUBSTRATE CONNECTED TO VEE TRANSISTOR COU
6. Distortion THD f 10MHz 50 dB Spurious Free Dynamic Range SFDR _ fc 3MHz 66 dBc Adjacent Channel Crosstalk f 10MHz Note 2 90 dB All Hostile Crosstalk f 10MHz Note 3 62 dB Off Isolation EN 1 f 10MHz Note 4 81 dB Differential Gain Diff Gain f 3 58MHz Note 5 RL 150Q 0 03 Differential Phase Diff Phase f 3 58MHz Note 5 RL 150Q 0 06 degrees TIMING CHARACTERISTICS Vcc 5V Vee 5V VIN__ OV RL 1509 LE EN CS OV Ta 0 C to 70 C Typical values are at Ta 25 C unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AO EN to CS Setup Time tsu LE high Note 6 8 ns AO EN to CS Hold Time tH LE high Note 6 4 ns CS Pulse Width tcs Note 6 15 ns Bey ey to Note 7 20 ns Channel Switching Time tsw Note 8 3 ns ae Positive 70 Channel Switching Transient VINA VINB OV mv Negative 50 Enable Disable Switching Vina Ving OV Positive 10 mV Transient Negative 150 Amplifier Disable Time tOFF Note 9 16 ns Amplifier Enable Time ton Note 10 24 ns Note 2 Figure 9 Note 3 Note 4 disabled Figure 9 Note 5 Note 6 Guaranteed by design Note 7 Note 8 Note 9 Delay from EN to 90 of Vout Note 10 Delay from EN to 10 of Vout MAXIM VINA 1V VINB 1V delay from CS to 10 of VouT VINA 1V VINB 1V delay from CS to 10 of VOUT Test channel input groun
7. larger capacitive loads or to reduce peaking add an isolation resistor Riso between the output and the capacitive load Figures 4a 4b and 5 11 66PXVWW86PXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers g 5 ys 47 100 150 200 270 390 510 CAPACITANCE pF Figure 5 Isolation Resistor vs Capacitive Load Switching Audio Signals Audio Distortion Measurement When switching audio signals distortion is the prime consideration in performance Figure 6 shows total harmonic distortion vs frequency in the audio range for the MAX498 MAX499 Large Switch Arrays Large crosspoint switch arrays are possible with the MAX498 MAX499 using the enable function EN When the amplifiers are disabled output impedance is typi cally 1 2kQ due to the feedback and gain resistors This limits the number of outputs that can be paralleled without a buffer Since each output can drive 100Q eight outputs can typically be connected together If additional outputs must be connected in parallel a MAX4178 single MAX496 quad or equivalent unity gain buffer can be used Whether enabled or disabled each input represents more than 200kQ of resistance Capacitance is the prime consideration limiting the number of inputs that can be connected to a single output Since each output can drive 100pF of capacitance without an isolation resistor 50 inputs CIN
8. o 200 TIME 10ns div CHANNEL SWITCHING 3 3 2 i or 3 5 ENABLE 0 TIME 10ns div IN A 1V IN B 1V ENABLE DISABLE dak a laka ENABLE 0 4 100m OUT 0 100m VOLTAGE V Voc 5V VEE 5V RL 100Q TA 25 C unless otherwise noted SMALL SIGNAL PULSE RESPONSE C4 47pF TIME 10ns div ENABLE DISABLE SWITCHING TIME 10ns div SWITCHING TRANSIENT MAX498 499TOO 25 MAX498 499 TOO 2 MAX498 489 TOC 23 300 280 260 SM ALL SIGNAL PULSE RESPONSE CL 100pF Zhi TIME 10ns div CHANNEL SWITCHING TRANSIENT TIME 50ns div BANDWIDTH vs INPUT VOLTAGE MAXA98 499 26 240 BANDWIDTH MHz TIME 50ns div 220 200 180 160 140 120 0 01 NI 0 1 0 PUT VOLTAGE Vp p MAXIM MAX498 499 TOC 21 Eo Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Pin Description PIN NAME FUNCTION MAX498 MAX499 er 2 4 9 GND Analog Ground All ground pins are internally connected Connect all ground pins externally to 19 i 11 24 ground to minimize impedance 2 1 IN1A Signal Input 1 Channel A 4 3 IN2A Signal Input 2 Channel A 6 5 IN3A Signal Input 3 Channel A Positive Power Supply Voltage Connect Vcc
9. typical application the MAX498 MAX499 drive a back terminated cable Figure 1 The back termination resistor at the output matches the impedance of the cable s driven end to the cable s impedance eliminating signal reflections This resistor along with the load termination resistor forms a voltage divider with the load impedance which attenuates the signal at the cable s output by one half The MAX498 MAX499 operate with an internal 2V V closed loop gain to provide unity gain at the cable s output MAXIM ARDY ON AD Figure 3b Small Signal Gain vs Frequency and Load Capacitor RL 1002 Riso 6 8Q TIME 10ns div Figure 4b Small Signal Pulse Response with CL 100pF and Riso 5 19 Capacitive Load Driving In most amplifier circuits driving large capacitive loads increases the likelihood of oscillation This is especially true for circuits with high loop gains such as voltage followers The amplifier s output resistance and the capacitive load form an RC filter that adds a pole to the loop response If the pole frequency is low enough as when driving a large capacitive load the circuit phase margin is degraded and oscillation may occur The MAX498 MAX499 drive capacitive loads up to 100pF without sustained oscillation although some peaking may occur Figures 3a and 3b When driving
10. 2 CHANNEL 3 CONTROL LOGIC Figure 2 Block Diagram Total Noise The MAX498 MAX499 s low 2 6pA VHz input current noise and 7 8nV Hz voltage noise provide for lower total noise compared to typical current mode feedback amplifiers which usually have significantly higher input current noise The input current noise multiplied by the feedback resistor is the dominant noise source of cur rent mode feedback amplifiers Differential Gain and Phase Errors Differential gain and phase errors are critical specifica tions for a buffer in composite NTSC PAL SECAM video applications because these errors correspond directly to color changes in the displayed picture of composite video systems The MAX498 MAX499 s low differential gain and phase errors 0 03 0 06 make them ideal in broadcast quality composite video applications MAKLA Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers OK DY ORM BR OD o Figure 3a Small Signal Gain vs Frequency and Load Capacitor RL 1002 Riso 0Q TIME 10ns div Figure 4a Large Signal Pulse Response with CL 100pF and Riso 5 12 Coaxial Cable Drivers High speed performance excellent output current capability and an internally fixed gain of 2 make the MAX498 MAX499 ideal for driving back terminated 50Q or 75Q coaxial cables to 2 5V In a
11. 2pF typical can be driven by a single output However peaking will occur as inputs are added Figure 3 which reduces the 0 1dB bandwidth 12 DISTORTION dBc Figure 6 Total Harmonic Distortion Audio vs Frequency Digital Interface The MAX498 MAX499 multiplexer architecture ensures that no input channels are ever connected together Select a channel by changing A0 s state AO 0 for channel A and AO 1 for channel B and pulsing CS low see Tables 1a and 1b Figure 7 shows the logic timing diagram When the enable input EN is driven to a TTL low state it enables the MAX498 MAX499 amplifier outputs When EN is driven high it disables the amplifier outputs When disabled the MAX498 MAX499 exhibit a 1 2kQ dis abled output resistance due to their internal feedback resistors LE determines whether EN is latched by CS or operates independently When the latch enable input LE is con nected to V CS becomes the latch control for the EN input register If CS is low both the EN and AO latches are transparent once CS returns high both AO and EN are latched When LE is connected to ground the EN latch is trans parent and independent of CS This allows all MAX498 MAX499 devices to be shut down simultane ously regardless of CS s input state Simply connect LE to ground and connect all EN inputs together Figure 8a Har
12. NT 813 MAXIM MAX498 Package Information INCHES MILLIMETERS MIN MAX MIN MAX DIM 0 101mm 0 004in z lo mlo w 2 gt INCHES MIN MAX MILLIMETERS MIN MAX DIM PINS Wide SO SMALL OUTLINE PACKAGE 0 300 in Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time 16 Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 1996 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products
13. SOUT SANs a 0 3V to Vcc 0 3V TENATA 4V deda Continuous Continuous Power Dissipation TA 70 C 24 Pin SO derate 11 76mW C above 70 C 941mW 28 Pin SO derate 12 5mW C above 70 C Operating Temperature Range Storage Temperature Range Lead Temperature soldering 10sec Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability DC ELECTRICAL CHARACTERISTICS Voc 5V Vee 5V VIN__ OV RL 1500 LE EN CS OV Ta 0 C to 70 C unless otherwise noted Typical values are at Ta 25 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS nput Voltage Range VIN 1 25 1 70 V RL 1502 1 25V lt VIN lt 1 25V 1 985 2 030 Voltage Gain Ay V V RL 750 1 0V lt VIN lt 1 0V 1 965 2 030 nput Offset Voltage Vos 2 9 mV nput Offset Voltage Drift TCVos 50 uV C nput Bias Current IB 1 7 pA nput Resistance RIN 1 25V lt VIN lt 1 25V 200 700 kQ nput Capacitance CIN Channel on or off 2 pF Output Short Circuit Current lout sc 3 5V l
14. WARES BARRA BPS Amit SERU gt d a Ww 1 MAXIM E PALA Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers General Description Features Tne MAX498 MAX499 are high speed quad triple sin High Speed gle pole double throw video switches with on board 250MHz Small Signal 3dB Bandwidth closed loop buffer amplifiers The buffer amplifiers fea ture 6dB gain AvcL 2V V 250MHz 3dB band width 7OMHz 0 1dB gain flatness and 1250V us slew rate Fast switching time 3ns and fast settling time 12ns for a 4V step make these devices excellent choices for a wide variety of video applications The low differential gain phase errors 0 03 0 06 and wide bandwidth make them ideal for both composite video and RGB applications The amplifiers are capable of delivering 2 5V into back terminated 509 or 75Q cables and they deliver 2V to a 75Q load allowing multiple cables to be driven from a single output For implementation of large switch arrays a low power Three State Output Allows Large Switch Arrays disable mode places the amplifier outputs in a high impedance state Channel selection and output Directly Drives 50 or 759 Back Terminated enable disable are controlled by four TTL CMOS Cables compatible logic inputs Each video input is isolated by an AC ground pin which minimizes channel to channel capacitance and reduces crosstalk to 90dB at 10MHz
15. d wire LE to V or ground rather than driving LE with a gate to prevent crosstalk from the digital inputs to INOA MAKLA Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Another option for output disable is to connect LE to V parallel the outputs of several MAX498 MAX499s and use EN to individually disable all devices but the one in use Figure 8b When the outputs are disabled off isolation from the analog inputs to the amplifier outputs is typically 81dB at 10MHz Grounding and Layout The MAX498 MAX499 bandwidths are in the RF fre quency range Depending on the size of the PC board used and the frequency of operation it may be neces sary to use Micro strip or Stripline techniques To realize the full AC performance of these high speed buffers pay careful attention to power supply bypassing and board layout The PC board should have at least two layers wire wrap boards are too inductive and bread boards are too capacitive with one side a signal layer and the other a large low impedance ground plane With multilayer boards locate the ground plane on the layer that is not dedicated to a specific signal trace The ground plane should be as free from voids as possible Connect all ground pins to the ground plane Connect both positive power supply pins together and bypass with a 0 10uF ceramic capacitor at each power supply pin as close to the device as possible Repeat for the negative power s
16. ded through a 502 resistor Adjacent channel driven to a 2Vp p output with a 10MHz sine wave Same as Note 2 except all channels but the test channel are driven to a 2Vp p output with a 10MHz sine wave Figure 9 Test channel input connected to a 2Vp p sine wave at 10MHz The test channel s output is measured with the outputs Input test signal is a 3 58MHz sine wave of 40IRE amplitude superimposed on a OIRE to 100IRE linear ramp Figure 10 66VXVW S6VXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Typical Operating Characteristics Voc 5V VEE 5V RL 100Q TA 25 C unless otherwise noted
17. dently of CS s state 28 INOA Signal Input 0 Channel A MAKIM 7 66PXVWWB86PXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers MAXIM MAX498 m EIGHT IN FOUR OUT VIDEO MUX AMP NOTE ALL RESISTORS ARE 502 OR 75Q Figure 1a MAX498 Typical Application Circuit 8 MAXIM Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers MAXIMA MAX499 SIX IN THREE OUT VIDEO MUX AMP NOTE ALL RESISTORS ARE 50 OR 759 Figure 1b MAX499 Typical Application Circuit MAKIM 9 66PXVWWB86PXVIN MAX498 MAX499 Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers Detailed Description The MAX498 MAX499 are quad triple video switches with high speed closed loop voltage feedback ampli fiers set to a 2V V gain Figure 1 shows typical applica tion circuits The amplifiers use a unique two stage voltage feedback architecture that combines the bene fits of conventional voltage feedback and current feedback topologies to achieve wide bandwidths and high slew rates while maintaining precision Figure 2 is a simplified block diagram of the MAX498 MAX499 All four amplifier switch blocks are identical to that shown for Ch_0 A common control logic block accepts external logic inputs AO EN CS and LE
18. t OUT_ lt 3 5V Note 1 120 mA Output Current lout 2 0V lt VouT_ lt 2 0V RL 75Q 27 40 mA On Output Resistance Rout 0 15 Q On Output Impedance f 10MHz 3 0 Q Off Output Resistance 2 50V lt VOUT lt 2 50V 1 0 1 2 kQ Operating Supply Voltage Range 4 50 5 50 V Positive Power Supply Rejection PSR 4 50V lt Vcc lt 5 50V Vee 5 0V 55 72 dB gate Pawel Supply PSR 5 50V lt Ver lt 4 5V Vcc 5 0V 55 72 dB Logic Low Voltage VINLL 0 8 V Logic High Voltage VINLH 2 V Logic Input Current INL OV lt VINL lt Voc 10 130 pA MAX498 40 52 z ENSY MAX499 31 41 Positive Supply Current Icc n MAX498 TI 17 mA MAX499 11 14 MAX498 38 50 Ens MAX499 29 39 Negative Supply Current IEE MAX498 T 15 mA MAX499 9 12 Note 1 Limited by package power dissipation 2 MAXI Voc 5V VEE 5V Vin OV RL 1000 LE EN CS OV Ta 25 C unless otherwise noted Quad Triple SPDT RGB Switches with 250MHz Video Buffer Amplifiers AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Small Signal 3dB Bandwidth BW 3dB VIN lt 100mVp p 250 MHz 0 1dB Gain Flatness VIN lt 100mVp p 70 MHz Full Power 3dB Bandwidth FPBW Vout 2V 135 MHz Slew Rate SR VouT 4V step 1250 V us Settling Time ts 0 1 VOUT 4V step 12 ns Input Voltage Noise Density f 100kHz 7 8 nV VHz Input Current Noise Density f 100kHz 2 6 pANHz Total Harmonic
19. to 5V Vcc pins are internally connected 7 22 6 18 Voc Connect both pins externally to 5V to minimize supply impedance Bypass each pin to ground with a 0 1uF ceramic capacitor 8 INOB Signal Input 0 Channel B Negative Power Supply Voltage Connect VEE to 5V VEE pins are internally connected 9 21 7 17 VEE Connect both pins to 5V externally to minimize supply impedance Bypass each pin to ground with a 0 1uF ceramic capacitor 10 8 IN1B Signal Input 1 Channel B 12 10 IN2B Signal Input 2 Channel B 14 12 IN3B Signal Input 3 Channel B 15 17 13 15 N C No Connect Not internally connected connect to GND 16 14 OUT3 Output 3 18 16 OUT2 Output 2 20 19 OUT1 Output 1 23 OUTO Output 0 Chip Select Input When CS is low the AO and EN latches are transparent The data present at AO 24 20 CS is latched when CS goes high LEs status determines whether EN is latched along with AO or if the EN latch remains transparent independently of CS Address Input AO 0 selects channel A and AO 1 selects channel B if CS is low AO is 25 21 AO E latched on CS s low to high transition Output Buffer Enable Input EN 0 enables the output buffer amplifiers and EN 1 disables 26 22 EN the output buffers if CS is low EN is latched during CS s low to high transition if LE is high EN is not latched if LE is low 27 23 LE Latch Enable Input With LE 1 EN is latched along with AO when CS goes high When LE 0 the EN latch is transparent indepen
20. upply pins The capacitor lead lengths should be as short as possible to minimize lead inductance surface mount chip capacitors are ideal A large value 10uF or greater tantalum or electrolytic bypass capacitor on each supply may be required for high current loads The location of this capacitor is not Critical The MAX498 MAX499 s analog input pins are isolated with ground pins to minimize parasitic coupling which can degrade crosstalk and or amplifier stability Keep signal paths as short as possible to minimize inductance Ensure that all input channel traces are the same length to main tain the phase relationship between the four channels To further reduce crosstalk connect the coaxial cable shield to the ground side of the 75Q terminating resistor at the ground plane and terminate all unused inputs to ground and outputs with a 100Q or 1502 resistor to ground MAXIM Table 1a Amplifier and Channel Selection with LE V CS EN A0 FUNCTION 0 0 0 Enables amplifier outputs Selects channel A Enables amplifier outputs Selects 0 0 1 channel B 0 1 Disables amplifiers Outputs high Z 1 X Latches AO EN Outputs unchanged Table 1b Amplifier and Channel Selection with LE GND CE EN AO FUNCTION 0 0 0 Enables amplifier outputs Selects channel A Enables amplifier outputs Latches AO 1 0 x to output A or B according to A s state at CS s last edge X 1 X
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MAXIM MAX498/MAX499 Manual